/*
 * Copyright (c) 2017 Linaro Limited
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <st/stm32f407.dtsi>

/ {
	soc {
		uart7: serial@40007800 {
			compatible = "st,stm32-uart";
			reg = <0x40007800 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
			interrupts = <82 0>;
			status = "disabled";
			label = "UART_7";
		};

		uart8: serial@40007c00 {
			compatible = "st,stm32-uart";
			reg = <0x40007c00 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
			interrupts = <83 0>;
			status = "disabled";
			label = "UART_8";
		};

		spi4: spi@40013400 {
			compatible = "st,stm32-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40013400 0x400>;
			interrupts = <84 5>;
			status = "disabled";
			label = "SPI_4";
		};

		/* spi5 is present on all STM32F429XX SoCs except
		 * STM32F429vX SoCs. Delete node in stm32f429vX.dtsi.
		 */
		 spi5: spi@40015000 {
			compatible = "st,stm32-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40015000 0x400>;
			interrupts = <85 5>;
			status = "disabled";
			label = "SPI_5";
		};

		/* spi6 is present on all STM32F429XX SoCs except
		 * STM32F429vX SoCs. Delete node in stm32f429vX.dtsi.
		 */
		spi6: spi@40015400 {
			compatible = "st,stm32-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40015400 0x400>;
			interrupts = <86 5>;
			status = "disabled";
			label = "SPI_6";
		};
	};
};