/*
 * Copyright (c) 2017-2019 Intel Corporation.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/intel-ioapic.h>

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "apollo_lake";
			reg = <0>;
		};

		intc: ioapic@fec00000  {
			compatible = "intel,ioapic";
			reg = <0xfec00000 0x100000>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};
	};

	flash0: flash@100000{
		compatible = "soc-nv-flash";
		reg = <0x00100000 DT_FLASH_SIZE>;
	};

	sram0: memory@400000 {
		device_type = "memory";
		compatible = "mmio-sram";
		reg = <0x00400000 DT_SRAM_SIZE>;
	};


	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges;

		gpio: gpio@d0c50000 {
			compatible = "intel,apl-gpio";
			reg = <0xd0c50000 0x1000>,
			      <0xd0c40000 0x1000>,
			      <0xd0c70000 0x1000>,
			      <0xd0c00000 0x1000>;
			label = "APL_GPIO";

			gpio-controller ;
			#gpio-cells = <2>;

			status = "disabled";
		};
	};

	sharedirq0: sharedirq0 {
		compatible = "shared-irq";
		label = "APL_GPIO_IRQ";
		interrupts = <14 IRQ_TYPE_LEVEL_LOW 3>;
		interrupt-parent = <&intc>;

		status = "ok";
	};
};