/*
 * Copyright (c) 2017 Linaro Limited
 * Copyright (c) 2019 Centaur Analytics, Inc
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <arm/armv7-m.dtsi>
#include <zephyr/dt-bindings/clock/stm32f1_clock.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/pwm/pwm.h>
#include <zephyr/dt-bindings/pwm/stm32_pwm.h>
#include <zephyr/dt-bindings/dma/stm32_dma.h>
#include <zephyr/dt-bindings/adc/stm32f1_adc.h>
#include <zephyr/dt-bindings/reset/stm32f0_1_3_reset.h>
#include <zephyr/dt-bindings/adc/adc.h>
#include <freq.h>

/ {
	chosen {
		zephyr,flash-controller = &flash;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-m3";
			reg = <0>;
		};
	};

	sram0: memory@20000000 {
		compatible = "mmio-sram";
	};

	clocks {
		clk_hse: clk-hse {
			#clock-cells = <0>;
			compatible = "st,stm32-hse-clock";
			status = "disabled";
		};

		clk_hsi: clk-hsi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <DT_FREQ_M(8)>;
			status = "disabled";
		};

		clk_lse: clk-lse {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
			status = "disabled";
		};

		clk_lsi: clk-lsi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <DT_FREQ_K(40)>;
			status = "disabled";
		};

		pll: pll {
			#clock-cells = <0>;
			compatible = "st,stm32f1-pll-clock";
			status = "disabled";
		};
	};

	soc {

		flash: flash-controller@40022000 {
			compatible = "st,stm32-flash-controller", "st,stm32f1-flash-controller";
			reg = <0x40022000 0x400>;
			interrupts = <3 0>;
			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>;

			#address-cells = <1>;
			#size-cells = <1>;

			flash0: flash@8000000 {
				compatible = "st,stm32-nv-flash", "soc-nv-flash";

				write-block-size = <2>;
				/* maximum erase time for a 2K sector */
				max-erase-time = <40>;
			};
		};

		rcc: rcc@40021000 {
			compatible = "st,stm32-rcc";
			#clock-cells = <2>;
			reg = <0x40021000 0x400>;

			rctl: reset-controller {
				compatible = "st,stm32-rcc-rctl";
				#reset-cells = <1>;
			};
		};

		exti: interrupt-controller@40010400 {
			compatible = "st,stm32-exti";
			interrupt-controller;
			#interrupt-cells = <1>;
			#address-cells = <1>;
			reg = <0x40010400 0x400>;
			num-lines = <16>;
			interrupts = <6 0>, <7 0>, <8 0>, <9 0>,
				     <10 0>, <23 0>, <40 0>;
			interrupt-names = "line0", "line1", "line2", "line3",
					  "line4", "line5-9", "line10-15";
			line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
				      <4 1>, <5 5>, <10 6>;
		};

		pinctrl: pin-controller@40010800 {
			compatible = "st,stm32f1-pinctrl";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x40010800 0x1C00>;

			gpioa: gpio@40010800 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x40010800 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000004>;
			};

			gpiob: gpio@40010c00 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x40010c00 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000008>;
			};

			gpioc: gpio@40011000 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x40011000 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000010>;
			};

			gpiod: gpio@40011400 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x40011400 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
			};

			gpioe: gpio@40011800 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x40011800 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000040>;
			};
		};

		usart1: serial@40013800 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40013800 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
			resets = <&rctl STM32_RESET(APB2, 14U)>;
			interrupts = <37 0>;
			status = "disabled";
		};

		usart2: serial@40004400 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40004400 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
			resets = <&rctl STM32_RESET(APB1, 17U)>;
			interrupts = <38 0>;
			status = "disabled";
		};

		usart3: serial@40004800 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40004800 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
			resets = <&rctl STM32_RESET(APB1, 18U)>;
			interrupts = <39 0>;
			status = "disabled";
		};

		i2c1: i2c@40005400 {
			compatible = "st,stm32-i2c-v1";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40005400 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
			interrupts = <31 0>, <32 0>;
			interrupt-names = "event", "error";
			status = "disabled";
		};

		i2c2: i2c@40005800 {
			compatible = "st,stm32-i2c-v1";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40005800 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
			interrupts = <33 0>, <34 0>;
			interrupt-names = "event", "error";
			status = "disabled";
		};

		spi1: spi@40013000 {
			compatible = "st,stm32-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40013000 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
			interrupts = <35 5>;
			status = "disabled";
		};

		iwdg: watchdog@40003000 {
			compatible = "st,stm32-watchdog";
			reg = <0x40003000 0x400>;
			status = "disabled";
		};

		wwdg: watchdog@40002c00 {
			compatible = "st,stm32-window-watchdog";
			reg = <0x40002C00 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
			interrupts = <0 7>;
			status = "disabled";
		};

		timers1: timers@40012c00 {
			compatible = "st,stm32-timers";
			reg = <0x40012c00 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
			resets = <&rctl STM32_RESET(APB2, 11U)>;
			interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
			interrupt-names = "brk", "up", "trgcom", "cc";
			st,prescaler = <0>;
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};
		};

		timers2: timers@40000000 {
			compatible = "st,stm32-timers";
			reg = <0x40000000 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
			resets = <&rctl STM32_RESET(APB1, 0U)>;
			interrupts = <28 0>;
			interrupt-names = "global";
			st,prescaler = <0>;
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};

			counter {
				compatible = "st,stm32-counter";
				status = "disabled";
			};
		};

		timers3: timers@40000400 {
			compatible = "st,stm32-timers";
			reg = <0x40000400 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
			resets = <&rctl STM32_RESET(APB1, 1U)>;
			interrupts = <29 0>;
			interrupt-names = "global";
			st,prescaler = <0>;
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};

			counter {
				compatible = "st,stm32-counter";
				status = "disabled";
			};
		};

		timers4: timers@40000800 {
			compatible = "st,stm32-timers";
			reg = <0x40000800 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
			resets = <&rctl STM32_RESET(APB1, 2U)>;
			interrupts = <30 0>;
			interrupt-names = "global";
			st,prescaler = <0>;
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};

			counter {
				compatible = "st,stm32-counter";
				status = "disabled";
			};
		};

		rtc: rtc@40002800 {
			compatible = "st,stm32-rtc";
			reg = <0x40002800 0x400>;
			interrupts = <41 0>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
			prescaler = <32768>;
			status = "disabled";
		};

		adc1: adc@40012400 {
			compatible = "st,stm32f1-adc", "st,stm32-adc";
			reg = <0x40012400 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>;
			interrupts = <18 0>;
			status = "disabled";
			#io-channel-cells = <1>;
			temp-channel = <16>;
			vref-channel = <17>;
			resolutions = <STM32F1_ADC_RES(12)>;
			sampling-times = <2 8 14 29 42 56 72 240>;
		};

		dma1: dma@40020000 {
			compatible = "st,stm32-dma-v2bis";
			#dma-cells = <2>;
			reg = <0x40020000 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
			interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
			status = "disabled";
		};
	};

	die_temp: dietemp {
		compatible = "st,stm32-temp";
		io-channels = <&adc1 16>;
		status = "disabled";
		avgslope = <43>;
		v25 = <1430>;
		ntc;
	};
};

&nvic {
	arm,num-irq-priority-bits = <4>;
};