/*
 * Copyright (c) 2023 STMicroelectronics
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <st/h5/stm32h5.dtsi>
#include <zephyr/dt-bindings/flash_controller/ospi.h>

/ {
	clocks {
		/* The pll scheme is similar to stm32u5 */
		pll3: pll3 {
			#clock-cells = <0>;
			compatible = "st,stm32u5-pll-clock";
			status = "disabled";
		};
	};

	soc {
		compatible = "st,stm32h562", "st,stm32h5", "simple-bus";

		pinctrl: pin-controller@42020000 {
			gpioe: gpio@42021000 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x42021000 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
			};

			gpiof: gpio@42021400 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x42021400 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>;
			};

			gpiog: gpio@42021800 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x42021800 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
			};

			gpioi: gpio@42022000 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x42022000 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000100>;
			};
		};

		uart4: serial@40004c00 {
			compatible = "st,stm32-uart";
			reg = <0x40004c00 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
			resets = <&rctl STM32_RESET(APB1L, 19U)>;
			interrupts = <61 0>;
			status = "disabled";
		};

		uart5: serial@40005000 {
			compatible = "st,stm32-uart";
			reg = <0x40005000 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
			resets = <&rctl STM32_RESET(APB1L, 20U)>;
			interrupts = <62 0>;
			status = "disabled";
		};

		uart9: serial@40008000 {
			compatible = "st,stm32-uart";
			reg = <0x40008000 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000001>;
			resets = <&rctl STM32_RESET(APB1H, 0U)>;
			interrupts = <100 0>;
			status = "disabled";
		};

		usart10: serial@40006800 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40006800 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>;
			resets = <&rctl STM32_RESET(APB1L, 26U)>;
			interrupts = <86 0>;
			status = "disabled";
		};

		uart12: serial@40008400 {
			compatible = "st,stm32-uart";
			reg = <0x40008400 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000002>;
			resets = <&rctl STM32_RESET(APB1H, 1U)>;
			interrupts = <101 0>;
			status = "disabled";
		};

		i2c3: i2c@44002800 {
			compatible = "st,stm32-i2c-v2";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x44002800 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000080>;
			interrupts = <80 0>, <81 0>;
			interrupt-names = "event", "error";
			status = "disabled";
		};

		i2c4: i2c@44002c00 {
			compatible = "st,stm32-i2c-v2";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x44002c00 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000100>;
			interrupts = <125 0>, <126 0>;
			interrupt-names = "event", "error";
			status = "disabled";
		};

		spi4: spi@40014c00 {
			compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40014c00 0x400>;
			interrupts = <82 5>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00080000>;
			status = "disabled";
		};

		spi5: spi@44002000 {
			compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x44002000 0x400>;
			interrupts = <83 5>;
			clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000020>;
			status = "disabled";
		};

		spi6: spi@40015000 {
			compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40015000 0x400>;
			interrupts = <84 5>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
			status = "disabled";
		};

		octospi1: octospi@47001400 {
			compatible = "st,stm32-ospi";
			reg = <0x47001400 0x400>;
			interrupts = <78 0>;
			clock-names = "ospix", "ospi-ker";
			clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00100000>,
				<&rcc STM32_SRC_PLL1_Q OCTOSPI1_SEL(1)>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		adc2: adc@42028100 {
			compatible = "st,stm32-adc";
			reg = <0x42028100 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000400>;
			interrupts = <69 0>;
			status = "disabled";
			vref-mv = <3300>;
			#io-channel-cells = <1>;
			resolutions = <STM32_ADC_RES(12, 0x00)
					STM32_ADC_RES(10, 0x01)
					STM32_ADC_RES(8, 0x02)
					STM32_ADC_RES(6, 0x03)>;
			sampling-times = <3 7 13 25 48 93 248 641>;
		};

		timers4: timers@40000800 {
			compatible = "st,stm32-timers";
			reg = <0x40000800 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
			resets = <&rctl STM32_RESET(APB1L, 2U)>;
			interrupts = <47 0>;
			interrupt-names = "global";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};

			counter {
				compatible = "st,stm32-counter";
				status = "disabled";
			};
		};

		timers5: timers@40000c00 {
			compatible = "st,stm32-timers";
			reg = <0x40000c00 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
			resets = <&rctl STM32_RESET(APB1L, 3U)>;
			interrupts = <48 0>;
			interrupt-names = "global";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};

			counter {
				compatible = "st,stm32-counter";
				status = "disabled";
			};
		};

		timers12: timers@40001800 {
			compatible = "st,stm32-timers";
			reg = <0x40001800 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
			resets = <&rctl STM32_RESET(APB1L, 6U)>;
			interrupts = <120 0>;
			interrupt-names = "global";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};

			counter {
				compatible = "st,stm32-counter";
				status = "disabled";
			};
		};

		timers13: timers@40001c00 {
			compatible = "st,stm32-timers";
			reg = <0x40001c00 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
			resets = <&rctl STM32_RESET(APB1L, 7U)>;
			interrupts = <121 0>;
			interrupt-names = "global";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};

			counter {
				compatible = "st,stm32-counter";
				status = "disabled";
			};
		};

		timers14: timers@40002000 {
			compatible = "st,stm32-timers";
			reg = <0x40002000 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
			resets = <&rctl STM32_RESET(APB1L, 8U)>;
			interrupts = <122 0>;
			interrupt-names = "global";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};

			counter {
				compatible = "st,stm32-counter";
				status = "disabled";
			};
		};

		aes: aes@420c0000 {
			compatible = "st,stm32-aes";
			reg = <0x420c0000 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00010000>;
			interrupts = <116 0>;
			status = "disabled";
		};

		can {
			can2: can@4000a800 {
				compatible = "st,stm32-fdcan";
				reg = <0x4000a800 0x400>, <0x4000af50 0x350>;
				reg-names = "m_can", "message_ram";
				interrupts = <109 0>, <110 0>;
				interrupt-names = "LINE_0", "LINE_1";
				/* common clock FDCAN 1 & 2 */
				clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>;
				status = "disabled";
				sjw = <1>;
				sample-point = <875>;
				sjw-data = <1>;
				sample-point-data = <875>;
			};
		};
	};
};