/* quark_se_clock_control.h - Clock controller header for Quark SE */

/*
 * Copyright (c) 2015 Intel Corporation.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_QUARK_SE_CLOCK_CONTROL_H_
#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_QUARK_SE_CLOCK_CONTROL_H_

enum quark_se_peripheral_clocks {
	QUARK_SE_PERIPH_PCLK_EN = 0,
	QUARK_SE_CCU_PERIPH_PCLK_EN,
	QUARK_SE_CCU_I2C_M0_PCLK_EN,
	QUARK_SE_CCU_I2C_M1_PCLK_EN,
	QUARK_SE_CCU_SPI_S_PCLK_EN,
	QUARK_SE_CCU_SPI_M0_PCLK_EN,
	QUARK_SE_CCU_SPI_M1_PCLK_EN,
	QUARK_SE_CCU_GPIO_INTR_PCLK_EN,
	QUARK_SE_CCU_PERIPH_GPIO_DB_PCLK_EN,
	QUARK_SE_CCU_I2S_PCLK_EN,
	QUARK_SE_CCU_WDT_PCLK_EN_SW,
	QUARK_SE_CCU_RTC_PCLK_EN_SW,
	QUARK_SE_CCU_PWM_PCLK_EN_SW,
	QUARK_SE_CCU_GPIO_PCLK_EN_SW,
	QUARK_SE_CCU_SPI_M0_PCLK_EN_SW,
	QUARK_SE_CCU_SPI_M1_PCLK_EN_SW,
	QUARK_SE_CCU_SPI_PCLK_EN_SW,
	QUARK_SE_CCU_UARTA_PCLK_EN_SW,
	QUARK_SE_CCU_UARTB_PCLK_EN_SW,
	QUARK_SE_CCU_I2C_M0_PCLK_EN_SW,
	QUARK_SE_CCU_I2C_M1_PCLK_EN_SW,
	QUARK_SE_CCU_I2S_PCLK_EN_SW,
};

enum quark_se_external_clocks {
	QUARK_SE_CCU_EXT_RTC_EN = 0,
	QUARK_SE_CCU_EXT_CLK_EN,
	QUARK_SE_CCU_EXT_CLK_DIV_EN,
};

enum quark_se_sensor_clocks {
	QUARK_SE_CCU_SENSOR_CLK_EN = 0,
	QUARK_SE_CCU_SS_I2C_M0_CLK_EN,
	QUARK_SE_CCU_SS_I2C_M1_CLK_EN,
	QUARK_SE_CCU_SS_SPI_M0_CLK_EN,
	QUARK_SE_CCU_SS_SPI_M1_CLK_EN,
	QUARK_SE_CCU_SS_GPIO_INTR_CLK_EN,
	QUARK_SE_CCU_SS_GPIO_DB_CLK_EN,
	QUARK_SE_CCU_ADC_CLK_EN,
};

#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_QUARK_SE_CLOCK_CONTROL_H_ */