/*
 * Copyright 2022-2023 NXP
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <mem.h>
#include <arm/armv8-m.dtsi>

/ {
	soc {
		sram: sram@30000000 {
			ranges = <0x20000000 0x30000000 0x130000
				  0x00000000 0x10000000 0x130000>;
		};

		peripheral: peripheral@50000000 {
			ranges = <0x0 0x50000000 0x10000000>;
		};

		flexspi: spi@134000 {
			reg = <0x50134000 0x1000>, <0x18000000 DT_SIZE_M(128)>;
		};
	};
};

#include "nxp_rw6xx_common.dtsi"