/*
 * Copyright 2022-2024 NXP
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <mem.h>
#include <arm/armv8-r.dtsi>
#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
#include <zephyr/dt-bindings/clock/nxp_s32z2_clock.h>

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-r52";
			reg = <0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-r52";
			reg = <1>;
		};

		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-r52";
			reg = <2>;
		};

		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-r52";
			reg = <3>;
		};

		cpu@4 {
			device_type = "cpu";
			compatible = "arm,cortex-r52";
			reg = <4>;
		};

		cpu@5 {
			device_type = "cpu";
			compatible = "arm,cortex-r52";
			reg = <5>;
		};

		cpu@6 {
			device_type = "cpu";
			compatible = "arm,cortex-r52";
			reg = <6>;
		};

		cpu@7 {
			device_type = "cpu";
			compatible = "arm,cortex-r52";
			reg = <7>;
		};
	};

	arch_timer: timer {
		compatible = "arm,armv8_timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
				<GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
				<GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
				<GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
		interrupt-parent = <&gic>;
	};

	/* Dummy pinctrl node, filled with pin mux options at board level */
	pinctrl: pinctrl {
		compatible = "nxp,s32ze-pinctrl";
		status = "okay";
	};

	soc {
		interrupt-parent = <&gic>;

		clock: clock-controller@40030000 {
			compatible = "nxp,s32-clock";
			reg = <0x40030000 0x10000>,
				<0x40200000 0x10000>,
				<0x40210000 0x10000>,
				<0x40220000 0x10000>,
				<0x40260000 0x10000>,
				<0x40270000 0x10000>,
				<0x40830000 0x10000>,
				<0x41030000 0x10000>,
				<0x41830000 0x10000>,
				<0x42030000 0x10000>,
				<0x42830000 0x10000>,
				<0x44030000 0x10000>,
				<0x440a0000 0x10000>;
			#clock-cells = <1>;
			status = "okay";
		};

		gic: interrupt-controller@47800000 {
			compatible = "arm,gic-v3", "arm,gic";
			reg = <0x47800000 0x10000>,
				<0x47900000 0x80000>;
			interrupt-controller;
			#interrupt-cells = <4>;
			status = "okay";
		};

		sram0: memory@31780000 {
			compatible = "mmio-sram";
			reg = <0x31780000 DT_SIZE_M(1)>;
		};

		sram1: memory@35780000 {
			compatible = "mmio-sram";
			reg = <0x35780000 DT_SIZE_M(1)>;
		};

		uart0: uart@40170000 {
			compatible = "nxp,s32-linflexd";
			reg = <0x40170000 0x1000>;
			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			status = "disabled";
		};

		uart1: uart@40180000 {
			compatible = "nxp,s32-linflexd";
			reg = <0x40180000 0x1000>;
			interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			status = "disabled";
		};

		uart2: uart@40190000 {
			compatible = "nxp,s32-linflexd";
			reg = <0x40190000 0x1000>;
			interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			status = "disabled";
		};

		uart3: uart@40970000 {
			compatible = "nxp,s32-linflexd";
			reg = <0x40970000 0x1000>;
			interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			status = "disabled";
		};

		uart4: uart@40980000 {
			compatible = "nxp,s32-linflexd";
			reg = <0x40980000 0x1000>;
			interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			status = "disabled";
		};

		uart5: uart@40990000 {
			compatible = "nxp,s32-linflexd";
			reg = <0x40990000 0x1000>;
			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			status = "disabled";
		};

		uart6: uart@42170000 {
			compatible = "nxp,s32-linflexd";
			reg = <0x42170000 0x1000>;
			interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			status = "disabled";
		};

		uart7: uart@42180000 {
			compatible = "nxp,s32-linflexd";
			reg = <0x42180000 0x1000>;
			interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			status = "disabled";
		};

		uart8: uart@42190000 {
			compatible = "nxp,s32-linflexd";
			reg = <0x42190000 0x1000>;
			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			status = "disabled";
		};

		uart9: uart@42980000 {
			compatible = "nxp,s32-linflexd";
			reg = <0x42980000 0x1000>;
			interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			status = "disabled";
		};

		uart10: uart@42990000 {
			compatible = "nxp,s32-linflexd";
			reg = <0x42990000 0x1000>;
			interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			status = "disabled";
		};

		uart11: uart@429a0000 {
			compatible = "nxp,s32-linflexd";
			reg = <0x429a0000 0x1000>;
			interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			status = "disabled";
		};

		uart12: uart@40330000 {
			compatible = "nxp,s32-linflexd";
			reg = <0x40330000 0x1000>;
			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			status = "disabled";
		};

		siul2_0: siul2@40520000 {
			reg = <0x40520000 0x10000>;
			#address-cells = <1>;
			#size-cells = <1>;

			eirq0: eirq0@40520010 {
				compatible = "nxp,s32-siul2-eirq";
				reg = <0x40520010 0x04>, <0x40520018 0x04>;
				reg-names = "disr0", "direr0";
				interrupts = <GIC_SPI 514 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
				interrupt-controller;
				#interrupt-cells = <2>;
				status = "disabled";
			};

			gpioa: gpio@40521702 {
				compatible = "nxp,s32-gpio";
				reg = <0x40521702 0x02>, <0x40520240 0x40>;
				reg-names = "pgpdo", "mscr";
				interrupt-parent = <&eirq0>;
				interrupts = <1 1>, <3 0>, <5 2>, <12 3>,
						<13 4>, <14 5>, <15 6>;
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <16>;
				status = "disabled";
			};

			gpiob: gpio@40521700 {
				compatible = "nxp,s32-gpio";
				reg = <0x40521700 0x02>, <0x40520280 0x40>;
				reg-names = "pgpdo", "mscr";
				interrupt-parent = <&eirq0>;
				interrupts = <0 7>;
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <15>;
				status = "disabled";
			};

			gpioo: gpio@40521716 {
				compatible = "nxp,s32-gpio";
				reg = <0x40521716 0x02>, <0x405204c0 0x40>;
				reg-names = "pgpdo", "mscr";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <14>;
				gpio-reserved-ranges = <0 10>;
				status = "disabled";
			};
		};

		siul2_1: siul2@40d20000 {
			reg = <0x40d20000 0x10000>;
			#address-cells = <1>;
			#size-cells = <1>;

			eirq1: eirq1@40d20010 {
				compatible = "nxp,s32-siul2-eirq";
				reg = <0x40d20010 0x04>, <0x40d20018 0x04>;
				reg-names = "disr0", "direr0";
				interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
				interrupt-controller;
				#interrupt-cells = <2>;
				status = "disabled";
			};

			gpioc: gpio@40d21700 {
				compatible = "nxp,s32-gpio";
				reg = <0x40d21700 0x02>, <0x40d20280 0x40>;
				reg-names = "pgpdo", "mscr";
				interrupt-parent = <&eirq1>;
				interrupts = <3 0>, <5 1>;
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <16>;
				gpio-reserved-ranges = <0 15>;
				status = "disabled";
			};

			gpiod: gpio@40d21706 {
				compatible = "nxp,s32-gpio";
				reg = <0x40d21706 0x02>, <0x40d202c0 0x40>;
				reg-names = "pgpdo", "mscr";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <16>;
				status = "disabled";
			};

			gpioe: gpio@40d21704 {
				compatible = "nxp,s32-gpio";
				reg = <0x40d21704 0x02>, <0x40d20300 0x40>;
				reg-names = "pgpdo", "mscr";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <16>;
				status = "disabled";
			};

			gpiof: gpio@40d2170a {
				compatible = "nxp,s32-gpio";
				reg = <0x40d2170a 0x02>, <0x40d20340 0x40>;
				reg-names = "pgpdo", "mscr";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <16>;
				status = "disabled";
			};

			gpiog: gpio@40d21708 {
				compatible = "nxp,s32-gpio";
				reg = <0x40d21708 0x02>, <0x40d20380 0x40>;
				reg-names = "pgpdo", "mscr";
				interrupt-parent = <&eirq1>;
				interrupts = <0 2>, <1 3>, <4 4>,
						<5 5>, <10 6>, <11 7>;
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <12>;
				status = "disabled";
			};
		};

		siul2_3: siul2@41d20000 {
			reg = <0x41d20000 0x10000>;
		};

		siul2_4: siul2@42520000 {
			reg = <0x42520000 0x10000>;
			#address-cells = <1>;
			#size-cells = <1>;

			eirq4: eirq4@42520010 {
				compatible = "nxp,s32-siul2-eirq";
				reg = <0x42520010 0x04>, <0x42520018 0x04>;
				reg-names = "disr0", "direr0";
				interrupts = <GIC_SPI 516 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
				interrupt-controller;
				#interrupt-cells = <2>;
				status = "disabled";
			};

			gpioh: gpio@42521708 {
				compatible = "nxp,s32-gpio";
				reg = <0x42521708 0x02>, <0x42520380 0x40>;
				reg-names = "pgpdo", "mscr";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <16>;
				gpio-reserved-ranges = <0 12>;
				status = "disabled";
			};

			gpioi: gpio@4252170e {
				compatible = "nxp,s32-gpio";
				reg = <0x4252170e 0x02>, <0x425203c0 0x40>;
				reg-names = "pgpdo", "mscr";
				interrupt-parent = <&eirq4>;
				interrupts = <11 0>, <13 1>;
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <16>;
				status = "disabled";
			};

			gpioj: gpio@4252170c {
				compatible = "nxp,s32-gpio";
				reg = <0x4252170c 0x02>, <0x42520400 0x40>;
				reg-names = "pgpdo", "mscr";
				interrupt-parent = <&eirq4>;
				interrupts = <12 2>;
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <16>;
				status = "disabled";
			};

			gpiok: gpio@42521712 {
				compatible = "nxp,s32-gpio";
				reg = <0x42521712 0x02>, <0x42520440 0x40>;
				reg-names = "pgpdo", "mscr";
				interrupt-parent = <&eirq4>;
				interrupts = <4 3>, <6 4>, <9 5>,
						<11 6>, <13 7>;
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <16>;
				status = "disabled";
			};

			gpiol: gpio@42521710 {
				compatible = "nxp,s32-gpio";
				reg = <0x42521710 0x02>, <0x42520480 0x40>;
				reg-names = "disr0", "direr0";
				reg-names = "pgpdo", "mscr";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <2>;
				status = "disabled";
			};
		};

		siul2_5: siul2@42d20000 {
			reg = <0x42d20000 0x10000>;
			#address-cells = <1>;
			#size-cells = <1>;

			eirq5: eirq5@42d20010 {
				compatible = "nxp,s32-siul2-eirq";
				reg = <0x42d20010 0x04>, <0x42d20018 0x04>;
				reg-names = "disr0", "direr0";
				interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
				interrupt-controller;
				#interrupt-cells = <2>;
				status = "disabled";
			};

			gpiom: gpio@42d21710 {
				compatible = "nxp,s32-gpio";
				reg = <0x42d21710 0x02>, <0x42d20480 0x40>;
				reg-names = "pgpdo", "mscr";
				interrupt-parent = <&eirq5>;
				interrupts = <1 0>, <3 1>, <5 2>, <7 3>;
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <16>;
				gpio-reserved-ranges = <0 2>;
				status = "disabled";
			};

			gpion: gpio@42d21716 {
				compatible = "nxp,s32-gpio";
				reg = <0x42d21716 0x02>, <0x42d204c0 0x40>;
				reg-names = "pgpdo", "mscr";
				interrupt-parent = <&eirq5>;
				interrupts = <0 4>, <2 5>, <5 6>, <6 7>;
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <10>;
				status = "disabled";
			};
		};

		spi0: spi@40130000 {
			compatible = "nxp,s32-spi";
			reg = <0x40130000 0x10000>;
			interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			clocks = <&clock NXP_S32_SPI0_CLK>;
			num-cs = <5>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi1: spi@40140000 {
			compatible = "nxp,s32-spi";
			reg = <0x40140000 0x10000>;
			interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			clocks = <&clock NXP_S32_SPI1_CLK>;
			num-cs = <5>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi2: spi@40930000 {
			compatible = "nxp,s32-spi";
			reg = <0x40930000 0x10000>;
			interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			clocks = <&clock NXP_S32_SPI2_CLK>;
			num-cs = <5>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi3: spi@40940000 {
			compatible = "nxp,s32-spi";
			reg = <0x40940000 0x10000>;
			interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			clocks = <&clock NXP_S32_SPI3_CLK>;
			num-cs = <5>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi4: spi@40950000 {
			compatible = "nxp,s32-spi";
			reg = <0x40950000 0x10000>;
			interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			clocks = <&clock NXP_S32_SPI4_CLK>;
			num-cs = <5>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi5: spi@42130000 {
			compatible = "nxp,s32-spi";
			reg = <0x42130000 0x10000>;
			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			clocks = <&clock NXP_S32_SPI5_CLK>;
			num-cs = <5>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi6: spi@42140000 {
			compatible = "nxp,s32-spi";
			reg = <0x42140000 0x10000>;
			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			clocks = <&clock NXP_S32_SPI6_CLK>;
			num-cs = <5>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi7: spi@42150000 {
			compatible = "nxp,s32-spi";
			reg = <0x42150000 0x10000>;
			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			clocks = <&clock NXP_S32_SPI7_CLK>;
			num-cs = <5>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi8: spi@42930000 {
			compatible = "nxp,s32-spi";
			reg = <0x42930000 0x10000>;
			interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			clocks = <&clock NXP_S32_SPI8_CLK>;
			num-cs = <5>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi9: spi@42940000 {
			compatible = "nxp,s32-spi";
			reg = <0x42940000 0x10000>;
			interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			clocks = <&clock NXP_S32_SPI9_CLK>;
			num-cs = <5>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		mru0: mbox@76070000 {
			compatible = "nxp,s32-mru";
			reg = <0x76070000 0x10000>;
			interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			#mbox-cells = <1>;
			status = "disabled";
		};

		mru1: mbox@76090000 {
			compatible = "nxp,s32-mru";
			reg = <0x76090000 0x10000>;
			interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			#mbox-cells = <1>;
			status = "disabled";
		};

		mru2: mbox@76270000 {
			compatible = "nxp,s32-mru";
			reg = <0x76270000 0x10000>;
			interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			#mbox-cells = <1>;
			status = "disabled";
		};

		mru3: mbox@76290000 {
			compatible = "nxp,s32-mru";
			reg = <0x76290000 0x10000>;
			interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			#mbox-cells = <1>;
			status = "disabled";
		};

		mru4: mbox@76870000 {
			compatible = "nxp,s32-mru";
			reg = <0x76870000 0x10000>;
			interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			#mbox-cells = <1>;
			status = "disabled";
		};

		mru5: mbox@76890000 {
			compatible = "nxp,s32-mru";
			reg = <0x76890000 0x10000>;
			interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			#mbox-cells = <1>;
			status = "disabled";
		};

		mru6: mbox@76a70000 {
			compatible = "nxp,s32-mru";
			reg = <0x76a70000 0x10000>;
			interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			#mbox-cells = <1>;
			status = "disabled";
		};

		mru7: mbox@76a90000 {
			compatible = "nxp,s32-mru";
			reg = <0x76a90000 0x10000>;
			interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			#mbox-cells = <1>;
			status = "disabled";
		};

		netc: ethernet@74000000 {
			reg = <0x74000000 0x1000000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			emdio: mdio@74b60000 {
				compatible = "nxp,s32-netc-emdio";
				reg = <0x74b60000 0x1c44>;
				status = "disabled";
				#address-cells = <1>;
				#size-cells = <0>;
			};

			enetc_psi0: ethernet@74b00000 {
				compatible = "nxp,s32-netc-psi";
				reg = <0x74b00000 0x10000>;
				status = "disabled";
			};

			enetc_vsi1: ethernet@74bc0000 {
				compatible = "nxp,s32-netc-vsi";
				reg = <0x74bc0000 0x10000>;
				status = "disabled";
			};

			enetc_vsi2: ethernet@74bd0000 {
				compatible = "nxp,s32-netc-vsi";
				reg = <0x74bd0000 0x10000>;
				status = "disabled";
			};

			enetc_vsi3: ethernet@74be0000 {
				compatible = "nxp,s32-netc-vsi";
				reg = <0x74be0000 0x10000>;
				status = "disabled";
			};

			enetc_vsi4: ethernet@74bf0000 {
				compatible = "nxp,s32-netc-vsi";
				reg = <0x74bf0000 0x10000>;
				status = "disabled";
			};

			enetc_vsi5: ethernet@74c00000 {
				compatible = "nxp,s32-netc-vsi";
				reg = <0x74c00000 0x10000>;
				status = "disabled";
			};

			enetc_vsi6: ethernet@74c10000 {
				compatible = "nxp,s32-netc-vsi";
				reg = <0x74c10000 0x10000>;
				status = "disabled";
			};

			enetc_vsi7: ethernet@74c20000 {
				compatible = "nxp,s32-netc-vsi";
				reg = <0x74c20000 0x10000>;
				status = "disabled";
			};
		};

		can0: can@4741b000 {
			compatible = "nxp,s32-canxl";
			reg = <0x4741b000 0x1000>,
				<0x47423000 0x1000>,
				<0x47425000 0x1000>;
			reg-names = "sic", "rx_fifo", "rx_fifo_ctrl";
			status = "disabled";
			interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
					<GIC_SPI 225 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			interrupt-names = "rx_tx", "error";
			clocks = <&clock NXP_S32_P5_CANXL_PE_CLK>;
		};

		can1: can@4751b000 {
			compatible = "nxp,s32-canxl";
			reg = <0x4751b000 0x1000>,
				<0x47523000 0x1000>,
				<0x47525000 0x1000>;
			reg-names = "sic", "rx_fifo", "rx_fifo_ctrl";
			status = "disabled";
			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
					<GIC_SPI 227 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			interrupt-names = "rx_tx", "error";
			clocks = <&clock NXP_S32_P5_CANXL_PE_CLK>;
		};
	};
};