)]}'
{
  "commit": "dadf9e7a81de66e2578fe85c2d66cc3d284225f4",
  "tree": "81af318d9ffcc347e91e2fe9dba60e5f21062890",
  "parents": [
    "e3f2fa4f8966dcbd6a57b37d340592d6e2614bd3"
  ],
  "author": {
    "name": "Rajavardhan Gundi",
    "email": "rajavardhan.gundi@intel.com",
    "time": "Thu Oct 12 18:32:23 2017 +0530"
  },
  "committer": {
    "name": "Anas Nashif",
    "email": "nashif@linux.intel.com",
    "time": "Tue May 01 16:46:41 2018 -0400"
  },
  "message": "xtensa: intel_s1000: implement interrupt mechanism\n\nintel_s1000 has multiple levels of interrupts consisting of core, CAVS\nLogic and designware interrupt controller. This patchset modifies\nthe regular gen_isr mechanism to support these multiple levels.\n\nChange-Id: I0450666d4e601dfbc8cadc9c9d8100afb61a214c\nSigned-off-by: Rajavardhan Gundi \u003crajavardhan.gundi@intel.com\u003e\nSigned-off-by: Anas Nashif \u003canas.nashif@intel.com\u003e\n",
  "tree_diff": [
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      "new_path": "arch/xtensa/soc/intel_s1000/CMakeLists.txt"
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}