tree 81af318d9ffcc347e91e2fe9dba60e5f21062890
parent e3f2fa4f8966dcbd6a57b37d340592d6e2614bd3
author Rajavardhan Gundi <rajavardhan.gundi@intel.com> 1507813343 +0530
committer Anas Nashif <nashif@linux.intel.com> 1525207601 -0400

xtensa: intel_s1000: implement interrupt mechanism

intel_s1000 has multiple levels of interrupts consisting of core, CAVS
Logic and designware interrupt controller. This patchset modifies
the regular gen_isr mechanism to support these multiple levels.

Change-Id: I0450666d4e601dfbc8cadc9c9d8100afb61a214c
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>