)]}'
{
  "commit": "dca9c2b165b92e90d38a5002ae7e6ad013daf04d",
  "tree": "f0beb3198e169743298f79c79d8d37aa7b8ee0ce",
  "parents": [
    "a0a124c5da626ebb730cf509085aa321dc78fa9c"
  ],
  "author": {
    "name": "Francois Ramu",
    "email": "francois.ramu@st.com",
    "time": "Thu Sep 15 14:25:16 2022 +0200"
  },
  "committer": {
    "name": "Fabio Baltieri",
    "email": "fabio.baltieri@gmail.com",
    "time": "Fri Sep 23 10:47:23 2022 +0000"
  },
  "message": "drivers: adc: stm32f3 adc driver set common clock to HCLK\n\nSet the synchronous clock mode to HCLK/1 (DIV1) or HCLK/2 (DIV2)\nBoth are valid common clock setting values.\nThe HCLK/1 (DIV1) is possible only if the ahb-prescaler \u003d \u003c1\u003e\nin the RCC_CFGR (see DTS).\n\nSigned-off-by: Francois Ramu \u003cfrancois.ramu@st.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "8fa5a312a34a821869823c877cc045cf5557ecd7",
      "old_mode": 33188,
      "old_path": "drivers/adc/adc_stm32.c",
      "new_id": "3cdb80afe3d94f6cffc3540ebd0ea240d55843bc",
      "new_mode": 33188,
      "new_path": "drivers/adc/adc_stm32.c"
    }
  ]
}