tree f0beb3198e169743298f79c79d8d37aa7b8ee0ce
parent a0a124c5da626ebb730cf509085aa321dc78fa9c
author Francois Ramu <francois.ramu@st.com> 1663244716 +0200
committer Fabio Baltieri <fabio.baltieri@gmail.com> 1663930043 +0000

drivers: adc: stm32f3 adc driver set common clock to HCLK

Set the synchronous clock mode to HCLK/1 (DIV1) or HCLK/2 (DIV2)
Both are valid common clock setting values.
The HCLK/1 (DIV1) is possible only if the ahb-prescaler = <1>
in the RCC_CFGR (see DTS).

Signed-off-by: Francois Ramu <francois.ramu@st.com>