# Copyright 2024 NXP
# SPDX-License-Identifier: Apache-2.0

config SOC_SERIES_MCXNX4X
	select HAS_MCUX
	select HAS_MCUX_FLEXCOMM
	select CPU_CORTEX_M_HAS_SYSTICK
	select CPU_CORTEX_M_HAS_DWT
	select PLATFORM_SPECIFIC_INIT

config SOC_MCXN947_CPU0
	select CPU_CORTEX_M33
	select CPU_HAS_ARM_SAU
	select CPU_HAS_ARM_MPU
	select CPU_HAS_FPU
	select ARMV8_M_DSP
	select ARM_TRUSTZONE_M
	select HAS_MCUX_CACHE

if SOC_SERIES_MCXNX4X

config SECOND_CORE_MCUX
	bool "MCXN94X's second core"
	depends on HAS_MCUX
	help
	  Indicates the second core will be enabled, and the part will run
	  in dual core mode.

config FLASH_DISABLE_CACHE64
	bool "Disable the CACHE64 cache for FlexSPI flash accesses"
	help
	  Disable cache64 cache.

config MCUX_CORE_SUFFIX
	default "_cm33_core0" if SOC_MCXN947_CPU0
	default "_cm33_core1" if SOC_MCXN947_CPU1

DT_CHOSEN_Z_FLASH := zephyr,flash
DT_COMPAT_FLEXSPI := nxp,imx-flexspi

DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH))
DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE))

DT_FLASH_PARENT_IS_FLEXSPI := $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI))
DT_FLASH_HAS_SIZE_PROP := $(dt_node_has_prop,$(DT_CHOSEN_FLASH_NODE),size)

config FLASH_BASE_ADDRESS
	default $(dt_node_reg_addr_hex,$(DT_CHOSEN_FLASH_PARENT),1) \
		if $(DT_FLASH_PARENT_IS_FLEXSPI)

config FLASH_SIZE
	default $(dt_node_int_prop_int,$(DT_CHOSEN_FLASH_NODE),size,Kb) \
		if $(DT_FLASH_HAS_SIZE_PROP)

config FLASH_MCUX_FLEXSPI_XIP
	bool
	default $(DT_FLASH_PARENT_IS_FLEXSPI)
	select XIP
	help
	  Allows for the soc to safely initialize the clocks for the
	  FlexSpi when planning to execute code in FlexSpi Memory.

endif # SOC_SERIES_MCXNX4X