CONFIG_ZTEST=y

CONFIG_ASSERT=y
CONFIG_ASSERT_LEVEL=2
CONFIG_ASSERT_VERBOSE=y


CONFIG_BT=y
CONFIG_BT_HCI=y
CONFIG_BT_CTLR=y
CONFIG_BT_LL_SW_SPLIT=y

CONFIG_BT_BUF_ACL_TX_SIZE=251
CONFIG_BT_BUF_ACL_RX_SIZE=251

CONFIG_BT_LLL_VENDOR_NORDIC=y

CONFIG_BT_CENTRAL=y
CONFIG_BT_PERIPHERAL=y
CONFIG_BT_CTLR_PERIPHERAL_ISO=y
CONFIG_BT_CTLR_CENTRAL_ISO=y

CONFIG_BT_ASSERT=y
CONFIG_BT_CTLR_ASSERT_HANDLER=y

CONFIG_BT_CTLR_PER_INIT_FEAT_XCHG=y
CONFIG_BT_CTLR_SCA_UPDATE=y
CONFIG_BT_SCA_UPDATE=y

CONFIG_BT_PHY_UPDATE=y
CONFIG_BT_CTLR_PHY_2M=y
CONFIG_BT_CTLR_PHY_CODED=y

CONFIG_BT_DATA_LEN_UPDATE=y
CONFIG_BT_CTLR_DATA_LENGTH_MAX=251

CONFIG_BT_CTLR_DF=y
CONFIG_BT_CTLR_DF_CTE_TX=y
CONFIG_BT_CTLR_DF_CTE_RX_SAMPLE_1US=y
CONFIG_BT_CTLR_DF_ANT_SWITCH_1US=y
CONFIG_BT_CTLR_DF_CONN_CTE_RX=y
CONFIG_BT_CTLR_DF_CONN_CTE_TX=y
CONFIG_BT_CTLR_DF_CONN_CTE_REQ=y
CONFIG_BT_CTLR_DF_CONN_CTE_RSP=y
CONFIG_BT_CTLR_DF_ANT_SWITCH_TX=y
CONFIG_BT_CTLR_DF_CTE_RX=y