tree 964462fd07447fee41d41575456242d1ae343ecd
parent ae350a9c773ab527eb1fa93eeb45bef7beca9a5a
author Tyler Ng <tkng@rivosinc.com> 1682456002 -0700
committer Anas Nashif <anas.nashif@intel.com> 1685108725 -0400

soc: riscv: riscv-privilege: opentitan: Fix PLIC interrupts

1. Fixes the number of interrupts in OpenTitan by default. This should
   be 32 + 185 = 217 IRQs, as there are 185 configurable registers,
   including interrupt 0.

2. Adds 2ND_LVL_INTR_00_OFFSET Kconfig, which is needed to generate a
   PLIC interrupt on IRQ 11.

Signed-off-by: Tyler Ng <tkng@rivosinc.com>