/*
 * Copyright (c) 2017 Linaro Limited
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <st/stm32f1-pinctrl.dtsi>
#include <arm/armv7-m.dtsi>
#include <st/mem.h>
#include <dt-bindings/clock/stm32_clock.h>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-m3";
			reg = <0>;
		};
	};

	flash0: flash@8000000 {
		compatible = "soc-nv-flash";
		label = "FLASH_STM32";
		reg = <0x08000000 DT_FLASH_SIZE>;
	};

	sram0: memory@20000000 {
		device_type = "memory";
		compatible = "mmio-sram";
		reg = <0x20000000 DT_SRAM_SIZE>;
	};

	soc {
		rcc: rcc@40021000 {
			compatible = "st,stm32-rcc";
			clocks-controller;
			#clock-cells = <2>;
			reg = <0x40021000 0x400>;
			label = "STM32_CLK_RCC";
		};

		pinctrl: pin-controller@40010800 {
			compatible = "st,stm32-pinmux";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x40010800 0x1C00>;

			gpioa: gpio@40010800 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x40010800 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000005>;
				label = "GPIOA";
			};

			gpiob: gpio@40010c00 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x40010c00 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000009>;
				label = "GPIOB";
			};

			gpioc: gpio@40011000 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x40011000 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000011>;
				label = "GPIOC";
			};

			gpiod: gpio@40011400 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x40011400 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000021>;
				label = "GPIOD";
			};

			gpioe: gpio@40011800 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x40011800 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000041>;
				label = "GPIOE";
			};
		};

		usart1: serial@40013800 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40013800 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
			interrupts = <37 0>;
			status = "disabled";
			label = "UART_1";
		};

		usart2: serial@40004400 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40004400 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
			interrupts = <38 0>;
			status = "disabled";
			label = "UART_2";
		};

		usart3: serial@40004800 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40004800 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
			interrupts = <39 0>;
			status = "disabled";
			label = "UART_3";
		};

		i2c1: i2c@40005400 {
			compatible = "st,stm32-i2c-v1";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40005400 0x400>;
			interrupts = <31 0>, <32 0>;
			interrupt-names = "event", "error";
			status = "disabled";
			label= "I2C_1";
		};

		i2c2: i2c@40005800 {
			compatible = "st,stm32-i2c-v1";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40005800 0x400>;
			interrupts = <33 0>, <34 0>;
			interrupt-names = "event", "error";
			status = "disabled";
			label= "I2C_2";
		};

		spi1: spi@40013000 {
			compatible = "st,stm32-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40013000 0x400>;
			interrupts = <35 5>;
			status = "disabled";
			label = "SPI_1";
		};
	};
};

&nvic {
	arm,num-irq-priority-bits = <4>;
};