| commit | e774d82cbe14655f3a3ca2694da139b4366b6d2a | [log] [tgz] |
|---|---|---|
| author | Andre Heinemans <andre.heinemans@nxp.com> | Thu Oct 02 16:03:23 2025 +0200 |
| committer | Benjamin Cabé <kartben@gmail.com> | Wed Oct 08 12:04:52 2025 +0200 |
| tree | 8b12a70e15e98cd33f05e3c41035b8c3a96e8bda | |
| parent | 424459d5d7cbba0f6c5e7160bd73be034ab18539 [diff] |
drivers: flash: flexspi_mx25um51345g: fix DDR dummy cycles In the DDR LUT, the dummy cycles were not defined for READ_STATUS_REG and had a wrong value for READ. The default amount of dummy cycles on this chip are 20 (0x14). This means the LUT should contain the value of 0x28 (0x14*2) for DDR at these entries. Signed-off-by: Andre Heinemans <andre.heinemans@nxp.com>