/*
 * Copyright (c) 2020 Linaro Limited
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <st/f4/stm32f407.dtsi>
#include <zephyr/dt-bindings/clock/stm32f427_clock.h>
#include <zephyr/dt-bindings/memory-controller/stm32-fmc-sdram.h>

/ {
	soc {
		pinctrl: pin-controller@40020000 {
			reg = <0x40020000 0x2C00>;

			gpioj: gpio@40022400 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x40022400 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000200>;
			};

			gpiok: gpio@40022800 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x40022800 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000400>;
			};
		};

		uart7: serial@40007800 {
			compatible = "st,stm32-uart";
			reg = <0x40007800 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
			resets = <&rctl STM32_RESET(APB1, 30U)>;
			interrupts = <82 0>;
			status = "disabled";
		};

		uart8: serial@40007c00 {
			compatible = "st,stm32-uart";
			reg = <0x40007c00 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
			resets = <&rctl STM32_RESET(APB1, 31U)>;
			interrupts = <83 0>;
			status = "disabled";
		};

		spi4: spi@40013400 {
			compatible = "st,stm32-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40013400 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
			interrupts = <84 5>;
			status = "disabled";
		};

		/* spi5 is present on all STM32F427XX and derivates SoCs except
		 * some vX variants. Delete node in vX.dtsi.
		 */
		 spi5: spi@40015000 {
			compatible = "st,stm32-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40015000 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
			interrupts = <85 5>;
			status = "disabled";
		};

		/* spi6 is present on all STM32F427XX and derivates SoCs except
		 * some vX variants. Delete node in vX.dtsi.
		 */
		spi6: spi@40015400 {
			compatible = "st,stm32-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40015400 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00200000>;
			interrupts = <86 5>;
			status = "disabled";
		};

		fmc: memory-controller@a0000000 {
			compatible = "st,stm32-fmc";
			reg = <0xa0000000 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000001>;
			status = "disabled";

			sdram: sdram {
				compatible = "st,stm32-fmc-sdram";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};
		};
	};

	die_temp: dietemp {
		io-channels = <&adc1 18>;
	};
};