tree 3f51742c59a72e73b233272fa2dfd97da43f0c31
parent b79d66a712b5945c1b0f6261341851055ae2c800
author Neil Armstrong <narmstrong@baylibre.com> 1633354211 +0200
committer Anas Nashif <anas.nashif@intel.com> 1642617456 -0500

pcie: controller: add Type 1 bridge configuration

This adds setup of Type 1 bridge endpoints in two steps, first when
endpoint is detected and secondly when enumerating the next endpoint.

First, the code configures the bus primary & secondary number and 0xff
as subordinate to redirect all PCIe messages to this bus.

Then memory & I/O base are programmed by getting the current allocation
bases.

Finally, now right away, we program the subordinate to the max bus
number under the bridge, here the same, and the memory & I/O limit,
here lower than the base.

This doesn't make the bridge totally usable, enumeration would work
bus not for nested bridges and BARs wouldn't be accessible.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>