| /* |
| * Copyright (c) 2025 STMicroelectronics |
| * Copyright (c) 2025 ZAL Zentrum für Angewandte Luftfahrtforschung GmbH |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <arm/armv8-m.dtsi> |
| #include <zephyr/dt-bindings/adc/adc.h> |
| #include <zephyr/dt-bindings/adc/stm32u5_adc.h> |
| #include <zephyr/dt-bindings/clock/stm32u3_clock.h> |
| #include <zephyr/dt-bindings/dma/stm32_dma.h> |
| #include <zephyr/dt-bindings/gpio/gpio.h> |
| #include <zephyr/dt-bindings/i2c/i2c.h> |
| #include <zephyr/dt-bindings/reset/stm32u3_reset.h> |
| #include <freq.h> |
| |
| / { |
| chosen { |
| zephyr,entropy = &rng; |
| zephyr,flash-controller = &flash; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-m33"; |
| reg = <0>; |
| }; |
| }; |
| |
| sram0: memory@20000000 { |
| compatible = "zephyr,memory-region", "mmio-sram"; |
| zephyr,memory-region = "SRAM0"; |
| }; |
| |
| clocks { |
| clk_hse: clk-hse { |
| #clock-cells = <0>; |
| compatible = "st,stm32-hse-clock"; |
| status = "disabled"; |
| }; |
| |
| clk_hsi: clk-hsi { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <DT_FREQ_M(16)>; |
| status = "disabled"; |
| }; |
| |
| clk_hsi48: clk-hsi48 { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <DT_FREQ_M(48)>; |
| status = "disabled"; |
| }; |
| |
| clk_msis: clk-msis { |
| #clock-cells = <0>; |
| compatible = "st,stm32u3-msi-clock"; |
| msi-range = <0>; /* 96MHz (reset value) */ |
| status = "disabled"; |
| }; |
| |
| clk_msik: clk-msik { |
| #clock-cells = <0>; |
| compatible = "st,stm32u3-msi-clock"; |
| msi-range = <0>; /* 96MHz (reset value) */ |
| status = "disabled"; |
| }; |
| |
| clk_lse: clk-lse { |
| #clock-cells = <0>; |
| compatible = "st,stm32-lse-clock"; |
| clock-frequency = <32768>; |
| driving-capability = <2>; |
| status = "disabled"; |
| }; |
| |
| clk_lsi: clk-lsi { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <DT_FREQ_K(32)>; |
| status = "disabled"; |
| }; |
| }; |
| |
| soc { |
| flash: flash-controller@40022000 { |
| compatible = "st,stm32-flash-controller", "st,stm32u3-flash-controller"; |
| reg = <0x40022000 0x400>; |
| interrupts = <6 0>; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| flash0: flash@8000000 { |
| compatible = "st,stm32-nv-flash", "soc-nv-flash"; |
| |
| write-block-size = <16>; |
| erase-block-size = <4096>; |
| /* maximum erase time(ms) for a 4KB page */ |
| max-erase-time = <14>; |
| }; |
| }; |
| |
| rcc: rcc@40030c00 { |
| compatible = "st,stm32u5-rcc"; |
| clocks-controller; |
| #clock-cells = <2>; |
| reg = <0x40030c00 0x400>; |
| |
| rctl: reset-controller { |
| compatible = "st,stm32-rcc-rctl"; |
| #reset-cells = <1>; |
| }; |
| }; |
| |
| exti: interrupt-controller@40032000 { |
| compatible = "st,stm32g0-exti", "st,stm32-exti"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| #address-cells = <1>; |
| reg = <0x40032000 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB3, 1)>; |
| num-lines = <22>; |
| interrupts = <11 0>, <12 0>, <13 0>, <14 0>, |
| <15 0>, <16 0>, <17 0>, <18 0>, |
| <19 0>, <20 0>, <21 0>, <22 0>, |
| <23 0>, <24 0>, <25 0>, <26 0>; |
| interrupt-names = "line0", "line1", "line2", "line3", |
| "line4", "line5", "line6", "line7", |
| "line8", "line9", "line10", "line11", |
| "line12", "line13", "line14", "line15"; |
| line-ranges = <0 1>, <1 1>, <2 1>, <3 1>, |
| <4 1>, <5 1>, <6 1>, <7 1>, |
| <8 1>, <9 1>, <10 1>, <11 1>, |
| <12 1>, <13 1>, <14 1>, <15 1>; |
| }; |
| |
| pinctrl: pin-controller@42020000 { |
| compatible = "st,stm32-pinctrl"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x42020000 0x2000>; |
| |
| gpioa: gpio@42020000 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x42020000 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB2, 0)>; |
| }; |
| |
| gpiob: gpio@42020400 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x42020400 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB2, 1)>; |
| }; |
| |
| gpioc: gpio@42020800 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x42020800 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB2, 2)>; |
| }; |
| |
| gpiod: gpio@42020c00 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x42020c00 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB2, 3)>; |
| }; |
| |
| gpioe: gpio@42021000 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x42021000 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB2, 4)>; |
| }; |
| |
| gpiog: gpio@42021800 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x42021800 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB2, 6)>; |
| }; |
| |
| gpioh: gpio@42021c00 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x42021c00 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB2, 7)>; |
| }; |
| }; |
| |
| usart1: serial@40013800 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40013800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 14)>; |
| resets = <&rctl STM32_RESET(APB2, 14)>; |
| interrupts = <61 0>; |
| status = "disabled"; |
| }; |
| |
| usart3: serial@40004800 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40004800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 18)>; |
| resets = <&rctl STM32_RESET(APB1L, 18)>; |
| interrupts = <63 0>; |
| status = "disabled"; |
| }; |
| |
| uart4: serial@40004c00 { |
| compatible = "st,stm32-uart"; |
| reg = <0x40004c00 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 19)>; |
| resets = <&rctl STM32_RESET(APB1L, 19)>; |
| interrupts = <64 0>; |
| status = "disabled"; |
| }; |
| |
| lpuart1: serial@40042400 { |
| compatible = "st,stm32-lpuart", "st,stm32-uart"; |
| reg = <0x40042400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB3, 6)>; |
| resets = <&rctl STM32_RESET(APB3, 6)>; |
| interrupts = <66 0>; |
| status = "disabled"; |
| }; |
| |
| adc1: adc@42028000 { |
| compatible = "st,stm32n6-adc", "st,stm32-adc"; |
| reg = <0x42028000 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB2, 10)>; |
| interrupts = <37 0>; |
| #io-channel-cells = <1>; |
| resolutions = <STM32_ADC_RES(12, 0x00) |
| STM32_ADC_RES(10, 0x01) |
| STM32_ADC_RES(8, 0x02) |
| STM32_ADC_RES(6, 0x03)>; |
| sampling-times = <2 3 7 12 24 47 247 1500>; |
| st,adc-sequencer = "FULLY_CONFIGURABLE"; |
| st,adc-oversampler = "OVERSAMPLER_EXTENDED"; |
| status = "disabled"; |
| }; |
| |
| adc2: adc@42028100 { |
| compatible = "st,stm32n6-adc", "st,stm32-adc"; |
| reg = <0x42028100 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB2, 10)>; |
| interrupts = <113 0>; |
| #io-channel-cells = <1>; |
| resolutions = <STM32_ADC_RES(12, 0x00) |
| STM32_ADC_RES(10, 0x01) |
| STM32_ADC_RES(8, 0x02) |
| STM32_ADC_RES(6, 0x03)>; |
| sampling-times = <2 3 7 12 24 47 247 1500>; |
| st,adc-sequencer = "FULLY_CONFIGURABLE"; |
| st,adc-oversampler = "OVERSAMPLER_EXTENDED"; |
| status = "disabled"; |
| }; |
| |
| dac1: dac@42028400 { |
| compatible = "st,stm32-dac"; |
| reg = <0x42028400 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB2, 11)>; |
| #io-channel-cells = <1>; |
| status = "disabled"; |
| }; |
| |
| fdcan1: can@4000a400 { |
| compatible = "st,stm32-fdcan"; |
| reg = <0x4000a400 0x400>, <0x4000ac00 0x350>; |
| reg-names = "m_can", "message_ram"; |
| interrupts = <39 0>, <40 0>; |
| interrupt-names = "int0", "int1"; |
| clocks = <&rcc STM32_CLOCK(APB1_2, 9)>; |
| bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@40005400 { |
| compatible = "st,stm32-i2c-v2"; |
| reg = <0x40005400 0x400>; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&rcc STM32_CLOCK(APB1, 21)>; |
| interrupts = <55 0>, <56 0>; |
| interrupt-names = "event", "error"; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@40005800 { |
| compatible = "st,stm32-i2c-v2"; |
| reg = <0x40005800 0x400>; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&rcc STM32_CLOCK(APB1, 22)>; |
| interrupts = <57 0>, <58 0>; |
| interrupt-names = "event", "error"; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@40042800 { |
| compatible = "st,stm32-i2c-v2"; |
| reg = <0x40042800 0x400>; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&rcc STM32_CLOCK(APB3, 7)>; |
| interrupts = <88 0>, <89 0>; |
| interrupt-names = "event", "error"; |
| status = "disabled"; |
| }; |
| |
| rng: rng@420c0800 { |
| compatible = "st,stm32-rng"; |
| reg = <0x420c0800 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB2, 18)>; |
| interrupts = <94 0>; |
| status = "disabled"; |
| }; |
| |
| gpdma1: dma@40020000 { |
| compatible = "st,stm32u5-dma"; |
| #dma-cells = <3>; |
| reg = <0x40020000 0x400>; |
| interrupts = <29 0 30 0 31 0 32 0 33 0 34 0 35 0 36 0 |
| 80 0 81 0 82 0 83 0>; |
| clocks = <&rcc STM32_CLOCK(AHB1, 0)>; |
| dma-channels = <12>; |
| dma-requests = <114>; |
| dma-offset = <0>; |
| status = "disabled"; |
| }; |
| |
| spi1: spi@40013000 { |
| compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40013000 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 12)>; |
| interrupts = <59 0>; |
| status = "disabled"; |
| }; |
| |
| spi2: spi@40003800 { |
| compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40003800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 14)>; |
| interrupts = <60 0>; |
| status = "disabled"; |
| }; |
| |
| spi3: spi@40002000 { |
| compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40002000 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 8)>; |
| interrupts = <99 0>; |
| status = "disabled"; |
| }; |
| |
| iwdg: watchdog@40003000 { |
| compatible = "st,stm32-watchdog"; |
| reg = <0x40003000 0x400>; |
| status = "disabled"; |
| }; |
| |
| wwdg: watchdog@40002c00 { |
| compatible = "st,stm32-window-watchdog"; |
| reg = <0x40002c00 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 11)>; |
| interrupts = <0 0>; |
| status = "disabled"; |
| }; |
| |
| sai1_a: sai1@40015404 { |
| compatible = "st,stm32-sai"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40015404 0x20>; |
| clocks = <&rcc STM32_CLOCK(APB2, 21)>; |
| dmas = <&gpdma1 1 36 (STM32_DMA_MODE_NORMAL | STM32_DMA_PRIORITY_HIGH | |
| STM32_DMA_16BITS)>; |
| status = "disabled"; |
| }; |
| |
| sai1_b: sai1@40015424 { |
| compatible = "st,stm32-sai"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40015424 0x20>; |
| clocks = <&rcc STM32_CLOCK(APB2, 21)>; |
| dmas = <&gpdma1 0 37 (STM32_DMA_MODE_NORMAL | STM32_DMA_PRIORITY_HIGH | |
| STM32_DMA_16BITS)>; |
| status = "disabled"; |
| }; |
| |
| usb: usb@40016000 { |
| compatible = "st,stm32-usb"; |
| reg = <0x40016000 0x400>; |
| interrupts = <73 0>; |
| interrupt-names = "usb"; |
| num-bidir-endpoints = <8>; |
| ram-size = <2048>; |
| maximum-speed = "full-speed"; |
| clocks = <&rcc STM32_CLOCK(APB2, 24)>, |
| <&rcc STM32_SRC_HSI48 ICLK_SEL(0)>; |
| phys = <&usb_fs_phy>; |
| status = "disabled"; |
| }; |
| }; |
| |
| usb_fs_phy: usb_fs_phy { |
| compatible = "usb-nop-xceiv"; |
| #phy-cells = <0>; |
| }; |
| }; |
| |
| &nvic { |
| arm,num-irq-priority-bits = <4>; |
| }; |
