# Copyright 2024 NXP
# SPDX-License-Identifier: Apache-2.0

config SOC_MIMX8MM6_A53
	select ARM64
	select CPU_CORTEX_A53
	select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS
	select HAS_MCUX if CLOCK_CONTROL
	select HAS_MCUX_CCM if CLOCK_CONTROL
	select HAS_MCUX_IOMUXC if PINCTRL
	select HAS_MCUX_RDC

config SOC_MIMX8MM6_M4
	select ARM
	select CPU_CORTEX_M4
	select CPU_HAS_FPU
	select CPU_HAS_ARM_MPU
	select HAS_MCUX
	select HAS_MCUX_CCM
	select HAS_MCUX_RDC
	select HAS_MCUX_IGPIO
	select HAS_MCUX_IOMUXC

config SOC_MIMX8ML8_A53
	select ARM64
	select CPU_CORTEX_A53
	select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS
	select HAS_MCUX if CLOCK_CONTROL
	select HAS_MCUX_CCM if CLOCK_CONTROL
	select HAS_MCUX_IOMUXC if PINCTRL
	select HAS_MCUX_RDC

config SOC_MIMX8MN6_A53
	select ARM64
	select CPU_CORTEX_A53
	select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS
	select HAS_MCUX if CLOCK_CONTROL
	select HAS_MCUX_CCM if CLOCK_CONTROL
	select HAS_MCUX_IOMUXC if PINCTRL
	select HAS_MCUX_RDC

config SOC_MIMX8ML8_ADSP
	select XTENSA
	select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang")
	select XTENSA_RESET_VECTOR
	select XTENSA_USE_CORE_CRT1
	select ATOMIC_OPERATIONS_BUILTIN
	select GEN_ISR_TABLES
	select XTENSA_SMALL_VECTOR_TABLE_ENTRY
	select HAS_MCUX if CLOCK_CONTROL
	select HAS_MCUX_CCM if CLOCK_CONTROL
	select HAS_MCUX_IOMUXC if PINCTRL
	select PINCTRL_IMX if HAS_MCUX_IOMUXC
	select CPU_HAS_DCACHE

config SOC_MIMX8ML8_M7
	select ARM
	select CPU_CORTEX_M7
	select CPU_HAS_FPU
	select CPU_HAS_ICACHE
	select CPU_HAS_DCACHE
	select INIT_VIDEO_PLL
	select HAS_MCUX
	select HAS_MCUX_CCM
	select HAS_MCUX_RDC
	select CPU_HAS_ARM_MPU
	select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
	select ARM_MPU
	select HAS_MCUX_IGPIO
	select HAS_MCUX_IOMUXC

config SOC_MIMX8MQ6_M4
	select ARM
	select CPU_CORTEX_M4
	select CPU_HAS_FPU
	select CPU_HAS_ARM_MPU
	select HAS_MCUX
	select HAS_MCUX_CCM
	select HAS_MCUX_RDC
	select HAS_MCUX_IOMUXC

config MCUX_CORE_SUFFIX
	default "_ca53" if SOC_MIMX8MM6_A53 || SOC_MIMX8MN6_A53 || SOC_MIMX8ML8_A53
	default "_dsp" if SOC_MIMX8ML8_ADSP

if SOC_MIMX8ML8_M7

choice CODE_LOCATION
	prompt "Code location selection"

config CODE_ITCM
	bool "Link code into internal instruction tightly coupled memory (ITCM)"

config CODE_DDR
	bool "Link code into DDR memory"

endchoice

config INIT_VIDEO_PLL
	bool "Initialize Video PLL"

endif # SOC_MIMX8ML8_M7