)]}'
{
  "commit": "f885763b507a29431c5b6dbdb44a410ec88c76bf",
  "tree": "38561029e067a8cd5067f18e0478a401bc0d129e",
  "parents": [
    "7631e0ddfaa9ff2f286fb11983cbab2db510f900"
  ],
  "author": {
    "name": "Gerard Marull-Paretas",
    "email": "gerard@teslabs.com",
    "time": "Wed Jan 10 13:05:28 2024 +0100"
  },
  "committer": {
    "name": "Carles Cufí",
    "email": "carles.cufi@nordicsemi.no",
    "time": "Fri Jan 12 09:58:31 2024 +0100"
  },
  "message": "arch: riscv: drop RISCV_HAS_CPU_IDLE\n\nBecause it was exclusively used by the \"common\" RISC-V privileged code\nto build CPU idle routines that are now handled by arch level code.\nAlso, all platforms defaulted to \"y\", making it pointless in practice.\n\nSigned-off-by: Gerard Marull-Paretas \u003cgerard@teslabs.com\u003e\n",
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