ext: simplelink: import HAL from TI CC13x2 / CC26x2 SDK 3.10.00.53
Add low level drivers (driverlib) and RF patches from the TI CC13x2 and
CC26x2 SDK. These sources have been added unmodified with the exception
of converting DOS to UNIX line endings.
The majority of these APIs are available in ROM and inclusion of the
headers will map functions that are not inline to the ROM versions.
Origin: Texas Instruments SimpleLink CC13x2 and CC26x2 SDK
License: BSD 3-Clause
URL: http://www.ti.com/tool/simplelink-cc13x2-26x2-sdk
Purpose: Provides HAL for TI CC13x2 and CC26x2 SoCs
Maintained-by: External
Signed-off-by: Brett Witherspoon <spoonb@cdspooner.com>
diff --git a/ext/hal/ti/simplelink/Kconfig b/ext/hal/ti/simplelink/Kconfig
index adc48f3..57b35e4 100644
--- a/ext/hal/ti/simplelink/Kconfig
+++ b/ext/hal/ti/simplelink/Kconfig
@@ -23,3 +23,8 @@
config HAS_MSP432P4XXSDK
bool
select HAS_CMSIS
+
+# Kconfig - CC13X2 / CC26X2 SDK HAL configuration
+
+config HAS_CC13X2_CC26X2_SDK
+ bool
diff --git a/ext/hal/ti/simplelink/README b/ext/hal/ti/simplelink/README
index 1f3254c..2d49f90 100644
--- a/ext/hal/ti/simplelink/README
+++ b/ext/hal/ti/simplelink/README
@@ -5,7 +5,29 @@
For an explanation of the SimpleLink family SDK directory structure, see:
http://dev.ti.com/tirex/content/simplelink_cc32xx_sdk_2_40_01_01/docs/simplelink_mcu_sdk/Users_Guide.html#directory-structure
-1. CC32xx SDK
+1. CC13x2/26x2 SDK
+
+The current version supported in Zephyr is the SimpleLink CC13x2 and CC26x2 SDK
+3.10.00.53, downloaded from:
+
+ http://www.ti.com/tool/simplelink-cc13x2-26x2-sdk
+
+The driver library source is copied from the SDK, as follows:
+
+ EXT_DIR=$ZEPHYR_BASE/ext/hal/ti/simplelink/source/ti
+ pushd simplelink_cc13x2_26x2_sdk_3_10_00_53/source/ti
+ find devices/cc13x2_cc26x2/{driverlib,inc,rf_patches} -depth -name '*.[c|h]' -print0 | cpio --null -pvdm $EXT_DIR
+ find devices/cc13x2_cc26x2/startup_files -depth -name ccfg.c -print0 | cpio --null -pvd $EXT_DIR
+ find $EXT_DIR/devices/cc13x2_cc26x2 -name '*.[c|h]' -exec dos2unix {} \;
+ popd
+
+TI provides the driver library functions burned into ROM at the factory,
+or updated via a service pack patch, thus saving application code space.
+
+After setting CONFIG_HAS_CC13X2_CC26X2_SDK=y in Kconfig, most of the
+peripheral driver library functions will be accessible from ROM.
+
+2. CC32xx SDK
The current version supported in Zephyr is the SimpleLink CC32xx SDK
2.40.01.01, downloaded from:
diff --git a/ext/hal/ti/simplelink/source/ti/devices/CMakeLists.txt b/ext/hal/ti/simplelink/source/ti/devices/CMakeLists.txt
index 5cb15e3..93caf4e 100644
--- a/ext/hal/ti/simplelink/source/ti/devices/CMakeLists.txt
+++ b/ext/hal/ti/simplelink/source/ti/devices/CMakeLists.txt
@@ -1,3 +1,3 @@
add_subdirectory_ifdef(CONFIG_HAS_CC3220SDK cc32xx)
add_subdirectory_ifdef(CONFIG_HAS_MSP432P4XXSDK msp432p4xx)
-
+add_subdirectory_ifdef(CONFIG_HAS_CC13X2_CC26X2_SDK cc13x2_cc26x2)
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/CMakeLists.txt b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/CMakeLists.txt
new file mode 100644
index 0000000..90a36b7
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/CMakeLists.txt
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(
+ .
+ )
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/adi.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/adi.c
new file mode 100644
index 0000000..77e5a47
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/adi.c
@@ -0,0 +1,43 @@
+/******************************************************************************
+* Filename: adi.c
+* Revised: 2016-11-17 16:39:28 +0100 (Thu, 17 Nov 2016)
+* Revision: 47706
+*
+* Description: Driver for the ADI interface
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "../inc/hw_types.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_aux_smph.h"
+#include "adi.h"
+#include "cpu.h"
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/adi.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/adi.h
new file mode 100644
index 0000000..450847e
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/adi.h
@@ -0,0 +1,791 @@
+/******************************************************************************
+* Filename: adi.h
+* Revised: 2016-11-17 16:39:28 +0100 (Thu, 17 Nov 2016)
+* Revision: 47706
+*
+* Description: Defines and prototypes for the ADI master interface.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup analog_group
+//! @{
+//! \addtogroup adi_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __ADI_H__
+#define __ADI_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "../inc/hw_types.h"
+#include "../inc/hw_uart.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_ints.h"
+#include "../inc/hw_adi.h"
+#include "debug.h"
+#include "ddi.h"
+
+//*****************************************************************************
+//
+// Number of registers in the ADI slave
+//
+//*****************************************************************************
+#define ADI_SLAVE_REGS 16
+
+
+//*****************************************************************************
+//
+// Defines that is used to control the ADI slave and master
+//
+//*****************************************************************************
+#define ADI_PROTECT 0x00000080
+#define ADI_ACK 0x00000001
+#define ADI_SYNC 0x00000000
+
+//*****************************************************************************
+//
+// API Functions and prototypes
+//
+//*****************************************************************************
+
+#ifdef DRIVERLIB_DEBUG
+//*****************************************************************************
+//
+//! \internal
+//! \brief Checks an ADI base address.
+//!
+//! This function determines if an ADI port base address is valid.
+//!
+//! \param ui32Base is the base address of the ADI port.
+//!
+//! \return Returns \c true if the base address is valid and \c false
+//! otherwise
+//
+//*****************************************************************************
+static bool
+ADIBaseValid(uint32_t ui32Base)
+{
+ return(ui32Base == ADI2_BASE || ui32Base == ADI3_BASE ||
+ ui32Base == AUX_ADI4_BASE);
+}
+#endif
+
+
+
+
+
+//*****************************************************************************
+//
+//! \brief Write an 8 bit value to a register in an ADI slave.
+//!
+//! This function will write a value to a single register in the analog domain.
+//! The access to the registers in the analog domain is either 8, 16, or 32 bit
+//! aligned. You can only do 16 bit access on registers 0-1 / 2-3, etc. Similarly
+//! 32 bit accesses are always performed on register 0-3 / 4-7, etc. Addresses
+//! for the registers and values being written to the registers will be
+//! truncated according to this access scheme.
+//!
+//! \note This operation is write only for the specified register. No
+//! previous value of the register will be kept (i.e. this is NOT
+//! read-modify-write on the register).
+//!
+//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be
+//! enabled before calling this function.
+//!
+//! \param ui32Base is ADI base address.
+//! \param ui32Reg is the register to write.
+//! \param ui8Val is the 8 bit value to write to the register.
+//!
+//! \return None
+//!
+//! \sa ADI16RegWrite(), ADI32RegWrite()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+ADI8RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint8_t ui8Val)
+{
+ // Check the arguments.
+ ASSERT(ADIBaseValid(ui32Base));
+ ASSERT(ui32Reg < ADI_SLAVE_REGS);
+
+ // Write the value to the register.
+ HWREGB(ui32Base + ui32Reg) = ui8Val;
+}
+
+//*****************************************************************************
+//
+//! \brief Write a 16 bit value to 2 registers in the ADI slave.
+//!
+//! This function will write a value to 2 consecutive registers in the analog
+//! domain. The access to the registers in the analog domain is either 8, 16
+//! or 32 bit aligned. You can only do 16 bit access on registers 0-1 / 2-3,
+//! etc. Similarly 32 bit accesses are always performed on register 0-3 / 4-7,
+//! etc. Addresses for the registers and values being written
+//! to the registers will be truncated according to this access scheme.
+//!
+//! \note The byte addressing bit will be ignored, to ensure 16 bit access
+//! to the ADI slave.
+//!
+//! \note This operation is write only for the specified register. No
+//! previous value of the register will be kept (i.e. this is NOT
+//! read-modify-write on the register).
+//!
+//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be
+//! enabled before calling this function.
+//!
+//! \param ui32Base is ADI base address.
+//! \param ui32Reg is the register to write.
+//! \param ui16Val is the 16 bit value to write to the register.
+//!
+//! \return None
+//!
+//! \sa ADI8RegWrite(), ADI32RegWrite()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+ADI16RegWrite(uint32_t ui32Base, uint32_t ui32Reg,
+ uint16_t ui16Val)
+{
+ // Check the arguments.
+ ASSERT(ADIBaseValid(ui32Base));
+ ASSERT(ui32Reg < ADI_SLAVE_REGS);
+
+ // Write the value to the register.
+ HWREGH(ui32Base + (ui32Reg & 0xFE)) = ui16Val;
+}
+
+//*****************************************************************************
+//
+//! \brief Write a 32 bit value to 4 registers in the ADI slave.
+//!
+//! This function will write a value to 4 consecutive registers in the analog
+//! domain. The access to the registers in the analog domain is either 8, 16
+//! or 32 bit aligned. You can only do 16 bit access on registers 0-1 / 2-3,
+//! etc. Similarly 32 bit accesses are always performed on register 0-3 / 4-7,
+//! etc. Addresses for the registers and values being written
+//! to the registers will be truncated according to this access scheme.
+//!
+//! \note The byte and half word addressing bits will be ignored, to ensure
+//! 32 bit access to the ADI slave.
+//!
+//! \note This operation is write only for the specified register. No
+//! previous value of the register will be kept (i.e. this is NOT
+//! read-modify-write on the register).
+//!
+//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be
+//! enabled before calling this function.
+//!
+//! \param ui32Base is ADI base address.
+//! \param ui32Reg is the register to write.
+//! \param ui32Val is the 32 bit value to write to the register.
+//!
+//! \return None
+//!
+//! \sa ADI8RegWrite(), ADI16RegWrite()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+ADI32RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val)
+{
+ // Check the arguments.
+ ASSERT(ADIBaseValid(ui32Base));
+ ASSERT(ui32Reg < ADI_SLAVE_REGS);
+
+ // Write the value to the register.
+ HWREG(ui32Base + (ui32Reg & 0xFC)) = ui32Val;
+}
+
+//*****************************************************************************
+//
+//! \brief Read the value of an 8 bit register in the ADI slave.
+//!
+//! This function will read an 8 bit register in the analog domain and return
+//! the value as the lower 8 bits of an \c uint32_t. The access to the
+//! registers in the analog domain is either 8, 16 or 32 bit aligned. You can
+//! only do 16 bit access on registers 0-1 / 2-3, etc. Similarly 32 bit accesses
+//! are always performed on register 0-3 / 4-7, etc. Addresses for the
+//! registers and values being written to the registers will be truncated
+//! according to this access scheme.
+//!
+//! \param ui32Base is ADI base address.
+//! \param ui32Reg is the 8 bit register to read.
+//!
+//! \return Returns the 8 bit value of the analog register in the least
+//! significant byte of the \c uint32_t.
+//!
+//! \sa ADI16RegRead(), ADI32RegRead()
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+ADI8RegRead(uint32_t ui32Base, uint32_t ui32Reg)
+{
+ // Check the arguments.
+ ASSERT(ADIBaseValid(ui32Base));
+ ASSERT(ui32Reg < ADI_SLAVE_REGS);
+
+ // Read the register and return the value.
+ return(HWREGB(ui32Base + ui32Reg));
+}
+
+//*****************************************************************************
+//
+//! \brief Read the value in a 16 bit register.
+//!
+//! This function will read 2 x 8 bit registers in the analog domain and return
+//! the value as the lower 16 bits of an \c uint32_t. The access to the
+//! registers in the analog domain is either 8, 16 or 32 bit aligned. You can
+//! only do 16 bit access on registers 0-1 / 2-3, etc. Similarly 32 bit accesses
+//! are always performed on register 0-3 / 4-7, etc. Addresses for the
+//! registers and values being written to the registers will be truncated
+//! according to this access scheme.
+//!
+//! \note The byte addressing bit will be ignored, to ensure 16 bit access
+//! to the ADI slave.
+//!
+//! \param ui32Base is ADI base address.
+//! \param ui32Reg is the 16 bit register to read.
+//!
+//! \return Returns the 16 bit value of the 2 analog register in the 2 least
+//! significant bytes of the \c uint32_t.
+//!
+//! \sa ADI8RegRead(), ADI32RegRead()
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+ADI16RegRead(uint32_t ui32Base, uint32_t ui32Reg)
+{
+ // Check the arguments.
+ ASSERT(ADIBaseValid(ui32Base));
+ ASSERT(ui32Reg < ADI_SLAVE_REGS);
+
+ // Read the registers and return the value.
+ return(HWREGH(ui32Base + (ui32Reg & 0xFE)));
+}
+
+//*****************************************************************************
+//
+//! \brief Read the value in a 32 bit register.
+//!
+//! This function will read 4 x 8 bit registers in the analog domain and return
+//! the value as an \c uint32_t. The access to the registers in the analog
+//! domain is either 8, 16 or 32 bit aligned. You can only do 16 bit access on
+//! registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always performed on
+//! register 0-3 / 4-7, etc. Addresses for the registers and values being
+//! written to the registers will be truncated according to this access scheme.
+//!
+//! \note The byte and half word addressing bits will be ignored, to ensure
+//! 32 bit access to the ADI slave.
+//!
+//! \param ui32Base is ADI base address.
+//! \param ui32Reg is the 32 bit register to read.
+//!
+//! \return Returns the 32 bit value of the 4 analog registers.
+//!
+//! \sa ADI8RegRead(), ADI16RegRead()
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+ADI32RegRead(uint32_t ui32Base, uint32_t ui32Reg)
+{
+ // Check the arguments.
+ ASSERT(ADIBaseValid(ui32Base));
+ ASSERT(ui32Reg < ADI_SLAVE_REGS);
+
+ // Read the registers and return the value.
+ return(HWREG(ui32Base + (ui32Reg & 0xFC)));
+}
+
+//*****************************************************************************
+//
+//! \brief Set specific bits in a single 8 bit ADI register.
+//!
+//! This function will set bits in a single register in the analog domain.
+//! The access to the registers in the analog domain is either 8, 16 or 32 bit
+//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access
+//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always
+//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values
+//! being written to the registers will be truncated according to this access
+//! scheme.
+//!
+//! \note This operation is write only for the specified register.
+//! This function is used to set bits in a specific 8 bit register in the
+//! ADI slave. Only bits in the selected register are affected by the
+//! operation.
+//!
+//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be
+//! enabled before calling this function.
+//!
+//! \param ui32Base is ADI base address.
+//! \param ui32Reg is the base register to assert the bits in.
+//! \param ui8Val is the 8 bit one-hot encoded value specifying which
+//! bits to set in the register.
+//!
+//! \return None
+//!
+//! \sa ADI16BitsSet(), ADI32BitsSet()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+ADI8BitsSet(uint32_t ui32Base, uint32_t ui32Reg, uint8_t ui8Val)
+{
+ uint32_t ui32RegOffset;
+
+ // Check the arguments.
+ ASSERT(ADIBaseValid(ui32Base));
+ ASSERT(ui32Reg < ADI_SLAVE_REGS);
+
+ // Get the correct address of the first register used for setting bits
+ // in the ADI slave.
+ ui32RegOffset = ADI_O_SET;
+
+ // Set the selected bits.
+ HWREGB(ui32Base + ui32RegOffset + ui32Reg) = ui8Val;
+}
+
+//*****************************************************************************
+//
+//! \brief Set specific bits in 2 x 8 bit ADI slave registers.
+//!
+//! This function will set bits in 2 registers in the analog domain.
+//! The access to the registers in the analog domain is either 8, 16 or 32 bit
+//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access
+//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always
+//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values
+//! being written to the registers will be truncated according to this access
+//! scheme.
+//!
+//! \note This operation is write only for the specified register.
+//! This function is used to set bits in 2 consecutive 8 bit registers in the
+//! ADI slave. Only bits in the selected registers are affected by the
+//! operation.
+//!
+//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be
+//! enabled before calling this function.
+//!
+//! \param ui32Base is ADI base address.
+//! \param ui32Reg is the base register to assert the bits in.
+//! \param ui16Val is the 16 bit one-hot encoded value specifying which
+//! bits to set in the registers.
+//!
+//! \return None
+//!
+//! \sa ADI8BitsSet(), ADI32BitsSet()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+ADI16BitsSet(uint32_t ui32Base, uint32_t ui32Reg, uint16_t ui16Val)
+{
+ uint32_t ui32RegOffset;
+
+ // Check the arguments.
+ ASSERT(ADIBaseValid(ui32Base));
+ ASSERT(ui32Reg < ADI_SLAVE_REGS);
+
+ // Get the correct address of the first register used for setting bits
+ // in the ADI slave.
+ ui32RegOffset = ADI_O_SET;
+
+ // Set the selected bits.
+ HWREGH(ui32Base + ui32RegOffset + (ui32Reg & 0xFE)) = ui16Val;
+}
+
+//*****************************************************************************
+//
+//! \brief Set specific bits in 4 x 8 bit ADI slave registers.
+//!
+//! This function will set bits in 4 registers in the analog domain.
+//! The access to the registers in the analog domain is either 8, 16 or 32 bit
+//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access
+//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always
+//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values
+//! being written to the registers will be truncated according to this access
+//! scheme.
+//!
+//! \note This operation is write only for the specified register.
+//! This function is used to set bits in 4 consecutive 8 bit registers in the
+//! ADI slave. Only bits in the selected registers are affected by the
+//! operation.
+//!
+//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be
+//! enabled before calling this function.
+//!
+//! \param ui32Base is ADI base address.
+//! \param ui32Reg is the base register to assert the bits in.
+//! \param ui32Val is the 32 bit one-hot encoded value specifying which
+//! bits to set in the registers.
+//!
+//! \return None
+//!
+//! \sa ADI8BitsSet(), ADI16BitsSet()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+ADI32BitsSet(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val)
+{
+ uint32_t ui32RegOffset;
+
+ // Check the arguments.
+ ASSERT(ADIBaseValid(ui32Base));
+ ASSERT(ui32Reg < ADI_SLAVE_REGS);
+
+ // Get the correct address of the first register used for setting bits
+ // in the ADI slave.
+ ui32RegOffset = ADI_O_SET;
+
+ // Set the selected bits.
+ HWREG(ui32Base + ui32RegOffset + (ui32Reg & 0xFC)) = ui32Val;
+}
+
+//*****************************************************************************
+//
+//! \brief Clear specific bits in an 8 bit ADI register.
+//!
+//! This function will clear bits in a register in the analog domain.
+//! The access to the registers in the analog domain is either 8, 16 or 32 bit
+//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access
+//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always
+//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values
+//! being written to the registers will be truncated according to this access
+//! scheme.
+//!
+//! \note This operation is write only for the specified register.
+//! This function is used to clear bits in a specific 8 bit register in
+//! the ADI slave. Only bits in the selected register are affected by the
+//! operation.
+//!
+//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be
+//! enabled before calling this function.
+//!
+//! \param ui32Base is ADI base address.
+//! \param ui32Reg is the base registers to clear the bits in.
+//! \param ui8Val is the 8 bit one-hot encoded value specifying which
+//! bits to clear in the register.
+//!
+//! \return None
+//!
+//! \sa ADI16BitsClear(), ADI32BitsClear()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+ADI8BitsClear(uint32_t ui32Base, uint32_t ui32Reg, uint8_t ui8Val)
+{
+ uint32_t ui32RegOffset;
+
+ // Check the arguments.
+ ASSERT(ADIBaseValid(ui32Base));
+ ASSERT(ui32Reg < ADI_SLAVE_REGS);
+
+ // Get the correct address of the first register used for setting bits
+ // in the ADI slave.
+ ui32RegOffset = ADI_O_CLR;
+
+ // Set the selected bits.
+ HWREGB(ui32Base + ui32RegOffset + ui32Reg) = ui8Val;
+}
+
+//*****************************************************************************
+//
+//! \brief Clear specific bits in two 8 bit ADI register.
+//!
+//! This function will clear bits in 2 registers in the analog domain.
+//! The access to the registers in the analog domain is either 8, 16 or 32 bit
+//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access
+//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always
+//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values
+//! being written to the registers will be truncated according to this access
+//! scheme.
+//!
+//! \note This operation is write only for the specified register.
+//! This function is used to clear bits in 2 consecutive 8 bit registers in
+//! the ADI slave. Only bits in the selected registers are affected by the
+//! operation.
+//!
+//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be
+//! enabled before calling this function.
+//!
+//! \param ui32Base is ADI base address.
+//! \param ui32Reg is the base registers to clear the bits in.
+//! \param ui16Val is the 16 bit one-hot encoded value specifying which
+//! bits to clear in the registers.
+//!
+//! \return None
+//!
+//! \sa ADI8BitsClear(), ADI32BitsClear()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+ADI16BitsClear(uint32_t ui32Base, uint32_t ui32Reg, uint16_t ui16Val)
+{
+ uint32_t ui32RegOffset;
+
+ // Check the arguments.
+ ASSERT(ADIBaseValid(ui32Base));
+ ASSERT(ui32Reg < ADI_SLAVE_REGS);
+
+ // Get the correct address of the first register used for setting bits
+ // in the ADI slave.
+ ui32RegOffset = ADI_O_CLR;
+
+ // Set the selected bits.
+ HWREGH(ui32Base + ui32RegOffset + (ui32Reg & 0xFE)) = ui16Val;
+}
+
+//*****************************************************************************
+//
+//! \brief Clear specific bits in four 8 bit ADI register.
+//!
+//! This function will clear bits in 4 registers in the analog domain.
+//! The access to the registers in the analog domain is either 8, 16 or 32 bit
+//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access
+//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always
+//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values
+//! being written to the registers will be truncated according to this access
+//! scheme.
+//!
+//! \note This operation is write only for the specified register.
+//! This function is used to clear bits in 4 consecutive 8 bit registers in
+//! the ADI slave. Only bits in the selected registers are affected by the
+//! operation.
+//!
+//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be
+//! enabled before calling this function.
+//!
+//! \param ui32Base is ADI base address.
+//! \param ui32Reg is the base registers to clear the bits in.
+//! \param ui32Val is the 32 bit one-hot encoded value specifying which
+//! bits to clear in the registers.
+//!
+//! \return None
+//!
+//! \sa ADI8BitsClear(), ADI16BitsClear()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+ADI32BitsClear(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val)
+{
+ uint32_t ui32RegOffset;
+
+ // Check the arguments.
+ ASSERT(ADIBaseValid(ui32Base));
+ ASSERT(ui32Reg < ADI_SLAVE_REGS);
+
+ // Get the correct address of the first register used for setting bits
+ // in the ADI slave.
+ ui32RegOffset = ADI_O_CLR;
+
+ // Set the selected bits.
+ HWREG(ui32Base + ui32RegOffset + (ui32Reg & 0xFC)) = ui32Val;
+}
+
+//*****************************************************************************
+//
+//! \brief Set a value on any 4 bits inside an 8 bit register in the ADI slave.
+//!
+//! This function allows halfbyte (4 bit) access to the ADI slave registers.
+//! The parameter \c bWriteHigh determines whether to write to the lower
+//! or higher part of the 8 bit register.
+//!
+//! Use this function to write any value in the range 0-3 bits aligned on a
+//! half byte boundary. Fx. for writing the value 0b101 to bits 1 to 3 the
+//! \c ui8Val = 0xA and the \c ui8Mask = 0xE. Bit 0 will not be affected by
+//! the operation, as the corresponding bit is not set in the \c ui8Mask.
+//!
+//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be
+//! enabled before calling this function.
+//!
+//! \param ui32Base is the base address of the ADI port.
+//! \param ui32Reg is the Least Significant Register in the ADI slave that
+//! will be affected by the write operation.
+//! \param bWriteHigh defines which part of the register to write in.
+//! - \c true: Write upper half byte of register.
+//! - \c false: Write lower half byte of register.
+//! \param ui8Mask is the mask defining which of the 4 bits that should be
+//! overwritten. The mask must be defined in the lower half of the 8 bits of
+//! the parameter.
+//! \param ui8Val is the value to write. The value must be defined in the lower
+//! half of the 8 bits of the parameter.
+//!
+//! \return None
+//!
+//! \sa ADI8SetValBit(), ADI16SetValBit
+//
+//*****************************************************************************
+__STATIC_INLINE void
+ADI4SetValBit(uint32_t ui32Base, uint32_t ui32Reg, bool bWriteHigh,
+ uint8_t ui8Mask, uint8_t ui8Val)
+{
+ uint32_t ui32RegOffset;
+
+ // Check the arguments.
+ ASSERT(ADIBaseValid(ui32Base));
+ ASSERT(ui32Reg < ADI_SLAVE_REGS);
+ ASSERT(!(ui8Val & 0xF0));
+ ASSERT(!(ui8Mask & 0xF0));
+
+ // Get the correct address of the first register used for setting bits
+ // in the ADI slave.
+ ui32RegOffset = ADI_O_MASK4B + (ui32Reg << 1) + (bWriteHigh ? 1 : 0);
+
+ // Set the selected bits.
+ HWREGB(ui32Base + ui32RegOffset) = (ui8Mask << 4) | ui8Val;
+}
+
+//*****************************************************************************
+//
+//! \brief Set a value on any bits inside an 8 bit register in the ADI slave.
+//!
+//! This function allows byte (8 bit) access to the ADI slave registers.
+//!
+//! Use this function to write any value in the range 0-7 bits aligned on a
+//! byte boundary. Fx. for writing the value 0b101 to bits 1 and 3 the
+//! \c ui16Val = 0x0A and the \c ui16Mask = 0x0E. Bits 0 and 5-7 will not be affected
+//! by the operation, as the corresponding bits are not set in the
+//! \c ui16Mask.
+//!
+//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be
+//! enabled before calling this function.
+//!
+//! \param ui32Base is the base address of the ADI port.
+//! \param ui32Reg is the Least Significant Register in the ADI slave that
+//! will be affected by the write operation.
+//! \param ui16Mask is the mask defining which of the 8 bit that should be
+//! overwritten. The mask must be defined in the lower half of the 16 bits.
+//! \param ui16Val is the value to write. The value must be defined in the lower
+//! half of the 16 bits.
+//!
+//! \return None
+//!
+//! \sa ADI4SetValBit(), ADI16SetValBit()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+ADI8SetValBit(uint32_t ui32Base, uint32_t ui32Reg, uint16_t ui16Mask,
+ uint16_t ui16Val)
+{
+ uint32_t ui32RegOffset;
+
+ // Check the arguments.
+ ASSERT(ADIBaseValid(ui32Base));
+ ASSERT(ui32Reg < ADI_SLAVE_REGS);
+ ASSERT(!(ui16Val & 0xFF00));
+ ASSERT(!(ui16Mask & 0xFF00));
+
+ // Get the correct address of the first register used for setting bits
+ // in the ADI slave.
+ ui32RegOffset = ADI_O_MASK8B + (ui32Reg << 1);
+
+ // Set the selected bits.
+ HWREGH(ui32Base + ui32RegOffset) = (ui16Mask << 8) | ui16Val;
+}
+
+//*****************************************************************************
+//
+//! \brief Set a value on any bits inside an 2 x 8 bit register aligned on a
+//! half-word (byte) boundary in the ADI slave.
+//!
+//! This function allows 2 byte (16 bit) access to the ADI slave registers.
+//!
+//! Use this function to write any value in the range 0-15 bits aligned on a
+//! half-word (byte) boundary. Fx. for writing the value 0b101 to bits 1 and 3 the
+//! \c ui32Val = 0x000A and the \c ui32Mask = 0x000E. Bits 0 and 5-15 will not
+//! be affected by the operation, as the corresponding bits are not set
+//! in the \c ui32Mask.
+//!
+//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be
+//! enabled before calling this function.
+//!
+//! \param ui32Base is the base address of the ADI port.
+//! \param ui32Reg is the Least Significant Register in the ADI slave that
+//! will be affected by the write operation.
+//! \param ui32Mask is the mask defining which of the 16 bit that should be
+//! overwritten. The mask must be defined in the lower half of the 32 bits.
+//! \param ui32Val is the value to write. The value must be defined in the lower
+//! half of the 32 bits.
+//!
+//! \return None
+//!
+//! \sa ADI4SetValBit(), ADI8SetValBit()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+ADI16SetValBit(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask,
+ uint32_t ui32Val)
+{
+ uint32_t ui32RegOffset;
+
+ // Check the arguments.
+ ASSERT(ADIBaseValid(ui32Base));
+ ASSERT(ui32Reg < ADI_SLAVE_REGS);
+ ASSERT(!(ui32Val & 0xFFFF0000));
+ ASSERT(!(ui32Mask & 0xFFFF0000));
+
+ // Get the correct address of the first register used for setting bits
+ // in the ADI slave.
+ ui32RegOffset = ADI_O_MASK16B + ((ui32Reg << 1) & 0xFC);
+
+ // Set the selected bits.
+ HWREG(ui32Base + ui32RegOffset) = (ui32Mask << 16) | ui32Val;
+}
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __ADI_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/adi_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/adi_doc.h
new file mode 100644
index 0000000..e7eadca
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/adi_doc.h
@@ -0,0 +1,68 @@
+/******************************************************************************
+* Filename: adi_doc.h
+* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016)
+* Revision: 45971
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+//! \addtogroup adi_api
+//! @{
+//! \section sec_adi Introduction
+//! \n
+//!
+//! \section sec_adi_api API
+//!
+//! The API functions can be grouped like this:
+//!
+//! Write:
+//! - Direct (all bits):
+//! - \ref ADI8RegWrite()
+//! - \ref ADI16RegWrite()
+//! - \ref ADI32RegWrite()
+//! - Set individual bits:
+//! - \ref ADI8BitsSet()
+//! - \ref ADI16BitsSet()
+//! - \ref ADI32BitsSet()
+//! - Clear individual bits:
+//! - \ref ADI8BitsClear()
+//! - \ref ADI16BitsClear()
+//! - \ref ADI32BitsClear()
+//! - Masked:
+//! - \ref ADI4SetValBit()
+//! - \ref ADI8SetValBit()
+//! - \ref ADI16SetValBit()
+//!
+//! Read:
+//! - \ref ADI8RegRead()
+//! - \ref ADI16RegRead()
+//! - \ref ADI32RegRead()
+//!
+//! @}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aes.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aes.c
new file mode 100644
index 0000000..c480bf7
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aes.c
@@ -0,0 +1,372 @@
+
+/******************************************************************************
+* Filename: crypto.c
+* Revised: 2019-01-25 13:11:50 +0100 (Fri, 25 Jan 2019)
+* Revision: 54285
+*
+* Description: Driver for the aes functions of the crypto module
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "aes.h"
+
+//*****************************************************************************
+//
+// Handle support for DriverLib in ROM:
+// This section will undo prototype renaming made in the header file
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #undef AESStartDMAOperation
+ #define AESStartDMAOperation NOROM_AESStartDMAOperation
+ #undef AESSetInitializationVector
+ #define AESSetInitializationVector NOROM_AESSetInitializationVector
+ #undef AESWriteCCMInitializationVector
+ #define AESWriteCCMInitializationVector NOROM_AESWriteCCMInitializationVector
+ #undef AESReadTag
+ #define AESReadTag NOROM_AESReadTag
+ #undef AESVerifyTag
+ #define AESVerifyTag NOROM_AESVerifyTag
+ #undef AESWriteToKeyStore
+ #define AESWriteToKeyStore NOROM_AESWriteToKeyStore
+ #undef AESReadFromKeyStore
+ #define AESReadFromKeyStore NOROM_AESReadFromKeyStore
+ #undef AESWaitForIRQFlags
+ #define AESWaitForIRQFlags NOROM_AESWaitForIRQFlags
+ #undef AESConfigureCCMCtrl
+ #define AESConfigureCCMCtrl NOROM_AESConfigureCCMCtrl
+#endif
+
+
+
+//*****************************************************************************
+//
+// Load the initialization vector.
+//
+//*****************************************************************************
+void AESSetInitializationVector(const uint32_t *initializationVector)
+{
+ // Write initialization vector to the aes registers
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = initializationVector[0];
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = initializationVector[1];
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = initializationVector[2];
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = initializationVector[3];
+}
+
+//*****************************************************************************
+//
+// Start a crypto DMA operation.
+//
+//*****************************************************************************
+void AESStartDMAOperation(const uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length)
+{
+ if (channel0Length && channel0Addr) {
+ // We actually want to perform an operation. Clear any outstanding events.
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = CRYPTO_IRQCLR_RESULT_AVAIL_M | CRYPTO_IRQEN_DMA_IN_DONE_M; // This might need AES_IRQEN_DMA_IN_DONE as well
+
+ while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | CRYPTO_IRQSTAT_RESULT_AVAIL_M));
+
+ // Configure the DMA controller - enable both DMA channels.
+ HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1;
+
+ // Base address of the payload data in ext. memory.
+ HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)channel0Addr;
+
+ // Payload data length in bytes, equal to the cipher text length.
+ HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = channel0Length;
+ }
+
+ if (channel1Length && channel1Addr) {
+ // Enable DMA channel 1.
+ HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1;
+
+ // Base address of the output data buffer.
+ HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = (uint32_t)channel1Addr;
+
+ // Output data length in bytes, equal to the cipher text length.
+ HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = channel1Length;
+ }
+}
+
+//*****************************************************************************
+//
+// Poll the IRQ status register and return.
+//
+//*****************************************************************************
+uint32_t AESWaitForIRQFlags(uint32_t irqFlags)
+{
+ uint32_t irqTrigger = 0;
+ // Wait for the DMA operation to complete. Add a delay to make sure we are
+ // not flooding the bus with requests too much.
+ do {
+ CPUdelay(1);
+ }
+ while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & irqFlags & (CRYPTO_IRQSTAT_DMA_IN_DONE_M |
+ CRYPTO_IRQSTAT_RESULT_AVAIL_M |
+ CRYPTO_IRQSTAT_DMA_BUS_ERR_M |
+ CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M)));
+
+ // Save the IRQ trigger source
+ irqTrigger = HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & irqFlags;
+
+ // Clear IRQ flags
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = irqTrigger;
+
+ return irqTrigger;
+}
+
+//*****************************************************************************
+//
+// Transfer a key from CM3 memory to a key store location.
+//
+//*****************************************************************************
+uint32_t AESWriteToKeyStore(const uint8_t *aesKey, uint32_t aesKeyLength, uint32_t keyStoreArea)
+{
+ // Check the arguments.
+ ASSERT((keyStoreArea == AES_KEY_AREA_0) ||
+ (keyStoreArea == AES_KEY_AREA_1) ||
+ (keyStoreArea == AES_KEY_AREA_2) ||
+ (keyStoreArea == AES_KEY_AREA_3) ||
+ (keyStoreArea == AES_KEY_AREA_4) ||
+ (keyStoreArea == AES_KEY_AREA_5) ||
+ (keyStoreArea == AES_KEY_AREA_6) ||
+ (keyStoreArea == AES_KEY_AREA_7));
+
+ ASSERT((aesKeyLength == AES_128_KEY_LENGTH_BYTES) ||
+ (aesKeyLength == AES_192_KEY_LENGTH_BYTES) ||
+ (aesKeyLength == AES_256_KEY_LENGTH_BYTES));
+
+ uint32_t keySize = 0;
+
+ switch (aesKeyLength) {
+ case AES_128_KEY_LENGTH_BYTES:
+ keySize = CRYPTO_KEYSIZE_SIZE_128_BIT;
+ break;
+ case AES_192_KEY_LENGTH_BYTES:
+ keySize = CRYPTO_KEYSIZE_SIZE_192_BIT;
+ break;
+ case AES_256_KEY_LENGTH_BYTES:
+ keySize = CRYPTO_KEYSIZE_SIZE_256_BIT;
+ break;
+ }
+
+ // Clear any previously written key at the keyLocation
+ AESInvalidateKey(keyStoreArea);
+
+ // Disable the external interrupt to stop the interrupt form propagating
+ // from the module to the System CPU.
+ IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ);
+
+ // Enable internal interrupts.
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL_M;
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE_M | CRYPTO_IRQEN_RESULT_AVAIL_M;
+
+ // Configure master control module.
+ HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_KEY_STORE;
+
+ // Clear any outstanding events.
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | CRYPTO_IRQCLR_RESULT_AVAIL);
+
+ // Configure the size of keys contained within the key store
+ // Do not write to the register if the correct key size is already set.
+ // Writing to this register causes all current keys to be invalidated.
+ uint32_t keyStoreKeySize = HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE);
+ if (keySize != keyStoreKeySize) {
+ HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE) = keySize;
+ }
+
+ // Enable key to write (e.g. Key 0).
+ HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITEAREA) = 1 << keyStoreArea;
+
+ // Total key length in bytes (16 for 1 x 128-bit key and 32 for 1 x 256-bit key).
+ AESStartDMAOperation(aesKey, aesKeyLength, 0, 0);
+
+ // Wait for the DMA operation to complete.
+ uint32_t irqTrigger = AESWaitForIRQFlags(CRYPTO_IRQCLR_RESULT_AVAIL | CRYPTO_IRQCLR_DMA_IN_DONE | CRYPTO_IRQSTAT_DMA_BUS_ERR | CRYPTO_IRQSTAT_KEY_ST_WR_ERR);
+
+ // Re-enable interrupts globally.
+ IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ);
+ IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ);
+
+ // If we had a bus error or the key is not in the CRYPTO_O_KEYWRITTENAREA, return an error.
+ if ((irqTrigger & (CRYPTO_IRQSTAT_DMA_BUS_ERR_M | CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M)) || !(HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) & (1 << keyStoreArea))) {
+ // There was an error in writing to the keyStore.
+ return AES_KEYSTORE_ERROR;
+ }
+ else {
+ return AES_SUCCESS;
+ }
+}
+
+//*****************************************************************************
+//
+// Transfer a key from the keyStoreArea to the internal buffer of the module.
+//
+//*****************************************************************************
+uint32_t AESReadFromKeyStore(uint32_t keyStoreArea)
+{
+ // Check the arguments.
+ ASSERT((keyStoreArea == AES_KEY_AREA_0) ||
+ (keyStoreArea == AES_KEY_AREA_1) ||
+ (keyStoreArea == AES_KEY_AREA_2) ||
+ (keyStoreArea == AES_KEY_AREA_3) ||
+ (keyStoreArea == AES_KEY_AREA_4) ||
+ (keyStoreArea == AES_KEY_AREA_5) ||
+ (keyStoreArea == AES_KEY_AREA_6) ||
+ (keyStoreArea == AES_KEY_AREA_7));
+
+ // Check if there is a valid key in the specified keyStoreArea
+ if (!(HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) & (1 << keyStoreArea))) {
+ return AES_KEYSTORE_AREA_INVALID;
+ }
+
+ // Enable keys to read (e.g. Key 0).
+ HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = keyStoreArea;
+
+ // Wait until key is loaded to the AES module.
+ // We cannot simply poll the IRQ status as only an error is communicated through
+ // the IRQ status and not the completion of the transfer.
+ do {
+ CPUdelay(1);
+ }
+ while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY_M));
+
+ // Check for keyStore read error.
+ if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_IRQSTAT_KEY_ST_RD_ERR_M)) {
+ return AES_KEYSTORE_ERROR;
+ }
+ else {
+ return AES_SUCCESS;
+ }
+}
+
+//*****************************************************************************
+//
+// Read the tag after a completed CCM, GCM, or CBC-MAC operation.
+//
+//*****************************************************************************
+uint32_t AESReadTag(uint8_t *tag, uint32_t tagLength)
+{
+ // The intermediate array is used instead of a caller-provided one
+ // to enable a simple API with no unintuitive alignment or size requirements.
+ // This is a trade-off of stack-depth vs ease-of-use that came out on the
+ // ease-of-use side.
+ uint32_t computedTag[AES_BLOCK_SIZE / sizeof(uint32_t)];
+
+ // Wait until the computed tag is ready.
+ while (!(HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) & CRYPTO_AESCTL_SAVED_CONTEXT_RDY_M));
+
+ // Read computed tag out from the HW registers
+ // Need to read out all 128 bits in four reads to correctly clear CRYPTO_AESCTL_SAVED_CONTEXT_RDY flag
+ computedTag[0] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT0);
+ computedTag[1] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT1);
+ computedTag[2] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT2);
+ computedTag[3] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT3);
+
+ memcpy(tag, computedTag, tagLength);
+
+ return AES_SUCCESS;
+}
+
+//*****************************************************************************
+//
+// Verify the provided tag against the computed tag after a completed CCM or
+// GCM operation.
+//
+//*****************************************************************************
+uint32_t AESVerifyTag(const uint8_t *tag, uint32_t tagLength)
+{
+ uint32_t resultStatus;
+ // The intermediate array is allocated on the stack to ensure users do not
+ // point the tag they provide and the one computed at the same location.
+ // That would cause memcmp to compare an array against itself. We could add
+ // a check that verifies that the arrays are not the same. If we did that and
+ // modified AESReadTag to just copy all 128 bits into a provided array,
+ // we could save 16 bytes of stack space while making the API much more
+ // complicated.
+ uint8_t computedTag[AES_BLOCK_SIZE];
+
+ resultStatus = AESReadTag(computedTag, tagLength);
+
+ if (resultStatus != AES_SUCCESS) {
+ return resultStatus;
+ }
+
+ resultStatus = memcmp(computedTag, tag, tagLength);
+
+ if (resultStatus != 0) {
+ return AES_TAG_VERIFICATION_FAILED;
+ }
+
+ return AES_SUCCESS;
+}
+
+//*****************************************************************************
+//
+// Configure the AES module for CCM mode
+//
+//*****************************************************************************
+void AESConfigureCCMCtrl(uint32_t nonceLength, uint32_t macLength, bool encrypt)
+{
+ uint32_t ctrlVal = 0;
+
+ ctrlVal = ((15 - nonceLength - 1) << CRYPTO_AESCTL_CCM_L_S);
+ if ( macLength >= 2 ) {
+ ctrlVal |= ((( macLength - 2 ) >> 1 ) << CRYPTO_AESCTL_CCM_M_S );
+ }
+ ctrlVal |= CRYPTO_AESCTL_CCM |
+ CRYPTO_AESCTL_CTR |
+ CRYPTO_AESCTL_SAVE_CONTEXT |
+ CRYPTO_AESCTL_CTR_WIDTH_128_BIT;
+ ctrlVal |= encrypt ? CRYPTO_AESCTL_DIR : 0;
+
+ AESSetCtrl(ctrlVal);
+}
+
+//*****************************************************************************
+//
+// Configure an IV for CCM mode of operation
+//
+//*****************************************************************************
+void AESWriteCCMInitializationVector(const uint8_t *nonce, uint32_t nonceLength)
+{
+ union {
+ uint32_t word[4];
+ uint8_t byte[16];
+ } initializationVector = {{0}};
+
+ initializationVector.byte[0] = 15 - nonceLength - 1;
+
+ memcpy(&(initializationVector.byte[1]), nonce, nonceLength);
+
+ AESSetInitializationVector(initializationVector.word);
+}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aes.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aes.h
new file mode 100644
index 0000000..f1ac452
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aes.h
@@ -0,0 +1,843 @@
+/******************************************************************************
+* Filename: aes.h
+* Revised: 2019-01-25 14:45:16 +0100 (Fri, 25 Jan 2019)
+* Revision: 54287
+*
+* Description: AES header file.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup peripheral_group
+//! @{
+//! \addtogroup aes_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __AES_H__
+#define __AES_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+#include "../inc/hw_types.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_ints.h"
+#include "../inc/hw_crypto.h"
+#include "debug.h"
+#include "interrupt.h"
+#include "cpu.h"
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// This section renames all functions that are not "static inline", so that
+// calling these functions will default to implementation in flash. At the end
+// of this file a second renaming will change the defaults to implementation in
+// ROM for available functions.
+//
+// To force use of the implementation in flash, e.g. for debugging:
+// - Globally: Define DRIVERLIB_NOROM at project level
+// - Per function: Use prefix "NOROM_" when calling the function
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #define AESStartDMAOperation NOROM_AESStartDMAOperation
+ #define AESSetInitializationVector NOROM_AESSetInitializationVector
+ #define AESWriteCCMInitializationVector NOROM_AESWriteCCMInitializationVector
+ #define AESReadTag NOROM_AESReadTag
+ #define AESVerifyTag NOROM_AESVerifyTag
+ #define AESWriteToKeyStore NOROM_AESWriteToKeyStore
+ #define AESReadFromKeyStore NOROM_AESReadFromKeyStore
+ #define AESWaitForIRQFlags NOROM_AESWaitForIRQFlags
+ #define AESConfigureCCMCtrl NOROM_AESConfigureCCMCtrl
+#endif
+
+
+//*****************************************************************************
+//
+// Values that can be passed to AESIntEnable, AESIntDisable, and AESIntClear
+// as the intFlags parameter, and returned from AESIntStatus.
+// Only AES_DMA_IN_DONE and AES_RESULT_RDY are routed to the NVIC. Check each
+// function to see if it supports other interrupt status flags.
+//
+//*****************************************************************************
+#define AES_DMA_IN_DONE CRYPTO_IRQEN_DMA_IN_DONE_M
+#define AES_RESULT_RDY CRYPTO_IRQEN_RESULT_AVAIL_M
+#define AES_DMA_BUS_ERR CRYPTO_IRQCLR_DMA_BUS_ERR_M
+#define AES_KEY_ST_WR_ERR CRYPTO_IRQCLR_KEY_ST_WR_ERR_M
+#define AES_KEY_ST_RD_ERR CRYPTO_IRQCLR_KEY_ST_RD_ERR_M
+
+
+//*****************************************************************************
+//
+// General constants
+//
+//*****************************************************************************
+
+// AES module return codes
+#define AES_SUCCESS 0
+#define AES_KEYSTORE_ERROR 1
+#define AES_KEYSTORE_AREA_INVALID 2
+#define AES_DMA_BUSY 3
+#define AES_DMA_ERROR 4
+#define AES_TAG_NOT_READY 5
+#define AES_TAG_VERIFICATION_FAILED 6
+
+// Key store module defines
+#define AES_IV_LENGTH_BYTES 16
+#define AES_TAG_LENGTH_BYTES 16
+#define AES_128_KEY_LENGTH_BYTES (128 / 8)
+#define AES_192_KEY_LENGTH_BYTES (192 / 8)
+#define AES_256_KEY_LENGTH_BYTES (256 / 8)
+
+#define AES_BLOCK_SIZE 16
+
+// DMA status codes
+#define AES_DMA_CHANNEL0_ACTIVE CRYPTO_DMASTAT_CH0_ACT_M
+#define AES_DMA_CHANNEL1_ACTIVE CRYPTO_DMASTAT_CH1_ACT_M
+#define AES_DMA_PORT_ERROR CRYPTO_DMASTAT_PORT_ERR_M
+
+// Crypto module operation types
+#define AES_ALGSEL_AES CRYPTO_ALGSEL_AES_M
+#define AES_ALGSEL_KEY_STORE CRYPTO_ALGSEL_KEY_STORE_M
+#define AES_ALGSEL_TAG CRYPTO_ALGSEL_TAG_M
+
+
+//*****************************************************************************
+//
+// For 128-bit keys, all 8 key area locations from 0 to 7 are valid.
+// A 256-bit key requires two consecutive Key Area locations. The base key area
+// may be odd. Do not attempt to write a 256-bit key to AES_KEY_AREA_7.
+//
+//*****************************************************************************
+#define AES_KEY_AREA_0 0
+#define AES_KEY_AREA_1 1
+#define AES_KEY_AREA_2 2
+#define AES_KEY_AREA_3 3
+#define AES_KEY_AREA_4 4
+#define AES_KEY_AREA_5 5
+#define AES_KEY_AREA_6 6
+#define AES_KEY_AREA_7 7
+
+//*****************************************************************************
+//
+// Defines for the AES-CTR mode counter width
+//
+//*****************************************************************************
+#define AES_CTR_WIDTH_32 0x0
+#define AES_CTR_WIDTH_64 0x1
+#define AES_CTR_WIDTH_96 0x2
+#define AES_CTR_WIDTH_128 0x3
+
+//*****************************************************************************
+//
+// API Functions and prototypes
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \brief Start a crypto DMA operation
+//!
+//! Enable the crypto DMA channels, configure the channel addresses,
+//! and set the length of the data transfer.
+//! Setting the length of the data transfer automatically starts the
+//! transfer. It is also used by the hardware module as a signal to
+//! begin the encryption, decryption, or MAC operation.
+//!
+//! \param [in] channel0Addr A pointer to the address channel 0 shall use.
+//!
+//! \param [in] channel0Length Length of the data in bytes to be read from or
+//! written to at channel0Addr. Set to 0 to not set up
+//! this channel. Permitted ranges are mode dependent
+//! and displayed below.
+//! - ECB: [16]
+//! - CBC: [1, sizeof(RAM)]
+//! - CBC-MAC: [1, sizeof(RAM)]
+//! - CCM: [1, sizeof(RAM)]
+//!
+//! \param [out] channel1Addr A pointer to the address channel 1 shall use.
+//!
+//! \param [in] channel1Length Length of the data in bytes to be read from or
+//! written to at channel1Addr. Set to 0 to not set up
+//! this channel.Permitted ranges are mode dependent
+//! and displayed below.
+//! - ECB: [16]
+//! - CBC: [1, sizeof(RAM)]
+//! - CBC-MAC: [1, sizeof(RAM)]
+//! - CCM: [1, sizeof(RAM)]
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void AESStartDMAOperation(const uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length);
+
+//*****************************************************************************
+//
+//! \brief Write the initialization vector (IV) to the crypto module.
+//!
+//! Depending on the mode of operation, the tag must be constructed
+//! differently:
+//! - CBC: No special care must be taken. Any 128-bit IV
+//! (initialization vector) will suffice.
+//! - CBC-MAC: IV's must be all 0's.
+//! - CCM: Only 12 and 13 byte IV's are permitted. See code
+//! below for formatting.
+//! \code
+//! uint8_t initVectorLength = 12; // Could also be 13
+//!
+//! union {
+//! uint32_t word[4];
+//! uint8_t byte[16];
+//! } initVector;
+//!
+//! uint8_t initVectorUnformatted[initVectorLength];
+//!
+//! // This is the same field length value that is written to the ctrl register
+//! initVector.byte[0] = L - 1;
+//!
+//! memcpy(&initVector.byte[1], initVectorUnformatted, initVectorLength);
+//!
+//! // Fill the remaining bytes with zeros
+//! for (initVectorLength++; initVectorLength < sizeof(initVector.byte); initVectorLength++) {
+//! initVector.byte[initVectorLength] = 0;
+//! }
+//! \endcode
+//!
+//! \param [in] initializationVector Pointer to an array with four 32-bit elements
+//! to be used as initialization vector.
+//! Elements of array must be word aligned in memory.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void AESSetInitializationVector(const uint32_t *initializationVector);
+
+//*****************************************************************************
+//
+//! \brief Generate and load the initialization vector for a CCM operation.
+//!
+//!
+//! \param [in] nonce Pointer to a nonce of length \c nonceLength.
+//!
+//! \param [in] nonceLength Number of bytes to copy from \c nonce when creating
+//! the CCM IV. The L-value is also derived from it.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void AESWriteCCMInitializationVector(const uint8_t *nonce, uint32_t nonceLength);
+
+//*****************************************************************************
+//
+//! \brief Read the tag out from the crypto module.
+//!
+//! This function copies the \c tagLength bytes from the tag calculated by the
+//! crypto module in CCM, GCM, or CBC-MAC mode to \c tag.
+//!
+//! \param [out] tag Pointer to an array of \c tagLength bytes.
+//!
+//! \param [in] tagLength Number of bytes to copy to \c tag.
+//!
+//! \return Returns a status code depending on the result of the transfer.
+//! - \ref AES_TAG_NOT_READY if the tag is not ready yet
+//! - \ref AES_SUCCESS otherwise
+//
+//*****************************************************************************
+extern uint32_t AESReadTag(uint8_t *tag, uint32_t tagLength);
+
+//*****************************************************************************
+//
+//! \brief Verifies the provided \c tag against calculated one
+//!
+//! This function compares the provided tag against the tag calculated by the
+//! crypto module during the last CCM, GCM, or CBC-MAC
+//!
+//! This function copies the \c tagLength bytes from the tag calculated by the
+//! crypto module in CCM, GCM, or CBC-MAC mode to \c tag.
+//!
+//! \param [in] tag Pointer to an array of \c tagLength bytes.
+//!
+//! \param [in] tagLength Number of bytes to compare.
+//!
+//! \return Returns a status code depending on the result of the transfer.
+//! - \ref AES_TAG_VERIFICATION_FAILED if the verification failed
+//! - \ref AES_SUCCESS otherwise
+//
+//*****************************************************************************
+extern uint32_t AESVerifyTag(const uint8_t *tag, uint32_t tagLength);
+
+//*****************************************************************************
+//
+//! \brief Transfer a key from main memory to a key area within the key store.
+//!
+//! The crypto DMA transfers the key and function does not return until
+//! the operation completes.
+//! The keyStore can only contain valid keys of one \c aesKeyLength at
+//! any one point in time. The keyStore cannot contain both 128-bit and
+//! 256-bit keys simultaneously. When a key of a different \c aesKeyLength
+//! from the previous \c aesKeyLength is loaded, all previous keys are
+//! invalidated.
+//!
+//! \param [in] aesKey Pointer to key. Does not need to be word-aligned.
+//!
+//! \param [in] aesKeyLength The key size in bytes. Currently, 128-bit, 192-bit,
+//! and 256-bit keys are supported.
+//! - \ref AES_128_KEY_LENGTH_BYTES
+//! - \ref AES_192_KEY_LENGTH_BYTES
+//! - \ref AES_256_KEY_LENGTH_BYTES
+//!
+//! \param [in] keyStoreArea The key store area to transfer the key to.
+//! When using 128-bit keys, only the specified key store
+//! area will be occupied.
+//! When using 256-bit or 192-bit keys, two consecutive key areas
+//! are used to store the key.
+//! - \ref AES_KEY_AREA_0
+//! - \ref AES_KEY_AREA_1
+//! - \ref AES_KEY_AREA_2
+//! - \ref AES_KEY_AREA_3
+//! - \ref AES_KEY_AREA_4
+//! - \ref AES_KEY_AREA_5
+//! - \ref AES_KEY_AREA_6
+//! - \ref AES_KEY_AREA_7
+//!
+//! When using 256-bit or 192-bit keys, the 8 \c keyStoreArea's are
+//! split into four sets of two. Selecting any \c keyStoreArea automatically
+//! occupies the second \c keyStoreArea of the tuples below:
+//!
+//! - (\ref AES_KEY_AREA_0, \ref AES_KEY_AREA_1)
+//! - (\ref AES_KEY_AREA_2, \ref AES_KEY_AREA_3)
+//! - (\ref AES_KEY_AREA_4, \ref AES_KEY_AREA_5)
+//! - (\ref AES_KEY_AREA_6, \ref AES_KEY_AREA_7)
+//!
+//! For example: if \c keyStoreArea == \ref AES_KEY_AREA_2,
+//! both \ref AES_KEY_AREA_2 and \ref AES_KEY_AREA_3 are occupied.
+//! If \c keyStoreArea == \ref AES_KEY_AREA_5, both \ref AES_KEY_AREA_4 and \ref AES_KEY_AREA_5 are occupied.
+//!
+//! \return Returns a status code depending on the result of the transfer.
+//! If there was an error in the read process itself, an error is
+//! returned.
+//! Otherwise, a success code is returned.
+//! - \ref AES_KEYSTORE_ERROR
+//! - \ref AES_SUCCESS
+//!
+//! \sa AESReadFromKeyStore
+//
+//*****************************************************************************
+extern uint32_t AESWriteToKeyStore(const uint8_t *aesKey, uint32_t aesKeyLength, uint32_t keyStoreArea);
+
+//*****************************************************************************
+//
+//! \brief Transfer a key from key store area to the internal buffers within
+//! the hardware module.
+//!
+//! The function polls until the transfer is complete.
+//!
+//! \param [in] keyStoreArea The key store area to transfer the key from. When using
+//! 256-bit keys, either of the occupied key areas may be
+//! specified to load the key. There is no need to specify
+//! the length of the key here as the key store keeps track
+//! of how long a key associated with any valid key area is
+//! and where is starts.
+//! - \ref AES_KEY_AREA_0
+//! - \ref AES_KEY_AREA_1
+//! - \ref AES_KEY_AREA_2
+//! - \ref AES_KEY_AREA_3
+//! - \ref AES_KEY_AREA_4
+//! - \ref AES_KEY_AREA_5
+//! - \ref AES_KEY_AREA_6
+//! - \ref AES_KEY_AREA_7
+//!
+//! \return Returns a status code depending on the result of the transfer.
+//! When specifying a \c keyStoreArea value without a valid key in it an
+//! error is returned.
+//! If there was an error in the read process itself, an error is
+//! returned.
+//! Otherwise, a success code is returned.
+//! - \ref AES_KEYSTORE_AREA_INVALID
+//! - \ref AES_KEYSTORE_ERROR
+//! - \ref AES_SUCCESS
+//!
+//! \sa AESWriteToKeyStore
+//
+//*****************************************************************************
+extern uint32_t AESReadFromKeyStore(uint32_t keyStoreArea);
+
+
+//*****************************************************************************
+//
+//! \brief Poll the interrupt status register and clear when done.
+//!
+//! This function polls until one of the bits in the \c irqFlags is
+//! asserted. Only \ref AES_DMA_IN_DONE and \ref AES_RESULT_RDY can actually
+//! trigger the interrupt line. That means that one of those should
+//! always be included in \c irqFlags and will always be returned together
+//! with any error codes.
+//!
+//! \param [in] irqFlags IRQ flags to poll and mask that the status register will be
+//! masked with. May consist of any bitwise OR of the flags
+//! below that includes at least one of
+//! \ref AES_DMA_IN_DONE or \ref AES_RESULT_RDY :
+//! - \ref AES_DMA_IN_DONE
+//! - \ref AES_RESULT_RDY
+//! - \ref AES_DMA_BUS_ERR
+//! - \ref AES_KEY_ST_WR_ERR
+//! - \ref AES_KEY_ST_RD_ERR
+//!
+//! \return Returns the IRQ status register masked with \c irqFlags. May be any
+//! bitwise OR of the following masks:
+//! - \ref AES_DMA_IN_DONE
+//! - \ref AES_RESULT_RDY
+//! - \ref AES_DMA_BUS_ERR
+//! - \ref AES_KEY_ST_WR_ERR
+//! - \ref AES_KEY_ST_RD_ERR
+//
+//*****************************************************************************
+extern uint32_t AESWaitForIRQFlags(uint32_t irqFlags);
+
+//*****************************************************************************
+//
+//! \brief Configure AES engine for CCM operation.
+//!
+//! \param [in] nonceLength Length of the nonce. Must be <= 14.
+//!
+//! \param [in] macLength Length of the MAC. Must be <= 16.
+//!
+//! \param [in] encrypt Whether to set up an encrypt or decrypt operation.
+//! - true: encrypt
+//! - false: decrypt
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void AESConfigureCCMCtrl(uint32_t nonceLength, uint32_t macLength, bool encrypt);
+
+//*****************************************************************************
+//
+//! \brief Invalidate a key in the key store
+//!
+//! \param [in] keyStoreArea is the entry in the key store to invalidate. This
+//! permanently deletes the key from the key store.
+//! - \ref AES_KEY_AREA_0
+//! - \ref AES_KEY_AREA_1
+//! - \ref AES_KEY_AREA_2
+//! - \ref AES_KEY_AREA_3
+//! - \ref AES_KEY_AREA_4
+//! - \ref AES_KEY_AREA_5
+//! - \ref AES_KEY_AREA_6
+//! - \ref AES_KEY_AREA_7
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void AESInvalidateKey(uint32_t keyStoreArea)
+{
+ ASSERT((keyStoreArea == AES_KEY_AREA_0) ||
+ (keyStoreArea == AES_KEY_AREA_1) ||
+ (keyStoreArea == AES_KEY_AREA_2) ||
+ (keyStoreArea == AES_KEY_AREA_3) ||
+ (keyStoreArea == AES_KEY_AREA_4) ||
+ (keyStoreArea == AES_KEY_AREA_5) ||
+ (keyStoreArea == AES_KEY_AREA_6) ||
+ (keyStoreArea == AES_KEY_AREA_7));
+
+ // Clear any previously written key at the key location
+ HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) = (0x00000001 << keyStoreArea);
+}
+
+//*****************************************************************************
+//
+//! \brief Select type of operation
+//!
+//! \param [in] algorithm Flags that specify which type of operation the crypto
+//! module shall perform. The flags are mutually exclusive.
+//! - 0 : Reset the module
+//! - \ref AES_ALGSEL_AES
+//! - \ref AES_ALGSEL_TAG
+//! - \ref AES_ALGSEL_KEY_STORE
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void AESSelectAlgorithm(uint32_t algorithm)
+{
+ ASSERT((algorithm == AES_ALGSEL_AES) ||
+ (algorithm == AES_ALGSEL_AES | AES_ALGSEL_TAG) ||
+ (algorithm == AES_ALGSEL_KEY_STORE));
+
+ HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = algorithm;
+}
+
+//*****************************************************************************
+//
+//! \brief Set up the next crypto module operation.
+//!
+//! The function uses a bitwise OR of the fields within the CRYPTO_O_AESCTL
+//! register. The relevant field names have the format:
+//! - CRYPTO_AESCTL_[field name]
+//!
+//! \param [in] ctrlMask Specifies which register fields shall be set.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void AESSetCtrl(uint32_t ctrlMask)
+{
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = ctrlMask;
+}
+
+//*****************************************************************************
+//
+//! \brief Specify length of the crypto operation.
+//!
+//! Despite specifying it here, the crypto DMA must still be
+//! set up with the correct data length.
+//!
+//! \param [in] length Data length in bytes. If this
+//! value is set to 0, only authentication of the AAD is
+//! performed in CCM-mode and AESWriteAuthLength() must be set to
+//! >0.
+//! Range depends on the mode:
+//! - ECB: [16]
+//! - CBC: [1, sizeof(RAM)]
+//! - CBC-MAC: [1, sizeof(RAM)]
+//! - CCM: [0, sizeof(RAM)]
+//!
+//! \return None
+//!
+//! \sa AESWriteAuthLength
+//
+//*****************************************************************************
+__STATIC_INLINE void AESSetDataLength(uint32_t length)
+{
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = length;
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0;
+}
+
+//*****************************************************************************
+//
+//! \brief Specify the length of the additional authentication data (AAD).
+//!
+//! Despite specifying it here, the crypto DMA must still be set up with
+//! the correct AAD length.
+//!
+//! \param [in] length Specifies how long the AAD is in a CCM operation. In CCM mode,
+//! set this to 0 if no AAD is required. If set to 0,
+//! AESWriteDataLength() must be set to >0.
+//! Range depends on the mode:
+//! - ECB: Do not call.
+//! - CBC: [0]
+//! - CBC-MAC: [0]
+//! - CCM: [0, sizeof(RAM)]
+//!
+//! \return None
+//!
+//! \sa AESWriteDataLength
+//
+//*****************************************************************************
+__STATIC_INLINE void AESSetAuthLength(uint32_t length)
+{
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESAUTHLEN) = length;
+}
+
+//*****************************************************************************
+//
+//! \brief Reset the accelerator and cancel ongoing operations
+//!
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void AESReset(void)
+{
+ HWREG(CRYPTO_BASE + CRYPTO_O_SWRESET) = 0x00000001;
+}
+
+//*****************************************************************************
+//
+//! \brief Enable individual crypto interrupt sources.
+//!
+//! This function enables the indicated crypto interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt.
+//! Disabled sources have no effect on the processor.
+//!
+//! \param [in] intFlags is the bitwise OR of the interrupt sources to be enabled.
+//! - \ref AES_DMA_IN_DONE
+//! - \ref AES_RESULT_RDY
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void AESIntEnable(uint32_t intFlags)
+{
+ // Check the arguments.
+ ASSERT((intFlags & AES_DMA_IN_DONE) ||
+ (intFlags & AES_RESULT_RDY));
+
+ // Using level interrupt.
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL_M;
+
+ // Enable the specified interrupts.
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) |= intFlags;
+}
+
+//*****************************************************************************
+//
+//! \brief Disable individual crypto interrupt sources.
+//!
+//! This function disables the indicated crypto interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt.
+//! Disabled sources have no effect on the processor.
+//!
+//! \param [in] intFlags is the bitwise OR of the interrupt sources to be enabled.
+//! - \ref AES_DMA_IN_DONE
+//! - \ref AES_RESULT_RDY
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void AESIntDisable(uint32_t intFlags)
+{
+ // Check the arguments.
+ ASSERT((intFlags & AES_DMA_IN_DONE) ||
+ (intFlags & AES_RESULT_RDY));
+
+ // Disable the specified interrupts.
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~intFlags;
+}
+
+//*****************************************************************************
+//
+//! \brief Get the current masked interrupt status.
+//!
+//! This function returns the masked interrupt status of the crypto module.
+//!
+//! \return Returns the status of the masked lines when enabled:
+//! - \ref AES_DMA_IN_DONE
+//! - \ref AES_RESULT_RDY
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t AESIntStatusMasked(void)
+{
+ uint32_t mask;
+
+ // Return the masked interrupt status
+ mask = HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN);
+ return(mask & HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT));
+}
+
+//*****************************************************************************
+//
+//! \brief Get the current raw interrupt status.
+//!
+//! This function returns the raw interrupt status of the crypto module.
+//! It returns both the status of the lines routed to the NVIC as well as the
+//! error flags.
+//!
+//! \return Returns the raw interrupt status:
+//! - \ref AES_DMA_IN_DONE
+//! - \ref AES_RESULT_RDY
+//! - \ref AES_DMA_BUS_ERR
+//! - \ref AES_KEY_ST_WR_ERR
+//! - \ref AES_KEY_ST_RD_ERR
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t AESIntStatusRaw(void)
+{
+ // Return either the raw interrupt status
+ return(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT));
+}
+
+//*****************************************************************************
+//
+//! \brief Clear crypto interrupt sources.
+//!
+//! The specified crypto interrupt sources are cleared, so that they no longer
+//! assert. This function must be called in the interrupt handler to keep the
+//! interrupt from being recognized again immediately upon exit.
+//!
+//! \note Due to write buffers and synchronizers in the system it may take several
+//! clock cycles from a register write clearing an event in the module until the
+//! event is actually cleared in the NVIC of the system CPU. It is recommended to
+//! clear the event source early in the interrupt service routine (ISR) to allow
+//! the event clear to propagate to the NVIC before returning from the ISR.
+//!
+//! \param [in] intFlags is a bit mask of the interrupt sources to be cleared.
+//! - \ref AES_DMA_IN_DONE
+//! - \ref AES_RESULT_RDY
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void AESIntClear(uint32_t intFlags)
+{
+ // Check the arguments.
+ ASSERT((intFlags & AES_DMA_IN_DONE) ||
+ (intFlags & AES_RESULT_RDY));
+
+ // Clear the requested interrupt sources,
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = intFlags;
+}
+
+//*****************************************************************************
+//
+//! \brief Register an interrupt handler for a crypto interrupt.
+//!
+//! This function does the actual registering of the interrupt handler. This
+//! function enables the global interrupt in the interrupt controller; specific
+//! crypto interrupts must be enabled via \ref AESIntEnable(). It is the interrupt
+//! handler's responsibility to clear the interrupt source.
+//!
+//! \param handlerFxn is a pointer to the function to be called when the
+//! crypto interrupt occurs.
+//!
+//! \return None
+//!
+//! \sa \ref IntRegister() for important information about registering interrupt
+//! handlers.
+//
+//*****************************************************************************
+__STATIC_INLINE void AESIntRegister(void (*handlerFxn)(void))
+{
+ // Register the interrupt handler.
+ IntRegister(INT_CRYPTO_RESULT_AVAIL_IRQ, handlerFxn);
+
+ // Enable the crypto interrupt.
+ IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ);
+}
+
+//*****************************************************************************
+//
+//! \brief Unregister an interrupt handler for a crypto interrupt.
+//!
+//! This function does the actual unregistering of the interrupt handler. It
+//! clears the handler called when a crypto interrupt occurs. This
+//! function also masks off the interrupt in the interrupt controller so that
+//! the interrupt handler no longer is called.
+//!
+//! \return None
+//!
+//! \sa \ref IntRegister() for important information about registering interrupt
+//! handlers.
+//
+//*****************************************************************************
+__STATIC_INLINE void AESIntUnregister(void)
+{
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(INT_CRYPTO_RESULT_AVAIL_IRQ);
+}
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// Redirect to implementation in ROM when available.
+//
+//*****************************************************************************
+#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
+ #include "../driverlib/rom.h"
+ #ifdef ROM_AESStartDMAOperation
+ #undef AESStartDMAOperation
+ #define AESStartDMAOperation ROM_AESStartDMAOperation
+ #endif
+ #ifdef ROM_AESSetInitializationVector
+ #undef AESSetInitializationVector
+ #define AESSetInitializationVector ROM_AESSetInitializationVector
+ #endif
+ #ifdef ROM_AESWriteCCMInitializationVector
+ #undef AESWriteCCMInitializationVector
+ #define AESWriteCCMInitializationVector ROM_AESWriteCCMInitializationVector
+ #endif
+ #ifdef ROM_AESReadTag
+ #undef AESReadTag
+ #define AESReadTag ROM_AESReadTag
+ #endif
+ #ifdef ROM_AESVerifyTag
+ #undef AESVerifyTag
+ #define AESVerifyTag ROM_AESVerifyTag
+ #endif
+ #ifdef ROM_AESWriteToKeyStore
+ #undef AESWriteToKeyStore
+ #define AESWriteToKeyStore ROM_AESWriteToKeyStore
+ #endif
+ #ifdef ROM_AESReadFromKeyStore
+ #undef AESReadFromKeyStore
+ #define AESReadFromKeyStore ROM_AESReadFromKeyStore
+ #endif
+ #ifdef ROM_AESWaitForIRQFlags
+ #undef AESWaitForIRQFlags
+ #define AESWaitForIRQFlags ROM_AESWaitForIRQFlags
+ #endif
+ #ifdef ROM_AESConfigureCCMCtrl
+ #undef AESConfigureCCMCtrl
+ #define AESConfigureCCMCtrl ROM_AESConfigureCCMCtrl
+ #endif
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __AES_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aes_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aes_doc.h
new file mode 100644
index 0000000..6d156a4
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aes_doc.h
@@ -0,0 +1,66 @@
+/******************************************************************************
+* Filename: aes_doc.h
+* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017)
+* Revision: 49096
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+//! \addtogroup aes_api
+//! @{
+//! \section sec_aes Introduction
+//!
+//! The AES (advanced encryption standard) API provides access to the AES and key
+//! store functionality of the crypto core. The SHA2 accelerator is also
+//! contained within the crypto core. Hence, only one of SHA2 and AES may be
+//! used at the same time.
+//! This module offers hardware acceleration for several protocols using the
+//! AES block cypher. The protocols below are supported by the hardware. The
+//! driverlib documentation only explicitly references the most commonly used ones.
+//! - ECB
+//! - CBC
+//! - CCM
+//! - CBC-MAC
+//! - GCM
+//!
+//! The key store is a section of crypto memory that is only accessible to the crypto module
+//! and may be written to by the application via the crypto DMA. It is not possible to
+//! read from the key store to main memory. Thereby, it is not possible to
+//! compromise the key should the application be hacked if the original key in main
+//! memory was overwritten already.
+//!
+//! The crypto core does not have retention and all configuration settings and
+//! keys in the keystore are lost when going into standby or shutdown.
+//! The typical security advantages a key store offers are not available in these
+//! low power modes as the key must be saved in regular memory to reload
+//! it after going into standby or shutdown.
+//! Consequently, the keystore primarily serves as an interface to the AES accelerator.
+//!
+//! @}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_batmon.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_batmon.c
new file mode 100644
index 0000000..de80801
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_batmon.c
@@ -0,0 +1,80 @@
+/******************************************************************************
+* Filename: aon_batmon.c
+* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016)
+* Revision: 47343
+*
+* Description: Driver for the AON Battery and Temperature Monitor
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "aon_batmon.h"
+#include "../inc/hw_fcfg1.h"
+
+//*****************************************************************************
+//
+// Handle support for DriverLib in ROM:
+// This section will undo prototype renaming made in the header file
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #undef AONBatMonTemperatureGetDegC
+ #define AONBatMonTemperatureGetDegC NOROM_AONBatMonTemperatureGetDegC
+#endif
+
+//*****************************************************************************
+//
+// AONBatMonTemperatureGetDegC()
+// Returns sign extended temperature in Deg C (-256 .. +255)
+//
+//*****************************************************************************
+int32_t
+AONBatMonTemperatureGetDegC( void )
+{
+ int32_t signedTemp ; // Signed extended temperature with 8 fractional bits
+ int32_t tempCorrection ; // Voltage dependent temp correction with 8 fractional bits
+ int8_t voltageSlope ; // Signed byte value representing the TEMP slope with battery voltage, in degrees C/V, with 4 fractional bits.
+
+ // Shift left then right to sign extend the BATMON_TEMP field
+ signedTemp = ((((int32_t)HWREG( AON_BATMON_BASE + AON_BATMON_O_TEMP ))
+ << ( 32 - AON_BATMON_TEMP_INT_W - AON_BATMON_TEMP_INT_S ))
+ >> ( 32 - AON_BATMON_TEMP_INT_W - AON_BATMON_TEMP_INT_S ));
+
+ // Typecasting voltageSlope to int8_t prior to assignment in order to make sure sign extension works properly
+ // Using byte read (HWREGB) in order to make more efficient code since voltageSlope is assigned to bits[7:0] of FCFG1_O_MISC_TRIM
+ voltageSlope = ((int8_t)HWREGB( FCFG1_BASE + FCFG1_O_MISC_TRIM ));
+ tempCorrection = (( voltageSlope * (((int32_t)HWREG( AON_BATMON_BASE + AON_BATMON_O_BAT )) - 0x300 )) >> 4 );
+
+ return ((( signedTemp - tempCorrection ) + 0x80 ) >> 8 );
+}
+
+
+// See aon_batmon.h for implementation of remaining functions
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_batmon.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_batmon.h
new file mode 100644
index 0000000..3a9b1ad
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_batmon.h
@@ -0,0 +1,306 @@
+/******************************************************************************
+* Filename: aon_batmon.h
+* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016)
+* Revision: 47343
+*
+* Description: Defines and prototypes for the AON Battery and Temperature
+* Monitor
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup aon_group
+//! @{
+//! \addtogroup aonbatmon_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __AON_BATMON_H__
+#define __AON_BATMON_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "../inc/hw_types.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_aon_batmon.h"
+#include "debug.h"
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// This section renames all functions that are not "static inline", so that
+// calling these functions will default to implementation in flash. At the end
+// of this file a second renaming will change the defaults to implementation in
+// ROM for available functions.
+//
+// To force use of the implementation in flash, e.g. for debugging:
+// - Globally: Define DRIVERLIB_NOROM at project level
+// - Per function: Use prefix "NOROM_" when calling the function
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #define AONBatMonTemperatureGetDegC NOROM_AONBatMonTemperatureGetDegC
+#endif
+
+
+//*****************************************************************************
+//
+// API Functions and prototypes
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \brief Enable the temperature and battery monitoring.
+//!
+//! This function will enable the measurements of the temperature and the
+//! battery voltage.
+//!
+//! To speed up the measurement of the levels the measurement can be enabled
+//! before configuring the battery and temperature settings. When all of the
+//! AON_BATMON registers are configured, the calculation of the voltage and
+//! temperature values can be enabled (the measurement will now take
+//! effect/propagate to other blocks).
+//!
+//! It is possible to enable both at the same time, after the AON_BATMON
+//! registers are configured, but then the first values will be ready at a
+//! later point compared to the scenario above.
+//!
+//! \note Temperature and battery voltage measurements are not done in
+//! parallel. The measurement cycle is controlled by a hardware Finite State
+//! Machine. First the temperature and then the battery voltage each taking
+//! one cycle to complete. However, if the comparator measuring the battery
+//! voltage detects a change on the reference value, a new measurement of the
+//! battery voltage only is performed immediately after. This has no impact on
+//! the cycle count.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+AONBatMonEnable(void)
+{
+ // Enable the measurements.
+ HWREG(AON_BATMON_BASE + AON_BATMON_O_CTL) =
+ AON_BATMON_CTL_CALC_EN |
+ AON_BATMON_CTL_MEAS_EN;
+}
+
+//*****************************************************************************
+//
+//! \brief Disable the temperature and battery monitoring.
+//!
+//! This function will disable the measurements of the temperature and the
+//! battery voltage.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+AONBatMonDisable(void)
+{
+ // Disable the measurements.
+ HWREG(AON_BATMON_BASE + AON_BATMON_O_CTL) = 0;
+}
+
+
+//*****************************************************************************
+//
+//! \brief Get the current temperature measurement as a signed value in Deg Celsius.
+//!
+//! This function returns an calibrated and rounded value in degree Celsius.
+//! The temperature measurements are updated every cycle.
+//!
+//! \note The temperature drifts slightly depending on the battery voltage.
+//! This function compensates for this drift and returns a calibrated temperature.
+//!
+//! \note Use the function AONBatMonNewTempMeasureReady() to test for a new measurement.
+//!
+//! \return Returns signed integer part of temperature in Deg C (-256 .. +255)
+//!
+//! \sa AONBatMonNewTempMeasureReady()
+//
+//*****************************************************************************
+extern int32_t AONBatMonTemperatureGetDegC( void );
+
+//*****************************************************************************
+//
+//! \brief Get the battery monitor measurement.
+//!
+//! This function will return the current battery monitor measurement.
+//! The battery voltage measurements are updated every cycle.
+//!
+//! \note The returned value is NOT sign-extended!
+//!
+//! \note Use the function \ref AONBatMonNewBatteryMeasureReady() to test for
+//! a change in measurement.
+//!
+//! \return Returns the current battery monitor value of the battery voltage
+//! measurement in a <int.frac> format size <3.8> in units of volt.
+//!
+//! \sa AONBatMonNewBatteryMeasureReady()
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+AONBatMonBatteryVoltageGet(void)
+{
+ uint32_t ui32CurrentBattery;
+
+ ui32CurrentBattery = HWREG(AON_BATMON_BASE + AON_BATMON_O_BAT);
+
+ // Return the current battery voltage measurement.
+ return (ui32CurrentBattery >> AON_BATMON_BAT_FRAC_S);
+}
+
+//*****************************************************************************
+//
+//! \brief Check if battery monitor measurement has changed.
+//!
+//! This function checks if a new battery monitor value is available. If the
+//! measurement value has \b changed since last clear the function returns \c true.
+//!
+//! If the measurement has changed the function will automatically clear the
+//! status bit.
+//!
+//! \note It is always possible to read out the current value of the
+//! battery level using AONBatMonBatteryVoltageGet() but this function can be
+//! used to check if the measurement has changed.
+//!
+//! \return Returns \c true if the measurement value has changed and \c false
+//! otherwise.
+//!
+//! \sa AONBatMonNewTempMeasureReady(), AONBatMonBatteryVoltageGet()
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+AONBatMonNewBatteryMeasureReady(void)
+{
+ bool bStatus;
+
+ // Check the status bit.
+ bStatus = HWREG(AON_BATMON_BASE + AON_BATMON_O_BATUPD) &
+ AON_BATMON_BATUPD_STAT ? true : false;
+
+ // Clear status bit if set.
+ if(bStatus)
+ {
+ HWREG(AON_BATMON_BASE + AON_BATMON_O_BATUPD) = 1;
+ }
+
+ // Return status.
+ return (bStatus);
+}
+
+//*****************************************************************************
+//
+//! \brief Check if temperature monitor measurement has changed.
+//!
+//! This function checks if a new temperature value is available. If the
+//! measurement value has \b changed since last clear the function returns \c true.
+//!
+//! If the measurement has changed the function will automatically clear the
+//! status bit.
+//!
+//! \note It is always possible to read out the current value of the
+//! temperature using \ref AONBatMonTemperatureGetDegC()
+//! but this function can be used to check if the measurement has changed.
+//!
+//! \return Returns \c true if the measurement value has changed and \c false
+//! otherwise.
+//!
+//! \sa AONBatMonNewBatteryMeasureReady(), AONBatMonTemperatureGetDegC()
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+AONBatMonNewTempMeasureReady(void)
+{
+ bool bStatus;
+
+ // Check the status bit.
+ bStatus = HWREG(AON_BATMON_BASE + AON_BATMON_O_TEMPUPD) &
+ AON_BATMON_TEMPUPD_STAT ? true : false;
+
+ // Clear status bit if set.
+ if(bStatus)
+ {
+ HWREG(AON_BATMON_BASE + AON_BATMON_O_TEMPUPD) = 1;
+ }
+
+ // Return status.
+ return (bStatus);
+}
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// Redirect to implementation in ROM when available.
+//
+//*****************************************************************************
+#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
+ #include "../driverlib/rom.h"
+ #ifdef ROM_AONBatMonTemperatureGetDegC
+ #undef AONBatMonTemperatureGetDegC
+ #define AONBatMonTemperatureGetDegC ROM_AONBatMonTemperatureGetDegC
+ #endif
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __AON_BATMON_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_event.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_event.c
new file mode 100644
index 0000000..cb699a1
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_event.c
@@ -0,0 +1,180 @@
+/******************************************************************************
+* Filename: aon_event.c
+* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017)
+* Revision: 49096
+*
+* Description: Driver for the AON Event fabric.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "aon_event.h"
+
+//*****************************************************************************
+//
+// Handle support for DriverLib in ROM:
+// This section will undo prototype renaming made in the header file
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #undef AONEventMcuWakeUpSet
+ #define AONEventMcuWakeUpSet NOROM_AONEventMcuWakeUpSet
+ #undef AONEventMcuWakeUpGet
+ #define AONEventMcuWakeUpGet NOROM_AONEventMcuWakeUpGet
+ #undef AONEventMcuSet
+ #define AONEventMcuSet NOROM_AONEventMcuSet
+ #undef AONEventMcuGet
+ #define AONEventMcuGet NOROM_AONEventMcuGet
+#endif
+
+//*****************************************************************************
+//
+// Select event source for the specified MCU wakeup programmable event
+//
+//*****************************************************************************
+void
+AONEventMcuWakeUpSet(uint32_t ui32MCUWUEvent, uint32_t ui32EventSrc)
+{
+ uint32_t ui32Shift ;
+ uint32_t ui32Mask ;
+ uint32_t ui32RegAdr ;
+
+ // Check the arguments.
+ ASSERT(( ui32MCUWUEvent >= AON_EVENT_MCU_WU0 ) && ( ui32MCUWUEvent <= AON_EVENT_MCU_WU7 ))
+ ASSERT( ui32EventSrc <= AON_EVENT_NONE );
+
+ ui32Shift = (( ui32MCUWUEvent & 3 ) << 3 );
+ ui32Mask = ( 0x3F << ui32Shift );
+ ui32RegAdr = ( AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL );
+ if ( ui32MCUWUEvent > 3 ) {
+ ui32RegAdr += 4;
+ }
+ HWREG( ui32RegAdr ) = ( HWREG( ui32RegAdr ) & ( ~ui32Mask )) | ( ui32EventSrc << ui32Shift );
+}
+
+//*****************************************************************************
+//
+// Get event source for the specified MCU wakeup programmable event
+//
+//*****************************************************************************
+uint32_t
+AONEventMcuWakeUpGet(uint32_t ui32MCUWUEvent)
+{
+ uint32_t ui32Shift ;
+ uint32_t ui32RegAdr ;
+
+ // Check the arguments.
+ ASSERT(( ui32MCUWUEvent >= AON_EVENT_MCU_WU0 ) && ( ui32MCUWUEvent <= AON_EVENT_MCU_WU7 ))
+
+ ui32Shift = (( ui32MCUWUEvent & 3 ) << 3 );
+ ui32RegAdr = ( AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL );
+ if ( ui32MCUWUEvent > 3 ) {
+ ui32RegAdr += 4;
+ }
+ return (( HWREG( ui32RegAdr ) >> ui32Shift ) & 0x3F );
+}
+
+//*****************************************************************************
+//
+// Select event source for the specified programmable event forwarded to the
+// MCU event fabric
+//
+//*****************************************************************************
+void
+AONEventMcuSet(uint32_t ui32MCUEvent, uint32_t ui32EventSrc)
+{
+ uint32_t ui32Ctrl;
+
+ // Check the arguments.
+ ASSERT((ui32MCUEvent == AON_EVENT_MCU_EVENT0) ||
+ (ui32MCUEvent == AON_EVENT_MCU_EVENT1) ||
+ (ui32MCUEvent == AON_EVENT_MCU_EVENT2));
+ ASSERT(ui32EventSrc <= AON_EVENT_NONE);
+
+ ui32Ctrl = HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL);
+
+ if(ui32MCUEvent == AON_EVENT_MCU_EVENT0)
+ {
+ ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M);
+ ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S;
+ }
+ else if(ui32MCUEvent == AON_EVENT_MCU_EVENT1)
+ {
+ ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M);
+ ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S;
+ }
+ else if(ui32MCUEvent == AON_EVENT_MCU_EVENT2)
+ {
+ ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M);
+ ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S;
+ }
+
+ HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL) = ui32Ctrl;
+}
+
+//*****************************************************************************
+//
+// Get source for the specified programmable event forwarded to the MCU event
+// fabric.
+//
+//*****************************************************************************
+uint32_t
+AONEventMcuGet(uint32_t ui32MCUEvent)
+{
+ uint32_t ui32EventSrc;
+
+ // Check the arguments.
+ ASSERT((ui32MCUEvent == AON_EVENT_MCU_EVENT0) ||
+ (ui32MCUEvent == AON_EVENT_MCU_EVENT1) ||
+ (ui32MCUEvent == AON_EVENT_MCU_EVENT2));
+
+ ui32EventSrc = HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL);
+
+ if(ui32MCUEvent == AON_EVENT_MCU_EVENT0)
+ {
+ return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M) >>
+ AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S);
+ }
+ else if(ui32MCUEvent == AON_EVENT_MCU_EVENT1)
+ {
+ return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M) >>
+ AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S);
+ }
+ else if(ui32MCUEvent == AON_EVENT_MCU_EVENT2)
+ {
+ return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M) >>
+ AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S);
+ }
+
+ // Should never get to this statement, but suppress warning.
+ ASSERT(0);
+ return(0);
+}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_event.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_event.h
new file mode 100644
index 0000000..999844a
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_event.h
@@ -0,0 +1,564 @@
+/******************************************************************************
+* Filename: aon_event.h
+* Revised: 2017-08-09 16:56:05 +0200 (Wed, 09 Aug 2017)
+* Revision: 49506
+*
+* Description: Defines and prototypes for the AON Event fabric.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup aon_group
+//! @{
+//! \addtogroup aonevent_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __AON_EVENT_H__
+#define __AON_EVENT_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "../inc/hw_types.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_aon_event.h"
+#include "debug.h"
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// This section renames all functions that are not "static inline", so that
+// calling these functions will default to implementation in flash. At the end
+// of this file a second renaming will change the defaults to implementation in
+// ROM for available functions.
+//
+// To force use of the implementation in flash, e.g. for debugging:
+// - Globally: Define DRIVERLIB_NOROM at project level
+// - Per function: Use prefix "NOROM_" when calling the function
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #define AONEventMcuWakeUpSet NOROM_AONEventMcuWakeUpSet
+ #define AONEventMcuWakeUpGet NOROM_AONEventMcuWakeUpGet
+ #define AONEventMcuSet NOROM_AONEventMcuSet
+ #define AONEventMcuGet NOROM_AONEventMcuGet
+#endif
+
+//*****************************************************************************
+//
+// Event sources for the event AON fabric.
+// Note: Events are level-triggered active high
+//
+//*****************************************************************************
+#define AON_EVENT_IOEV_MCU_WU 0 // Edge detect event from DIOs which have enabled contribution to IOEV_MCU_WU
+#define AON_EVENT_AUX_TIMER2_EV0 1 // Event 0 from AUX Timer2
+#define AON_EVENT_AUX_TIMER2_EV1 2 // Event 1 from AUX Timer2
+#define AON_EVENT_AUX_TIMER2_EV2 3 // Event 2 from AUX Timer2
+#define AON_EVENT_AUX_TIMER2_EV3 4 // Event 3 from AUX Timer2
+#define AON_EVENT_BATMON_BATT_UL 5 // BATMON event: Battery level above upper limit
+#define AON_EVENT_BATMON_BATT_LL 6 // BATMON event: Battery level below lower limit
+#define AON_EVENT_BATMON_TEMP_UL 7 // BATMON event: Temperature level above upper limit
+#define AON_EVENT_BATMON_TEMP_LL 8 // BATMON event: Temperature level below lower limit
+#define AON_EVENT_BATMON_COMBINED 9 // Combined event from BATMON
+#define AON_EVENT_IO 32 // Edge detect on any DIO. Edge detect is enabled and configured in IOC.
+ // Event ID 33 is reserved for future use
+ // Event ID 34 is reserved for future use
+#define AON_EVENT_RTC_CH0 35 // RTC channel 0
+#define AON_EVENT_RTC_CH1 36 // RTC channel 1
+#define AON_EVENT_RTC_CH2 37 // RTC channel 2
+#define AON_EVENT_RTC_CH0_DLY 38 // RTC channel 0 - delayed event
+#define AON_EVENT_RTC_CH1_DLY 39 // RTC channel 1 - delayed event
+#define AON_EVENT_RTC_CH2_DLY 40 // RTC channel 2 - delayed event
+#define AON_EVENT_RTC_COMB_DLY 41 // RTC combined delayed event
+#define AON_EVENT_RTC_UPD 42 // RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period)
+#define AON_EVENT_JTAG 43 // JTAG generated event
+#define AON_EVENT_AUX_SWEV0 44 // AUX Software triggered event #0
+#define AON_EVENT_AUX_SWEV1 45 // AUX Software triggered event #1
+#define AON_EVENT_AUX_SWEV2 46 // AUX Software triggered event #2
+#define AON_EVENT_AUX_COMPA 47 // Comparator A triggered (synchronized in AUX)
+#define AON_EVENT_AUX_COMPB 48 // Comparator B triggered (synchronized in AUX)
+#define AON_EVENT_AUX_ADC_DONE 49 // ADC conversion completed
+#define AON_EVENT_AUX_TDC_DONE 50 // TDC completed or timed out
+#define AON_EVENT_AUX_TIMER0_EV 51 // Timer 0 event
+#define AON_EVENT_AUX_TIMER1_EV 52 // Timer 1 event
+#define AON_EVENT_BATMON_TEMP 53 // BATMON temperature update event
+#define AON_EVENT_BATMON_VOLT 54 // BATMON voltage update event
+#define AON_EVENT_AUX_COMPB_ASYNC 55 // Comparator B triggered. Asynchronous signal directly from the AUX Comparator B
+#define AON_EVENT_AUX_COMPB_ASYNC_N 56 // Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B
+ // Event ID 57-62 is reserved for future use
+#define AON_EVENT_NONE 63 // No event, always low
+
+// Keeping backward compatibility until major revision number is incremented
+#define AON_EVENT_RTC0 ( AON_EVENT_RTC_CH0 )
+
+//*****************************************************************************
+//
+// Values that can be passed to AONEventMCUWakeUpSet() and returned
+// by AONEventMCUWakeUpGet().
+//
+//*****************************************************************************
+#define AON_EVENT_MCU_WU0 0 // Programmable MCU wake-up event 0
+#define AON_EVENT_MCU_WU1 1 // Programmable MCU wake-up event 1
+#define AON_EVENT_MCU_WU2 2 // Programmable MCU wake-up event 2
+#define AON_EVENT_MCU_WU3 3 // Programmable MCU wake-up event 3
+#define AON_EVENT_MCU_WU4 4 // Programmable MCU wake-up event 4
+#define AON_EVENT_MCU_WU5 5 // Programmable MCU wake-up event 5
+#define AON_EVENT_MCU_WU6 6 // Programmable MCU wake-up event 6
+#define AON_EVENT_MCU_WU7 7 // Programmable MCU wake-up event 7
+
+//*****************************************************************************
+//
+// Values that can be passed to AONEventMcuSet() and AONEventMcuGet()
+//
+//*****************************************************************************
+#define AON_EVENT_MCU_EVENT0 0 // Programmable event source fed to MCU event fabric (first of 3)
+#define AON_EVENT_MCU_EVENT1 1 // Programmable event source fed to MCU event fabric (second of 3)
+#define AON_EVENT_MCU_EVENT2 2 // Programmable event source fed to MCU event fabric (third of 3)
+
+//*****************************************************************************
+//
+// API Functions and prototypes
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \brief Select event source for the specified MCU wake-up programmable event.
+//!
+//! The AON event fabric has several programmable events that can wake up the MCU.
+//!
+//! \note The programmable event sources are effectively OR'ed together
+//! to form a single wake-up event.
+//!
+//! \param ui32MCUWUEvent is one of the programmable MCU wake-up event sources.
+//! - \ref AON_EVENT_MCU_WU0
+//! - \ref AON_EVENT_MCU_WU1
+//! - \ref AON_EVENT_MCU_WU2
+//! - \ref AON_EVENT_MCU_WU3
+//! - \ref AON_EVENT_MCU_WU4
+//! - \ref AON_EVENT_MCU_WU5
+//! - \ref AON_EVENT_MCU_WU6
+//! - \ref AON_EVENT_MCU_WU7
+//! \param ui32EventSrc is an event source for the event AON fabric.
+//! - \ref AON_EVENT_IOEV_MCU_WU : Edge detect event from DIOs which have enabled contribution to IOEV_MCU_WU
+//! - \ref AON_EVENT_AUX_TIMER2_EV0 : Event 0 from AUX Timer2
+//! - \ref AON_EVENT_AUX_TIMER2_EV1 : Event 1 from AUX Timer2
+//! - \ref AON_EVENT_AUX_TIMER2_EV2 : Event 2 from AUX Timer2
+//! - \ref AON_EVENT_AUX_TIMER2_EV3 : Event 3 from AUX Timer2
+//! - \ref AON_EVENT_BATMON_BATT_UL : BATMON event: Battery level above upper limit
+//! - \ref AON_EVENT_BATMON_BATT_LL : BATMON event: Battery level below lower limit
+//! - \ref AON_EVENT_BATMON_TEMP_UL : BATMON event: Temperature level above upper limit
+//! - \ref AON_EVENT_BATMON_TEMP_LL : BATMON event: Temperature level below lower limit
+//! - \ref AON_EVENT_BATMON_COMBINED : Combined event from BATMON
+//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC.
+//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0
+//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1
+//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2
+//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event
+//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event
+//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event
+//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event
+//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period)
+//! - \ref AON_EVENT_JTAG : JTAG generated event
+//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0
+//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1
+//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2
+//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX)
+//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX)
+//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed
+//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out
+//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event
+//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event
+//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event
+//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event
+//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B
+//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B
+//! - \ref AON_EVENT_NONE : No event, always low
+//!
+//! \return None
+//!
+//! \sa AONEventMcuWakeUpGet()
+//
+//*****************************************************************************
+extern void AONEventMcuWakeUpSet(uint32_t ui32MCUWUEvent,
+ uint32_t ui32EventSrc);
+
+//*****************************************************************************
+//
+//! \brief Get event source for the specified MCU wake-up programmable event.
+//!
+//! \param ui32MCUWUEvent is one of the programmable MCU wake-up event sources.
+//! - \ref AON_EVENT_MCU_WU0
+//! - \ref AON_EVENT_MCU_WU1
+//! - \ref AON_EVENT_MCU_WU2
+//! - \ref AON_EVENT_MCU_WU3
+//! - \ref AON_EVENT_MCU_WU4
+//! - \ref AON_EVENT_MCU_WU5
+//! - \ref AON_EVENT_MCU_WU6
+//! - \ref AON_EVENT_MCU_WU7
+//!
+//! \return Returns the event source for the event AON fabric.
+//! - \ref AON_EVENT_IOEV_MCU_WU : Edge detect event from DIOs which have enabled contribution to IOEV_MCU_WU
+//! - \ref AON_EVENT_AUX_TIMER2_EV0 : Event 0 from AUX Timer2
+//! - \ref AON_EVENT_AUX_TIMER2_EV1 : Event 1 from AUX Timer2
+//! - \ref AON_EVENT_AUX_TIMER2_EV2 : Event 2 from AUX Timer2
+//! - \ref AON_EVENT_AUX_TIMER2_EV3 : Event 3 from AUX Timer2
+//! - \ref AON_EVENT_BATMON_BATT_UL : BATMON event: Battery level above upper limit
+//! - \ref AON_EVENT_BATMON_BATT_LL : BATMON event: Battery level below lower limit
+//! - \ref AON_EVENT_BATMON_TEMP_UL : BATMON event: Temperature level above upper limit
+//! - \ref AON_EVENT_BATMON_TEMP_LL : BATMON event: Temperature level below lower limit
+//! - \ref AON_EVENT_BATMON_COMBINED : Combined event from BATMON
+//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC.
+//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0
+//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1
+//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2
+//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event
+//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event
+//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event
+//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event
+//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period)
+//! - \ref AON_EVENT_JTAG : JTAG generated event
+//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0
+//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1
+//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2
+//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX)
+//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX)
+//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed
+//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out
+//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event
+//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event
+//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event
+//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event
+//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B
+//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B
+//! - \ref AON_EVENT_NONE : No event, always low
+//!
+//! \sa AONEventMcuWakeUpSet()
+//
+//*****************************************************************************
+extern uint32_t AONEventMcuWakeUpGet(uint32_t ui32MCUWUEvent);
+
+//*****************************************************************************
+//
+//! \brief Select event source for the specified programmable event forwarded to the
+//! MCU event fabric.
+//!
+//! The AON event fabric has a total of three programmable events that can
+//! be forwarded to the MCU event fabric.
+//!
+//! \note The three programmable event sources are forwarded to the MCU Event
+//! Fabric as:
+//! - AON_PROG0
+//! - AON_PROG1
+//! - AON_PROG2
+//!
+//! \param ui32MCUEvent is one of three programmable events forwarded to the
+//! MCU event fabric.
+//! - \ref AON_EVENT_MCU_EVENT0
+//! - \ref AON_EVENT_MCU_EVENT1
+//! - \ref AON_EVENT_MCU_EVENT2
+//! \param ui32EventSrc is an event source for the event AON fabric.
+//! - \ref AON_EVENT_IOEV_MCU_WU : Edge detect event from DIOs which have enabled contribution to IOEV_MCU_WU
+//! - \ref AON_EVENT_AUX_TIMER2_EV0 : Event 0 from AUX Timer2
+//! - \ref AON_EVENT_AUX_TIMER2_EV1 : Event 1 from AUX Timer2
+//! - \ref AON_EVENT_AUX_TIMER2_EV2 : Event 2 from AUX Timer2
+//! - \ref AON_EVENT_AUX_TIMER2_EV3 : Event 3 from AUX Timer2
+//! - \ref AON_EVENT_BATMON_BATT_UL : BATMON event: Battery level above upper limit
+//! - \ref AON_EVENT_BATMON_BATT_LL : BATMON event: Battery level below lower limit
+//! - \ref AON_EVENT_BATMON_TEMP_UL : BATMON event: Temperature level above upper limit
+//! - \ref AON_EVENT_BATMON_TEMP_LL : BATMON event: Temperature level below lower limit
+//! - \ref AON_EVENT_BATMON_COMBINED : Combined event from BATMON
+//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC.
+//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0
+//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1
+//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2
+//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event
+//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event
+//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event
+//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event
+//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period)
+//! - \ref AON_EVENT_JTAG : JTAG generated event
+//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0
+//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1
+//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2
+//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX)
+//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX)
+//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed
+//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out
+//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event
+//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event
+//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event
+//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event
+//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B
+//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B
+//! - \ref AON_EVENT_NONE : No event, always low
+//!
+//! \return None
+//!
+//! \sa AONEventMcuGet()
+//
+//*****************************************************************************
+extern void AONEventMcuSet(uint32_t ui32MCUEvent, uint32_t ui32EventSrc);
+
+//*****************************************************************************
+//
+//! \brief Get source for the specified programmable event forwarded to the MCU event
+//! fabric.
+//!
+//! The AON event fabric has a total of three programmable events that can
+//! be forwarded to the MCU event fabric.
+//!
+//! \param ui32MCUEvent is one of three programmable events forwarded to the
+//! MCU event fabric.
+//! - \ref AON_EVENT_MCU_EVENT0
+//! - \ref AON_EVENT_MCU_EVENT1
+//! - \ref AON_EVENT_MCU_EVENT2
+//!
+//! \return Returns the event source for the event AON fabric.
+//! - \ref AON_EVENT_IOEV_MCU_WU : Edge detect event from DIOs which have enabled contribution to IOEV_MCU_WU
+//! - \ref AON_EVENT_AUX_TIMER2_EV0 : Event 0 from AUX Timer2
+//! - \ref AON_EVENT_AUX_TIMER2_EV1 : Event 1 from AUX Timer2
+//! - \ref AON_EVENT_AUX_TIMER2_EV2 : Event 2 from AUX Timer2
+//! - \ref AON_EVENT_AUX_TIMER2_EV3 : Event 3 from AUX Timer2
+//! - \ref AON_EVENT_BATMON_BATT_UL : BATMON event: Battery level above upper limit
+//! - \ref AON_EVENT_BATMON_BATT_LL : BATMON event: Battery level below lower limit
+//! - \ref AON_EVENT_BATMON_TEMP_UL : BATMON event: Temperature level above upper limit
+//! - \ref AON_EVENT_BATMON_TEMP_LL : BATMON event: Temperature level below lower limit
+//! - \ref AON_EVENT_BATMON_COMBINED : Combined event from BATMON
+//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC.
+//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0
+//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1
+//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2
+//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event
+//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event
+//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event
+//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event
+//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period)
+//! - \ref AON_EVENT_JTAG : JTAG generated event
+//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0
+//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1
+//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2
+//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX)
+//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX)
+//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed
+//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out
+//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event
+//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event
+//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event
+//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event
+//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B
+//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B
+//! - \ref AON_EVENT_NONE : No event, always low
+//!
+//! \sa AONEventMcuSet()
+//
+//*****************************************************************************
+extern uint32_t AONEventMcuGet(uint32_t ui32MCUEvent);
+
+//*****************************************************************************
+//
+//! \brief Select event source forwarded to AON Real Time Clock (RTC).
+//!
+//! A programmable event can be forwarded to the AON real time clock
+//! for triggering a capture event on RTC channel 1.
+//!
+//! \param ui32EventSrc is an event source for the event AON fabric.
+//! - \ref AON_EVENT_IOEV_MCU_WU : Edge detect event from DIOs which have enabled contribution to IOEV_MCU_WU
+//! - \ref AON_EVENT_AUX_TIMER2_EV0 : Event 0 from AUX Timer2
+//! - \ref AON_EVENT_AUX_TIMER2_EV1 : Event 1 from AUX Timer2
+//! - \ref AON_EVENT_AUX_TIMER2_EV2 : Event 2 from AUX Timer2
+//! - \ref AON_EVENT_AUX_TIMER2_EV3 : Event 3 from AUX Timer2
+//! - \ref AON_EVENT_BATMON_BATT_UL : BATMON event: Battery level above upper limit
+//! - \ref AON_EVENT_BATMON_BATT_LL : BATMON event: Battery level below lower limit
+//! - \ref AON_EVENT_BATMON_TEMP_UL : BATMON event: Temperature level above upper limit
+//! - \ref AON_EVENT_BATMON_TEMP_LL : BATMON event: Temperature level below lower limit
+//! - \ref AON_EVENT_BATMON_COMBINED : Combined event from BATMON
+//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC.
+//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0
+//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1
+//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2
+//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event
+//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event
+//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event
+//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event
+//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period)
+//! - \ref AON_EVENT_JTAG : JTAG generated event
+//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0
+//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1
+//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2
+//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX)
+//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX)
+//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed
+//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out
+//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event
+//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event
+//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event
+//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event
+//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B
+//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B
+//! - \ref AON_EVENT_NONE : No event, always low
+//!
+//! \return None
+//!
+//! \sa AONEventRtcGet()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+AONEventRtcSet(uint32_t ui32EventSrc)
+{
+ uint32_t ui32Ctrl;
+
+ // Check the arguments.
+ ASSERT(ui32EventSrc <= AON_EVENT_NONE);
+
+ ui32Ctrl = HWREG(AON_EVENT_BASE + AON_EVENT_O_RTCSEL);
+ ui32Ctrl &= ~(AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_M);
+ ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_S;
+
+ HWREG(AON_EVENT_BASE + AON_EVENT_O_RTCSEL) = ui32Ctrl;
+}
+
+//*****************************************************************************
+//
+//! \brief Get event source forwarded to AON Real Time Clock (RTC).
+//!
+//! A programmable event can be forwarded to the AON real time clock
+//! for triggering a capture event on RTC channel 1.
+//!
+//! \return Returns the event source to the event AON fabric.
+//! - \ref AON_EVENT_IOEV_MCU_WU : Edge detect event from DIOs which have enabled contribution to IOEV_MCU_WU
+//! - \ref AON_EVENT_AUX_TIMER2_EV0 : Event 0 from AUX Timer2
+//! - \ref AON_EVENT_AUX_TIMER2_EV1 : Event 1 from AUX Timer2
+//! - \ref AON_EVENT_AUX_TIMER2_EV2 : Event 2 from AUX Timer2
+//! - \ref AON_EVENT_AUX_TIMER2_EV3 : Event 3 from AUX Timer2
+//! - \ref AON_EVENT_BATMON_BATT_UL : BATMON event: Battery level above upper limit
+//! - \ref AON_EVENT_BATMON_BATT_LL : BATMON event: Battery level below lower limit
+//! - \ref AON_EVENT_BATMON_TEMP_UL : BATMON event: Temperature level above upper limit
+//! - \ref AON_EVENT_BATMON_TEMP_LL : BATMON event: Temperature level below lower limit
+//! - \ref AON_EVENT_BATMON_COMBINED : Combined event from BATMON
+//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC.
+//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0
+//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1
+//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2
+//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event
+//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event
+//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event
+//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event
+//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period)
+//! - \ref AON_EVENT_JTAG : JTAG generated event
+//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0
+//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1
+//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2
+//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX)
+//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX)
+//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed
+//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out
+//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event
+//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event
+//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event
+//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event
+//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B
+//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B
+//! - \ref AON_EVENT_NONE : No event, always low
+//!
+//! \sa AONEventRtcSet()
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+AONEventRtcGet(void)
+{
+ uint32_t ui32EventSrc;
+
+ // Return the active event.
+ ui32EventSrc = HWREG(AON_EVENT_BASE + AON_EVENT_O_RTCSEL);
+
+ return ((ui32EventSrc & AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_M) >>
+ AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_S);
+}
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// Redirect to implementation in ROM when available.
+//
+//*****************************************************************************
+#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
+ #include "../driverlib/rom.h"
+ #ifdef ROM_AONEventMcuWakeUpSet
+ #undef AONEventMcuWakeUpSet
+ #define AONEventMcuWakeUpSet ROM_AONEventMcuWakeUpSet
+ #endif
+ #ifdef ROM_AONEventMcuWakeUpGet
+ #undef AONEventMcuWakeUpGet
+ #define AONEventMcuWakeUpGet ROM_AONEventMcuWakeUpGet
+ #endif
+ #ifdef ROM_AONEventMcuSet
+ #undef AONEventMcuSet
+ #define AONEventMcuSet ROM_AONEventMcuSet
+ #endif
+ #ifdef ROM_AONEventMcuGet
+ #undef AONEventMcuGet
+ #define AONEventMcuGet ROM_AONEventMcuGet
+ #endif
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __AON_EVENT_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_event_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_event_doc.h
new file mode 100644
index 0000000..5210bbf
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_event_doc.h
@@ -0,0 +1,58 @@
+/******************************************************************************
+* Filename: aon_event_doc.h
+* Revised: 2017-08-09 16:56:05 +0200 (Wed, 09 Aug 2017)
+* Revision: 49506
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+//! \addtogroup aonevent_api
+//! @{
+//! \section sec_aonevent Introduction
+//!
+//! The event fabric consists of two event modules. One in the MCU power domain (MCU event fabric) and
+//! the other in the AON power domain (AON event fabric). The MCU event fabric is one of the subscribers
+//! to the AON event fabric. For more information on MCU event fabric, see [MCU event API](@ref event_api).
+//!
+//! The AON event fabric is a configurable combinatorial router between AON event sources and event
+//! subscribers in both AON and MCU domains. The API to control the AON event fabric configuration
+//! can be grouped based on the event subscriber to configure:
+//!
+//! - Wake-up events.
+//! - MCU wake-up event
+//! - @ref AONEventMcuWakeUpSet()
+//! - @ref AONEventMcuWakeUpGet()
+//! - AON RTC receives a single programmable event line from the AON event fabric. For more information, see [AON RTC API](@ref aonrtc_api).
+//! - @ref AONEventRtcSet()
+//! - @ref AONEventRtcGet()
+//! - MCU event fabric receives a number of programmable event lines from the AON event fabric. For more information, see [MCU event API](@ref event_api).
+//! - @ref AONEventMcuSet()
+//! - @ref AONEventMcuGet()
+//! @}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_ioc.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_ioc.c
new file mode 100644
index 0000000..c0c9b3c
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_ioc.c
@@ -0,0 +1,39 @@
+/******************************************************************************
+* Filename: aon_ioc.c
+* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016)
+* Revision: 47343
+*
+* Description: Driver for the AON IO Controller
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "aon_ioc.h"
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_ioc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_ioc.h
new file mode 100644
index 0000000..13ab449
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_ioc.h
@@ -0,0 +1,292 @@
+/******************************************************************************
+* Filename: aon_ioc.h
+* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016)
+* Revision: 47343
+*
+* Description: Defines and prototypes for the AON IO Controller
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup aon_group
+//! @{
+//! \addtogroup aonioc_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __AON_IOC_H__
+#define __AON_IOC_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "../inc/hw_types.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_aon_ioc.h"
+#include "debug.h"
+
+//*****************************************************************************
+//
+// Defines for the drive strength
+//
+//*****************************************************************************
+#define AONIOC_DRV_STR_1 0x00000000 // Lowest drive strength
+#define AONIOC_DRV_STR_2 0x00000001
+#define AONIOC_DRV_STR_3 0x00000003
+#define AONIOC_DRV_STR_4 0x00000002
+#define AONIOC_DRV_STR_5 0x00000006
+#define AONIOC_DRV_STR_6 0x00000007
+#define AONIOC_DRV_STR_7 0x00000005
+#define AONIOC_DRV_STR_8 0x00000004 // Highest drive strength
+
+#define AONIOC_DRV_LVL_MIN (AON_IOC_O_IOSTRMIN)
+#define AONIOC_DRV_LVL_MED (AON_IOC_O_IOSTRMED)
+#define AONIOC_DRV_LVL_MAX (AON_IOC_O_IOSTRMAX)
+
+//*****************************************************************************
+//
+// API Functions and prototypes
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \brief Configure drive strength values for the manual drive strength options.
+//!
+//! This function defines the general drive strength settings for the non-AUTO
+//! drive strength options in the MCU IOC. Consequently, if all IOs are using the
+//! automatic drive strength option this function has no effect.
+//!
+//! Changing the drive strength values affects all current modes (Low-Current,
+//! High-Current, and Extended-Current). Current mode for individual IOs is set in
+//! MCU IOC by \ref IOCIODrvStrengthSet().
+//!
+//! \note Values are Gray encoded. Simply incrementing values to increase drive
+//! strength will not work.
+//!
+//! \param ui32DriveLevel
+//! - \ref AONIOC_DRV_LVL_MIN : Minimum drive strength option. Default value is selected
+//! to give minimum 2/4/8 mA @3.3V for Low-Current mode, High-Current mode,
+//! and Extended-Current mode respectively.
+//! - \ref AONIOC_DRV_LVL_MED : Medium drive strength option. Default value is selected
+//! to give minimum 2/4/8 mA @2.5V for Low-Current mode, High-Current mode,
+//! and Extended-Current mode respectively.
+//! - \ref AONIOC_DRV_LVL_MAX : Maximum drive strength option. Default value is selected
+//! to give minimum 2/4/8 mA @1.8V for Low-Current mode, High-Current mode,
+//! and Extended-Current mode respectively.
+//! \param ui32DriveStrength sets the value used by IOs configured as non-AUTO drive strength in MCU IOC.
+//! - \ref AONIOC_DRV_STR_1 : Lowest drive strength
+//! - \ref AONIOC_DRV_STR_2
+//! - \ref AONIOC_DRV_STR_3
+//! - \ref AONIOC_DRV_STR_4
+//! - \ref AONIOC_DRV_STR_5
+//! - \ref AONIOC_DRV_STR_6
+//! - \ref AONIOC_DRV_STR_7
+//! - \ref AONIOC_DRV_STR_8 : Highest drive strength
+//!
+//! \return None
+//!
+//! \sa \ref AONIOCDriveStrengthGet(), \ref IOCIODrvStrengthSet()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+AONIOCDriveStrengthSet(uint32_t ui32DriveLevel, uint32_t ui32DriveStrength)
+{
+ ASSERT((ui32DriveLevel == AONIOC_DRV_LVL_MIN) ||
+ (ui32DriveLevel == AONIOC_DRV_LVL_MED) ||
+ (ui32DriveLevel == AONIOC_DRV_LVL_MAX));
+ ASSERT((ui32DriveStrength == AONIOC_DRV_STR_1) ||
+ (ui32DriveStrength == AONIOC_DRV_STR_2) ||
+ (ui32DriveStrength == AONIOC_DRV_STR_3) ||
+ (ui32DriveStrength == AONIOC_DRV_STR_4) ||
+ (ui32DriveStrength == AONIOC_DRV_STR_5) ||
+ (ui32DriveStrength == AONIOC_DRV_STR_6) ||
+ (ui32DriveStrength == AONIOC_DRV_STR_7) ||
+ (ui32DriveStrength == AONIOC_DRV_STR_8));
+
+ // Set the drive strength.
+ HWREG(AON_IOC_BASE + ui32DriveLevel) = ui32DriveStrength;
+}
+
+//*****************************************************************************
+//
+//! \brief Get a specific drive level setting for all IOs.
+//!
+//! Use this function to read the drive strength setting for a specific
+//! IO drive level.
+//!
+//! \note Values are Gray encoded.
+//!
+//! \param ui32DriveLevel is the specific drive level to get the setting for.
+//! - \ref AONIOC_DRV_LVL_MIN : Minimum drive strength option.
+//! - \ref AONIOC_DRV_LVL_MED : Medium drive strength option.
+//! - \ref AONIOC_DRV_LVL_MAX : Maximum drive strength option.
+//!
+//! \return Returns the requested drive strength level setting for all IOs.
+//! Possible values are:
+//! - \ref AONIOC_DRV_STR_1 : Lowest drive strength
+//! - \ref AONIOC_DRV_STR_2
+//! - \ref AONIOC_DRV_STR_3
+//! - \ref AONIOC_DRV_STR_4
+//! - \ref AONIOC_DRV_STR_5
+//! - \ref AONIOC_DRV_STR_6
+//! - \ref AONIOC_DRV_STR_7
+//! - \ref AONIOC_DRV_STR_8 : Highest drive strength
+//!
+//! \sa AONIOCDriveStrengthSet()
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+AONIOCDriveStrengthGet(uint32_t ui32DriveLevel)
+{
+ // Check the arguments.
+ ASSERT((ui32DriveLevel == AONIOC_DRV_LVL_MIN) ||
+ (ui32DriveLevel == AONIOC_DRV_LVL_MED) ||
+ (ui32DriveLevel == AONIOC_DRV_LVL_MAX));
+
+ // Return the drive strength value.
+ return( HWREG(AON_IOC_BASE + ui32DriveLevel) );
+}
+
+//*****************************************************************************
+//
+//! \brief Freeze the IOs.
+//!
+//! To retain the values of the output IOs during a powerdown/shutdown of the
+//! device all IO latches in the AON domain should be frozen in their current
+//! state. This ensures that software can regain control of the IOs after a
+//! reboot without the IOs first falling back to the default values (i.e. input
+//! and no pull).
+//!
+//! \return None
+//!
+//! \sa AONIOCFreezeDisable()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+AONIOCFreezeEnable(void)
+{
+ // Set the AON IO latches as static.
+ HWREG(AON_IOC_BASE + AON_IOC_O_IOCLATCH) = 0x0;
+}
+
+//*****************************************************************************
+//
+//! \brief Un-freeze the IOs.
+//!
+//! When rebooting the chip after it has entered powerdown/shutdown mode, the
+//! software can regain control of the IOs by setting the IO latches as
+//! transparent. The IOs should not be unfrozen before software has restored
+//! the functionality of the IO.
+//!
+//! \return None
+//!
+//! \sa AONIOCFreezeEnable()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+AONIOCFreezeDisable(void)
+{
+ // Set the AON IOC latches as transparent.
+ HWREG(AON_IOC_BASE + AON_IOC_O_IOCLATCH) = AON_IOC_IOCLATCH_EN;
+}
+
+//*****************************************************************************
+//
+//! \brief Disable the 32kHz clock output.
+//!
+//! When outputting a 32 kHz clock on an IO, the output enable/disable functionality
+//! in the IOC is bypassed. Therefore, the programmer needs to call this
+//! function to disable the clock output.
+//!
+//! \return None
+//!
+//! \sa AONIOC32kHzOutputEnable()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+AONIOC32kHzOutputDisable(void)
+{
+ // Disable the LF clock output.
+ HWREG(AON_IOC_BASE + AON_IOC_O_CLK32KCTL) = AON_IOC_CLK32KCTL_OE_N;
+}
+
+//*****************************************************************************
+//
+//! \brief Enable the 32kHz clock output.
+//!
+//! When outputting a 32 kHz clock on an IO, the output enable/disable functionality
+//! in the IOC is bypassed. Therefore, the programmer needs to call this
+//! function to enable the clock output.
+//!
+//! \return None
+//!
+//! \sa AONIOC32kHzOutputDisable()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+AONIOC32kHzOutputEnable(void)
+{
+ // Enable the LF clock output.
+ HWREG(AON_IOC_BASE + AON_IOC_O_CLK32KCTL) = 0x0;
+}
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __AON_IOC_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_ioc_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_ioc_doc.h
new file mode 100644
index 0000000..3d37978
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_ioc_doc.h
@@ -0,0 +1,65 @@
+/******************************************************************************
+* Filename: aon_ioc_doc.h
+* Revised: 2016-03-30 11:01:30 +0200 (Wed, 30 Mar 2016)
+* Revision: 45969
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+//! \addtogroup aonioc_api
+//! @{
+//! \section sec_aonioc Introduction
+//!
+//! The Input/Output Controller (IOC) controls the functionality of the pins (called DIO).
+//! The IOC consists of two APIs:
+//! - MCU IOC API selects which peripheral module is connected to the individual DIO and thus allowed to control it.
+//! It also controls individual drive strength, slew rate, pull-up/pull-down, edge detection, etc.
+//! - AON IOC API controls the general drive strength definitions, IO latches, and if the LF clock is
+//! routed to a DIO for external use.
+//!
+//! For more information on the MCU IOC see the [IOC API](\ref ioc_api).
+//!
+//! \section sec_aonioc_api API
+//!
+//! The API functions can be grouped like this:
+//!
+//! Freeze IOs while MCU domain is powered down:
+//! - \ref AONIOCFreezeEnable()
+//! - \ref AONIOCFreezeDisable()
+//!
+//! Output LF clock to a DIO:
+//! - \ref AONIOC32kHzOutputEnable()
+//! - \ref AONIOC32kHzOutputDisable()
+//!
+//! Configure the value of drive strength for the three manual MCU IOC settings (MIN, MED, MAX):
+//! - \ref AONIOCDriveStrengthSet()
+//! - \ref AONIOCDriveStrengthGet()
+//!
+//! @}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_pmctl.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_pmctl.c
new file mode 100644
index 0000000..b680fd7
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_pmctl.c
@@ -0,0 +1,41 @@
+/******************************************************************************
+* Filename: aon_pmctl.c
+* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017)
+* Revision: 49096
+*
+* Description: Driver for the AON Power-Management Controller.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "aon_pmctl.h"
+
+// See aon_pmctl.h for implementation
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_pmctl.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_pmctl.h
new file mode 100644
index 0000000..ec6bf2e
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_pmctl.h
@@ -0,0 +1,201 @@
+/******************************************************************************
+* Filename: aon_pmctl.h
+* Revised: 2017-11-02 14:16:14 +0100 (Thu, 02 Nov 2017)
+* Revision: 50156
+*
+* Description: Defines and prototypes for the AON Power-Management Controller
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup aon_group
+//! @{
+//! \addtogroup aonpmctl_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __AON_PMCTL_H__
+#define __AON_PMCTL_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "../inc/hw_types.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_aon_pmctl.h"
+#include "debug.h"
+
+//*****************************************************************************
+//
+// Defines that can be be used to enable/disable the retention on the SRAM
+// banks during power off of the MCU BUS domain. The defines can be passed to
+// AONPMCTLMcuSRamConfig) .
+//
+//*****************************************************************************
+#define MCU_RAM_RET_NONE AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_NONE
+#define MCU_RAM_RET_LVL1 AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL1
+#define MCU_RAM_RET_LVL2 AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL2
+#define MCU_RAM_RET_LVL3 AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL3
+#define MCU_RAM_RET_FULL AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_FULL
+
+//*****************************************************************************
+//
+// Defines for all the different power modes available through
+// AONPMCTLPowerStatusGet() .
+//
+//*****************************************************************************
+#define AONPMCTL_JTAG_POWER_ON AON_PMCTL_PWRSTAT_JTAG_PD_ON
+
+//*****************************************************************************
+//
+// API Functions and prototypes
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \brief Configure the retention on the block SRAM in the MCU BUS domain.
+//!
+//! MCU SRAM is partitioned into 5 banks of 16 KB each. The SRAM supports
+//! retention on all 5 banks during MCU BUS domain power off. The retention
+//! on the SRAM can be turned on and off. Use this function to enable the
+//! retention on the banks.
+//!
+//! If a group of banks is not represented in the parameter \c ui32Retention
+//! then the retention will be disabled for that bank group during MCU BUS
+//! domain power off.
+//!
+//! \note Retention on all SRAM banks is enabled by default. Configuration of
+//! individual SRAM banks is not supported. Configuration is only supported
+//! on bank group level.
+//!
+//! \param ui32Retention defines which groups of SRAM banks to enable/disable
+//! retention on:
+//! - \ref MCU_RAM_RET_NONE Retention is disabled
+//! - \ref MCU_RAM_RET_LVL1 Retention on for banks 0 and 1
+//! - \ref MCU_RAM_RET_LVL2 Retention on for banks 0, 1 and 2
+//! - \ref MCU_RAM_RET_LVL3 Retention on for banks 0, 1, 2 and 3
+//! - \ref MCU_RAM_RET_FULL Retention on for all five banks
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+AONPMCTLMcuSRamRetConfig(uint32_t ui32Retention)
+{
+ uint32_t ui32Reg;
+
+ // Check the arguments.
+ ASSERT((ui32Retention == MCU_RAM_RET_NONE) ||
+ (ui32Retention == MCU_RAM_RET_LVL1) ||
+ (ui32Retention == MCU_RAM_RET_LVL2) ||
+ (ui32Retention == MCU_RAM_RET_LVL3) ||
+ (ui32Retention == MCU_RAM_RET_FULL));
+
+ // Configure the retention.
+ ui32Reg = HWREG(AON_PMCTL_BASE + AON_PMCTL_O_RAMCFG) & ~AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_M;
+ ui32Reg |= ui32Retention;
+ HWREG(AON_PMCTL_BASE + AON_PMCTL_O_RAMCFG) = ui32Reg;
+}
+
+//*****************************************************************************
+//
+//! \brief Get the power status of the Always On (AON) domain.
+//!
+//! This function reports the power management status in AON.
+//!
+//! \return Returns the current power status of the device as a bitwise OR'ed
+//! combination of these values:
+//! - \ref AONPMCTL_JTAG_POWER_ON
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+AONPMCTLPowerStatusGet(void)
+{
+ // Return the power status.
+ return (HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRSTAT));
+}
+
+
+//*****************************************************************************
+//
+//! \brief Request power off of the JTAG domain.
+//!
+//! The JTAG domain is automatically powered up on if a debugger is connected.
+//! If a debugger is not connected this function can be used to power off the
+//! JTAG domain.
+//!
+//! \note Achieving the lowest power modes (shutdown/powerdown) requires the
+//! JTAG domain to be turned off. In general the JTAG domain should never be
+//! powered in production code.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+AONPMCTLJtagPowerOff(void)
+{
+ // Request the power off of the JTAG domain
+ HWREG(AON_PMCTL_BASE + AON_PMCTL_O_JTAGCFG) = 0;
+}
+
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __AON_PMCTL_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_pmctl_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_pmctl_doc.h
new file mode 100644
index 0000000..0f44256
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_pmctl_doc.h
@@ -0,0 +1,99 @@
+/******************************************************************************
+* Filename: aon_pmctl_doc.h
+* Revised: 2017-11-02 15:41:14 +0100 (Thu, 02 Nov 2017)
+* Revision: 50165
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+//! \addtogroup aonpmctl_api
+//! @{
+//! \section sec_aonpmctl Introduction
+//!
+//! This API provides a set of functions for using the AON Power Management
+//! Controller module (AON_PMCTL).
+//!
+//! The AON_PMCTL module contains the following functional options:
+//! - Selection of voltage regulator for the digital domain.
+//! - Control of retention of MCU SRAM banks during power off of the BUS power domain.
+//! - Control of power and retention of AUX SRAM.
+//! - Control of power, reset, and clock for the following domains:
+//! - MCU_VD
+//! - JTAG_PD
+//! - AUX
+//! - Control of the recharging of VDDR while in uLDO state.
+//! - Control of the generation of a periodic request to the OSCDIG to initiate
+//! an XOSC_HF amplitude calibration sequence.
+//!
+//! The main clock for the AON_PMCTL module is the 2 MHz SCLK MF clock.
+//!
+//! AON_PMCTL supports the MCU_voltage domain with a 48 MHz clock (SCLK_HF) that is divided
+//! and gated by the PRCM module before being distributed to all modules in the
+//! MCU voltage domain.
+//!
+//! The AON_PMCTL controls the SCLK_HF clock to ensure that it is available in the
+//! Active and Idle power modes, and disabled for all other modes. SCLK_HF is not
+//! allowed in uLDO state since it uses too much power.
+//! The SCLK_HF clock is also available for the AUX module in the Active and Idle
+//! power modes.
+//!
+//! The AON_PMCTL selects the clock source for the AUX domain in the different
+//! power modes.
+//!
+//! Main functionality to control power management of the JTAG power domain is
+//! supported. Note that no clock control is supported, as the JTAG is clocked
+//! on the TCK clock.
+//!
+//!
+//! \section sec_aonpmctl_api API
+//!
+//! The API functions can be grouped like this:
+//!
+//! Functions to perform status report:
+//! - \ref AONPMCTLPowerStatusGet()
+//!
+//!
+//! Functions to perform device configuration:
+//! - \ref AONPMCTLJtagPowerOff()
+//! - \ref AONPMCTLMcuSRamRetConfig()
+//!
+//! Please note that due to legacy software compatibility some functionalities controlled
+//! by the AON Power Management Controller module are supported through the APIs of
+//! the [System Controller](@ref sysctrl_api) and [Power Controller](@ref pwrctrl_api). Relevant functions are:
+//! - \ref PowerCtrlSourceGet()
+//! - \ref PowerCtrlSourceSet()
+//! - \ref PowerCtrlResetSourceGet()
+//! - \ref SysCtrl_DCDC_VoltageConditionalControl()
+//! - \ref SysCtrlClockLossResetDisable()
+//! - \ref SysCtrlClockLossResetEnable()
+//! - \ref SysCtrlSystemReset()
+//! - \ref SysCtrlResetSourceGet()
+//!
+//! @}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_rtc.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_rtc.c
new file mode 100644
index 0000000..7187f84
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_rtc.c
@@ -0,0 +1,77 @@
+/******************************************************************************
+* Filename: aon_rtc.c
+* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017)
+* Revision: 49096
+*
+* Description: Driver for the AON RTC.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "aon_rtc.h"
+#include "cpu.h"
+
+//*****************************************************************************
+//
+// Handle support for DriverLib in ROM:
+// This section will undo prototype renaming made in the header file
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #undef AONRTCCurrent64BitValueGet
+ #define AONRTCCurrent64BitValueGet NOROM_AONRTCCurrent64BitValueGet
+#endif
+
+
+//*****************************************************************************
+//
+// Get the current 64-bit value of the RTC counter.
+//
+//*****************************************************************************
+uint64_t
+AONRTCCurrent64BitValueGet( void )
+{
+ union {
+ uint64_t returnValue ;
+ uint32_t secAndSubSec[ 2 ] ;
+ } currentRtc ;
+ uint32_t ui32SecondSecRead ;
+
+ // Reading SEC both before and after SUBSEC in order to detect if SEC incremented while reading SUBSEC
+ // If SEC incremented, we can't be sure which SEC the SUBSEC belongs to, so repeating the sequence then.
+ do {
+ currentRtc.secAndSubSec[ 1 ] = HWREG( AON_RTC_BASE + AON_RTC_O_SEC );
+ currentRtc.secAndSubSec[ 0 ] = HWREG( AON_RTC_BASE + AON_RTC_O_SUBSEC );
+ ui32SecondSecRead = HWREG( AON_RTC_BASE + AON_RTC_O_SEC );
+ } while ( currentRtc.secAndSubSec[ 1 ] != ui32SecondSecRead );
+
+ return ( currentRtc.returnValue );
+}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_rtc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_rtc.h
new file mode 100644
index 0000000..6e131d2
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_rtc.h
@@ -0,0 +1,931 @@
+/******************************************************************************
+* Filename: aon_rtc.h
+* Revised: 2017-08-16 15:13:43 +0200 (Wed, 16 Aug 2017)
+* Revision: 49593
+*
+* Description: Defines and prototypes for the AON RTC
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup aon_group
+//! @{
+//! \addtogroup aonrtc_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __AON_RTC_H__
+#define __AON_RTC_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "../inc/hw_types.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_aon_rtc.h"
+#include "debug.h"
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// This section renames all functions that are not "static inline", so that
+// calling these functions will default to implementation in flash. At the end
+// of this file a second renaming will change the defaults to implementation in
+// ROM for available functions.
+//
+// To force use of the implementation in flash, e.g. for debugging:
+// - Globally: Define DRIVERLIB_NOROM at project level
+// - Per function: Use prefix "NOROM_" when calling the function
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #define AONRTCCurrent64BitValueGet NOROM_AONRTCCurrent64BitValueGet
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to most of the AON_RTC APIs as the ui32Channel
+// parameter.
+//
+//*****************************************************************************
+#define AON_RTC_CH_NONE 0x0 // RTC No channel
+#define AON_RTC_CH0 0x1 // RTC Channel 0
+#define AON_RTC_CH1 0x2 // RTC Channel 1
+#define AON_RTC_CH2 0x4 // RTC Channel 2
+#define AON_RTC_ACTIVE 0x8 // RTC Active
+
+//*****************************************************************************
+//
+// Values that can be passed to AONRTCConfigDelay as the ui32Delay parameter.
+//
+//*****************************************************************************
+#define AON_RTC_CONFIG_DELAY_NODELAY 0 // NO DELAY
+#define AON_RTC_CONFIG_DELAY_1 1 // Delay of 1 clk cycle
+#define AON_RTC_CONFIG_DELAY_2 2 // Delay of 2 clk cycles
+#define AON_RTC_CONFIG_DELAY_4 3 // Delay of 4 clk cycles
+#define AON_RTC_CONFIG_DELAY_8 4 // Delay of 8 clk cycles
+#define AON_RTC_CONFIG_DELAY_16 5 // Delay of 16 clk cycles
+#define AON_RTC_CONFIG_DELAY_32 6 // Delay of 32 clk cycles
+#define AON_RTC_CONFIG_DELAY_48 7 // Delay of 48 clk cycles
+#define AON_RTC_CONFIG_DELAY_64 8 // Delay of 64 clk cycles
+#define AON_RTC_CONFIG_DELAY_80 9 // Delay of 80 clk cycles
+#define AON_RTC_CONFIG_DELAY_96 10 // Delay of 96 clk cycles
+#define AON_RTC_CONFIG_DELAY_112 11 // Delay of 112 clk cycles
+#define AON_RTC_CONFIG_DELAY_128 12 // Delay of 128 clk cycles
+#define AON_RTC_CONFIG_DELAY_144 13 // Delay of 144 clk cycles
+
+//*****************************************************************************
+//
+// Values that can be passed to AONRTCSetModeCH1 as the ui32Mode
+// parameter.
+//
+//*****************************************************************************
+#define AON_RTC_MODE_CH1_CAPTURE 1 // Capture mode
+#define AON_RTC_MODE_CH1_COMPARE 0 // Compare Mode
+
+//*****************************************************************************
+//
+// Values that can be passed to AONRTCSetModeCH2 as the ui32Mode
+// parameter.
+//
+//*****************************************************************************
+#define AON_RTC_MODE_CH2_CONTINUOUS 1 // Continuous mode
+#define AON_RTC_MODE_CH2_NORMALCOMPARE 0 // Normal compare mode
+
+//*****************************************************************************
+//
+// Mutliplication factor for converting from seconds to corresponding time in
+// the "CompareValue" format.
+// The factor correspond to the compare value format described in the registers
+// \ref AON_RTC_O_CH0CMP, \ref AON_RTC_O_CH1CMP and \ref AON_RTC_O_CH2CMP.
+// Example1:
+// 4 milliseconds in CompareValue format can be written like this:
+// ((uint32_t)( 0.004 * FACTOR_SEC_TO_COMP_VAL_FORMAT ))
+// Example2:
+// 4 seconds in CompareValue format can be written like this:
+// ( 4 * FACTOR_SEC_TO_COMP_VAL_FORMAT )
+//
+//*****************************************************************************
+#define FACTOR_SEC_TO_COMP_VAL_FORMAT 0x00010000
+
+//*****************************************************************************
+//
+// API Functions and prototypes
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \brief Enable the RTC.
+//!
+//! Enable the AON Real Time Clock.
+//!
+//! \note Event generation for each of the three channels must also be enabled
+//! using the function AONRTCChannelEnable().
+//!
+//! \return None
+//!
+//! \sa AONRTCChannelEnable()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+AONRTCEnable(void)
+{
+ // Enable RTC.
+ HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_EN_BITN) = 1;
+}
+
+//*****************************************************************************
+//
+//! \brief Disable the RTC.
+//!
+//! Disable the AON Real Time Clock.
+//!
+//! \note Event generation for each of the three channels can also be disabled
+//! using the function AONRTCChannelDisable().
+//!
+//! \return None
+//!
+//! \sa AONRTCChannelDisable()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+AONRTCDisable(void)
+{
+ // Disable RTC
+ HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_EN_BITN) = 0;
+}
+
+//*****************************************************************************
+//
+//! \brief Reset the RTC.
+//!
+//! Reset the AON Real Time Clock.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+AONRTCReset(void)
+{
+ // Reset RTC.
+ HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_RESET_BITN) = 1;
+}
+
+//*****************************************************************************
+//
+//! \brief Check if the RTC is active (enabled).
+//!
+//! \return Returns the status of the RTC.
+//! - false : RTC is disabled
+//! - true : RTC is enabled
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+AONRTCActive(void)
+{
+ // Read if RTC is enabled
+ return(HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_EN_BITN));
+}
+
+//*****************************************************************************
+//
+//! \brief Check if an RTC channel is active (enabled).
+//!
+//! \param ui32Channel specifies the RTC channel to check status of.
+//! Parameter must be one (and only one) of the following:
+//! - \ref AON_RTC_CH0
+//! - \ref AON_RTC_CH1
+//! - \ref AON_RTC_CH2
+//!
+//! \return Returns the status of the requested channel:
+//! - false : Channel is disabled
+//! - true : Channel is enabled
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+AONRTCChannelActive(uint32_t ui32Channel)
+{
+ uint32_t uint32Status = 0;
+
+ if(ui32Channel & AON_RTC_CH0)
+ {
+ uint32Status = HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH0_EN_BITN);
+ }
+
+ if(ui32Channel & AON_RTC_CH1)
+ {
+ uint32Status = HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_EN_BITN);
+ }
+
+ if(ui32Channel & AON_RTC_CH2)
+ {
+ uint32Status = HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_EN_BITN);
+ }
+
+ return(uint32Status);
+}
+
+//*****************************************************************************
+//
+//! \brief Configure Event Delay for the RTC.
+//!
+//! Each event from the three individual channels can generate a delayed
+//! event. The delay time for these events is set using this function.
+//! The delay is measured in clock cycles.
+//!
+//! \note There is only one delay setting shared for all three channels.
+//!
+//! \param ui32Delay specifies the delay time for delayed events.
+//! Parameter must be one of the following:
+//! - \ref AON_RTC_CONFIG_DELAY_NODELAY
+//! - \ref AON_RTC_CONFIG_DELAY_1
+//! - \ref AON_RTC_CONFIG_DELAY_2
+//! - \ref AON_RTC_CONFIG_DELAY_4
+//! - \ref AON_RTC_CONFIG_DELAY_8
+//! - \ref AON_RTC_CONFIG_DELAY_16
+//! - \ref AON_RTC_CONFIG_DELAY_32
+//! - \ref AON_RTC_CONFIG_DELAY_48
+//! - \ref AON_RTC_CONFIG_DELAY_64
+//! - \ref AON_RTC_CONFIG_DELAY_80
+//! - \ref AON_RTC_CONFIG_DELAY_96
+//! - \ref AON_RTC_CONFIG_DELAY_112
+//! - \ref AON_RTC_CONFIG_DELAY_128
+//! - \ref AON_RTC_CONFIG_DELAY_144
+//!
+//! \return None.
+//
+//*****************************************************************************
+__STATIC_INLINE void
+AONRTCDelayConfig(uint32_t ui32Delay)
+{
+ uint32_t ui32Cfg;
+
+ // Check the arguments.
+ ASSERT(ui32Delay <= AON_RTC_CONFIG_DELAY_144);
+
+
+ ui32Cfg = HWREG(AON_RTC_BASE + AON_RTC_O_CTL);
+ ui32Cfg &= ~(AON_RTC_CTL_EV_DELAY_M);
+ ui32Cfg |= (ui32Delay << AON_RTC_CTL_EV_DELAY_S);
+
+ HWREG(AON_RTC_BASE + AON_RTC_O_CTL) = ui32Cfg;
+}
+
+//*****************************************************************************
+//
+//! \brief Configure the source of the combined event.
+//!
+//! A combined delayed event can be generated from a combination of the three
+//! delayed events. Delayed events form the specified channels are OR'ed
+//! together to generate the combined event.
+//!
+//! \param ui32Channels specifies the channels that are to be used for
+//! generating the combined event.
+//! The parameter must be the bitwise OR of any of the following:
+//! - \ref AON_RTC_CH0
+//! - \ref AON_RTC_CH1
+//! - \ref AON_RTC_CH2
+//! - \ref AON_RTC_CH_NONE
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+AONRTCCombinedEventConfig(uint32_t ui32Channels)
+{
+ uint32_t ui32Cfg;
+
+ // Check the arguments.
+ ASSERT( (ui32Channels & (AON_RTC_CH0 | AON_RTC_CH1 | AON_RTC_CH2)) ||
+ (ui32Channels == AON_RTC_CH_NONE) );
+
+ ui32Cfg = HWREG(AON_RTC_BASE + AON_RTC_O_CTL);
+ ui32Cfg &= ~(AON_RTC_CTL_COMB_EV_MASK_M);
+ ui32Cfg |= (ui32Channels << AON_RTC_CTL_COMB_EV_MASK_S);
+
+ HWREG(AON_RTC_BASE + AON_RTC_O_CTL) = ui32Cfg;
+}
+
+//*****************************************************************************
+//
+//! \brief Clear event from a specified channel.
+//!
+//! In case of an active event from the specified channel, the event
+//! will be cleared (de-asserted).
+//!
+//! \param ui32Channel clears the event from one or more RTC channels:
+//! - \ref AON_RTC_CH0
+//! - \ref AON_RTC_CH1
+//! - \ref AON_RTC_CH2
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+AONRTCEventClear(uint32_t ui32Channel)
+{
+ // Check the arguments.
+ ASSERT((ui32Channel == AON_RTC_CH0) ||
+ (ui32Channel == AON_RTC_CH1) ||
+ (ui32Channel == AON_RTC_CH2));
+
+ if(ui32Channel & AON_RTC_CH0)
+ {
+ HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) = AON_RTC_EVFLAGS_CH0;
+ }
+
+ if(ui32Channel & AON_RTC_CH1)
+ {
+ HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) = AON_RTC_EVFLAGS_CH1;
+ }
+
+ if(ui32Channel & AON_RTC_CH2)
+ {
+ HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) = AON_RTC_EVFLAGS_CH2;
+ }
+}
+
+//*****************************************************************************
+//
+//! \brief Get event status for a specified channel.
+//!
+//! In case of an active event from the specified channel,
+//! this call will return \c true otherwise \c false.
+//!
+//! \param ui32Channel specifies the channel from which to query the event state.
+//! The parameter must be one (and only one) of the following:
+//! - \ref AON_RTC_CH0
+//! - \ref AON_RTC_CH1
+//! - \ref AON_RTC_CH2
+//!
+//! \return Returns \c true if an event has occurred for the given channel,
+//! otherwise \c false.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+AONRTCEventGet(uint32_t ui32Channel)
+{
+ uint32_t uint32Event = 0;
+
+ // Check the arguments.
+ ASSERT((ui32Channel == AON_RTC_CH0) ||
+ (ui32Channel == AON_RTC_CH1) ||
+ (ui32Channel == AON_RTC_CH2));
+
+ if(ui32Channel & AON_RTC_CH0)
+ {
+ uint32Event = HWREGBITW(AON_RTC_BASE + AON_RTC_O_EVFLAGS, AON_RTC_EVFLAGS_CH0_BITN);
+ }
+
+ if(ui32Channel & AON_RTC_CH1)
+ {
+ uint32Event = HWREGBITW(AON_RTC_BASE + AON_RTC_O_EVFLAGS, AON_RTC_EVFLAGS_CH1_BITN);
+ }
+
+ if(ui32Channel & AON_RTC_CH2)
+ {
+ uint32Event = HWREGBITW(AON_RTC_BASE + AON_RTC_O_EVFLAGS, AON_RTC_EVFLAGS_CH2_BITN);
+ }
+
+ return(uint32Event);
+}
+
+//*****************************************************************************
+//
+//! \brief Get integer part (seconds) of RTC free-running timer.
+//!
+//! Get the value in seconds of RTC free-running timer, i.e. the integer part.
+//! The fractional part is returned from a call to AONRTCFractionGet().
+//!
+//! \note It is recommended to use \ref AONRTCCurrentCompareValueGet() instead
+//! of this function if the <16.16> format is sufficient.
+//!
+//! \note To read a consistent pair of integer and fractional parts,
+//! \ref AONRTCSecGet() must be called first to trigger latching of the
+//! fractional part, which is then read by \ref AONRTCFractionGet(). Interrupts
+//! must be disabled to ensure that these operations are performed atomically.
+//!
+//! \return Returns the integer part of RTC free running timer.
+//!
+//! \sa \ref AONRTCFractionGet() \ref AONRTCCurrentCompareValueGet()
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+AONRTCSecGet(void)
+{
+ // The following read gets the seconds, but also latches the fractional
+ // part.
+ return(HWREG(AON_RTC_BASE + AON_RTC_O_SEC));
+}
+
+//*****************************************************************************
+//
+//! \brief Get fractional part (sub-seconds) of RTC free-running timer.
+//!
+//! Get the value of the fractional part of RTC free-running timer, i.e. the
+//! sub-second part.
+//!
+//! \note It is recommended to use \ref AONRTCCurrentCompareValueGet() instead
+//! of this function if the <16.16> format is sufficient.
+//!
+//! \note To read a consistent pair of integer and fractional parts,
+//! \ref AONRTCSecGet() must be called first to trigger latching of the
+//! fractional part, which is then read by \ref AONRTCFractionGet(). Interrupts
+//! must be disabled to ensure that these operations are performed atomically.
+//!
+//! \return Returns the fractional part of RTC free running timer.
+//!
+//! \sa \ref AONRTCSecGet() \ref AONRTCCurrentCompareValueGet()
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+AONRTCFractionGet(void)
+{
+ // Note1: It is recommended to use AON RTCCurrentCompareValueGet() instead
+ // of this function if the <16.16> format is sufficient.
+ // Note2: AONRTCSecGet() must be called before this function to get a
+ // consistent reading.
+ // Note3: Interrupts must be disabled between the call to AONRTCSecGet() and this
+ // call since there are interrupt functions that reads AON_RTC_O_SEC
+ return(HWREG(AON_RTC_BASE + AON_RTC_O_SUBSEC));
+}
+
+//*****************************************************************************
+//
+//! \brief Get the sub second increment of the RTC.
+//!
+//! Get the value of the sub-second increment which is added to the RTC
+//! absolute time on every clock tick.
+//!
+//! \note For a precise and temperature independent LF clock (e.g. an LF XTAL)
+//! this value would stay the same across temperature. For temperatue
+//! dependent clock sources like an RC oscillator, this value will change
+//! over time if the application includes functionality for doing temperature
+//! compensation of the RTC clock source. The default value corresponds to a
+//! LF clock frequency of exactly 32.768 kHz.
+//!
+//! \return Returns the sub-second increment of the RTC added to the overall
+//! value on every RTC clock tick.
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+AONRTCSubSecIncrGet(void)
+{
+ return(HWREG(AON_RTC_BASE + AON_RTC_O_SUBSECINC));
+}
+
+//*****************************************************************************
+//
+//! \brief Set operational mode of channel 1.
+//!
+//! Set the operational mode of channel 1. It can be capture or compare mode.
+//! In capture mode, an external event causes the value of the free running
+//! counter to be stored, to remember the time of the event.
+//!
+//! \note The default mode is compare.
+//!
+//! \param ui32Mode specifies the mode for channel 1.
+//! The parameter must be one of the following:
+//! - \ref AON_RTC_MODE_CH1_CAPTURE
+//! - \ref AON_RTC_MODE_CH1_COMPARE
+//!
+//! \return None
+//!
+//! \sa AONRTCModeCh1Get()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+AONRTCModeCh1Set(uint32_t ui32Mode)
+{
+ // Check the arguments.
+ ASSERT((ui32Mode == AON_RTC_MODE_CH1_CAPTURE) ||
+ (ui32Mode == AON_RTC_MODE_CH1_COMPARE));
+
+ HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_CAPT_EN_BITN) = ui32Mode;
+}
+
+//*****************************************************************************
+//
+//! \brief Get operational mode of channel 1.
+//!
+//! Get the operational mode of channel 1. It can be capture or compare mode.
+//! In capture mode, an external event causes the value of the free running
+//! counter to be stored, to remember the time of the event.
+//!
+//! \return Returns the operational mode of channel 1, one of:
+//! - \ref AON_RTC_MODE_CH1_CAPTURE
+//! - \ref AON_RTC_MODE_CH1_COMPARE
+//!
+//! \sa AONRTCModeCh1Set()
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+AONRTCModeCh1Get(void)
+{
+ return(HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_CAPT_EN_BITN));
+}
+
+//*****************************************************************************
+//
+//! \brief Set operational mode of channel 2.
+//!
+//! Set the operational mode of channel 2. It can be in continuous compare
+//! mode or normal compare mode.
+//! In continuous mode, a value is automatically incremented to the channel 2
+//! compare register, upon a channel 2 compare event. This allows channel 2 to
+//! generate a series of completely equidistant events.
+//! The increment value is set by the AONRTCIncValueCh2Set() call.
+//!
+//! \note The default mode is normal compare.
+//!
+//! \param ui32Mode specifies the mode for channel 2.
+//! The parameter must be one of the following:
+//! - \ref AON_RTC_MODE_CH2_CONTINUOUS
+//! - \ref AON_RTC_MODE_CH2_NORMALCOMPARE
+//!
+//! \return None
+//!
+//! \sa AONRTCIncValueCh2Set(), AONRTCIncValueCh2Get()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+AONRTCModeCh2Set(uint32_t ui32Mode)
+{
+ // Check the arguments.
+ ASSERT((ui32Mode == AON_RTC_MODE_CH2_CONTINUOUS) ||
+ (ui32Mode == AON_RTC_MODE_CH2_NORMALCOMPARE));
+
+ HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_CONT_EN_BITN) = ui32Mode;
+}
+
+//*****************************************************************************
+//
+//! \brief Get operational mode of channel 2.
+//!
+//! Get the operational mode of channel 2. It can be in continuous compare
+//! mode or normal compare mode.
+//! In continuous mode, a value is automatically incremented to the channel 2
+//! compare register, upon a channel 2 compare event. This allows channel 2 to
+//! generate a series of completely equidistant events.
+//! The increment value is set by the AONRTCIncValueCh2Set() call.
+//!
+//! \return Returns the operational mode of channel 2, i.e. one of:
+//! - \ref AON_RTC_MODE_CH2_CONTINUOUS
+//! - \ref AON_RTC_MODE_CH2_NORMALCOMPARE
+//!
+//! \sa AONRTCIncValueCh2Set(), AONRTCIncValueCh2Get()
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+AONRTCModeCh2Get(void)
+{
+ return(HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_CONT_EN_BITN));
+}
+
+//*****************************************************************************
+//
+//! \brief Enable event operation for the specified channel.
+//!
+//! Enable the event generation for the specified channel.
+//!
+//! \note The RTC free running clock must also be enabled globally using the
+//! AONRTCEnable() call.
+//!
+//! \param ui32Channel specifies one or more channels to enable:
+//! - \ref AON_RTC_CH0
+//! - \ref AON_RTC_CH1
+//! - \ref AON_RTC_CH2
+//!
+//! \return None
+//!
+//! \sa AONRTCEnable()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+AONRTCChannelEnable(uint32_t ui32Channel)
+{
+ // Check the arguments.
+ ASSERT((ui32Channel == AON_RTC_CH0) ||
+ (ui32Channel == AON_RTC_CH1) ||
+ (ui32Channel == AON_RTC_CH2));
+
+ if(ui32Channel & AON_RTC_CH0)
+ {
+ HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH0_EN_BITN) = 1;
+ }
+
+ if(ui32Channel & AON_RTC_CH1)
+ {
+ HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_EN_BITN) = 1;
+ }
+
+ if(ui32Channel & AON_RTC_CH2)
+ {
+ HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_EN_BITN) = 1;
+ }
+}
+
+//*****************************************************************************
+//
+//! \brief Disable event operation for the specified channel.
+//!
+//! Disable the event generation for the specified channel.
+//!
+//! \note The RTC free running clock can also be disabled globally using the
+//! AONRTCDisable() call.
+//!
+//! \param ui32Channel specifies one or more channels to disable:
+//! - \ref AON_RTC_CH0
+//! - \ref AON_RTC_CH1
+//! - \ref AON_RTC_CH2
+//!
+//! \return None
+//!
+//! \sa AONRTCDisable()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+AONRTCChannelDisable(uint32_t ui32Channel)
+{
+ // Check the arguments.
+ ASSERT((ui32Channel == AON_RTC_CH0) ||
+ (ui32Channel == AON_RTC_CH1) ||
+ (ui32Channel == AON_RTC_CH2));
+
+ if(ui32Channel & AON_RTC_CH0)
+ {
+ HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH0_EN_BITN) = 0;
+ }
+
+ if(ui32Channel & AON_RTC_CH1)
+ {
+ HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_EN_BITN) = 0;
+ }
+
+ if(ui32Channel & AON_RTC_CH2)
+ {
+ HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_EN_BITN) = 0;
+ }
+}
+
+//*****************************************************************************
+//
+//! \brief Set the compare value for the given channel.
+//!
+//! Set compare value for the specified channel.
+//!
+//! The format of the compare value is a 16 bit integer and 16 bit fractional
+//! format <16 sec.16 subsec>. The current value of the RTC counter
+//! can be retrieved in a format compatible to the compare register using
+//! \ref AONRTCCurrentCompareValueGet()
+//!
+//! \param ui32Channel specifies one or more channels to set compare value for:
+//! - \ref AON_RTC_CH0
+//! - \ref AON_RTC_CH1
+//! - \ref AON_RTC_CH2
+//! \param ui32CompValue is the compare value to set for the specified channel.
+//! - Format: <16 sec.16 subsec>
+//!
+//! \return None
+//!
+//! \sa AONRTCCurrentCompareValueGet()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+AONRTCCompareValueSet(uint32_t ui32Channel, uint32_t ui32CompValue)
+{
+ // Check the arguments.
+ ASSERT((ui32Channel == AON_RTC_CH0) ||
+ (ui32Channel == AON_RTC_CH1) ||
+ (ui32Channel == AON_RTC_CH2));
+
+ if(ui32Channel & AON_RTC_CH0)
+ {
+ HWREG(AON_RTC_BASE + AON_RTC_O_CH0CMP) = ui32CompValue;
+ }
+
+ if(ui32Channel & AON_RTC_CH1)
+ {
+ HWREG(AON_RTC_BASE + AON_RTC_O_CH1CMP) = ui32CompValue;
+ }
+
+ if(ui32Channel & AON_RTC_CH2)
+ {
+ HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMP) = ui32CompValue;
+ }
+}
+
+//*****************************************************************************
+//
+//! \brief Get the compare value for the given channel.
+//!
+//! Get compare value for the specified channel.
+//!
+//! \param ui32Channel specifies a channel.
+//! The parameter must be one (and only one) of the following:
+//! - \ref AON_RTC_CH0
+//! - \ref AON_RTC_CH1
+//! - \ref AON_RTC_CH2
+//!
+//! \return Returns the stored compare value for the given channel.
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+AONRTCCompareValueGet(uint32_t ui32Channel)
+{
+ uint32_t ui32Value = 0;
+
+ // Check the arguments
+ ASSERT((ui32Channel == AON_RTC_CH0) ||
+ (ui32Channel == AON_RTC_CH1) ||
+ (ui32Channel == AON_RTC_CH2));
+
+ if(ui32Channel & AON_RTC_CH0)
+ {
+ ui32Value = HWREG(AON_RTC_BASE + AON_RTC_O_CH0CMP);
+ }
+
+ if(ui32Channel & AON_RTC_CH1)
+ {
+ ui32Value = HWREG(AON_RTC_BASE + AON_RTC_O_CH1CMP);
+ }
+
+ if(ui32Channel & AON_RTC_CH2)
+ {
+ ui32Value = HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMP);
+ }
+
+ return(ui32Value);
+}
+
+//*****************************************************************************
+//
+//! \brief Get the current value of the RTC counter in a format that matches
+//! RTC compare values.
+//!
+//! The compare value registers contains 16 integer and 16 fractional bits.
+//! This function will return the current value of the RTC counter in an
+//! identical format.
+//!
+//! \return Returns the current value of the RTC counter in a <16.16> format
+//! (SEC[15:0].SUBSEC[31:16]).
+//!
+//! \sa \ref AONRTCCompareValueSet()
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+AONRTCCurrentCompareValueGet( void )
+{
+ return ( HWREG( AON_RTC_BASE + AON_RTC_O_TIME ));
+}
+
+//*****************************************************************************
+//
+//! \brief Get the current 64-bit value of the RTC counter.
+//!
+//! \note Reading SEC both before and after SUBSEC in order to detect if SEC
+//! incremented while reading SUBSEC. If SEC incremented, we can't be sure
+//! which SEC the SUBSEC belongs to, so repeating the sequence then.
+//!
+//! \return Returns the current value of the RTC counter in a 64-bits format
+//! (SEC[31:0].SUBSEC[31:0]).
+//
+//*****************************************************************************
+extern uint64_t AONRTCCurrent64BitValueGet(void);
+
+//*****************************************************************************
+//
+//! \brief Set the channel 2 increment value when operating in continuous mode.
+//!
+//! Set the channel 2 increment value when operating in continuous mode.
+//! The specified value is automatically incremented to the channel 2 compare
+//! register, upon a channel 2 compare event. This allows channel 2 to generate
+//! a series of completely equidistant events.
+//!
+//! \param ui32IncValue is the increment value when operating in continuous mode.
+//!
+//! \return None
+//!
+//! \sa AONRTCIncValueCh2Get()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+AONRTCIncValueCh2Set(uint32_t ui32IncValue)
+{
+ HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMPINC) = ui32IncValue;
+}
+
+//*****************************************************************************
+//
+//! \brief Get the channel2 increment value when operating in continuous mode.
+//!
+//! Get the channel 2 increment value, when channel 2 is operating in
+//! continuous mode.
+//! This value is automatically incremented to the channel 2 compare
+//! register, upon a channel 2 compare event. This allows channel 2 to
+//! generate a series of completely equidistant events.
+//!
+//! \return Returns the channel 2 increment value when operating in continuous
+//! mode.
+//!
+//! \sa AONRTCIncValueCh2Set()
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+AONRTCIncValueCh2Get(void)
+{
+ return(HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMPINC));
+}
+
+//*****************************************************************************
+//
+//! \brief Get the channel 1 capture value.
+//!
+//! Get the channel 1 capture value.
+//! The upper 16 bits of the returned value is the lower 16 bits of the
+//! integer part of the RTC timer. The lower 16 bits of the returned part
+//! is the upper 16 bits of the fractional part.
+//!
+//! \return Returns the channel 1 capture value.
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+AONRTCCaptureValueCh1Get(void)
+{
+ return(HWREG(AON_RTC_BASE + AON_RTC_O_CH1CAPT));
+}
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// Redirect to implementation in ROM when available.
+//
+//*****************************************************************************
+#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
+ #include "../driverlib/rom.h"
+ #ifdef ROM_AONRTCCurrent64BitValueGet
+ #undef AONRTCCurrent64BitValueGet
+ #define AONRTCCurrent64BitValueGet ROM_AONRTCCurrent64BitValueGet
+ #endif
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __AON_RTC_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_rtc_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_rtc_doc.h
new file mode 100644
index 0000000..e5be29f
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_rtc_doc.h
@@ -0,0 +1,41 @@
+/******************************************************************************
+* Filename: aon_rtc_doc.h
+* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016)
+* Revision: 45971
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+//! \addtogroup aonrtc_api
+//! @{
+//! \section sec_aonrtc Introduction
+//!
+//! \note If using TI-RTOS then only TI-RTOS is allowed to configure the RTC timer!
+//! @}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_adc.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_adc.c
new file mode 100644
index 0000000..b1b3f19
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_adc.c
@@ -0,0 +1,337 @@
+/******************************************************************************
+* Filename: aux_adc.c
+* Revised: 2017-11-20 14:31:35 +0100 (Mon, 20 Nov 2017)
+* Revision: 50315
+*
+* Description: Driver for the AUX Time to Digital Converter interface.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "aux_adc.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_aux_sysif.h"
+#include "../inc/hw_fcfg1.h"
+#include "adi.h"
+#include "event.h"
+
+//*****************************************************************************
+//
+// Handle support for DriverLib in ROM:
+// This section will undo prototype renaming made in the header file
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #undef AUXADCDisable
+ #define AUXADCDisable NOROM_AUXADCDisable
+ #undef AUXADCEnableAsync
+ #define AUXADCEnableAsync NOROM_AUXADCEnableAsync
+ #undef AUXADCEnableSync
+ #define AUXADCEnableSync NOROM_AUXADCEnableSync
+ #undef AUXADCDisableInputScaling
+ #define AUXADCDisableInputScaling NOROM_AUXADCDisableInputScaling
+ #undef AUXADCFlushFifo
+ #define AUXADCFlushFifo NOROM_AUXADCFlushFifo
+ #undef AUXADCReadFifo
+ #define AUXADCReadFifo NOROM_AUXADCReadFifo
+ #undef AUXADCPopFifo
+ #define AUXADCPopFifo NOROM_AUXADCPopFifo
+ #undef AUXADCGetAdjustmentGain
+ #define AUXADCGetAdjustmentGain NOROM_AUXADCGetAdjustmentGain
+ #undef AUXADCGetAdjustmentOffset
+ #define AUXADCGetAdjustmentOffset NOROM_AUXADCGetAdjustmentOffset
+ #undef AUXADCValueToMicrovolts
+ #define AUXADCValueToMicrovolts NOROM_AUXADCValueToMicrovolts
+ #undef AUXADCMicrovoltsToValue
+ #define AUXADCMicrovoltsToValue NOROM_AUXADCMicrovoltsToValue
+ #undef AUXADCAdjustValueForGainAndOffset
+ #define AUXADCAdjustValueForGainAndOffset NOROM_AUXADCAdjustValueForGainAndOffset
+ #undef AUXADCUnadjustValueForGainAndOffset
+ #define AUXADCUnadjustValueForGainAndOffset NOROM_AUXADCUnadjustValueForGainAndOffset
+#endif
+
+//*****************************************************************************
+//
+// Disables the ADC
+//
+//*****************************************************************************
+void
+AUXADCDisable(void)
+{
+ // Disable the ADC reference
+ ADI8BitsClear(AUX_ADI4_BASE, ADI_4_AUX_O_ADCREF0, ADI_4_AUX_ADCREF0_EN_M | ADI_4_AUX_ADCREF0_REF_ON_IDLE_M | ADI_4_AUX_ADCREF0_SRC_M);
+
+ // Assert reset and disable the ADC
+ ADI8BitsClear(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_EN_M | ADI_4_AUX_ADC0_RESET_N_M | ADI_4_AUX_ADC0_SMPL_MODE_M | ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_M);
+
+ // Ensure that scaling is enabled by default before next use of the ADC
+ ADI8BitsClear(AUX_ADI4_BASE, ADI_4_AUX_O_ADC1, ADI_4_AUX_ADC1_SCALE_DIS_M);
+
+ // Flush the FIFO before disabling the clocks
+ HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 1; // CMD: EN(1) -> FLUSH(3)
+ HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 0; // CMD: FLUSH(3) -> EN(1)
+
+ // Disable the ADC clock (no need to wait since IOB_WUC_ADCCLKCTL_ACK goes low immediately)
+ HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_ADCCLKCTL) = 0;
+
+ // Disable the ADC data interface
+ HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = 0;
+}
+
+//*****************************************************************************
+//
+// Enables the ADC for asynchronous operation
+//
+//*****************************************************************************
+void
+AUXADCEnableAsync(uint32_t refSource, uint32_t trigger)
+{
+ // Enable the ADC reference, with the following options:
+ // - SRC: Set when using relative reference
+ // - REF_ON_IDLE: Always cleared since there is no idle state in asynchronous operation
+ ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADCREF0, refSource | ADI_4_AUX_ADCREF0_EN_M);
+
+ // Enable the ADC clock
+ HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_ADCCLKCTL) = AUX_SYSIF_ADCCLKCTL_REQ_M;
+ while (!(HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_ADCCLKCTL) & AUX_SYSIF_ADCCLKCTL_ACK_M));
+
+ // Enable the ADC data interface
+ if (trigger == AUXADC_TRIGGER_MANUAL) {
+ // Manual trigger: No need to configure event routing from GPT
+ HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT | AUX_ANAIF_ADCCTL_CMD_EN;
+ } else {
+ // GPT trigger: Configure event routing via MCU_EV to the AUX domain
+ HWREG(EVENT_BASE + EVENT_O_AUXSEL0) = trigger;
+ HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_MCU_EV | AUX_ANAIF_ADCCTL_CMD_EN;
+ }
+
+ // Configure the ADC
+ ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_SMPL_MODE_M);
+
+ // Release reset and enable the ADC
+ ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_EN_M | ADI_4_AUX_ADC0_RESET_N_M);
+}
+
+//*****************************************************************************
+//
+// Enables the ADC for synchronous operation
+//
+//*****************************************************************************
+void
+AUXADCEnableSync(uint32_t refSource, uint32_t sampleTime, uint32_t trigger)
+{
+ // Enable the ADC reference, with the following options:
+ // - SRC: Set when using relative reference
+ // - REF_ON_IDLE: Set when using fixed reference and sample time < 21.3 us
+ uint8_t adcref0 = refSource | ADI_4_AUX_ADCREF0_EN_M;
+ if (!refSource && (sampleTime < AUXADC_SAMPLE_TIME_21P3_US)) {
+ adcref0 |= ADI_4_AUX_ADCREF0_REF_ON_IDLE_M;
+ }
+ ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADCREF0, adcref0);
+
+ // Enable the ADC clock
+ HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_ADCCLKCTL) = AUX_SYSIF_ADCCLKCTL_REQ_M;
+ while (!(HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_ADCCLKCTL) & AUX_SYSIF_ADCCLKCTL_ACK_M));
+
+ // Enable the ADC data interface
+ if (trigger == AUXADC_TRIGGER_MANUAL) {
+ // Manual trigger: No need to configure event routing from GPT
+ HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT | AUX_ANAIF_ADCCTL_CMD_EN;
+ } else {
+ // GPT trigger: Configure event routing via MCU_EV to the AUX domain
+ HWREG(EVENT_BASE + EVENT_O_AUXSEL0) = trigger;
+ HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_MCU_EV | AUX_ANAIF_ADCCTL_CMD_EN;
+ }
+
+ // Configure the ADC
+ ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, sampleTime << ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_S);
+
+ // Release reset and enable the ADC
+ ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_EN_M | ADI_4_AUX_ADC0_RESET_N_M);
+}
+
+//*****************************************************************************
+//
+// Disables scaling of the ADC input
+//
+//*****************************************************************************
+void
+AUXADCDisableInputScaling(void)
+{
+ ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC1, ADI_4_AUX_ADC1_SCALE_DIS_M);
+}
+
+//*****************************************************************************
+//
+// Flushes the ADC FIFO
+//
+//*****************************************************************************
+void
+AUXADCFlushFifo(void)
+{
+ HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 1; // CMD: EN(1) -> FLUSH(3)
+ HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 0; // CMD: FLUSH(3) -> EN(1)
+}
+
+//*****************************************************************************
+//
+// Waits for and returns the first sample in the ADC FIFO
+//
+//*****************************************************************************
+uint32_t
+AUXADCReadFifo(void) {
+
+ // Wait until there is at least one sample in the FIFO
+ while (HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFOSTAT) & AUX_ANAIF_ADCFIFOSTAT_EMPTY_M);
+
+ // Return the first sample from the FIFO
+ return HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFO);
+}
+
+//*****************************************************************************
+//
+// Returns the first sample in the ADC FIFO, without waiting
+//
+//*****************************************************************************
+uint32_t
+AUXADCPopFifo(void) {
+
+ // Return the first sample from the FIFO. If the FIFO is empty, this
+ // generates ADC FIFO underflow
+ return HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFO);
+}
+
+//*****************************************************************************
+//
+// Returns the gain value used when adjusting for ADC gain/offset
+//
+//*****************************************************************************
+int32_t
+AUXADCGetAdjustmentGain(uint32_t refSource)
+{
+ int32_t gain;
+ if (refSource == AUXADC_REF_FIXED) {
+ // AUXADC_REF_FIXED ==> ABS_GAIN
+ gain = (HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_ABS_GAIN) & FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_M) >> FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_S;
+ } else {
+ // AUXADC_REF_VDDS_REL ==> REL_GAIN
+ gain = (HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_REL_GAIN) & FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_M) >> FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_S;
+ }
+ return gain;
+}
+
+//*****************************************************************************
+//
+// Returns the offset value used when adjusting for ADC gain/offset
+//
+//*****************************************************************************
+int32_t
+AUXADCGetAdjustmentOffset(uint32_t refSource)
+{
+ int8_t offset;
+ if ( refSource == AUXADC_REF_FIXED ) {
+ // AUXADC_REF_FIXED ==> ABS_OFFSET
+ offset = HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_OFFSET_INT) >> FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_S;
+ } else {
+ // AUXADC_REF_VDDS_REL ==> REL_OFFSET
+ offset = HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_OFFSET_INT) >> FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_S;
+ }
+ return offset;
+}
+
+//*****************************************************************************
+//
+// Converts an "ideal" ADC value to microvolts
+//
+//*****************************************************************************
+int32_t
+AUXADCValueToMicrovolts(int32_t fixedRefVoltage, int32_t adcValue)
+{
+ // Chop off 4 bits during calculations to avoid 32-bit overflow
+ fixedRefVoltage >>= 4;
+ return (((adcValue * fixedRefVoltage) + 2047) / 4095) << 4;
+}
+
+//*****************************************************************************
+//
+// Converts a number of microvolts to corresponding "ideal" ADC value
+//
+//*****************************************************************************
+int32_t
+AUXADCMicrovoltsToValue(int32_t fixedRefVoltage, int32_t microvolts)
+{
+ // Chop off 4 bits during calculations to avoid 32-bit overflow
+ fixedRefVoltage >>= 4;
+ microvolts >>= 4;
+ return ((microvolts * 4095) + (fixedRefVoltage / 2)) / fixedRefVoltage;
+}
+
+//*****************************************************************************
+//
+// Performs ADC value gain and offset adjustment
+//
+//*****************************************************************************
+int32_t
+AUXADCAdjustValueForGainAndOffset(int32_t adcValue, int32_t gain, int32_t offset)
+{
+ // Apply gain and offset adjustment
+ adcValue = (((adcValue + offset) * gain) + 16384) / 32768;
+
+ // Saturate
+ if (adcValue < 0) {
+ return 0;
+ } else if (adcValue > 4095) {
+ return 4095;
+ } else {
+ return adcValue;
+ }
+}
+
+//*****************************************************************************
+//
+// Performs the inverse of the ADC value gain and offset adjustment
+//
+//*****************************************************************************
+int32_t
+AUXADCUnadjustValueForGainAndOffset(int32_t adcValue, int32_t gain, int32_t offset)
+{
+ // Apply inverse gain and offset adjustment
+ adcValue = (((adcValue * 32768) + (gain / 2)) / gain) - offset;
+
+ // Saturate
+ if (adcValue < 0) {
+ return 0;
+ } else if (adcValue > 4095) {
+ return 4095;
+ } else {
+ return adcValue;
+ }
+}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_adc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_adc.h
new file mode 100644
index 0000000..c87fd2f
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_adc.h
@@ -0,0 +1,599 @@
+/******************************************************************************
+* Filename: aux_adc.h
+* Revised: 2018-02-07 09:45:39 +0100 (Wed, 07 Feb 2018)
+* Revision: 51437
+*
+* Description: Defines and prototypes for the AUX Analog-to-Digital
+* Converter
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup aux_group
+//! @{
+//! \addtogroup auxadc_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __AUX_ADC_H__
+#define __AUX_ADC_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "../inc/hw_types.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_event.h"
+#include "../inc/hw_adi.h"
+#include "../inc/hw_adi_4_aux.h"
+#include "../inc/hw_aux_anaif.h"
+#include "rom.h"
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// This section renames all functions that are not "static inline", so that
+// calling these functions will default to implementation in flash. At the end
+// of this file a second renaming will change the defaults to implementation in
+// ROM for available functions.
+//
+// To force use of the implementation in flash, e.g. for debugging:
+// - Globally: Define DRIVERLIB_NOROM at project level
+// - Per function: Use prefix "NOROM_" when calling the function
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #define AUXADCDisable NOROM_AUXADCDisable
+ #define AUXADCEnableAsync NOROM_AUXADCEnableAsync
+ #define AUXADCEnableSync NOROM_AUXADCEnableSync
+ #define AUXADCDisableInputScaling NOROM_AUXADCDisableInputScaling
+ #define AUXADCFlushFifo NOROM_AUXADCFlushFifo
+ #define AUXADCReadFifo NOROM_AUXADCReadFifo
+ #define AUXADCPopFifo NOROM_AUXADCPopFifo
+ #define AUXADCGetAdjustmentGain NOROM_AUXADCGetAdjustmentGain
+ #define AUXADCGetAdjustmentOffset NOROM_AUXADCGetAdjustmentOffset
+ #define AUXADCValueToMicrovolts NOROM_AUXADCValueToMicrovolts
+ #define AUXADCMicrovoltsToValue NOROM_AUXADCMicrovoltsToValue
+ #define AUXADCAdjustValueForGainAndOffset NOROM_AUXADCAdjustValueForGainAndOffset
+ #define AUXADCUnadjustValueForGainAndOffset NOROM_AUXADCUnadjustValueForGainAndOffset
+#endif
+
+//*****************************************************************************
+//
+// Defines for ADC reference sources.
+//
+//*****************************************************************************
+#define AUXADC_REF_FIXED (0 << ADI_4_AUX_ADCREF0_SRC_S)
+#define AUXADC_REF_VDDS_REL (1 << ADI_4_AUX_ADCREF0_SRC_S)
+
+//*****************************************************************************
+//
+// Defines for the ADC FIFO status bits.
+//
+//*****************************************************************************
+#define AUXADC_FIFO_EMPTY_M (AUX_ANAIF_ADCFIFOSTAT_EMPTY_M)
+#define AUXADC_FIFO_ALMOST_FULL_M (AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_M)
+#define AUXADC_FIFO_FULL_M (AUX_ANAIF_ADCFIFOSTAT_FULL_M)
+#define AUXADC_FIFO_UNDERFLOW_M (AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_M)
+#define AUXADC_FIFO_OVERFLOW_M (AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_M)
+
+//*****************************************************************************
+//
+// Defines for supported ADC triggers.
+//
+//*****************************************************************************
+#define AUXADC_TRIGGER_MANUAL (EVENT_AUXSEL0_EV_NONE)
+#define AUXADC_TRIGGER_GPT0A (EVENT_AUXSEL0_EV_GPT0A)
+#define AUXADC_TRIGGER_GPT0B (EVENT_AUXSEL0_EV_GPT0B)
+#define AUXADC_TRIGGER_GPT1A (EVENT_AUXSEL0_EV_GPT1A)
+#define AUXADC_TRIGGER_GPT1B (EVENT_AUXSEL0_EV_GPT1B)
+#define AUXADC_TRIGGER_GPT2A (EVENT_AUXSEL0_EV_GPT2A)
+#define AUXADC_TRIGGER_GPT2B (EVENT_AUXSEL0_EV_GPT2B)
+#define AUXADC_TRIGGER_GPT3A (EVENT_AUXSEL0_EV_GPT3A)
+#define AUXADC_TRIGGER_GPT3B (EVENT_AUXSEL0_EV_GPT3B)
+// Additional triggers specific for cc26x2 and cc13x2 devices
+#define AUXADC_TRIGGER_GPT0A_CMP (EVENT_AUXSEL0_EV_GPT0A_CMP)
+#define AUXADC_TRIGGER_GPT0B_CMP (EVENT_AUXSEL0_EV_GPT0B_CMP)
+#define AUXADC_TRIGGER_GPT1A_CMP (EVENT_AUXSEL0_EV_GPT1A_CMP)
+#define AUXADC_TRIGGER_GPT1B_CMP (EVENT_AUXSEL0_EV_GPT1B_CMP)
+#define AUXADC_TRIGGER_GPT2A_CMP (EVENT_AUXSEL0_EV_GPT2A_CMP)
+#define AUXADC_TRIGGER_GPT2B_CMP (EVENT_AUXSEL0_EV_GPT2B_CMP)
+#define AUXADC_TRIGGER_GPT3A_CMP (EVENT_AUXSEL0_EV_GPT3A_CMP)
+#define AUXADC_TRIGGER_GPT3B_CMP (EVENT_AUXSEL0_EV_GPT3B_CMP)
+
+//*****************************************************************************
+//
+// Defines for ADC sampling type for synchronous operation.
+//
+//*****************************************************************************
+#define AUXADC_SAMPLE_TIME_2P7_US 3
+#define AUXADC_SAMPLE_TIME_5P3_US 4
+#define AUXADC_SAMPLE_TIME_10P6_US 5
+#define AUXADC_SAMPLE_TIME_21P3_US 6
+#define AUXADC_SAMPLE_TIME_42P6_US 7
+#define AUXADC_SAMPLE_TIME_85P3_US 8
+#define AUXADC_SAMPLE_TIME_170_US 9
+#define AUXADC_SAMPLE_TIME_341_US 10
+#define AUXADC_SAMPLE_TIME_682_US 11
+#define AUXADC_SAMPLE_TIME_1P37_MS 12
+#define AUXADC_SAMPLE_TIME_2P73_MS 13
+#define AUXADC_SAMPLE_TIME_5P46_MS 14
+#define AUXADC_SAMPLE_TIME_10P9_MS 15
+
+//*****************************************************************************
+//
+// Equivalent voltages for fixed ADC reference, in microvolts.
+//
+//*****************************************************************************
+#define AUXADC_FIXED_REF_VOLTAGE_NORMAL 4300000
+#define AUXADC_FIXED_REF_VOLTAGE_UNSCALED 1478500
+
+
+//*****************************************************************************
+//
+// API Functions and prototypes
+//
+//*****************************************************************************
+
+
+//*****************************************************************************
+//
+//! \brief Disables the ADC.
+//!
+//! This function must be called:
+//! - Before re-enabling the ADC using \ref AUXADCEnableAsync() or
+//! \ref AUXADCEnableSync()
+//! - Before entering system standby
+//
+//*****************************************************************************
+extern void AUXADCDisable(void);
+
+//*****************************************************************************
+//
+//! \brief Enables the ADC for asynchronous operation.
+//!
+//! In asynchronous operation, the ADC samples continuously between
+//! conversions.
+//!
+//! The ADC trigger starts the conversion. Note that the first conversion may
+//! be invalid if the sampling period is too short.
+//!
+//! ADC input scaling is enabled by default after device reset, and is also re-
+//! enabled by \ref AUXADCDisable(). To disable input scaling, call
+//! \ref AUXADCDisableInputScaling() before calling \ref AUXADCEnableAsync().
+//!
+//! \param refSource
+//! ADC reference source:
+//! - \ref AUXADC_REF_FIXED (nominally 4.3 V)
+//! - \ref AUXADC_REF_VDDS_REL (nominally VDDS)
+//! \param trigger
+//! ADC conversion trigger:
+//! - \ref AUXADC_TRIGGER_MANUAL
+//! - \ref AUXADC_TRIGGER_GPT0A
+//! - \ref AUXADC_TRIGGER_GPT0B
+//! - \ref AUXADC_TRIGGER_GPT1A
+//! - \ref AUXADC_TRIGGER_GPT1B
+//! - \ref AUXADC_TRIGGER_GPT2A
+//! - \ref AUXADC_TRIGGER_GPT2B
+//! - \ref AUXADC_TRIGGER_GPT3A
+//! - \ref AUXADC_TRIGGER_GPT3B
+//
+//*****************************************************************************
+extern void AUXADCEnableAsync(uint32_t refSource, uint32_t trigger);
+
+//*****************************************************************************
+//
+//! \brief Enables the ADC for synchronous operation.
+//!
+//! In synchronous operation, the ADC is idle between a conversion and
+//! subsequent samplings.
+//!
+//! The ADC trigger starts sampling with specified duration, followed by the
+//! conversion. Note that the first conversion may be invalid if the initial
+//! sampling period is too short.
+//!
+//! ADC input scaling is enabled by default after device reset, and is also re-
+//! enabled by \ref AUXADCDisable(). To disable input scaling, call
+//! \ref AUXADCDisableInputScaling() before calling \ref AUXADCEnableSync().
+//!
+//! \param refSource
+//! ADC reference source:
+//! - \ref AUXADC_REF_FIXED (nominally 4.3 V)
+//! - \ref AUXADC_REF_VDDS_REL (nominally VDDS)
+//! \param sampleTime
+//! ADC sampling time:
+//! - \ref AUXADC_SAMPLE_TIME_2P7_US
+//! - \ref AUXADC_SAMPLE_TIME_5P3_US
+//! - \ref AUXADC_SAMPLE_TIME_10P6_US
+//! - \ref AUXADC_SAMPLE_TIME_21P3_US
+//! - \ref AUXADC_SAMPLE_TIME_42P6_US
+//! - \ref AUXADC_SAMPLE_TIME_85P3_US
+//! - \ref AUXADC_SAMPLE_TIME_170_US
+//! - \ref AUXADC_SAMPLE_TIME_341_US
+//! - \ref AUXADC_SAMPLE_TIME_682_US
+//! - \ref AUXADC_SAMPLE_TIME_1P37_MS
+//! - \ref AUXADC_SAMPLE_TIME_2P73_MS
+//! - \ref AUXADC_SAMPLE_TIME_5P46_MS
+//! - \ref AUXADC_SAMPLE_TIME_10P9_MS
+//! \param trigger
+//! ADC conversion trigger:
+//! - \ref AUXADC_TRIGGER_MANUAL
+//! - \ref AUXADC_TRIGGER_GPT0A
+//! - \ref AUXADC_TRIGGER_GPT0B
+//! - \ref AUXADC_TRIGGER_GPT1A
+//! - \ref AUXADC_TRIGGER_GPT1B
+//! - \ref AUXADC_TRIGGER_GPT2A
+//! - \ref AUXADC_TRIGGER_GPT2B
+//! - \ref AUXADC_TRIGGER_GPT3A
+//! - \ref AUXADC_TRIGGER_GPT3B
+//
+//*****************************************************************************
+extern void AUXADCEnableSync(uint32_t refSource, uint32_t sampleTime, uint32_t trigger);
+
+//*****************************************************************************
+//
+//! \brief Disables scaling of the ADC input.
+//!
+//! By default, the ADC operates internally on a version of the input signal
+//! that has been scaled down by a factor <tt>1408 / 4095</tt>. This function
+//! disables that scaling, allowing for a trade-off between dynamic range and
+//! and resolution.
+//!
+//! \note This function must only be called while the ADC is disabled, before
+//! calling \ref AUXADCEnableSync() or \ref AUXADCEnableAsync().
+//! \note Different input maximum ratings apply when input scaling is disabled.
+//! Violating these may damage the device.
+//
+//*****************************************************************************
+extern void AUXADCDisableInputScaling(void);
+
+//*****************************************************************************
+//
+//! \brief Flushes the ADC FIFO.
+//!
+//! This empties the FIFO and clears the underflow/overflow flags.
+//!
+//! Note: This function must only be called while the ADC is enabled.
+//
+//*****************************************************************************
+extern void AUXADCFlushFifo(void);
+
+//*****************************************************************************
+//
+//! \brief Generates a single manual ADC trigger.
+//!
+//! For synchronous mode, the trigger starts sampling followed by conversion.
+//! For asynchronous mode, the trigger starts conversion.
+//
+//*****************************************************************************
+__STATIC_INLINE void
+AUXADCGenManualTrigger(void)
+{
+ HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCTRIG) = 0;
+}
+
+//*****************************************************************************
+//
+//! \brief Returns flags indicating the status of the ADC FIFO.
+//!
+//! The flags indicate FIFO empty, full and almost full, and whether
+//! overflow/underflow has occurred.
+//!
+//! \return
+//! A combination (bitwise OR) of the following flags:
+//! - \ref AUXADC_FIFO_EMPTY_M
+//! - \ref AUXADC_FIFO_ALMOST_FULL_M
+//! - \ref AUXADC_FIFO_FULL_M
+//! - \ref AUXADC_FIFO_UNDERFLOW_M
+//! - \ref AUXADC_FIFO_OVERFLOW_M
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+AUXADCGetFifoStatus(void)
+{
+ return HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFOSTAT);
+}
+
+//*****************************************************************************
+//
+//! \brief Waits for and returns the first sample in the ADC FIFO.
+//!
+//! This function waits until there is at least one sample in the ADC FIFO. It
+//! then pops and returns the first sample from the FIFO.
+//!
+//! \note This procedure will deadlock if called without setting up ADC trigger
+//! generation in advance. The trigger can either be manual or periodical
+//! (using a GPT).
+//!
+//! \return The first (12-bit) sample from the ADC FIFO
+//
+//*****************************************************************************
+extern uint32_t AUXADCReadFifo(void);
+
+//*****************************************************************************
+//
+//! \brief Returns the first sample in the ADC FIFO, without waiting.
+//!
+//! This function does not wait, and must only be called when there is at least
+//! one sample in the ADC FIFO. Otherwise the call will generate FIFO underflow
+//! (\ref AUXADC_FIFO_UNDERFLOW_M).
+//!
+//! \return The first (12-bit) sample from the ADC FIFO, or an undefined value
+//! if the FIFO is empty
+//
+//*****************************************************************************
+extern uint32_t AUXADCPopFifo(void);
+
+//*****************************************************************************
+//
+//! \brief Selects internal or external input for the ADC.
+//!
+//! Note that calling this function also selects the same input for AUX_COMPB.
+//!
+//! \param input
+//! Internal/external input selection:
+//! - \ref ADC_COMPB_IN_DCOUPL
+//! - \ref ADC_COMPB_IN_VSS
+//! - \ref ADC_COMPB_IN_VDDS
+//! - \ref ADC_COMPB_IN_AUXIO7
+//! - \ref ADC_COMPB_IN_AUXIO6
+//! - \ref ADC_COMPB_IN_AUXIO5
+//! - \ref ADC_COMPB_IN_AUXIO4
+//! - \ref ADC_COMPB_IN_AUXIO3
+//! - \ref ADC_COMPB_IN_AUXIO2
+//! - \ref ADC_COMPB_IN_AUXIO1
+//! - \ref ADC_COMPB_IN_AUXIO0
+//
+//*****************************************************************************
+__STATIC_INLINE void
+AUXADCSelectInput(uint32_t input)
+{
+ HapiSelectADCCompBInput(input);
+}
+
+//*****************************************************************************
+//
+//! \brief Returns the gain value used when adjusting for ADC gain/offset.
+//!
+//! The function returns the gain value to be used with
+//! \ref AUXADCAdjustValueForGainAndOffset() or
+//! \ref AUXADCUnadjustValueForGainAndOffset(). The gain value is found during
+//! chip manufacturing and is stored in the factory configuration, FCFG1.
+//!
+//! \param refSource
+//! ADC reference source:
+//! - \ref AUXADC_REF_FIXED (nominally 4.3 V)
+//! - \ref AUXADC_REF_VDDS_REL (nominally VDDS)
+//!
+//! \return
+//! The gain value to be used in adjustments
+//
+//*****************************************************************************
+extern int32_t AUXADCGetAdjustmentGain(uint32_t refSource);
+
+//*****************************************************************************
+//
+//! \brief Returns the offset value used when adjusting for ADC gain/offset.
+//!
+//! The function returns the offset value to be used with
+//! \ref AUXADCAdjustValueForGainAndOffset() or
+//! \ref AUXADCUnadjustValueForGainAndOffset(). The offset value is found
+//! during chip manufacturing and is stored in the factory configuration,
+//! FCFG1.
+//!
+//! \param refSource
+//! ADC reference source:
+//! - \ref AUXADC_REF_FIXED (nominally 4.3 V)
+//! - \ref AUXADC_REF_VDDS_REL (nominally VDDS)
+//!
+//! \return
+//! The offset value to be used in adjustments
+//
+//*****************************************************************************
+extern int32_t AUXADCGetAdjustmentOffset(uint32_t refSource);
+
+//*****************************************************************************
+//
+//! \brief Converts an "adjusted" ADC value to microvolts.
+//!
+//! This function can only be used when measuring with fixed ADC reference
+//! (\ref AUXADC_REF_FIXED). The specified reference voltage accounts for
+//! whether the sampled ADC input is scaled down before conversion or not.
+//!
+//! \param fixedRefVoltage
+//! Fixed reference voltage, in microvolts
+//! - \ref AUXADC_FIXED_REF_VOLTAGE_NORMAL when using scaled input (normal)
+//! - \ref AUXADC_FIXED_REF_VOLTAGE_UNSCALED when using unscaled input
+//! \param adcValue
+//! The ADC value
+//!
+//! \return
+//! The corresponding number of microvolts
+//
+//*****************************************************************************
+extern int32_t AUXADCValueToMicrovolts(int32_t fixedRefVoltage, int32_t adcValue);
+
+//*****************************************************************************
+//
+//! \brief Converts a number of microvolts to corresponding "adjusted" ADC value.
+//!
+//! This function can only be used when measuring with fixed ADC reference
+//! (\ref AUXADC_REF_FIXED). The specified reference voltage accounts for
+//! whether the sampled ADC input is scaled down before conversion or not.
+//!
+//! \param fixedRefVoltage
+//! Fixed reference voltage, in microvolts
+//! - \ref AUXADC_FIXED_REF_VOLTAGE_NORMAL when using scaled input (normal)
+//! - \ref AUXADC_FIXED_REF_VOLTAGE_UNSCALED when using unscaled input
+//! \param microvolts
+//! The number of microvolts
+//!
+//! \return
+//! The corresponding expected ADC value (adjusted for ADC gain/offset)
+//
+//*****************************************************************************
+extern int32_t AUXADCMicrovoltsToValue(int32_t fixedRefVoltage, int32_t microvolts);
+
+//*****************************************************************************
+//
+//! \brief Performs ADC value gain and offset adjustment.
+//!
+//! This function takes a measured ADC value compensates for the internal gain
+//! and offset in the ADC.
+//!
+//! \param adcValue
+//! 12-bit ADC unadjusted value
+//! \param gain
+//! Gain adjustment value provided by \ref AUXADCGetAdjustmentGain()
+//! \param offset
+//! Offset adjustment value provided by \ref AUXADCGetAdjustmentOffset()
+//!
+//! \return
+//! 12-bit ADC adjusted value
+//
+//*****************************************************************************
+extern int32_t AUXADCAdjustValueForGainAndOffset(int32_t adcValue, int32_t gain, int32_t offset);
+
+//*****************************************************************************
+//
+//! \brief Performs the inverse of the ADC value gain and offset adjustment.
+//!
+//! This function finds the expected measured ADC value, without gain and
+//! offset compensation, for a given "ideal" ADC value. The function can for
+//! example be used to find ADC value thresholds to be used in Sensor
+//! Controller task configurations.
+//!
+//! \param adcValue
+//! 12-bit ADC adjusted value
+//! \param gain
+//! Gain adjustment value provided by \ref AUXADCGetAdjustmentGain()
+//! \param offset
+//! Offset adjustment value provided by \ref AUXADCGetAdjustmentOffset()
+//!
+//! \return
+//! 12-bit ADC unadjusted value
+//
+//*****************************************************************************
+extern int32_t AUXADCUnadjustValueForGainAndOffset(int32_t adcValue, int32_t gain, int32_t offset);
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// Redirect to implementation in ROM when available.
+//
+//*****************************************************************************
+#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
+ #include "../driverlib/rom.h"
+ #ifdef ROM_AUXADCDisable
+ #undef AUXADCDisable
+ #define AUXADCDisable ROM_AUXADCDisable
+ #endif
+ #ifdef ROM_AUXADCEnableAsync
+ #undef AUXADCEnableAsync
+ #define AUXADCEnableAsync ROM_AUXADCEnableAsync
+ #endif
+ #ifdef ROM_AUXADCEnableSync
+ #undef AUXADCEnableSync
+ #define AUXADCEnableSync ROM_AUXADCEnableSync
+ #endif
+ #ifdef ROM_AUXADCDisableInputScaling
+ #undef AUXADCDisableInputScaling
+ #define AUXADCDisableInputScaling ROM_AUXADCDisableInputScaling
+ #endif
+ #ifdef ROM_AUXADCFlushFifo
+ #undef AUXADCFlushFifo
+ #define AUXADCFlushFifo ROM_AUXADCFlushFifo
+ #endif
+ #ifdef ROM_AUXADCReadFifo
+ #undef AUXADCReadFifo
+ #define AUXADCReadFifo ROM_AUXADCReadFifo
+ #endif
+ #ifdef ROM_AUXADCPopFifo
+ #undef AUXADCPopFifo
+ #define AUXADCPopFifo ROM_AUXADCPopFifo
+ #endif
+ #ifdef ROM_AUXADCGetAdjustmentGain
+ #undef AUXADCGetAdjustmentGain
+ #define AUXADCGetAdjustmentGain ROM_AUXADCGetAdjustmentGain
+ #endif
+ #ifdef ROM_AUXADCGetAdjustmentOffset
+ #undef AUXADCGetAdjustmentOffset
+ #define AUXADCGetAdjustmentOffset ROM_AUXADCGetAdjustmentOffset
+ #endif
+ #ifdef ROM_AUXADCValueToMicrovolts
+ #undef AUXADCValueToMicrovolts
+ #define AUXADCValueToMicrovolts ROM_AUXADCValueToMicrovolts
+ #endif
+ #ifdef ROM_AUXADCMicrovoltsToValue
+ #undef AUXADCMicrovoltsToValue
+ #define AUXADCMicrovoltsToValue ROM_AUXADCMicrovoltsToValue
+ #endif
+ #ifdef ROM_AUXADCAdjustValueForGainAndOffset
+ #undef AUXADCAdjustValueForGainAndOffset
+ #define AUXADCAdjustValueForGainAndOffset ROM_AUXADCAdjustValueForGainAndOffset
+ #endif
+ #ifdef ROM_AUXADCUnadjustValueForGainAndOffset
+ #undef AUXADCUnadjustValueForGainAndOffset
+ #define AUXADCUnadjustValueForGainAndOffset ROM_AUXADCUnadjustValueForGainAndOffset
+ #endif
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __AUX_ADC_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_smph.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_smph.c
new file mode 100644
index 0000000..a5d3f08
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_smph.c
@@ -0,0 +1,41 @@
+/******************************************************************************
+* Filename: aux_smph.c
+* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016)
+* Revision: 47179
+*
+* Description: Driver for the AUX Semaphore.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "aux_smph.h"
+
+// See aux_smph.h for implementation
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_smph.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_smph.h
new file mode 100644
index 0000000..d2d6d4d
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_smph.h
@@ -0,0 +1,258 @@
+/******************************************************************************
+* Filename: aux_smph.h
+* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016)
+* Revision: 47343
+*
+* Description: Defines and prototypes for the AUX Semaphore
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup aux_group
+//! @{
+//! \addtogroup auxsmph_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __AUX_SMPH_H__
+#define __AUX_SMPH_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "../inc/hw_types.h"
+#include "../inc/hw_aux_smph.h"
+#include "../inc/hw_memmap.h"
+#include "debug.h"
+
+//*****************************************************************************
+//
+// General constants and defines
+//
+//*****************************************************************************
+#define AUX_SMPH_FREE 0x00000001 // MCU Semaphore has not been claimed
+#define AUX_SMPH_CLAIMED 0x00000000 // MCU Semaphore has been claimed
+
+//*****************************************************************************
+//
+// Values that can be passed to AUXSMPHAcquire and AUXSMPHRelease
+// as the ui32Semaphore parameter.
+//
+//*****************************************************************************
+#define AUX_SMPH_0 0 // AUX Semaphore 0
+#define AUX_SMPH_1 1 // AUX Semaphore 1
+#define AUX_SMPH_2 2 // AUX Semaphore 2
+#define AUX_SMPH_3 3 // AUX Semaphore 3
+#define AUX_SMPH_4 4 // AUX Semaphore 4
+#define AUX_SMPH_5 5 // AUX Semaphore 5
+#define AUX_SMPH_6 6 // AUX Semaphore 6
+#define AUX_SMPH_7 7 // AUX Semaphore 7
+
+//*****************************************************************************
+//
+// API Functions and prototypes
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \brief Acquire an AUX semaphore.
+//!
+//! This function acquires the given AUX semaphore, blocking the call until
+//! the semaphore is available.
+//!
+//! \note The semaphore can also be acquired by the dedicated Sensor Controller.
+//! The System CPU master can thus be competing for the shared resource, i.e.
+//! the specified semaphore.
+//!
+//! \param ui32Semaphore is the semaphore number.
+//! - \ref AUX_SMPH_0
+//! - \ref AUX_SMPH_1
+//! - \ref AUX_SMPH_2
+//! - \ref AUX_SMPH_3
+//! - \ref AUX_SMPH_4
+//! - \ref AUX_SMPH_5
+//! - \ref AUX_SMPH_6
+//! - \ref AUX_SMPH_7
+//!
+//! \return None
+//!
+//! \sa AUXSMPHTryAcquire(), AUXSMPHRelease()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+AUXSMPHAcquire(uint32_t ui32Semaphore)
+{
+ // Check the arguments.
+ ASSERT((ui32Semaphore == AUX_SMPH_0) ||
+ (ui32Semaphore == AUX_SMPH_1) ||
+ (ui32Semaphore == AUX_SMPH_2) ||
+ (ui32Semaphore == AUX_SMPH_3) ||
+ (ui32Semaphore == AUX_SMPH_4) ||
+ (ui32Semaphore == AUX_SMPH_5) ||
+ (ui32Semaphore == AUX_SMPH_6) ||
+ (ui32Semaphore == AUX_SMPH_7));
+
+ // Wait for semaphore to be released such that it can be claimed
+ // Semaphore register reads 1 when lock was acquired otherwise 0
+ // (i.e. AUX_SMPH_CLAIMED).
+ while(HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 + 4 * ui32Semaphore) ==
+ AUX_SMPH_CLAIMED)
+ {
+ }
+}
+
+//*****************************************************************************
+//
+//! \brief Try to acquire an AUX semaphore.
+//!
+//! This function tries to acquire the given AUX semaphore, if the semaphore
+//! could not be claimed the function returns false.
+//!
+//! \note The semaphore can also be acquired by the dedicated Sensor Controller.
+//! The System CPU master can thus be competing for the shared resource, i.e.
+//! the specified semaphore.
+//!
+//! \param ui32Semaphore is the semaphore number.
+//! - \ref AUX_SMPH_0
+//! - \ref AUX_SMPH_1
+//! - \ref AUX_SMPH_2
+//! - \ref AUX_SMPH_3
+//! - \ref AUX_SMPH_4
+//! - \ref AUX_SMPH_5
+//! - \ref AUX_SMPH_6
+//! - \ref AUX_SMPH_7
+//!
+//! \return Returns true if semaphore was acquired, false otherwise
+//!
+//! \sa AUXSMPHAcquire(), AUXSMPHRelease()
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+AUXSMPHTryAcquire(uint32_t ui32Semaphore)
+{
+ uint32_t ui32SemaReg;
+
+ // Check the arguments.
+ ASSERT((ui32Semaphore == AUX_SMPH_0) ||
+ (ui32Semaphore == AUX_SMPH_1) ||
+ (ui32Semaphore == AUX_SMPH_2) ||
+ (ui32Semaphore == AUX_SMPH_3) ||
+ (ui32Semaphore == AUX_SMPH_4) ||
+ (ui32Semaphore == AUX_SMPH_5) ||
+ (ui32Semaphore == AUX_SMPH_6) ||
+ (ui32Semaphore == AUX_SMPH_7));
+
+ // AUX Semaphore register reads 1 if lock was acquired
+ // (i.e. SMPH_FREE when read) but subsequent reads will read 0.
+ ui32SemaReg = HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 + 4 * ui32Semaphore);
+
+ return (ui32SemaReg == AUX_SMPH_FREE);
+}
+
+//*****************************************************************************
+//
+//! \brief Release an AUX semaphore by System CPU master.
+//!
+//! This function releases the given AUX semaphore.
+//!
+//! \note It is up to the application to provide the convention for clearing
+//! semaphore.
+//!
+//! \note The semaphore can also be acquired by the dedicated Sensor Controller.
+//! The System CPU master can thus be competing for the shared resource, i.e.
+//! the specified semaphore.
+//!
+//! \param ui32Semaphore is the semaphore number.
+//! - \ref AUX_SMPH_0
+//! - \ref AUX_SMPH_1
+//! - \ref AUX_SMPH_2
+//! - \ref AUX_SMPH_3
+//! - \ref AUX_SMPH_4
+//! - \ref AUX_SMPH_5
+//! - \ref AUX_SMPH_6
+//! - \ref AUX_SMPH_7
+//!
+//! \return None
+//!
+//! \sa AUXSMPHAcquire(), AUXSMPHTryAcquire()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+AUXSMPHRelease(uint32_t ui32Semaphore)
+{
+ // Check the arguments.
+ ASSERT((ui32Semaphore == AUX_SMPH_0) ||
+ (ui32Semaphore == AUX_SMPH_1) ||
+ (ui32Semaphore == AUX_SMPH_2) ||
+ (ui32Semaphore == AUX_SMPH_3) ||
+ (ui32Semaphore == AUX_SMPH_4) ||
+ (ui32Semaphore == AUX_SMPH_5) ||
+ (ui32Semaphore == AUX_SMPH_6) ||
+ (ui32Semaphore == AUX_SMPH_7));
+
+ // No check before release. It is up to the application to provide the
+ // conventions for who and when a semaphore can be released.
+ HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 + 4 * ui32Semaphore) =
+ AUX_SMPH_FREE;
+}
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __AUX_SMPH_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_sysif.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_sysif.c
new file mode 100644
index 0000000..5e3e90b
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_sysif.c
@@ -0,0 +1,96 @@
+/******************************************************************************
+* Filename: aux_sysif.c
+* Revised: 2018-04-17 14:54:06 +0200 (Tue, 17 Apr 2018)
+* Revision: 51890
+*
+* Description: Driver for the AUX System Interface
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "aux_sysif.h"
+
+//*****************************************************************************
+//
+// Handle support for DriverLib in ROM:
+// This section will undo prototype renaming made in the header file
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #undef AUXSYSIFOpModeChange
+ #define AUXSYSIFOpModeChange NOROM_AUXSYSIFOpModeChange
+#endif
+
+
+//*****************************************************************************
+//
+// Used in AUXSYSIFOpModeChange() to control the change of the operational mode.
+//
+//*****************************************************************************
+static const uint8_t g_OpMode_to_order[4] = {1,2,0,3};
+static const uint8_t g_Order_to_OpMode[4] = {2,0,1,3};
+
+//*****************************************************************************
+//
+// Controls AUX operational mode change
+//
+//*****************************************************************************
+void
+AUXSYSIFOpModeChange(uint32_t targetOpMode)
+{
+ uint32_t currentOpMode;
+ uint32_t currentOrder;
+ uint32_t nextMode;
+
+ // Check the argument
+ ASSERT((targetOpMode == AUX_SYSIF_OPMODEREQ_REQ_PDLP)||
+ (targetOpMode == AUX_SYSIF_OPMODEREQ_REQ_PDA) ||
+ (targetOpMode == AUX_SYSIF_OPMODEREQ_REQ_LP) ||
+ (targetOpMode == AUX_SYSIF_OPMODEREQ_REQ_A));
+
+ do {
+ currentOpMode = HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_OPMODEREQ);
+ while ( currentOpMode != HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_OPMODEACK));
+ if (currentOpMode != targetOpMode)
+ {
+ currentOrder = g_OpMode_to_order[currentOpMode];
+ if ( currentOrder < g_OpMode_to_order[targetOpMode])
+ {
+ nextMode = g_Order_to_OpMode[currentOrder + 1];
+ }
+ else
+ {
+ nextMode = g_Order_to_OpMode[currentOrder - 1];
+ }
+ HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_OPMODEREQ) = nextMode;
+ }
+ } while ( currentOpMode != targetOpMode );
+}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_sysif.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_sysif.h
new file mode 100644
index 0000000..04214bc
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_sysif.h
@@ -0,0 +1,154 @@
+/******************************************************************************
+* Filename: aux_sysif.h
+* Revised: 2017-06-27 08:41:49 +0200 (Tue, 27 Jun 2017)
+* Revision: 49245
+*
+* Description: Defines and prototypes for the AUX System Interface
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup aux_group
+//! @{
+//! \addtogroup auxsysif_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __AUX_SYSIF_H__
+#define __AUX_SYSIF_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "../inc/hw_types.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_aux_sysif.h"
+#include "debug.h"
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// This section renames all functions that are not "static inline", so that
+// calling these functions will default to implementation in flash. At the end
+// of this file a second renaming will change the defaults to implementation in
+// ROM for available functions.
+//
+// To force use of the implementation in flash, e.g. for debugging:
+// - Globally: Define DRIVERLIB_NOROM at project level
+// - Per function: Use prefix "NOROM_" when calling the function
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #define AUXSYSIFOpModeChange NOROM_AUXSYSIFOpModeChange
+#endif
+
+
+//*****************************************************************************
+//
+// API Functions and prototypes
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Defines for AUX operational modes.
+//
+//*****************************************************************************
+#define AUX_SYSIF_OPMODE_TARGET_PDLP (AUX_SYSIF_OPMODEREQ_REQ_PDLP)
+#define AUX_SYSIF_OPMODE_TARGET_PDA (AUX_SYSIF_OPMODEREQ_REQ_PDA)
+#define AUX_SYSIF_OPMODE_TARGET_LP (AUX_SYSIF_OPMODEREQ_REQ_LP)
+#define AUX_SYSIF_OPMODE_TARGET_A (AUX_SYSIF_OPMODEREQ_REQ_A)
+
+//*****************************************************************************
+//
+//! \brief Changes the AUX operational mode to the requested target mode.
+//!
+//! This function controls the change of the AUX operational mode.
+//! The function controls the change of the current operational mode to the
+//! operational mode target by adhering to rules specified by HW.
+//!
+//! \param targetOpMode
+//! AUX operational mode:
+//! - \ref AUX_SYSIF_OPMODE_TARGET_PDLP (Powerdown operational mode with wakeup to lowpower mode)
+//! - \ref AUX_SYSIF_OPMODE_TARGET_PDA (Powerdown operational mode with wakeup to active mode)
+//! - \ref AUX_SYSIF_OPMODE_TARGET_LP (Lowpower operational mode)
+//! - \ref AUX_SYSIF_OPMODE_TARGET_A (Active operational mode)
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void AUXSYSIFOpModeChange(uint32_t targetOpMode);
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// Redirect to implementation in ROM when available.
+//
+//*****************************************************************************
+#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
+ #include "../driverlib/rom.h"
+ #ifdef ROM_AUXSYSIFOpModeChange
+ #undef AUXSYSIFOpModeChange
+ #define AUXSYSIFOpModeChange ROM_AUXSYSIFOpModeChange
+ #endif
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __AUX_SYSIF_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_tdc.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_tdc.c
new file mode 100644
index 0000000..6bbcf55
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_tdc.c
@@ -0,0 +1,111 @@
+/******************************************************************************
+* Filename: aux_tdc.c
+* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017)
+* Revision: 48852
+*
+* Description: Driver for the AUX Time to Digital Converter interface.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "aux_tdc.h"
+
+//*****************************************************************************
+//
+// Handle support for DriverLib in ROM:
+// This section will undo prototype renaming made in the header file
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #undef AUXTDCConfigSet
+ #define AUXTDCConfigSet NOROM_AUXTDCConfigSet
+ #undef AUXTDCMeasurementDone
+ #define AUXTDCMeasurementDone NOROM_AUXTDCMeasurementDone
+#endif
+
+//*****************************************************************************
+//
+// Configure the operation of the AUX TDC
+//
+//*****************************************************************************
+void
+AUXTDCConfigSet(uint32_t ui32Base, uint32_t ui32StartCondition,
+ uint32_t ui32StopCondition)
+{
+ // Check the arguments.
+ ASSERT(AUXTDCBaseValid(ui32Base));
+
+ // Make sure the AUX TDC is in the idle state before changing the
+ // configuration.
+ while(!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) ==
+ AUX_TDC_STAT_STATE_IDLE))
+ {
+ }
+
+ // Clear previous results.
+ HWREG(ui32Base + AUX_TDC_O_CTL) = 0x0;
+
+ // Change the configuration.
+ HWREG(ui32Base + AUX_TDC_O_TRIGSRC) = ui32StartCondition | ui32StopCondition;
+}
+
+//*****************************************************************************
+//
+// Check if the AUX TDC is done measuring
+//
+//*****************************************************************************
+uint32_t
+AUXTDCMeasurementDone(uint32_t ui32Base)
+{
+ uint32_t ui32Reg;
+ uint32_t ui32Status;
+
+ // Check the arguments.
+ ASSERT(AUXTDCBaseValid(ui32Base));
+
+ // Check if the AUX TDC is done measuring.
+ ui32Reg = HWREG(ui32Base + AUX_TDC_O_STAT);
+ if(ui32Reg & AUX_TDC_STAT_DONE)
+ {
+ ui32Status = AUX_TDC_DONE;
+ }
+ else if(ui32Reg & AUX_TDC_STAT_SAT)
+ {
+ ui32Status = AUX_TDC_TIMEOUT;
+ }
+ else
+ {
+ ui32Status = AUX_TDC_BUSY;
+ }
+
+ // Return the status.
+ return (ui32Status);
+}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_tdc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_tdc.h
new file mode 100644
index 0000000..402c834
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_tdc.h
@@ -0,0 +1,904 @@
+/******************************************************************************
+* Filename: aux_tdc.h
+* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017)
+* Revision: 49096
+*
+* Description: Defines and prototypes for the AUX Time-to-Digital Converter
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup aux_group
+//! @{
+//! \addtogroup auxtdc_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __AUX_TDC_H__
+#define __AUX_TDC_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "../inc/hw_types.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_ints.h"
+#include "../inc/hw_aux_tdc.h"
+#include "debug.h"
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// This section renames all functions that are not "static inline", so that
+// calling these functions will default to implementation in flash. At the end
+// of this file a second renaming will change the defaults to implementation in
+// ROM for available functions.
+//
+// To force use of the implementation in flash, e.g. for debugging:
+// - Globally: Define DRIVERLIB_NOROM at project level
+// - Per function: Use prefix "NOROM_" when calling the function
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #define AUXTDCConfigSet NOROM_AUXTDCConfigSet
+ #define AUXTDCMeasurementDone NOROM_AUXTDCMeasurementDone
+#endif
+
+//*****************************************************************************
+//
+// Defines for the status of a AUX TDC measurement.
+//
+//*****************************************************************************
+#define AUX_TDC_BUSY 0x00000001
+#define AUX_TDC_TIMEOUT 0x00000002
+#define AUX_TDC_DONE 0x00000004
+
+//*****************************************************************************
+//
+// Defines for the control of a AUX TDC.
+//
+//*****************************************************************************
+#define AUX_TDC_RUNSYNC 0x00000001
+#define AUX_TDC_RUN 0x00000002
+#define AUX_TDC_ABORT 0x00000003
+
+//*****************************************************************************
+//
+// Defines for possible states of the TDC internal state machine.
+//
+//*****************************************************************************
+#define AUXTDC_WAIT_START (AUX_TDC_STAT_STATE_WAIT_START)
+#define AUXTDC_WAIT_START_CNTEN (AUX_TDC_STAT_STATE_WAIT_START_STOP_CNT_EN)
+#define AUXTDC_IDLE (AUX_TDC_STAT_STATE_IDLE)
+#define AUXTDC_CLRCNT (AUX_TDC_STAT_STATE_CLR_CNT)
+#define AUXTDC_WAIT_STOP (AUX_TDC_STAT_STATE_WAIT_STOP)
+#define AUXTDC_WAIT_STOP_CNTDOWN (AUX_TDC_STAT_STATE_WAIT_STOP_CNTDWN)
+#define AUXTDC_GETRESULTS (AUX_TDC_STAT_STATE_GET_RESULT)
+#define AUXTDC_POR (AUX_TDC_STAT_STATE_POR)
+#define AUXTDC_WAIT_CLRCNT_DONE (AUX_TDC_STAT_STATE_WAIT_CLR_CNT_DONE)
+#define AUXTDC_START_FALL (AUX_TDC_STAT_STATE_START_FALL)
+#define AUXTDC_FORCE_STOP (AUX_TDC_STAT_STATE_FORCE_STOP)
+
+//*****************************************************************************
+//
+// Defines for controlling the AUX TDC. Values can be passed to AUXTDCConfigSet().
+//
+//*****************************************************************************
+#define AUXTDC_STOPPOL_RIS (AUX_TDC_TRIGSRC_STOP_POL_HIGH) // Rising edge polarity for stop event
+#define AUXTDC_STOPPOL_FALL (AUX_TDC_TRIGSRC_STOP_POL_LOW) // Falling edge polarity for stop event
+
+#define AUXTDC_STOP_AUXIO0 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO0)
+#define AUXTDC_STOP_AUXIO1 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO1)
+#define AUXTDC_STOP_AUXIO2 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO2)
+#define AUXTDC_STOP_AUXIO3 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO3)
+#define AUXTDC_STOP_AUXIO4 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO4)
+#define AUXTDC_STOP_AUXIO5 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO5)
+#define AUXTDC_STOP_AUXIO6 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO6)
+#define AUXTDC_STOP_AUXIO7 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO7)
+#define AUXTDC_STOP_AUXIO8 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO8)
+#define AUXTDC_STOP_AUXIO9 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO9)
+#define AUXTDC_STOP_AUXIO10 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO10)
+#define AUXTDC_STOP_AUXIO11 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO11)
+#define AUXTDC_STOP_AUXIO12 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO12)
+#define AUXTDC_STOP_AUXIO13 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO13)
+#define AUXTDC_STOP_AUXIO14 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO14)
+#define AUXTDC_STOP_AUXIO15 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO15)
+#define AUXTDC_STOP_AUXIO16 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO16)
+#define AUXTDC_STOP_AUXIO17 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO17)
+#define AUXTDC_STOP_AUXIO18 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO18)
+#define AUXTDC_STOP_AUXIO19 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO19)
+#define AUXTDC_STOP_AUXIO20 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO20)
+#define AUXTDC_STOP_AUXIO21 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO21)
+#define AUXTDC_STOP_AUXIO22 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO22)
+#define AUXTDC_STOP_AUXIO23 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO23)
+#define AUXTDC_STOP_AUXIO24 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO24)
+#define AUXTDC_STOP_AUXIO25 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO25)
+#define AUXTDC_STOP_AUXIO26 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO26)
+#define AUXTDC_STOP_AUXIO27 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO27)
+#define AUXTDC_STOP_AUXIO28 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO28)
+#define AUXTDC_STOP_AUXIO29 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO29)
+#define AUXTDC_STOP_AUXIO30 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO30)
+#define AUXTDC_STOP_AUXIO31 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO31)
+#define AUXTDC_STOP_MANUAL_EV (AUX_TDC_TRIGSRC_STOP_SRC_MANUAL_EV)
+#define AUXTDC_STOP_AON_RTC_CH2_DLY (AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2_DLY)
+#define AUXTDC_STOP_AON_RTC_4KHZ (AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_4KHZ)
+#define AUXTDC_STOP_AON_BATMON_BAT_UPD (AUX_TDC_TRIGSRC_STOP_SRC_AON_BATMON_BAT_UPD)
+#define AUXTDC_STOP_AON_BATMON_TEMP_UPD (AUX_TDC_TRIGSRC_STOP_SRC_AON_BATMON_TEMP_UPD)
+#define AUXTDC_STOP_SCLK_LF (AUX_TDC_TRIGSRC_STOP_SRC_SCLK_LF)
+#define AUXTDC_STOP_PWR_DWN (AUX_TDC_TRIGSRC_STOP_SRC_PWR_DWN)
+#define AUXTDC_STOP_MCU_ACTIVE (AUX_TDC_TRIGSRC_STOP_SRC_MCU_ACTIVE)
+#define AUXTDC_STOP_VDDR_RECHARGE (AUX_TDC_TRIGSRC_STOP_SRC_VDDR_RECHARGE)
+#define AUXTDC_STOP_TIMER2_EV0 (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV0)
+#define AUXTDC_STOP_TIMER2_EV1 (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV1)
+#define AUXTDC_STOP_TIMER2_EV2 (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV2)
+#define AUXTDC_STOP_TIMER2_EV3 (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV3)
+#define AUXTDC_STOP_TIMER2_PULSE (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_PULSE)
+#define AUXTDC_STOP_TDC_DONE (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TDC_DONE)
+#define AUXTDC_STOP_ADC_IRQ (AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_IRQ)
+#define AUXTDC_STOP_ADC_FIFO_NOT_EMPTY (AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_FIFO_NOT_EMPTY)
+#define AUXTDC_STOP_NO_EVENT (AUX_TDC_TRIGSRC_STOP_SRC_NO_EVENT)
+#define AUXTDC_STOP_ADC_DONE (AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_DONE)
+#define AUXTDC_STOP_ADC_FIFO_ALMOST_FULL (AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_FIFO_ALMOST_FULL)
+#define AUXTDC_STOP_ISRC_RESET (AUX_TDC_TRIGSRC_STOP_SRC_AUX_ISRC_RESET_N)
+#define AUXTDC_STOP_OBSMUX0 (AUX_TDC_TRIGSRC_STOP_SRC_MCU_OBSMUX0)
+#define AUXTDC_STOP_OBSMUX1 (AUX_TDC_TRIGSRC_STOP_SRC_MCU_OBSMUX1)
+#define AUXTDC_STOP_SMPH_AUTOTAKE_DONE (AUX_TDC_TRIGSRC_STOP_SRC_AUX_SMPH_AUTOTAKE_DONE)
+#define AUXTDC_STOP_TDC_PRE (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TDC_PRE)
+#define AUXTDC_STOP_TIMER0_EV (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER0_EV)
+#define AUXTDC_STOP_TIMER1_EV (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER1_EV)
+#define AUXTDC_STOP_AON_RTC_CH2 (AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2)
+#define AUXTDC_STOP_AUX_COMPA (AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPA)
+#define AUXTDC_STOP_AUX_COMPB (AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPB)
+#define AUXTDC_STOP_ACLK_REF (AUX_TDC_TRIGSRC_STOP_SRC_ACLK_REF)
+#define AUXTDC_STOP_MCU_EV (AUX_TDC_TRIGSRC_STOP_SRC_MCU_EV)
+
+#define AUXTDC_STARTPOL_RIS (AUX_TDC_TRIGSRC_START_POL_HIGH) // Rising edge polarity for start event
+#define AUXTDC_STARTPOL_FALL (AUX_TDC_TRIGSRC_START_POL_LOW) // Falling edge polarity for start event
+
+#define AUXTDC_START_AUXIO0 (AUX_TDC_TRIGSRC_START_SRC_AUXIO0)
+#define AUXTDC_START_AUXIO1 (AUX_TDC_TRIGSRC_START_SRC_AUXIO1)
+#define AUXTDC_START_AUXIO2 (AUX_TDC_TRIGSRC_START_SRC_AUXIO2)
+#define AUXTDC_START_AUXIO3 (AUX_TDC_TRIGSRC_START_SRC_AUXIO3)
+#define AUXTDC_START_AUXIO4 (AUX_TDC_TRIGSRC_START_SRC_AUXIO4)
+#define AUXTDC_START_AUXIO5 (AUX_TDC_TRIGSRC_START_SRC_AUXIO5)
+#define AUXTDC_START_AUXIO6 (AUX_TDC_TRIGSRC_START_SRC_AUXIO6)
+#define AUXTDC_START_AUXIO7 (AUX_TDC_TRIGSRC_START_SRC_AUXIO7)
+#define AUXTDC_START_AUXIO8 (AUX_TDC_TRIGSRC_START_SRC_AUXIO8)
+#define AUXTDC_START_AUXIO9 (AUX_TDC_TRIGSRC_START_SRC_AUXIO9)
+#define AUXTDC_START_AUXIO10 (AUX_TDC_TRIGSRC_START_SRC_AUXIO10)
+#define AUXTDC_START_AUXIO11 (AUX_TDC_TRIGSRC_START_SRC_AUXIO11)
+#define AUXTDC_START_AUXIO12 (AUX_TDC_TRIGSRC_START_SRC_AUXIO12)
+#define AUXTDC_START_AUXIO13 (AUX_TDC_TRIGSRC_START_SRC_AUXIO13)
+#define AUXTDC_START_AUXIO14 (AUX_TDC_TRIGSRC_START_SRC_AUXIO14)
+#define AUXTDC_START_AUXIO15 (AUX_TDC_TRIGSRC_START_SRC_AUXIO15)
+#define AUXTDC_START_AUXIO16 (AUX_TDC_TRIGSRC_START_SRC_AUXIO16)
+#define AUXTDC_START_AUXIO17 (AUX_TDC_TRIGSRC_START_SRC_AUXIO17)
+#define AUXTDC_START_AUXIO18 (AUX_TDC_TRIGSRC_START_SRC_AUXIO18)
+#define AUXTDC_START_AUXIO19 (AUX_TDC_TRIGSRC_START_SRC_AUXIO19)
+#define AUXTDC_START_AUXIO20 (AUX_TDC_TRIGSRC_START_SRC_AUXIO20)
+#define AUXTDC_START_AUXIO21 (AUX_TDC_TRIGSRC_START_SRC_AUXIO21)
+#define AUXTDC_START_AUXIO22 (AUX_TDC_TRIGSRC_START_SRC_AUXIO22)
+#define AUXTDC_START_AUXIO23 (AUX_TDC_TRIGSRC_START_SRC_AUXIO23)
+#define AUXTDC_START_AUXIO24 (AUX_TDC_TRIGSRC_START_SRC_AUXIO24)
+#define AUXTDC_START_AUXIO25 (AUX_TDC_TRIGSRC_START_SRC_AUXIO25)
+#define AUXTDC_START_AUXIO26 (AUX_TDC_TRIGSRC_START_SRC_AUXIO26)
+#define AUXTDC_START_AUXIO27 (AUX_TDC_TRIGSRC_START_SRC_AUXIO27)
+#define AUXTDC_START_AUXIO28 (AUX_TDC_TRIGSRC_START_SRC_AUXIO28)
+#define AUXTDC_START_AUXIO29 (AUX_TDC_TRIGSRC_START_SRC_AUXIO29)
+#define AUXTDC_START_AUXIO30 (AUX_TDC_TRIGSRC_START_SRC_AUXIO30)
+#define AUXTDC_START_AUXIO31 (AUX_TDC_TRIGSRC_START_SRC_AUXIO31)
+#define AUXTDC_START_MANUAL_EV (AUX_TDC_TRIGSRC_START_SRC_MANUAL_EV)
+#define AUXTDC_START_AON_RTC_CH2_DLY (AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2_DLY)
+#define AUXTDC_START_AON_RTC_4KHZ (AUX_TDC_TRIGSRC_START_SRC_AON_RTC_4KHZ)
+#define AUXTDC_START_AON_BATMON_BAT_UPD (AUX_TDC_TRIGSRC_START_SRC_AON_BATMON_BAT_UPD)
+#define AUXTDC_START_AON_BATMON_TEMP_UPD (AUX_TDC_TRIGSRC_START_SRC_AON_BATMON_TEMP_UPD)
+#define AUXTDC_START_SCLK_LF (AUX_TDC_TRIGSRC_START_SRC_SCLK_LF)
+#define AUXTDC_START_PWR_DWN (AUX_TDC_TRIGSRC_START_SRC_PWR_DWN)
+#define AUXTDC_START_MCU_ACTIVE (AUX_TDC_TRIGSRC_START_SRC_MCU_ACTIVE)
+#define AUXTDC_START_VDDR_RECHARGE (AUX_TDC_TRIGSRC_START_SRC_VDDR_RECHARGE)
+#define AUXTDC_START_TIMER2_EV0 (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV0)
+#define AUXTDC_START_TIMER2_EV1 (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV1)
+#define AUXTDC_START_TIMER2_EV2 (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV2)
+#define AUXTDC_START_TIMER2_EV3 (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV3)
+#define AUXTDC_START_TIMER2_PULSE (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_PULSE)
+#define AUXTDC_START_TDC_DONE (AUX_TDC_TRIGSRC_START_SRC_AUX_TDC_DONE)
+#define AUXTDC_START_ADC_IRQ (AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_IRQ)
+#define AUXTDC_START_ADC_FIFO_NOT_EMPTY (AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_FIFO_NOT_EMPTY)
+#define AUXTDC_START_NO_EVENT (AUX_TDC_TRIGSRC_START_SRC_NO_EVENT)
+#define AUXTDC_START_ADC_DONE (AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_DONE)
+#define AUXTDC_START_ADC_FIFO_ALMOST_FULL (AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_FIFO_ALMOST_FULL)
+#define AUXTDC_START_ISRC_RESET (AUX_TDC_TRIGSRC_START_SRC_AUX_ISRC_RESET_N)
+#define AUXTDC_START_OBSMUX0 (AUX_TDC_TRIGSRC_START_SRC_MCU_OBSMUX0)
+#define AUXTDC_START_OBSMUX1 (AUX_TDC_TRIGSRC_START_SRC_MCU_OBSMUX1)
+#define AUXTDC_START_SMPH_AUTOTAKE_DONE (AUX_TDC_TRIGSRC_START_SRC_AUX_SMPH_AUTOTAKE_DONE)
+#define AUXTDC_START_TDC_PRE (AUX_TDC_TRIGSRC_START_SRC_AUX_TDC_PRE)
+#define AUXTDC_START_TIMER0_EV (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER0_EV)
+#define AUXTDC_START_TIMER1_EV (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER1_EV)
+#define AUXTDC_START_AON_RTC_CH2 (AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2)
+#define AUXTDC_START_AUX_COMPA (AUX_TDC_TRIGSRC_START_SRC_AUX_COMPA)
+#define AUXTDC_START_AUX_COMPB (AUX_TDC_TRIGSRC_START_SRC_AUX_COMPB)
+#define AUXTDC_START_ACLK_REF (AUX_TDC_TRIGSRC_START_SRC_ACLK_REF)
+#define AUXTDC_START_MCU_EV (AUX_TDC_TRIGSRC_START_SRC_MCU_EV)
+
+//*****************************************************************************
+//
+// Defines for the possible saturation values set using AUXTDCLimitSet().
+//
+//*****************************************************************************
+#define AUXTDC_SAT_4096 (AUX_TDC_SATCFG_LIMIT_R12)
+#define AUXTDC_SAT_8192 (AUX_TDC_SATCFG_LIMIT_R13)
+#define AUXTDC_SAT_16384 (AUX_TDC_SATCFG_LIMIT_R14)
+#define AUXTDC_SAT_32768 (AUX_TDC_SATCFG_LIMIT_R15)
+#define AUXTDC_SAT_65536 (AUX_TDC_SATCFG_LIMIT_R16)
+#define AUXTDC_SAT_131072 (AUX_TDC_SATCFG_LIMIT_R17)
+#define AUXTDC_SAT_262144 (AUX_TDC_SATCFG_LIMIT_R18)
+#define AUXTDC_SAT_524288 (AUX_TDC_SATCFG_LIMIT_R19)
+#define AUXTDC_SAT_1048576 (AUX_TDC_SATCFG_LIMIT_R20)
+#define AUXTDC_SAT_2097152 (AUX_TDC_SATCFG_LIMIT_R21)
+#define AUXTDC_SAT_4194304 (AUX_TDC_SATCFG_LIMIT_R22)
+#define AUXTDC_SAT_8388608 (AUX_TDC_SATCFG_LIMIT_R23)
+#define AUXTDC_SAT_16777216 (AUX_TDC_SATCFG_LIMIT_R24)
+#define AUXTDC_NUM_SAT_VALS 16
+
+//*****************************************************************************
+//
+// API Functions and prototypes
+//
+//*****************************************************************************
+
+#ifdef DRIVERLIB_DEBUG
+//*****************************************************************************
+//
+//! \internal
+//! \brief Checks an AUX TDC base address.
+//!
+//! This function determines if a AUX TDC port base address is valid.
+//!
+//! \param ui32Base is the base address of the AUX TDC port.
+//!
+//! \return Returns \c true if the base address is valid and \c false
+//! otherwise.
+//
+//*****************************************************************************
+static bool
+AUXTDCBaseValid(uint32_t ui32Base)
+{
+ return(ui32Base == AUX_TDC_BASE);
+}
+#endif
+
+//*****************************************************************************
+//
+//! \brief Get the status of the AUX TDC internal state machine.
+//!
+//! This function will return the current state of the AUX TDC internal state
+//! machine.
+//! \param ui32Base is base address of the AUX TDC
+//!
+//! \return Returns the current state of the state machine.
+//! Possible states for the state machine are:
+//! - \ref AUXTDC_WAIT_START
+//! - \ref AUXTDC_WAIT_START_CNTEN
+//! - \ref AUXTDC_IDLE
+//! - \ref AUXTDC_CLRCNT
+//! - \ref AUXTDC_WAIT_STOP
+//! - \ref AUXTDC_WAIT_STOP_CNTDOWN
+//! - \ref AUXTDC_GETRESULTS
+//! - \ref AUXTDC_POR
+//! - \ref AUXTDC_WAIT_CLRCNT_DONE
+//! - \ref AUXTDC_START_FALL
+//! - \ref AUXTDC_FORCE_STOP.
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+AUXTDCStatusGet(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(AUXTDCBaseValid(ui32Base));
+
+ // Return the status value for the correct ADI Slave.
+ return((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) >>
+ AUX_TDC_STAT_STATE_S);
+}
+
+//*****************************************************************************
+//
+//! \brief Configure the operation of the AUX TDC.
+//!
+//! Use this function to configure the start and stop event for the AUX TDC.
+//!
+//! The \c ui32StartCondition must be a bitwise OR of the start event and the
+//! polarity of the start event. The start events are:
+//! - \ref AUXTDC_START_AUXIO0
+//! - \ref AUXTDC_START_AUXIO1
+//! - \ref AUXTDC_START_AUXIO2
+//! - \ref AUXTDC_START_AUXIO3
+//! - \ref AUXTDC_START_AUXIO4
+//! - \ref AUXTDC_START_AUXIO5
+//! - \ref AUXTDC_START_AUXIO6
+//! - \ref AUXTDC_START_AUXIO7
+//! - \ref AUXTDC_START_AUXIO8
+//! - \ref AUXTDC_START_AUXIO9
+//! - \ref AUXTDC_START_AUXIO10
+//! - \ref AUXTDC_START_AUXIO11
+//! - \ref AUXTDC_START_AUXIO12
+//! - \ref AUXTDC_START_AUXIO13
+//! - \ref AUXTDC_START_AUXIO14
+//! - \ref AUXTDC_START_AUXIO15
+//! - \ref AUXTDC_START_AUXIO16
+//! - \ref AUXTDC_START_AUXIO17
+//! - \ref AUXTDC_START_AUXIO18
+//! - \ref AUXTDC_START_AUXIO19
+//! - \ref AUXTDC_START_AUXIO20
+//! - \ref AUXTDC_START_AUXIO21
+//! - \ref AUXTDC_START_AUXIO22
+//! - \ref AUXTDC_START_AUXIO23
+//! - \ref AUXTDC_START_AUXIO24
+//! - \ref AUXTDC_START_AUXIO25
+//! - \ref AUXTDC_START_AUXIO26
+//! - \ref AUXTDC_START_AUXIO27
+//! - \ref AUXTDC_START_AUXIO28
+//! - \ref AUXTDC_START_AUXIO29
+//! - \ref AUXTDC_START_AUXIO30
+//! - \ref AUXTDC_START_AUXIO31
+//! - \ref AUXTDC_START_MANUAL_EV
+//! - \ref AUXTDC_START_AON_RTC_CH2_DLY
+//! - \ref AUXTDC_START_AON_RTC_4KHZ
+//! - \ref AUXTDC_START_AON_BATMON_BAT_UPD
+//! - \ref AUXTDC_START_AON_BATMON_TEMP_UPD
+//! - \ref AUXTDC_START_SCLK_LF
+//! - \ref AUXTDC_START_PWR_DWN
+//! - \ref AUXTDC_START_MCU_ACTIVE
+//! - \ref AUXTDC_START_VDDR_RECHARGE
+//! - \ref AUXTDC_START_TIMER2_EV0
+//! - \ref AUXTDC_START_TIMER2_EV1
+//! - \ref AUXTDC_START_TIMER2_EV2
+//! - \ref AUXTDC_START_TIMER2_EV3
+//! - \ref AUXTDC_START_TIMER2_PULSE
+//! - \ref AUXTDC_START_TDC_DONE
+//! - \ref AUXTDC_START_ADC_IRQ
+//! - \ref AUXTDC_START_ADC_FIFO_NOT_EMPTY
+//! - \ref AUXTDC_START_NO_EVENT
+//! - \ref AUXTDC_START_ADC_DONE
+//! - \ref AUXTDC_START_ADC_FIFO_ALMOST_FULL
+//! - \ref AUXTDC_START_ISRC_RESET
+//! - \ref AUXTDC_START_OBSMUX0
+//! - \ref AUXTDC_START_OBSMUX1
+//! - \ref AUXTDC_START_SMPH_AUTOTAKE_DONE
+//! - \ref AUXTDC_START_TDC_PRE
+//! - \ref AUXTDC_START_TIMER0_EV
+//! - \ref AUXTDC_START_TIMER1_EV
+//! - \ref AUXTDC_START_AON_RTC_CH2
+//! - \ref AUXTDC_START_AUX_COMPA
+//! - \ref AUXTDC_START_AUX_COMPB
+//! - \ref AUXTDC_START_ACLK_REF
+//! - \ref AUXTDC_START_MCU_EV
+//!
+//! The polarity of the start event is either rising \ref AUXTDC_STARTPOL_RIS
+//! or falling \ref AUXTDC_STARTPOL_FALL.
+//!
+//! The \c ui32StopCondition must be a bitwise OR of the stop event and the
+//! polarity of the stop event. The stop events are:
+//! - \ref AUXTDC_STOP_AUXIO0
+//! - \ref AUXTDC_STOP_AUXIO1
+//! - \ref AUXTDC_STOP_AUXIO2
+//! - \ref AUXTDC_STOP_AUXIO3
+//! - \ref AUXTDC_STOP_AUXIO4
+//! - \ref AUXTDC_STOP_AUXIO5
+//! - \ref AUXTDC_STOP_AUXIO6
+//! - \ref AUXTDC_STOP_AUXIO7
+//! - \ref AUXTDC_STOP_AUXIO8
+//! - \ref AUXTDC_STOP_AUXIO9
+//! - \ref AUXTDC_STOP_AUXIO10
+//! - \ref AUXTDC_STOP_AUXIO11
+//! - \ref AUXTDC_STOP_AUXIO12
+//! - \ref AUXTDC_STOP_AUXIO13
+//! - \ref AUXTDC_STOP_AUXIO14
+//! - \ref AUXTDC_STOP_AUXIO15
+//! - \ref AUXTDC_STOP_AUXIO16
+//! - \ref AUXTDC_STOP_AUXIO17
+//! - \ref AUXTDC_STOP_AUXIO18
+//! - \ref AUXTDC_STOP_AUXIO19
+//! - \ref AUXTDC_STOP_AUXIO20
+//! - \ref AUXTDC_STOP_AUXIO21
+//! - \ref AUXTDC_STOP_AUXIO22
+//! - \ref AUXTDC_STOP_AUXIO23
+//! - \ref AUXTDC_STOP_AUXIO24
+//! - \ref AUXTDC_STOP_AUXIO25
+//! - \ref AUXTDC_STOP_AUXIO26
+//! - \ref AUXTDC_STOP_AUXIO27
+//! - \ref AUXTDC_STOP_AUXIO28
+//! - \ref AUXTDC_STOP_AUXIO29
+//! - \ref AUXTDC_STOP_AUXIO30
+//! - \ref AUXTDC_STOP_AUXIO31
+//! - \ref AUXTDC_STOP_MANUAL_EV
+//! - \ref AUXTDC_STOP_AON_RTC_CH2_DLY
+//! - \ref AUXTDC_STOP_AON_RTC_4KHZ
+//! - \ref AUXTDC_STOP_AON_BATMON_BAT_UPD
+//! - \ref AUXTDC_STOP_AON_BATMON_TEMP_UPD
+//! - \ref AUXTDC_STOP_SCLK_LF
+//! - \ref AUXTDC_STOP_PWR_DWN
+//! - \ref AUXTDC_STOP_MCU_ACTIVE
+//! - \ref AUXTDC_STOP_VDDR_RECHARGE
+//! - \ref AUXTDC_STOP_TIMER2_EV0
+//! - \ref AUXTDC_STOP_TIMER2_EV1
+//! - \ref AUXTDC_STOP_TIMER2_EV2
+//! - \ref AUXTDC_STOP_TIMER2_EV3
+//! - \ref AUXTDC_STOP_TIMER2_PULSE
+//! - \ref AUXTDC_STOP_TDC_DONE
+//! - \ref AUXTDC_STOP_ADC_IRQ
+//! - \ref AUXTDC_STOP_ADC_FIFO_NOT_EMPTY
+//! - \ref AUXTDC_STOP_NO_EVENT
+//! - \ref AUXTDC_STOP_ADC_DONE
+//! - \ref AUXTDC_STOP_ADC_FIFO_ALMOST_FULL
+//! - \ref AUXTDC_STOP_ISRC_RESET
+//! - \ref AUXTDC_STOP_OBSMUX0
+//! - \ref AUXTDC_STOP_OBSMUX1
+//! - \ref AUXTDC_STOP_SMPH_AUTOTAKE_DONE
+//! - \ref AUXTDC_STOP_TDC_PRE
+//! - \ref AUXTDC_STOP_TIMER0_EV
+//! - \ref AUXTDC_STOP_TIMER1_EV
+//! - \ref AUXTDC_STOP_AON_RTC_CH2
+//! - \ref AUXTDC_STOP_AUX_COMPA
+//! - \ref AUXTDC_STOP_AUX_COMPB
+//! - \ref AUXTDC_STOP_ACLK_REF
+//! - \ref AUXTDC_STOP_MCU_EV
+//!
+//! The polarity of the stop event is either rising \ref AUXTDC_STOPPOL_RIS
+//! or falling \ref AUXTDC_STOPPOL_FALL.
+//!
+//! \note The AUX TDC should only be configured when the AUX TDC is in the Idle
+//! state. To ensure that software does not lock up, it is recommended to
+//! ensure that the AUX TDC is actually in idle when calling \ref AUXTDCConfigSet().
+//! This can be tested using \ref AUXTDCIdle().
+//!
+//! \param ui32Base is base address of the AUX TDC.
+//! \param ui32StartCondition is AUX TDC a bitwise OR of a start event and polarity.
+//! \param ui32StopCondition is AUX TDC a bitwise OR of a stop event and polarity.
+//!
+//! \return None
+//!
+//! \sa \ref AUXTDCConfigSet(), \ref AUXTDCIdle()
+//
+//*****************************************************************************
+extern void AUXTDCConfigSet(uint32_t ui32Base, uint32_t ui32StartCondition,
+ uint32_t ui32StopCondition);
+
+//*****************************************************************************
+//
+//! \brief Check if the AUX TDC is in idle mode.
+//!
+//! This function can be used to check whether the AUX TDC internal state
+//! machine is in idle mode. This is required before setting the polarity
+//! of the start and stop event.
+//!
+//! \param ui32Base is the base address of the AUX TDC.
+//!
+//! \return Returns \c true if state machine is in idle and returns \c false
+//! if the state machine is in any other state.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+AUXTDCIdle(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(AUXTDCBaseValid(ui32Base));
+
+ // Check if the AUX TDC is in the Idle state.
+ return (((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) ==
+ AUX_TDC_STAT_STATE_IDLE) ? true : false);
+}
+
+//*****************************************************************************
+//
+//! \brief Enable the AUX TDC for a measurement.
+//!
+//! This function is used for arming the AUX TDC to begin a measurement as
+//! soon as the start condition is met. There are two run modes:
+//! - \ref AUX_TDC_RUNSYNC will wait for a falling event of the start pulse before
+//! starting measurement on next rising edge of start. This guarantees an edge
+//! triggered start and is recommended for frequency measurements. If the
+//! first falling edge is close to the start command it may be missed, but
+//! the TDC shall catch later falling edges and in any case guarantee a
+//! measurement start synchronous to the rising edge of the start event.
+//! - The \ref AUX_TDC_RUN is asynchronous start and asynchronous stop mode. Using
+//! this a TDC measurement may start immediately if start is high and hence it
+//! may not give precise edge to edge measurements. This mode is only
+//! recommended when start pulse is guaranteed to arrive at least 7 clock
+//! periods after command.
+//!
+//! \note The AUX TDC should be configured and in Idle mode before calling this
+//! function.
+//!
+//! \param ui32Base is the base address of the AUX TDC.
+//! \param ui32RunMode is the run mode for the AUX TDC.
+//! - \ref AUX_TDC_RUNSYNC : Synchronous run mode.
+//! - \ref AUX_TDC_RUN : Asynchronous run mode.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+AUXTDCEnable(uint32_t ui32Base, uint32_t ui32RunMode)
+{
+ // Check the arguments.
+ ASSERT(AUXTDCBaseValid(ui32Base));
+ ASSERT((ui32RunMode == AUX_TDC_RUN) ||
+ (ui32RunMode == AUX_TDC_RUNSYNC));
+
+ // Enable the AUX TDC.
+ HWREG(ui32Base + AUX_TDC_O_CTL) = ui32RunMode;
+}
+
+//*****************************************************************************
+//
+//! \brief Force the AUX TDC back to Idle mode.
+//!
+//! This function will force the AUX TDC in Idle mode. The internal state
+//! machine will not go directly to Idle mode, so it is left to the programmer to
+//! ensure that the state machine is in Idle mode before doing any new
+//! configuration. This can be checked using \ref AUXTDCIdle().
+//!
+//! \param ui32Base is the base address of the AUX TDC.
+//!
+//! \return None
+//!
+//! \sa \ref AUXTDCIdle()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+AUXTDCIdleForce(uint32_t ui32Base)
+{
+ // Check the arguments
+ ASSERT(AUXTDCBaseValid(ui32Base));
+
+ // Abort operation of AUX TDC and force into Idle mode.
+ HWREG(ui32Base + AUX_TDC_O_CTL) = AUX_TDC_CTL_CMD_ABORT;
+}
+
+//*****************************************************************************
+//
+//! \brief Check if the AUX TDC is done measuring.
+//!
+//! This function can be used to check whether the AUX TDC has finished a
+//! measurement. The AUX TDC may have completed a measurement for two reasons.
+//! Either it finish successfully \ref AUX_TDC_DONE or it failed due to a timeout
+//! \ref AUX_TDC_TIMEOUT. If the AUX TDC is still measuring it this function
+//! will return \ref AUX_TDC_BUSY.
+//!
+//! \param ui32Base is the base address of the AUX TDC.
+//!
+//! \return Returns the current status of a measurement:
+//! - \ref AUX_TDC_DONE : An AUX TDC measurement finished successfully.
+//! - \ref AUX_TDC_TIMEOUT : An AUX TDC measurement failed due to timeout.
+//! - \ref AUX_TDC_BUSY : An AUX TDC measurement is being performed.
+//
+//*****************************************************************************
+extern uint32_t AUXTDCMeasurementDone(uint32_t ui32Base);
+
+//*****************************************************************************
+//
+//! \brief Get the value of the latest measurement.
+//!
+//! This function is used for retrieving the value of the latest measurement
+//! performed by the AUX TDC.
+//!
+//! \param ui32Base is the base address of the AUX TDC.
+//!
+//! \return Returns the result of the latest measurement.
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+AUXTDCMeasurementGet(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(AUXTDCBaseValid(ui32Base));
+
+ // Return the measurement.
+ return (HWREG(ui32Base + AUX_TDC_O_RESULT));
+}
+
+//*****************************************************************************
+//
+//! \brief Set the saturation limit of the measurement.
+//!
+//! This function is used to set a saturation limit for the event accumulation
+//! register. The saturation limit is defined as a bit width of the
+//! accumulation register and therefore increases in power of 2.
+//!
+//! \param ui32Base is base address of the AUX TDC.
+//! \param ui32Limit is the saturation limit.
+//! - \ref AUXTDC_SAT_4096
+//! - \ref AUXTDC_SAT_8192
+//! - \ref AUXTDC_SAT_16384
+//! - \ref AUXTDC_SAT_32768
+//! - \ref AUXTDC_SAT_65536
+//! - \ref AUXTDC_SAT_131072
+//! - \ref AUXTDC_SAT_262144
+//! - \ref AUXTDC_SAT_524288
+//! - \ref AUXTDC_SAT_1048576
+//! - \ref AUXTDC_SAT_2097152
+//! - \ref AUXTDC_SAT_4194304
+//! - \ref AUXTDC_SAT_8388608
+//! - \ref AUXTDC_SAT_16777216 (default)
+//!
+//! \return None
+//!
+//! \note The actual value of the accumulation register might increase slightly beyond
+//! the saturation value before the saturation takes effect.
+//!
+//! \sa \ref AUXTDCLimitGet()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+AUXTDCLimitSet(uint32_t ui32Base, uint32_t ui32Limit)
+{
+ // Check the arguments.
+ ASSERT(AUXTDCBaseValid(ui32Base));
+ ASSERT(ui32Limit < AUXTDC_NUM_SAT_VALS);
+
+ // Set the saturation limit.
+ HWREG(ui32Base + AUX_TDC_O_SATCFG) = ui32Limit;
+}
+
+//*****************************************************************************
+//
+//! \brief Get the saturation limit of the measurement.
+//!
+//! This function is used to retrieve the current saturation for the
+//! accumulator register.
+//!
+//! \param ui32Base is base address of the AUX TDC.
+//!
+//! \return Returns the saturation limit.
+//! - \ref AUXTDC_SAT_4096
+//! - \ref AUXTDC_SAT_8192
+//! - \ref AUXTDC_SAT_16384
+//! - \ref AUXTDC_SAT_32768
+//! - \ref AUXTDC_SAT_65536
+//! - \ref AUXTDC_SAT_131072
+//! - \ref AUXTDC_SAT_262144
+//! - \ref AUXTDC_SAT_524288
+//! - \ref AUXTDC_SAT_1048576
+//! - \ref AUXTDC_SAT_2097152
+//! - \ref AUXTDC_SAT_4194304
+//! - \ref AUXTDC_SAT_8388608
+//! - \ref AUXTDC_SAT_16777216
+//!
+//! \sa \ref AUXTDCLimitSet()
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+AUXTDCLimitGet(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(AUXTDCBaseValid(ui32Base));
+
+ // Return the saturation limit.
+ return (HWREG(ui32Base + AUX_TDC_O_SATCFG));
+}
+
+//*****************************************************************************
+//
+//! \brief Enables the counter if possible.
+//!
+//! This function can be used to enable the AUX TDC stop/compare event counter.
+//! The counter can be used to measure multiple periods of a clock signal.
+//! For each stop/compare event the counter will be decremented by one and
+//! the measurement will continue running until the value of the counter
+//! reaches 0. The current value of the counter can be read using
+//! \ref AUXTDCCounterGet(). The reset value of the counter can be set using
+//! \ref AUXTDCCounterSet().
+//!
+//! \param ui32Base is base address of the AUX TDC.
+//!
+//! \return Returns \c true if the counter was successfully enabled. If the
+//! AUX TDC is not in Idle mode, the counter can not be enabled, and the
+//! return value will be \c false.
+//!
+//! \sa \ref AUXTDCCounterGet(), \ref AUXTDCCounterSet()
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+AUXTDCCounterEnable(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(AUXTDCBaseValid(ui32Base));
+
+ // Check if the AUX TDC is in idle mode. If not in Idle mode, the counter
+ // will not be enabled.
+ if(!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) ==
+ AUX_TDC_STAT_STATE_IDLE))
+ {
+ return false;
+ }
+
+ // Enable the counter.
+ HWREG(ui32Base + AUX_TDC_O_TRIGCNTCFG) = AUX_TDC_TRIGCNTCFG_EN;
+
+ // Counter successfully enabled.
+ return true;
+}
+
+//*****************************************************************************
+//
+//! \brief Disables the counter if possible.
+//!
+//! This function can be used to disable the AUX TDC stop/compare event counter.
+//!
+//! \param ui32Base is base address of the AUX TDC.
+//!
+//! \return Returns \c true if the counter was successfully disabled. If the
+//! AUX TDC is not in Idle mode, the counter can not be disabled, and the
+//! return value will be \c false.
+//!
+//! \sa \ref AUXTDCCounterEnable() for more information on how to use the counter.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+AUXTDCCounterDisable(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(AUXTDCBaseValid(ui32Base));
+
+ // Check if the AUX TDC is in Idle mode. If not in Idle mode, the counter
+ // will not be disabled.
+ if(!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) ==
+ AUX_TDC_STAT_STATE_IDLE))
+ {
+ return false;
+ }
+
+ // Disable the counter.
+ HWREG(ui32Base + AUX_TDC_O_TRIGCNTCFG) = 0;
+
+ // Counter successfully disabled.
+ return true;
+}
+
+//*****************************************************************************
+//
+//! \brief Set the reset number of counter compare/stop event to ignore before taking
+//! a measurement.
+//!
+//! This function loads the reset value of the counter with the specified
+//! number of events to ignore. A reset in this context means the counter
+//! has been disabled and then enabled.
+//!
+//! \param ui32Base is base address of the AUX TDC.
+//! \param ui32Events is the number of compare/stop events to load into the
+//! counter.
+//!
+//! \return Returns \c true if the counter was successfully updated. If the
+//! AUX TDC is not in Idle mode, the counter can not be updated, and the
+//! return value will be \c false.
+//!
+//! \sa \ref AUXTDCCounterEnable()
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+AUXTDCCounterSet(uint32_t ui32Base, uint32_t ui32Events)
+{
+ // Check the arguments.
+ ASSERT(AUXTDCBaseValid(ui32Base));
+
+ // Check if the AUX TDC is in idle mode. If not in idle mode, the counter
+ // will not be disabled.
+ if(!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) ==
+ AUX_TDC_STAT_STATE_IDLE))
+ {
+ return false;
+ }
+
+ // Update the reset counter value.
+ HWREG(ui32Base + AUX_TDC_O_TRIGCNTLOAD) = ui32Events;
+
+ // Counter successfully updated.
+ return true;
+}
+
+//*****************************************************************************
+//
+//! \brief Get the current number of counter compare/stop event to ignore before
+//! taking a measurement.
+//!
+//! This function returns the current value of compare/stop events before
+//! a measurement is registered. This value is decremented by one for each
+//! registered compare/stop event and will always be less than or equal the
+//! reset value of the counter set using \ref AUXTDCCounterSet().
+//!
+//! \param ui32Base is base address of the AUX TDC.
+//!
+//! \return Returns the current value of compare/stop events ignored before a
+//! measurement is performed.
+//!
+//! \sa \ref AUXTDCCounterEnable().
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+AUXTDCCounterGet(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(AUXTDCBaseValid(ui32Base));
+
+ // Return the current counter value.
+ return (HWREG(ui32Base + AUX_TDC_O_TRIGCNT));
+}
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// Redirect to implementation in ROM when available.
+//
+//*****************************************************************************
+#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
+ #include "../driverlib/rom.h"
+ #ifdef ROM_AUXTDCConfigSet
+ #undef AUXTDCConfigSet
+ #define AUXTDCConfigSet ROM_AUXTDCConfigSet
+ #endif
+ #ifdef ROM_AUXTDCMeasurementDone
+ #undef AUXTDCMeasurementDone
+ #define AUXTDCMeasurementDone ROM_AUXTDCMeasurementDone
+ #endif
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __AUX_TDC_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ccfgread.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ccfgread.c
new file mode 100644
index 0000000..9f0e8d7
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ccfgread.c
@@ -0,0 +1,41 @@
+/******************************************************************************
+* Filename: ccfgread.c
+* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016)
+* Revision: 47179
+*
+* Description: API for reading CCFG.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "ccfgread.h"
+
+// See ccfgread.h for implementation
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ccfgread.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ccfgread.h
new file mode 100644
index 0000000..a1e809d
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ccfgread.h
@@ -0,0 +1,187 @@
+/******************************************************************************
+* Filename: ccfgread.h
+* Revised: 2016-09-13 14:21:40 +0200 (Tue, 13 Sep 2016)
+* Revision: 47152
+*
+* Description: API for reading CCFG.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup system_control_group
+//! @{
+//! \addtogroup ccfgread_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __CCFGREAD_H__
+#define __CCFGREAD_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "../inc/hw_types.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_ccfg.h"
+
+//*****************************************************************************
+//
+// General constants and defines
+//
+//*****************************************************************************
+
+
+//*****************************************************************************
+//
+// API Functions and prototypes
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \brief Read DIS_GPRAM from CCFG.
+//!
+//! \return Value of CCFG field CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+CCFGRead_DIS_GPRAM( void )
+{
+ return (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) &
+ CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M ) >>
+ CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S ) ;
+}
+
+//*****************************************************************************
+//
+//! \brief Read EXT_LF_CLK_DIO from CCFG.
+//!
+//! \return Value of CCFG field CCFG_EXT_LF_CLK_DIO
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+CCFGRead_EXT_LF_CLK_DIO( void )
+{
+ return (( HWREG( CCFG_BASE + CCFG_O_EXT_LF_CLK ) &
+ CCFG_EXT_LF_CLK_DIO_M ) >>
+ CCFG_EXT_LF_CLK_DIO_S ) ;
+}
+
+//*****************************************************************************
+//
+// Defines the possible values returned from CCFGRead_SCLK_LF_OPTION()
+//
+//*****************************************************************************
+#define CCFGREAD_SCLK_LF_OPTION_XOSC_HF_DLF ( CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_HF_DLF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S )
+#define CCFGREAD_SCLK_LF_OPTION_EXTERNAL_LF ( CCFG_MODE_CONF_SCLK_LF_OPTION_EXTERNAL_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S )
+#define CCFGREAD_SCLK_LF_OPTION_XOSC_LF ( CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S )
+#define CCFGREAD_SCLK_LF_OPTION_RCOSC_LF ( CCFG_MODE_CONF_SCLK_LF_OPTION_RCOSC_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S )
+
+//*****************************************************************************
+//
+//! \brief Read SCLK_LF_OPTION from CCFG.
+//!
+//! \return Returns the value of the CCFG field CCFG_MODE_CONF_SCLK_LF_OPTION field.
+//! Returns one of the following:
+//! - \ref CCFGREAD_SCLK_LF_OPTION_XOSC_HF_DLF
+//! - \ref CCFGREAD_SCLK_LF_OPTION_EXTERNAL_LF
+//! - \ref CCFGREAD_SCLK_LF_OPTION_XOSC_LF
+//! - \ref CCFGREAD_SCLK_LF_OPTION_RCOSC_LF
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+CCFGRead_SCLK_LF_OPTION( void )
+{
+ return (( HWREG( CCFG_BASE + CCFG_O_MODE_CONF ) &
+ CCFG_MODE_CONF_SCLK_LF_OPTION_M ) >>
+ CCFG_MODE_CONF_SCLK_LF_OPTION_S ) ;
+}
+
+//*****************************************************************************
+//
+// Defines the possible values returned from CCFGRead_XOSC_FREQ()
+//
+//*****************************************************************************
+#define CCFGREAD_XOSC_FREQ_24M ( CCFG_MODE_CONF_XOSC_FREQ_24M >> CCFG_MODE_CONF_XOSC_FREQ_S )
+#define CCFGREAD_XOSC_FREQ_48M ( CCFG_MODE_CONF_XOSC_FREQ_48M >> CCFG_MODE_CONF_XOSC_FREQ_S )
+#define CCFGREAD_XOSC_FREQ_HPOSC ( CCFG_MODE_CONF_XOSC_FREQ_HPOSC >> CCFG_MODE_CONF_XOSC_FREQ_S )
+
+//*****************************************************************************
+//
+//! \brief Read XOSC_FREQ setting CCFG.
+//!
+//! \return Returns the value of the CCFG_MODE_CONF_XOSC_FREQ field.
+//! Returns one of the following:
+//! - \ref CCFGREAD_XOSC_FREQ_24M
+//! - \ref CCFGREAD_XOSC_FREQ_48M
+//! - \ref CCFGREAD_XOSC_FREQ_HPOSC
+//!
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+CCFGRead_XOSC_FREQ( void )
+{
+ return (( HWREG( CCFG_BASE + CCFG_O_MODE_CONF ) &
+ CCFG_MODE_CONF_XOSC_FREQ_M ) >>
+ CCFG_MODE_CONF_XOSC_FREQ_S ) ;
+}
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __AUX_SMPH_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ccfgread_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ccfgread_doc.h
new file mode 100644
index 0000000..76946f1
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ccfgread_doc.h
@@ -0,0 +1,51 @@
+/******************************************************************************
+* Filename: ccfgread_doc.h
+* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016)
+* Revision: 45971
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+//! \addtogroup ccfgread_api
+//! @{
+//! \section sec_ccfgread Introduction
+//!
+//! The values of customer configuration (CCFG) settings in flash are determined by ccfg.c and typically
+//! a user application does not need to read these CCFG values as they are used mainly during ROM boot
+//! and device trimming. However, a subset of the CCFG settings need to be read by application
+//! code thus DriverLib provides this API to allow easy read access to these specific settings.
+//!
+//! The remaining settings not accessible through this API can of course be read directly at the CCFG
+//! addresses in the flash (starting at CCFG_BASE) using the HWREG macro and the provided defines.
+//! CCFG settings are documented as part of the register descriptions in the CPU memory map.
+//!
+//! \note CCFG settings are located in flash and should be considered read-only from an application
+//! point-of-view.
+//! @}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/chipinfo.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/chipinfo.c
new file mode 100644
index 0000000..d0b00a1
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/chipinfo.c
@@ -0,0 +1,210 @@
+/******************************************************************************
+* Filename: chipinfo.c
+* Revised: 2018-08-17 09:28:06 +0200 (Fri, 17 Aug 2018)
+* Revision: 52354
+*
+* Description: Collection of functions returning chip information.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "chipinfo.h"
+
+//*****************************************************************************
+//
+// Handle support for DriverLib in ROM:
+// This section will undo prototype renaming made in the header file
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #undef ChipInfo_GetSupportedProtocol_BV
+ #define ChipInfo_GetSupportedProtocol_BV NOROM_ChipInfo_GetSupportedProtocol_BV
+ #undef ChipInfo_GetPackageType
+ #define ChipInfo_GetPackageType NOROM_ChipInfo_GetPackageType
+ #undef ChipInfo_GetChipType
+ #define ChipInfo_GetChipType NOROM_ChipInfo_GetChipType
+ #undef ChipInfo_GetChipFamily
+ #define ChipInfo_GetChipFamily NOROM_ChipInfo_GetChipFamily
+ #undef ChipInfo_GetHwRevision
+ #define ChipInfo_GetHwRevision NOROM_ChipInfo_GetHwRevision
+ #undef ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated
+ #define ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated NOROM_ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated
+#endif
+
+//*****************************************************************************
+//
+// ChipInfo_GetSupportedProtocol_BV()
+//
+//*****************************************************************************
+ProtocolBitVector_t
+ChipInfo_GetSupportedProtocol_BV( void )
+{
+ return ((ProtocolBitVector_t)( HWREG( PRCM_BASE + 0x1D4 ) & 0x0E ));
+}
+
+//*****************************************************************************
+//
+// ChipInfo_GetPackageType()
+//
+//*****************************************************************************
+PackageType_t
+ChipInfo_GetPackageType( void )
+{
+ PackageType_t packType = (PackageType_t)((
+ HWREG( FCFG1_BASE + FCFG1_O_USER_ID ) &
+ FCFG1_USER_ID_PKG_M ) >>
+ FCFG1_USER_ID_PKG_S ) ;
+
+ if (( packType < PACKAGE_4x4 ) ||
+ ( packType > PACKAGE_7x7_Q1 ) )
+ {
+ packType = PACKAGE_Unknown;
+ }
+
+ return ( packType );
+}
+
+//*****************************************************************************
+//
+// ChipInfo_GetChipFamily()
+//
+//*****************************************************************************
+ChipFamily_t
+ChipInfo_GetChipFamily( void )
+{
+ uint32_t waferId ;
+ ChipFamily_t chipFam = FAMILY_Unknown ;
+
+ waferId = (( HWREG( FCFG1_BASE + FCFG1_O_ICEPICK_DEVICE_ID ) &
+ FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_M ) >>
+ FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_S ) ;
+
+ if ( waferId == 0xBB41 ) {
+ chipFam = FAMILY_CC13x2_CC26x2 ;
+ }
+
+ return ( chipFam );
+}
+
+//*****************************************************************************
+//
+// ChipInfo_GetChipType()
+//
+//*****************************************************************************
+ChipType_t
+ChipInfo_GetChipType( void )
+{
+ ChipType_t chipType = CHIP_TYPE_Unknown ;
+ ChipFamily_t chipFam = ChipInfo_GetChipFamily() ;
+ uint32_t fcfg1UserId = ChipInfo_GetUserId() ;
+ uint32_t fcfg1Protocol = (( fcfg1UserId & FCFG1_USER_ID_PROTOCOL_M ) >>
+ FCFG1_USER_ID_PROTOCOL_S ) ;
+ uint32_t fcfg1Cc13 = (( fcfg1UserId & FCFG1_USER_ID_CC13_M ) >>
+ FCFG1_USER_ID_CC13_S ) ;
+ uint32_t fcfg1Pa = (( fcfg1UserId & FCFG1_USER_ID_PA_M ) >>
+ FCFG1_USER_ID_PA_S ) ;
+
+ if ( chipFam == FAMILY_CC13x2_CC26x2 ) {
+ switch ( fcfg1Protocol ) {
+ case 0xF :
+ if( fcfg1Cc13 ) {
+ if ( fcfg1Pa ) {
+ chipType = CHIP_TYPE_CC1352P ;
+ } else {
+ chipType = CHIP_TYPE_CC1352 ;
+ }
+ } else {
+ chipType = CHIP_TYPE_CC2652 ;
+ }
+ break;
+ case 0x9 :
+ if( fcfg1Pa ) {
+ chipType = CHIP_TYPE_unused ;
+ } else {
+ chipType = CHIP_TYPE_CC2642 ;
+ }
+ break;
+ case 0x8 :
+ chipType = CHIP_TYPE_CC1312 ;
+ break;
+ }
+ }
+
+ return ( chipType );
+}
+
+//*****************************************************************************
+//
+// ChipInfo_GetHwRevision()
+//
+//*****************************************************************************
+HwRevision_t
+ChipInfo_GetHwRevision( void )
+{
+ HwRevision_t hwRev = HWREV_Unknown ;
+ uint32_t fcfg1Rev = ChipInfo_GetDeviceIdHwRevCode() ;
+ uint32_t minorHwRev = ChipInfo_GetMinorHwRev() ;
+ ChipFamily_t chipFam = ChipInfo_GetChipFamily() ;
+
+ if ( chipFam == FAMILY_CC13x2_CC26x2 ) {
+ switch ( fcfg1Rev ) {
+ case 0 : // CC13x2, CC26x2 - PG1.0
+ case 1 : // CC13x2, CC26x2 - PG1.01 (will also show up as PG1.0)
+ hwRev = (HwRevision_t)((uint32_t)HWREV_1_0 );
+ break;
+ case 2 : // CC13x2, CC26x2 - PG1.1 (or later)
+ hwRev = (HwRevision_t)(((uint32_t)HWREV_1_1 ) + minorHwRev );
+ break;
+ case 3 : // CC13x2, CC26x2 - PG2.1 (or later)
+ hwRev = (HwRevision_t)(((uint32_t)HWREV_2_1 ) + minorHwRev );
+ break;
+ }
+ }
+
+ return ( hwRev );
+}
+
+//*****************************************************************************
+// ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated()
+//*****************************************************************************
+void
+ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated( void )
+{
+ if (( ! ChipInfo_ChipFamilyIs_CC13x2_CC26x2() ) ||
+ ( ! ChipInfo_HwRevisionIs_GTEQ_2_0() ) )
+ {
+ while(1)
+ {
+ // This driverlib version is for the CC13x2/CC26x2 PG2.0 and later chips.
+ // Do nothing - stay here forever
+ }
+ }
+}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/chipinfo.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/chipinfo.h
new file mode 100644
index 0000000..b02d5f8
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/chipinfo.h
@@ -0,0 +1,685 @@
+/******************************************************************************
+* Filename: chipinfo.h
+* Revised: 2018-06-18 10:26:12 +0200 (Mon, 18 Jun 2018)
+* Revision: 52189
+*
+* Description: Collection of functions returning chip information.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup system_control_group
+//! @{
+//! \addtogroup ChipInfo
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __CHIP_INFO_H__
+#define __CHIP_INFO_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "../inc/hw_types.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_fcfg1.h"
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// This section renames all functions that are not "static inline", so that
+// calling these functions will default to implementation in flash. At the end
+// of this file a second renaming will change the defaults to implementation in
+// ROM for available functions.
+//
+// To force use of the implementation in flash, e.g. for debugging:
+// - Globally: Define DRIVERLIB_NOROM at project level
+// - Per function: Use prefix "NOROM_" when calling the function
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #define ChipInfo_GetSupportedProtocol_BV NOROM_ChipInfo_GetSupportedProtocol_BV
+ #define ChipInfo_GetPackageType NOROM_ChipInfo_GetPackageType
+ #define ChipInfo_GetChipType NOROM_ChipInfo_GetChipType
+ #define ChipInfo_GetChipFamily NOROM_ChipInfo_GetChipFamily
+ #define ChipInfo_GetHwRevision NOROM_ChipInfo_GetHwRevision
+ #define ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated NOROM_ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated
+#endif
+
+//*****************************************************************************
+//
+//! \brief Enumeration identifying the protocols supported.
+//!
+//! \note
+//! This is a bit vector enumeration that indicates supported protocols.
+//! E.g: 0x06 means that the chip supports both BLE and IEEE 802.15.4
+//
+//*****************************************************************************
+typedef enum {
+ PROTOCOL_Unknown = 0 , //!< None of the known protocols are supported.
+ PROTOCOLBIT_BLE = 0x02, //!< Bit[1] set, indicates that Bluetooth Low Energy is supported.
+ PROTOCOLBIT_IEEE_802_15_4 = 0x04, //!< Bit[2] set, indicates that IEEE 802.15.4 is supported.
+ PROTOCOLBIT_Proprietary = 0x08 //!< Bit[3] set, indicates that proprietary protocols are supported.
+} ProtocolBitVector_t;
+
+//*****************************************************************************
+//
+//! \brief Returns bit vector showing supported protocols.
+//!
+//! \return
+//! Returns \ref ProtocolBitVector_t which is a bit vector indicating supported protocols.
+//
+//*****************************************************************************
+extern ProtocolBitVector_t ChipInfo_GetSupportedProtocol_BV( void );
+
+//*****************************************************************************
+//
+//! \brief Returns true if the chip supports the BLE protocol.
+//!
+//! \return
+//! Returns \c true if supporting the BLE protocol, \c false otherwise.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+ChipInfo_SupportsBLE( void )
+{
+ return (( ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_BLE ) != 0 );
+}
+
+//*****************************************************************************
+//
+//! \brief Returns true if the chip supports the IEEE 802.15.4 protocol.
+//!
+//! \return
+//! Returns \c true if supporting the IEEE 802.15.4 protocol, \c false otherwise.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+ChipInfo_SupportsIEEE_802_15_4( void )
+{
+ return (( ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_IEEE_802_15_4 ) != 0 );
+}
+
+//*****************************************************************************
+//
+//! \brief Returns true if the chip supports proprietary protocols.
+//!
+//! \return
+//! Returns \c true if supporting proprietary protocols, \c false otherwise.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+ChipInfo_SupportsPROPRIETARY( void )
+{
+ return (( ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_Proprietary ) != 0 );
+}
+
+//*****************************************************************************
+//
+//! \brief Package type enumeration
+//!
+//! \note
+//! Packages available for a specific device are shown in the device datasheet.
+//
+//*****************************************************************************
+typedef enum {
+ PACKAGE_Unknown = -1, //!< -1 means that current package type is unknown.
+ PACKAGE_4x4 = 0, //!< 0 means that this is a 4x4 mm QFN (RHB) package.
+ PACKAGE_5x5 = 1, //!< 1 means that this is a 5x5 mm QFN (RSM) package.
+ PACKAGE_7x7 = 2, //!< 2 means that this is a 7x7 mm QFN (RGZ) package.
+ PACKAGE_WAFER = 3, //!< 3 means that this is a wafer sale package (naked die).
+ PACKAGE_WCSP = 4, //!< 4 means that this is a 2.7x2.7 mm WCSP (YFV).
+ PACKAGE_7x7_Q1 = 5 //!< 5 means that this is a 7x7 mm QFN package with Wettable Flanks.
+} PackageType_t;
+
+//*****************************************************************************
+//
+//! \brief Returns package type.
+//!
+//! \return
+//! Returns \ref PackageType_t
+//
+//*****************************************************************************
+extern PackageType_t ChipInfo_GetPackageType( void );
+
+//*****************************************************************************
+//
+//! \brief Returns true if this is a 4x4mm chip.
+//!
+//! \return
+//! Returns \c true if this is a 4x4mm chip, \c false otherwise.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+ChipInfo_PackageTypeIs4x4( void )
+{
+ return ( ChipInfo_GetPackageType() == PACKAGE_4x4 );
+}
+
+//*****************************************************************************
+//
+//! \brief Returns true if this is a 5x5mm chip.
+//!
+//! \return
+//! Returns \c true if this is a 5x5mm chip, \c false otherwise.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+ChipInfo_PackageTypeIs5x5( void )
+{
+ return ( ChipInfo_GetPackageType() == PACKAGE_5x5 );
+}
+
+//*****************************************************************************
+//
+//! \brief Returns true if this is a 7x7mm chip.
+//!
+//! \return
+//! Returns \c true if this is a 7x7mm chip, \c false otherwise.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+ChipInfo_PackageTypeIs7x7( void )
+{
+ return ( ChipInfo_GetPackageType() == PACKAGE_7x7 );
+}
+
+//*****************************************************************************
+//
+//! \brief Returns true if this is a wafer sale chip (naked die).
+//!
+//! \return
+//! Returns \c true if this is a wafer sale chip, \c false otherwise.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+ChipInfo_PackageTypeIsWAFER( void )
+{
+ return ( ChipInfo_GetPackageType() == PACKAGE_WAFER );
+}
+
+//*****************************************************************************
+//
+//! \brief Returns true if this is a WCSP chip (flip chip).
+//!
+//! \return
+//! Returns \c true if this is a WCSP chip, \c false otherwise.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+ChipInfo_PackageTypeIsWCSP( void )
+{
+ return ( ChipInfo_GetPackageType() == PACKAGE_WCSP );
+}
+
+//*****************************************************************************
+//
+//! \brief Returns true if this is a 7x7 Q1 chip.
+//!
+//! \return
+//! Returns \c true if this is a 7x7 Q1 chip, \c false otherwise.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+ChipInfo_PackageTypeIs7x7Q1( void )
+{
+ return ( ChipInfo_GetPackageType() == PACKAGE_7x7_Q1 );
+}
+
+//*****************************************************************************
+//
+//! \brief Returns the internal chip HW revision code.
+//!
+//! \return
+//! Returns the internal chip HW revision code (in range 0-15)
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+ChipInfo_GetDeviceIdHwRevCode( void )
+{
+ // Returns HwRevCode = FCFG1_O_ICEPICK_DEVICE_ID[31:28]
+ return ( HWREG( FCFG1_BASE + FCFG1_O_ICEPICK_DEVICE_ID ) >> 28 );
+}
+
+//*****************************************************************************
+//
+//! \brief Returns minor hardware revision number
+//!
+//! The minor revision number is set to 0 for the first market released chip
+//! and thereafter incremented by 1 for each minor hardware change.
+//!
+//! \return
+//! Returns the minor hardware revision number (in range 0-127)
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+ChipInfo_GetMinorHwRev( void )
+{
+ uint32_t minorRev = (( HWREG( FCFG1_BASE + FCFG1_O_MISC_CONF_1 ) &
+ FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_M ) >>
+ FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_S ) ;
+
+ if ( minorRev >= 0x80 ) {
+ minorRev = 0;
+ }
+
+ return( minorRev );
+}
+
+//*****************************************************************************
+//
+//! \brief Returns the 32 bits USER_ID field
+//!
+//! How to decode the USER_ID filed is described in the Technical Reference Manual (TRM)
+//!
+//! \return
+//! Returns the 32 bits USER_ID field
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+ChipInfo_GetUserId( void )
+{
+ return ( HWREG( FCFG1_BASE + FCFG1_O_USER_ID ));
+}
+
+//*****************************************************************************
+//
+//! \brief Chip type enumeration
+//
+//*****************************************************************************
+typedef enum {
+ CHIP_TYPE_Unknown = -1, //!< -1 means that the chip type is unknown.
+ CHIP_TYPE_CC1310 = 0, //!< 0 means that this is a CC1310 chip.
+ CHIP_TYPE_CC1350 = 1, //!< 1 means that this is a CC1350 chip.
+ CHIP_TYPE_CC2620 = 2, //!< 2 means that this is a CC2620 chip.
+ CHIP_TYPE_CC2630 = 3, //!< 3 means that this is a CC2630 chip.
+ CHIP_TYPE_CC2640 = 4, //!< 4 means that this is a CC2640 chip.
+ CHIP_TYPE_CC2650 = 5, //!< 5 means that this is a CC2650 chip.
+ CHIP_TYPE_CUSTOM_0 = 6, //!< 6 means that this is a CUSTOM_0 chip.
+ CHIP_TYPE_CUSTOM_1 = 7, //!< 7 means that this is a CUSTOM_1 chip.
+ CHIP_TYPE_CC2640R2 = 8, //!< 8 means that this is a CC2640R2 chip.
+ CHIP_TYPE_CC2642 = 9, //!< 9 means that this is a CC2642 chip.
+ CHIP_TYPE_unused = 10,//!< 10 unused value
+ CHIP_TYPE_CC2652 = 11,//!< 11 means that this is a CC2652 chip.
+ CHIP_TYPE_CC1312 = 12,//!< 12 means that this is a CC1312 chip.
+ CHIP_TYPE_CC1352 = 13,//!< 13 means that this is a CC1352 chip.
+ CHIP_TYPE_CC1352P = 14 //!< 14 means that this is a CC1352P chip.
+} ChipType_t;
+
+//*****************************************************************************
+//
+//! \brief Returns chip type.
+//!
+//! \return
+//! Returns \ref ChipType_t
+//
+//*****************************************************************************
+extern ChipType_t ChipInfo_GetChipType( void );
+
+//*****************************************************************************
+//
+//! \brief Chip family enumeration
+//
+//*****************************************************************************
+typedef enum {
+ FAMILY_Unknown = -1, //!< -1 means that the chip's family member is unknown.
+ FAMILY_CC26x0 = 0, //!< 0 means that the chip is a CC26x0 family member.
+ FAMILY_CC13x0 = 1, //!< 1 means that the chip is a CC13x0 family member.
+ FAMILY_CC26x1 = 2, //!< 2 means that the chip is a CC26x1 family member.
+ FAMILY_CC26x0R2 = 3, //!< 3 means that the chip is a CC26x0R2 family (new ROM contents).
+ FAMILY_CC13x2_CC26x2 = 4 //!< 4 means that the chip is a CC13x2, CC26x2 family member.
+} ChipFamily_t;
+
+//*****************************************************************************
+//
+//! \brief Returns chip family member.
+//!
+//! \return
+//! Returns \ref ChipFamily_t
+//
+//*****************************************************************************
+extern ChipFamily_t ChipInfo_GetChipFamily( void );
+
+//*****************************************************************************
+//
+// Options for the define THIS_DRIVERLIB_BUILD
+//
+//*****************************************************************************
+#define DRIVERLIB_BUILD_CC26X0 0 //!< 0 is the driverlib build ID for the cc26x0 driverlib.
+#define DRIVERLIB_BUILD_CC13X0 1 //!< 1 is the driverlib build ID for the cc13x0 driverlib.
+#define DRIVERLIB_BUILD_CC26X1 2 //!< 2 is the driverlib build ID for the cc26x1 driverlib.
+#define DRIVERLIB_BUILD_CC26X0R2 3 //!< 3 is the driverlib build ID for the cc26x0r2 driverlib.
+#define DRIVERLIB_BUILD_CC13X2_CC26X2 4 //!< 4 is the driverlib build ID for the cc13x2_cc26x2 driverlib.
+
+//*****************************************************************************
+//
+//! \brief Define THIS_DRIVERLIB_BUILD, identifying current driverlib build ID.
+//!
+//! This driverlib build identifier can be useful for compile time checking/optimization (supporting C preprocessor expressions).
+//
+//*****************************************************************************
+#define THIS_DRIVERLIB_BUILD DRIVERLIB_BUILD_CC13X2_CC26X2
+
+//*****************************************************************************
+//
+//! \brief Returns true if this chip is member of the CC13x0 family.
+//!
+//! \return
+//! Returns \c true if this chip is member of the CC13x0 family, \c false otherwise.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+ChipInfo_ChipFamilyIs_CC13x0( void )
+{
+ return ( ChipInfo_GetChipFamily() == FAMILY_CC13x0 );
+}
+
+//*****************************************************************************
+//
+//! \brief Returns true if this chip is member of the CC26x0 family.
+//!
+//! \return
+//! Returns \c true if this chip is member of the CC26x0 family, \c false otherwise.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+ChipInfo_ChipFamilyIs_CC26x0( void )
+{
+ return ( ChipInfo_GetChipFamily() == FAMILY_CC26x0 );
+}
+
+//*****************************************************************************
+//
+//! \brief Returns true if this chip is member of the CC26x0R2 family.
+//!
+//! \return
+//! Returns \c true if this chip is member of the CC26x0R2 family, \c false otherwise.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+ChipInfo_ChipFamilyIs_CC26x0R2( void )
+{
+ return ( ChipInfo_GetChipFamily() == FAMILY_CC26x0R2 );
+}
+
+//*****************************************************************************
+//
+//! \brief Returns true if this chip is member of the CC26x1 family.
+//!
+//! \return
+//! Returns \c true if this chip is member of the CC26x1 family, \c false otherwise.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+ChipInfo_ChipFamilyIs_CC26x1( void )
+{
+ return ( ChipInfo_GetChipFamily() == FAMILY_CC26x1 );
+}
+
+//*****************************************************************************
+//
+//! \brief Returns true if this chip is member of the CC13x2, CC26x2 family.
+//!
+//! \return
+//! Returns \c true if this chip is member of the CC13x2, CC26x2 family, \c false otherwise.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+ChipInfo_ChipFamilyIs_CC13x2_CC26x2( void )
+{
+ return ( ChipInfo_GetChipFamily() == FAMILY_CC13x2_CC26x2 );
+}
+
+//*****************************************************************************
+//
+//! \brief HW revision enumeration.
+//
+//*****************************************************************************
+typedef enum {
+ HWREV_Unknown = -1, //!< -1 means that the chip's HW revision is unknown.
+ HWREV_1_0 = 10, //!< 10 means that the chip's HW revision is 1.0
+ HWREV_1_1 = 11, //!< 11 means that the chip's HW revision is 1.1
+ HWREV_2_0 = 20, //!< 20 means that the chip's HW revision is 2.0
+ HWREV_2_1 = 21, //!< 21 means that the chip's HW revision is 2.1
+ HWREV_2_2 = 22, //!< 22 means that the chip's HW revision is 2.2
+ HWREV_2_3 = 23, //!< 23 means that the chip's HW revision is 2.3
+ HWREV_2_4 = 24 //!< 24 means that the chip's HW revision is 2.4
+} HwRevision_t;
+
+//*****************************************************************************
+//
+//! \brief Returns chip HW revision.
+//!
+//! \return
+//! Returns \ref HwRevision_t
+//
+//*****************************************************************************
+extern HwRevision_t ChipInfo_GetHwRevision( void );
+
+//*****************************************************************************
+//
+//! \brief Returns true if HW revision for this chip is 1.0.
+//!
+//! \return
+//! Returns \c true if HW revision for this chip is 1.0, \c false otherwise.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+ChipInfo_HwRevisionIs_1_0( void )
+{
+ return ( ChipInfo_GetHwRevision() == HWREV_1_0 );
+}
+
+//*****************************************************************************
+//
+//! \brief Returns true if HW revision for this chip is 2.0.
+//!
+//! \return
+//! Returns \c true if HW revision for this chip is 2.0, \c false otherwise.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+ChipInfo_HwRevisionIs_2_0( void )
+{
+ return ( ChipInfo_GetHwRevision() == HWREV_2_0 );
+}
+
+//*****************************************************************************
+//
+//! \brief Returns true if HW revision for this chip is 2.0 or greater.
+//!
+//! \return
+//! Returns \c true if HW revision for this chip is 2.0 or greater, \c false otherwise.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+ChipInfo_HwRevisionIs_GTEQ_2_0( void )
+{
+ return ( ChipInfo_GetHwRevision() >= HWREV_2_0 );
+}
+
+//*****************************************************************************
+//
+//! \brief Returns true if HW revision for this chip is 2.1.
+//!
+//! \return
+//! Returns \c true if HW revision for this chip is 2.1, \c false otherwise.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+ChipInfo_HwRevisionIs_2_1( void )
+{
+ return ( ChipInfo_GetHwRevision() == HWREV_2_1 );
+}
+
+//*****************************************************************************
+//
+//! \brief Returns true if HW revision for this chip is 2.1 or greater.
+//!
+//! \return
+//! Returns \c true if HW revision for this chip is 2.1 or greater, \c false otherwise.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+ChipInfo_HwRevisionIs_GTEQ_2_1( void )
+{
+ return ( ChipInfo_GetHwRevision() >= HWREV_2_1 );
+}
+
+//*****************************************************************************
+//
+//! \brief Returns true if HW revision for this chip is 2.2.
+//!
+//! \return
+//! Returns \c true if HW revision for this chip is 2.2, \c false otherwise.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+ChipInfo_HwRevisionIs_2_2( void )
+{
+ return ( ChipInfo_GetHwRevision() == HWREV_2_2 );
+}
+
+//*****************************************************************************
+//
+//! \brief Returns true if HW revision for this chip is 2.2 or greater.
+//!
+//! \return
+//! Returns \c true if HW revision for this chip is 2.2 or greater, \c false otherwise.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+ChipInfo_HwRevisionIs_GTEQ_2_2( void )
+{
+ return ( ChipInfo_GetHwRevision() >= HWREV_2_2 );
+}
+
+//*****************************************************************************
+//
+//! \brief Returns true if HW revision for this chip is 2.3 or greater.
+//!
+//! \return
+//! Returns \c true if HW revision for this chip is 2.3 or greater, \c false otherwise.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+ChipInfo_HwRevisionIs_GTEQ_2_3( void )
+{
+ return ( ChipInfo_GetHwRevision() >= HWREV_2_3 );
+}
+
+//*****************************************************************************
+//
+//! \brief Returns true if HW revision for this chip is 2.4 or greater.
+//!
+//! \return
+//! Returns \c true if HW revision for this chip is 2.4 or greater, \c false otherwise.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+ChipInfo_HwRevisionIs_GTEQ_2_4( void )
+{
+ return ( ChipInfo_GetHwRevision() >= HWREV_2_4 );
+}
+
+//*****************************************************************************
+//
+//! \brief Verifies that current chip is CC13x2 or CC26x2 PG2.0 or later and never returns if violated.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated( void );
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// Redirect to implementation in ROM when available.
+//
+//*****************************************************************************
+#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
+ #include "../driverlib/rom.h"
+ #ifdef ROM_ChipInfo_GetSupportedProtocol_BV
+ #undef ChipInfo_GetSupportedProtocol_BV
+ #define ChipInfo_GetSupportedProtocol_BV ROM_ChipInfo_GetSupportedProtocol_BV
+ #endif
+ #ifdef ROM_ChipInfo_GetPackageType
+ #undef ChipInfo_GetPackageType
+ #define ChipInfo_GetPackageType ROM_ChipInfo_GetPackageType
+ #endif
+ #ifdef ROM_ChipInfo_GetChipType
+ #undef ChipInfo_GetChipType
+ #define ChipInfo_GetChipType ROM_ChipInfo_GetChipType
+ #endif
+ #ifdef ROM_ChipInfo_GetChipFamily
+ #undef ChipInfo_GetChipFamily
+ #define ChipInfo_GetChipFamily ROM_ChipInfo_GetChipFamily
+ #endif
+ #ifdef ROM_ChipInfo_GetHwRevision
+ #undef ChipInfo_GetHwRevision
+ #define ChipInfo_GetHwRevision ROM_ChipInfo_GetHwRevision
+ #endif
+ #ifdef ROM_ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated
+ #undef ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated
+ #define ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated ROM_ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated
+ #endif
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __CHIP_INFO_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/cpu.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/cpu.c
new file mode 100644
index 0000000..14d549e
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/cpu.c
@@ -0,0 +1,396 @@
+/******************************************************************************
+* Filename: cpu.c
+* Revised: 2018-05-08 10:04:01 +0200 (Tue, 08 May 2018)
+* Revision: 51972
+*
+* Description: Instruction wrappers for special CPU instructions needed by
+* the drivers.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "cpu.h"
+
+//*****************************************************************************
+//
+// Handle support for DriverLib in ROM:
+// This section will undo prototype renaming made in the header file
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #undef CPUcpsid
+ #define CPUcpsid NOROM_CPUcpsid
+ #undef CPUprimask
+ #define CPUprimask NOROM_CPUprimask
+ #undef CPUcpsie
+ #define CPUcpsie NOROM_CPUcpsie
+ #undef CPUbasepriGet
+ #define CPUbasepriGet NOROM_CPUbasepriGet
+ #undef CPUdelay
+ #define CPUdelay NOROM_CPUdelay
+#endif
+
+//*****************************************************************************
+//
+// Disable all external interrupts
+//
+//*****************************************************************************
+#if defined(DOXYGEN)
+uint32_t
+CPUcpsid(void)
+{
+ // This function is written in assembly. See cpu.c for compiler specific implementation.
+}
+#elif defined(__IAR_SYSTEMS_ICC__)
+uint32_t
+CPUcpsid(void)
+{
+ // Read PRIMASK and disable interrupts.
+ __asm(" mrs r0, PRIMASK\n"
+ " cpsid i\n");
+
+ // "Warning[Pe940]: missing return statement at end of non-void function"
+ // is suppressed here to avoid putting a "bx lr" in the inline assembly
+ // above and a superfluous return statement here.
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+__asm uint32_t
+CPUcpsid(void)
+{
+ // Read PRIMASK and disable interrupts.
+ mrs r0, PRIMASK;
+ cpsid i;
+ bx lr
+}
+#elif defined(__TI_COMPILER_VERSION__)
+uint32_t
+CPUcpsid(void)
+{
+ // Read PRIMASK and disable interrupts.
+ __asm(" mrs r0, PRIMASK\n"
+ " cpsid i\n"
+ " bx lr\n");
+
+ // The following keeps the compiler happy, because it wants to see a
+ // return value from this function. It will generate code to return
+ // a zero. However, the real return is the "bx lr" above, so the
+ // return(0) is never executed and the function returns with the value
+ // you expect in R0.
+ return(0);
+}
+#else
+uint32_t __attribute__((naked))
+CPUcpsid(void)
+{
+ uint32_t ui32Ret;
+
+ // Read PRIMASK and disable interrupts
+ __asm volatile (" mrs %0, PRIMASK\n"
+ " cpsid i\n"
+ " bx lr\n"
+ : "=r"(ui32Ret)
+ );
+
+ // The return is handled in the inline assembly, but the compiler will
+ // still complain if there is not an explicit return here (despite the fact
+ // that this does not result in any code being produced because of the
+ // naked attribute).
+ return(ui32Ret);
+}
+#endif
+
+//*****************************************************************************
+//
+// Get the current interrupt state
+//
+//*****************************************************************************
+#if defined(DOXYGEN)
+uint32_t
+CPUprimask(void)
+{
+ // This function is written in assembly. See cpu.c for compiler specific implementation.
+}
+#elif defined(__IAR_SYSTEMS_ICC__)
+uint32_t
+CPUprimask(void)
+{
+ // Read PRIMASK.
+ __asm(" mrs r0, PRIMASK\n");
+
+ // "Warning[Pe940]: missing return statement at end of non-void function"
+ // is suppressed here to avoid putting a "bx lr" in the inline assembly
+ // above and a superfluous return statement here.
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+__asm uint32_t
+CPUprimask(void)
+{
+ // Read PRIMASK.
+ mrs r0, PRIMASK;
+ bx lr
+}
+#elif defined(__TI_COMPILER_VERSION__)
+uint32_t
+CPUprimask(void)
+{
+ // Read PRIMASK.
+ __asm(" mrs r0, PRIMASK\n"
+ " bx lr\n");
+
+ // The following keeps the compiler happy, because it wants to see a
+ // return value from this function. It will generate code to return
+ // a zero. However, the real return is the "bx lr" above, so the
+ // return(0) is never executed and the function returns with the value
+ // you expect in R0.
+ return(0);
+}
+#else
+uint32_t __attribute__((naked))
+CPUprimask(void)
+{
+ uint32_t ui32Ret;
+
+ // Read PRIMASK
+ __asm volatile (" mrs %0, PRIMASK\n"
+ " bx lr\n"
+ : "=r"(ui32Ret)
+ );
+
+ // The return is handled in the inline assembly, but the compiler will
+ // still complain if there is not an explicit return here (despite the fact
+ // that this does not result in any code being produced because of the
+ // naked attribute).
+ return(ui32Ret);
+}
+#endif
+
+//*****************************************************************************
+//
+// Enable all external interrupts
+//
+//*****************************************************************************
+#if defined(DOXYGEN)
+uint32_t
+CPUcpsie(void)
+{
+ // This function is written in assembly. See cpu.c for compiler specific implementation.
+}
+#elif defined(__IAR_SYSTEMS_ICC__)
+uint32_t
+CPUcpsie(void)
+{
+ // Read PRIMASK and enable interrupts.
+ __asm(" mrs r0, PRIMASK\n"
+ " cpsie i\n");
+
+ // "Warning[Pe940]: missing return statement at end of non-void function"
+ // is suppressed here to avoid putting a "bx lr" in the inline assembly
+ // above and a superfluous return statement here.
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+__asm uint32_t
+CPUcpsie(void)
+{
+ // Read PRIMASK and enable interrupts.
+ mrs r0, PRIMASK;
+ cpsie i;
+ bx lr
+}
+#elif defined(__TI_COMPILER_VERSION__)
+uint32_t
+CPUcpsie(void)
+{
+ // Read PRIMASK and enable interrupts.
+ __asm(" mrs r0, PRIMASK\n"
+ " cpsie i\n"
+ " bx lr\n");
+
+ // The following keeps the compiler happy, because it wants to see a
+ // return value from this function. It will generate code to return
+ // a zero. However, the real return is the "bx lr" above, so the
+ // return(0) is never executed and the function returns with the value
+ // you expect in R0.
+ return(0);
+}
+#else
+uint32_t __attribute__((naked))
+CPUcpsie(void)
+{
+ uint32_t ui32Ret;
+
+ // Read PRIMASK and enable interrupts.
+ __asm volatile (" mrs %0, PRIMASK\n"
+ " cpsie i\n"
+ " bx lr\n"
+ : "=r"(ui32Ret)
+ );
+
+ // The return is handled in the inline assembly, but the compiler will
+ // still complain if there is not an explicit return here (despite the fact
+ // that this does not result in any code being produced because of the
+ // naked attribute).
+ return(ui32Ret);
+}
+#endif
+
+//*****************************************************************************
+//
+// Get the interrupt priority disable level
+//
+//*****************************************************************************
+#if defined(DOXYGEN)
+uint32_t
+CPUbasepriGet(void)
+{
+ // This function is written in assembly. See cpu.c for compiler specific implementation.
+}
+#elif defined(__IAR_SYSTEMS_ICC__)
+uint32_t
+CPUbasepriGet(void)
+{
+ // Read BASEPRI.
+ __asm(" mrs r0, BASEPRI\n");
+
+ // "Warning[Pe940]: missing return statement at end of non-void function"
+ // is suppressed here to avoid putting a "bx lr" in the inline assembly
+ // above and a superfluous return statement here.
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+__asm uint32_t
+CPUbasepriGet(void)
+{
+ // Read BASEPRI.
+ mrs r0, BASEPRI;
+ bx lr
+}
+#elif defined(__TI_COMPILER_VERSION__)
+uint32_t
+CPUbasepriGet(void)
+{
+ // Read BASEPRI.
+ __asm(" mrs r0, BASEPRI\n"
+ " bx lr\n");
+
+ // The following keeps the compiler happy, because it wants to see a
+ // return value from this function. It will generate code to return
+ // a zero. However, the real return is the "bx lr" above, so the
+ // return(0) is never executed and the function returns with the value
+ // you expect in R0.
+ return(0);
+}
+#else
+uint32_t __attribute__((naked))
+CPUbasepriGet(void)
+{
+ uint32_t ui32Ret;
+
+ // Read BASEPRI.
+ __asm volatile (" mrs %0, BASEPRI\n"
+ " bx lr\n"
+ : "=r"(ui32Ret)
+ );
+
+ // The return is handled in the inline assembly, but the compiler will
+ // still complain if there is not an explicit return here (despite the fact
+ // that this does not result in any code being produced because of the
+ // naked attribute).
+ return(ui32Ret);
+}
+#endif
+//*****************************************************************************
+//
+// Provide a small delay
+//
+//*****************************************************************************
+#if defined(DOXYGEN)
+void
+CPUdelay(uint32_t ui32Count)
+{
+ // This function is written in assembly. See cpu.c for compiler specific implementation.
+}
+#elif defined(__IAR_SYSTEMS_ICC__)
+void
+CPUdelay(uint32_t ui32Count)
+{
+ // Loop the specified number of times
+ __asm("CPUdelay:\n"
+ " subs r0, #1\n"
+ " bne.n CPUdelay\n"
+ " bx lr");
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+__asm void
+CPUdelay(uint32_t ui32Count)
+{
+ // Delay the specified number of times (3 cycles pr. loop)
+CPUdel
+ subs r0, #1;
+ bne CPUdel;
+ bx lr;
+}
+#elif defined(__TI_COMPILER_VERSION__)
+ // For CCS implement this function in pure assembly. This prevents the TI
+ // compiler from doing funny things with the optimizer.
+
+ // Loop the specified number of times
+__asm(" .sect \".text:NOROM_CPUdelay\"\n"
+ " .clink\n"
+ " .thumbfunc NOROM_CPUdelay\n"
+ " .thumb\n"
+ " .global NOROM_CPUdelay\n"
+ "NOROM_CPUdelay:\n"
+ " subs r0, #1\n"
+ " bne.n NOROM_CPUdelay\n"
+ " bx lr\n");
+#else
+// GCC
+void __attribute__((naked))
+CPUdelay(uint32_t ui32Count)
+{
+ // Loop the specified number of times
+ __asm volatile ("%=: subs %0, #1\n"
+ " bne %=b\n"
+ " bx lr\n"
+ : /* No output */
+ : "r" (ui32Count)
+ );
+}
+#endif
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/cpu.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/cpu.h
new file mode 100644
index 0000000..13fda81
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/cpu.h
@@ -0,0 +1,466 @@
+/******************************************************************************
+* Filename: cpu.h
+* Revised: 2018-06-04 16:10:13 +0200 (Mon, 04 Jun 2018)
+* Revision: 52111
+*
+* Description: Defines and prototypes for the CPU instruction wrapper
+* functions.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup system_cpu_group
+//! @{
+//! \addtogroup cpu_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __CPU_H__
+#define __CPU_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "../inc/hw_types.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_cpu_scs.h"
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// This section renames all functions that are not "static inline", so that
+// calling these functions will default to implementation in flash. At the end
+// of this file a second renaming will change the defaults to implementation in
+// ROM for available functions.
+//
+// To force use of the implementation in flash, e.g. for debugging:
+// - Globally: Define DRIVERLIB_NOROM at project level
+// - Per function: Use prefix "NOROM_" when calling the function
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #define CPUcpsid NOROM_CPUcpsid
+ #define CPUprimask NOROM_CPUprimask
+ #define CPUcpsie NOROM_CPUcpsie
+ #define CPUbasepriGet NOROM_CPUbasepriGet
+ #define CPUdelay NOROM_CPUdelay
+#endif
+
+//*****************************************************************************
+//
+// API Functions and prototypes
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \brief Disable all external interrupts.
+//!
+//! Use this function to disable all system interrupts. This function is
+//! implemented as a wrapper function for the CPSID instruction.
+//!
+//! \return Returns the state of \b PRIMASK on entry
+//
+//*****************************************************************************
+extern uint32_t CPUcpsid(void);
+
+//*****************************************************************************
+//
+//! \brief Get the current interrupt state.
+//!
+//! Use this function to retrieve the current state of the interrupts. This
+//! function is implemented as a wrapper function returning the state of
+//! PRIMASK.
+//!
+//! \return Returns the state of the \b PRIMASK (indicating whether interrupts
+//! are enabled or disabled).
+//
+//*****************************************************************************
+extern uint32_t CPUprimask(void);
+
+//*****************************************************************************
+//
+//! \brief Enable all external interrupts.
+//!
+//! Use this function to enable all system interrupts. This function is
+//! implemented as a wrapper function for the CPSIE instruction.
+//!
+//! \return Returns the state of \b PRIMASK on entry.
+//
+//*****************************************************************************
+extern uint32_t CPUcpsie(void);
+
+//*****************************************************************************
+//
+//! \brief Get the interrupt priority disable level.
+//!
+//! Use this function to get the level of priority that will disable
+//! interrupts with a lower priority level.
+//!
+//! \return Returns the value of the \b BASEPRI register.
+//
+//*****************************************************************************
+extern uint32_t CPUbasepriGet(void);
+
+//*****************************************************************************
+//
+//! \brief Provide a small non-zero delay using a simple loop counter.
+//!
+//! This function provides means for generating a constant length delay. It
+//! is written in assembly to keep the delay consistent across tool chains,
+//! avoiding the need to tune the delay based on the tool chain in use.
+//!
+//! \note It is not recommended using this function for long delays.
+//!
+//! Notice that interrupts can affect the delay if not manually disabled in advance.
+//!
+//! The delay depends on where code resides and the path for code fetching:
+//! - Code in flash, cache enabled, prefetch enabled : 4 cycles per loop (Default)
+//! - Code in flash, cache enabled, prefetch disabled : 5 cycles per loop
+//! - Code in flash, cache disabled : 7 cycles per loop
+//! - Code in SRAM : 6 cycles per loop
+//! - Code in GPRAM : 3 cycles per loop
+//!
+//! \note If using an RTOS, consider using RTOS provided delay functions because
+//! these will not block task scheduling and will potentially save power.
+//!
+//! Calculate delay count based on the wanted delay in microseconds (us):
+//! - ui32Count = [delay in us] * [CPU clock in MHz] / [cycles per loop]
+//!
+//! Example: 250 us delay with code in flash and with cache and prefetch enabled:
+//! - ui32Count = 250 * 48 / 4 = 3000
+//!
+//! \param ui32Count is the number of delay loop iterations to perform. Number must be greater than zero.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void CPUdelay(uint32_t ui32Count);
+
+//*****************************************************************************
+//
+//! \brief Wait for interrupt.
+//!
+//! Use this function to let the System CPU wait for the next interrupt. This
+//! function is implemented as a wrapper function for the WFI instruction.
+//!
+//! \return None
+//
+//*****************************************************************************
+#if defined(DOXYGEN)
+__STATIC_INLINE void
+CPUwfi(void)
+{
+ // This function is written in assembly. See cpu.h for compiler specific implementation.
+}
+#elif defined(__IAR_SYSTEMS_ICC__)
+__STATIC_INLINE void
+CPUwfi(void)
+{
+ // Wait for the next interrupt.
+ __asm(" wfi\n");
+}
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+__asm __STATIC_INLINE void
+CPUwfi(void)
+{
+ // Wait for the next interrupt.
+ wfi;
+ bx lr
+}
+#elif defined(__TI_COMPILER_VERSION__)
+__STATIC_INLINE void
+CPUwfi(void)
+{
+ // Wait for the next interrupt.
+ __asm(" wfi\n");
+}
+#else
+__STATIC_INLINE void __attribute__((always_inline))
+CPUwfi(void)
+{
+ // Wait for the next interrupt.
+ __asm volatile (" wfi\n");
+}
+#endif
+
+//*****************************************************************************
+//
+//! \brief Wait for event.
+//!
+//! Use this function to let the System CPU wait for the next event. This
+//! function is implemented as a wrapper function for the WFE instruction.
+//!
+//! \return None
+//
+//*****************************************************************************
+#if defined(DOXYGEN)
+__STATIC_INLINE void
+CPUwfe(void)
+{
+ // This function is written in assembly. See cpu.h for compiler specific implementation.
+}
+#elif defined(__IAR_SYSTEMS_ICC__)
+__STATIC_INLINE void
+CPUwfe(void)
+{
+ // Wait for the next event.
+ __asm(" wfe\n");
+}
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+__asm __STATIC_INLINE void
+CPUwfe(void)
+{
+ // Wait for the next event.
+ wfe;
+ bx lr
+}
+#elif defined(__TI_COMPILER_VERSION__)
+__STATIC_INLINE void
+CPUwfe(void)
+{
+ // Wait for the next event.
+ __asm(" wfe\n");
+}
+#else
+__STATIC_INLINE void __attribute__((always_inline))
+CPUwfe(void)
+{
+ // Wait for the next event.
+ __asm volatile (" wfe\n");
+}
+#endif
+
+//*****************************************************************************
+//
+//! \brief Send event.
+//!
+//! Use this function to let the System CPU send an event. This function is
+//! implemented as a wrapper function for the SEV instruction.
+//!
+//! \return None
+//
+//*****************************************************************************
+#if defined(DOXYGEN)
+__STATIC_INLINE void
+CPUsev(void)
+{
+ // This function is written in assembly. See cpu.h for compiler specific implementation.
+}
+#elif defined(__IAR_SYSTEMS_ICC__)
+__STATIC_INLINE void
+CPUsev(void)
+{
+ // Send event.
+ __asm(" sev\n");
+}
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+__asm __STATIC_INLINE void
+CPUsev(void)
+{
+ // Send event.
+ sev;
+ bx lr
+}
+#elif defined(__TI_COMPILER_VERSION__)
+__STATIC_INLINE void
+CPUsev(void)
+{
+ // Send event.
+ __asm(" sev\n");
+}
+#else
+__STATIC_INLINE void __attribute__((always_inline))
+CPUsev(void)
+{
+ // Send event.
+ __asm volatile (" sev\n");
+}
+#endif
+
+
+//*****************************************************************************
+//
+//! \brief Update the interrupt priority disable level.
+//!
+//! Use this function to change the level of priority that will disable
+//! interrupts with a lower priority level.
+//!
+//! \param ui32NewBasepri is the new basis priority level to set.
+//!
+//! \return None
+//
+//*****************************************************************************
+#if defined(DOXYGEN)
+__STATIC_INLINE void
+CPUbasepriSet(uint32_t ui32NewBasepri)
+{
+ // This function is written in assembly. See cpu.h for compiler specific implementation.
+}
+#elif defined(__IAR_SYSTEMS_ICC__)
+__STATIC_INLINE void
+CPUbasepriSet(uint32_t ui32NewBasepri)
+{
+ // Set the BASEPRI register.
+ __asm(" msr BASEPRI, r0\n");
+}
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+__asm __STATIC_INLINE void
+CPUbasepriSet(uint32_t ui32NewBasepri)
+{
+ // Set the BASEPRI register.
+ msr BASEPRI, r0;
+ bx lr
+}
+#elif defined(__TI_COMPILER_VERSION__)
+__STATIC_INLINE void
+CPUbasepriSet(uint32_t ui32NewBasepri)
+{
+ // Set the BASEPRI register.
+ __asm(" msr BASEPRI, r0\n");
+}
+#else
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wattributes"
+__STATIC_INLINE void __attribute__ ((naked))
+CPUbasepriSet(uint32_t ui32NewBasepri)
+{
+ // Set the BASEPRI register.
+ __asm volatile (" msr BASEPRI, %0\n"
+ " bx lr\n"
+ : /* No output */
+ : "r" (ui32NewBasepri)
+ );
+}
+#pragma GCC diagnostic pop
+#endif
+
+//*****************************************************************************
+//
+//! \brief Disable CPU write buffering (recommended for debug purpose only).
+//!
+//! This function helps debugging "bus fault crashes".
+//! Disables write buffer use during default memory map accesses.
+//!
+//! This causes all bus faults to be precise bus faults but decreases the
+//! performance of the processor because the stores to memory have to complete
+//! before the next instruction can be executed.
+//!
+//! \return None
+//!
+//! \sa \ref CPU_WriteBufferEnable()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+CPU_WriteBufferDisable( void )
+{
+ HWREGBITW( CPU_SCS_BASE + CPU_SCS_O_ACTLR, CPU_SCS_ACTLR_DISDEFWBUF_BITN ) = 1;
+}
+
+//*****************************************************************************
+//
+//! \brief Enable CPU write buffering (default setting).
+//!
+//! Re-enables write buffer during default memory map accesses if
+//! \ref CPU_WriteBufferDisable() has been used for bus fault debugging.
+//!
+//! \return None
+//!
+//! \sa \ref CPU_WriteBufferDisable()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+CPU_WriteBufferEnable( void )
+{
+ HWREGBITW( CPU_SCS_BASE + CPU_SCS_O_ACTLR, CPU_SCS_ACTLR_DISDEFWBUF_BITN ) = 0;
+}
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// Redirect to implementation in ROM when available.
+//
+//*****************************************************************************
+#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
+ #include "../driverlib/rom.h"
+ #ifdef ROM_CPUcpsid
+ #undef CPUcpsid
+ #define CPUcpsid ROM_CPUcpsid
+ #endif
+ #ifdef ROM_CPUprimask
+ #undef CPUprimask
+ #define CPUprimask ROM_CPUprimask
+ #endif
+ #ifdef ROM_CPUcpsie
+ #undef CPUcpsie
+ #define CPUcpsie ROM_CPUcpsie
+ #endif
+ #ifdef ROM_CPUbasepriGet
+ #undef CPUbasepriGet
+ #define CPUbasepriGet ROM_CPUbasepriGet
+ #endif
+ #ifdef ROM_CPUdelay
+ #undef CPUdelay
+ #define CPUdelay ROM_CPUdelay
+ #endif
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __CPU_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/cpu_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/cpu_doc.h
new file mode 100644
index 0000000..2981e8c
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/cpu_doc.h
@@ -0,0 +1,44 @@
+/******************************************************************************
+* Filename: cpu_doc.h
+* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016)
+* Revision: 45971
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+//! \addtogroup cpu_api
+//! @{
+//! \section sec_cpu Introduction
+//!
+//! The CPU API provides a set of functions performing very low-level control of the system CPU.
+//! All functions in this API are written in assembler in order to either access special registers
+//! or avoid any compiler optimizations. Each function exists in several compiler specific versions:
+//! One version for each supported compiler.
+//! @}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/crypto.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/crypto.c
new file mode 100644
index 0000000..1944f85
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/crypto.c
@@ -0,0 +1,943 @@
+/******************************************************************************
+* Filename: crypto.c
+* Revised: 2017-12-20 16:40:03 +0100 (Wed, 20 Dec 2017)
+* Revision: 50869
+*
+* Description: Driver for the Crypto module
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "crypto.h"
+
+//*****************************************************************************
+//
+// Handle support for DriverLib in ROM:
+// This section will undo prototype renaming made in the header file
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #undef CRYPTOAesLoadKey
+ #define CRYPTOAesLoadKey NOROM_CRYPTOAesLoadKey
+ #undef CRYPTOAesCbc
+ #define CRYPTOAesCbc NOROM_CRYPTOAesCbc
+ #undef CRYPTOAesCbcStatus
+ #define CRYPTOAesCbcStatus NOROM_CRYPTOAesCbcStatus
+ #undef CRYPTOAesEcb
+ #define CRYPTOAesEcb NOROM_CRYPTOAesEcb
+ #undef CRYPTOAesEcbStatus
+ #define CRYPTOAesEcbStatus NOROM_CRYPTOAesEcbStatus
+ #undef CRYPTOCcmAuthEncrypt
+ #define CRYPTOCcmAuthEncrypt NOROM_CRYPTOCcmAuthEncrypt
+ #undef CRYPTOCcmAuthEncryptStatus
+ #define CRYPTOCcmAuthEncryptStatus NOROM_CRYPTOCcmAuthEncryptStatus
+ #undef CRYPTOCcmAuthEncryptResultGet
+ #define CRYPTOCcmAuthEncryptResultGet NOROM_CRYPTOCcmAuthEncryptResultGet
+ #undef CRYPTOCcmInvAuthDecrypt
+ #define CRYPTOCcmInvAuthDecrypt NOROM_CRYPTOCcmInvAuthDecrypt
+ #undef CRYPTOCcmInvAuthDecryptStatus
+ #define CRYPTOCcmInvAuthDecryptStatus NOROM_CRYPTOCcmInvAuthDecryptStatus
+ #undef CRYPTOCcmInvAuthDecryptResultGet
+ #define CRYPTOCcmInvAuthDecryptResultGet NOROM_CRYPTOCcmInvAuthDecryptResultGet
+ #undef CRYPTODmaEnable
+ #define CRYPTODmaEnable NOROM_CRYPTODmaEnable
+ #undef CRYPTODmaDisable
+ #define CRYPTODmaDisable NOROM_CRYPTODmaDisable
+#endif
+
+//*****************************************************************************
+//
+// Write the key into the Key Ram.
+//
+//*****************************************************************************
+uint32_t
+CRYPTOAesLoadKey(uint32_t *pui32AesKey,
+ uint32_t ui32KeyLocation)
+{
+ uint32_t returnStatus = AES_KEYSTORE_READ_ERROR;
+
+ // Check the arguments.
+ ASSERT((ui32KeyLocation == CRYPTO_KEY_AREA_0) |
+ (ui32KeyLocation == CRYPTO_KEY_AREA_1) |
+ (ui32KeyLocation == CRYPTO_KEY_AREA_2) |
+ (ui32KeyLocation == CRYPTO_KEY_AREA_3) |
+ (ui32KeyLocation == CRYPTO_KEY_AREA_4) |
+ (ui32KeyLocation == CRYPTO_KEY_AREA_5) |
+ (ui32KeyLocation == CRYPTO_KEY_AREA_6) |
+ (ui32KeyLocation == CRYPTO_KEY_AREA_7));
+
+ // Disable the external interrupt to stop the interrupt form propagating
+ // from the module to the System CPU.
+ IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ);
+
+ // Clear any previously written key at the keyLocation
+ HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) = (0x00000001 << ui32KeyLocation);
+
+ // Enable internal interrupts.
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL;
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE |
+ CRYPTO_IRQEN_RESULT_AVAIL;
+
+ // Configure master control module.
+ HWREGBITW(CRYPTO_BASE + CRYPTO_O_ALGSEL, CRYPTO_ALGSEL_KEY_STORE_BITN) = 1;
+
+ // Clear any outstanding events.
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE |
+ CRYPTO_IRQCLR_RESULT_AVAIL);
+
+ // Configure key store module for 128 bit operation.
+ // Do not write to the register if the correct key size is already set.
+ // Writing to this register causes all current keys to be invalidated.
+ if (HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE) != KEY_STORE_SIZE_128) {
+ HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE) = KEY_STORE_SIZE_128;
+ }
+
+ // Enable keys to write (e.g. Key 0).
+ HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITEAREA) = (0x00000001 << ui32KeyLocation);
+
+ // Enable Crypto DMA channel 0.
+ HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1;
+
+ // Base address of the key in ext. memory.
+ HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32AesKey;
+
+ // Total key length in bytes (e.g. 16 for 1 x 128-bit key).
+ // Writing the length of the key enables the DMA operation.
+ HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = KEY_BLENGTH;
+
+ // Wait for the DMA operation to complete.
+ do
+ {
+ CPUdelay(1);
+ }
+ while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) &
+ (CRYPTO_IRQSTAT_DMA_BUS_ERR_M |
+ CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M |
+ CRYPTO_IRQSTAT_DMA_IN_DONE |
+ CRYPTO_IRQSTAT_RESULT_AVAIL_M)));
+
+ // Check for errors in DMA and key store.
+ if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) &
+ (CRYPTO_IRQSTAT_DMA_BUS_ERR |
+ CRYPTO_IRQSTAT_KEY_ST_WR_ERR)) == 0)
+ {
+ // Acknowledge/clear the interrupt and disable the master control.
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE |
+ CRYPTO_IRQCLR_RESULT_AVAIL);
+ HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000;
+
+ // Check key status, return success if key valid.
+ if(HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) & (0x00000001 << ui32KeyLocation))
+ {
+ returnStatus = AES_SUCCESS;
+ }
+ }
+
+ // Return status.
+ return returnStatus;
+}
+
+//*****************************************************************************
+//
+// Start an AES-CBC operation (encryption or decryption).
+//
+//*****************************************************************************
+uint32_t
+CRYPTOAesCbc(uint32_t *pui32MsgIn, uint32_t *pui32MsgOut, uint32_t ui32MsgLength,
+ uint32_t *pui32Nonce, uint32_t ui32KeyLocation,
+ bool bEncrypt, bool bIntEnable)
+{
+ uint32_t ui32CtrlVal;
+
+ // Enable internal interrupts.
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL;
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL;
+
+ // Clear any outstanding interrupts.
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE |
+ CRYPTO_IRQCLR_RESULT_AVAIL);
+
+ // Wait for interrupt lines from module to be cleared
+ while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE | CRYPTO_IRQSTAT_RESULT_AVAIL));
+
+ // If using interrupts clear any pending interrupts and enable interrupts
+ // for the Crypto module.
+ if(bIntEnable)
+ {
+ IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ);
+ IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ);
+ }
+
+ // Configure Master Control module.
+ HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_AES;
+
+ // Enable keys to read (e.g. Key 0).
+ HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = ui32KeyLocation;
+
+ //Wait until key is loaded to the AES module.
+ do
+ {
+ CPUdelay(1);
+ }
+ while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY));
+
+ // Check for Key store Read error.
+ if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)& CRYPTO_KEY_ST_RD_ERR))
+ {
+ return (AES_KEYSTORE_READ_ERROR);
+ }
+
+ // Write initialization vector.
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = pui32Nonce[0];
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = pui32Nonce[1];
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = pui32Nonce[2];
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = pui32Nonce[3];
+
+ // Configure AES engine for AES-CBC with 128-bit key size.
+ ui32CtrlVal = (CRYPTO_AESCTL_SAVE_CONTEXT | CRYPTO_AESCTL_CBC);
+ if(bEncrypt)
+ {
+ ui32CtrlVal |= CRYPTO_AES128_ENCRYPT;
+ }
+ else
+ {
+ ui32CtrlVal |= CRYPTO_AES128_DECRYPT;
+ }
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = ui32CtrlVal;
+
+ // Write the length of the crypto block (plain text).
+ // Low and high part (high part is assumed to be always 0).
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = ui32MsgLength;
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0;
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESAUTHLEN) = 0;
+
+ // Enable Crypto DMA channel 0.
+ HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1;
+
+ // Base address of the input data in ext. memory.
+ HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32MsgIn;
+
+ // Input data length in bytes, equal to the message.
+ HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32MsgLength;
+
+ // Enable Crypto DMA channel 1.
+ HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1;
+
+ // Set up the address and length of the output data.
+ HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = (uint32_t)pui32MsgOut;
+ HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = ui32MsgLength;
+
+ // Return success
+ return AES_SUCCESS;
+}
+
+//*****************************************************************************
+//
+// Check the result of an AES CBC operation
+//
+//*****************************************************************************
+uint32_t
+CRYPTOAesCbcStatus(void)
+{
+ return(CRYPTOAesEcbStatus());
+}
+
+//*****************************************************************************
+//
+// Start an AES-ECB operation (encryption or decryption).
+//
+//*****************************************************************************
+uint32_t
+CRYPTOAesEcb(uint32_t *pui32MsgIn, uint32_t *pui32MsgOut,
+ uint32_t ui32KeyLocation, bool bEncrypt,
+ bool bIntEnable)
+{
+ // Enable internal interrupts.
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL;
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL;
+
+ // Clear any outstanding interrupts.
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE |
+ CRYPTO_IRQCLR_RESULT_AVAIL);
+
+ // Wait for interrupt lines from module to be cleared
+ while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE | CRYPTO_IRQSTAT_RESULT_AVAIL));
+
+ // If using interrupts clear any pending interrupts and enable interrupts
+ // for the Crypto module.
+ if(bIntEnable)
+ {
+ IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ);
+ IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ);
+ }
+
+ // Configure Master Control module.
+ HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_AES;
+
+ // Enable keys to read (e.g. Key 0).
+ HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = ui32KeyLocation;
+
+ //Wait until key is loaded to the AES module.
+ do
+ {
+ CPUdelay(1);
+ }
+ while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY));
+
+ // Check for Key store Read error.
+ if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)& CRYPTO_KEY_ST_RD_ERR))
+ {
+ return (AES_KEYSTORE_READ_ERROR);
+ }
+
+ // Configure AES engine (program AES-ECB-128 encryption and no
+ // initialization vector - IV).
+ if(bEncrypt)
+ {
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = CRYPTO_AES128_ENCRYPT;
+ }
+ else
+ {
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = CRYPTO_AES128_DECRYPT;
+ }
+
+ // Write the length of the data.
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = AES_ECB_LENGTH;
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0;
+
+ // Enable Crypto DMA channel 0.
+ HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1;
+
+ // Base address of the input data in ext. memory.
+ HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32MsgIn;
+
+ // Input data length in bytes, equal to the message.
+ HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = AES_ECB_LENGTH;
+
+ // Enable Crypto DMA channel 1.
+ HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1;
+
+ // Set up the address and length of the output data.
+ HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = (uint32_t)pui32MsgOut;
+ HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = AES_ECB_LENGTH;
+
+ // Return success
+ return AES_SUCCESS;
+}
+
+//*****************************************************************************
+//
+// Check the result of an AES ECB operation
+//
+//*****************************************************************************
+uint32_t
+CRYPTOAesEcbStatus(void)
+{
+ uint32_t ui32Status;
+
+ // Get the current DMA status.
+ ui32Status = HWREG(CRYPTO_BASE + CRYPTO_O_DMASTAT);
+
+ // Check if DMA is still busy.
+ if(ui32Status & CRYPTO_DMA_BSY)
+ {
+ return (AES_DMA_BSY);
+ }
+
+ // Check the status of the DMA operation - return error if not success.
+ if(ui32Status & CRYPTO_DMA_BUS_ERROR)
+ {
+ return (AES_DMA_BUS_ERROR);
+ }
+
+ // Operation successful - disable interrupt and return success.
+ IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ);
+ return (AES_SUCCESS);
+}
+
+//*****************************************************************************
+//
+// Start CCM operation
+//
+//*****************************************************************************
+uint32_t
+CRYPTOCcmAuthEncrypt(bool bEncrypt, uint32_t ui32AuthLength ,
+ uint32_t *pui32Nonce, uint32_t *pui32PlainText,
+ uint32_t ui32PlainTextLength, uint32_t *pui32Header,
+ uint32_t ui32HeaderLength, uint32_t ui32KeyLocation,
+ uint32_t ui32FieldLength, bool bIntEnable)
+{
+ uint32_t ui32CtrlVal;
+ uint32_t i;
+ uint32_t *pui32CipherText;
+ union {
+ uint32_t w[4];
+ uint8_t b[16];
+ } ui8InitVec;
+
+ // Input address for the encryption engine is the same as the output.
+ pui32CipherText = pui32PlainText;
+
+ // Disable global interrupt, enable local interrupt and clear any pending
+ // interrupts.
+ IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ);
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE |
+ CRYPTO_IRQCLR_RESULT_AVAIL);
+
+ // Enable internal interrupts.
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL;
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE |
+ CRYPTO_IRQEN_RESULT_AVAIL;
+
+ // Configure master control module for AES operation.
+ HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_AES;
+
+ // Enable keys to read (e.g. Key 0).
+ HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = ui32KeyLocation;
+
+ // Wait until key is loaded to the AES module.
+ do
+ {
+ CPUdelay(1);
+ }
+ while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY));
+
+ // Check for Key store Read error.
+ if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)& CRYPTO_KEY_ST_RD_ERR))
+ {
+ return (AES_KEYSTORE_READ_ERROR);
+ }
+
+ // Prepare the initialization vector (IV),
+ // Length of Nonce l(n) = 15 - ui32FieldLength.
+ ui8InitVec.b[0] = ui32FieldLength - 1;
+ for(i = 0; i < 12; i++)
+ {
+ ui8InitVec.b[i + 1] = ((uint8_t*)pui32Nonce)[i];
+ }
+ if(ui32FieldLength == 2)
+ {
+ ui8InitVec.b[13] = ((uint8_t*)pui32Nonce)[12];
+ }
+ else
+ {
+ ui8InitVec.b[13] = 0;
+ }
+ ui8InitVec.b[14] = 0;
+ ui8InitVec.b[15] = 0;
+
+ // Write initialization vector.
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = ui8InitVec.w[0];
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = ui8InitVec.w[1];
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = ui8InitVec.w[2];
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = ui8InitVec.w[3];
+
+ // Configure AES engine.
+ ui32CtrlVal = ((ui32FieldLength - 1) << CRYPTO_AESCTL_CCM_L_S);
+ if ( ui32AuthLength >= 2 ) {
+ ui32CtrlVal |= ((( ui32AuthLength - 2 ) >> 1 ) << CRYPTO_AESCTL_CCM_M_S );
+ }
+ ui32CtrlVal |= CRYPTO_AESCTL_CCM;
+ ui32CtrlVal |= CRYPTO_AESCTL_CTR;
+ ui32CtrlVal |= CRYPTO_AESCTL_SAVE_CONTEXT;
+ ui32CtrlVal |= (KEY_STORE_SIZE_128 << CRYPTO_AESCTL_KEY_SIZE_S);
+ ui32CtrlVal |= (1 << CRYPTO_AESCTL_DIR_S);
+ ui32CtrlVal |= (CRYPTO_AES_CTR_128 << CRYPTO_AESCTL_CTR_WIDTH_S);
+
+ // Write the configuration for 128 bit AES-CCM.
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = ui32CtrlVal;
+
+ // Write the length of the crypto block (plain text).
+ // Low and high part (high part is assumed to be always 0).
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = ui32PlainTextLength;
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0;
+
+ // Write the length of the header field.
+ // Also called AAD - Additional Authentication Data.
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESAUTHLEN) = ui32HeaderLength;
+
+ // Check if any header information (AAD).
+ // If so configure the DMA controller to fetch the header.
+ if(ui32HeaderLength != 0)
+ {
+ // Enable DMA channel 0.
+ HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1;
+
+ // Register the base address of the header (AAD).
+ HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32Header;
+
+ // Header length in bytes (may be non-block size aligned).
+ HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32HeaderLength;
+
+ // Wait for completion of the header data transfer, DMA_IN_DONE.
+ do
+ {
+ CPUdelay(1);
+ }
+ while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_IRQSTAT_DMA_IN_DONE));
+
+ // Check for DMA errors.
+ if(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_DMA_BUS_ERR)
+ {
+ return AES_DMA_BUS_ERROR;
+ }
+ }
+
+ // Clear interrupt status.
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE |
+ CRYPTO_IRQCLR_RESULT_AVAIL);
+
+ // Wait for interrupt lines from module to be cleared
+ while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE | CRYPTO_IRQSTAT_RESULT_AVAIL));
+
+ // Disable CRYPTO_IRQEN_DMA_IN_DONE interrupt as we only
+ // want interrupt to trigger once RESULT_AVAIL occurs.
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~CRYPTO_IRQEN_DMA_IN_DONE;
+
+
+ // Is using interrupts enable globally.
+ if(bIntEnable)
+ {
+ IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ);
+ IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ);
+ }
+
+ // Enable interrupts locally.
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL;
+
+ // Perform encryption if requested.
+ if(bEncrypt)
+ {
+ // Enable DMA channel 0
+ HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1;
+
+ // base address of the payload data in ext. memory.
+ HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) =
+ (uint32_t)pui32PlainText;
+
+ // Enable DMA channel 1
+ HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1;
+
+ // Base address of the output data buffer.
+ HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) =
+ (uint32_t)pui32CipherText;
+
+ // Payload data length in bytes, equal to the plaintext length.
+ HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32PlainTextLength;
+ // Output data length in bytes, equal to the plaintext length.
+ HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = ui32PlainTextLength;
+ }
+
+ return AES_SUCCESS;
+}
+
+//*****************************************************************************
+//
+// Check the result of an AES CCM operation.
+//
+//*****************************************************************************
+uint32_t
+CRYPTOCcmAuthEncryptStatus(void)
+{
+ uint32_t ui32Status;
+
+ // Get the current DMA status.
+ ui32Status = HWREG(CRYPTO_BASE + CRYPTO_O_DMASTAT);
+
+ // Check if DMA is still busy.
+ if(ui32Status & CRYPTO_DMA_BSY)
+ {
+ return (AES_DMA_BSY);
+ }
+
+ // Check the status of the DMA operation - return error if not success.
+ if(ui32Status & CRYPTO_DMA_BUS_ERROR)
+ {
+ return (AES_DMA_BUS_ERROR);
+ }
+
+ // Operation successful - disable interrupt and return success.
+ IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ);
+ return (AES_SUCCESS);
+}
+
+//*****************************************************************************
+//
+// Get the result of an AES-CCM operation
+//
+//*****************************************************************************
+uint32_t
+CRYPTOCcmAuthEncryptResultGet(uint32_t ui32TagLength, uint32_t *pui32CcmTag)
+{
+ uint32_t volatile ui32Tag[4];
+ uint32_t ui32Idx;
+
+ // Result has already been copied to the output buffer by DMA
+ // Disable master control.
+ HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000;
+
+ // Read tag - wait for the context ready bit.
+ do
+ {
+ CPUdelay(1);
+ }
+ while(!(HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) &
+ CRYPTO_AESCTL_SAVED_CONTEXT_RDY));
+
+ // Read the Tag registers.
+ ui32Tag[0] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT0);
+ ui32Tag[1] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT1);
+ ui32Tag[2] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT2);
+ ui32Tag[3] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT3);
+
+ for(ui32Idx = 0; ui32Idx < ui32TagLength ; ui32Idx++)
+ {
+ *((uint8_t*)pui32CcmTag + ui32Idx) = *((uint8_t*)ui32Tag + ui32Idx);
+ }
+
+ // Operation successful - clear interrupt status.
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE |
+ CRYPTO_IRQCLR_RESULT_AVAIL);
+ return AES_SUCCESS;
+}
+
+//*****************************************************************************
+//
+// Start a CCM Decryption and Inverse Authentication operation.
+//
+//*****************************************************************************
+uint32_t
+CRYPTOCcmInvAuthDecrypt(bool bDecrypt, uint32_t ui32AuthLength,
+ uint32_t *pui32Nonce, uint32_t *pui32CipherText,
+ uint32_t ui32CipherTextLength,
+ uint32_t *pui32Header, uint32_t ui32HeaderLength,
+ uint32_t ui32KeyLocation,
+ uint32_t ui32FieldLength, bool bIntEnable)
+{
+ uint32_t ui32CtrlVal;
+ uint32_t i;
+ uint32_t *pui32PlainText;
+ uint32_t ui32CryptoBlockLength;
+ union {
+ uint32_t w[4];
+ uint8_t b[16];
+ } ui8InitVec;
+
+ // Input address for the encryption engine is the same as the output.
+ pui32PlainText = pui32CipherText;
+
+ // Disable global interrupt, enable local interrupt and clear any pending.
+ // interrupts.
+ IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ);
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE |
+ CRYPTO_IRQCLR_RESULT_AVAIL);
+ // Enable internal interrupts.
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL;
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE |
+ CRYPTO_IRQEN_RESULT_AVAIL;
+
+ // Configure master control module for AES operation.
+ HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_AES;
+
+ // Enable keys to read (e.g. Key 0).
+ HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = ui32KeyLocation;
+
+ // Wait until key is loaded to the AES module.
+ do
+ {
+ CPUdelay(1);
+ }
+ while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY));
+
+ // Check for Key store Read error.
+ if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)& CRYPTO_KEY_ST_RD_ERR))
+ {
+ return (AES_KEYSTORE_READ_ERROR);
+ }
+
+ // Prepare the initialization vector (IV),
+ // Length of Nonce l(n) = 15 - ui32FieldLength.
+ ui8InitVec.b[0] = ui32FieldLength - 1;
+ for(i = 0; i < 12; i++)
+ {
+ ui8InitVec.b[i + 1] = ((uint8_t*)pui32Nonce)[i];
+ }
+ if(ui32FieldLength == 2)
+ {
+ ui8InitVec.b[13] = ((uint8_t*)pui32Nonce)[12];
+ }
+ else
+ {
+ ui8InitVec.b[13] = 0;
+ }
+ ui8InitVec.b[14] = 0;
+ ui8InitVec.b[15] = 0;
+
+ // Write initialization vector.
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = ui8InitVec.w[0];
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = ui8InitVec.w[1];
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = ui8InitVec.w[2];
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = ui8InitVec.w[3];
+
+ // Configure AES engine
+ ui32CryptoBlockLength = ui32CipherTextLength - ui32AuthLength;
+ ui32CtrlVal = ((ui32FieldLength - 1) << CRYPTO_AESCTL_CCM_L_S);
+ if ( ui32AuthLength >= 2 ) {
+ ui32CtrlVal |= ((( ui32AuthLength - 2 ) >> 1 ) << CRYPTO_AESCTL_CCM_M_S );
+ }
+ ui32CtrlVal |= CRYPTO_AESCTL_CCM;
+ ui32CtrlVal |= CRYPTO_AESCTL_CTR;
+ ui32CtrlVal |= CRYPTO_AESCTL_SAVE_CONTEXT;
+ ui32CtrlVal |= (KEY_STORE_SIZE_128 << CRYPTO_AESCTL_KEY_SIZE_S);
+ ui32CtrlVal |= (0 << CRYPTO_AESCTL_DIR_S);
+ ui32CtrlVal |= (CRYPTO_AES_CTR_128 << CRYPTO_AESCTL_CTR_WIDTH_S);
+
+ // Write the configuration for 128 bit AES-CCM.
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = ui32CtrlVal;
+
+ // Write the length of the crypto block (plain text).
+ // Low and high part (high part is assumed to be always 0).
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = ui32CryptoBlockLength;
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0;
+
+ // Write the length of the header field.
+ // Also called AAD - Additional Authentication Data.
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESAUTHLEN) = ui32HeaderLength;
+
+ // Check if any header information (AAD).
+ // If so configure the DMA controller to fetch the header.
+ if(ui32HeaderLength != 0)
+ {
+ // Enable DMA channel 0.
+ HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1;
+
+ // Register the base address of the header (AAD).
+ HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32Header;
+
+ // Header length in bytes (may be non-block size aligned).
+ HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32HeaderLength;
+
+ // Wait for completion of the header data transfer, DMA_IN_DONE.
+ do
+ {
+ CPUdelay(1);
+ }
+ while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_IRQSTAT_DMA_IN_DONE));
+
+ // Check for DMA errors.
+ if(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_DMA_BUS_ERR)
+ {
+ return AES_DMA_BUS_ERROR;
+ }
+ }
+
+ // Clear interrupt status.
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE |
+ CRYPTO_IRQCLR_RESULT_AVAIL);
+
+ // Wait for interrupt lines from module to be cleared
+ while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE | CRYPTO_IRQSTAT_RESULT_AVAIL));
+
+ // Disable CRYPTO_IRQEN_DMA_IN_DONE interrupt as we only
+ // want interrupt to trigger once RESULT_AVAIL occurs.
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~CRYPTO_IRQEN_DMA_IN_DONE;
+
+ // Is using interrupts - clear and enable globally.
+ if(bIntEnable)
+ {
+ IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ);
+ IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ);
+ }
+
+ // Enable internal interrupts.
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL;
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL;
+
+ // Perform decryption if requested.
+ if(bDecrypt)
+ {
+ // Configure the DMA controller - enable both DMA channels.
+ HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1;
+
+ // Base address of the payload data in ext. memory.
+ HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) =
+ (uint32_t)pui32CipherText;
+
+ // Payload data length in bytes, equal to the cipher text length.
+ HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32CryptoBlockLength;
+
+ // Enable DMA channel 1.
+ HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1;
+
+ // Base address of the output data buffer.
+ HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) =
+ (uint32_t)pui32PlainText;
+
+ // Output data length in bytes, equal to the cipher text length.
+ HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = ui32CryptoBlockLength;
+ }
+
+ return AES_SUCCESS;
+}
+
+//*****************************************************************************
+//
+// Checks CCM decrypt and Inverse Authentication result.
+//
+//*****************************************************************************
+uint32_t
+CRYPTOCcmInvAuthDecryptStatus(void)
+{
+ uint32_t ui32Status;
+
+ // Get the current DMA status.
+ ui32Status = HWREG(CRYPTO_BASE + CRYPTO_O_DMASTAT);
+
+ // Check if DMA is still busy.
+ if(ui32Status & CRYPTO_DMA_BSY)
+ {
+ return (AES_DMA_BSY);
+ }
+
+ // Check the status of the DMA operation - return error if not success.
+ if(ui32Status & CRYPTO_DMA_BUS_ERROR)
+ {
+ return (AES_DMA_BUS_ERROR);
+ }
+
+ // Operation successful - disable interrupt and return success
+ IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ);
+ return (AES_SUCCESS);
+}
+
+//*****************************************************************************
+//
+// Get the result of the CCM operation.
+//
+//*****************************************************************************
+uint32_t
+CRYPTOCcmInvAuthDecryptResultGet(uint32_t ui32AuthLength,
+ uint32_t *pui32CipherText,
+ uint32_t ui32CipherTextLength,
+ uint32_t *pui32CcmTag)
+{
+ uint32_t volatile ui32Tag[4];
+ uint32_t ui32TagIndex;
+ uint32_t i;
+ uint32_t ui32Idx;
+
+ ui32TagIndex = ui32CipherTextLength - ui32AuthLength;
+
+ // Result has already been copied to the output buffer by DMA
+ // Disable master control.
+ HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000;
+
+ // Read tag - wait for the context ready bit.
+ do
+ {
+ CPUdelay(1);
+ }
+ while(!(HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) &
+ CRYPTO_AESCTL_SAVED_CONTEXT_RDY));
+
+ // Read the Tag registers.
+ ui32Tag[0] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT0);
+ ui32Tag[1] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT1);
+ ui32Tag[2] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT2);
+ ui32Tag[3] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT3);
+
+ for(ui32Idx = 0; ui32Idx < ui32AuthLength ; ui32Idx++)
+ {
+ *((uint8_t*)pui32CcmTag + ui32Idx) = *((uint8_t*)ui32Tag + ui32Idx);
+ }
+
+ // Operation successful - clear interrupt status.
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE |
+ CRYPTO_IRQCLR_RESULT_AVAIL);
+
+ // Verify the Tag.
+ for(i = 0; i < ui32AuthLength; i++)
+ {
+ if(*((uint8_t *)pui32CcmTag + i) !=
+ (*((uint8_t *)pui32CipherText + ui32TagIndex + i)))
+ {
+ return CCM_AUTHENTICATION_FAILED;
+ }
+ }
+
+ return AES_SUCCESS;
+}
+
+//*****************************************************************************
+//
+// Enable Crypto DMA operation
+//
+//*****************************************************************************
+void
+CRYPTODmaEnable(uint32_t ui32Channels)
+{
+ // Check the arguments.
+ ASSERT((ui32Channels & CRYPTO_DMA_CHAN0) |
+ (ui32Channels & CRYPTO_DMA_CHAN1));
+
+ // Enable the selected channels,
+ if(ui32Channels & CRYPTO_DMA_CHAN0)
+ {
+ HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1;
+ }
+ if(ui32Channels & CRYPTO_DMA_CHAN1)
+ {
+ HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1;
+ }
+}
+
+//*****************************************************************************
+//
+// Disable Crypto DMA operation
+//
+//*****************************************************************************
+void
+CRYPTODmaDisable(uint32_t ui32Channels)
+{
+ // Check the arguments.
+ ASSERT((ui32Channels & CRYPTO_DMA_CHAN0) |
+ (ui32Channels & CRYPTO_DMA_CHAN1));
+
+ // Enable the selected channels.
+ if(ui32Channels & CRYPTO_DMA_CHAN0)
+ {
+ HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 0;
+ }
+ if(ui32Channels & CRYPTO_DMA_CHAN1)
+ {
+ HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 0;
+ }
+}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/crypto.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/crypto.h
new file mode 100644
index 0000000..e9e4496
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/crypto.h
@@ -0,0 +1,856 @@
+/******************************************************************************
+* Filename: crypto.h
+* Revised: 2018-01-12 18:46:31 +0100 (Fri, 12 Jan 2018)
+* Revision: 51161
+*
+* Description: AES header file.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup peripheral_group
+//! @{
+//! \addtogroup crypto_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __CRYPTO_H__
+#define __CRYPTO_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "../inc/hw_types.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_ints.h"
+#include "../inc/hw_crypto.h"
+#include "debug.h"
+#include "interrupt.h"
+#include "cpu.h"
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// This section renames all functions that are not "static inline", so that
+// calling these functions will default to implementation in flash. At the end
+// of this file a second renaming will change the defaults to implementation in
+// ROM for available functions.
+//
+// To force use of the implementation in flash, e.g. for debugging:
+// - Globally: Define DRIVERLIB_NOROM at project level
+// - Per function: Use prefix "NOROM_" when calling the function
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #define CRYPTOAesLoadKey NOROM_CRYPTOAesLoadKey
+ #define CRYPTOAesCbc NOROM_CRYPTOAesCbc
+ #define CRYPTOAesCbcStatus NOROM_CRYPTOAesCbcStatus
+ #define CRYPTOAesEcb NOROM_CRYPTOAesEcb
+ #define CRYPTOAesEcbStatus NOROM_CRYPTOAesEcbStatus
+ #define CRYPTOCcmAuthEncrypt NOROM_CRYPTOCcmAuthEncrypt
+ #define CRYPTOCcmAuthEncryptStatus NOROM_CRYPTOCcmAuthEncryptStatus
+ #define CRYPTOCcmAuthEncryptResultGet NOROM_CRYPTOCcmAuthEncryptResultGet
+ #define CRYPTOCcmInvAuthDecrypt NOROM_CRYPTOCcmInvAuthDecrypt
+ #define CRYPTOCcmInvAuthDecryptStatus NOROM_CRYPTOCcmInvAuthDecryptStatus
+ #define CRYPTOCcmInvAuthDecryptResultGet NOROM_CRYPTOCcmInvAuthDecryptResultGet
+ #define CRYPTODmaEnable NOROM_CRYPTODmaEnable
+ #define CRYPTODmaDisable NOROM_CRYPTODmaDisable
+#endif
+
+//*****************************************************************************
+//
+// Length of AES Electronic Code Book (ECB) block in bytes
+//
+//*****************************************************************************
+#define AES_ECB_LENGTH 16
+
+//*****************************************************************************
+//
+// Values that can be passed to CryptoIntEnable, CryptoIntDisable, and CryptoIntClear
+// as the ui32IntFlags parameter, and returned from CryptoIntStatus.
+//
+//*****************************************************************************
+#define CRYPTO_DMA_IN_DONE 0x00000002 // DMA done interrupt mask
+#define CRYPTO_RESULT_RDY 0x00000001 // Result ready interrupt mask
+#define CRYPTO_DMA_BUS_ERR 0x80000000 // DMA Bus error
+#define CRYPTO_KEY_ST_WR_ERR 0x40000000 // Key Store Write failed
+#define CRYPTO_KEY_ST_RD_ERR 0x20000000 // Key Store Read failed
+
+#define CRYPTO_IRQTYPE_LEVEL 0x00000001 // Crypto Level interrupt enabled
+#define CRYPTO_IRQTYPE_PULSE 0x00000000 // Crypto pulse interrupt enabled
+
+#define CRYPTO_DMA_CHAN0 0x00000001 // Crypto DMA Channel 0
+#define CRYPTO_DMA_CHAN1 0x00000002 // Crypto DMA Channel 1
+
+#define CRYPTO_AES128_ENCRYPT 0x0000000C //
+#define CRYPTO_AES128_DECRYPT 0x00000008 //
+
+#define CRYPTO_DMA_READY 0x00000000 // DMA ready
+#define CRYPTO_DMA_BSY 0x00000003 // DMA busy
+#define CRYPTO_DMA_BUS_ERROR 0x00020000 // DMA encountered bus error
+
+//*****************************************************************************
+//
+// General constants
+//
+//*****************************************************************************
+
+// AES module return codes
+#define AES_SUCCESS 0
+#define AES_KEYSTORE_READ_ERROR 1
+#define AES_KEYSTORE_WRITE_ERROR 2
+#define AES_DMA_BUS_ERROR 3
+#define CCM_AUTHENTICATION_FAILED 4
+#define AES_ECB_TEST_ERROR 8
+#define AES_NULL_ERROR 9
+#define AES_CCM_TEST_ERROR 10
+#define AES_DMA_BSY 11
+
+// Key store module defines
+#define STATE_BLENGTH 16 // Number of bytes in State
+#define KEY_BLENGTH 16 // Number of bytes in Key
+#define KEY_EXP_LENGTH 176 // Nb * (Nr+1) * 4
+
+#define KEY_STORE_SIZE_128 0x00000001
+#define KEY_STORE_SIZE_192 0x00000002
+#define KEY_STORE_SIZE_256 0x00000003
+#define KEY_STORE_SIZE_BITS 0x00000003
+
+//*****************************************************************************
+//
+// For 128 bit key all 8 Key Area locations from 0 to 8 are valid
+// However for 192 bit and 256 bit keys, only even Key Areas 0, 2, 4, 6
+// are valid.
+//
+//*****************************************************************************
+#define CRYPTO_KEY_AREA_0 0
+#define CRYPTO_KEY_AREA_1 1
+#define CRYPTO_KEY_AREA_2 2
+#define CRYPTO_KEY_AREA_3 3
+#define CRYPTO_KEY_AREA_4 4
+#define CRYPTO_KEY_AREA_5 5
+#define CRYPTO_KEY_AREA_6 6
+#define CRYPTO_KEY_AREA_7 7
+
+//*****************************************************************************
+//
+// Defines for the current AES operation
+//
+//*****************************************************************************
+#define CRYPTO_AES_NONE 0
+#define CRYPTO_AES_KEYL0AD 1
+#define CRYPTO_AES_ECB 2
+#define CRYPTO_AES_CCM 3
+#define CRYPTO_AES_RNG 4
+#define CRYPTO_AES_CBC 5
+
+//*****************************************************************************
+//
+// Defines for the AES-CTR mode counter width
+//
+//*****************************************************************************
+#define CRYPTO_AES_CTR_32 0x0
+#define CRYPTO_AES_CTR_64 0x1
+#define CRYPTO_AES_CTR_96 0x2
+#define CRYPTO_AES_CTR_128 0x3
+
+//*****************************************************************************
+//
+// API Functions and prototypes
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \brief Write the key into the Key Ram.
+//!
+//! The \c ui32KeyLocation parameter is an enumerated type which specifies
+//! the Key Ram location in which the key is stored.
+//!
+//! The pointer \c pui8AesKey has the address where the Key is stored.
+//!
+//! \param pui32AesKey is a pointer to an AES Key.
+//! \param ui32KeyLocation is the location of the key in Key RAM.
+//! This parameter can have any of the following values:
+//! - \ref CRYPTO_KEY_AREA_0
+//! - \ref CRYPTO_KEY_AREA_1
+//! - \ref CRYPTO_KEY_AREA_2
+//! - \ref CRYPTO_KEY_AREA_3
+//! - \ref CRYPTO_KEY_AREA_4
+//! - \ref CRYPTO_KEY_AREA_5
+//! - \ref CRYPTO_KEY_AREA_6
+//! - \ref CRYPTO_KEY_AREA_7
+//!
+//! \return Returns status of the function:
+//! - \ref AES_SUCCESS
+//! - \ref AES_KEYSTORE_READ_ERROR
+//
+//*****************************************************************************
+extern uint32_t CRYPTOAesLoadKey(uint32_t *pui32AesKey,
+ uint32_t ui32KeyLocation);
+
+//*****************************************************************************
+//
+//! \brief Start an AES-CBC operation (encryption or decryption).
+//!
+//! The function starts an AES CBC mode encrypt or decrypt operation.
+//! End operation can be detected by enabling interrupt or by polling
+//! CRYPTOAesCbcStatus(). Result of operation is returned by CRYPTOAesCbcStatus().
+//!
+//! \param pui32MsgIn is a pointer to the input data.
+//! \param pui32MsgOut is a pointer to the output data.
+//! \param ui32MsgLength is the length in bytes of the input data.
+//! \param pui32Nonce is a pointer to 16-byte Nonce.
+//! \param ui32KeyLocation is the location of the key in Key RAM.
+//! This parameter can have any of the following values:
+//! - \ref CRYPTO_KEY_AREA_0
+//! - \ref CRYPTO_KEY_AREA_1
+//! - \ref CRYPTO_KEY_AREA_2
+//! - \ref CRYPTO_KEY_AREA_3
+//! - \ref CRYPTO_KEY_AREA_4
+//! - \ref CRYPTO_KEY_AREA_5
+//! - \ref CRYPTO_KEY_AREA_6
+//! - \ref CRYPTO_KEY_AREA_7
+//! \param bEncrypt is set \c true to encrypt or set \c false to decrypt.
+//! \param bIntEnable is set \c true to enable Crypto interrupts or \c false to
+//! disable Crypto interrupt.
+//!
+//! \return Returns status of the AES-CBC operation:
+//! - \ref AES_SUCCESS
+//! - \ref AES_KEYSTORE_READ_ERROR
+//!
+//! \sa \ref CRYPTOAesCbcStatus()
+//
+//*****************************************************************************
+extern uint32_t CRYPTOAesCbc(uint32_t *pui32MsgIn, uint32_t *pui32MsgOut,
+ uint32_t ui32MsgLength, uint32_t *pui32Nonce,
+ uint32_t ui32KeyLocation, bool bEncrypt,
+ bool bIntEnable);
+
+//*****************************************************************************
+//
+//! \brief Check the result of an AES CBC operation.
+//!
+//! This function should be called after \ref CRYPTOAesCbc() function to
+//! check if the AES CBC operation was successful.
+//!
+//! \return Returns the status of the AES CBC operation:
+//! - \ref AES_SUCCESS : Successful.
+//! - \ref AES_DMA_BUS_ERROR : Failed.
+//! - \ref AES_DMA_BSY : Operation is ongoing.
+//!
+//! \sa \ref CRYPTOAesCbc()
+//
+//*****************************************************************************
+extern uint32_t CRYPTOAesCbcStatus(void);
+
+//*****************************************************************************
+//
+//! \brief Start an AES-ECB operation (encryption or decryption).
+//!
+//! The \c ui32KeyLocation parameter is an enumerated type which specifies
+//! the Key Ram location in which the key is stored.
+//!
+//! \param pui32MsgIn is a pointer to the input data.
+//! \param pui32MsgOut is a pointer to the output data.
+//! \param ui32KeyLocation is the location of the key in Key RAM.
+//! This parameter can have any of the following values:
+//! - \ref CRYPTO_KEY_AREA_0
+//! - \ref CRYPTO_KEY_AREA_1
+//! - \ref CRYPTO_KEY_AREA_2
+//! - \ref CRYPTO_KEY_AREA_3
+//! - \ref CRYPTO_KEY_AREA_4
+//! - \ref CRYPTO_KEY_AREA_5
+//! - \ref CRYPTO_KEY_AREA_6
+//! - \ref CRYPTO_KEY_AREA_7
+//! \param bEncrypt is set \c true to encrypt or set \c false to decrypt.
+//! \param bIntEnable is set \c true to enable Crypto interrupts or \c false to
+//! disable Crypto interrupt.
+//!
+//! \return Returns status of the AES-ECB operation:
+//! - \ref AES_SUCCESS
+//! - \ref AES_KEYSTORE_READ_ERROR
+//!
+//! \sa \ref CRYPTOAesEcbStatus()
+//
+//*****************************************************************************
+extern uint32_t CRYPTOAesEcb(uint32_t *pui32MsgIn, uint32_t *pui32MsgOut,
+ uint32_t ui32KeyLocation, bool bEncrypt,
+ bool bIntEnable);
+
+//*****************************************************************************
+//
+//! \brief Check the result of an AES ECB operation.
+//!
+//! This function should be called after \ref CRYPTOAesEcb() function to
+//! check if the AES ECB operation was successful.
+//!
+//! \return Returns the status of the AES ECB operation:
+//! - \ref AES_SUCCESS : Successful.
+//! - \ref AES_DMA_BUS_ERROR : Failed.
+//! - \ref AES_DMA_BSY : Operation is ongoing.
+//!
+//! \sa \ref CRYPTOAesEcb()
+//
+//*****************************************************************************
+extern uint32_t CRYPTOAesEcbStatus(void);
+
+//*****************************************************************************
+//
+//! \brief Finish the encryption operation by resetting the operation mode.
+//!
+//! This function should be called after \ref CRYPTOAesEcbStatus() has reported
+//! that the operation is finished successfully.
+//!
+//! \return None
+//!
+//! \sa \ref CRYPTOAesEcbStatus()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+CRYPTOAesEcbFinish(void)
+{
+ // Result has already been copied to the output buffer by DMA.
+ // Disable master control/DMA clock and clear the operating mode.
+ HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000;
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = 0x00000000;
+}
+
+//*****************************************************************************
+//
+//! \brief Finish the encryption operation by resetting the operation mode.
+//!
+//! This function should be called after \ref CRYPTOAesCbcStatus() has reported
+//! that the operation is finished successfully.
+//!
+//! \return None
+//!
+//! \sa \ref CRYPTOAesCbcStatus()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+CRYPTOAesCbcFinish(void)
+{
+ // Result has already been copied to the output buffer by DMA.
+ // Disable master control/DMA clock and clear the operating mode.
+ HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000;
+ HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = 0x00000000;
+}
+
+//*****************************************************************************
+//
+//! \brief Start CCM operation.
+//!
+//! The \c ui32KeyLocation is an enumerated type which specifies the Key Ram
+//! location in which the key is stored.
+//!
+//! \param bEncrypt determines whether to run encryption or not.
+//! \param ui32AuthLength is the length of the authentication field -
+//! 0, 2, 4, 6, 8, 10, 12, 14 or 16 octets.
+//! \param pui32Nonce is a pointer to 13-byte or 12-byte Nonce (Number used once).
+//! \param pui32PlainText is a pointer to the octet string input message.
+//! \param ui32PlainTextLength is the length of the message.
+//! \param pui32Header is the length of the header (Additional Authentication
+//! Data or AAD).
+//! \param ui32HeaderLength is the length of the header in octets.
+//! \param ui32KeyLocation is the location in Key RAM where the key is stored.
+//! This parameter can have any of the following values:
+//! - \ref CRYPTO_KEY_AREA_0
+//! - \ref CRYPTO_KEY_AREA_1
+//! - \ref CRYPTO_KEY_AREA_2
+//! - \ref CRYPTO_KEY_AREA_3
+//! - \ref CRYPTO_KEY_AREA_4
+//! - \ref CRYPTO_KEY_AREA_5
+//! - \ref CRYPTO_KEY_AREA_6
+//! - \ref CRYPTO_KEY_AREA_7
+//! \param ui32FieldLength is the size of the length field (2 or 3).
+//! \param bIntEnable enables interrupts.
+//!
+//! \return Returns the status of the CCM operation
+//! - \ref AES_SUCCESS
+//! - \ref AES_KEYSTORE_READ_ERROR
+//! - \ref AES_DMA_BUS_ERROR
+//!
+//! \sa \ref CRYPTOCcmAuthEncryptStatus()
+//
+//*****************************************************************************
+extern uint32_t CRYPTOCcmAuthEncrypt(bool bEncrypt, uint32_t ui32AuthLength,
+ uint32_t *pui32Nonce,
+ uint32_t *pui32PlainText,
+ uint32_t ui32PlainTextLength,
+ uint32_t *pui32Header,
+ uint32_t ui32HeaderLength,
+ uint32_t ui32KeyLocation,
+ uint32_t ui32FieldLength,
+ bool bIntEnable);
+
+//*****************************************************************************
+//
+//! \brief Check the result of an AES CCM operation.
+//!
+//! This function should be called after \ref CRYPTOCcmAuthEncrypt() function to check
+//! if the AES CCM operation was successful.
+//!
+//! \return Returns the status of the AES CCM operation:
+//! - \ref AES_SUCCESS : Successful.
+//! - \ref AES_DMA_BUS_ERROR : Failed.
+//! - \ref AES_DMA_BSY : Operation is ongoing.
+//!
+//! \sa \ref CRYPTOCcmAuthEncrypt()
+//
+//*****************************************************************************
+extern uint32_t CRYPTOCcmAuthEncryptStatus(void);
+
+//*****************************************************************************
+//
+//! \brief Get the result of an AES CCM operation.
+//!
+//! This function should be called after \ref CRYPTOCcmAuthEncryptStatus().
+//!
+//! \param ui32TagLength is length of the Tag.
+//! \param pui32CcmTag is the location of the authentication Tag.
+//!
+//! \return Returns \ref AES_SUCCESS if successful.
+//!
+//! \sa \ref CRYPTOCcmAuthEncryptStatus()
+//
+//*****************************************************************************
+extern uint32_t CRYPTOCcmAuthEncryptResultGet(uint32_t ui32TagLength,
+ uint32_t *pui32CcmTag);
+
+//*****************************************************************************
+//
+//! \brief Start a CCM Decryption and Inverse Authentication operation.
+//!
+//! The \c ui32KeyLocation is an enumerated type which specifies the Key Ram
+//! location in which the key is stored.
+//!
+//! \param bDecrypt determines whether to run decryption or not.
+//! \param ui32AuthLength is the length of the authentication field -
+//! 0, 2, 4, 6, 8, 10, 12, 14 or 16 octets.
+//! \param pui32Nonce is a pointer to 13-byte or 12-byte Nonce (Number used once).
+//! \param pui32CipherText is a pointer to the octet string encrypted message.
+//! \param ui32CipherTextLength is the length of the encrypted message.
+//! \param pui32Header is the length of the header (Additional Authentication
+//! Data or AAD).
+//! \param ui32HeaderLength is the length of the header in octets.
+//! \param ui32KeyLocation is the location in Key RAM where the key is stored.
+//! This parameter can have any of the following values:
+//! - \ref CRYPTO_KEY_AREA_0
+//! - \ref CRYPTO_KEY_AREA_1
+//! - \ref CRYPTO_KEY_AREA_2
+//! - \ref CRYPTO_KEY_AREA_3
+//! - \ref CRYPTO_KEY_AREA_4
+//! - \ref CRYPTO_KEY_AREA_5
+//! - \ref CRYPTO_KEY_AREA_6
+//! - \ref CRYPTO_KEY_AREA_7
+//! \param ui32FieldLength is the size of the length field (2 or 3).
+//! \param bIntEnable enables interrupts.
+//!
+//! \return Returns the status of the operation:
+//! - \ref AES_SUCCESS
+//! - \ref AES_KEYSTORE_READ_ERROR
+//! - \ref AES_DMA_BUS_ERROR
+//
+//*****************************************************************************
+extern uint32_t CRYPTOCcmInvAuthDecrypt(bool bDecrypt, uint32_t ui32AuthLength,
+ uint32_t *pui32Nonce,
+ uint32_t *pui32CipherText,
+ uint32_t ui32CipherTextLength,
+ uint32_t *pui32Header,
+ uint32_t ui32HeaderLength,
+ uint32_t ui32KeyLocation,
+ uint32_t ui32FieldLength,
+ bool bIntEnable);
+
+//*****************************************************************************
+//
+//! \brief Checks CCM decrypt and Inverse Authentication result.
+//!
+//! \return Returns status of operation:
+//! - \ref AES_SUCCESS : Operation was successful.
+//! - \ref AES_DMA_BSY : Operation is busy.
+//! - \ref AES_DMA_BUS_ERROR : An error is encountered.
+//
+//*****************************************************************************
+extern uint32_t CRYPTOCcmInvAuthDecryptStatus(void);
+
+//*****************************************************************************
+//
+//! \brief Get the result of the CCM operation.
+//!
+//! \param ui32AuthLength is the length of the authentication field -
+//! 0, 2, 4, 6, 8, 10, 12, 14 or 16 octets.
+//! \param pui32CipherText is a pointer to the octet string encrypted message.
+//! \param ui32CipherTextLength is the length of the encrypted message.
+//! \param pui32CcmTag is the location of the authentication Tag.
+//!
+//! \return Returns AES_SUCCESS if successful.
+//
+//*****************************************************************************
+extern uint32_t CRYPTOCcmInvAuthDecryptResultGet(uint32_t ui32AuthLength,
+ uint32_t *pui32CipherText,
+ uint32_t ui32CipherTextLength,
+ uint32_t *pui32CcmTag);
+
+//*****************************************************************************
+//
+//! \brief Get the current status of the Crypto DMA controller.
+//!
+//! This function is used to poll the Crypto DMA controller to check if it is
+//! ready for a new operation or if an error has occurred.
+//!
+//! The \ref CRYPTO_DMA_BUS_ERROR can also be caught using the crypto event
+//! handler.
+//!
+//! \return Returns the current status of the DMA controller:
+//! - \ref CRYPTO_DMA_READY : DMA ready for a new operation
+//! - \ref CRYPTO_DMA_BSY : DMA is busy
+//! - \ref CRYPTO_DMA_BUS_ERROR : DMA Bus error
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+CRYPTODmaStatus(void)
+{
+ // Return the value of the status register.
+ return (HWREG(CRYPTO_BASE + CRYPTO_O_DMASTAT));
+}
+
+//*****************************************************************************
+//
+//! \brief Enable Crypto DMA operation.
+//!
+//! The specified Crypto DMA channels are enabled.
+//!
+//! \param ui32Channels is a bitwise OR of the channels to enable.
+//! - \ref CRYPTO_DMA_CHAN0
+//! - \ref CRYPTO_DMA_CHAN1
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void CRYPTODmaEnable(uint32_t ui32Channels);
+
+//*****************************************************************************
+//
+//! \brief Disable Crypto DMA operation.
+//!
+//! The specified Crypto DMA channels are disabled.
+//!
+//! \param ui32Channels is a bitwise OR of the channels to disable.
+//! - \ref CRYPTO_DMA_CHAN0
+//! - \ref CRYPTO_DMA_CHAN1
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void CRYPTODmaDisable(uint32_t ui32Channels);
+
+//*****************************************************************************
+//
+//! \brief Enables individual Crypto interrupt sources.
+//!
+//! This function enables the indicated Crypto interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt.
+//! Disabled sources have no effect on the processor.
+//!
+//! \param ui32IntFlags is the bitwise OR of the interrupt sources to be enabled.
+//! - \ref CRYPTO_DMA_IN_DONE
+//! - \ref CRYPTO_RESULT_RDY
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+CRYPTOIntEnable(uint32_t ui32IntFlags)
+{
+ // Check the arguments.
+ ASSERT((ui32IntFlags & CRYPTO_DMA_IN_DONE) |
+ (ui32IntFlags & CRYPTO_RESULT_RDY));
+
+ // Using level interrupt.
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL;
+
+ // Enable the specified interrupts.
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) |= ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! \brief Disables individual CRYPTO interrupt sources.
+//!
+//! This function disables the indicated Crypto interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt.
+//! Disabled sources have no effect on the processor.
+//!
+//! \param ui32IntFlags is the bitwise OR of the interrupt sources to be enabled.
+//! - \ref CRYPTO_DMA_IN_DONE
+//! - \ref CRYPTO_RESULT_RDY
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+CRYPTOIntDisable(uint32_t ui32IntFlags)
+{
+ // Check the arguments.
+ ASSERT((ui32IntFlags & CRYPTO_DMA_IN_DONE) |
+ (ui32IntFlags & CRYPTO_RESULT_RDY));
+
+ // Disable the specified interrupts.
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! \brief Gets the current interrupt status.
+//!
+//! This function returns the interrupt status for the specified Crypto. Either
+//! the raw interrupt status or the status of interrupts that are allowed to
+//! reflect to the processor can be returned.
+//!
+//! \param bMasked whether to use raw or masked interrupt status:
+//! - \c false : Raw interrupt status is required.
+//! - \c true : Masked interrupt status is required.
+//!
+//! \return Returns the current interrupt status:
+//! - \ref CRYPTO_DMA_IN_DONE
+//! - \ref CRYPTO_RESULT_RDY
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+CRYPTOIntStatus(bool bMasked)
+{
+ uint32_t ui32Mask;
+
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ if(bMasked)
+ {
+ ui32Mask = HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN);
+ return(ui32Mask & HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT));
+ }
+ else
+ {
+ return(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & 0x00000003);
+ }
+}
+
+//*****************************************************************************
+//
+//! \brief Clears Crypto interrupt sources.
+//!
+//! The specified Crypto interrupt sources are cleared, so that they no longer
+//! assert. This function must be called in the interrupt handler to keep the
+//! interrupt from being recognized again immediately upon exit.
+//!
+//! \note Due to write buffers and synchronizers in the system it may take several
+//! clock cycles from a register write clearing an event in a module and until the
+//! event is actually cleared in the NVIC of the system CPU. It is recommended to
+//! clear the event source early in the interrupt service routine (ISR) to allow
+//! the event clear to propagate to the NVIC before returning from the ISR.
+//! At the same time, an early event clear allows new events of the same type to be
+//! pended instead of ignored if the event is cleared later in the ISR.
+//! It is the responsibility of the programmer to make sure that enough time has passed
+//! before returning from the ISR to avoid false re-triggering of the cleared event.
+//! A simple, although not necessarily optimal, way of clearing an event before
+//! returning from the ISR is:
+//! -# Write to clear event (interrupt source). (buffered write)
+//! -# Dummy read from the event source module. (making sure the write has propagated)
+//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers)
+//!
+//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared.
+//! - \ref CRYPTO_DMA_IN_DONE
+//! - \ref CRYPTO_RESULT_RDY
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+CRYPTOIntClear(uint32_t ui32IntFlags)
+{
+ // Check the arguments.
+ ASSERT((ui32IntFlags & CRYPTO_DMA_IN_DONE) |
+ (ui32IntFlags & CRYPTO_RESULT_RDY));
+
+ // Clear the requested interrupt sources,
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! \brief Registers an interrupt handler for a Crypto interrupt in the dynamic interrupt table.
+//!
+//! \note Only use this function if you want to use the dynamic vector table (in SRAM)!
+//!
+//! This function registers a function as the interrupt handler for a specific
+//! interrupt and enables the corresponding interrupt in the interrupt controller.
+//!
+//! Specific UART interrupts must be enabled via \ref CRYPTOIntEnable(). It is the
+//! interrupt handler's responsibility to clear the interrupt source.
+//!
+//! \param pfnHandler is a pointer to the function to be called when the
+//! UART interrupt occurs.
+//!
+//! \return None
+//!
+//! \sa \ref IntRegister() for important information about registering interrupt
+//! handlers.
+//
+//*****************************************************************************
+__STATIC_INLINE void
+CRYPTOIntRegister(void (*pfnHandler)(void))
+{
+ // Register the interrupt handler.
+ IntRegister(INT_CRYPTO_RESULT_AVAIL_IRQ, pfnHandler);
+
+ // Enable the UART interrupt.
+ IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ);
+}
+
+//*****************************************************************************
+//
+//! \brief Unregisters an interrupt handler for a Crypto interrupt in the dynamic interrupt table.
+//!
+//! This function does the actual unregistering of the interrupt handler. It
+//! clears the handler to be called when a Crypto interrupt occurs. This
+//! function also masks off the interrupt in the interrupt controller so that
+//! the interrupt handler no longer is called.
+//!
+//! \return None
+//!
+//! \sa \ref IntRegister() for important information about registering interrupt
+//! handlers.
+//
+//*****************************************************************************
+__STATIC_INLINE void
+CRYPTOIntUnregister(void)
+{
+ // Disable the interrupt.
+ IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ);
+
+ // Unregister the interrupt handler.
+ IntUnregister(INT_CRYPTO_RESULT_AVAIL_IRQ);
+}
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// Redirect to implementation in ROM when available.
+//
+//*****************************************************************************
+#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
+ #include "../driverlib/rom.h"
+ #ifdef ROM_CRYPTOAesLoadKey
+ #undef CRYPTOAesLoadKey
+ #define CRYPTOAesLoadKey ROM_CRYPTOAesLoadKey
+ #endif
+ #ifdef ROM_CRYPTOAesCbc
+ #undef CRYPTOAesCbc
+ #define CRYPTOAesCbc ROM_CRYPTOAesCbc
+ #endif
+ #ifdef ROM_CRYPTOAesCbcStatus
+ #undef CRYPTOAesCbcStatus
+ #define CRYPTOAesCbcStatus ROM_CRYPTOAesCbcStatus
+ #endif
+ #ifdef ROM_CRYPTOAesEcb
+ #undef CRYPTOAesEcb
+ #define CRYPTOAesEcb ROM_CRYPTOAesEcb
+ #endif
+ #ifdef ROM_CRYPTOAesEcbStatus
+ #undef CRYPTOAesEcbStatus
+ #define CRYPTOAesEcbStatus ROM_CRYPTOAesEcbStatus
+ #endif
+ #ifdef ROM_CRYPTOCcmAuthEncrypt
+ #undef CRYPTOCcmAuthEncrypt
+ #define CRYPTOCcmAuthEncrypt ROM_CRYPTOCcmAuthEncrypt
+ #endif
+ #ifdef ROM_CRYPTOCcmAuthEncryptStatus
+ #undef CRYPTOCcmAuthEncryptStatus
+ #define CRYPTOCcmAuthEncryptStatus ROM_CRYPTOCcmAuthEncryptStatus
+ #endif
+ #ifdef ROM_CRYPTOCcmAuthEncryptResultGet
+ #undef CRYPTOCcmAuthEncryptResultGet
+ #define CRYPTOCcmAuthEncryptResultGet ROM_CRYPTOCcmAuthEncryptResultGet
+ #endif
+ #ifdef ROM_CRYPTOCcmInvAuthDecrypt
+ #undef CRYPTOCcmInvAuthDecrypt
+ #define CRYPTOCcmInvAuthDecrypt ROM_CRYPTOCcmInvAuthDecrypt
+ #endif
+ #ifdef ROM_CRYPTOCcmInvAuthDecryptStatus
+ #undef CRYPTOCcmInvAuthDecryptStatus
+ #define CRYPTOCcmInvAuthDecryptStatus ROM_CRYPTOCcmInvAuthDecryptStatus
+ #endif
+ #ifdef ROM_CRYPTOCcmInvAuthDecryptResultGet
+ #undef CRYPTOCcmInvAuthDecryptResultGet
+ #define CRYPTOCcmInvAuthDecryptResultGet ROM_CRYPTOCcmInvAuthDecryptResultGet
+ #endif
+ #ifdef ROM_CRYPTODmaEnable
+ #undef CRYPTODmaEnable
+ #define CRYPTODmaEnable ROM_CRYPTODmaEnable
+ #endif
+ #ifdef ROM_CRYPTODmaDisable
+ #undef CRYPTODmaDisable
+ #define CRYPTODmaDisable ROM_CRYPTODmaDisable
+ #endif
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __CRYPTO_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ddi.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ddi.c
new file mode 100644
index 0000000..35cf60f
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ddi.c
@@ -0,0 +1,214 @@
+/******************************************************************************
+* Filename: ddi.c
+* Revised: 2018-06-04 16:10:13 +0200 (Mon, 04 Jun 2018)
+* Revision: 52111
+*
+* Description: Driver for the DDI master interface
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "ddi.h"
+
+//*****************************************************************************
+//
+// Handle support for DriverLib in ROM:
+// This section will undo prototype renaming made in the header file
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #undef DDI32RegWrite
+ #define DDI32RegWrite NOROM_DDI32RegWrite
+ #undef DDI16BitWrite
+ #define DDI16BitWrite NOROM_DDI16BitWrite
+ #undef DDI16BitfieldWrite
+ #define DDI16BitfieldWrite NOROM_DDI16BitfieldWrite
+ #undef DDI16BitRead
+ #define DDI16BitRead NOROM_DDI16BitRead
+ #undef DDI16BitfieldRead
+ #define DDI16BitfieldRead NOROM_DDI16BitfieldRead
+#endif
+
+//*****************************************************************************
+//
+// Write a 32 bit value to a register in the DDI slave.
+//
+//*****************************************************************************
+void
+DDI32RegWrite(uint32_t ui32Base, uint32_t ui32Reg,
+ uint32_t ui32Val)
+{
+ // Check the arguments.
+ ASSERT(DDIBaseValid(ui32Base));
+ ASSERT(ui32Reg < DDI_SLAVE_REGS);
+
+ // Write the value to the register.
+ HWREG(ui32Base + ui32Reg) = ui32Val;
+}
+
+//*****************************************************************************
+//
+// Write a single bit using a 16-bit maskable write
+//
+//*****************************************************************************
+void
+DDI16BitWrite(uint32_t ui32Base, uint32_t ui32Reg,
+ uint32_t ui32Mask, uint32_t ui32WrData)
+{
+ uint32_t ui32RegAddr;
+ uint32_t ui32Data;
+
+ // Check the arguments.
+ ASSERT(DDIBaseValid(ui32Base));
+ ASSERT(!((ui32Mask & 0xFFFF0000) ^ (ui32Mask & 0x0000FFFF)));
+ ASSERT(!(ui32WrData & 0xFFFF0000));
+
+ // DDI 16-bit target is on 32-bit boundary so double offset
+ ui32RegAddr = ui32Base + (ui32Reg << 1) + DDI_O_MASK16B;
+
+ // Adjust for target bit in high half of the word.
+ if(ui32Mask & 0xFFFF0000)
+ {
+ ui32RegAddr += 4;
+ ui32Mask >>= 16;
+ }
+
+ // Write mask if data is not zero (to set mask bit), else write '0'.
+ ui32Data = ui32WrData ? ui32Mask : 0x0;
+
+ // Update the register.
+ HWREG(ui32RegAddr) = (ui32Mask << 16) | ui32Data;
+}
+
+//*****************************************************************************
+//
+// Write a bit field via the DDI using 16-bit maskable write
+//
+//*****************************************************************************
+void
+DDI16BitfieldWrite(uint32_t ui32Base, uint32_t ui32Reg,
+ uint32_t ui32Mask, uint32_t ui32Shift,
+ uint16_t ui32Data)
+{
+ uint32_t ui32RegAddr;
+ uint32_t ui32WrData;
+
+ // Check the arguments.
+ ASSERT(DDIBaseValid(ui32Base));
+
+ // 16-bit target is on 32-bit boundary so double offset.
+ ui32RegAddr = ui32Base + (ui32Reg << 1) + DDI_O_MASK16B;
+
+ // Adjust for target bit in high half of the word.
+ if(ui32Shift >= 16)
+ {
+ ui32Shift = ui32Shift - 16;
+ ui32RegAddr += 4;
+ ui32Mask = ui32Mask >> 16;
+ }
+
+ // Shift data in to position.
+ ui32WrData = ui32Data << ui32Shift;
+
+ // Write data.
+ HWREG(ui32RegAddr) = (ui32Mask << 16) | ui32WrData;
+}
+
+//*****************************************************************************
+//
+// Read a bit via the DDI using 16-bit READ.
+//
+//*****************************************************************************
+uint16_t
+DDI16BitRead(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask)
+{
+ uint32_t ui32RegAddr;
+ uint16_t ui16Data;
+
+ // Check the arguments.
+ ASSERT(DDIBaseValid(ui32Base));
+
+ // Calculate the address of the register.
+ ui32RegAddr = ui32Base + ui32Reg + DDI_O_DIR;
+
+ // Adjust for target bit in high half of the word.
+ if(ui32Mask & 0xFFFF0000)
+ {
+ ui32RegAddr += 2;
+ ui32Mask = ui32Mask >> 16;
+ }
+
+ // Read a halfword on the DDI interface.
+ ui16Data = HWREGH(ui32RegAddr);
+
+ // Mask data.
+ ui16Data = ui16Data & ui32Mask;
+
+ // Return masked data.
+ return(ui16Data);
+}
+
+//*****************************************************************************
+//
+// Read a bit field via the DDI using 16-bit read.
+//
+//*****************************************************************************
+uint16_t
+DDI16BitfieldRead(uint32_t ui32Base, uint32_t ui32Reg,
+ uint32_t ui32Mask, uint32_t ui32Shift)
+{
+ uint32_t ui32RegAddr;
+ uint16_t ui16Data;
+
+ // Check the arguments.
+ ASSERT(DDIBaseValid(ui32Base));
+
+ // Calculate the register address.
+ ui32RegAddr = ui32Base + ui32Reg + DDI_O_DIR;
+
+ // Adjust for target bit in high half of the word.
+ if(ui32Shift >= 16)
+ {
+ ui32Shift = ui32Shift - 16;
+ ui32RegAddr += 2;
+ ui32Mask = ui32Mask >> 16;
+ }
+
+ // Read the register.
+ ui16Data = HWREGH(ui32RegAddr);
+
+ // Mask data and shift into place.
+ ui16Data &= ui32Mask;
+ ui16Data >>= ui32Shift;
+
+ // Return data.
+ return(ui16Data);
+}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ddi.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ddi.h
new file mode 100644
index 0000000..c4e83e3
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ddi.h
@@ -0,0 +1,462 @@
+/******************************************************************************
+* Filename: ddi.h
+* Revised: 2018-06-04 16:10:13 +0200 (Mon, 04 Jun 2018)
+* Revision: 52111
+*
+* Description: Defines and prototypes for the DDI master interface.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup analog_group
+//! @{
+//! \addtogroup ddi_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __DDI_H__
+#define __DDI_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "../inc/hw_types.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_ddi.h"
+#include "../inc/hw_aux_smph.h"
+#include "debug.h"
+#include "cpu.h"
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// This section renames all functions that are not "static inline", so that
+// calling these functions will default to implementation in flash. At the end
+// of this file a second renaming will change the defaults to implementation in
+// ROM for available functions.
+//
+// To force use of the implementation in flash, e.g. for debugging:
+// - Globally: Define DRIVERLIB_NOROM at project level
+// - Per function: Use prefix "NOROM_" when calling the function
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #define DDI32RegWrite NOROM_DDI32RegWrite
+ #define DDI16BitWrite NOROM_DDI16BitWrite
+ #define DDI16BitfieldWrite NOROM_DDI16BitfieldWrite
+ #define DDI16BitRead NOROM_DDI16BitRead
+ #define DDI16BitfieldRead NOROM_DDI16BitfieldRead
+#endif
+
+//*****************************************************************************
+//
+// Number of register in the DDI slave
+//
+//*****************************************************************************
+#define DDI_SLAVE_REGS 64
+
+
+//*****************************************************************************
+//
+// Defines that is used to control the ADI slave and master
+//
+//*****************************************************************************
+#define DDI_PROTECT 0x00000080
+#define DDI_ACK 0x00000001
+#define DDI_SYNC 0x00000000
+
+//*****************************************************************************
+//
+// API Functions and prototypes
+//
+//*****************************************************************************
+
+
+//*****************************************************************************
+//
+// Helper functions
+//
+//*****************************************************************************
+
+#ifdef DRIVERLIB_DEBUG
+//*****************************************************************************
+//
+//! \internal
+//!
+//! \brief Check a DDI base address.
+//!
+//! This function determines if a DDI port base address is valid.
+//!
+//! \param ui32Base is the base address of the DDI port.
+//!
+//! \return Returns \c true if the base address is valid and \c false
+//! otherwise.
+//!
+//! \endinternal
+//
+//*****************************************************************************
+static bool
+DDIBaseValid(uint32_t ui32Base)
+{
+ return(ui32Base == AUX_DDI0_OSC_BASE);
+}
+#endif
+
+
+//*****************************************************************************
+//
+//! \brief Read the value in a 32 bit register.
+//!
+//! This function will read a register in the analog domain and return
+//! the value as an \c uint32_t.
+//!
+//! \param ui32Base is DDI base address.
+//! \param ui32Reg is the 32 bit register to read.
+//!
+//! \return Returns the 32 bit value of the analog register.
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+DDI32RegRead(uint32_t ui32Base, uint32_t ui32Reg)
+{
+ // Check the arguments.
+ ASSERT(DDIBaseValid(ui32Base));
+ ASSERT(ui32Reg < DDI_SLAVE_REGS);
+
+ // Read the register and return the value.
+ return(HWREG(ui32Base + ui32Reg));
+}
+
+//*****************************************************************************
+//
+//! \brief Set specific bits in a DDI slave register.
+//!
+//! This function will set bits in a register in the analog domain.
+//!
+//! \note This operation is write only for the specified register.
+//! This function is used to set bits in specific register in the
+//! DDI slave. Only bits in the selected register are affected by the
+//! operation.
+//!
+//! \param ui32Base is DDI base address.
+//! \param ui32Reg is the base register to assert the bits in.
+//! \param ui32Val is the 32 bit one-hot encoded value specifying which
+//! bits to set in the register.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+DDI32BitsSet(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val)
+{
+ uint32_t ui32RegOffset;
+
+ // Check the arguments.
+ ASSERT(DDIBaseValid(ui32Base));
+ ASSERT(ui32Reg < DDI_SLAVE_REGS);
+
+ // Get the correct address of the first register used for setting bits
+ // in the DDI slave.
+ ui32RegOffset = DDI_O_SET;
+
+ // Set the selected bits.
+ HWREG(ui32Base + ui32RegOffset + ui32Reg) = ui32Val;
+}
+
+//*****************************************************************************
+//
+//! \brief Clear specific bits in a 32 bit DDI register.
+//!
+//! This function will clear bits in a register in the analog domain.
+//!
+//! \param ui32Base is DDI base address.
+//! \param ui32Reg is the base registers to clear the bits in.
+//! \param ui32Val is the 32 bit one-hot encoded value specifying which
+//! bits to clear in the register.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+DDI32BitsClear(uint32_t ui32Base, uint32_t ui32Reg,
+ uint32_t ui32Val)
+{
+ uint32_t ui32RegOffset;
+
+ // Check the arguments.
+ ASSERT(DDIBaseValid(ui32Base));
+ ASSERT(ui32Reg < DDI_SLAVE_REGS);
+
+ // Get the correct address of the first register used for setting bits
+ // in the DDI slave.
+ ui32RegOffset = DDI_O_CLR;
+
+ // Clear the selected bits.
+ HWREG(ui32Base + ui32RegOffset + ui32Reg) = ui32Val;
+}
+
+//*****************************************************************************
+//
+//! \brief Set a value on any 8 bits inside a 32 bit register in the DDI slave.
+//!
+//! This function allows byte (8 bit access) to the DDI slave registers.
+//!
+//! Use this function to write any value in the range 0-7 bits aligned on a
+//! byte boundary. For example, for writing the value 0b101 to bits 1-3 set
+//! <tt>ui16Val = 0x0A</tt> and <tt>ui16Mask = 0x0E</tt>. Bits 0 and 5-7 will
+//! not be affected by the operation, as long as the corresponding bits are
+//! not set in the \c ui16Mask.
+//!
+//! \param ui32Base is the base address of the DDI port.
+//! \param ui32Reg is the Least Significant Register in the DDI slave that
+//! will be affected by the write operation.
+//! \param ui32Byte is the byte number to access within the 32 bit register.
+//! \param ui16Mask is the mask defining which of the 8 bits that should be
+//! overwritten. The mask must be defined in the lower half of the 16 bits.
+//! \param ui16Val is the value to write. The value must be defined in the lower
+//! half of the 16 bits.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+DDI8SetValBit(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Byte,
+ uint16_t ui16Mask, uint16_t ui16Val)
+{
+ uint32_t ui32RegOffset;
+
+ // Check the arguments.
+ ASSERT(DDIBaseValid(ui32Base));
+ ASSERT(ui32Reg < DDI_SLAVE_REGS);
+ ASSERT(!(ui16Val & 0xFF00));
+ ASSERT(!(ui16Mask & 0xFF00));
+
+ // Get the correct address of the first register used for setting bits
+ // in the DDI slave.
+ ui32RegOffset = DDI_O_MASK8B + (ui32Reg << 1) + (ui32Byte << 1);
+
+ // Set the selected bits.
+ HWREGH(ui32Base + ui32RegOffset) = (ui16Mask << 8) | ui16Val;
+}
+
+//*****************************************************************************
+//
+//! \brief Set a value on any 16 bits inside a 32 bit register aligned on a
+//! half-word boundary in the DDI slave.
+//!
+//! This function allows 16 bit masked access to the DDI slave registers.
+//!
+//! Use this function to write any value in the range 0-15 bits aligned on a
+//! half-word boundary. For example, for writing the value 0b101 to bits 1-3 set
+//! <tt>ui32Val = 0x000A</tt> and <tt>ui32Mask = 0x000E</tt>. Bits 0 and 5-15 will not be
+//! affected by the operation, as long as the corresponding bits are not set
+//! in the \c ui32Mask.
+//!
+//! \param ui32Base is the base address of the DDI port.
+//! \param ui32Reg is register to access.
+//! \param bWriteHigh defines which part of the register to write in.
+//! \param ui32Mask is the mask defining which of the 16 bit that should be
+//! overwritten. The mask must be defined in the lower half of the 32 bits.
+//! \param ui32Val is the value to write. The value must be defined in the lower
+//! half of the 32 bits.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+DDI16SetValBit(uint32_t ui32Base, uint32_t ui32Reg, bool bWriteHigh,
+ uint32_t ui32Mask, uint32_t ui32Val)
+{
+ uint32_t ui32RegOffset;
+
+ // Check the arguments.
+ ASSERT(DDIBaseValid(ui32Base));
+ ASSERT(ui32Reg < DDI_SLAVE_REGS);
+ ASSERT(!(ui32Val & 0xFFFF0000));
+ ASSERT(!(ui32Mask & 0xFFFF0000));
+
+ // Get the correct address of the first register used for setting bits
+ // in the DDI slave.
+ ui32RegOffset = DDI_O_MASK16B + (ui32Reg << 1) + (bWriteHigh ? 4 : 0);
+
+ // Set the selected bits.
+ HWREG(ui32Base + ui32RegOffset) = (ui32Mask << 16) | ui32Val;
+}
+
+//*****************************************************************************
+//
+//! \brief Write a 32 bit value to a register in the DDI slave.
+//!
+//! This function will write a value to a register in the analog
+//! domain.
+//!
+//! \note This operation is write only for the specified register. No
+//! conservation of the previous value of the register will be kept (i.e. this
+//! is NOT read-modify-write on the register).
+//!
+//! \param ui32Base is DDI base address.
+//! \param ui32Reg is the register to write.
+//! \param ui32Val is the 32 bit value to write to the register.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void DDI32RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val);
+
+//*****************************************************************************
+//
+//! \brief Write a single bit using a 16-bit maskable write.
+//!
+//! A '1' is written to the bit if \c ui32WrData is non-zero, else a '0' is written.
+//!
+//! \param ui32Base is the base address of the DDI port.
+//! \param ui32Reg is register to access.
+//! \param ui32Mask is the mask defining which of the 16 bit that should be overwritten.
+//! \param ui32WrData is the value to write. The value must be defined in the lower half of the 32 bits.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void DDI16BitWrite(uint32_t ui32Base, uint32_t ui32Reg,
+ uint32_t ui32Mask, uint32_t ui32WrData);
+
+
+//*****************************************************************************
+//
+//! \brief Write a bit field via the DDI using 16-bit maskable write.
+//!
+//! Requires that entire bit field is within the half word boundary.
+//!
+//! \param ui32Base is the base address of the DDI port.
+//! \param ui32Reg is register to access.
+//! \param ui32Mask is the mask defining which of the 16 bits that should be overwritten.
+//! \param ui32Shift is the shift value for the bit field.
+//! \param ui32Data is the data aligned to bit 0.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void DDI16BitfieldWrite(uint32_t ui32Base, uint32_t ui32Reg,
+ uint32_t ui32Mask, uint32_t ui32Shift,
+ uint16_t ui32Data);
+
+//*****************************************************************************
+//
+//! \brief Read a bit via the DDI using 16-bit read.
+//!
+//! \param ui32Base is the base address of the DDI module.
+//! \param ui32Reg is the register to read.
+//! \param ui32Mask defines the bit which should be read.
+//!
+//! \return Returns a zero if bit selected by mask is '0'. Else returns the mask.
+//
+//*****************************************************************************
+extern uint16_t DDI16BitRead(uint32_t ui32Base, uint32_t ui32Reg,
+ uint32_t ui32Mask);
+
+//*****************************************************************************
+//
+//! \brief Read a bit field via the DDI using 16-bit read.
+//!
+//! Requires that entire bit field is within the half word boundary.
+//!
+//! \param ui32Base is the base address of the DDI port.
+//! \param ui32Reg is register to access.
+//! \param ui32Mask is the mask defining which of the 16 bits that should be overwritten.
+//! \param ui32Shift defines the required shift of the data to align with bit 0.
+//!
+//! \return Returns data aligned to bit 0.
+//
+//*****************************************************************************
+extern uint16_t DDI16BitfieldRead(uint32_t ui32Base, uint32_t ui32Reg,
+ uint32_t ui32Mask, uint32_t ui32Shift);
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// Redirect to implementation in ROM when available.
+//
+//*****************************************************************************
+#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
+ #include "../driverlib/rom.h"
+ #ifdef ROM_DDI32RegWrite
+ #undef DDI32RegWrite
+ #define DDI32RegWrite ROM_DDI32RegWrite
+ #endif
+ #ifdef ROM_DDI16BitWrite
+ #undef DDI16BitWrite
+ #define DDI16BitWrite ROM_DDI16BitWrite
+ #endif
+ #ifdef ROM_DDI16BitfieldWrite
+ #undef DDI16BitfieldWrite
+ #define DDI16BitfieldWrite ROM_DDI16BitfieldWrite
+ #endif
+ #ifdef ROM_DDI16BitRead
+ #undef DDI16BitRead
+ #define DDI16BitRead ROM_DDI16BitRead
+ #endif
+ #ifdef ROM_DDI16BitfieldRead
+ #undef DDI16BitfieldRead
+ #define DDI16BitfieldRead ROM_DDI16BitfieldRead
+ #endif
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DDI_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ddi_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ddi_doc.h
new file mode 100644
index 0000000..063c156
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ddi_doc.h
@@ -0,0 +1,67 @@
+/******************************************************************************
+* Filename: ddi_doc.h
+* Revised: 2016-08-30 14:34:13 +0200 (Tue, 30 Aug 2016)
+* Revision: 47080
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+//! \addtogroup ddi_api
+//! @{
+//! \section sec_ddi Introduction
+//! \n
+//!
+//! \section sec_ddi_api API
+//!
+//! The API functions can be grouped like this:
+//!
+//! Write:
+//! - Direct (all bits):
+//! - \ref DDI32RegWrite()
+//! - Set individual bits:
+//! - \ref DDI32BitsSet()
+//! - Clear individual bits:
+//! - \ref DDI32BitsClear()
+//! - Masked:
+//! - \ref DDI8SetValBit()
+//! - \ref DDI16SetValBit()
+//! - Special functions using masked write:
+//! - \ref DDI16BitWrite()
+//! - \ref DDI16BitfieldWrite()
+//!
+//! Read:
+//! - Direct (all bits):
+//! - \ref DDI32RegRead()
+//! - Special functions using masked read:
+//! - \ref DDI16BitRead()
+//! - \ref DDI16BitfieldRead()
+//!
+//!
+//! @}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/debug.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/debug.c
new file mode 100644
index 0000000..d27d623
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/debug.c
@@ -0,0 +1,57 @@
+/******************************************************************************
+* Filename: debug.c
+* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017)
+* Revision: 48852
+*
+* Description: Driver for the Debug functionality (NB. This is a stub which
+* should never be included in a release).
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "../inc/hw_types.h"
+#include "debug.h"
+
+//*****************************************************************************
+//
+// Function stub for allowing compile with DRIVERLIB_DEBUG flag asserted.
+//
+//*****************************************************************************
+void
+__error__(char *pcFilename, uint32_t ui32Line)
+{
+ // Error catching.
+ // User can implement custom error handling for failing ASSERTs.
+ // Setting breakpoint here allows tracing of the failing ASSERT.
+ while( true );
+}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/debug.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/debug.h
new file mode 100644
index 0000000..0cd8a6a
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/debug.h
@@ -0,0 +1,84 @@
+/******************************************************************************
+* Filename: debug.h
+* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017)
+* Revision: 48852
+*
+* Description: Macros for assisting debug of the driver library.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup system_control_group
+//! @{
+//! \addtogroup debug_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __DEBUG_H__
+#define __DEBUG_H__
+
+//*****************************************************************************
+//
+//! Function stub for allowing compile with DRIVERLIB_DEBUG flag asserted.
+//
+//*****************************************************************************
+extern void __error__(char *pcFilename, uint32_t ui32Line);
+
+//*****************************************************************************
+//
+// The ASSERT macro, which does the actual assertion checking. Typically, this
+// will be for procedure arguments.
+//
+//*****************************************************************************
+#ifdef DRIVERLIB_DEBUG
+#define ASSERT(expr) { \
+ if(!(expr)) \
+ { \
+ __error__(__FILE__, __LINE__); \
+ } \
+ }
+
+#else
+#define ASSERT(expr)
+#endif
+
+#endif // __DEBUG_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/driverlib_release.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/driverlib_release.c
new file mode 100644
index 0000000..cdb08e3
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/driverlib_release.c
@@ -0,0 +1,45 @@
+/******************************************************************************
+* Filename: driverlib_release.c
+* Revised: $Date: 2016-09-13 14:21:40 +0200 (Tue, 13 Sep 2016) $
+* Revision: $Revision: 47152 $
+*
+* Description: Provides macros for ensuring that a specfic release of
+* DriverLib is used.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+#include "../driverlib/driverlib_release.h"
+
+
+
+
+/// Declare the current DriverLib release
+DRIVERLIB_DECLARE_RELEASE(0, 54539);
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/driverlib_release.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/driverlib_release.h
new file mode 100644
index 0000000..497f8b0
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/driverlib_release.h
@@ -0,0 +1,156 @@
+/******************************************************************************
+* Filename: driverlib_release.h
+* Revised: $Date: 2015-07-16 12:12:04 +0200 (Thu, 16 Jul 2015) $
+* Revision: $Revision: 44151 $
+*
+* Description: Provides macros for ensuring that a specfic release of
+* DriverLib is used.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup system_control_group
+//! @{
+//! \addtogroup driverlib_release_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_RELEASE_H__
+#define __DRIVERLIB_RELEASE_H__
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+
+
+
+
+/// DriverLib release group number
+#define DRIVERLIB_RELEASE_GROUP 0
+/// DriverLib release build number
+#define DRIVERLIB_RELEASE_BUILD 54539
+
+
+
+
+//*****************************************************************************
+//
+//! This macro is called internally from within DriverLib to declare the
+//! DriverLib release locking object:
+//! \param group is the DriverLib release group number.
+//! \param build is the DriverLib release build number.
+//!
+//! This macro shall not be called in the application unless the intention is
+//! to bypass the release locking (at own risk).
+//
+//*****************************************************************************
+#define DRIVERLIB_DECLARE_RELEASE(group, build) \
+ const volatile uint8_t driverlib_release_##group##_##build
+
+/// External declaration of the DriverLib release locking object
+extern DRIVERLIB_DECLARE_RELEASE(0, 54539);
+
+
+
+
+//*****************************************************************************
+//
+//! This macro shall be called once from within a function of a precompiled
+//! software deliverable to lock the deliverable to a specific DriverLib
+//! release. It is essential that the call is made from code that is not
+//! optimized away.
+//!
+//! This macro locks to a specific DriverLib release:
+//! \param group is the DriverLib release group number.
+//! \param build is the DriverLib release build number.
+//!
+//! If attempting to use the precompiled deliverable with a different release
+//! of DriverLib, a linker error will be produced, stating that
+//! "driverlib_release_xx_yyyyy is undefined" or similar.
+//!
+//! To override the check, for example when upgrading DriverLib but not the
+//! precompiled deliverables, or when mixing precompiled deliverables,
+//! application developers may (at own risk) declare the missing DriverLib
+//! release using the \ref DRIVERLIB_DECLARE_RELEASE() macro.
+//
+//*****************************************************************************
+#define DRIVERLIB_ASSERT_RELEASE(group, build) \
+ (driverlib_release_##group##_##build)
+
+
+
+
+//*****************************************************************************
+//
+//! This macro shall be called once from within a function of a precompiled
+//! software deliverable to lock the deliverable to a specific DriverLib
+//! release. It is essential that the call is made from code that is not
+//! optimized away.
+//!
+//! This macro locks to the current DriverLib release used at compile-time.
+//!
+//! If attempting to use the precompiled deliverable with a different release
+//! of DriverLib, a linker error will be produced, stating that
+//! "driverlib_release_xx_yyyyy is undefined" or similar.
+//!
+//! To override the check, for example when upgrading DriverLib but not the
+//! precompiled deliverables, or when mixing precompiled deliverables,
+//! application developers may (at own risk) declare the missing DriverLib
+//! release using the \ref DRIVERLIB_DECLARE_RELEASE() macro.
+//
+//*****************************************************************************
+#define DRIVERLIB_ASSERT_CURR_RELEASE() \
+ DRIVERLIB_ASSERT_RELEASE(0, 54539)
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_RELEASE_H__
+
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/event.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/event.c
new file mode 100644
index 0000000..a5cf55f
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/event.c
@@ -0,0 +1,41 @@
+/******************************************************************************
+* Filename: event.c
+* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016)
+* Revision: 47179
+*
+* Description: Driver for the Event Fabric.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "event.h"
+
+// See event.h for implementation
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/event.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/event.h
new file mode 100644
index 0000000..2df3e20
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/event.h
@@ -0,0 +1,267 @@
+/******************************************************************************
+* Filename: event.h
+* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016)
+* Revision: 47179
+*
+* Description: Defines and prototypes for the Event Handler.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup peripheral_group
+//! @{
+//! \addtogroup event_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __EVENT_H__
+#define __EVENT_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "../inc/hw_types.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_event.h"
+#include "debug.h"
+
+
+//*****************************************************************************
+//
+// API Functions and prototypes
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \brief Connects an event to an event subscriber via Event Fabric.
+//!
+//! This function connects event sources to event subscribers.
+//!
+//! It is not possible to read event status in this module (except software events).
+//! Event status must be read in the module that contains the event source. How a
+//! specific event subscriber reacts to an event is configured and documented in
+//! the respective modules.
+//!
+//! For a full list of configurable and constant mapped event sources to event
+//! subscribers see the register descriptions for
+//! <a href="../register_descriptions/CPU_MMAP/EVENT.html" target="_blank">Event Fabric</a>.
+//!
+//! Defines for event subscriber argument (\c ui32EventSubscriber) have the format:
+//! - \ti_code{EVENT_O_[subscriber_name]}
+//!
+//! Defines for event source argument (\c ui32EventSource) must have the
+//! following format where valid \c event_enum values are found in the
+//! register description :
+//! - \ti_code{EVENT_[subscriber_name]_EV_[event_enum]}
+//!
+//! Examples of valid defines for \c ui32EventSource:
+//! - EVENT_CPUIRQSEL30_EV_AUX_TDC_DONE
+//! - EVENT_RFCSEL9_EV_AUX_COMPA
+//! - EVENT_GPT0ACAPTSEL_EV_AON_RTC_UPD
+//!
+//! \note Each event subscriber can only receive a sub-set of the event sources!
+//!
+//! \note Switching the event source is not glitch free, so it is imperative
+//! that the subscriber is disabled for interrupts when switching the event
+//! source. The behavior is undefined if not disabled.
+//!
+//! \param ui32EventSubscriber is the \b configurable event subscriber to receive the event.
+//! Click the event subscriber to see the list of valid event sources in the
+//! register description.
+//! - EVENT_O_CPUIRQSEL30 : System CPU interrupt 30
+//! - EVENT_O_RFCSEL9 : RF Core event 9
+//! - EVENT_O_GPT0ACAPTSEL : GPT 0A capture event
+//! - EVENT_O_GPT0BCAPTSEL : GPT 0B capture event
+//! - EVENT_O_GPT1ACAPTSEL : GPT 1A capture event
+//! - EVENT_O_GPT1BCAPTSEL : GPT 1B capture event
+//! - EVENT_O_GPT2ACAPTSEL : GPT 2A capture event
+//! - EVENT_O_GPT2BCAPTSEL : GPT 2B capture event
+//! - EVENT_O_GPT3ACAPTSEL : GPT 3A capture event
+//! - EVENT_O_GPT3BCAPTSEL : GPT 3B capture event
+//! - EVENT_O_UDMACH9SSEL : uDMA channel 9 single request
+//! - EVENT_O_UDMACH9BSEL : uDMA channel 9 burst request
+//! - EVENT_O_UDMACH10SSEL : uDMA channel 10 single request
+//! - EVENT_O_UDMACH10BSEL : uDMA channel 10 burst request
+//! - EVENT_O_UDMACH11SSEL : uDMA channel 11 single request
+//! - EVENT_O_UDMACH11BSEL : uDMA channel 11 burst request
+//! - EVENT_O_UDMACH12SSEL : uDMA channel 12 single request
+//! - EVENT_O_UDMACH12BSEL : uDMA channel 12 burst request
+//! - EVENT_O_UDMACH14BSEL : uDMA channel 14 single request
+//! - EVENT_O_AUXSEL0 : AUX
+//! - EVENT_O_I2SSTMPSEL0 : I2S
+//! - EVENT_O_FRZSEL0 : Freeze modules (some modules can freeze on CPU Halt)
+//! \param ui32EventSource is the specific event that must be acted upon.
+//! - Format: \ti_code{EVENT_[subscriber_name]_EV_[event_enum]} (see explanation above)
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+EventRegister(uint32_t ui32EventSubscriber, uint32_t ui32EventSource)
+{
+ // Check the arguments.
+ ASSERT(( ui32EventSubscriber == EVENT_O_CPUIRQSEL30 ) ||
+ ( ui32EventSubscriber == EVENT_O_RFCSEL9 ) ||
+ ( ui32EventSubscriber == EVENT_O_GPT0ACAPTSEL ) ||
+ ( ui32EventSubscriber == EVENT_O_GPT0BCAPTSEL ) ||
+ ( ui32EventSubscriber == EVENT_O_GPT1ACAPTSEL ) ||
+ ( ui32EventSubscriber == EVENT_O_GPT1BCAPTSEL ) ||
+ ( ui32EventSubscriber == EVENT_O_GPT2ACAPTSEL ) ||
+ ( ui32EventSubscriber == EVENT_O_GPT2BCAPTSEL ) ||
+ ( ui32EventSubscriber == EVENT_O_GPT3ACAPTSEL ) ||
+ ( ui32EventSubscriber == EVENT_O_GPT3BCAPTSEL ) ||
+ ( ui32EventSubscriber == EVENT_O_UDMACH9SSEL ) ||
+ ( ui32EventSubscriber == EVENT_O_UDMACH9BSEL ) ||
+ ( ui32EventSubscriber == EVENT_O_UDMACH10SSEL ) ||
+ ( ui32EventSubscriber == EVENT_O_UDMACH10BSEL ) ||
+ ( ui32EventSubscriber == EVENT_O_UDMACH11SSEL ) ||
+ ( ui32EventSubscriber == EVENT_O_UDMACH11BSEL ) ||
+ ( ui32EventSubscriber == EVENT_O_UDMACH12SSEL ) ||
+ ( ui32EventSubscriber == EVENT_O_UDMACH12BSEL ) ||
+ ( ui32EventSubscriber == EVENT_O_UDMACH14BSEL ) ||
+ ( ui32EventSubscriber == EVENT_O_AUXSEL0 ) ||
+ ( ui32EventSubscriber == EVENT_O_I2SSTMPSEL0 ) ||
+ ( ui32EventSubscriber == EVENT_O_FRZSEL0 ) );
+
+ // Map the event source to the event subscriber
+ HWREG(EVENT_BASE + ui32EventSubscriber) = ui32EventSource;
+}
+
+//*****************************************************************************
+//
+//! \brief Sets software event.
+//!
+//! Setting a software event triggers the event if the value was 0 before.
+//!
+//! \note The software event must be cleared manually after the event has
+//! triggered the event subscriber.
+//!
+//! \param ui32SwEvent is the software event number.
+//! - 0 : SW Event 0
+//! - 1 : SW Event 1
+//! - 2 : SW Event 2
+//! - 3 : SW Event 3
+//!
+//! \return None
+//!
+//! \sa \ref EventSwEventClear()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+EventSwEventSet(uint32_t ui32SwEvent)
+{
+ // Check the arguments.
+ ASSERT( ui32SwEvent <= 3 );
+
+ // Each software event is byte accessible
+ HWREGB(EVENT_BASE + EVENT_O_SWEV + ui32SwEvent) = 1;
+}
+
+//*****************************************************************************
+//
+//! \brief Clears software event.
+//!
+//! \param ui32SwEvent is the software event number.
+//! - 0 : SW Event 0
+//! - 1 : SW Event 1
+//! - 2 : SW Event 2
+//! - 3 : SW Event 3
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+EventSwEventClear(uint32_t ui32SwEvent)
+{
+ // Check the arguments.
+ ASSERT( ui32SwEvent <= 3 );
+
+ // Each software event is byte accessible
+ HWREGB(EVENT_BASE + EVENT_O_SWEV + ui32SwEvent) = 0;
+}
+
+//*****************************************************************************
+//
+//! \brief Gets software event status.
+//!
+//! \param ui32SwEvent is the software event number.
+//! - 0 : SW Event 0
+//! - 1 : SW Event 1
+//! - 2 : SW Event 2
+//! - 3 : SW Event 3
+//!
+//! \return Returns current value of requested software event.
+//! - 0 : Software event is de-asserted.
+//! - 1 : Software event is asserted.
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+EventSwEventGet(uint32_t ui32SwEvent)
+{
+ // Check the arguments.
+ ASSERT( ui32SwEvent <= 3 );
+
+ // Each software event is byte accessible
+ return( HWREGB(EVENT_BASE + EVENT_O_SWEV + ui32SwEvent));
+}
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __EVENT_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/event_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/event_doc.h
new file mode 100644
index 0000000..299305c
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/event_doc.h
@@ -0,0 +1,58 @@
+/******************************************************************************
+* Filename: event_doc.h
+* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016)
+* Revision: 45971
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+//! \addtogroup event_api
+//! @{
+//! \section sec_event Introduction
+//!
+//! The event fabric consists of two event modules. One in the MCU power domain (MCU event fabric) and
+//! the other in the AON power domain (AON event fabric). The MCU event fabric is one of the subscribers
+//! to the AON event fabric. For more information on AON event fabric, see [AON event API](@ref aonevent_api).
+//!
+//! The MCU event fabric is a combinational router between event sources and event subscribers. Most
+//! event subscribers have statically routed event sources but several event subscribers have
+//! configurable event sources which is configured in the MCU event fabric through this API. Although
+//! configurable only a subset of event sources are available to each of the configurable event subscribers.
+//! This is explained in more details in the function @ref EventRegister() which does all the event routing
+//! configuration.
+//!
+//! MCU event fabric also contains four software events which allow software to trigger certain event
+//! subscribers. Each of the four software events is an independent event source which must be set and
+//! cleared in the MCU event fabric through the functions:
+//! - @ref EventSwEventSet()
+//! - @ref EventSwEventClear()
+//! - @ref EventSwEventGet()
+//!
+//! @}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/flash.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/flash.c
new file mode 100644
index 0000000..f51b30f
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/flash.c
@@ -0,0 +1,672 @@
+/******************************************************************************
+* Filename: flash.c
+* Revised: 2017-10-30 13:37:49 +0100 (Mon, 30 Oct 2017)
+* Revision: 50105
+*
+* Description: Driver for on chip Flash.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "../inc/hw_types.h"
+#include "../inc/hw_ccfg.h"
+#include "flash.h"
+#include "rom.h"
+#include "chipinfo.h"
+
+//*****************************************************************************
+//
+// Handle support for DriverLib in ROM:
+// This section will undo prototype renaming made in the header file
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #undef FlashPowerModeSet
+ #define FlashPowerModeSet NOROM_FlashPowerModeSet
+ #undef FlashPowerModeGet
+ #define FlashPowerModeGet NOROM_FlashPowerModeGet
+ #undef FlashProtectionSet
+ #define FlashProtectionSet NOROM_FlashProtectionSet
+ #undef FlashProtectionGet
+ #define FlashProtectionGet NOROM_FlashProtectionGet
+ #undef FlashProtectionSave
+ #define FlashProtectionSave NOROM_FlashProtectionSave
+ #undef FlashSectorErase
+ #define FlashSectorErase NOROM_FlashSectorErase
+ #undef FlashProgram
+ #define FlashProgram NOROM_FlashProgram
+ #undef FlashEfuseReadRow
+ #define FlashEfuseReadRow NOROM_FlashEfuseReadRow
+ #undef FlashDisableSectorsForWrite
+ #define FlashDisableSectorsForWrite NOROM_FlashDisableSectorsForWrite
+#endif
+
+
+//*****************************************************************************
+//
+// Defines for accesses to the security control in the customer configuration
+// area in flash top sector.
+//
+//*****************************************************************************
+#define CCFG_OFFSET_SECURITY CCFG_O_BL_CONFIG
+#define CCFG_OFFSET_SECT_PROT CCFG_O_CCFG_PROT_31_0
+#define CCFG_SIZE_SECURITY 0x00000014
+#define CCFG_SIZE_SECT_PROT 0x00000004
+
+//*****************************************************************************
+//
+// Default values for security control in customer configuration area in flash
+// top sector.
+//
+//*****************************************************************************
+const uint8_t g_pui8CcfgDefaultSec[] = {0xFF, 0xFF, 0xFF, 0xC5,
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xC5, 0xFF, 0xFF, 0xFF,
+ 0xC5, 0xC5, 0xC5, 0xFF,
+ 0xC5, 0xC5, 0xC5, 0xFF
+ };
+
+typedef uint32_t (* FlashPrgPointer_t) (uint8_t *, uint32_t, uint32_t);
+
+typedef uint32_t (* FlashSectorErasePointer_t) (uint32_t);
+
+//*****************************************************************************
+//
+// Function prototypes for static functions
+//
+//*****************************************************************************
+static void SetReadMode(void);
+
+//*****************************************************************************
+//
+// Set power mode
+//
+//*****************************************************************************
+void
+FlashPowerModeSet(uint32_t ui32PowerMode, uint32_t ui32BankGracePeriod,
+ uint32_t ui32PumpGracePeriod)
+{
+ // Check the arguments.
+ ASSERT(ui32PowerMode == FLASH_PWR_ACTIVE_MODE ||
+ ui32PowerMode == FLASH_PWR_OFF_MODE ||
+ ui32PowerMode == FLASH_PWR_DEEP_STDBY_MODE);
+ ASSERT(ui32BankGracePeriod <= 0xFF);
+ ASSERT(ui32PumpGracePeriod <= 0xFFFF);
+
+ switch(ui32PowerMode)
+ {
+ case FLASH_PWR_ACTIVE_MODE:
+ // Set bank power mode to ACTIVE.
+ HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) =
+ (HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) &
+ ~FLASH_FBFALLBACK_BANKPWR0_M) | FBFALLBACK_ACTIVE;
+
+ // Set charge pump power mode to ACTIVE mode.
+ HWREG(FLASH_BASE + FLASH_O_FPAC1) =
+ (HWREG(FLASH_BASE + FLASH_O_FPAC1) & ~FLASH_FPAC1_PUMPPWR_M) | (1 << FLASH_FPAC1_PUMPPWR_S);
+ break;
+
+ case FLASH_PWR_OFF_MODE:
+ // Set bank grace period.
+ HWREG(FLASH_BASE + FLASH_O_FBAC) =
+ (HWREG(FLASH_BASE + FLASH_O_FBAC) & (~FLASH_FBAC_BAGP_M)) |
+ ((ui32BankGracePeriod << FLASH_FBAC_BAGP_S) & FLASH_FBAC_BAGP_M);
+
+ // Set pump grace period.
+ HWREG(FLASH_BASE + FLASH_O_FPAC2) =
+ (HWREG(FLASH_BASE + FLASH_O_FPAC2) & (~FLASH_FPAC2_PAGP_M)) |
+ ((ui32PumpGracePeriod << FLASH_FPAC2_PAGP_S) & FLASH_FPAC2_PAGP_M);
+
+ // Set bank power mode to SLEEP.
+ HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) &= ~FLASH_FBFALLBACK_BANKPWR0_M;
+
+ // Set charge pump power mode to SLEEP mode.
+ HWREG(FLASH_BASE + FLASH_O_FPAC1) &= ~FLASH_FPAC1_PUMPPWR_M;
+ break;
+
+ case FLASH_PWR_DEEP_STDBY_MODE:
+ // Set bank grace period.
+ HWREG(FLASH_BASE + FLASH_O_FBAC) =
+ (HWREG(FLASH_BASE + FLASH_O_FBAC) & (~FLASH_FBAC_BAGP_M)) |
+ ((ui32BankGracePeriod << FLASH_FBAC_BAGP_S) & FLASH_FBAC_BAGP_M);
+
+ // Set pump grace period.
+ HWREG(FLASH_BASE + FLASH_O_FPAC2) =
+ (HWREG(FLASH_BASE + FLASH_O_FPAC2) & (~FLASH_FPAC2_PAGP_M)) |
+ ((ui32PumpGracePeriod << FLASH_FPAC2_PAGP_S) & FLASH_FPAC2_PAGP_M);
+
+ // Set bank power mode to DEEP STANDBY mode.
+ HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) =
+ (HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) &
+ ~FLASH_FBFALLBACK_BANKPWR0_M) | FBFALLBACK_DEEP_STDBY;
+
+ // Set charge pump power mode to STANDBY mode.
+ HWREG(FLASH_BASE + FLASH_O_FPAC1) |= FLASH_FPAC1_PUMPPWR_M;
+ break;
+ }
+}
+
+//*****************************************************************************
+//
+// Get current configured power mode
+//
+//*****************************************************************************
+uint32_t
+FlashPowerModeGet(void)
+{
+ uint32_t ui32PowerMode;
+ uint32_t ui32BankPwrMode;
+
+ ui32BankPwrMode = HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) &
+ FLASH_FBFALLBACK_BANKPWR0_M;
+
+ if(ui32BankPwrMode == FBFALLBACK_SLEEP)
+ {
+ ui32PowerMode = FLASH_PWR_OFF_MODE;
+ }
+ else if(ui32BankPwrMode == FBFALLBACK_DEEP_STDBY)
+ {
+ ui32PowerMode = FLASH_PWR_DEEP_STDBY_MODE;
+ }
+ else
+ {
+ ui32PowerMode = FLASH_PWR_ACTIVE_MODE;
+ }
+
+ // Return power mode.
+ return(ui32PowerMode);
+}
+
+//*****************************************************************************
+//
+// Set sector protection
+//
+//*****************************************************************************
+void
+FlashProtectionSet(uint32_t ui32SectorAddress, uint32_t ui32ProtectMode)
+{
+ uint32_t ui32SectorNumber;
+
+ // Check the arguments.
+ ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() -
+ FlashSectorSizeGet()));
+ ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00);
+
+ if(ui32ProtectMode == FLASH_WRITE_PROTECT)
+ {
+ ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) /
+ FlashSectorSizeGet();
+ HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
+
+ if(ui32SectorNumber <= 31)
+ {
+ HWREG(FLASH_BASE + FLASH_O_FSM_BSLE0) |= (1 << ui32SectorNumber);
+ HWREG(FLASH_BASE + FLASH_O_FSM_BSLP0) |= (1 << ui32SectorNumber);
+ }
+ else if(ui32SectorNumber <= 63)
+ {
+ HWREG(FLASH_BASE + FLASH_O_FSM_BSLE1) |=
+ (1 << (ui32SectorNumber & 0x1F));
+ HWREG(FLASH_BASE + FLASH_O_FSM_BSLP1) |=
+ (1 << (ui32SectorNumber & 0x1F));
+ }
+
+ HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
+ }
+}
+
+//*****************************************************************************
+//
+// Get sector protection
+//
+//*****************************************************************************
+uint32_t
+FlashProtectionGet(uint32_t ui32SectorAddress)
+{
+ uint32_t ui32SectorProtect;
+ uint32_t ui32SectorNumber;
+
+ // Check the arguments.
+ ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() -
+ FlashSectorSizeGet()));
+ ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00);
+
+ ui32SectorProtect = FLASH_NO_PROTECT;
+ ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / FlashSectorSizeGet();
+
+ if(ui32SectorNumber <= 31)
+ {
+ if((HWREG(FLASH_BASE + FLASH_O_FSM_BSLE0) & (1 << ui32SectorNumber)) &&
+ (HWREG(FLASH_BASE + FLASH_O_FSM_BSLP0) & (1 << ui32SectorNumber)))
+ {
+ ui32SectorProtect = FLASH_WRITE_PROTECT;
+ }
+ }
+ else if(ui32SectorNumber <= 63)
+ {
+ if((HWREG(FLASH_BASE + FLASH_O_FSM_BSLE1) &
+ (1 << (ui32SectorNumber & 0x1F))) &&
+ (HWREG(FLASH_BASE + FLASH_O_FSM_BSLP1) &
+ (1 << (ui32SectorNumber & 0x1F))))
+ {
+ ui32SectorProtect = FLASH_WRITE_PROTECT;
+ }
+ }
+
+ return(ui32SectorProtect);
+}
+
+//*****************************************************************************
+//
+// Save sector protection to make it permanent
+//
+//*****************************************************************************
+uint32_t
+FlashProtectionSave(uint32_t ui32SectorAddress)
+{
+ uint32_t ui32ErrorReturn;
+ uint32_t ui32SectorNumber;
+ uint32_t ui32CcfgSectorAddr;
+ uint32_t ui32ProgBuf;
+
+ ui32ErrorReturn = FAPI_STATUS_SUCCESS;
+
+ // Check the arguments.
+ ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() -
+ FlashSectorSizeGet()));
+ ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00);
+
+ if(FlashProtectionGet(ui32SectorAddress) == FLASH_WRITE_PROTECT)
+ {
+ // Find sector number for specified sector.
+ ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / FlashSectorSizeGet();
+ ui32CcfgSectorAddr = FLASHMEM_BASE + FlashSizeGet() - FlashSectorSizeGet();
+
+ // Adjust CCFG address to the 32-bit CCFG word holding the
+ // protect-bit for the specified sector.
+ ui32CcfgSectorAddr += (((ui32SectorNumber >> 5) * 4) + CCFG_OFFSET_SECT_PROT);
+
+ // Find value to program by setting the protect-bit which
+ // corresponds to specified sector number, to 0.
+ // Leave other protect-bits unchanged.
+ ui32ProgBuf = (~(1 << (ui32SectorNumber & 0x1F))) &
+ *(uint32_t *)ui32CcfgSectorAddr;
+
+ ui32ErrorReturn = FlashProgram((uint8_t*)&ui32ProgBuf, ui32CcfgSectorAddr,
+ CCFG_SIZE_SECT_PROT);
+ }
+
+ // Return status.
+ return(ui32ErrorReturn);
+}
+
+//*****************************************************************************
+//
+// Erase a flash sector
+//
+//*****************************************************************************
+uint32_t
+FlashSectorErase(uint32_t ui32SectorAddress)
+{
+ uint32_t ui32ErrorReturn;
+ FlashSectorErasePointer_t FuncPointer;
+
+ // Check the arguments.
+ ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() -
+ FlashSectorSizeGet()));
+ ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00);
+
+ // Call ROM function that handles the actual erase operation
+ FuncPointer = (uint32_t (*)(uint32_t)) (ROM_API_FLASH_TABLE[5]);
+ ui32ErrorReturn = FuncPointer(ui32SectorAddress);
+
+ // Enable standby in flash bank since ROM function might have disabled it
+ HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0;
+
+ // Return status of operation.
+ return(ui32ErrorReturn);
+
+}
+
+
+//*****************************************************************************
+//
+// Programs unprotected main bank flash sectors
+//
+//*****************************************************************************
+uint32_t
+FlashProgram(uint8_t *pui8DataBuffer, uint32_t ui32Address, uint32_t ui32Count)
+{
+ uint32_t ui32ErrorReturn;
+ FlashPrgPointer_t FuncPointer;
+
+ // Check the arguments.
+ ASSERT((ui32Address + ui32Count) <= (FLASHMEM_BASE + FlashSizeGet()));
+
+ // Call ROM function that handles the actual program operation
+ FuncPointer = (uint32_t (*)(uint8_t *, uint32_t, uint32_t)) (ROM_API_FLASH_TABLE[6]);
+ ui32ErrorReturn = FuncPointer( pui8DataBuffer, ui32Address, ui32Count);
+
+ // Enable standby in flash bank since ROM function might have disabled it
+ HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0;
+
+ // Return status of operation.
+ return(ui32ErrorReturn);
+
+}
+
+//*****************************************************************************
+//
+// Reads efuse data from specified row
+//
+//*****************************************************************************
+bool
+FlashEfuseReadRow(uint32_t *pui32EfuseData, uint32_t ui32RowAddress)
+{
+ bool bStatus;
+
+ // Make sure the clock for the efuse is enabled
+ HWREG(FLASH_BASE + FLASH_O_CFG) &= ~FLASH_CFG_DIS_EFUSECLK;
+
+ // Set timing for EFUSE read operations.
+ HWREG(FLASH_BASE + FLASH_O_EFUSEREAD) |= ((5 << FLASH_EFUSEREAD_READCLOCK_S) &
+ FLASH_EFUSEREAD_READCLOCK_M);
+
+ // Clear status register.
+ HWREG(FLASH_BASE + FLASH_O_EFUSEERROR) = 0;
+
+ // Select the FuseROM block 0.
+ HWREG(FLASH_BASE + FLASH_O_EFUSEADDR) = 0x00000000;
+
+ // Start the read operation.
+ HWREG(FLASH_BASE + FLASH_O_EFUSE) =
+ (DUMPWORD_INSTR << FLASH_EFUSE_INSTRUCTION_S) |
+ (ui32RowAddress & FLASH_EFUSE_DUMPWORD_M);
+
+ // Wait for operation to finish.
+ while(!(HWREG(FLASH_BASE + FLASH_O_EFUSEERROR) & FLASH_EFUSEERROR_DONE))
+ {
+ }
+
+ // Check if error reported.
+ if(HWREG(FLASH_BASE + FLASH_O_EFUSEERROR) & FLASH_EFUSEERROR_CODE_M)
+ {
+ // Set error status.
+ bStatus = 1;
+
+ // Clear data.
+ *pui32EfuseData = 0;
+ }
+ else
+ {
+ // Set ok status.
+ bStatus = 0;
+
+ // No error. Get data from data register.
+ *pui32EfuseData = HWREG(FLASH_BASE + FLASH_O_DATALOWER);
+ }
+
+ // Disable the efuse clock to conserve power
+ HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_EFUSECLK;
+
+ // Return the data.
+ return(bStatus);
+}
+
+
+//*****************************************************************************
+//
+// Disables all sectors for erase and programming on the active bank
+//
+//*****************************************************************************
+void
+FlashDisableSectorsForWrite(void)
+{
+ // Configure flash back to read mode
+ SetReadMode();
+
+ // Disable Level 1 Protection.
+ HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS;
+
+ // Disable all sectors for erase and programming.
+ HWREG(FLASH_BASE + FLASH_O_FBSE) = 0x0000;
+
+ // Enable Level 1 Protection.
+ HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0;
+
+ // Protect sectors from sector erase.
+ HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
+ HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0xFFFFFFFF;
+ HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0xFFFFFFFF;
+ HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
+}
+
+//*****************************************************************************
+//
+//! \internal
+//! Used to set flash in read mode.
+//!
+//! Flash is configured with values loaded from OTP dependent on the current
+//! regulator mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+static void
+SetReadMode(void)
+{
+ uint32_t ui32TrimValue;
+ uint32_t ui32Value;
+
+ // Configure the STANDBY_MODE_SEL, STANDBY_PW_SEL, DIS_STANDBY, DIS_IDLE,
+ // VIN_AT_X and VIN_BY_PASS for read mode
+ if(HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) &
+ AON_PMCTL_PWRCTL_EXT_REG_MODE)
+ {
+ // Select trim values for external regulator mode:
+ // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 7)
+ // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 6:5)
+ // Must be done while the register bit field CONFIG.DIS_STANDBY = 1
+ HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY;
+
+ ui32TrimValue =
+ HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4);
+
+ ui32Value = ((ui32TrimValue &
+ FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M) >>
+ FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S) <<
+ FLASH_CFG_STANDBY_MODE_SEL_S;
+
+ ui32Value |= ((ui32TrimValue &
+ FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M) >>
+ FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S) <<
+ FLASH_CFG_STANDBY_PW_SEL_S;
+
+ // Configure DIS_STANDBY (OTP offset 0x308 bit 4).
+ // Configure DIS_IDLE (OTP offset 0x308 bit 3).
+ ui32Value |= ((ui32TrimValue &
+ (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M |
+ FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M)) >>
+ FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S) <<
+ FLASH_CFG_DIS_IDLE_S;
+
+ HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) &
+ ~(FLASH_CFG_STANDBY_MODE_SEL_M |
+ FLASH_CFG_STANDBY_PW_SEL_M |
+ FLASH_CFG_DIS_STANDBY_M |
+ FLASH_CFG_DIS_IDLE_M)) | ui32Value;
+
+ // Check if sample and hold functionality is disabled.
+ if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE)
+ {
+ // Wait for disabled sample and hold functionality to be stable.
+ while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS))
+ {
+ }
+ }
+
+ // Configure VIN_AT_X (OTP offset 0x308 bits 2:0)
+ ui32Value = ((ui32TrimValue &
+ FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M) >>
+ FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S) <<
+ FLASH_FSEQPMP_VIN_AT_X_S;
+
+ // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value.
+ // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise
+ // VIN_BY_PASS should be 1
+ if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >>
+ FLASH_FSEQPMP_VIN_AT_X_S) != 0x7)
+ {
+ ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS;
+ }
+
+ HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA;
+ HWREG(FLASH_BASE + FLASH_O_FSEQPMP) =
+ (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) &
+ ~(FLASH_FSEQPMP_VIN_BY_PASS_M |
+ FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value;
+ HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA;
+ }
+ else
+ {
+ // Select trim values for internal regulator mode:
+ // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 15)
+ // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 14:13)
+ // Must be done while the register bit field CONFIG.DIS_STANDBY = 1
+ HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY;
+
+ ui32TrimValue =
+ HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4);
+
+ ui32Value = ((ui32TrimValue &
+ FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M) >>
+ FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S) <<
+ FLASH_CFG_STANDBY_MODE_SEL_S;
+
+ ui32Value |= ((ui32TrimValue &
+ FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M) >>
+ FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S) <<
+ FLASH_CFG_STANDBY_PW_SEL_S;
+
+ // Configure DIS_STANDBY (OTP offset 0x308 bit 12).
+ // Configure DIS_IDLE (OTP offset 0x308 bit 11).
+ ui32Value |= ((ui32TrimValue &
+ (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M |
+ FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M)) >>
+ FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S) <<
+ FLASH_CFG_DIS_IDLE_S;
+
+ HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) &
+ ~(FLASH_CFG_STANDBY_MODE_SEL_M |
+ FLASH_CFG_STANDBY_PW_SEL_M |
+ FLASH_CFG_DIS_STANDBY_M |
+ FLASH_CFG_DIS_IDLE_M)) | ui32Value;
+
+ // Check if sample and hold functionality is disabled.
+ if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE)
+ {
+ // Wait for disabled sample and hold functionality to be stable.
+ while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS))
+ {
+ }
+ }
+
+ // Configure VIN_AT_X (OTP offset 0x308 bits 10:8)
+ ui32Value = (((ui32TrimValue &
+ FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M) >>
+ FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S) <<
+ FLASH_FSEQPMP_VIN_AT_X_S);
+
+ // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value.
+ // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise
+ // VIN_BY_PASS should be 1
+ if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >>
+ FLASH_FSEQPMP_VIN_AT_X_S) != 0x7)
+ {
+ ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS;
+ }
+
+ HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA;
+ HWREG(FLASH_BASE + FLASH_O_FSEQPMP) =
+ (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) &
+ ~(FLASH_FSEQPMP_VIN_BY_PASS_M |
+ FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value;
+ HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA;
+ }
+}
+
+//*****************************************************************************
+//
+// HAPI Flash program function
+//
+//*****************************************************************************
+uint32_t
+MemBusWrkAroundHapiProgramFlash(uint8_t *pui8DataBuffer, uint32_t ui32Address,
+ uint32_t ui32Count)
+{
+ uint32_t ui32ErrorReturn;
+ FlashPrgPointer_t FuncPointer;
+ uint32_t ui32RomAddr = HWREG(ROM_HAPI_TABLE_ADDR + (5 * 4));
+
+ // Call ROM function
+ FuncPointer = (uint32_t (*)(uint8_t *, uint32_t, uint32_t)) (ui32RomAddr);
+ ui32ErrorReturn = FuncPointer( pui8DataBuffer, ui32Address, ui32Count);
+
+ // Enable standby in flash bank since ROM function might have disabled it
+ HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0;
+
+ // Return status of operation.
+ return(ui32ErrorReturn);
+}
+
+//*****************************************************************************
+//
+// HAPI Flash sector erase function
+//
+//*****************************************************************************
+uint32_t
+MemBusWrkAroundHapiEraseSector(uint32_t ui32Address)
+{
+ uint32_t ui32ErrorReturn;
+
+ FlashSectorErasePointer_t FuncPointer;
+ uint32_t ui32RomAddr = HWREG(ROM_HAPI_TABLE_ADDR + (3 * 4));
+
+ // Call ROM function
+ FuncPointer = (uint32_t (*)(uint32_t)) (ui32RomAddr);
+ ui32ErrorReturn = FuncPointer(ui32Address);
+
+ // Enable standby in flash bank since ROM function might have disabled it
+ HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0;
+
+ // Return status of operation.
+ return(ui32ErrorReturn);
+}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/flash.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/flash.h
new file mode 100644
index 0000000..a44b02d
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/flash.h
@@ -0,0 +1,817 @@
+/******************************************************************************
+* Filename: flash.h
+* Revised: 2017-11-02 16:09:32 +0100 (Thu, 02 Nov 2017)
+* Revision: 50166
+*
+* Description: Defines and prototypes for the Flash driver.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup system_control_group
+//! @{
+//! \addtogroup flash_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __FLASH_H__
+#define __FLASH_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "../inc/hw_types.h"
+#include "../inc/hw_flash.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_ints.h"
+#include "../inc/hw_aon_pmctl.h"
+#include "../inc/hw_fcfg1.h"
+#include "interrupt.h"
+#include "debug.h"
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// This section renames all functions that are not "static inline", so that
+// calling these functions will default to implementation in flash. At the end
+// of this file a second renaming will change the defaults to implementation in
+// ROM for available functions.
+//
+// To force use of the implementation in flash, e.g. for debugging:
+// - Globally: Define DRIVERLIB_NOROM at project level
+// - Per function: Use prefix "NOROM_" when calling the function
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #define FlashPowerModeSet NOROM_FlashPowerModeSet
+ #define FlashPowerModeGet NOROM_FlashPowerModeGet
+ #define FlashProtectionSet NOROM_FlashProtectionSet
+ #define FlashProtectionGet NOROM_FlashProtectionGet
+ #define FlashProtectionSave NOROM_FlashProtectionSave
+ #define FlashSectorErase NOROM_FlashSectorErase
+ #define FlashProgram NOROM_FlashProgram
+ #define FlashEfuseReadRow NOROM_FlashEfuseReadRow
+ #define FlashDisableSectorsForWrite NOROM_FlashDisableSectorsForWrite
+#endif
+
+//*****************************************************************************
+//
+// Values that can be returned from the API functions
+//
+//*****************************************************************************
+#define FAPI_STATUS_SUCCESS 0x00000000 // Function completed successfully
+#define FAPI_STATUS_FSM_BUSY 0x00000001 // FSM is Busy
+#define FAPI_STATUS_FSM_READY 0x00000002 // FSM is Ready
+#define FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH \
+ 0x00000003 // Incorrect parameter value
+#define FAPI_STATUS_FSM_ERROR 0x00000004 // Operation failed
+
+//*****************************************************************************
+//
+// Values passed to FlashIntEnable(), FlashIntDisable() and FlashIntClear() and
+// returned from FlashIntStatus().
+//
+//*****************************************************************************
+#define FLASH_INT_FSM_DONE 0x00400000 // FSM Done Interrupt Mask
+#define FLASH_INT_RV 0x00010000 // Read Verify error Interrupt Mask
+
+//*****************************************************************************
+//
+// Values passed to FlashSetPowerMode() and returned from FlashGetPowerMode().
+//
+//*****************************************************************************
+#define FLASH_PWR_ACTIVE_MODE 0x00000000
+#define FLASH_PWR_OFF_MODE 0x00000001
+#define FLASH_PWR_DEEP_STDBY_MODE \
+ 0x00000002
+
+//*****************************************************************************
+//
+// Values passed to FlashSetProtection() and returned from FlashGetProtection().
+//
+//*****************************************************************************
+#define FLASH_NO_PROTECT 0x00000000 // Sector not protected
+#define FLASH_WRITE_PROTECT 0x00000001 // Sector erase and program
+ // protected
+
+//*****************************************************************************
+//
+// Define used by the flash programming and erase functions
+//
+//*****************************************************************************
+#define ADDR_OFFSET (0x1F800000 - FLASHMEM_BASE)
+
+//*****************************************************************************
+//
+// Define used for access to factory configuration area.
+//
+//*****************************************************************************
+#define FCFG1_OFFSET 0x1000
+
+//*****************************************************************************
+//
+// Define for the clock frequency input to the flash module in number of MHz
+//
+//*****************************************************************************
+#define FLASH_MODULE_CLK_FREQ 48
+
+//*****************************************************************************
+//
+//! \brief Defined values for Flash State Machine commands
+//
+//*****************************************************************************
+typedef enum
+{
+ FAPI_PROGRAM_DATA = 0x0002, //!< Program data.
+ FAPI_ERASE_SECTOR = 0x0006, //!< Erase sector.
+ FAPI_ERASE_BANK = 0x0008, //!< Erase bank.
+ FAPI_VALIDATE_SECTOR = 0x000E, //!< Validate sector.
+ FAPI_CLEAR_STATUS = 0x0010, //!< Clear status.
+ FAPI_PROGRAM_RESUME = 0x0014, //!< Program resume.
+ FAPI_ERASE_RESUME = 0x0016, //!< Erase resume.
+ FAPI_CLEAR_MORE = 0x0018, //!< Clear more.
+ FAPI_PROGRAM_SECTOR = 0x0020, //!< Program sector.
+ FAPI_ERASE_OTP = 0x0030 //!< Erase OTP.
+} tFlashStateCommandsType;
+
+//*****************************************************************************
+//
+// Defines for values written to the FLASH_O_FSM_WR_ENA register
+//
+//*****************************************************************************
+#define FSM_REG_WRT_ENABLE 5
+#define FSM_REG_WRT_DISABLE 2
+
+//*****************************************************************************
+//
+// Defines for the bank power mode field the FLASH_O_FBFALLBACK register
+//
+//*****************************************************************************
+#define FBFALLBACK_SLEEP 0
+#define FBFALLBACK_DEEP_STDBY 1
+#define FBFALLBACK_ACTIVE 3
+
+//*****************************************************************************
+//
+// Defines for the bank grace period and pump grace period
+//
+//*****************************************************************************
+#define FLASH_BAGP 0x14
+#define FLASH_PAGP 0x14
+
+//*****************************************************************************
+//
+// Defines used by the FlashProgramPattern() function
+//
+//*****************************************************************************
+#define PATTERN_BITS 0x20 // No of bits in data pattern to program
+
+//*****************************************************************************
+//
+// Defines for the FW flag bits in the FLASH_O_FWFLAG register
+//
+//*****************************************************************************
+#define FW_WRT_TRIMMED 0x00000001
+
+//*****************************************************************************
+//
+// Defines used by the flash programming functions
+//
+//*****************************************************************************
+typedef volatile uint8_t tFwpWriteByte;
+#define FWPWRITE_BYTE_ADDRESS ((tFwpWriteByte *)((FLASH_BASE + FLASH_O_FWPWRITE0)))
+
+//*****************************************************************************
+//
+// Define for efuse instruction
+//
+//*****************************************************************************
+#define DUMPWORD_INSTR 0x04
+
+//*****************************************************************************
+//
+// Define for FSM command execution
+//
+//*****************************************************************************
+#define FLASH_CMD_EXEC 0x15
+
+//*****************************************************************************
+//
+//! \brief Get size of a flash sector in number of bytes.
+//!
+//! This function will return the size of a flash sector in number of bytes.
+//!
+//! \return Returns size of a flash sector in number of bytes.
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+FlashSectorSizeGet(void)
+{
+ uint32_t ui32SectorSizeInKbyte;
+
+ ui32SectorSizeInKbyte = (HWREG(FLASH_BASE + FLASH_O_FCFG_B0_SSIZE0) &
+ FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_M) >>
+ FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_S;
+
+ // Return flash sector size in number of bytes.
+ return(ui32SectorSizeInKbyte * 1024);
+}
+
+//*****************************************************************************
+//
+//! \brief Get the size of the flash.
+//!
+//! This function returns the size of the flash main bank in number of bytes.
+//!
+//! \return Returns the flash size in number of bytes.
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+FlashSizeGet(void)
+{
+ uint32_t ui32NoOfSectors;
+
+ // Get number of flash sectors
+ ui32NoOfSectors = (HWREG(FLASH_BASE + FLASH_O_FLASH_SIZE) &
+ FLASH_FLASH_SIZE_SECTORS_M) >>
+ FLASH_FLASH_SIZE_SECTORS_S;
+
+ // Return flash size in number of bytes
+ return(ui32NoOfSectors * FlashSectorSizeGet());
+}
+
+//*****************************************************************************
+//
+//! \brief Set power mode.
+//!
+//! This function will set the specified power mode.
+//!
+//! Any access to the bank causes a reload of the specified bank grace period
+//! input value into the bank down counter. After the last access to the
+//! flash bank, the down counter delays from 0 to 255 prescaled HCLK clock
+//! cycles before putting the bank into one of the fallback power modes as
+//! determined by \c ui32PowerMode. This value must be greater than 1 when the
+//! fallback mode is not \ref FLASH_PWR_ACTIVE_MODE.
+//!
+//! Note: The prescaled clock used for the down counter is a clock divided by
+//! 16 from input HCLK. The \c ui32BankGracePeriod parameter is ignored if
+//! \c ui32PowerMode is equal to \ref FLASH_PWR_ACTIVE_MODE.
+//! Any access to flash memory causes the pump grace period down counter to
+//! reload with value of \c ui32PumpGracePeriod. After the bank has gone to sleep,
+//! the down counter delays this number of prescaled HCLK clock cycles before
+//! entering one of the charge pump fallback power modes as determined by
+//! \c ui32PowerMode. The prescaled clock used for the pump grace period down
+//! counter is a clock divided by 16 from input HCLK. This parameter is ignored
+//! if \c ui32PowerMode is equal to \ref FLASH_PWR_ACTIVE_MODE.
+//!
+//! Changing the power mode of the flash module must be a part within a
+//! device power mode transition requiring configuration of multiple modules.
+//! Refer to documents describing the device power modes.
+//!
+//! \param ui32PowerMode is the wanted power mode.
+//! The defined flash power modes are:
+//! - \ref FLASH_PWR_ACTIVE_MODE
+//! - \ref FLASH_PWR_OFF_MODE
+//! - \ref FLASH_PWR_DEEP_STDBY_MODE
+//! \param ui32BankGracePeriod is the starting count value for the bank grace
+//! period down counter.
+//! \param ui32PumpGracePeriod is the starting count value for the pump grace
+//! period down counter.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void FlashPowerModeSet(uint32_t ui32PowerMode,
+ uint32_t ui32BankGracePeriod,
+ uint32_t ui32PumpGracePeriod);
+
+//*****************************************************************************
+//
+//! \brief Get current configured power mode.
+//!
+//! This function will return the current configured power mode.
+//!
+//! \return Returns the current configured power mode.
+//! The defined power modes are:
+//! - \ref FLASH_PWR_ACTIVE_MODE
+//! - \ref FLASH_PWR_OFF_MODE
+//! - \ref FLASH_PWR_DEEP_STDBY_MODE
+//
+//*****************************************************************************
+extern uint32_t FlashPowerModeGet(void);
+
+//*****************************************************************************
+//
+//! \brief Set sector protection.
+//!
+//! This function will set the specified protection on specified flash bank
+//! sector. A sector can either have no protection or have write protection
+//! which guards for both program and erase of that sector.
+//! Sector protection can only be changed from \ref FLASH_NO_PROTECT to
+//! \ref FLASH_WRITE_PROTECT! After write protecting a sector this sector can
+//! only be set back to unprotected by a device reset.
+//!
+//! \param ui32SectorAddress is the start address of the sector to protect.
+//! \param ui32ProtectMode is the enumerated sector protection mode.
+//! - \ref FLASH_NO_PROTECT
+//! - \ref FLASH_WRITE_PROTECT
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void FlashProtectionSet(uint32_t ui32SectorAddress,
+ uint32_t ui32ProtectMode);
+
+//*****************************************************************************
+//
+//! \brief Get sector protection.
+//!
+//! This return the protection mode for the specified flash bank sector.
+//!
+//! \param ui32SectorAddress is the start address of the desired sector.
+//!
+//! \return Returns the sector protection:
+//! - \ref FLASH_NO_PROTECT
+//! - \ref FLASH_WRITE_PROTECT
+//
+//*****************************************************************************
+extern uint32_t FlashProtectionGet(uint32_t ui32SectorAddress);
+
+//*****************************************************************************
+//
+//! \brief Save sector protection to make it permanent.
+//!
+//! This function will save the current protection mode for the specified
+//! flash bank sector.
+//!
+//! This function must only be executed from ROM or SRAM.
+//!
+//! \note A write protected sector will become permanent write
+//! protected!! A device reset will not change the write protection!
+//!
+//! \param ui32SectorAddress is the start address of the sector to be protected.
+//!
+//! \return Returns the status of the sector protection:
+//! - \ref FAPI_STATUS_SUCCESS : Success.
+//! - \ref FAPI_STATUS_FSM_ERROR : An erase error is encountered.
+//
+//*****************************************************************************
+extern uint32_t FlashProtectionSave(uint32_t ui32SectorAddress);
+
+//*****************************************************************************
+//
+//! \brief Checks if the Flash state machine has detected an error.
+//!
+//! This function returns the status of the Flash State Machine indicating if
+//! an error is detected or not. Primary use is to check if an Erase or
+//! Program operation has failed.
+//!
+//! \note Please note that code can not execute in flash while any part of the flash
+//! is being programmed or erased. This function must be called from ROM or
+//! SRAM while any part of the flash is being programmed or erased.
+//!
+//! \return Returns status of Flash state machine:
+//! - \ref FAPI_STATUS_FSM_ERROR
+//! - \ref FAPI_STATUS_SUCCESS
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+FlashCheckFsmForError(void)
+{
+ if(HWREG(FLASH_BASE + FLASH_O_FMSTAT) & FLASH_FMSTAT_CSTAT)
+ {
+ return(FAPI_STATUS_FSM_ERROR);
+ }
+ else
+ {
+ return(FAPI_STATUS_SUCCESS);
+ }
+}
+
+//*****************************************************************************
+//
+//! \brief Checks if the Flash state machine is ready.
+//!
+//! This function returns the status of the Flash State Machine indicating if
+//! it is ready to accept a new command or not. Primary use is to check if an
+//! Erase or Program operation has finished.
+//!
+//! \note Please note that code can not execute in flash while any part of the flash
+//! is being programmed or erased. This function must be called from ROM or
+//! SRAMh while any part of the flash is being programmed or erased.
+//!
+//! \return Returns readiness status of Flash state machine:
+//! - \ref FAPI_STATUS_FSM_READY
+//! - \ref FAPI_STATUS_FSM_BUSY
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+FlashCheckFsmForReady(void)
+{
+ if(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_BUSY)
+ {
+ return(FAPI_STATUS_FSM_BUSY);
+ }
+ else
+ {
+ return(FAPI_STATUS_FSM_READY);
+ }
+}
+
+//*****************************************************************************
+//
+//! \brief Registers an interrupt handler for the flash interrupt in the dynamic interrupt table.
+//!
+//! \note Only use this function if you want to use the dynamic vector table (in SRAM)!
+//!
+//! This function registers a function as the interrupt handler for a specific
+//! interrupt and enables the corresponding interrupt in the interrupt controller.
+//!
+//! Specific FLASH interrupts must be enabled via \ref FlashIntEnable(). It is the
+//! interrupt handler's responsibility to clear the interrupt source.
+//!
+//! \param pfnHandler is a pointer to the function to be called when the flash
+//! interrupt occurs.
+//!
+//! \return None
+//!
+//! \sa \ref IntRegister() for important information about registering interrupt
+//! handlers.
+//
+//*****************************************************************************
+__STATIC_INLINE void
+FlashIntRegister(void (*pfnHandler)(void))
+{
+ // Register the interrupt handler.
+ IntRegister(INT_FLASH, pfnHandler);
+
+ // Enable the flash interrupt.
+ IntEnable(INT_FLASH);
+}
+
+//*****************************************************************************
+//
+//! \brief Unregisters the interrupt handler for the flash interrupt in the dynamic interrupt table.
+//!
+//! This function does the actual unregistering of the interrupt handler. It
+//! clears the handler to be called when a FLASH interrupt occurs. This
+//! function also masks off the interrupt in the interrupt controller so that
+//! the interrupt handler no longer is called.
+//!
+//! \return None
+//!
+//! \sa \ref IntRegister() for important information about registering interrupt
+//! handlers.
+//
+//*****************************************************************************
+__STATIC_INLINE void
+FlashIntUnregister(void)
+{
+ // Disable the interrupts.
+ IntDisable(INT_FLASH);
+
+ // Unregister the interrupt handler.
+ IntUnregister(INT_FLASH);
+}
+
+//*****************************************************************************
+//
+//! \brief Enables flash controller interrupt sources.
+//!
+//! This function enables the flash controller interrupt sources.
+//!
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled.
+//! The parameter is the bitwise OR of any of the following:
+//! - \ref FLASH_INT_FSM_DONE : FSM Done interrupt.
+//! - \ref FLASH_INT_RV : Read verify error interrupt.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+FlashIntEnable(uint32_t ui32IntFlags)
+{
+ HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
+ HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= ui32IntFlags;
+ HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
+}
+
+//*****************************************************************************
+//
+//! \brief Disables individual flash controller interrupt sources.
+//!
+//! This function disables the flash controller interrupt sources.
+//!
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled.
+//! The parameter is the bitwise OR of any of the following:
+//! - \ref FLASH_INT_FSM_DONE : FSM Done interrupt.
+//! - \ref FLASH_INT_RV : Read verify error interrupt.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+FlashIntDisable(uint32_t ui32IntFlags)
+{
+ HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE;
+ HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= ~ui32IntFlags;
+ HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE;
+}
+
+//*****************************************************************************
+//
+//! \brief Gets the current interrupt status.
+//!
+//! This function returns the interrupt status for the Flash.
+//!
+//! \return Returns the current interrupt status as values described in
+//! \ref FlashIntEnable().
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+FlashIntStatus(void)
+{
+ uint32_t ui32IntFlags;
+
+ ui32IntFlags = 0;
+
+ // Check if FSM_DONE interrupt status is set.
+ if(HWREG(FLASH_BASE + FLASH_O_FEDACSTAT) & FLASH_FEDACSTAT_FSM_DONE)
+ {
+ ui32IntFlags = FLASH_INT_FSM_DONE;
+ }
+
+ // Check if RVF_INT interrupt status is set.
+ if(HWREG(FLASH_BASE + FLASH_O_FEDACSTAT) & FLASH_FEDACSTAT_RVF_INT)
+ {
+ ui32IntFlags |= FLASH_INT_RV;
+ }
+
+ return(ui32IntFlags);
+}
+
+//*****************************************************************************
+//
+//! \brief Clears flash controller interrupt source.
+//!
+//! The flash controller interrupt source is cleared, so that it no longer
+//! asserts. This must be done in the interrupt handler to keep it from being
+//! called again immediately upon exit.
+//!
+//! \note Due to write buffers and synchronizers in the system it may take several
+//! clock cycles from a register write clearing an event in a module and until the
+//! event is actually cleared in the NVIC of the system CPU. It is recommended to
+//! clear the event source early in the interrupt service routine (ISR) to allow
+//! the event clear to propagate to the NVIC before returning from the ISR.
+//! At the same time, an early event clear allows new events of the same type to be
+//! pended instead of ignored if the event is cleared later in the ISR.
+//! It is the responsibility of the programmer to make sure that enough time has passed
+//! before returning from the ISR to avoid false re-triggering of the cleared event.
+//! A simple, although not necessarily optimal, way of clearing an event before
+//! returning from the ISR is:
+//! -# Write to clear event (interrupt source). (buffered write)
+//! -# Dummy read from the event source module. (making sure the write has propagated)
+//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers)
+//!
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be cleared.
+//! Can be any of:
+//! - \ref FLASH_INT_FSM_DONE
+//! - \ref FLASH_INT_RV
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+FlashIntClear(uint32_t ui32IntFlags)
+{
+ uint32_t ui32TempVal;
+
+ ui32TempVal = 0;
+
+ if(ui32IntFlags & FLASH_INT_FSM_DONE)
+ {
+ ui32TempVal = FLASH_FEDACSTAT_FSM_DONE;
+ }
+
+ if(ui32IntFlags & FLASH_INT_RV)
+ {
+ ui32TempVal |= FLASH_FEDACSTAT_RVF_INT;
+ }
+
+ // Clear the flash interrupt source.
+ HWREG(FLASH_BASE + FLASH_O_FEDACSTAT) = ui32TempVal;
+}
+
+//*****************************************************************************
+//
+//! \brief Erase a flash sector.
+//!
+//! This function will erase the specified flash sector. The function will
+//! not return until the flash sector has been erased or an error condition
+//! occurred. If flash top sector is erased the function will program the
+//! the device security data bytes with default values. The device security
+//! data located in the customer configuration area of the flash top sector,
+//! must have valid values at all times. These values affect the configuration
+//! of the device during boot.
+//!
+//! \warning Please note that code can not execute in flash while any part of the flash
+//! is being programmed or erased. The application must disable interrupts that have
+//! interrupt routines in flash. This function calls a ROM function which handles the
+//! actual program operation.
+//!
+//! \param ui32SectorAddress is the starting address in flash of the sector to be
+//! erased.
+//!
+//! \return Returns the status of the sector erase:
+//! - \ref FAPI_STATUS_SUCCESS : Success.
+//! - \ref FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH : Invalid argument.
+//! - \ref FAPI_STATUS_FSM_ERROR : A programming error is encountered.
+//
+//*****************************************************************************
+extern uint32_t FlashSectorErase(uint32_t ui32SectorAddress);
+
+
+//*****************************************************************************
+//
+//! \brief Programs unprotected flash sectors in the main bank.
+//!
+//! This function programs a sequence of bytes into the on-chip flash.
+//! Programming each location consists of the result of an AND operation
+//! of the new data and the existing data; in other words bits that contain
+//! 1 can remain 1 or be changed to 0, but bits that are 0 cannot be changed
+//! to 1. Therefore, a byte can be programmed multiple times as long as these
+//! rules are followed; if a program operation attempts to change a 0 bit to
+//! a 1 bit, that bit will not have its value changed.
+//!
+//! This function does not return until the data has been programmed or a
+//! programming error occurs.
+//!
+//! \note It is recommended to disable cache and line buffer before programming the
+//! flash. Cache and line buffer are not automatically updated if a flash program
+//! causes a mismatch between new flash content and old content in cache and
+//! line buffer. Remember to enable cache and line buffer when the program
+//! operation completes. See \ref VIMSModeSafeSet(), \ref VIMSLineBufDisable(),
+//! and \ref VIMSLineBufEnable() for more information.
+//!
+//! \warning Please note that code can not execute in flash while any part of the flash
+//! is being programmed or erased. The application must disable interrupts that have
+//! interrupt routines in flash. This function calls a ROM function which handles the
+//! actual program operation.
+//!
+//! The \c pui8DataBuffer pointer can not point to flash.
+//!
+//! \param pui8DataBuffer is a pointer to the data to be programmed.
+//! \param ui32Address is the starting address in flash to be programmed.
+//! \param ui32Count is the number of bytes to be programmed.
+//!
+//! \return Returns status of the flash programming:
+//! - \ref FAPI_STATUS_SUCCESS : Success.
+//! - \ref FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH : Too many bytes were requested.
+//! - \ref FAPI_STATUS_FSM_ERROR : A programming error is encountered.
+//
+//*****************************************************************************
+extern uint32_t FlashProgram(uint8_t *pui8DataBuffer,
+ uint32_t ui32Address, uint32_t ui32Count);
+
+//*****************************************************************************
+//
+//! \brief Reads efuse data from specified row.
+//!
+//! This function will read one efuse row.
+//! It is assumed that any previous efuse operation has finished.
+//!
+//! \param pui32EfuseData is pointer to variable to be updated with efuse data.
+//! \param ui32RowAddress is the efuse row number to be read. First row is row
+//! number 0.
+//!
+//! \return Returns the status of the efuse read operation.
+//! - \c false : OK status.
+//! - \c true : Error status
+//
+//*****************************************************************************
+extern bool FlashEfuseReadRow(uint32_t *pui32EfuseData,
+ uint32_t ui32RowAddress);
+
+//*****************************************************************************
+//
+//! \brief Disables all sectors for erase and programming on the active bank.
+//!
+//! This function disables all sectors for erase and programming on the active
+//! bank and enables the Idle Reading Power reduction mode if no low power
+//! mode is configured. Furthermore, an additional level of protection from
+//! erase is enabled.
+//!
+//! \note Please note that code can not execute in flash while any part of the flash
+//! is being programmed or erased.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void FlashDisableSectorsForWrite(void);
+
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// Redirect to implementation in ROM when available.
+//
+//*****************************************************************************
+#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
+ #include "../driverlib/rom.h"
+ #ifdef ROM_FlashPowerModeSet
+ #undef FlashPowerModeSet
+ #define FlashPowerModeSet ROM_FlashPowerModeSet
+ #endif
+ #ifdef ROM_FlashPowerModeGet
+ #undef FlashPowerModeGet
+ #define FlashPowerModeGet ROM_FlashPowerModeGet
+ #endif
+ #ifdef ROM_FlashProtectionSet
+ #undef FlashProtectionSet
+ #define FlashProtectionSet ROM_FlashProtectionSet
+ #endif
+ #ifdef ROM_FlashProtectionGet
+ #undef FlashProtectionGet
+ #define FlashProtectionGet ROM_FlashProtectionGet
+ #endif
+ #ifdef ROM_FlashProtectionSave
+ #undef FlashProtectionSave
+ #define FlashProtectionSave ROM_FlashProtectionSave
+ #endif
+ #ifdef ROM_FlashSectorErase
+ #undef FlashSectorErase
+ #define FlashSectorErase ROM_FlashSectorErase
+ #endif
+ #ifdef ROM_FlashProgram
+ #undef FlashProgram
+ #define FlashProgram ROM_FlashProgram
+ #endif
+ #ifdef ROM_FlashEfuseReadRow
+ #undef FlashEfuseReadRow
+ #define FlashEfuseReadRow ROM_FlashEfuseReadRow
+ #endif
+ #ifdef ROM_FlashDisableSectorsForWrite
+ #undef FlashDisableSectorsForWrite
+ #define FlashDisableSectorsForWrite ROM_FlashDisableSectorsForWrite
+ #endif
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __FLASH_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/gpio.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/gpio.c
new file mode 100644
index 0000000..ace56ae
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/gpio.c
@@ -0,0 +1,41 @@
+/******************************************************************************
+* Filename: gpio.c
+* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016)
+* Revision: 47179
+*
+* Description: Driver for the GPIO
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "gpio.h"
+
+// see gpio.h for implementation
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/gpio.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/gpio.h
new file mode 100644
index 0000000..2829ea6
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/gpio.h
@@ -0,0 +1,643 @@
+/******************************************************************************
+* Filename: gpio.h
+* Revised: 2018-05-02 11:11:40 +0200 (Wed, 02 May 2018)
+* Revision: 51951
+*
+* Description: Defines and prototypes for the GPIO.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup peripheral_group
+//! @{
+//! \addtogroup gpio_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __GPIO_H__
+#define __GPIO_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include "../inc/hw_types.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_gpio.h"
+#include "debug.h"
+
+//*****************************************************************************
+//
+// Check for legal range of variable dioNumber
+//
+//*****************************************************************************
+#ifdef DRIVERLIB_DEBUG
+#include "../inc/hw_fcfg1.h"
+#include "chipinfo.h"
+
+static bool
+dioNumberLegal( uint32_t dioNumber )
+{
+ uint32_t ioCount =
+ (( HWREG( FCFG1_BASE + FCFG1_O_IOCONF ) &
+ FCFG1_IOCONF_GPIO_CNT_M ) >>
+ FCFG1_IOCONF_GPIO_CNT_S ) ;
+
+ // CC13x2 + CC26x2
+ if ( ChipInfo_ChipFamilyIs_CC13x2_CC26x2() )
+ {
+ return ( (dioNumber >= (31 - ioCount)) && (dioNumber < 31) )
+ }
+ // Special handling of CC13x0 7x7, where IO_CNT = 30 and legal range is 1..30
+ // for all other chips legal range is 0..(dioNumber-1)
+ else if (( ioCount == 30 ) && ChipInfo_ChipFamilyIs_CC13x0() )
+ {
+ return (( dioNumber > 0 ) && ( dioNumber <= ioCount ));
+ }
+ else
+ {
+ return ( dioNumber < ioCount );
+ }
+
+}
+#endif
+
+//*****************************************************************************
+//
+// The following values define the bit field for the GPIO DIOs.
+//
+//*****************************************************************************
+#define GPIO_DIO_0_MASK 0x00000001 // GPIO DIO 0 mask
+#define GPIO_DIO_1_MASK 0x00000002 // GPIO DIO 1 mask
+#define GPIO_DIO_2_MASK 0x00000004 // GPIO DIO 2 mask
+#define GPIO_DIO_3_MASK 0x00000008 // GPIO DIO 3 mask
+#define GPIO_DIO_4_MASK 0x00000010 // GPIO DIO 4 mask
+#define GPIO_DIO_5_MASK 0x00000020 // GPIO DIO 5 mask
+#define GPIO_DIO_6_MASK 0x00000040 // GPIO DIO 6 mask
+#define GPIO_DIO_7_MASK 0x00000080 // GPIO DIO 7 mask
+#define GPIO_DIO_8_MASK 0x00000100 // GPIO DIO 8 mask
+#define GPIO_DIO_9_MASK 0x00000200 // GPIO DIO 9 mask
+#define GPIO_DIO_10_MASK 0x00000400 // GPIO DIO 10 mask
+#define GPIO_DIO_11_MASK 0x00000800 // GPIO DIO 11 mask
+#define GPIO_DIO_12_MASK 0x00001000 // GPIO DIO 12 mask
+#define GPIO_DIO_13_MASK 0x00002000 // GPIO DIO 13 mask
+#define GPIO_DIO_14_MASK 0x00004000 // GPIO DIO 14 mask
+#define GPIO_DIO_15_MASK 0x00008000 // GPIO DIO 15 mask
+#define GPIO_DIO_16_MASK 0x00010000 // GPIO DIO 16 mask
+#define GPIO_DIO_17_MASK 0x00020000 // GPIO DIO 17 mask
+#define GPIO_DIO_18_MASK 0x00040000 // GPIO DIO 18 mask
+#define GPIO_DIO_19_MASK 0x00080000 // GPIO DIO 19 mask
+#define GPIO_DIO_20_MASK 0x00100000 // GPIO DIO 20 mask
+#define GPIO_DIO_21_MASK 0x00200000 // GPIO DIO 21 mask
+#define GPIO_DIO_22_MASK 0x00400000 // GPIO DIO 22 mask
+#define GPIO_DIO_23_MASK 0x00800000 // GPIO DIO 23 mask
+#define GPIO_DIO_24_MASK 0x01000000 // GPIO DIO 24 mask
+#define GPIO_DIO_25_MASK 0x02000000 // GPIO DIO 25 mask
+#define GPIO_DIO_26_MASK 0x04000000 // GPIO DIO 26 mask
+#define GPIO_DIO_27_MASK 0x08000000 // GPIO DIO 27 mask
+#define GPIO_DIO_28_MASK 0x10000000 // GPIO DIO 28 mask
+#define GPIO_DIO_29_MASK 0x20000000 // GPIO DIO 29 mask
+#define GPIO_DIO_30_MASK 0x40000000 // GPIO DIO 30 mask
+#define GPIO_DIO_31_MASK 0x80000000 // GPIO DIO 31 mask
+#define GPIO_DIO_ALL_MASK 0xFFFFFFFF // GPIO all DIOs mask
+
+//*****************************************************************************
+//
+// Define constants that shall be passed as the outputEnableValue parameter to
+// GPIO_setOutputEnableDio() and will be returned from the function
+// GPIO_getOutputEnableDio().
+//
+//*****************************************************************************
+#define GPIO_OUTPUT_DISABLE 0x00000000 // DIO output is disabled
+#define GPIO_OUTPUT_ENABLE 0x00000001 // DIO output is enabled
+
+//*****************************************************************************
+//
+// API Functions and prototypes
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \brief Reads a specific DIO.
+//!
+//! \param dioNumber specifies the DIO to read (0-31).
+//!
+//! \return Returns 0 or 1 reflecting the input value of the specified DIO.
+//!
+//! \sa \ref GPIO_readMultiDio(), \ref GPIO_writeDio(), \ref GPIO_writeMultiDio()
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+GPIO_readDio( uint32_t dioNumber )
+{
+ // Check the arguments.
+ ASSERT( dioNumberLegal( dioNumber ));
+
+ // Return the input value from the specified DIO.
+ return (( HWREG( GPIO_BASE + GPIO_O_DIN31_0 ) >> dioNumber ) & 1 );
+}
+
+//*****************************************************************************
+//
+//! \brief Reads the input value for the specified DIOs.
+//!
+//! This function returns the input value for multiple DIOs.
+//! The value returned is not shifted and hence matches the corresponding dioMask bits.
+//!
+//! \param dioMask is the bit-mask representation of the DIOs to read.
+//! The parameter must be a bitwise OR'ed combination of the following:
+//! - \ref GPIO_DIO_0_MASK
+//! - ...
+//! - \ref GPIO_DIO_31_MASK
+//!
+//! \return Returns a bit vector reflecting the input value of the corresponding DIOs.
+//! - 0 : Corresponding DIO is low.
+//! - 1 : Corresponding DIO is high.
+//!
+//! \sa \ref GPIO_readDio(), \ref GPIO_writeDio(), \ref GPIO_writeMultiDio()
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+GPIO_readMultiDio( uint32_t dioMask )
+{
+ // Check the arguments.
+ ASSERT( dioMask & GPIO_DIO_ALL_MASK );
+
+ // Return the input value from the specified DIOs.
+ return ( HWREG( GPIO_BASE + GPIO_O_DIN31_0 ) & dioMask );
+}
+
+//*****************************************************************************
+//
+//! \brief Writes a value to a specific DIO.
+//!
+//! \param dioNumber specifies the DIO to update (0-31).
+//! \param value specifies the value to write
+//! - 0 : Logic zero (low)
+//! - 1 : Logic one (high)
+//!
+//! \return None
+//!
+//! \sa \ref GPIO_writeMultiDio(), \ref GPIO_readDio(), \ref GPIO_readMultiDio()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+GPIO_writeDio( uint32_t dioNumber, uint32_t value )
+{
+ // Check the arguments.
+ ASSERT( dioNumberLegal( dioNumber ));
+ ASSERT(( value == 0 ) || ( value == 1 ));
+
+ // Write 0 or 1 to the byte indexed DOUT map
+ HWREGB( GPIO_BASE + dioNumber ) = value;
+}
+
+//*****************************************************************************
+//
+//! \brief Writes masked data to the specified DIOs.
+//!
+//! Enables for writing multiple bits simultaneously.
+//! The value to write must be shifted so it matches the corresponding dioMask bits.
+//!
+//! \note Note that this is a read-modify-write operation and hence not atomic.
+//!
+//! \param dioMask is the bit-mask representation of the DIOs to write.
+//! The parameter must be a bitwise OR'ed combination of the following:
+//! - \ref GPIO_DIO_0_MASK
+//! - ...
+//! - \ref GPIO_DIO_31_MASK
+//! \param bitVectoredValue holds the value to be written to the corresponding DIO-bits.
+//!
+//! \return None
+//!
+//! \sa \ref GPIO_writeDio(), \ref GPIO_readDio(), \ref GPIO_readMultiDio()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+GPIO_writeMultiDio( uint32_t dioMask, uint32_t bitVectoredValue )
+{
+ // Check the arguments.
+ ASSERT( dioMask & GPIO_DIO_ALL_MASK );
+
+ HWREG( GPIO_BASE + GPIO_O_DOUT31_0 ) =
+ ( HWREG( GPIO_BASE + GPIO_O_DOUT31_0 ) & ~dioMask ) |
+ ( bitVectoredValue & dioMask );
+}
+
+//*****************************************************************************
+//
+//! \brief Sets a specific DIO to 1 (high).
+//!
+//! \param dioNumber specifies the DIO to set (0-31).
+//!
+//! \return None
+//!
+//! \sa \ref GPIO_setMultiDio(), \ref GPIO_clearDio(), \ref GPIO_clearMultiDio()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+GPIO_setDio( uint32_t dioNumber )
+{
+ // Check the arguments.
+ ASSERT( dioNumberLegal( dioNumber ));
+
+ // Set the specified DIO.
+ HWREG( GPIO_BASE + GPIO_O_DOUTSET31_0 ) = ( 1 << dioNumber );
+}
+
+//*****************************************************************************
+//
+//! \brief Sets the specified DIOs to 1 (high).
+//!
+//! \param dioMask is the bit-mask representation of the DIOs to set.
+//! The parameter must be a bitwise OR'ed combination of the following:
+//! - \ref GPIO_DIO_0_MASK
+//! - ...
+//! - \ref GPIO_DIO_31_MASK
+//!
+//! \return None
+//!
+//! \sa \ref GPIO_setDio(), \ref GPIO_clearDio(), \ref GPIO_clearMultiDio()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+GPIO_setMultiDio( uint32_t dioMask )
+{
+ // Check the arguments.
+ ASSERT( dioMask & GPIO_DIO_ALL_MASK );
+
+ // Set the DIOs.
+ HWREG( GPIO_BASE + GPIO_O_DOUTSET31_0 ) = dioMask;
+}
+
+//*****************************************************************************
+//
+//! \brief Clears a specific DIO to 0 (low).
+//!
+//! \param dioNumber specifies the DIO to clear (0-31).
+//!
+//! \return None
+//!
+//! \sa \ref GPIO_clearMultiDio(), \ref GPIO_setDio(), \ref GPIO_setMultiDio()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+GPIO_clearDio( uint32_t dioNumber )
+{
+ // Check the arguments.
+ ASSERT( dioNumberLegal( dioNumber ));
+
+ // Clear the specified DIO.
+ HWREG( GPIO_BASE + GPIO_O_DOUTCLR31_0 ) = ( 1 << dioNumber );
+}
+
+//*****************************************************************************
+//
+//! \brief Clears the specified DIOs to 0 (low).
+//!
+//! \param dioMask is the bit-mask representation of the DIOs to clear.
+//! The parameter must be a bitwise OR'ed combination of the following:
+//! - \ref GPIO_DIO_0_MASK
+//! - ...
+//! - \ref GPIO_DIO_31_MASK
+//!
+//! \return None
+//!
+//! \sa \ref GPIO_clearDio(), \ref GPIO_setDio(), \ref GPIO_setMultiDio()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+GPIO_clearMultiDio( uint32_t dioMask )
+{
+ // Check the arguments.
+ ASSERT( dioMask & GPIO_DIO_ALL_MASK );
+
+ // Clear the DIOs.
+ HWREG( GPIO_BASE + GPIO_O_DOUTCLR31_0 ) = dioMask;
+}
+
+//*****************************************************************************
+//
+//! \brief Toggles a specific DIO.
+//!
+//! \param dioNumber specifies the DIO to toggle (0-31).
+//!
+//! \return None
+//!
+//! \sa \ref GPIO_toggleMultiDio()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+GPIO_toggleDio( uint32_t dioNumber )
+{
+ // Check the arguments.
+ ASSERT( dioNumberLegal( dioNumber ));
+
+ // Toggle the specified DIO.
+ HWREG( GPIO_BASE + GPIO_O_DOUTTGL31_0 ) = ( 1 << dioNumber );
+}
+
+//*****************************************************************************
+//
+//! \brief Toggles the specified DIOs.
+//!
+//! \param dioMask is the bit-mask representation of the DIOs to toggle.
+//! The parameter must be a bitwise OR'ed combination of the following:
+//! - \ref GPIO_DIO_0_MASK
+//! - ...
+//! - \ref GPIO_DIO_31_MASK
+//!
+//! \return None
+//!
+//! \sa \ref GPIO_toggleDio()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+GPIO_toggleMultiDio( uint32_t dioMask )
+{
+ // Check the arguments.
+ ASSERT( dioMask & GPIO_DIO_ALL_MASK );
+
+ // Toggle the DIOs.
+ HWREG( GPIO_BASE + GPIO_O_DOUTTGL31_0 ) = dioMask;
+}
+
+//*****************************************************************************
+//
+//! \brief Gets the output enable status of a specific DIO.
+//!
+//! This function returns the output enable status for the specified DIO.
+//! The DIO can be configured as either input or output under software control.
+//!
+//! \param dioNumber specifies the DIO to get the output enable setting from (0-31).
+//!
+//! \return Returns one of the enumerated data types (0 or 1):
+//! - \ref GPIO_OUTPUT_DISABLE : DIO output is disabled.
+//! - \ref GPIO_OUTPUT_ENABLE : DIO output is enabled.
+//!
+//! \sa \ref GPIO_getOutputEnableMultiDio(), \ref GPIO_setOutputEnableDio(), \ref GPIO_setOutputEnableMultiDio()
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+GPIO_getOutputEnableDio( uint32_t dioNumber )
+{
+ // Check the arguments.
+ ASSERT( dioNumberLegal( dioNumber ));
+
+ // Return the output enable status for the specified DIO.
+ return (( HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) >> dioNumber ) & 1 );
+}
+
+//*****************************************************************************
+//
+//! \brief Gets the output enable setting of the specified DIOs.
+//!
+//! This function returns the output enable setting for multiple DIOs.
+//! The value returned is not shifted and hence matches the corresponding dioMask bits.
+//!
+//! \param dioMask is the bit-mask representation of the DIOs to return the output enable settings from.
+//! The parameter must be a bitwise OR'ed combination of the following:
+//! - \ref GPIO_DIO_0_MASK
+//! - ...
+//! - \ref GPIO_DIO_31_MASK
+//!
+//! \return Returns the output enable setting for multiple DIOs as a bit vector corresponding to the dioMask bits.
+//! - 0 : Corresponding DIO is configured with output disabled.
+//! - 1 : Corresponding DIO is configured with output enabled.
+//!
+//! \sa \ref GPIO_getOutputEnableDio(), \ref GPIO_setOutputEnableDio(), \ref GPIO_setOutputEnableMultiDio()
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+GPIO_getOutputEnableMultiDio( uint32_t dioMask )
+{
+ // Check the arguments.
+ ASSERT( dioMask & GPIO_DIO_ALL_MASK );
+
+ // Return the output enable value for the specified DIOs.
+ return ( HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) & dioMask );
+}
+
+//*****************************************************************************
+//
+//! \brief Sets output enable of a specific DIO.
+//!
+//! This function sets the GPIO output enable bit for the specified DIO.
+//! The DIO can be configured as either input or output under software control.
+//!
+//! \param dioNumber specifies the DIO to configure (0-31).
+//! \param outputEnableValue specifies the output enable setting of the specified DIO:
+//! - \ref GPIO_OUTPUT_DISABLE : DIO output is disabled.
+//! - \ref GPIO_OUTPUT_ENABLE : DIO output is enabled.
+//!
+//! \return None
+//!
+//! \sa \ref GPIO_setOutputEnableMultiDio(), \ref GPIO_getOutputEnableDio(), \ref GPIO_getOutputEnableMultiDio()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+GPIO_setOutputEnableDio( uint32_t dioNumber, uint32_t outputEnableValue )
+{
+ // Check the arguments.
+ ASSERT( dioNumberLegal( dioNumber ));
+ ASSERT(( outputEnableValue == GPIO_OUTPUT_DISABLE ) ||
+ ( outputEnableValue == GPIO_OUTPUT_ENABLE ) );
+
+ // Update the output enable bit for the specified DIO.
+ HWREGBITW( GPIO_BASE + GPIO_O_DOE31_0, dioNumber ) = outputEnableValue;
+}
+
+//*****************************************************************************
+//
+//! \brief Configures the output enable setting for all specified DIOs.
+//!
+//! This function configures the output enable setting for the specified DIOs.
+//! The output enable setting must be shifted so it matches the corresponding dioMask bits.
+//! The DIOs can be configured as either an input or output under software control.
+//!
+//! \note Note that this is a read-modify-write operation and hence not atomic.
+//!
+//! \param dioMask is the bit-mask representation of the DIOs on which to configure the
+//! output enable setting. The parameter must be a bitwise OR'ed combination of the following:
+//! - \ref GPIO_DIO_0_MASK
+//! - ...
+//! - \ref GPIO_DIO_31_MASK
+//! \param bitVectoredOutputEnable holds the output enable setting the corresponding DIO-bits:
+//! - 0 : Corresponding DIO is configured with output disabled.
+//! - 1 : Corresponding DIO is configured with output enabled.
+//!
+//! \return None
+//!
+//! \sa \ref GPIO_setOutputEnableDio(), \ref GPIO_getOutputEnableDio(), \ref GPIO_getOutputEnableMultiDio()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+GPIO_setOutputEnableMultiDio( uint32_t dioMask, uint32_t bitVectoredOutputEnable )
+{
+ // Check the arguments.
+ ASSERT( dioMask & GPIO_DIO_ALL_MASK );
+
+ HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) =
+ ( HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) & ~dioMask ) |
+ ( bitVectoredOutputEnable & dioMask );
+}
+
+//*****************************************************************************
+//
+//! \brief Gets the event status of a specific DIO.
+//!
+//! \param dioNumber specifies the DIO to get the event status from (0-31).
+//!
+//! \return Returns the current event status on the specified DIO.
+//! - 0 : Non-triggered event.
+//! - 1 : Triggered event.
+//!
+//! \sa \ref GPIO_getEventMultiDio(), \ref GPIO_clearEventDio(), \ref GPIO_clearEventMultiDio()
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+GPIO_getEventDio( uint32_t dioNumber )
+{
+ // Check the arguments.
+ ASSERT( dioNumberLegal( dioNumber ));
+
+ // Return the event status for the specified DIO.
+ return (( HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) >> dioNumber ) & 1 );
+}
+
+//*****************************************************************************
+//
+//! \brief Gets the event status of the specified DIOs.
+//!
+//! This function returns the event status for multiple DIOs.
+//! The value returned is not shifted and hence matches the corresponding dioMask bits.
+//!
+//! \param dioMask is the bit-mask representation of the DIOs to get the
+//! event status from (0-31).
+//! The parameter must be a bitwise OR'ed combination of the following:
+//! - \ref GPIO_DIO_0_MASK
+//! - ...
+//! - \ref GPIO_DIO_31_MASK
+//!
+//! \return Returns a bit vector with the current event status corresponding to the specified DIOs.
+//! - 0 : Corresponding DIO has no triggered event.
+//! - 1 : Corresponding DIO has a triggered event.
+//!
+//! \sa \ref GPIO_getEventDio(), \ref GPIO_clearEventDio(), \ref GPIO_clearEventMultiDio()
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+GPIO_getEventMultiDio( uint32_t dioMask )
+{
+ // Check the arguments.
+ ASSERT( dioMask & GPIO_DIO_ALL_MASK );
+
+ // Return the event status for the specified DIO.
+ return ( HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) & dioMask );
+}
+
+//*****************************************************************************
+//
+//! \brief Clears the IO event status of a specific DIO.
+//!
+//! \param dioNumber specifies the DIO on which to clear the event status (0-31).
+//!
+//! \return None
+//!
+//! \sa \ref GPIO_clearEventMultiDio(), \ref GPIO_getEventDio(), \ref GPIO_getEventMultiDio()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+GPIO_clearEventDio( uint32_t dioNumber )
+{
+ // Check the arguments.
+ ASSERT( dioNumberLegal( dioNumber ));
+
+ // Clear the event status for the specified DIO.
+ HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) = ( 1 << dioNumber );
+}
+
+//*****************************************************************************
+//
+//! \brief Clears the IO event status on the specified DIOs.
+//!
+//! \param dioMask is the bit-mask representation of the DIOs on which to
+//! clear the events status.
+//! The parameter must be a bitwise OR'ed combination of the following:
+//! - \ref GPIO_DIO_0_MASK
+//! - ...
+//! - \ref GPIO_DIO_31_MASK
+//!
+//! \return None
+//!
+//! \sa \ref GPIO_clearEventDio(), \ref GPIO_getEventDio(), \ref GPIO_getEventMultiDio()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+GPIO_clearEventMultiDio( uint32_t dioMask )
+{
+ // Check the arguments.
+ ASSERT( dioMask & GPIO_DIO_ALL_MASK );
+
+ // Clear the event status for the specified DIOs.
+ HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) = dioMask;
+}
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __GPIO_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/gpio_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/gpio_doc.h
new file mode 100644
index 0000000..bdee473
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/gpio_doc.h
@@ -0,0 +1,90 @@
+/******************************************************************************
+* Filename: gpio_doc.h
+* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016)
+* Revision: 45971
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+//! \addtogroup gpio_api
+//! @{
+//! \section sec_gpio Introduction
+//!
+//! The GPIO module allows software to control the pins of the device directly if the IOC module has
+//! been configured to route the GPIO signal to a physical pin (called DIO). Alternatively, pins can
+//! be hardware controlled by other peripheral modules. For more information about the IOC module,
+//! how to configure physical pins, and how to select between software controlled and hardware controlled,
+//! see the [IOC API](\ref ioc_api).
+//!
+//! The System CPU can access the GPIO module to read the value of any DIO of the device and if the IOC
+//! module has been configured such that one or more DIOs are GPIO controlled (software controlled) the
+//! System CPU can write these DIOs through the GPIO module.
+//!
+//! The IOC module can also be configured to generate events on edge detection and these events can be
+//! read and cleared in the GPIO module by the System CPU.
+//!
+//! \section sec_gpio_api API
+//!
+//! The API functions can be grouped like this:
+//!
+//! Set and get direction of DIO (output enable):
+//! - \ref GPIO_setOutputEnableDio()
+//! - \ref GPIO_setOutputEnableMultiDio()
+//! - \ref GPIO_getOutputEnableDio()
+//! - \ref GPIO_getOutputEnableMultiDio()
+//!
+//! Write DIO (requires IOC to be configured for GPIO usage):
+//! - \ref GPIO_writeDio()
+//! - \ref GPIO_writeMultiDio()
+//!
+//! Set, clear, or toggle DIO (requires IOC to be configured for GPIO usage):
+//! - \ref GPIO_setDio()
+//! - \ref GPIO_setMultiDio()
+//! - \ref GPIO_clearDio()
+//! - \ref GPIO_clearMultiDio()
+//! - \ref GPIO_toggleDio()
+//! - \ref GPIO_toggleMultiDio()
+//!
+//! Read DIO (even if IOC is NOT configured for GPIO usage; however, the DIO must be configured for input enable in IOC):
+//! - \ref GPIO_readDio()
+//! - \ref GPIO_readMultiDio()
+//!
+//! Read or clear events (even if IOC is NOT configured for GPIO usage; however, the DIO must be configured for input enable in IOC):
+//! - \ref GPIO_getEventDio()
+//! - \ref GPIO_getEventMultiDio()
+//! - \ref GPIO_clearEventDio()
+//! - \ref GPIO_clearEventMultiDio()
+//!
+//! The [IOC API](\ref ioc_api) provides two functions for easy configuration of DIOs as GPIO enabled using
+//! typical settings. They also serve as examples on how to configure the IOC and GPIO modules for GPIO usage:
+//! - \ref IOCPinTypeGpioInput()
+//! - \ref IOCPinTypeGpioOutput()
+//!
+//! @}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/group_analog_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/group_analog_doc.h
new file mode 100644
index 0000000..67422a5
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/group_analog_doc.h
@@ -0,0 +1,105 @@
+/******************************************************************************
+* Filename: group_analog_doc.h
+* Revised: 2016-08-30 14:34:13 +0200 (Tue, 30 Aug 2016)
+* Revision: 47080
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+//! \addtogroup analog_group
+//! @{
+//! \section sec_analog Introduction
+//!
+//! Access to registers in the analog domain of the device goes through master modules controlling slave
+//! modules which contain the actual registers. The master module is located in the digital domain of the
+//! device. The interfaces between master and slave modules are called ADI (Analog-to-Digital Interface)
+//! and DDI (Digital-to-Digital Interface) depending on the type of module to access and thus the slave
+//! modules are referred to as ADI slave and DDI slave.
+//!
+//! The ADI and DDI APIs provide access to these registers:
+//! - <a href="../register_descriptions/ANATOP_MMAP/ADI_2_REFSYS.html" target="_blank">ADI_2_REFSYS</a> : Reference System for generating reference voltages and reference currents.
+//! - Reference system control
+//! - SOC LDO control
+//! - <a href="../register_descriptions/ANATOP_MMAP/ADI_3_REFSYS.html" target="_blank">ADI_3_REFSYS</a> : Reference System for generating reference voltages and reference currents.
+//! - Reference system control
+//! - DC/DC control
+//! - <a href="../register_descriptions/ANATOP_MMAP/ADI_4_AUX.html" target="_blank">ADI_4_AUX</a> : Controlling analog peripherals of AUX.
+//! - Multiplexers
+//! - Current source
+//! - Comparators
+//! - ADCs
+//! - <a href="../register_descriptions/ANATOP_MMAP/DDI_0_OSC.html" target="_blank">DDI_0_OSC</a> : Controlling the oscillators (via AUX domain)
+//!
+//! The register descriptions of CPU memory map document the ADI/DDI masters. The register descriptions of
+//! analog memory map document the ADI/DDI slaves. The ADI/DDI APIs allow the programmer to focus on the
+//! slave registers of interest without being concerned with the ADI/DDI master part of the interface.
+//!
+//! Although the ADI/DDI APIs make the master "transparent" it can be useful to know a few details about
+//! the ADI/DDI protocol and how the master handles transactions as it can affect how the system CPU performs.
+//! - ADI protocol uses 8-bit write bus compared to 32-bit write bus in DDI. ADI protocol uses 4-bit read
+//! bus compared to 16-bit read bus in DDI. Hence a 32-bit read from an ADI register is translated into 8
+//! transactions in the ADI protocol.
+//! - One transaction on the ADI/DDI protocol takes several clock cycles for the master to complete.
+//! - ADI slave registers are 8-bit wide.
+//! - DDI slave registers are 32-bit wide.
+//! - ADI/DDI master supports multiple data width accesses seen from the system CPU
+//! (however, not all bit width accesses are supported by the APIs):
+//! - Read: 8, 16, 32-bit
+//! - Write
+//! - Direct (write, set, clear): 8, 16, 32-bit
+//! - Masked: 4, 8, 16-bit
+//!
+//! Making posted/buffered writes from the system CPU (default) to the ADI/DDI allows the system CPU to continue
+//! while the ADI/DDI master handles the transactions on the ADI/DDI protocol. If using non-posted/non-buffered
+//! writes the system CPU will wait for ADI/DDI master to complete the transactions to the slave before continuing
+//! execution.
+//!
+//! Reading from ADI/DDI requires that all transactions on the ADI/DDI protocol have completed before the system CPU
+//! receives the response thus the programmer must understand that the response time depends on the number of bytes
+//! read. However, due to the 'set', 'clear' and 'masked write' features of the ADI/DDI most writes can be done
+//! without the typical read-modify-write sequence thus reducing the need for reads to a minimum.
+//!
+//! Consequently, if making posted/buffered writes then the written value will not take effect in the
+//! analog domain until some point later in time. An alternative to non-posted/non-buffered writes - in order to make
+//! sure a written value has taken effect - is to read from the same ADI/DDI as the write as this will keep the system CPU
+//! waiting until both the write and the read have completed.
+//!
+//! \note
+//! Do NOT use masked write when writing bit fields spanning the "masked write boundary" i.e. the widest possible
+//! masked write that the protocol supports (ADI = 4 bits, DDI = 16 bits). This will put the device into a
+//! temporary state - which is potentially harmful to the device - as the bit field will be written over two transactions.
+//! Thus to use masked writes:
+//! - For ADI the bit field(s) must be within bit 0 to 3 (REG[3:0]) or bit 4 to 7 (REG[7:4]).
+//! - For DDI the bit field(s) must be within bit 0 to 15 (REG[15:0]) or bit 16 to 31 (REG[31:16]).
+//!
+//! \note
+//! If masked write is not allowed, a regular read-modify-write is necessary.
+//!
+//! @}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/group_aon_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/group_aon_doc.h
new file mode 100644
index 0000000..55cc2ea
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/group_aon_doc.h
@@ -0,0 +1,76 @@
+/******************************************************************************
+* Filename: group_aon_doc.h
+* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016)
+* Revision: 45971
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+//! \addtogroup aon_group
+//! @{
+//! \section sec_aon Introduction
+//!
+//! The Always-ON (AON) voltage domain contains the AUX power domain, AON power domain, and JTAG power domain.
+//! The AON API includes functions to access the AON power domain. For functions accessing the AUX power domain
+//! see the [AUX API](@ref aux_group).
+//!
+//! The AON power domain contains circuitry that is always enabled, except for the shutdown mode
+//! (digital supply is off), and the AON power domain is clocked at 32-kHz.
+//!
+//! The AON API accesses the AON registers through a common module called AON Interface (AON IF) which handles the
+//! actual transactions towards the much slower AON registers. Because accessing AON can cause a significant
+//! delay in terms of system CPU clock cycles it is important to understand the basics about how the AON IF
+//! operates. The following list describes a few of the most relevant properties of the AON IF seen from the system CPU:
+//! - \ti_bold{Shadow registers}: The system CPU actually accesses a set of "shadow registers" which are being synchronized to the AON registers
+//! by the AON IF every AON clock cycle.
+//! - Writing an AON register via AON IF can take up to one AON clock cycle before taking effect in the AON domain. However, the system CPU can
+//! continue executing without waiting for this.
+//! - The AON IF supports multiple writes within the same AON clock cycle thus several registers/bit fields can be synchronized simultaneously.
+//! - Reading from AON IF returns the value from last time the shadow registers were synchronized (if no writes to AON IF have occurred since)
+//! thus the value can be up to one AON clock cycle old.
+//! - Reading from AON IF after a write (but before synchronization has happened) will return the value from the shadow register
+//! and not the last value from the AON register. Thus doing multiple read-modify-writes within one AON clock cycle is supported.
+//! - \ti_bold{Read delay}: Due to an asynchronous interface to the AON IF, reading AON registers will generate a few wait cycles thus stalling
+//! the system CPU until the read completes. There is no delay on writes to AON IF if using posted/buffered writes.
+//! - \ti_bold{Synchronizing}: If it is required that a write to AON takes effect before continuing code execution it is possible to do a conditional "wait for
+//! synchronization" by calling \ref SysCtrlAonSync(). This will wait for any pending writes to synchronize.
+//! - \ti_bold{Updating}: It is also possible to do an unconditional "wait for synchronization", in case a new read
+//! value is required, by calling \ref SysCtrlAonUpdate(). This is typically used after wake-up to make sure the AON IF has been
+//! synchronized at least once before reading the values.
+//!
+//! Below are a few guidelines to write efficient code for AON access based on the properties of the interface to the AON registers.
+//! - Avoid synchronizing unless required by the application. If synchronization is needed then try to group/arrange AON writes to
+//! minimize the number of required synchronizations.
+//! - If modifying several bit fields within a single AON register it is slightly faster to do a single read, modify the bit fields,
+//! and then write it back rather than doing multiple independent read-modify-writes (due to the read delay).
+//! - Using posted/buffered writes to AON (default) lets the system CPU continue execution immediately. Using non-posted/non-buffered
+//! writes will generate a delay similar to a read access.
+//!
+//! @}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/group_aux_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/group_aux_doc.h
new file mode 100644
index 0000000..6efc1c6
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/group_aux_doc.h
@@ -0,0 +1,58 @@
+/******************************************************************************
+* Filename: group_aux_doc.h
+* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016)
+* Revision: 45971
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+//! \addtogroup aux_group
+//! @{
+//! \section sec_aux Introduction
+//!
+//! The AUX is a collective description of all the analog peripherals (ADC, comparators, and current source) and
+//! the digital modules in the AUX power domain (AUX_PD) such as the sensor controller, timers, time-to-digital
+//! converter, etc. AUX_PD is located within the AON voltage domain of the device.
+//!
+//! The sensor controller has the ability to
+//! do its own power and clock management of AUX_PD, independently of the MCU domain. The sensor
+//! controller can also continue doing tasks while the MCU subsystem is powered down, but with limited
+//! resources compared to the larger MCU domain.
+//!
+//! The AUX power domain is connected to the MCU system through an asynchronous interface, ensuring
+//! that all modules connected to the AUX bus are accessible from the system CPU.
+//! Accessing the analog peripherals from the system CPU must be done by using TI-provided
+//! drivers to ensure proper control of power management.
+//!
+//! \note To ease development of program code running on the sensor controller, TI provides a tool
+//! chain for writing software for the controller, Sensor Controller Studio (SCS), which is a fully
+//! integrated tool consisting of an IDE, compiler, assembler, and linker.
+//!
+//! @}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2c.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2c.c
new file mode 100644
index 0000000..0d254fb
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2c.c
@@ -0,0 +1,172 @@
+/******************************************************************************
+* Filename: i2c.c
+* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017)
+* Revision: 48852
+*
+* Description: Driver for the I2C module
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "i2c.h"
+
+//*****************************************************************************
+//
+// Handle support for DriverLib in ROM:
+// This section will undo prototype renaming made in the header file
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #undef I2CMasterInitExpClk
+ #define I2CMasterInitExpClk NOROM_I2CMasterInitExpClk
+ #undef I2CMasterErr
+ #define I2CMasterErr NOROM_I2CMasterErr
+ #undef I2CIntRegister
+ #define I2CIntRegister NOROM_I2CIntRegister
+ #undef I2CIntUnregister
+ #define I2CIntUnregister NOROM_I2CIntUnregister
+#endif
+
+//*****************************************************************************
+//
+// Initializes the I2C Master block
+//
+//*****************************************************************************
+void
+I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk,
+ bool bFast)
+{
+ uint32_t ui32SCLFreq;
+ uint32_t ui32TPR;
+
+ // Check the arguments.
+ ASSERT(I2CBaseValid(ui32Base));
+
+ // Must enable the device before doing anything else.
+ I2CMasterEnable(I2C0_BASE);
+
+ // Get the desired SCL speed.
+ if(bFast == true)
+ {
+ ui32SCLFreq = 400000;
+ }
+ else
+ {
+ ui32SCLFreq = 100000;
+ }
+
+ // Compute the clock divider that achieves the fastest speed less than or
+ // equal to the desired speed. The numerator is biased to favor a larger
+ // clock divider so that the resulting clock is always less than or equal
+ // to the desired clock, never greater.
+ ui32TPR = ((ui32I2CClk + (2 * 10 * ui32SCLFreq) - 1) / (2 * 10 * ui32SCLFreq)) - 1;
+ HWREG(I2C0_BASE + I2C_O_MTPR) = ui32TPR;
+}
+
+//*****************************************************************************
+//
+// Gets the error status of the I2C Master module
+//
+//*****************************************************************************
+uint32_t
+I2CMasterErr(uint32_t ui32Base)
+{
+ uint32_t ui32Err;
+
+ // Check the arguments.
+ ASSERT(I2CBaseValid(ui32Base));
+
+ // Get the raw error state.
+ ui32Err = HWREG(I2C0_BASE + I2C_O_MSTAT);
+
+ // If the I2C master is busy, then all the other status bits are invalid,
+ // and there is no error to report.
+ if(ui32Err & I2C_MSTAT_BUSY)
+ {
+ return(I2C_MASTER_ERR_NONE);
+ }
+
+ // Check for errors.
+ if(ui32Err & (I2C_MSTAT_ERR | I2C_MSTAT_ARBLST))
+ {
+ return(ui32Err & (I2C_MSTAT_ARBLST | I2C_MSTAT_DATACK_N | I2C_MSTAT_ADRACK_N));
+ }
+ else
+ {
+ return(I2C_MASTER_ERR_NONE);
+ }
+}
+
+//*****************************************************************************
+//
+// Registers an interrupt handler for the I2C module
+//
+//*****************************************************************************
+void
+I2CIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
+{
+ uint32_t ui32Int;
+
+ // Check the arguments.
+ ASSERT(I2CBaseValid(ui32Base));
+
+ // Get the interrupt number.
+ ui32Int = INT_I2C_IRQ;
+
+ // Register the interrupt handler, returning an error if an error occurs.
+ IntRegister(ui32Int, pfnHandler);
+
+ // Enable the I2C interrupt.
+ IntEnable(ui32Int);
+}
+
+//*****************************************************************************
+//
+// Unregisters an interrupt handler for the I2C module
+//
+//*****************************************************************************
+void
+I2CIntUnregister(uint32_t ui32Base)
+{
+ uint32_t ui32Int;
+
+ // Check the arguments.
+ ASSERT(I2CBaseValid(ui32Base));
+
+ // Get the interrupt number.
+ ui32Int = INT_I2C_IRQ;
+
+ // Disable the interrupt.
+ IntDisable(ui32Int);
+
+ // Unregister the interrupt handler.
+ IntUnregister(ui32Int);
+}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2c.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2c.h
new file mode 100644
index 0000000..4ef0930
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2c.h
@@ -0,0 +1,974 @@
+/******************************************************************************
+* Filename: i2c.h
+* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017)
+* Revision: 49048
+*
+* Description: Defines and prototypes for the I2C.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup peripheral_group
+//! @{
+//! \addtogroup i2c_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __I2C_H__
+#define __I2C_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "../inc/hw_types.h"
+#include "../inc/hw_ints.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_i2c.h"
+#include "../inc/hw_sysctl.h"
+#include "debug.h"
+#include "interrupt.h"
+#include "cpu.h"
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// This section renames all functions that are not "static inline", so that
+// calling these functions will default to implementation in flash. At the end
+// of this file a second renaming will change the defaults to implementation in
+// ROM for available functions.
+//
+// To force use of the implementation in flash, e.g. for debugging:
+// - Globally: Define DRIVERLIB_NOROM at project level
+// - Per function: Use prefix "NOROM_" when calling the function
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #define I2CMasterInitExpClk NOROM_I2CMasterInitExpClk
+ #define I2CMasterErr NOROM_I2CMasterErr
+ #define I2CIntRegister NOROM_I2CIntRegister
+ #define I2CIntUnregister NOROM_I2CIntUnregister
+#endif
+
+//*****************************************************************************
+//
+// I2C Master commands
+//
+//*****************************************************************************
+#define I2C_MASTER_CMD_SINGLE_SEND \
+ 0x00000007
+#define I2C_MASTER_CMD_SINGLE_RECEIVE \
+ 0x00000007
+#define I2C_MASTER_CMD_BURST_SEND_START \
+ 0x00000003
+#define I2C_MASTER_CMD_BURST_SEND_CONT \
+ 0x00000001
+#define I2C_MASTER_CMD_BURST_SEND_FINISH \
+ 0x00000005
+#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \
+ 0x00000004
+#define I2C_MASTER_CMD_BURST_RECEIVE_START \
+ 0x0000000b
+#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \
+ 0x00000009
+#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \
+ 0x00000005
+#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \
+ 0x00000004
+
+//*****************************************************************************
+//
+// I2C Master error status
+//
+//*****************************************************************************
+#define I2C_MASTER_ERR_NONE 0
+#define I2C_MASTER_ERR_ADDR_ACK 0x00000004
+#define I2C_MASTER_ERR_DATA_ACK 0x00000008
+#define I2C_MASTER_ERR_ARB_LOST 0x00000010
+
+//*****************************************************************************
+//
+// I2C Slave action requests
+//
+//*****************************************************************************
+#define I2C_SLAVE_ACT_NONE 0
+#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data
+#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data
+#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte
+
+//*****************************************************************************
+//
+// I2C Slave interrupts
+//
+//*****************************************************************************
+#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt.
+#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt.
+#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt.
+
+//*****************************************************************************
+//
+// API Functions and prototypes
+//
+//*****************************************************************************
+
+#ifdef DRIVERLIB_DEBUG
+//*****************************************************************************
+//
+//! \internal
+//!
+//! \brief Checks an I2C base address.
+//!
+//! This function determines if a I2C port base address is valid.
+//!
+//! \param ui32Base is the base address of the I2C port.
+//!
+//! \return Returns \c true if the base address is valid and \c false
+//! otherwise
+//
+//*****************************************************************************
+static bool
+I2CBaseValid(uint32_t ui32Base)
+{
+ return(ui32Base == I2C0_BASE);
+}
+#endif
+
+//*****************************************************************************
+//
+//! \brief Initializes the I2C Master block.
+//!
+//! This function initializes operation of the I2C Master block. Upon
+//! successful initialization of the I2C block, this function will have set the
+//! bus speed for the master, and will have enabled the I2C Master block.
+//!
+//! If the parameter \c bFast is \c true, then the master block will be set up
+//! to transfer data at 400 kbps; otherwise, it will be set up to transfer data
+//! at 100 kbps.
+//!
+//!
+//! \param ui32Base is the base address of the I2C module.
+//! \param ui32I2CClk is the rate of the clock supplied to the I2C module.
+//! \param bFast set up for fast data transfers.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk,
+ bool bFast);
+
+//*****************************************************************************
+//
+//! \brief Controls the state of the I2C Master module.
+//!
+//! This function is used to control the state of the Master module send and
+//! receive operations.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//! \param ui32Cmd is the command to be issued by the I2C Master module
+//! The parameter can be one of the following values:
+//! - \ref I2C_MASTER_CMD_SINGLE_SEND
+//! - \ref I2C_MASTER_CMD_SINGLE_RECEIVE
+//! - \ref I2C_MASTER_CMD_BURST_SEND_START
+//! - \ref I2C_MASTER_CMD_BURST_SEND_CONT
+//! - \ref I2C_MASTER_CMD_BURST_SEND_FINISH
+//! - \ref I2C_MASTER_CMD_BURST_SEND_ERROR_STOP
+//! - \ref I2C_MASTER_CMD_BURST_RECEIVE_START
+//! - \ref I2C_MASTER_CMD_BURST_RECEIVE_CONT
+//! - \ref I2C_MASTER_CMD_BURST_RECEIVE_FINISH
+//! - \ref I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd)
+{
+ // Check the arguments.
+ ASSERT(I2CBaseValid(ui32Base));
+ ASSERT((ui32Cmd == I2C_MASTER_CMD_SINGLE_SEND) ||
+ // (ui32Cmd == I2C_MASTER_CMD_SINGLE_RECEIVE) || -> Equal to SINGLE_SEND
+ (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_START) ||
+ (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_CONT) ||
+ (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_FINISH) ||
+ (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_ERROR_STOP) ||
+ (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_START) ||
+ (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_CONT) ||
+ (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_FINISH) ||
+ (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP));
+
+ // Send the command.
+ HWREG(I2C0_BASE + I2C_O_MCTRL) = ui32Cmd;
+
+ // Delay minimum four cycles in order to ensure that the I2C_O_MSTAT
+ // register has been correctly updated before function exit
+ CPUdelay(2);
+}
+
+//*****************************************************************************
+//
+//! \brief Sets the address that the I2C Master will place on the bus.
+//!
+//! This function will set the address that the I2C Master will place on the
+//! bus when initiating a transaction. When the \e bReceive parameter is set
+//! to \b true, the address will indicate that the I2C Master is initiating a
+//! read from the slave; otherwise the address will indicate that the I2C
+//! Master is initiating a write to the slave.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//! \param ui8SlaveAddr is a 7-bit slave address
+//! \param bReceive flag indicates the type of communication with the slave.
+//! - \c true : I2C Master is initiating a read from the slave.
+//! - \c false : I2C Master is initiating a write to the slave.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+I2CMasterSlaveAddrSet(uint32_t ui32Base, uint8_t ui8SlaveAddr,
+ bool bReceive)
+{
+ // Check the arguments.
+ ASSERT(I2CBaseValid(ui32Base));
+ ASSERT(!(ui8SlaveAddr & 0x80));
+
+ // Set the address of the slave with which the master will communicate.
+ HWREG(I2C0_BASE + I2C_O_MSA) = (ui8SlaveAddr << 1) | bReceive;
+}
+
+//*****************************************************************************
+//
+//! \brief Enables the I2C Master block.
+//!
+//! This will enable operation of the I2C Master block.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+I2CMasterEnable(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(I2CBaseValid(ui32Base));
+
+ // Enable the clock for the master.
+ HWREGBITW(I2C0_BASE + I2C_O_MCR, I2C_MCR_MFE_BITN) = 1;
+
+ // Enable the master block.
+ HWREG(I2C0_BASE + I2C_O_MCTRL) = I2C_MCTRL_RUN;
+}
+
+//*****************************************************************************
+//
+//! \brief Disables the I2C master block.
+//!
+//! This will disable operation of the I2C master block.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+I2CMasterDisable(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(I2CBaseValid(ui32Base));
+
+ // Disable the master block.
+ HWREG(I2C0_BASE + I2C_O_MCTRL) = 0;
+
+ // Disable the clock for the master.
+ HWREGBITW(I2C0_BASE + I2C_O_MCR, I2C_MCR_MFE_BITN) = 0;
+}
+
+//*****************************************************************************
+//
+//! \brief Indicates whether or not the I2C Master is busy.
+//!
+//! This function returns an indication of whether or not the I2C Master is
+//! busy transmitting or receiving data.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//!
+//! \return Returns status of I2C Master:
+//! - \c true : I2C Master is busy.
+//! - \c false : I2C Master is not busy.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+I2CMasterBusy(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(I2CBaseValid(ui32Base));
+
+ // Return the busy status.
+ if(HWREG(I2C0_BASE + I2C_O_MSTAT) & I2C_MSTAT_BUSY)
+ {
+ return(true);
+ }
+ else
+ {
+ return(false);
+ }
+}
+
+//*****************************************************************************
+//
+//! \brief Indicates whether or not the I2C bus is busy.
+//!
+//! This function returns an indication of whether or not the I2C bus is busy.
+//! This function can be used in a multi-master environment to determine if
+//! another master is currently using the bus.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//!
+//! \return Returns status of the I2C bus:
+//! - \c true : I2C bus is busy.
+//! - \c false : I2C bus is not busy.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+I2CMasterBusBusy(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(I2CBaseValid(ui32Base));
+
+ // Return the bus busy status.
+ if(HWREG(I2C0_BASE + I2C_O_MSTAT) & I2C_MSTAT_BUSBSY)
+ {
+ return(true);
+ }
+ else
+ {
+ return(false);
+ }
+}
+
+//*****************************************************************************
+//
+//! \brief Receives a byte that has been sent to the I2C Master.
+//!
+//! This function reads a byte of data from the I2C Master Data Register.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//!
+//! \return Returns the byte received from by the I2C Master, cast as an
+//! uint32_t.
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+I2CMasterDataGet(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(I2CBaseValid(ui32Base));
+
+ // Read a byte.
+ return(HWREG(I2C0_BASE + I2C_O_MDR));
+}
+
+//*****************************************************************************
+//
+//! \brief Transmits a byte from the I2C Master.
+//!
+//! This function will place the supplied data into I2C Master Data Register.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//! \param ui8Data is the data to be transmitted by the I2C Master
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data)
+{
+ // Check the arguments.
+ ASSERT(I2CBaseValid(ui32Base));
+
+ // Write the byte.
+ HWREG(I2C0_BASE + I2C_O_MDR) = ui8Data;
+}
+
+//*****************************************************************************
+//
+//! \brief Gets the error status of the I2C Master module.
+//!
+//! This function is used to obtain the error status of the Master module send
+//! and receive operations.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//!
+//! \return Returns the error status of the Master module:
+//! - \ref I2C_MASTER_ERR_NONE
+//! - \ref I2C_MASTER_ERR_ADDR_ACK
+//! - \ref I2C_MASTER_ERR_DATA_ACK
+//! - \ref I2C_MASTER_ERR_ARB_LOST
+//
+//*****************************************************************************
+extern uint32_t I2CMasterErr(uint32_t ui32Base);
+
+//*****************************************************************************
+//
+//! \brief Enables the I2C Master interrupt.
+//!
+//! Enables the I2C Master interrupt source.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+I2CMasterIntEnable(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(I2CBaseValid(ui32Base));
+
+ // Enable the master interrupt.
+ HWREG(I2C0_BASE + I2C_O_MIMR) = I2C_MIMR_IM;
+}
+
+//*****************************************************************************
+//
+//! \brief Disables the I2C Master interrupt.
+//!
+//! Disables the I2C Master interrupt source.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+I2CMasterIntDisable(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(I2CBaseValid(ui32Base));
+
+ // Disable the master interrupt.
+ HWREG(I2C0_BASE + I2C_O_MIMR) = 0;
+}
+
+//*****************************************************************************
+//
+//! \brief Clears I2C Master interrupt sources.
+//!
+//! The I2C Master interrupt source is cleared, so that it no longer asserts.
+//! This must be done in the interrupt handler to keep it from being called
+//! again immediately upon exit.
+//!
+//! \note Due to write buffers and synchronizers in the system it may take several
+//! clock cycles from a register write clearing an event in a module and until the
+//! event is actually cleared in the NVIC of the system CPU. It is recommended to
+//! clear the event source early in the interrupt service routine (ISR) to allow
+//! the event clear to propagate to the NVIC before returning from the ISR.
+//! At the same time, an early event clear allows new events of the same type to be
+//! pended instead of ignored if the event is cleared later in the ISR.
+//! It is the responsibility of the programmer to make sure that enough time has passed
+//! before returning from the ISR to avoid false re-triggering of the cleared event.
+//! A simple, although not necessarily optimal, way of clearing an event before
+//! returning from the ISR is:
+//! -# Write to clear event (interrupt source). (buffered write)
+//! -# Dummy read from the event source module. (making sure the write has propagated)
+//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers)
+//!
+//! \param ui32Base is the base address of the I2C module.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+I2CMasterIntClear(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(I2CBaseValid(ui32Base));
+
+ // Clear the I2C master interrupt source.
+ HWREG(I2C0_BASE + I2C_O_MICR) = I2C_MICR_IC;
+}
+
+//*****************************************************************************
+//
+//! \brief Gets the current I2C Master interrupt status.
+//!
+//! This returns the interrupt status for the I2C Master module. Either the
+//! raw interrupt status or the status of interrupts that are allowed to
+//! reflect to the processor can be returned.
+//!
+//! \param ui32Base is the base address of the I2C Master module.
+//! \param bMasked selects either raw or masked interrupt status.
+//! - \c false : Raw interrupt status is requested.
+//! - \c true : Masked interrupt status is requested.
+//!
+//! \return Returns the current interrupt status.
+//! - \c true : Active.
+//! - \c false : Not active.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+I2CMasterIntStatus(uint32_t ui32Base, bool bMasked)
+{
+ // Check the arguments.
+ ASSERT(I2CBaseValid(ui32Base));
+
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ if(bMasked)
+ {
+ return((HWREG(I2C0_BASE + I2C_O_MMIS)) ? true : false);
+ }
+ else
+ {
+ return((HWREG(I2C0_BASE + I2C_O_MRIS)) ? true : false);
+ }
+}
+
+//*****************************************************************************
+//
+//! \brief Enables the I2C Slave block.
+//!
+//! This will enable operation of the I2C Slave block.
+//!
+//! \param ui32Base is the base address of the I2C Slave module.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+I2CSlaveEnable(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(I2CBaseValid(ui32Base));
+
+ // Enable the clock to the slave block.
+ HWREGBITW(I2C0_BASE + I2C_O_MCR, I2C_MCR_SFE_BITN) = 1;
+
+ // Enable the slave.
+ HWREG(I2C0_BASE + I2C_O_SCTL) = I2C_SCTL_DA;
+}
+
+//*****************************************************************************
+//
+//! \brief Initializes the I2C Slave block.
+//!
+//! This function initializes operation of the I2C Slave block. Upon
+//! successful initialization of the I2C blocks, this function will have set
+//! the slave address and have enabled the I2C Slave block.
+//!
+//! The parameter \c ui8SlaveAddr is the value that will be compared against the
+//! slave address sent by an I2C master.
+//!
+//! \param ui32Base is the base address of the I2C Slave module.
+//! \param ui8SlaveAddr is the 7-bit slave address.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr)
+{
+ // Check the arguments.
+ ASSERT(I2CBaseValid(ui32Base));
+ ASSERT(!(ui8SlaveAddr & 0x80));
+
+ // Must enable the device before doing anything else.
+ I2CSlaveEnable(I2C0_BASE);
+
+ // Set up the slave address.
+ HWREG(I2C0_BASE + I2C_O_SOAR) = ui8SlaveAddr;
+}
+
+//*****************************************************************************
+//
+//! \brief Sets the I2C slave address.
+//!
+//! This function writes the specified slave address.
+//!
+//! \param ui32Base is the base address of the I2C Slave module.
+//! \param ui8SlaveAddr is the 7-bit slave address
+//!
+//! \return None.
+//
+//*****************************************************************************
+__STATIC_INLINE void
+I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8SlaveAddr)
+{
+ // Check the arguments.
+ ASSERT(I2CBaseValid(ui32Base));
+ ASSERT(!(ui8SlaveAddr & 0x80));
+
+ // Set up the primary slave address.
+ HWREG(I2C0_BASE + I2C_O_SOAR) = ui8SlaveAddr;
+}
+
+//*****************************************************************************
+//
+//! \brief Disables the I2C slave block.
+//!
+//! This will disable operation of the I2C slave block.
+//!
+//! \param ui32Base is the base address of the I2C Slave module.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+I2CSlaveDisable(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(I2CBaseValid(ui32Base));
+
+ // Disable the slave.
+ HWREG(I2C0_BASE + I2C_O_SCTL) = 0x0;
+
+ // Disable the clock to the slave block.
+ HWREGBITW(I2C0_BASE + I2C_O_MCR, I2C_MCR_SFE_BITN) = 0;
+}
+
+//*****************************************************************************
+//
+//! \brief Gets the I2C Slave module status.
+//!
+//! This function will return the action requested from a master, if any.
+//!
+//! \param ui32Base is the base address of the I2C Slave module.
+//!
+//! \return Returns the status of the I2C Slave module:
+//! - \ref I2C_SLAVE_ACT_NONE : No action has been requested of the I2C Slave module.
+//! - \ref I2C_SLAVE_ACT_RREQ : An I2C master has sent data to the I2C Slave module.
+//! - \ref I2C_SLAVE_ACT_TREQ : An I2C master has requested that the I2C Slave module send data.
+//! - \ref I2C_SLAVE_ACT_RREQ_FBR : An I2C master has sent data to the I2C slave
+//! and the first byte following the slave's own address has been received.
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+I2CSlaveStatus(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(I2CBaseValid(ui32Base));
+
+ // Return the slave status.
+ return(HWREG(I2C0_BASE + I2C_O_SSTAT));
+}
+
+//*****************************************************************************
+//
+//! \brief Receives a byte that has been sent to the I2C Slave.
+//!
+//! This function reads a byte of data from the I2C Slave Data Register.
+//!
+//! \param ui32Base is the base address of the I2C Slave module.
+//!
+//! \return Returns the byte received from by the I2C Slave, cast as an
+//! uint32_t.
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+I2CSlaveDataGet(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(I2CBaseValid(ui32Base));
+
+ // Read a byte.
+ return(HWREG(I2C0_BASE + I2C_O_SDR));
+}
+
+//*****************************************************************************
+//
+//! \brief Transmits a byte from the I2C Slave.
+//!
+//! This function will place the supplied data into I2C Slave Data Register.
+//!
+//! \param ui32Base is the base address of the I2C Slave module.
+//! \param ui8Data data to be transmitted from the I2C Slave.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data)
+{
+ // Check the arguments.
+ ASSERT(I2CBaseValid(ui32Base));
+
+ // Write the byte.
+ HWREG(I2C0_BASE + I2C_O_SDR) = ui8Data;
+}
+
+//*****************************************************************************
+//
+//! \brief Enables individual I2C Slave interrupt sources.
+//!
+//! Enables the indicated I2C Slave interrupt sources. Only the sources that
+//! are enabled can be reflected to the processor interrupt; disabled sources
+//! have no effect on the processor.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//! \param ui32IntFlags is the bit mask of the slave interrupt sources to be enabled.
+//! The parameter is the bitwise OR of any of the following:
+//! - \ref I2C_SLAVE_INT_STOP
+//! - \ref I2C_SLAVE_INT_START
+//! - \ref I2C_SLAVE_INT_DATA
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+I2CSlaveIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ uint32_t ui32Val;
+
+ // Check the arguments.
+ ASSERT(I2CBaseValid(ui32Base));
+ ASSERT(ui32IntFlags & (I2C_SLAVE_INT_STOP | I2C_SLAVE_INT_START |
+ I2C_SLAVE_INT_DATA));
+
+ // Enable the slave interrupt.
+ ui32Val = HWREG(I2C0_BASE + I2C_O_SIMR);
+ ui32Val |= ui32IntFlags;
+ HWREG(I2C0_BASE + I2C_O_SIMR) = ui32Val;
+}
+
+//*****************************************************************************
+//
+//! \brief Disables individual I2C Slave interrupt sources.
+//!
+//! Disables the indicated I2C Slave interrupt sources. Only the sources that
+//! are enabled can be reflected to the processor interrupt; disabled sources
+//! have no effect on the processor.
+//!
+//! \param ui32Base is the base address of the I2C Slave module.
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled.
+//! The parameter is the bitwise OR of any of the following:
+//! - \ref I2C_SLAVE_INT_STOP
+//! - \ref I2C_SLAVE_INT_START
+//! - \ref I2C_SLAVE_INT_DATA
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+I2CSlaveIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ uint32_t ui32Val;
+
+ // Check the arguments.
+ ASSERT(I2CBaseValid(ui32Base));
+ ASSERT(ui32IntFlags & (I2C_SLAVE_INT_STOP | I2C_SLAVE_INT_START |
+ I2C_SLAVE_INT_DATA));
+
+ // Disable the slave interrupt.
+ ui32Val = HWREG(I2C0_BASE + I2C_O_SIMR);
+ ui32Val &= ~ui32IntFlags;
+ HWREG(I2C0_BASE + I2C_O_SIMR) = ui32Val;
+}
+
+//*****************************************************************************
+//
+//! \brief Clears I2C Slave interrupt sources.
+//!
+//! The specified I2C Slave interrupt sources are cleared, so that they no
+//! longer assert. This must be done in the interrupt handler to keep it from
+//! being called again immediately upon exit.
+//!
+//! \note Due to write buffers and synchronizers in the system it may take several
+//! clock cycles from a register write clearing an event in a module and until the
+//! event is actually cleared in the NVIC of the system CPU. It is recommended to
+//! clear the event source early in the interrupt service routine (ISR) to allow
+//! the event clear to propagate to the NVIC before returning from the ISR.
+//! At the same time, an early event clear allows new events of the same type to be
+//! pended instead of ignored if the event is cleared later in the ISR.
+//! It is the responsibility of the programmer to make sure that enough time has passed
+//! before returning from the ISR to avoid false re-triggering of the cleared event.
+//! A simple, although not necessarily optimal, way of clearing an event before
+//! returning from the ISR is:
+//! -# Write to clear event (interrupt source). (buffered write)
+//! -# Dummy read from the event source module. (making sure the write has propagated)
+//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers)
+//!
+//! \param ui32Base is the base address of the I2C module.
+//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared.
+//! The parameter is the bitwise OR of any of the following:
+//! - \ref I2C_SLAVE_INT_STOP
+//! - \ref I2C_SLAVE_INT_START
+//! - \ref I2C_SLAVE_INT_DATA
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+I2CSlaveIntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ // Check the arguments.
+ ASSERT(I2CBaseValid(ui32Base));
+
+ // Clear the I2C slave interrupt source.
+ HWREG(I2C0_BASE + I2C_O_SICR) = ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! \brief Gets the current I2C Slave interrupt status.
+//!
+//! This returns the interrupt status for the I2C Slave module. Either the raw
+//! interrupt status or the status of interrupts that are allowed to reflect to
+//! the processor can be returned.
+//!
+//! \param ui32Base is the base address of the I2C Slave module.
+//! \param bMasked selects either raw or masked interrupt status.
+//! - \c false : Raw interrupt status is requested.
+//! - \c true : Masked interrupt status is requested.
+//!
+//! \return Returns the current interrupt status as an OR'ed combination of:
+//! - \ref I2C_SLAVE_INT_STOP
+//! - \ref I2C_SLAVE_INT_START
+//! - \ref I2C_SLAVE_INT_DATA
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked)
+{
+ // Check the arguments.
+ ASSERT(I2CBaseValid(ui32Base));
+
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ if(bMasked)
+ {
+ return(HWREG(I2C0_BASE + I2C_O_SMIS));
+ }
+ else
+ {
+ return(HWREG(I2C0_BASE + I2C_O_SRIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! \brief Registers an interrupt handler for the I2C module in the dynamic interrupt table.
+//!
+//! \note Only use this function if you want to use the dynamic vector table (in SRAM)!
+//!
+//! This function registers a function as the interrupt handler for a specific
+//! interrupt and enables the corresponding interrupt in the interrupt controller.
+//!
+//! Specific I2C interrupts must be enabled via \ref I2CMasterIntEnable() and
+//! \ref I2CSlaveIntEnable(). If necessary, it is the interrupt handler's
+//! responsibility to clear the interrupt source via \ref I2CMasterIntClear() and
+//! \ref I2CSlaveIntClear().
+//!
+//! \param ui32Base is the base address of the I2C Master module.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! I2C interrupt occurs.
+//!
+//! \return None
+//!
+//! \sa \ref IntRegister() for important information about registering interrupt
+//! handlers.
+//
+//*****************************************************************************
+extern void I2CIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
+
+//*****************************************************************************
+//
+//! \brief Unregisters an interrupt handler for the I2C module in the dynamic interrupt table.
+//!
+//! This function will clear the handler to be called when an I2C interrupt
+//! occurs. This will also mask off the interrupt in the interrupt controller
+//! so that the interrupt handler no longer is called.
+//!
+//! \param ui32Base is the base address of the I2C Master module.
+//!
+//! \return None
+//!
+//! \sa \brief IntRegister() for important information about registering interrupt
+//! handlers.
+//
+//*****************************************************************************
+extern void I2CIntUnregister(uint32_t ui32Base);
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// Redirect to implementation in ROM when available.
+//
+//*****************************************************************************
+#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
+ #include "../driverlib/rom.h"
+ #ifdef ROM_I2CMasterInitExpClk
+ #undef I2CMasterInitExpClk
+ #define I2CMasterInitExpClk ROM_I2CMasterInitExpClk
+ #endif
+ #ifdef ROM_I2CMasterErr
+ #undef I2CMasterErr
+ #define I2CMasterErr ROM_I2CMasterErr
+ #endif
+ #ifdef ROM_I2CIntRegister
+ #undef I2CIntRegister
+ #define I2CIntRegister ROM_I2CIntRegister
+ #endif
+ #ifdef ROM_I2CIntUnregister
+ #undef I2CIntUnregister
+ #define I2CIntUnregister ROM_I2CIntUnregister
+ #endif
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __I2C_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2c_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2c_doc.h
new file mode 100644
index 0000000..05298e0
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2c_doc.h
@@ -0,0 +1,162 @@
+/******************************************************************************
+* Filename: i2c_doc.h
+* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016)
+* Revision: 45971
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+//! \addtogroup i2c_api
+//! @{
+//! \section sec_i2c Introduction
+//!
+//! The Inter-Integrated Circuit (\i2c) API provides a set of functions for using
+//! the \ti_device \i2c master and slave module. Functions are provided to perform
+//! the following actions:
+//! - Initialize the \i2c module.
+//! - Send and receive data.
+//! - Obtain status.
+//! - Manage interrupts for the \i2c module.
+//!
+//! The \i2c master and slave module provide the ability to communicate to other IC
+//! devices over an \i2c bus. The \i2c bus is specified to support devices that can
+//! both transmit and receive (write and read) data. Also, devices on the \i2c bus
+//! can be designated as either a master or a slave. The \ti_device \i2c module
+//! supports both sending and receiving data as either a master or a slave, and also
+//! support the simultaneous operation as both a master and a slave. Finally, the
+//! \ti_device \i2c module can operate at two speeds: standard (100 kb/s) and fast
+//! (400 kb/s).
+//!
+//! The master and slave \i2c module can generate interrupts. The \i2c master
+//! module generates interrupts when a transmit or receive operation
+//! completes (or aborts due to an error).
+//! The \i2c slave module can generate interrupts when data is
+//! sent or requested by a master and when a START or STOP condition is present.
+//!
+//! \section sec_i2c_master Master Operations
+//!
+//! When using this API to drive the \i2c master module, the user must first
+//! initialize the \i2c master module with a call to \ref I2CMasterInitExpClk(). This
+//! function sets the bus speed and enables the master module.
+//!
+//! The user may transmit or receive data after the successful initialization of
+//! the \i2c master module. Data is transferred by first setting the slave address
+//! using \ref I2CMasterSlaveAddrSet(). This function is also used to define whether
+//! the transfer is a send (a write to the slave from the master) or a receive (a
+//! read from the slave by the master). Then, if connected to an \i2c bus that has
+//! multiple masters, the \ti_device \i2c master must first call \ref I2CMasterBusBusy()
+//! before trying to initiate the desired transaction. After determining that
+//! the bus is not busy, if trying to send data, the user must call the
+//! \ref I2CMasterDataPut() function. The transaction can then be initiated on the bus
+//! by calling the \ref I2CMasterControl() function with any of the following commands:
+//! - \ref I2C_MASTER_CMD_SINGLE_SEND
+//! - \ref I2C_MASTER_CMD_SINGLE_RECEIVE
+//! - \ref I2C_MASTER_CMD_BURST_SEND_START
+//! - \ref I2C_MASTER_CMD_BURST_RECEIVE_START
+//!
+//! Any of these commands result in the master arbitrating for the bus,
+//! driving the start sequence onto the bus, and sending the slave address and
+//! direction bit across the bus. The remainder of the transaction can then be
+//! driven using either a polling or interrupt-driven method.
+//!
+//! For the single send and receive cases, the polling method involves looping
+//! on the return from \ref I2CMasterBusy(). Once the function indicates that the \i2c
+//! master is no longer busy, the bus transaction is complete and can be
+//! checked for errors using \ref I2CMasterErr(). If there are no errors, then the data
+//! has been sent or is ready to be read using \ref I2CMasterDataGet(). For the burst
+//! send and receive cases, the polling method also involves calling the
+//! \ref I2CMasterControl() function for each byte transmitted or received
+//! (using either the \ref I2C_MASTER_CMD_BURST_SEND_CONT or \ref I2C_MASTER_CMD_BURST_RECEIVE_CONT
+//! commands), and for the last byte sent or received (using either the
+//! \ref I2C_MASTER_CMD_BURST_SEND_FINISH or \ref I2C_MASTER_CMD_BURST_RECEIVE_FINISH
+//! commands).
+//!
+//! If any error is detected during the burst transfer,
+//! the appropriate stop command (\ref I2C_MASTER_CMD_BURST_SEND_ERROR_STOP or
+//! \ref I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP) should be used to call the
+//! \ref I2CMasterControl() function.
+//!
+//! For the interrupt-driven transaction, the user must register an interrupt
+//! handler for the \i2c devices and enable the \i2c master interrupt; the interrupt
+//! occurs when the master is no longer busy.
+//!
+//! \section sec_i2c_slave Slave Operations
+//!
+//! When using this API to drive the \i2c slave module, the user must first
+//! initialize the \i2c slave module with a call to \ref I2CSlaveInit(). This function
+//! enables the \i2c slave module and initializes the address of the slave. After the
+//! initialization completes, the user may poll the slave status using
+//! \ref I2CSlaveStatus() to determine if a master requested a send or receive
+//! operation. Depending on the type of operation requested, the user can call
+//! \ref I2CSlaveDataPut() or \ref I2CSlaveDataGet() to complete the transaction.
+//! Alternatively, the \i2c slave can handle transactions using an interrupt handler
+//! registered with \ref I2CIntRegister(), and by enabling the \i2c slave interrupt.
+//!
+//! \section sec_i2c_api API
+//!
+//! The \i2c API is broken into three groups of functions:
+//! those that handle status and initialization, those that
+//! deal with sending and receiving data, and those that deal with
+//! interrupts.
+//!
+//! Status and initialization functions for the \i2c module are:
+//! - \ref I2CMasterInitExpClk()
+//! - \ref I2CMasterEnable()
+//! - \ref I2CMasterDisable()
+//! - \ref I2CMasterBusBusy()
+//! - \ref I2CMasterBusy()
+//! - \ref I2CMasterErr()
+//! - \ref I2CSlaveInit()
+//! - \ref I2CSlaveEnable()
+//! - \ref I2CSlaveDisable()
+//! - \ref I2CSlaveStatus()
+//!
+//! Sending and receiving data from the \i2c module is handled by the following functions:
+//! - \ref I2CMasterSlaveAddrSet()
+//! - \ref I2CSlaveAddressSet()
+//! - \ref I2CMasterControl()
+//! - \ref I2CMasterDataGet()
+//! - \ref I2CMasterDataPut()
+//! - \ref I2CSlaveDataGet()
+//! - \ref I2CSlaveDataPut()
+//!
+//! The \i2c master and slave interrupts are handled by the following functions:
+//! - \ref I2CIntRegister()
+//! - \ref I2CIntUnregister()
+//! - \ref I2CMasterIntEnable()
+//! - \ref I2CMasterIntDisable()
+//! - \ref I2CMasterIntClear()
+//! - \ref I2CMasterIntStatus()
+//! - \ref I2CSlaveIntEnable()
+//! - \ref I2CSlaveIntDisable()
+//! - \ref I2CSlaveIntClear()
+//! - \ref I2CSlaveIntStatus()
+//!
+//! @}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2s.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2s.c
new file mode 100644
index 0000000..b8b38a0
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2s.c
@@ -0,0 +1,349 @@
+/******************************************************************************
+* Filename: i2s.c
+* Revised: 2017-05-08 12:18:04 +0200 (Mon, 08 May 2017)
+* Revision: 48924
+*
+* Description: Driver for the I2S.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "i2s.h"
+
+//*****************************************************************************
+//
+// Handle support for DriverLib in ROM:
+// This section will undo prototype renaming made in the header file
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #undef I2SEnable
+ #define I2SEnable NOROM_I2SEnable
+ #undef I2SAudioFormatConfigure
+ #define I2SAudioFormatConfigure NOROM_I2SAudioFormatConfigure
+ #undef I2SChannelConfigure
+ #define I2SChannelConfigure NOROM_I2SChannelConfigure
+ #undef I2SBufferConfig
+ #define I2SBufferConfig NOROM_I2SBufferConfig
+ #undef I2SPointerUpdate
+ #define I2SPointerUpdate NOROM_I2SPointerUpdate
+ #undef I2SPointerSet
+ #define I2SPointerSet NOROM_I2SPointerSet
+ #undef I2SSampleStampConfigure
+ #define I2SSampleStampConfigure NOROM_I2SSampleStampConfigure
+ #undef I2SSampleStampGet
+ #define I2SSampleStampGet NOROM_I2SSampleStampGet
+#endif
+
+//*****************************************************************************
+//
+// Global pointer to the current I2S data structure
+//
+//*****************************************************************************
+I2SControlTable *g_pControlTable;
+
+//*****************************************************************************
+//
+// Enables the I2S module for operation
+//
+//*****************************************************************************
+void
+I2SEnable(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(I2SBaseValid(ui32Base));
+
+ // Make sure the control table pointer is setup to a memory location.
+ if(!(g_pControlTable))
+ {
+ return;
+ }
+
+ // Write the address to the first input/output buffer.
+ HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT) = g_pControlTable->ui32InBase;
+ g_pControlTable->ui32InOffset = 0;
+ HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT) = g_pControlTable->ui32OutBase;
+ g_pControlTable->ui32OutOffset = 0;
+
+ // Enable the I2S module.
+ HWREG(I2S0_BASE + I2S_O_AIFDMACFG) = (uint32_t)g_pControlTable->ui16DMABufSize - 1;
+}
+
+//*****************************************************************************
+//
+// Configures the I2S module
+//
+//*****************************************************************************
+void
+I2SAudioFormatConfigure(uint32_t ui32Base, uint32_t ui32FmtCfg,
+ uint32_t ui32BitClkDelay)
+{
+ // Check the arguments.
+ ASSERT(I2SBaseValid(ui32Base));
+ ASSERT(ui32BitClkDelay <= 255);
+
+ // Save the length of the audio words stored in memory.
+ g_pControlTable->ui16MemLen = (ui32FmtCfg & I2S_MEM_LENGTH_24) ? 24 : 16;
+
+ // Write the configuration.
+ HWREG(I2S0_BASE + I2S_O_AIFFMTCFG) = ui32FmtCfg | (ui32BitClkDelay << I2S_AIFFMTCFG_DATA_DELAY_S);
+}
+
+//****************************************************************************
+//
+// Setup the audio channel configuration
+//
+//****************************************************************************
+void
+I2SChannelConfigure(uint32_t ui32Base, uint32_t ui32Chan0Cfg,
+ uint32_t ui32Chan1Cfg)
+{
+ uint32_t ui32InChan;
+ uint32_t ui32OutChan;
+ uint32_t ui32ChanMask;
+
+ // Check the arguments.
+ ASSERT(I2SBaseValid(ui32Base));
+ ASSERT(ui32Chan0Cfg & (I2S_CHAN_CFG_MASK | I2S_LINE_MASK))
+ ASSERT(ui32Chan1Cfg & (I2S_CHAN_CFG_MASK | I2S_LINE_MASK))
+
+ ui32InChan = 0;
+ ui32OutChan = 0;
+
+ // Configure input/output channels.
+ HWREG(I2S0_BASE + I2S_O_AIFDIRCFG) = (
+ (( ui32Chan0Cfg << I2S_AIFDIRCFG_AD0_S) & I2S_AIFDIRCFG_AD0_M ) |
+ (( ui32Chan1Cfg << I2S_AIFDIRCFG_AD1_S) & I2S_AIFDIRCFG_AD1_M ) );
+
+ // Configure the valid channel mask.
+ HWREG(I2S0_BASE + I2S_O_AIFWMASK0) = (ui32Chan0Cfg >> 8) & I2S_AIFWMASK0_MASK_M;
+ HWREG(I2S0_BASE + I2S_O_AIFWMASK1) = (ui32Chan1Cfg >> 8) & I2S_AIFWMASK1_MASK_M;
+
+ // Resolve and save the number of input and output channels.
+ ui32ChanMask = (ui32Chan0Cfg & I2S_CHAN_CFG_MASK) >> 8;
+ if(ui32Chan0Cfg & I2S_LINE_INPUT)
+ {
+ while(ui32ChanMask)
+ {
+ if(ui32ChanMask & 0x1)
+ {
+ ui32InChan++;
+ }
+ // Shift down channel mask
+ ui32ChanMask >>= 1;
+ }
+
+ }
+ else if(ui32Chan0Cfg & I2S_LINE_OUTPUT)
+ {
+ while(ui32ChanMask)
+ {
+ if(ui32ChanMask & 0x1)
+ {
+ ui32OutChan++;
+ }
+ // Shift down channel mask
+ ui32ChanMask >>= 1;
+ }
+ }
+
+ ui32ChanMask = (ui32Chan1Cfg & I2S_CHAN_CFG_MASK) >> 8;
+ if(ui32Chan1Cfg & I2S_LINE_INPUT)
+ {
+ while(ui32ChanMask)
+ {
+ if(ui32ChanMask & 0x1)
+ {
+ ui32InChan++;
+ }
+ // Shift down channel mask
+ ui32ChanMask >>= 1;
+ }
+ }
+ else if(ui32Chan1Cfg & I2S_LINE_OUTPUT)
+ {
+ while(ui32ChanMask)
+ {
+ if(ui32ChanMask & 0x1)
+ {
+ ui32OutChan++;
+ }
+ // Shift down channel mask
+ ui32ChanMask >>= 1;
+ }
+ }
+
+ g_pControlTable->ui8InChan = (uint8_t)ui32InChan;
+ g_pControlTable->ui8OutChan = (uint8_t)ui32OutChan;
+}
+
+//****************************************************************************
+//
+// Set the input buffer pointers
+//
+//****************************************************************************
+void
+I2SBufferConfig(uint32_t ui32Base, uint32_t ui32InBufBase,
+ uint32_t ui32OutBufBase, uint16_t ui16DMABufSize,
+ uint16_t ui16ChanBufSize)
+{
+ // Check the arguments.
+ ASSERT(I2SBaseValid(ui32Base));
+ ASSERT(ui16DMABufSize > 0);
+
+ // Setup the input data pointer and buffer sizes.
+ g_pControlTable->ui16DMABufSize = ui16DMABufSize;
+ g_pControlTable->ui16ChBufSize = ui16ChanBufSize;
+ g_pControlTable->ui32InBase = ui32InBufBase;
+ g_pControlTable->ui32OutBase = ui32OutBufBase;
+}
+
+//****************************************************************************
+//
+// Set the buffer pointers
+//
+//****************************************************************************
+void
+I2SPointerSet(uint32_t ui32Base, bool bInput, void * pNextPointer)
+{
+ // Check the arguments.
+ ASSERT(I2SBaseValid(ui32Base));
+
+ // Update the next input/output pointer with the correct address.
+ if(bInput == true)
+ {
+ HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT) = (uint32_t)pNextPointer;
+ }
+ else
+ {
+ HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT) = (uint32_t)pNextPointer;
+ }
+}
+
+//****************************************************************************
+//
+// Update the buffer pointers
+//
+//****************************************************************************
+void
+I2SPointerUpdate(uint32_t ui32Base, bool bInput)
+{
+ uint32_t ui32NextPtr;
+
+ // Check the arguments.
+ ASSERT(I2SBaseValid(ui32Base));
+
+ // Update the next input/output pointer with the correct address.
+ if(bInput == true)
+ {
+ ui32NextPtr = (g_pControlTable->ui8InChan *
+ (g_pControlTable->ui16MemLen >> 3)) *
+ g_pControlTable->ui16DMABufSize;
+ g_pControlTable->ui32InOffset = ((g_pControlTable->ui32InOffset +
+ ui32NextPtr) %
+ g_pControlTable->ui16ChBufSize);
+ HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT) = g_pControlTable->ui32InOffset +
+ g_pControlTable->ui32InBase;
+ }
+ else
+ {
+ ui32NextPtr = (g_pControlTable->ui8OutChan *
+ (g_pControlTable->ui16MemLen >> 3)) *
+ g_pControlTable->ui16DMABufSize;
+ g_pControlTable->ui32OutOffset = ((g_pControlTable->ui32OutOffset +
+ ui32NextPtr) %
+ g_pControlTable->ui16ChBufSize);
+ HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT) =
+ g_pControlTable->ui32OutOffset +
+ g_pControlTable->ui32OutBase;
+ }
+}
+
+//*****************************************************************************
+//
+// Configure the sample stamp generator
+//
+//*****************************************************************************
+void
+I2SSampleStampConfigure(uint32_t ui32Base, bool bInput, bool bOutput)
+{
+ uint32_t ui32Trigger;
+
+ // Check the arguments.
+ ASSERT(I2SBaseValid(ui32Base));
+
+ ui32Trigger = HWREG(I2S0_BASE + I2S_O_STMPWCNT);
+ ui32Trigger = (ui32Trigger + 2) % g_pControlTable->ui16ChBufSize;
+
+ // Setup the sample stamp trigger for input streams.
+ if(bInput)
+ {
+ HWREG(I2S0_BASE + I2S_O_STMPINTRIG) = ui32Trigger;
+ }
+
+ // Setup the sample stamp trigger for output streams.
+ if(bOutput)
+ {
+ HWREG(I2S0_BASE + I2S_O_STMPOUTTRIG) = ui32Trigger;
+ }
+
+}
+
+//*****************************************************************************
+//
+// Get the current value of a sample stamp counter
+//
+//*****************************************************************************
+uint32_t
+I2SSampleStampGet(uint32_t ui32Base, uint32_t ui32Channel)
+{
+ uint32_t ui32FrameClkCnt;
+ uint32_t ui32SysClkCnt;
+ uint32_t ui32PeriodSysClkCnt;
+ uint32_t ui32SampleStamp;
+
+ // Get the number of Frame clock counts since last stamp.
+ ui32FrameClkCnt = HWREG(I2S0_BASE + I2S_O_STMPWCNTCAPT0);
+
+ // Get the number of system clock ticks since last frame clock edge.
+ ui32SysClkCnt = HWREG(I2S0_BASE + I2S_O_STMPXCNTCAPT0);
+
+ // Get the number system clock ticks in the last frame clock period.
+ ui32PeriodSysClkCnt = HWREG(I2S0_BASE + I2S_O_STMPXPER);
+
+ // Calculate the sample stamp.
+ ui32SampleStamp = (ui32SysClkCnt << 16) / ui32PeriodSysClkCnt;
+ ui32SampleStamp = (ui32SampleStamp > I2S_STMP_SATURATION) ?
+ I2S_STMP_SATURATION : ui32SampleStamp;
+ ui32SampleStamp |= (ui32FrameClkCnt << 16);
+
+ return (ui32SampleStamp);
+}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2s.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2s.h
new file mode 100644
index 0000000..62c2c5e
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2s.h
@@ -0,0 +1,1359 @@
+/******************************************************************************
+* Filename: i2s.h
+* Revised: 2018-11-16 11:16:53 +0100 (Fri, 16 Nov 2018)
+* Revision: 53356
+*
+* Description: Defines and prototypes for the I2S.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//****************************************************************************
+//
+//! \addtogroup peripheral_group
+//! @{
+//! \addtogroup i2s_api
+//! @{
+//
+//****************************************************************************
+
+#ifndef __I2S_H__
+#define __I2S_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "../inc/hw_types.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_ints.h"
+#include "../inc/hw_i2s.h"
+#include "debug.h"
+#include "interrupt.h"
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// This section renames all functions that are not "static inline", so that
+// calling these functions will default to implementation in flash. At the end
+// of this file a second renaming will change the defaults to implementation in
+// ROM for available functions.
+//
+// To force use of the implementation in flash, e.g. for debugging:
+// - Globally: Define DRIVERLIB_NOROM at project level
+// - Per function: Use prefix "NOROM_" when calling the function
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #define I2SEnable NOROM_I2SEnable
+ #define I2SAudioFormatConfigure NOROM_I2SAudioFormatConfigure
+ #define I2SChannelConfigure NOROM_I2SChannelConfigure
+ #define I2SBufferConfig NOROM_I2SBufferConfig
+ #define I2SPointerUpdate NOROM_I2SPointerUpdate
+ #define I2SPointerSet NOROM_I2SPointerSet
+ #define I2SSampleStampConfigure NOROM_I2SSampleStampConfigure
+ #define I2SSampleStampGet NOROM_I2SSampleStampGet
+#endif
+
+//*****************************************************************************
+//
+//! \brief A structure that defines an audio control table. Note: Memory for this
+//! structure \b must be initialized by user application. See detailed description!
+//!
+//! \deprecated This structure will be removed in a future release.
+//!
+//! These fields are used by the I2S and normally it is not necessary for
+//! software to directly read or write fields in the table.
+//!
+//! \note The control table must be defined by the user as a global variable and
+//! the global pointer must then be assigned the address of the control table
+//! inside a user function (but before calling any I2S-function).
+//!
+/*!
+\verbatim
+ I2SControlTable g_controlTable; // Define global
+ g_pControlTable = &g_controlTable; // Assign pointer (inside a function)
+\endverbatim
+*/
+//!
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+typedef struct
+{
+ uint16_t ui16DMABufSize; //!< Size of DMA buffer in number of samples.
+ uint16_t ui16ChBufSize; //!< Size of Channel buffer.
+ uint8_t ui8InChan; //!< Input Channel.
+ uint8_t ui8OutChan; //!< Output Channel.
+ uint16_t ui16MemLen; //!< Length of the audio words stored in memory.
+ uint32_t ui32InBase; //!< Base address of the input buffer.
+ uint32_t ui32InOffset; //!< Value of the current input pointer offset.
+ uint32_t ui32OutBase; //!< Base address of the output buffer.
+ uint32_t ui32OutOffset; //!< Value of the current output pointer offset.
+} I2SControlTable;
+#endif
+
+//*****************************************************************************
+//
+// Declare global pointer to the I2S data structure.
+//
+// The control table must be defined by the user as a global variable and the
+// global pointer must then be assigned the address of the control table:
+//
+// I2SControlTable g_controlTable;
+// g_pControlTable = &g_controlTable;
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+extern I2SControlTable *g_pControlTable;
+#endif
+
+//*****************************************************************************
+//
+// Defines for the I2S DMA buffer sizes
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#define I2S_DMA_BUF_SIZE_64 0x00000040
+#define I2S_DMA_BUF_SIZE_128 0x00000080
+#define I2S_DMA_BUF_SIZE_256 0x00000100
+#endif
+
+//*****************************************************************************
+//
+// Defines for the I2S audio clock configuration
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#define I2S_EXT_WCLK 0x00000001
+#define I2S_INT_WCLK 0x00000002
+#define I2S_INVERT_WCLK 0x00000004
+#define I2S_NORMAL_WCLK 0x00000000
+#endif
+
+//*****************************************************************************
+//
+// Defines for the audio data line input/output configuration
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#define I2S_LINE_UNUSED 0x00000000
+#define I2S_LINE_INPUT 0x00000001
+#define I2S_LINE_OUTPUT 0x00000002
+#define I2S_LINE_MASK 0x00000003
+#endif
+
+//*****************************************************************************
+//
+// Defines for activating an audio channel.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#define I2S_CHAN0_ACT 0x00000100
+#define I2S_CHAN1_ACT 0x00000200
+#define I2S_CHAN2_ACT 0x00000400
+#define I2S_CHAN3_ACT 0x00000800
+#define I2S_CHAN4_ACT 0x00001000
+#define I2S_CHAN5_ACT 0x00002000
+#define I2S_CHAN6_ACT 0x00004000
+#define I2S_CHAN7_ACT 0x00008000
+#define I2S_MONO_MODE 0x00000100
+#define I2S_STEREO_MODE 0x00000300
+#define I2S_CHAN_CFG_MASK 0x0000FF00
+#endif
+
+#define I2S_CHAN0_MASK 0x00000001
+#define I2S_CHAN1_MASK 0x00000002
+#define I2S_CHAN2_MASK 0x00000004
+#define I2S_CHAN3_MASK 0x00000008
+#define I2S_CHAN4_MASK 0x00000010
+#define I2S_CHAN5_MASK 0x00000020
+#define I2S_CHAN6_MASK 0x00000040
+#define I2S_CHAN7_MASK 0x00000080
+
+//*****************************************************************************
+//
+// Defines for the audio format configuration
+//
+//*****************************************************************************
+#define I2S_MEM_LENGTH_16 0x00000000 // 16 bit size of word in memory
+#define I2S_MEM_LENGTH_24 0x00000080 // 24 bit size of word in memory
+#define I2S_POS_EDGE 0x00000040 // Sample on positive edge
+#define I2S_NEG_EDGE 0x00000000 // Sample on negative edge
+#define I2S_DUAL_PHASE_FMT 0x00000020 // Dual Phased audio format
+#define I2S_SINGLE_PHASE_FMT 0x00000000 // Single Phased audio format
+#define I2S_WORD_LENGTH_8 0x00000008 // Word length is 8 bits
+#define I2S_WORD_LENGTH_16 0x00000010 // Word length is 16 bits
+#define I2S_WORD_LENGTH_24 0x00000018 // Word length is 24 bits
+
+//*****************************************************************************
+//
+// Defines for the sample stamp counters
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#define I2S_STMP0 0x00000001 // Sample stamp counter channel 0
+#define I2S_STMP1 0x00000002 // Sample stamp counter channel 1
+#endif
+#define I2S_STMP_SATURATION 0x0000FFFF // The saturation value used when
+ // calculating the sample stamp
+
+//*****************************************************************************
+//
+// Defines for the interrupt
+//
+//*****************************************************************************
+#define I2S_INT_DMA_IN 0x00000020 // DMA output buffer full interrupt
+#define I2S_INT_DMA_OUT 0x00000010 // DMA input buffer empty interrupt
+#define I2S_INT_TIMEOUT 0x00000008 // Word Clock Timeout
+#define I2S_INT_BUS_ERR 0x00000004 // DMA Bus error
+#define I2S_INT_WCLK_ERR 0x00000002 // Word Clock error
+#define I2S_INT_PTR_ERR 0x00000001 // Data pointer error (DMA data was not updated in time).
+#define I2S_INT_ALL 0x0000003F // All interrupts
+
+//*****************************************************************************
+//
+// API Functions and prototypes
+//
+//*****************************************************************************
+
+#ifdef DRIVERLIB_DEBUG
+//*****************************************************************************
+//
+//! \internal
+//!
+//! \brief Checks an I2S base address.
+//!
+//! This function determines if an I2S port base address is valid.
+//!
+//! \param ui32Base is the base address of the I2S port.
+//!
+//! \return Returns \c true if the base address is valid and \c false
+//! otherwise.
+//
+//*****************************************************************************
+static bool
+I2SBaseValid(uint32_t ui32Base)
+{
+ return(ui32Base == I2S0_BASE);
+}
+#endif
+
+//*****************************************************************************
+//
+//! \brief Enables the I2S module for operation.
+//!
+//! \deprecated This function will be removed in a future release.
+//!
+//! \note The module should only be enabled after configuration. When the
+//! module is disabled, no data or clocks will be generated on the I2S signals.
+//!
+//! \note Immediately after enabling the module the programmer should update
+//! the DMA data pointer registers using \ref I2SPointerUpdate() to ensure a new
+//! pointer is written before the DMA transfer completes. Failure to update
+//! the pointer in time will result in an \ref I2S_INT_PTR_ERR.
+//!
+//! \param ui32Base is the I2S module base address.
+//!
+//! \return None
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+extern void I2SEnable(uint32_t ui32Base);
+#endif
+
+//*****************************************************************************
+//
+//! \brief Disables the I2S module for operation.
+//!
+//! \deprecated This function will be removed in a future release.
+//!
+//! This function will immediately disable the I2S module. To ensure that
+//! all buffer operations are completed before shutting down, the correct
+//! procedure is:
+//! 1. Do not update the data pointers using \ref I2SPointerUpdate().
+//! 2. Await next interrupt resulting in \ref I2S_INT_PTR_ERR.
+//! 3. Disable the I2S using \ref I2SDisable() and clear the pointer error using
+//! \ref I2SIntClear().
+//! 4. Disable bit clock source (done externally).
+//!
+//! \param ui32Base is the I2S module base address.
+//!
+//! \return None
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+__STATIC_INLINE void
+I2SDisable(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(I2SBaseValid(ui32Base));
+
+ // Disable the I2S module.
+ HWREG(I2S0_BASE + I2S_O_AIFDMACFG) = 0x0;
+}
+#endif
+
+//*****************************************************************************
+//
+//! \brief Configures the I2S module.
+//!
+//! \deprecated This function will be removed in a future release.
+//!
+//! The word length defines the size of the word transmitted on the data
+//! lines. For single phased formats \c I2S_WORD_LENGTH_x is the exact number
+//! of bits per word. In dual phased format this is the maximum number of bits
+//! per word. The size is set using \ref I2S_WORD_LENGTH_8,
+//! \ref I2S_WORD_LENGTH_16 or \ref I2S_WORD_LENGTH_24.
+//!
+//! \param ui32Base is the I2S module base address.
+//! \param ui32FmtCfg is the bitwise OR of several options:
+//! - Sample size:
+//! - \ref I2S_MEM_LENGTH_16
+//! - \ref I2S_MEM_LENGTH_24
+//! - Clock edge sampling:
+//! - \ref I2S_POS_EDGE
+//! - \ref I2S_NEG_EDGE
+//! - Phase:
+//! - \ref I2S_DUAL_PHASE_FMT
+//! - \ref I2S_SINGLE_PHASE_FMT
+//! - Word length:
+//! - \ref I2S_WORD_LENGTH_8
+//! - \ref I2S_WORD_LENGTH_16
+//! - \ref I2S_WORD_LENGTH_24
+//! \param ui32BitClkDelay defines the bit clock delay by setting the number of bit clock periods between the
+//! positive word clock edge and the MSB of the first word in a phase. The bit
+//! clock delay is determined by the ratio between the bit clock and the frame
+//! clock and the chosen audio format. The bit clock delay \b must be configured
+//! depending on the chosen audio format:
+//! - 0 : Left Justified Format (LJF).
+//! - 1 : I2S and DSP format.
+//! - 2-255 : Right Justified format (RJF).
+//!
+//! \return None
+//!
+//! \sa \ref I2SChannelConfigure()
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+extern void I2SAudioFormatConfigure(uint32_t ui32Base, uint32_t ui32FmtCfg,
+ uint32_t ui32BitClkDelay);
+#endif
+
+//****************************************************************************
+//
+//! \brief Setup the audio channel configuration.
+//!
+//! \deprecated This function will be removed in a future release.
+//!
+//! The channel configuration is a bitwise OR of the input/output mode of each
+//! data line and the active audio channels within a specific audio frame.
+//!
+//! Setting up the input/output mode use one of:
+//! - \ref I2S_LINE_UNUSED
+//! - \ref I2S_LINE_INPUT
+//! - \ref I2S_LINE_OUTPUT
+//!
+//! For dual phased audio (LJF,RJF,I2S) only mono and stereo modes are allowed.
+//! For single phased audio format (DSP) up to 8 active channels are allowed
+//! on a single data line. For setting up the active channels in a frame use:
+//! - Single phased, use a bitwise OR'ed combination of:
+//! - \ref I2S_CHAN0_ACT
+//! - \ref I2S_CHAN1_ACT
+//! - \ref I2S_CHAN2_ACT
+//! - \ref I2S_CHAN3_ACT
+//! - \ref I2S_CHAN4_ACT
+//! - \ref I2S_CHAN5_ACT
+//! - \ref I2S_CHAN6_ACT
+//! - \ref I2S_CHAN7_ACT
+//! - Dual phased, use one of:
+//! - \ref I2S_MONO_MODE (same as \ref I2S_CHAN0_ACT)
+//! - \ref I2S_STEREO_MODE (same as \ref I2S_CHAN0_ACT | \ref I2S_CHAN1_ACT)
+//!
+//! \note The audio format and the clock configuration should be set using
+//! \ref I2SAudioFormatConfigure()
+//!
+//! \param ui32Base is base address of the I2S module.
+//! \param ui32Chan0Cfg defines the channel configuration for data line 0.
+//! \param ui32Chan1Cfg defines the channel configuration for data line 1.
+//!
+//! \return None
+//!
+//! \sa \ref I2SAudioFormatConfigure()
+//
+//****************************************************************************
+#ifndef DEPRECATED
+extern void I2SChannelConfigure(uint32_t ui32Base, uint32_t ui32Chan0Cfg,
+ uint32_t ui32Chan1Cfg);
+#endif
+
+//****************************************************************************
+//
+//! \brief Configure the I2S frame clock.
+//!
+//! \deprecated This function will be removed in a future release.
+//!
+//! Configure I2S clock to be either internal or external and either normal
+//! or inverted.
+//!
+//! \note The bit clock configuration is done externally, but the internal/
+//! external setting must match what is chosen internally in the I2S module
+//! for the frame clock.
+//!
+//! \param ui32Base is the base address of the I2S module.
+//! \param ui32ClkConfig is the clock configuration parameter. Bitwise OR'ed
+//! combination of clock source and clock polarity:
+//! - Clock source:
+//! - \ref I2S_EXT_WCLK : External clock.
+//! - \ref I2S_INT_WCLK : Internal clock.
+//! - Clock polarity:
+//! - \ref I2S_NORMAL_WCLK : Normal clock.
+//! - \ref I2S_INVERT_WCLK : Inverted clock.
+//!
+//! \return None
+//
+//****************************************************************************
+#ifndef DEPRECATED
+__STATIC_INLINE void
+I2SClockConfigure(uint32_t ui32Base, uint32_t ui32ClkConfig)
+{
+ // Check the arguments.
+ ASSERT(I2SBaseValid(ui32Base));
+
+ // Setup register WCLK Source.
+ HWREG(I2S0_BASE + I2S_O_AIFWCLKSRC) = ui32ClkConfig &
+ (I2S_AIFWCLKSRC_WCLK_INV_M |
+ I2S_AIFWCLKSRC_WCLK_SRC_M);
+}
+#endif
+
+//****************************************************************************
+//
+//! \brief Set the input buffer pointers.
+//!
+//! \deprecated This function will be removed in a future release.
+//!
+//! The next pointer should always be written while the DMA is using the
+//! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR will
+//! occur and all outputs will be disabled.
+//!
+//! \note At startup the next data pointer should be
+//! written just before and just after calling the \ref I2SEnable().
+//!
+//! \param ui32Base is the base address of the I2S module.
+//! \param ui32InBufBase is the address of the input buffer.
+//! \param ui32OutBufBase is the address of the output buffer.
+//! \param ui16DMABufSize is the size of the DMA buffers. Must be greater than 0!
+//! \param ui16ChanBufSize is the size of the channel buffers.
+//!
+//! \return None
+//
+//****************************************************************************
+#ifndef DEPRECATED
+extern void I2SBufferConfig(uint32_t ui32Base, uint32_t ui32InBufBase,
+ uint32_t ui32OutBufBase, uint16_t ui16DMABufSize,
+ uint16_t ui16ChanBufSize);
+#endif
+
+//****************************************************************************
+//
+//! \brief Update the buffer pointers.
+//!
+//! \deprecated This function will be removed in a future release.
+//!
+//! The next pointer should always be written while the DMA is using the
+//! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR will occur
+//! and all outputs will be disabled. Nothing is preventing the pointers from
+//! being identical, but this function relies on both pointers (input or
+//! output pointers) are pointing to a valid address.
+//!
+//! \note It is recommended that the pointer update is done in an interrupt context
+//! to ensure that the update is performed before the buffer is full.
+//!
+//! \param ui32Base is the base address of the I2S module.
+//! \param bInput determines whether to update input or output pointer.
+//! - \c true : Update input pointer.
+//! - \c false : Update output pointer
+//!
+//! \return None
+//!
+//! \sa \ref I2SPointerSet()
+//
+//****************************************************************************
+#ifndef DEPRECATED
+extern void I2SPointerUpdate(uint32_t ui32Base, bool bInput);
+#endif
+
+//****************************************************************************
+//
+//! \brief Set a buffer pointer (input or output) directly.
+//!
+//! \deprecated This function will be removed in a future release.
+//!
+//! This function allows bypassing of the pointers in the global control table.
+//!
+//! The next pointer should always be written while the DMA is using the
+//! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR will occur
+//! and all outputs will be disabled. Nothing is preventing the pointers from
+//! being identical, but this function relies on both pointers (input or
+//! output pointers) are pointing to a valid address.
+//!
+//! \note It is recommended that the pointer update is done in an interrupt context
+//! to ensure that the update is performed before the buffer is full.
+//!
+//! \param ui32Base is the base address of the I2S module.
+//! \param bInput determines whether to update input or output pointer.
+//! - \c true : Update input pointer.
+//! - \c false : Update output pointer
+//! \param pNextPointer is a void pointer to user defined buffer.
+//!
+//! \return None
+//!
+//! \sa \ref I2SPointerUpdate()
+//
+//****************************************************************************
+#ifndef DEPRECATED
+extern void I2SPointerSet(uint32_t ui32Base, bool bInput, void * pNextPointer);
+#endif
+
+//*****************************************************************************
+//
+//! \brief Registers an interrupt handler for an I2S interrupt in the dynamic interrupt table.
+//!
+//! \deprecated This function will be removed in a future release.
+//!
+//! \note Only use this function if you want to use the dynamic vector table (in SRAM)!
+//!
+//! This function registers a function as the interrupt handler for a specific
+//! interrupt and enables the corresponding interrupt in the interrupt controller.
+//!
+//! Specific I2S interrupts must be enabled via \ref I2SIntEnable(). It is the interrupt
+//! handler's responsibility to clear the interrupt source.
+//!
+//! \param ui32Base is the base address of the I2S module.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! I2S interrupt occurs.
+//!
+//! \return None
+//!
+//! \sa \ref IntRegister() for important information about registering interrupt
+//! handlers.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+__STATIC_INLINE void
+I2SIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
+{
+ // Check the arguments.
+ ASSERT(I2SBaseValid(ui32Base));
+
+ // Register the interrupt handler.
+ IntRegister(INT_I2S_IRQ, pfnHandler);
+
+ // Enable the I2S interrupt.
+ IntEnable(INT_I2S_IRQ);
+}
+#endif
+
+//*****************************************************************************
+//
+//! \brief Unregisters an interrupt handler for a I2S interrupt in the dynamic interrupt table.
+//!
+//! \deprecated This function will be removed in a future release.
+//!
+//! This function does the actual unregistering of the interrupt handler. It
+//! clears the handler to be called when an I2S interrupt occurs. This
+//! function also masks off the interrupt in the interrupt controller so that
+//! the interrupt handler no longer is called.
+//!
+//! \param ui32Base is the base address of the I2S port.
+//!
+//! \return None
+//!
+//! \sa \ref IntRegister() for important information about registering interrupt
+//! handlers.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+__STATIC_INLINE void
+I2SIntUnregister(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(I2SBaseValid(ui32Base));
+
+ // Disable the interrupt.
+ IntDisable(INT_I2S_IRQ);
+
+ // Unregister the interrupt handler.
+ IntUnregister(INT_I2S_IRQ);
+}
+#endif
+
+//*****************************************************************************
+//
+//! \brief Configure the sample stamp generator.
+//!
+//! \deprecated This function will be removed in a future release.
+//!
+//! Use this function to configure the sample stamp generator.
+//!
+//! \param ui32Base is the base address of the I2S module.
+//! \param bInput enables triggering of the sample stamp generator on input.
+//! \param bOutput enables triggering of the sample stamp generator on output.
+//!
+//! \return None
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+extern void I2SSampleStampConfigure(uint32_t ui32Base, bool bInput,
+ bool bOutput);
+#endif
+
+//*****************************************************************************
+//
+//! \brief Enables individual I2S interrupt sources.
+//!
+//! This function enables the indicated I2S interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! \param ui32Base is the base address of the I2S port.
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled.
+//! The parameter is the bitwise OR of any of the following:
+//! - \ref I2S_INT_DMA_IN
+//! - \ref I2S_INT_DMA_OUT
+//! - \ref I2S_INT_TIMEOUT
+//! - \ref I2S_INT_BUS_ERR
+//! - \ref I2S_INT_WCLK_ERR
+//! - \ref I2S_INT_PTR_ERR
+//! - \ref I2S_INT_ALL (covers all the above)
+//!
+//! \return None.
+//
+//*****************************************************************************
+__STATIC_INLINE void
+I2SIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ // Check the arguments.
+ ASSERT(I2SBaseValid(ui32Base));
+
+ // Enable the specified interrupts.
+ HWREG(I2S0_BASE + I2S_O_IRQMASK) |= ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! \brief Disables individual I2S interrupt sources.
+//!
+//! This function disables the indicated I2S interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! \param ui32Base is the base address of the I2S port.
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled.
+//! The parameter is the bitwise OR of any of the following:
+//! - \ref I2S_INT_DMA_IN
+//! - \ref I2S_INT_DMA_OUT
+//! - \ref I2S_INT_TIMEOUT
+//! - \ref I2S_INT_BUS_ERR
+//! - \ref I2S_INT_WCLK_ERR
+//! - \ref I2S_INT_PTR_ERR
+//! - \ref I2S_INT_ALL (covers all the above)
+//!
+//! \return None.
+//
+//*****************************************************************************
+__STATIC_INLINE void
+I2SIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ // Check the arguments.
+ ASSERT(I2SBaseValid(ui32Base));
+
+ // Disable the specified interrupts.
+ HWREG(I2S0_BASE + I2S_O_IRQMASK) &= ~ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! \brief Gets the current interrupt status.
+//!
+//! This function returns the interrupt status for the specified I2S. Either
+//! the raw interrupt status or the status of interrupts that are allowed to
+//! reflect to the processor can be returned.
+//!
+//! \param ui32Base is the base address of the I2S port
+//! \param bMasked selects between raw and masked interrupt status:
+//! - \c false : Raw interrupt status is required.
+//! - \c true : Masked interrupt status is required.
+//!
+//! \return Returns the current interrupt status as a vector of:
+//! - \ref I2S_INT_DMA_IN
+//! - \ref I2S_INT_DMA_OUT
+//! - \ref I2S_INT_TIMEOUT
+//! - \ref I2S_INT_BUS_ERR
+//! - \ref I2S_INT_WCLK_ERR
+//! - \ref I2S_INT_PTR_ERR
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+I2SIntStatus(uint32_t ui32Base, bool bMasked)
+{
+ uint32_t ui32Mask;
+
+ // Check the arguments.
+ ASSERT(I2SBaseValid(ui32Base));
+
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ if(bMasked)
+ {
+ ui32Mask = HWREG(I2S0_BASE + I2S_O_IRQFLAGS);
+ return(ui32Mask & HWREG(I2S0_BASE + I2S_O_IRQMASK));
+ }
+ else
+ {
+ return(HWREG(I2S0_BASE + I2S_O_IRQFLAGS));
+ }
+}
+
+//*****************************************************************************
+//
+//! \brief Clears I2S interrupt sources.
+//!
+//! The specified I2S interrupt sources are cleared, so that they no longer
+//! assert. This function must be called in the interrupt handler to keep the
+//! interrupt from being recognized again immediately upon exit.
+//!
+//! \note Due to write buffers and synchronizers in the system it may take several
+//! clock cycles from a register write clearing an event in a module and until the
+//! event is actually cleared in the NVIC of the system CPU. It is recommended to
+//! clear the event source early in the interrupt service routine (ISR) to allow
+//! the event clear to propagate to the NVIC before returning from the ISR.
+//! At the same time, an early event clear allows new events of the same type to be
+//! pended instead of ignored if the event is cleared later in the ISR.
+//! It is the responsibility of the programmer to make sure that enough time has passed
+//! before returning from the ISR to avoid false re-triggering of the cleared event.
+//! A simple, although not necessarily optimal, way of clearing an event before
+//! returning from the ISR is:
+//! -# Write to clear event (interrupt source). (buffered write)
+//! -# Dummy read from the event source module. (making sure the write has propagated)
+//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers)
+//!
+//! \param ui32Base is the base address of the I2S port.
+//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared.
+//! The parameter is the bitwise OR of any of the following:
+//! - \ref I2S_INT_DMA_IN
+//! - \ref I2S_INT_DMA_OUT
+//! - \ref I2S_INT_TIMEOUT
+//! - \ref I2S_INT_BUS_ERR
+//! - \ref I2S_INT_WCLK_ERR
+//! - \ref I2S_INT_PTR_ERR
+//! - \ref I2S_INT_ALL (covers all the above)
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+I2SIntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ // Check the arguments.
+ ASSERT(I2SBaseValid(ui32Base));
+
+ // Clear the requested interrupt sources.
+ HWREG(I2S0_BASE + I2S_O_IRQCLR) = ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! \brief Enable the Sample Stamp generator.
+//!
+//! Use this function to enable the sample stamp generators.
+//!
+//! \note It is the user's responsibility to ensure that the sample stamp
+//! generator is properly configured before it is enabled. It is the setting
+//! of the Input and Output triggers configured using \ref I2SSampleStampConfigure()
+//! that triggers the start point of the audio streams.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+I2SSampleStampEnable(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(I2SBaseValid(ui32Base));
+
+ // Set the enable bit.
+ HWREG(I2S0_BASE + I2S_O_STMPCTL) = I2S_STMPCTL_STMP_EN;
+}
+
+//*****************************************************************************
+//
+//! \brief Disable the Sample Stamp generator.
+//!
+//! Use this function to disable the sample stamp generators. When the sample
+//! stamp generator is disabled, the clock counters are automatically cleared.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+I2SSampleStampDisable(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(I2SBaseValid(ui32Base));
+
+ // Clear the enable bit.
+ HWREG(I2S0_BASE + I2S_O_STMPCTL) = 0;
+
+}
+
+//*****************************************************************************
+//
+//! \brief Get the current value of a sample stamp counter.
+//!
+//! \param ui32Base is the base address of the I2S module.
+//! \param ui32Channel is the sample stamp counter to sample
+//!
+//! \return Returns the current value of the selected sample stamp channel.
+//
+//*****************************************************************************
+extern uint32_t I2SSampleStampGet(uint32_t ui32Base, uint32_t ui32Channel);
+
+//*****************************************************************************
+//
+//! \brief Starts the I2S.
+//!
+//! I2S must be configured before it is started.
+//!
+//! \note Immediately after enabling the module the programmer must update
+//! the DMA data pointer registers using \ref I2SInPointerSet() and
+//! \ref I2SOutPointerSet() to ensure a new pointer is written before the DMA
+//! transfer completes. Failure to update the pointer in time will result in
+//! an \ref I2S_INT_PTR_ERR.
+//!
+//! \param ui32Base is the I2S module base address.
+//! \param ui8FixDMALength is the length of the DMA buffer: this will allow
+//! the DMA to read ui8FixDMALength between to pointer refreshes.
+//!
+//! \return None
+//!
+//! \sa \ref I2SStop()
+//
+//*****************************************************************************
+__STATIC_INLINE void I2SStart(uint32_t ui32Base, uint8_t ui8FixDMALength)
+{
+ // Check the arguments.
+ ASSERT(I2SBaseValid(ui32Base));
+
+ // Enable the I2S module.
+ HWREG(I2S0_BASE + I2S_O_AIFDMACFG) = ui8FixDMALength;
+}
+
+//*****************************************************************************
+//
+//! \brief Stops the I2S module for operation.
+//!
+//! This function will immediately disable the I2S module. To ensure that
+//! all buffer operations are completed before shutting down, the correct
+//! procedure is:
+//! 1. Do not update the data pointers using \ref I2SInPointerSet() and
+//! \ref I2SOutPointerSet().
+//! 2. Await that values returned by \ref I2SInPointerNextGet(),
+//! \ref I2SOutPointerNextGet(), \ref I2SInPointerGet() and \ref I2SOutPointerGet()
+//! are zero.
+//! 3. Disable the I2S using \ref I2SStop() and clear the pointer
+//! error using \ref I2SIntClear().
+//! 4. Disable bit clock source (done externally).
+//!
+//! \param ui32Base is the I2S module base address.
+//!
+//! \return None
+//!
+//! \sa \ref I2SStart()
+//
+//*****************************************************************************
+__STATIC_INLINE void I2SStop(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(I2SBaseValid(ui32Base));
+
+ // Disable the I2S module.
+ HWREG(I2S0_BASE + I2S_O_AIFDMACFG) = 0x00;
+}
+
+//*****************************************************************************
+//
+//! \brief Configure the serial format of the I2S module.
+//!
+//! The word length defines the size of the word transmitted on the data
+//! lines. For single phased formats \c ui8BitsPerSample is the exact number
+//! of bits per word. In dual phased format this is the maximum number of bits
+//! per word.
+//!
+//! \param ui32Base is the I2S module base address.
+//! \param ui8iDataDelay is the number of BCLK periods between the first WCLK
+//! edge and the MSB of the first audio channel data transferred during
+//! the phase.
+//! \param ui8iMemory24Bits selects if the samples in memory are coded on 16 bits
+//! or 24 bits. Possible values are:
+//! - \ref I2S_MEM_LENGTH_16
+//! - \ref I2S_MEM_LENGTH_24
+//! \param ui8iSamplingEdge selects if sampling on falling or rising edges.
+//! Possible values are:
+//! - \ref I2S_NEG_EDGE
+//! - \ref I2S_POS_EDGE
+//! \param boolDualPhase must be set to true for dual phase and to false for
+//! single phase and user-defined phase.
+//! \param ui8BitsPerSample is the number of bits transmitted for each sample.
+//! If this number does not match with the memory length selected
+//! (16 bits or24 bits), samples will be truncated or padded.
+//! \param ui16transmissionDelay is the number of WCLK periods before the first
+//! transmission.
+//!
+//! \return None
+//!
+//! \sa \ref I2SFrameConfigure()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+I2SFormatConfigure(uint32_t ui32Base,
+ uint8_t ui8iDataDelay,
+ uint8_t ui8iMemory24Bits,
+ uint8_t ui8iSamplingEdge,
+ bool boolDualPhase,
+ uint8_t ui8BitsPerSample,
+ uint16_t ui16transmissionDelay)
+{
+ // Check the arguments.
+ ASSERT(I2SBaseValid(ui32Base));
+ ASSERT(ui8BitsPerSample <= I2S_AIFFMTCFG_WORD_LEN_MAX);
+ ASSERT(ui8BitsPerSample >= I2S_AIFFMTCFG_WORD_LEN_MIN);
+
+ // Setup register AIFFMTCFG Source.
+ HWREGH(I2S0_BASE + I2S_O_AIFFMTCFG) =
+ (ui8iDataDelay << I2S_AIFFMTCFG_DATA_DELAY_S) |
+ (ui8iMemory24Bits << I2S_AIFFMTCFG_MEM_LEN_24_S) |
+ (ui8iSamplingEdge << I2S_AIFFMTCFG_SMPL_EDGE_S ) |
+ (boolDualPhase << I2S_AIFFMTCFG_DUAL_PHASE_S) |
+ (ui8BitsPerSample << I2S_AIFFMTCFG_WORD_LEN_S );
+
+ // Number of WCLK periods before the first read / write
+ HWREGH(I2S0_BASE + I2S_O_STMPWPER) = ui16transmissionDelay;
+}
+
+//****************************************************************************
+//
+//! \brief Setup the two interfaces SD0 and SD1 (also called AD0 and AD1).
+//!
+//! This function sets interface's direction and activated channels.
+//!
+//! \param ui32Base is base address of the I2S module.
+//! \param ui8StatusAD0 defines the usage of AD0
+//! 0x00: AD0 is disabled
+//! 0x01, AD0 is an input
+//! 0x02, AD0 is an output
+//! \param ui8ChanAD0 defines the channel mask for AD0.
+//! Use a bitwise OR'ed combination of:
+//! - \ref I2S_CHAN0_MASK
+//! - \ref I2S_CHAN1_MASK
+//! - \ref I2S_CHAN2_MASK
+//! - \ref I2S_CHAN3_MASK
+//! - \ref I2S_CHAN4_MASK
+//! - \ref I2S_CHAN5_MASK
+//! - \ref I2S_CHAN6_MASK
+//! - \ref I2S_CHAN7_MASK
+//! \param ui8StatusAD1 defines the usage of AD1
+//! 0x00: AD1 is disabled
+//! 0x10, AD1 is an input
+//! 0x20, AD1 is an output
+//! \param ui8ChanAD1 defines the channel mask for AD1.
+//! Use a bitwise OR'ed combination of:
+//! - \ref I2S_CHAN0_MASK
+//! - \ref I2S_CHAN1_MASK
+//! - \ref I2S_CHAN2_MASK
+//! - \ref I2S_CHAN3_MASK
+//! - \ref I2S_CHAN4_MASK
+//! - \ref I2S_CHAN5_MASK
+//! - \ref I2S_CHAN6_MASK
+//! - \ref I2S_CHAN7_MASK
+//!
+//! \return None
+//!
+//! \sa \ref I2SFormatConfigure()
+//
+//****************************************************************************
+__STATIC_INLINE void
+I2SFrameConfigure(uint32_t ui32Base,
+ uint8_t ui8StatusAD0, uint8_t ui8ChanAD0,
+ uint8_t ui8StatusAD1, uint8_t ui8ChanAD1)
+{
+ // Check the arguments.
+ ASSERT(I2SBaseValid(ui32Base));
+
+ // Configure input/output channels.
+ HWREGB(I2S0_BASE + I2S_O_AIFDIRCFG) = (ui8StatusAD0 | ui8StatusAD1);
+
+ // Configure the valid channel mask.
+ HWREGB(I2S0_BASE + I2S_O_AIFWMASK0) = ui8ChanAD0;
+ HWREGB(I2S0_BASE + I2S_O_AIFWMASK1) = ui8ChanAD1;
+}
+
+//****************************************************************************
+//
+//! \brief Configure the I2S frame clock (also called WCLK or WS).
+//!
+//! Configure WCLK clock to be either internal (master) or external (slave).
+//! Configure WCLK clock either normal or inverted.
+//!
+//! \note The bit clock configuration is done externally, but the internal/
+//! external setting must match what is chosen internally in the I2S module
+//! for the frame clock.
+//!
+//! \param ui32Base is the base address of the I2S module.
+//! \param boolMaster false: the device is a slave (external clock)
+//! true: the device is a master (internal clock)
+//! \param boolWCLKInvert false: WCLK is not inverted
+//! true: WCLK is internally inverted
+//!
+//! \return None
+//
+//****************************************************************************
+__STATIC_INLINE void
+I2SWclkConfigure(uint32_t ui32Base,
+ bool boolMaster,
+ bool boolWCLKInvert)
+{
+ // Check the arguments.
+ ASSERT(I2SBaseValid(ui32Base));
+ ASSERT(ui8ClkSource < I2S_AIFWCLKSRC_WCLK_SRC_RESERVED);
+
+ // if(boolMaster == 0) then ui8ClkSource = 1
+ // if(boolMaster == 1) then ui8ClkSource = 2
+ uint8_t ui8ClkSource = (uint8_t)boolMaster + 0x01;
+
+ // Setup register WCLK Source.
+ HWREGB(I2S0_BASE + I2S_O_AIFWCLKSRC) =
+ ((ui8ClkSource << I2S_AIFWCLKSRC_WCLK_SRC_S) |
+ (boolWCLKInvert << I2S_AIFWCLKSRC_WCLK_INV_S ));
+}
+
+//****************************************************************************
+//
+//! \brief Set the input buffer pointer.
+//!
+//! The next pointer should always be written while the DMA is using the
+//! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR
+//! will occur and all inputs and outputs will be disabled.
+//! This function relies on pointer is pointing to a valid address.
+//!
+//! \note It is recommended that the pointer update is done in an interrupt context
+//! to ensure that the update is performed before the buffer is full.
+//!
+//! \param ui32Base is the base address of the I2S module.
+//! \param ui32NextPointer is the adress of the data
+//!
+//! \return None
+//!
+//! \sa \ref I2SOutPointerSet()
+//
+//****************************************************************************
+__STATIC_INLINE void
+I2SInPointerSet(uint32_t ui32Base, uint32_t ui32NextPointer)
+{
+ // Check the arguments.
+ ASSERT(I2SBaseValid(ui32Base));
+
+ HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT) = ui32NextPointer;
+}
+
+//****************************************************************************
+//
+//! \brief Set the output buffer pointer.
+//!
+//! The next pointer should always be written while the DMA is using the
+//! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR
+//! will occur and all inputs and outputs will be disabled.
+//! This function relies on pointer is pointing to a valid address.
+//!
+//! \note It is recommended that the pointer update is done in an interrupt context
+//! to ensure that the update is performed before the buffer is full.
+//!
+//! \param ui32Base is the base address of the I2S module.
+//! \param ui32NextPointer is the adress of the data
+//!
+//! \return None
+//!
+//! \sa \ref I2SInPointerSet()
+//
+//****************************************************************************
+__STATIC_INLINE void
+I2SOutPointerSet(uint32_t ui32Base, uint32_t ui32NextPointer)
+{
+ // Check the arguments.
+ ASSERT(I2SBaseValid(ui32Base));
+
+ HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT) = ui32NextPointer;
+}
+
+//****************************************************************************
+//
+//! \brief Get value stored in PTR NEXT IN register
+//!
+//! \param ui32Base is the base address of the I2S module.
+//!
+//! \return the value of PTR NEXT IN.
+//
+//****************************************************************************
+__STATIC_INLINE uint32_t
+I2SInPointerNextGet(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(I2SBaseValid(ui32Base));
+
+ return (HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT));
+}
+
+
+//****************************************************************************
+//
+//! \brief Get value stored in PTR NEXT OUT register
+//!
+//! \param ui32Base is the base address of the I2S module.
+//!
+//! \return the value of PTR NEXT OUT.
+//
+//****************************************************************************
+__STATIC_INLINE uint32_t
+I2SOutPointerNextGet(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(I2SBaseValid(ui32Base));
+
+ return (HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT));
+}
+
+//****************************************************************************
+//
+//! \brief Get value stored in PTR IN register
+//!
+//! \param ui32Base is the base address of the I2S module.
+//!
+//! \return the value of PTR IN.
+//
+//****************************************************************************
+__STATIC_INLINE uint32_t
+I2SInPointerGet(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(I2SBaseValid(ui32Base));
+
+ return (HWREG(I2S0_BASE + I2S_O_AIFINPTR));
+}
+
+//****************************************************************************
+//
+//! \brief Get value stored in PTR OUT register
+//!
+//! \param ui32Base is the base address of the I2S module.
+//!
+//! \return the value of PTR OUT.
+//
+//****************************************************************************
+__STATIC_INLINE uint32_t
+I2SOutPointerGet(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(I2SBaseValid(ui32Base));
+
+ return (HWREG(I2S0_BASE + I2S_O_AIFOUTPTR));
+}
+
+//*****************************************************************************
+//
+//! \brief Configure the IN sample stamp generator.
+//!
+//! Use this function to configure the sample stamp generator.
+//!
+//! \param ui32Base is the base address of the I2S module.
+//! \param ui16TrigValue value used to set the trigger.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+I2SSampleStampInConfigure(uint32_t ui32Base, uint16_t ui16TrigValue)
+{
+ // Check the arguments.
+ ASSERT(I2SBaseValid(ui32Base));
+
+ // Setup the sample stamp trigger for input streams.
+ HWREGH(I2S0_BASE + I2S_O_STMPINTRIG) = ui16TrigValue;
+}
+
+//*****************************************************************************
+//
+//! \brief Configure the OUT sample stamp generator.
+//!
+//! Use this function to configure the sample stamp generator.
+//!
+//! \param ui32Base is the base address of the I2S module.
+//! \param ui16TrigValue value used to set the trigger.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+I2SSampleStampOutConfigure(uint32_t ui32Base, uint16_t ui16TrigValue)
+{
+ // Check the arguments.
+ ASSERT(I2SBaseValid(ui32Base));
+
+ // Setup the sample stamp trigger for output streams.
+ HWREGH(I2S0_BASE + I2S_O_STMPOUTTRIG) = ui16TrigValue;
+}
+
+//*****************************************************************************
+//
+//! \brief Add the specified value to the WCLK count.
+//!
+//! \param ui32Base is the base address of the I2S module.
+//! \param i16Value is the offset to add to the counter (this value can be negative)
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+I2SWclkCounterConfigure(uint32_t ui32Base, int16_t i16Value)
+{
+ uint16_t ui16MinusValue;
+
+ // Check the arguments.
+ ASSERT(I2SBaseValid(ui32Base));
+
+ if (i16Value >= 0)
+ {
+ HWREGH(I2S0_BASE + I2S_O_STMPWADD) = i16Value;
+ }
+ else
+ {
+ ui16MinusValue = (uint16_t)(-i16Value);
+ HWREGH(I2S0_BASE + I2S_O_STMPWADD) = HWREGH(I2S0_BASE + I2S_O_STMPWPER) - ui16MinusValue;
+ }
+}
+
+//*****************************************************************************
+//
+//! \brief Reset the WCLK count.
+//!
+//! \param ui32Base is the base address of the I2S module.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+I2SWclkCounterReset(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(I2SBaseValid(ui32Base));
+
+ HWREGH(I2S0_BASE + I2S_O_STMPWSET) = 0;
+}
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// Redirect to implementation in ROM when available.
+//
+//*****************************************************************************
+#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
+ #include "../driverlib/rom.h"
+ #ifdef ROM_I2SEnable
+ #undef I2SEnable
+ #define I2SEnable ROM_I2SEnable
+ #endif
+ #ifdef ROM_I2SAudioFormatConfigure
+ #undef I2SAudioFormatConfigure
+ #define I2SAudioFormatConfigure ROM_I2SAudioFormatConfigure
+ #endif
+ #ifdef ROM_I2SChannelConfigure
+ #undef I2SChannelConfigure
+ #define I2SChannelConfigure ROM_I2SChannelConfigure
+ #endif
+ #ifdef ROM_I2SBufferConfig
+ #undef I2SBufferConfig
+ #define I2SBufferConfig ROM_I2SBufferConfig
+ #endif
+ #ifdef ROM_I2SPointerUpdate
+ #undef I2SPointerUpdate
+ #define I2SPointerUpdate ROM_I2SPointerUpdate
+ #endif
+ #ifdef ROM_I2SPointerSet
+ #undef I2SPointerSet
+ #define I2SPointerSet ROM_I2SPointerSet
+ #endif
+ #ifdef ROM_I2SSampleStampConfigure
+ #undef I2SSampleStampConfigure
+ #define I2SSampleStampConfigure ROM_I2SSampleStampConfigure
+ #endif
+ #ifdef ROM_I2SSampleStampGet
+ #undef I2SSampleStampGet
+ #define I2SSampleStampGet ROM_I2SSampleStampGet
+ #endif
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __I2S_H__
+
+//****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2s_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2s_doc.h
new file mode 100644
index 0000000..5f2e1d9
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2s_doc.h
@@ -0,0 +1,141 @@
+/******************************************************************************
+* Filename: i2s_doc.h
+* Revised: $$
+* Revision: $$
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+//! \addtogroup i2s_api
+//! @{
+//! \section sec_i2s Introduction
+//!
+//! The I2S API provides a set of functions for using the I2S module.
+//! This module provides a standardized serial interface to transfer
+//! audio samples from and to external audio devices such as a codec,
+//! DAC, or ADC.
+//!
+//! The I2S module has the following features:
+//! - Audio clock signals are internally generated by the PRCM module
+//! or externally by another device.
+//! - One or two data pins, which can be configured independently as
+//! input or output
+//! - Various data formats according to the settings of the module
+//! - Up to two channels per data pin for dual phase formats and up
+//! to eight channels per data pin for single phase formats
+//! - DMA with double-buffered pointers
+//! - Error detection for DMA and audio clock signal integrity
+//! - A Samplestamp generator that allows maintaining of constant
+//! audio latency
+//!
+//! The I2S module is configured through the functions \ref I2SFormatConfigure(),
+//! \ref I2SFrameConfigure() and \ref I2SWclkConfigure().
+//! Transfers are enabled using \ref I2SStart(). Transfers are disabled using
+//! \ref I2SStop(). Please note that a specific procedure exists in order
+//! to disable transfers without losing data (refer to \ref I2SStop()).
+//!
+//! Data are transmitted using the two double-buffered pointers.
+//! For each interface, two registers are set with the address of the data to
+//! transfer. These registers are named INPTR and INPTRNEXT for the input
+//! interface and OUTPTR and OUTPTRNEXT for the output. When PTR is consumed,
+//! the hardware copies the content of PTRNEXT into PTR and the next transfer
+//! begins.
+//! The address of the next value to write or to read in memory (i.e. to receive
+//! or to send out) is set using \ref I2SInPointerSet() and \ref I2SOutPointerSet().
+//! The values contented by INPTRNEXT, OUTPTRNEXT, INPTR and OUTPTR can be read using
+//! \ref I2SInPointerNextGet(), \ref I2SOutPointerNextGet(), \ref I2SInPointerGet() and
+//! \ref I2SOutPointerGet() functions.
+//!
+//! Interrupts can help the user to refresh pointers on time. Interrupts can also
+//! be used to detect I2S errors. \ref I2SIntEnable() and \ref I2SIntDisable()
+//! activate and deactivate interrupt(s). Interrupt status can be read through
+//! \ref I2SIntStatus() and a pending interrupt can be acquitted by
+//! \ref I2SIntClear() function.
+//!
+//! The sample stamps generator can be configured to slightly delay the
+//! emission or the reception of the data (based on the number of WCLK
+//! cycles) using \ref I2SSampleStampInConfigure(), \ref I2SSampleStampOutConfigure(),
+//! \ref I2SWclkCounterReset() and \ref I2SWclkCounterConfigure(). The current sample stamp
+//! can be computed using \ref I2SSampleStampGet().
+//! To finish, the sample stamps generator can be enable and disable using
+//! the following functions: \ref I2SSampleStampEnable() and
+//! \ref I2SSampleStampDisable().
+//! The sample stamps generator must be enabled prior to any transfer.
+//!
+//! Note: Other functions contained in the PRCM API are required to handle I2S.
+//!
+//! \section sec_i2s_api API
+//!
+//! Two APIs are coexisting.
+//! It is recommended to only use the new API as the old one is deprecated and
+//! will be removed soon.
+//!
+//! New API:
+//! Functions to perform I2S configuration:
+//! - \ref I2SStart()
+//! - \ref I2SStop()
+//! - \ref I2SFormatConfigure()
+//! - \ref I2SFrameConfigure()
+//! - \ref I2SWclkConfigure()
+//!
+//! Functions to perform transfers:
+//! - \ref I2SInPointerSet()
+//! - \ref I2SOutPointerSet()
+//! - \ref I2SInPointerGet()
+//! - \ref I2SOutPointerGet()
+//! - \ref I2SInPointerNextGet()
+//! - \ref I2SOutPointerNextGet()
+//!
+//! Functions to handle interruptions:
+//! - \ref I2SIntEnable()
+//! - \ref I2SIntDisable()
+//! - \ref I2SIntStatus()
+//! - \ref I2SIntClear()
+//!
+//! Functions to handle sample stamps
+//! - \ref I2SSampleStampEnable()
+//! - \ref I2SSampleStampDisable()
+//! - \ref I2SSampleStampInConfigure()
+//! - \ref I2SSampleStampOutConfigure()
+//! - \ref I2SSampleStampGet()
+//! - \ref I2SWclkCounterConfigure()
+//! - \ref I2SWclkCounterReset()
+//!
+//! Old API:
+//! \ref I2SEnable(), \ref I2SDisable(), \ref I2SAudioFormatConfigure(),
+//! \ref I2SChannelConfigure(), \ref I2SClockConfigure(),
+//! \ref I2SBufferConfig(), \ref I2SIntEnable(), \ref I2SIntDisable(),
+//! \ref I2SIntStatus(), \ref I2SIntClear(), \ref I2SSampleStampEnable(),
+//! \ref I2SSampleStampDisable(), \ref I2SSampleStampGet(),
+//! \ref I2SPointerSet (), \ref I2SPointerUpdate(),
+//! \ref I2SSampleStampConfigure(), \ref I2SIntRegister(),
+//! \ref I2SIntUnregister()
+//!
+//! @}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/interrupt.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/interrupt.c
new file mode 100644
index 0000000..d0cd9bc
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/interrupt.c
@@ -0,0 +1,469 @@
+/******************************************************************************
+* Filename: interrupt.c
+* Revised: 2017-05-19 11:31:39 +0200 (Fri, 19 May 2017)
+* Revision: 49017
+*
+* Description: Driver for the NVIC Interrupt Controller.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "interrupt.h"
+
+//*****************************************************************************
+//
+// Handle support for DriverLib in ROM:
+// This section will undo prototype renaming made in the header file
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #undef IntRegister
+ #define IntRegister NOROM_IntRegister
+ #undef IntUnregister
+ #define IntUnregister NOROM_IntUnregister
+ #undef IntPriorityGroupingSet
+ #define IntPriorityGroupingSet NOROM_IntPriorityGroupingSet
+ #undef IntPriorityGroupingGet
+ #define IntPriorityGroupingGet NOROM_IntPriorityGroupingGet
+ #undef IntPrioritySet
+ #define IntPrioritySet NOROM_IntPrioritySet
+ #undef IntPriorityGet
+ #define IntPriorityGet NOROM_IntPriorityGet
+ #undef IntEnable
+ #define IntEnable NOROM_IntEnable
+ #undef IntDisable
+ #define IntDisable NOROM_IntDisable
+ #undef IntPendSet
+ #define IntPendSet NOROM_IntPendSet
+ #undef IntPendGet
+ #define IntPendGet NOROM_IntPendGet
+ #undef IntPendClear
+ #define IntPendClear NOROM_IntPendClear
+#endif
+
+//*****************************************************************************
+//
+//! This is a mapping between priority grouping encodings and the number of
+//! preemption priority bits.
+//
+//*****************************************************************************
+static const uint32_t g_pui32Priority[] =
+{
+ NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6,
+ NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3,
+ NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1
+};
+
+//*****************************************************************************
+//
+//! This is a mapping between interrupt number and the register that contains
+//! the priority encoding for that interrupt.
+//
+//*****************************************************************************
+static const uint32_t g_pui32Regs[] =
+{
+ 0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1,
+ NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7,
+ NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13
+};
+
+//*****************************************************************************
+//
+//! \brief The default interrupt handler.
+//!
+//! This is the default interrupt handler for all interrupts. It simply loops
+//! forever so that the system state is preserved for observation by a
+//! debugger. Since interrupts should be disabled before unregistering the
+//! corresponding handler, this should never be called.
+//!
+//! \return None
+//
+//*****************************************************************************
+static void
+IntDefaultHandler(void)
+{
+ // Go into an infinite loop.
+ while(1)
+ {
+ }
+}
+
+//*****************************************************************************
+//
+//! \brief Global pointer to the (dynamic) interrupt vector table when placed in SRAM.
+//!
+//! Interrupt vector table is placed at "vtable_ram" defined in the linker file
+//! provided by Texas Instruments. By default, this is at the beginning of SRAM.
+//!
+//! \note See \ti_code{interrupt.c} for compiler specific implementation!
+//
+//*****************************************************************************
+#if defined(DOXYGEN)
+// Dummy void pointer used as placeholder to generate Doxygen documentation.
+void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
+#elif defined(__IAR_SYSTEMS_ICC__)
+#pragma data_alignment=256
+static __no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) @ ".vtable_ram";
+#elif defined(__TI_COMPILER_VERSION__)
+#pragma DATA_ALIGN(g_pfnRAMVectors, 256)
+#pragma DATA_SECTION(g_pfnRAMVectors, ".vtable_ram")
+void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
+#elif defined (__CC_ARM)
+static __attribute__((section("vtable_ram")))
+void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__((aligned(256)));
+#else
+static __attribute__((section("vtable_ram")))
+void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__((aligned(256)));
+#endif
+
+//*****************************************************************************
+//
+// Registers a function to be called when an interrupt occurs.
+//
+//*****************************************************************************
+void
+IntRegister(uint32_t ui32Interrupt, void (*pfnHandler)(void))
+{
+ uint32_t ui32Idx, ui32Value;
+
+ // Check the arguments.
+ ASSERT(ui32Interrupt < NUM_INTERRUPTS);
+
+ // Make sure that the RAM vector table is correctly aligned.
+ ASSERT(((uint32_t)g_pfnRAMVectors & 0x000000ff) == 0);
+
+ // See if the RAM vector table has been initialized.
+ if(HWREG(NVIC_VTABLE) != (uint32_t)g_pfnRAMVectors)
+ {
+ // Copy the vector table from the beginning of FLASH to the RAM vector
+ // table.
+ ui32Value = HWREG(NVIC_VTABLE);
+ for(ui32Idx = 0; ui32Idx < NUM_INTERRUPTS; ui32Idx++)
+ {
+ g_pfnRAMVectors[ui32Idx] = (void (*)(void))HWREG((ui32Idx * 4) +
+ ui32Value);
+ }
+
+ // Point NVIC at the RAM vector table.
+ HWREG(NVIC_VTABLE) = (uint32_t)g_pfnRAMVectors;
+ }
+
+ // Save the interrupt handler.
+ g_pfnRAMVectors[ui32Interrupt] = pfnHandler;
+}
+
+//*****************************************************************************
+//
+// Unregisters the function to be called when an interrupt occurs.
+//
+//*****************************************************************************
+void
+IntUnregister(uint32_t ui32Interrupt)
+{
+ // Check the arguments.
+ ASSERT(ui32Interrupt < NUM_INTERRUPTS);
+
+ // Reset the interrupt handler.
+ g_pfnRAMVectors[ui32Interrupt] = IntDefaultHandler;
+}
+
+//*****************************************************************************
+//
+// Sets the priority grouping of the interrupt controller.
+//
+//*****************************************************************************
+void
+IntPriorityGroupingSet(uint32_t ui32Bits)
+{
+ // Check the arguments.
+ ASSERT(ui32Bits < NUM_PRIORITY);
+
+ // Set the priority grouping.
+ HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pui32Priority[ui32Bits];
+}
+
+//*****************************************************************************
+//
+// Gets the priority grouping of the interrupt controller
+//
+//*****************************************************************************
+uint32_t
+IntPriorityGroupingGet(void)
+{
+ uint32_t ui32Loop, ui32Value;
+
+ // Read the priority grouping.
+ ui32Value = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M;
+
+ // Loop through the priority grouping values.
+ for(ui32Loop = 0; ui32Loop < NUM_PRIORITY; ui32Loop++)
+ {
+ // Stop looping if this value matches.
+ if(ui32Value == g_pui32Priority[ui32Loop])
+ {
+ break;
+ }
+ }
+
+ // Return the number of priority bits.
+ return(ui32Loop);
+}
+
+//*****************************************************************************
+//
+// Sets the priority of an interrupt
+//
+//*****************************************************************************
+void
+IntPrioritySet(uint32_t ui32Interrupt, uint8_t ui8Priority)
+{
+ uint32_t ui32Temp;
+
+ // Check the arguments.
+ ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS));
+ ASSERT(ui8Priority <= INT_PRI_LEVEL7);
+
+ // Set the interrupt priority.
+ ui32Temp = HWREG(g_pui32Regs[ui32Interrupt >> 2]);
+ ui32Temp &= ~(0xFF << (8 * (ui32Interrupt & 3)));
+ ui32Temp |= ui8Priority << (8 * (ui32Interrupt & 3));
+ HWREG(g_pui32Regs[ui32Interrupt >> 2]) = ui32Temp;
+}
+
+//*****************************************************************************
+//
+// Gets the priority of an interrupt
+//
+//*****************************************************************************
+int32_t
+IntPriorityGet(uint32_t ui32Interrupt)
+{
+ // Check the arguments.
+ ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS));
+
+ // Return the interrupt priority.
+ return((HWREG(g_pui32Regs[ui32Interrupt >> 2]) >> (8 * (ui32Interrupt & 3))) &
+ 0xFF);
+}
+
+//*****************************************************************************
+//
+// Enables an interrupt
+//
+//*****************************************************************************
+void
+IntEnable(uint32_t ui32Interrupt)
+{
+ // Check the arguments.
+ ASSERT(ui32Interrupt < NUM_INTERRUPTS);
+
+ // Determine the interrupt to enable.
+ if(ui32Interrupt == INT_MEMMANAGE_FAULT)
+ {
+ // Enable the MemManage interrupt.
+ HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM;
+ }
+ else if(ui32Interrupt == INT_BUS_FAULT)
+ {
+ // Enable the bus fault interrupt.
+ HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS;
+ }
+ else if(ui32Interrupt == INT_USAGE_FAULT)
+ {
+ // Enable the usage fault interrupt.
+ HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE;
+ }
+ else if(ui32Interrupt == INT_SYSTICK)
+ {
+ // Enable the System Tick interrupt.
+ HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
+ }
+ else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47))
+ {
+ // Enable the general interrupt.
+ HWREG(NVIC_EN0) = 1 << (ui32Interrupt - 16);
+ }
+ else if(ui32Interrupt >= 48)
+ {
+ // Enable the general interrupt.
+ HWREG(NVIC_EN1) = 1 << (ui32Interrupt - 48);
+ }
+}
+
+//*****************************************************************************
+//
+// Disables an interrupt
+//
+//*****************************************************************************
+void
+IntDisable(uint32_t ui32Interrupt)
+{
+ // Check the arguments.
+ ASSERT(ui32Interrupt < NUM_INTERRUPTS);
+
+ // Determine the interrupt to disable.
+ if(ui32Interrupt == INT_MEMMANAGE_FAULT)
+ {
+ // Disable the MemManage interrupt.
+ HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM);
+ }
+ else if(ui32Interrupt == INT_BUS_FAULT)
+ {
+ // Disable the bus fault interrupt.
+ HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS);
+ }
+ else if(ui32Interrupt == INT_USAGE_FAULT)
+ {
+ // Disable the usage fault interrupt.
+ HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE);
+ }
+ else if(ui32Interrupt == INT_SYSTICK)
+ {
+ // Disable the System Tick interrupt.
+ HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
+ }
+ else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47))
+ {
+ // Disable the general interrupt.
+ HWREG(NVIC_DIS0) = 1 << (ui32Interrupt - 16);
+ }
+ else if(ui32Interrupt >= 48)
+ {
+ // Disable the general interrupt.
+ HWREG(NVIC_DIS1) = 1 << (ui32Interrupt - 48);
+ }
+}
+
+//*****************************************************************************
+//
+// Pends an interrupt
+//
+//*****************************************************************************
+void
+IntPendSet(uint32_t ui32Interrupt)
+{
+ // Check the arguments.
+ ASSERT(ui32Interrupt < NUM_INTERRUPTS);
+
+ // Determine the interrupt to pend.
+ if(ui32Interrupt == INT_NMI_FAULT)
+ {
+ // Pend the NMI interrupt.
+ HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_NMI_SET;
+ }
+ else if(ui32Interrupt == INT_PENDSV)
+ {
+ // Pend the PendSV interrupt.
+ HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PEND_SV;
+ }
+ else if(ui32Interrupt == INT_SYSTICK)
+ {
+ // Pend the SysTick interrupt.
+ HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET;
+ }
+ else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47))
+ {
+ // Pend the general interrupt.
+ HWREG(NVIC_PEND0) = 1 << (ui32Interrupt - 16);
+ }
+ else if(ui32Interrupt >= 48)
+ {
+ // Pend the general interrupt.
+ HWREG(NVIC_PEND1) = 1 << (ui32Interrupt - 48);
+ }
+}
+
+//*****************************************************************************
+//
+// Query whether an interrupt is pending
+//
+//*****************************************************************************
+bool
+IntPendGet(uint32_t ui32Interrupt)
+{
+ uint32_t ui32IntPending;
+
+ // Check the arguments.
+ ASSERT(ui32Interrupt < NUM_INTERRUPTS);
+
+ // Assume no interrupts are pending.
+ ui32IntPending = 0;
+
+ // The lower 16 IRQ vectors are unsupported by this function
+ if (ui32Interrupt < 16)
+ {
+
+ return 0;
+ }
+
+ // Subtract lower 16 irq vectors
+ ui32Interrupt -= 16;
+
+ // Check if the interrupt is pending
+ ui32IntPending = HWREG(NVIC_PEND0 + (ui32Interrupt / 32));
+ ui32IntPending &= (1 << (ui32Interrupt & 31));
+
+ return ui32IntPending ? true : false;
+}
+
+//*****************************************************************************
+//
+// Unpends an interrupt
+//
+//*****************************************************************************
+void
+IntPendClear(uint32_t ui32Interrupt)
+{
+ // Check the arguments.
+ ASSERT(ui32Interrupt < NUM_INTERRUPTS);
+
+ // Determine the interrupt to unpend.
+ if(ui32Interrupt == INT_PENDSV)
+ {
+ // Unpend the PendSV interrupt.
+ HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_UNPEND_SV;
+ }
+ else if(ui32Interrupt == INT_SYSTICK)
+ {
+ // Unpend the SysTick interrupt.
+ HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR;
+ }
+ else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47))
+ {
+ // Unpend the general interrupt.
+ HWREG(NVIC_UNPEND0) = 1 << (ui32Interrupt - 16);
+ }
+ else if(ui32Interrupt >= 48)
+ {
+ // Unpend the general interrupt.
+ HWREG(NVIC_UNPEND1) = 1 << (ui32Interrupt - 48);
+ }
+}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/interrupt.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/interrupt.h
new file mode 100644
index 0000000..3a2d1dd
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/interrupt.h
@@ -0,0 +1,718 @@
+/******************************************************************************
+* Filename: interrupt.h
+* Revised: 2017-11-14 15:26:03 +0100 (Tue, 14 Nov 2017)
+* Revision: 50272
+*
+* Description: Defines and prototypes for the NVIC Interrupt Controller
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup system_cpu_group
+//! @{
+//! \addtogroup interrupt_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __INTERRUPT_H__
+#define __INTERRUPT_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "../inc/hw_ints.h"
+#include "../inc/hw_types.h"
+#include "../inc/hw_nvic.h"
+#include "debug.h"
+#include "cpu.h"
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// This section renames all functions that are not "static inline", so that
+// calling these functions will default to implementation in flash. At the end
+// of this file a second renaming will change the defaults to implementation in
+// ROM for available functions.
+//
+// To force use of the implementation in flash, e.g. for debugging:
+// - Globally: Define DRIVERLIB_NOROM at project level
+// - Per function: Use prefix "NOROM_" when calling the function
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #define IntRegister NOROM_IntRegister
+ #define IntUnregister NOROM_IntUnregister
+ #define IntPriorityGroupingSet NOROM_IntPriorityGroupingSet
+ #define IntPriorityGroupingGet NOROM_IntPriorityGroupingGet
+ #define IntPrioritySet NOROM_IntPrioritySet
+ #define IntPriorityGet NOROM_IntPriorityGet
+ #define IntEnable NOROM_IntEnable
+ #define IntDisable NOROM_IntDisable
+ #define IntPendSet NOROM_IntPendSet
+ #define IntPendGet NOROM_IntPendGet
+ #define IntPendClear NOROM_IntPendClear
+#endif
+
+//*****************************************************************************
+//
+// Macro to generate an interrupt priority mask based on the number of bits
+// of priority supported by the hardware. For CC26xx the number of priority
+// bit is 3 as defined in <tt>hw_types.h</tt>. The priority mask is
+// defined as
+//
+// INT_PRIORITY_MASK = ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF)
+//
+//*****************************************************************************
+#define INT_PRIORITY_MASK 0x000000E0
+#define INT_PRI_LEVEL0 0x00000000
+#define INT_PRI_LEVEL1 0x00000020
+#define INT_PRI_LEVEL2 0x00000040
+#define INT_PRI_LEVEL3 0x00000060
+#define INT_PRI_LEVEL4 0x00000080
+#define INT_PRI_LEVEL5 0x000000A0
+#define INT_PRI_LEVEL6 0x000000C0
+#define INT_PRI_LEVEL7 0x000000E0
+
+//*****************************************************************************
+//
+// API Functions and prototypes
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \brief Registers a function as an interrupt handler in the dynamic vector table.
+//!
+//! \note Only use this function if you want to use the dynamic vector table (in SRAM)!
+//!
+//! This function writes a function pointer to the dynamic interrupt vector table
+//! in SRAM to register the function as an interrupt handler (ISR). When the corresponding
+//! interrupt occurs, and it has been enabled (see \ref IntEnable()), the function
+//! pointer is fetched from the dynamic vector table, and the System CPU will
+//! execute the interrupt handler.
+//!
+//! \note The first call to this function (directly or indirectly via a peripheral
+//! driver interrupt register function) copies the interrupt vector table from
+//! Flash to SRAM. NVIC uses the static vector table (in Flash) until this function
+//! is called.
+//!
+//! \param ui32Interrupt specifies the index in the vector table to modify.
+//! - System exceptions (vectors 0 to 15):
+//! - INT_NMI_FAULT
+//! - INT_HARD_FAULT
+//! - INT_MEMMANAGE_FAULT
+//! - INT_BUS_FAULT
+//! - INT_USAGE_FAULT
+//! - INT_SVCALL
+//! - INT_DEBUG
+//! - INT_PENDSV
+//! - INT_SYSTICK
+//! - Interrupts (vectors >15):
+//! - INT_AON_GPIO_EDGE
+//! - INT_I2C_IRQ
+//! - INT_RFC_CPE_1
+//! - INT_PKA_IRQ
+//! - INT_AON_RTC_COMB
+//! - INT_UART0_COMB
+//! - INT_AUX_SWEV0
+//! - INT_SSI0_COMB
+//! - INT_SSI1_COMB
+//! - INT_RFC_CPE_0
+//! - INT_RFC_HW_COMB
+//! - INT_RFC_CMD_ACK
+//! - INT_I2S_IRQ
+//! - INT_AUX_SWEV1
+//! - INT_WDT_IRQ
+//! - INT_GPT0A
+//! - INT_GPT0B
+//! - INT_GPT1A
+//! - INT_GPT1B
+//! - INT_GPT2A
+//! - INT_GPT2B
+//! - INT_GPT3A
+//! - INT_GPT3B
+//! - INT_CRYPTO_RESULT_AVAIL_IRQ
+//! - INT_DMA_DONE_COMB
+//! - INT_DMA_ERR
+//! - INT_FLASH
+//! - INT_SWEV0
+//! - INT_AUX_COMB
+//! - INT_AON_PROG0
+//! - INT_PROG0 (Programmable interrupt, see \ref EventRegister())
+//! - INT_AUX_COMPA
+//! - INT_AUX_ADC_IRQ
+//! - INT_TRNG_IRQ
+//! - INT_OSC_COMB
+//! - INT_AUX_TIMER2_EV0
+//! - INT_UART1_COMB
+//! - INT_BATMON_COMB
+//! \param pfnHandler is a pointer to the function to register as interrupt handler.
+//!
+//! \return None.
+//!
+//! \sa \ref IntUnregister(), \ref IntEnable()
+//
+//*****************************************************************************
+extern void IntRegister(uint32_t ui32Interrupt, void (*pfnHandler)(void));
+
+//*****************************************************************************
+//
+//! \brief Unregisters an interrupt handler in the dynamic vector table.
+//!
+//! This function removes an interrupt handler from the dynamic vector table and
+//! replaces it with the default interrupt handler \ref IntDefaultHandler().
+//!
+//! \note Remember to disable the interrupt before removing its interrupt handler
+//! from the vector table.
+//!
+//! \param ui32Interrupt specifies the index in the vector table to modify.
+//! - See \ref IntRegister() for list of valid arguments.
+//!
+//! \return None.
+//!
+//! \sa \ref IntRegister(), \ref IntDisable()
+//
+//*****************************************************************************
+extern void IntUnregister(uint32_t ui32Interrupt);
+
+//*****************************************************************************
+//
+//! \brief Sets the priority grouping of the interrupt controller.
+//!
+//! This function specifies the split between preemptable priority levels and
+//! subpriority levels in the interrupt priority specification.
+//!
+//! Three bits are available for hardware interrupt prioritization thus priority
+//! grouping values of three through seven have the same effect.
+//!
+//! \param ui32Bits specifies the number of bits of preemptable priority.
+//! - 0 : No pre-emption priority, eight bits of subpriority.
+//! - 1 : One bit of pre-emption priority, seven bits of subpriority
+//! - 2 : Two bits of pre-emption priority, six bits of subpriority
+//! - 3-7 : Three bits of pre-emption priority, five bits of subpriority
+//!
+//! \return None
+//!
+//! \sa \ref IntPrioritySet()
+//
+//*****************************************************************************
+extern void IntPriorityGroupingSet(uint32_t ui32Bits);
+
+//*****************************************************************************
+//
+//! \brief Gets the priority grouping of the interrupt controller.
+//!
+//! This function returns the split between preemptable priority levels and
+//! subpriority levels in the interrupt priority specification.
+//!
+//! \return Returns the number of bits of preemptable priority.
+//! - 0 : No pre-emption priority, eight bits of subpriority.
+//! - 1 : One bit of pre-emption priority, seven bits of subpriority
+//! - 2 : Two bits of pre-emption priority, six bits of subpriority
+//! - 3-7 : Three bits of pre-emption priority, five bits of subpriority
+//
+//*****************************************************************************
+extern uint32_t IntPriorityGroupingGet(void);
+
+//*****************************************************************************
+//
+//! \brief Sets the priority of an interrupt.
+//!
+//! This function sets the priority of an interrupt, including system exceptions.
+//! When multiple interrupts are asserted simultaneously, the ones with the highest
+//! priority are processed before the lower priority interrupts. Smaller numbers
+//! correspond to higher interrupt priorities thus priority 0 is the highest
+//! interrupt priority.
+//!
+//! \warning This function does not support setting priority of interrupt vectors
+//! one through three which are:
+//! - 1: Reset handler
+//! - 2: NMI handler
+//! - 3: Hard fault handler
+//!
+//! \param ui32Interrupt specifies the index in the vector table to change priority for.
+//! - System exceptions:
+//! - INT_MEMMANAGE_FAULT
+//! - INT_BUS_FAULT
+//! - INT_USAGE_FAULT
+//! - INT_SVCALL
+//! - INT_DEBUG
+//! - INT_PENDSV
+//! - INT_SYSTICK
+//! - Interrupts:
+//! - INT_AON_GPIO_EDGE
+//! - INT_I2C_IRQ
+//! - INT_RFC_CPE_1
+//! - INT_PKA_IRQ
+//! - INT_AON_RTC_COMB
+//! - INT_UART0_COMB
+//! - INT_AUX_SWEV0
+//! - INT_SSI0_COMB
+//! - INT_SSI1_COMB
+//! - INT_RFC_CPE_0
+//! - INT_RFC_HW_COMB
+//! - INT_RFC_CMD_ACK
+//! - INT_I2S_IRQ
+//! - INT_AUX_SWEV1
+//! - INT_WDT_IRQ
+//! - INT_GPT0A
+//! - INT_GPT0B
+//! - INT_GPT1A
+//! - INT_GPT1B
+//! - INT_GPT2A
+//! - INT_GPT2B
+//! - INT_GPT3A
+//! - INT_GPT3B
+//! - INT_CRYPTO_RESULT_AVAIL_IRQ
+//! - INT_DMA_DONE_COMB
+//! - INT_DMA_ERR
+//! - INT_FLASH
+//! - INT_SWEV0
+//! - INT_AUX_COMB
+//! - INT_AON_PROG0
+//! - INT_PROG0 (Programmable interrupt, see \ref EventRegister())
+//! - INT_AUX_COMPA
+//! - INT_AUX_ADC_IRQ
+//! - INT_TRNG_IRQ
+//! - INT_OSC_COMB
+//! - INT_AUX_TIMER2_EV0
+//! - INT_UART1_COMB
+//! - INT_BATMON_COMB
+//! \param ui8Priority specifies the priority of the interrupt.
+//! - \ref INT_PRI_LEVEL0 : Highest priority.
+//! - \ref INT_PRI_LEVEL1
+//! - \ref INT_PRI_LEVEL2
+//! - \ref INT_PRI_LEVEL3
+//! - \ref INT_PRI_LEVEL4
+//! - \ref INT_PRI_LEVEL5
+//! - \ref INT_PRI_LEVEL6
+//! - \ref INT_PRI_LEVEL7 : Lowest priority.
+//!
+//! \return None
+//!
+//! \sa \ref IntPriorityGroupingSet()
+//
+//*****************************************************************************
+extern void IntPrioritySet(uint32_t ui32Interrupt, uint8_t ui8Priority);
+
+//*****************************************************************************
+//
+//! \brief Gets the priority of an interrupt.
+//!
+//! This function gets the priority of an interrupt.
+//!
+//! \warning This function does not support getting priority of interrupt vectors
+//! one through three which are:
+//! - 1: Reset handler
+//! - 2: NMI handler
+//! - 3: Hard fault handler
+//!
+//! \param ui32Interrupt specifies the index in the vector table to read priority of.
+//! - See \ref IntPrioritySet() for list of valid arguments.
+//!
+//! \return Returns the interrupt priority:
+//! - \ref INT_PRI_LEVEL0 : Highest priority.
+//! - \ref INT_PRI_LEVEL1
+//! - \ref INT_PRI_LEVEL2
+//! - \ref INT_PRI_LEVEL3
+//! - \ref INT_PRI_LEVEL4
+//! - \ref INT_PRI_LEVEL5
+//! - \ref INT_PRI_LEVEL6
+//! - \ref INT_PRI_LEVEL7 : Lowest priority.
+//
+//*****************************************************************************
+extern int32_t IntPriorityGet(uint32_t ui32Interrupt);
+
+//*****************************************************************************
+//
+//! \brief Enables an interrupt or system exception.
+//!
+//! This function enables the specified interrupt in the interrupt controller.
+//!
+//! \note If a fault condition occurs while the corresponding system exception
+//! is disabled, the fault is treated as a Hard Fault.
+//!
+//! \param ui32Interrupt specifies the index in the vector table to enable.
+//! - System exceptions:
+//! - INT_MEMMANAGE_FAULT
+//! - INT_BUS_FAULT
+//! - INT_USAGE_FAULT
+//! - INT_SYSTICK
+//! - Interrupts:
+//! - INT_AON_GPIO_EDGE
+//! - INT_I2C_IRQ
+//! - INT_RFC_CPE_1
+//! - INT_PKA_IRQ
+//! - INT_AON_RTC_COMB
+//! - INT_UART0_COMB
+//! - INT_AUX_SWEV0
+//! - INT_SSI0_COMB
+//! - INT_SSI1_COMB
+//! - INT_RFC_CPE_0
+//! - INT_RFC_HW_COMB
+//! - INT_RFC_CMD_ACK
+//! - INT_I2S_IRQ
+//! - INT_AUX_SWEV1
+//! - INT_WDT_IRQ
+//! - INT_GPT0A
+//! - INT_GPT0B
+//! - INT_GPT1A
+//! - INT_GPT1B
+//! - INT_GPT2A
+//! - INT_GPT2B
+//! - INT_GPT3A
+//! - INT_GPT3B
+//! - INT_CRYPTO_RESULT_AVAIL_IRQ
+//! - INT_DMA_DONE_COMB
+//! - INT_DMA_ERR
+//! - INT_FLASH
+//! - INT_SWEV0
+//! - INT_AUX_COMB
+//! - INT_AON_PROG0
+//! - INT_PROG0 (Programmable interrupt, see \ref EventRegister())
+//! - INT_AUX_COMPA
+//! - INT_AUX_ADC_IRQ
+//! - INT_TRNG_IRQ
+//! - INT_OSC_COMB
+//! - INT_AUX_TIMER2_EV0
+//! - INT_UART1_COMB
+//! - INT_BATMON_COMB
+//!
+//! \return None
+//!
+//! \sa \ref IntDisable()
+//
+//*****************************************************************************
+extern void IntEnable(uint32_t ui32Interrupt);
+
+//*****************************************************************************
+//
+//! \brief Disables an interrupt or system exception.
+//!
+//! This function disables the specified interrupt in the interrupt controller.
+//!
+//! \param ui32Interrupt specifies the index in the vector table to disable.
+//! - See \ref IntEnable() for list of valid arguments.
+//!
+//! \return None
+//!
+//! \sa \ref IntEnable()
+//
+//*****************************************************************************
+extern void IntDisable(uint32_t ui32Interrupt);
+
+//*****************************************************************************
+//
+//! \brief Pends an interrupt.
+//!
+//! This function pends the specified interrupt in the interrupt controller.
+//! This causes the interrupt controller to execute the corresponding interrupt
+//! handler at the next available time, based on the current interrupt state
+//! priorities.
+//!
+//! This interrupt controller automatically clears the pending interrupt once the
+//! interrupt handler is executed.
+//!
+//! \param ui32Interrupt specifies the index in the vector table to pend.
+//! - System exceptions:
+//! - INT_NMI_FAULT
+//! - INT_PENDSV
+//! - INT_SYSTICK
+//! - Interrupts:
+//! - INT_AON_GPIO_EDGE
+//! - INT_I2C_IRQ
+//! - INT_RFC_CPE_1
+//! - INT_PKA_IRQ
+//! - INT_AON_RTC_COMB
+//! - INT_UART0_COMB
+//! - INT_AUX_SWEV0
+//! - INT_SSI0_COMB
+//! - INT_SSI1_COMB
+//! - INT_RFC_CPE_0
+//! - INT_RFC_HW_COMB
+//! - INT_RFC_CMD_ACK
+//! - INT_I2S_IRQ
+//! - INT_AUX_SWEV1
+//! - INT_WDT_IRQ
+//! - INT_GPT0A
+//! - INT_GPT0B
+//! - INT_GPT1A
+//! - INT_GPT1B
+//! - INT_GPT2A
+//! - INT_GPT2B
+//! - INT_GPT3A
+//! - INT_GPT3B
+//! - INT_CRYPTO_RESULT_AVAIL_IRQ
+//! - INT_DMA_DONE_COMB
+//! - INT_DMA_ERR
+//! - INT_FLASH
+//! - INT_SWEV0
+//! - INT_AUX_COMB
+//! - INT_AON_PROG0
+//! - INT_PROG0 (Programmable interrupt, see \ref EventRegister())
+//! - INT_AUX_COMPA
+//! - INT_AUX_ADC_IRQ
+//! - INT_TRNG_IRQ
+//! - INT_OSC_COMB
+//! - INT_AUX_TIMER2_EV0
+//! - INT_UART1_COMB
+//! - INT_BATMON_COMB
+//!
+//! \return None
+//!
+//! \sa \ref IntEnable()
+//
+//*****************************************************************************
+extern void IntPendSet(uint32_t ui32Interrupt);
+
+//*****************************************************************************
+//
+//! \brief Checks if an interrupt is pending.
+//!
+//! This function checks the interrupt controller to see if an interrupt is pending.
+//!
+//! The interrupt must be enabled in order for the corresponding interrupt handler
+//! to be executed, so an interrupt can be pending waiting to be enabled or waiting
+//! for an interrupt of higher priority to be done executing.
+//!
+//! \note This function does not support reading pending status for system exceptions
+//! (vector table indexes <16).
+//!
+//! \param ui32Interrupt specifies the index in the vector table to check pending
+//! status for.
+//! - See \ref IntPendSet() for list of valid arguments (except system exceptions).
+//!
+//! \return Returns:
+//! - \c true : Specified interrupt is pending.
+//! - \c false : Specified interrupt is not pending.
+//
+//*****************************************************************************
+extern bool IntPendGet(uint32_t ui32Interrupt);
+
+//*****************************************************************************
+//
+//! \brief Unpends an interrupt.
+//!
+//! This function unpends the specified interrupt in the interrupt controller.
+//! This causes any previously generated interrupts that have not been handled yet
+//! (due to higher priority interrupts or the interrupt no having been enabled
+//! yet) to be discarded.
+//!
+//! \note It is not possible to unpend the NMI because it takes effect
+//! immediately when being pended.
+//!
+//! \param ui32Interrupt specifies the index in the vector table to unpend.
+//! - See \ref IntPendSet() for list of valid arguments (except NMI).
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void IntPendClear(uint32_t ui32Interrupt);
+
+//*****************************************************************************
+//
+//! \brief Enables the CPU interrupt.
+//!
+//! Allows the CPU to respond to interrupts.
+//!
+//! \return Returns:
+//! - \c true : Interrupts were disabled and are now enabled.
+//! - \c false : Interrupts were already enabled when the function was called.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+IntMasterEnable(void)
+{
+ // Enable CPU interrupts.
+ return(CPUcpsie());
+}
+
+//*****************************************************************************
+//
+//! \brief Disables the CPU interrupts with configurable priority.
+//!
+//! Prevents the CPU from receiving interrupts except NMI and hard fault. This
+//! does not affect the set of interrupts enabled in the interrupt controller;
+//! it just gates the interrupt from the interrupt controller to the CPU.
+//!
+//! \return Returns:
+//! - \c true : Interrupts were already disabled when the function was called.
+//! - \c false : Interrupts were enabled and are now disabled.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+IntMasterDisable(void)
+{
+ // Disable CPU interrupts.
+ return(CPUcpsid());
+}
+
+//*****************************************************************************
+//
+//! \brief Sets the priority masking level.
+//!
+//! This function sets the interrupt priority masking level so that all
+//! interrupts at the specified or lesser priority level are masked. This
+//! can be used to globally disable a set of interrupts with priority below
+//! a predetermined threshold. A value of 0 disables priority
+//! masking.
+//!
+//! Smaller numbers correspond to higher interrupt priorities. So for example
+//! a priority level mask of 4 will allow interrupts of priority level 0-3,
+//! and interrupts with a numerical priority of 4 and greater will be blocked.
+//! The device supports priority levels 0 through 7.
+//!
+//! \param ui32PriorityMask is the priority level that will be masked.
+//! - 0 : Disable priority masking.
+//! - 1 : Allow priority 0 interrupts, mask interrupts with priority 1-7.
+//! - 2 : Allow priority 0-1 interrupts, mask interrupts with priority 2-7.
+//! - 3 : Allow priority 0-2 interrupts, mask interrupts with priority 3-7.
+//! - 4 : Allow priority 0-3 interrupts, mask interrupts with priority 4-7.
+//! - 5 : Allow priority 0-4 interrupts, mask interrupts with priority 5-7.
+//! - 6 : Allow priority 0-5 interrupts, mask interrupts with priority 6-7.
+//! - 7 : Allow priority 0-6 interrupts, mask interrupts with priority 7.
+//!
+//! \return None.
+//
+//*****************************************************************************
+__STATIC_INLINE void
+IntPriorityMaskSet(uint32_t ui32PriorityMask)
+{
+ CPUbasepriSet(ui32PriorityMask);
+}
+
+//*****************************************************************************
+//
+//! \brief Gets the priority masking level.
+//!
+//! This function gets the current setting of the interrupt priority masking
+//! level. The value returned is the priority level such that all interrupts
+//! of that and lesser priority are masked. A value of 0 means that priority
+//! masking is disabled.
+//!
+//! Smaller numbers correspond to higher interrupt priorities. So for example
+//! a priority level mask of 4 will allow interrupts of priority level 0-3,
+//! and interrupts with a numerical priority of 4 and greater will be blocked.
+//!
+//! \return Returns the value of the interrupt priority level mask.
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+IntPriorityMaskGet(void)
+{
+ return(CPUbasepriGet());
+}
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// Redirect to implementation in ROM when available.
+//
+//*****************************************************************************
+#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
+ #include "../driverlib/rom.h"
+ #ifdef ROM_IntRegister
+ #undef IntRegister
+ #define IntRegister ROM_IntRegister
+ #endif
+ #ifdef ROM_IntUnregister
+ #undef IntUnregister
+ #define IntUnregister ROM_IntUnregister
+ #endif
+ #ifdef ROM_IntPriorityGroupingSet
+ #undef IntPriorityGroupingSet
+ #define IntPriorityGroupingSet ROM_IntPriorityGroupingSet
+ #endif
+ #ifdef ROM_IntPriorityGroupingGet
+ #undef IntPriorityGroupingGet
+ #define IntPriorityGroupingGet ROM_IntPriorityGroupingGet
+ #endif
+ #ifdef ROM_IntPrioritySet
+ #undef IntPrioritySet
+ #define IntPrioritySet ROM_IntPrioritySet
+ #endif
+ #ifdef ROM_IntPriorityGet
+ #undef IntPriorityGet
+ #define IntPriorityGet ROM_IntPriorityGet
+ #endif
+ #ifdef ROM_IntEnable
+ #undef IntEnable
+ #define IntEnable ROM_IntEnable
+ #endif
+ #ifdef ROM_IntDisable
+ #undef IntDisable
+ #define IntDisable ROM_IntDisable
+ #endif
+ #ifdef ROM_IntPendSet
+ #undef IntPendSet
+ #define IntPendSet ROM_IntPendSet
+ #endif
+ #ifdef ROM_IntPendGet
+ #undef IntPendGet
+ #define IntPendGet ROM_IntPendGet
+ #endif
+ #ifdef ROM_IntPendClear
+ #undef IntPendClear
+ #define IntPendClear ROM_IntPendClear
+ #endif
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __INTERRUPT_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/interrupt_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/interrupt_doc.h
new file mode 100644
index 0000000..a8a0ad4
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/interrupt_doc.h
@@ -0,0 +1,162 @@
+/******************************************************************************
+* Filename: interrupt_doc.h
+* Revised: 2017-11-14 15:26:03 +0100 (Tue, 14 Nov 2017)
+* Revision: 50272
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+//! \addtogroup interrupt_api
+//! @{
+//! \section sec_interrupt Introduction
+//!
+//! The interrupt controller API provides a set of functions for dealing with the
+//! Nested Vectored Interrupt Controller (NVIC). Functions are provided to enable
+//! and disable interrupts, register interrupt handlers, and set the priority of
+//! interrupts.
+//!
+//! The event sources that trigger the interrupt lines in the NVIC are controlled by
+//! the MCU event fabric. All event sources are statically connected to the NVIC interrupt lines
+//! except one which is programmable. For more information about the MCU event fabric, see the
+//! [MCU event fabric API](\ref event_api).
+//!
+//! \section sec_interrupt_api API
+//!
+//! Interrupts and system exceptions must be individually enabled and disabled through:
+//! - \ref IntEnable()
+//! - \ref IntDisable()
+//!
+//! The global CPU interrupt can be enabled and disabled with the following functions:
+//! - \ref IntMasterEnable()
+//! - \ref IntMasterDisable()
+//!
+//! This does not affect the individual interrupt enable states. Masking of the CPU
+//! interrupt can be used as a simple critical section (only an NMI can interrupt the
+//! CPU while the CPU interrupt is disabled), although masking the CPU
+//! interrupt can increase the interrupt response time.
+//!
+//! It is possible to access the NVIC to see if any interrupts are pending and manually
+//! clear pending interrupts which have not yet been serviced or set a specific interrupt as
+//! pending to be handled based on its priority. Pending interrupts are cleared automatically
+//! when the interrupt is accepted and executed. However, the event source which caused the
+//! interrupt might need to be cleared manually to avoid re-triggering the corresponding interrupt.
+//! The functions to read, clear, and set pending interrupts are:
+//! - \ref IntPendGet()
+//! - \ref IntPendClear()
+//! - \ref IntPendSet()
+//!
+//! The interrupt prioritization in the NVIC allows handling of higher priority interrupts
+//! before lower priority interrupts, as well as allowing preemption of lower priority interrupt
+//! handlers by higher priority interrupts.
+//! The device supports eight priority levels from 0 to 7 with 0 being the highest priority.
+//! The priority of each interrupt source can be set and examined using:
+//! - \ref IntPrioritySet()
+//! - \ref IntPriorityGet()
+//!
+//! Interrupts can be masked based on their priority such that interrupts with the same or lower
+//! priority than the mask are effectively disabled. This can be configured with:
+//! - \ref IntPriorityMaskSet()
+//! - \ref IntPriorityMaskGet()
+//!
+//! Subprioritization is also possible. Instead of having three bits of preemptable
+//! prioritization (eight levels), the NVIC can be configured for 3 - M bits of
+//! preemptable prioritization and M bits of subpriority. In this scheme, two
+//! interrupts with the same preemptable prioritization but different subpriorities
+//! do not cause a preemption. Instead, tail chaining is used to process
+//! the two interrupts back-to-back.
+//! If two interrupts with the same priority (and subpriority if so configured) are
+//! asserted at the same time, the one with the lower interrupt number is
+//! processed first.
+//! Subprioritization is handled by:
+//! - \ref IntPriorityGroupingSet()
+//! - \ref IntPriorityGroupingGet()
+//!
+//! \section sec_interrupt_table Interrupt Vector Table
+//!
+//! The interrupt vector table can be configured in one of two ways:
+//! - Statically (at compile time): Vector table is placed in Flash and each entry has a fixed
+//! pointer to an interrupt handler (ISR).
+//! - Dynamically (at runtime): Vector table is placed in SRAM and each entry can be changed
+//! (registered or unregistered) at runtime. This allows a single interrupt to trigger different
+//! interrupt handlers (ISRs) depending on which interrupt handler is registered at the time the
+//! System CPU responds to the interrupt.
+//!
+//! When configured, the interrupts must be explicitly enabled in the NVIC through \ref IntEnable()
+//! before the CPU can respond to the interrupt (in addition to any interrupt enabling required
+//! within the peripheral).
+//!
+//! \subsection sec_interrupt_table_static Static Vector Table
+//!
+//! Static registration of interrupt handlers is accomplished by editing the interrupt handler
+//! table in the startup code of the application. Texas Instruments provides startup files for
+//! each supported compiler ( \ti_code{startup_<compiler>.c} ) and these startup files include
+//! a default static interrupt vector table.
+//! All entries, except ResetISR, are declared as \c extern with weak assignment to a default
+//! interrupt handler. This allows the user to declare and define a function (in the user's code)
+//! with the same name as an entry in the vector table. At compile time, the linker then replaces
+//! the pointer to the default interrupt handler in the vector table with the pointer to the
+//! interrupt handler defined by the user.
+//!
+//! Statically configuring the interrupt table provides the fastest interrupt response time
+//! because the stacking operation (a write to SRAM on the data bus) is performed in parallel
+//! with the interrupt handler table fetch (a read from Flash on the instruction bus), as well
+//! as the prefetch of the interrupt handler (assuming it is also in Flash).
+//!
+//! \subsection sec_interrupt_table_dynamic Dynamic Vector Table
+//!
+//! Alternatively, interrupts can be registered in the vector table at runtime, thus dynamically.
+//! The dynamic vector table is placed in SRAM and the code can then modify the pointers to
+//! interrupt handlers throughout the application.
+//!
+//! DriverLib uses these two functions to modify the dynamic vector table:
+//! - \ref IntRegister() : Write a pointer to an interrupt handler into the vector table.
+//! - \ref IntUnregister() : Write pointer to default interrupt handler into the vector table.
+//!
+//! \note First call to \ref IntRegister() initializes the vector table in SRAM by copying the
+//! static vector table from Flash and forcing the NVIC to use the dynamic vector table from
+//! this point forward. If using the dynamic vector table it is highly recommended to
+//! initialize it during the setup phase of the application. The NVIC uses the static vector
+//! table in Flash until the application initializes the dynamic vector table in SRAM.
+//!
+//! Runtime configuration of interrupts adds a small latency to the interrupt response time
+//! because the stacking operation (a write to SRAM on the data bus) and the interrupt handler
+//! fetch from the vector table (a read from SRAM on the instruction bus) must be performed
+//! sequentially.
+//!
+//! The dynamic vector table, \ref g_pfnRAMVectors, is placed in SRAM in the section called
+//! \c vtable_ram which is a section defined in the linker file. By default the linker file
+//! places this section at the start of the SRAM but this is configurable by the user.
+//!
+//! \warning Runtime configuration of interrupt handlers requires that the interrupt
+//! handler table is placed on a 256-byte boundary in SRAM (typically, this is
+//! at the beginning of SRAM). Failure to do so results in an incorrect vector
+//! address being fetched in response to an interrupt.
+//!
+//! @}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ioc.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ioc.c
new file mode 100644
index 0000000..d92f811
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ioc.c
@@ -0,0 +1,683 @@
+/******************************************************************************
+* Filename: ioc.c
+* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017)
+* Revision: 49096
+*
+* Description: Driver for the IOC.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "ioc.h"
+
+//*****************************************************************************
+//
+// Handle support for DriverLib in ROM:
+// This section will undo prototype renaming made in the header file
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #undef IOCPortConfigureSet
+ #define IOCPortConfigureSet NOROM_IOCPortConfigureSet
+ #undef IOCPortConfigureGet
+ #define IOCPortConfigureGet NOROM_IOCPortConfigureGet
+ #undef IOCIOShutdownSet
+ #define IOCIOShutdownSet NOROM_IOCIOShutdownSet
+ #undef IOCIOModeSet
+ #define IOCIOModeSet NOROM_IOCIOModeSet
+ #undef IOCIOIntSet
+ #define IOCIOIntSet NOROM_IOCIOIntSet
+ #undef IOCIOEvtSet
+ #define IOCIOEvtSet NOROM_IOCIOEvtSet
+ #undef IOCIOPortPullSet
+ #define IOCIOPortPullSet NOROM_IOCIOPortPullSet
+ #undef IOCIOHystSet
+ #define IOCIOHystSet NOROM_IOCIOHystSet
+ #undef IOCIOInputSet
+ #define IOCIOInputSet NOROM_IOCIOInputSet
+ #undef IOCIOSlewCtrlSet
+ #define IOCIOSlewCtrlSet NOROM_IOCIOSlewCtrlSet
+ #undef IOCIODrvStrengthSet
+ #define IOCIODrvStrengthSet NOROM_IOCIODrvStrengthSet
+ #undef IOCIOPortIdSet
+ #define IOCIOPortIdSet NOROM_IOCIOPortIdSet
+ #undef IOCIntEnable
+ #define IOCIntEnable NOROM_IOCIntEnable
+ #undef IOCIntDisable
+ #define IOCIntDisable NOROM_IOCIntDisable
+ #undef IOCPinTypeGpioInput
+ #define IOCPinTypeGpioInput NOROM_IOCPinTypeGpioInput
+ #undef IOCPinTypeGpioOutput
+ #define IOCPinTypeGpioOutput NOROM_IOCPinTypeGpioOutput
+ #undef IOCPinTypeUart
+ #define IOCPinTypeUart NOROM_IOCPinTypeUart
+ #undef IOCPinTypeSsiMaster
+ #define IOCPinTypeSsiMaster NOROM_IOCPinTypeSsiMaster
+ #undef IOCPinTypeSsiSlave
+ #define IOCPinTypeSsiSlave NOROM_IOCPinTypeSsiSlave
+ #undef IOCPinTypeI2c
+ #define IOCPinTypeI2c NOROM_IOCPinTypeI2c
+ #undef IOCPinTypeAux
+ #define IOCPinTypeAux NOROM_IOCPinTypeAux
+#endif
+
+//*****************************************************************************
+//
+// Set the configuration of an IO port
+//
+//*****************************************************************************
+void
+IOCPortConfigureSet(uint32_t ui32IOId, uint32_t ui32PortId,
+ uint32_t ui32IOConfig)
+{
+ uint32_t ui32Reg;
+
+ // Check the arguments.
+ ASSERT(ui32IOId <= IOID_31);
+ ASSERT(ui32PortId <= IOC_PORT_RFC_GPI1);
+
+ // Get the register address.
+ ui32Reg = IOC_BASE + ( ui32IOId << 2 );
+
+ // Configure the port.
+ HWREG(ui32Reg) = ui32IOConfig | ui32PortId;
+}
+
+//*****************************************************************************
+//
+// Get the configuration of an IO port
+//
+//*****************************************************************************
+uint32_t
+IOCPortConfigureGet(uint32_t ui32IOId)
+{
+ uint32_t ui32Reg;
+
+ // Check the arguments.
+ ASSERT(ui32IOId <= IOID_31);
+
+ // Get the register address.
+ ui32Reg = IOC_BASE + ( ui32IOId << 2 );
+
+ // Return the IO configuration.
+ return HWREG(ui32Reg);
+}
+
+//*****************************************************************************
+//
+// Set wake-up on an IO port
+//
+//*****************************************************************************
+void
+IOCIOShutdownSet(uint32_t ui32IOId, uint32_t ui32IOShutdown)
+{
+ uint32_t ui32Reg;
+ uint32_t ui32Config;
+
+ // Check the arguments.
+ ASSERT(ui32IOId <= IOID_31);
+ ASSERT((ui32IOShutdown == IOC_NO_WAKE_UP) ||
+ (ui32IOShutdown == IOC_WAKE_ON_LOW) ||
+ (ui32IOShutdown == IOC_WAKE_ON_HIGH));
+
+ // Get the register address.
+ ui32Reg = IOC_BASE + ( ui32IOId << 2 );
+
+ // Configure the IO.
+ ui32Config = HWREG(ui32Reg);
+ ui32Config &= ~IOC_IOCFG0_WU_CFG_M;
+ HWREG(ui32Reg) = ui32Config | ui32IOShutdown;
+}
+
+
+//*****************************************************************************
+//
+// Set the IO Mode of an IO Port
+//
+//*****************************************************************************
+void
+IOCIOModeSet(uint32_t ui32IOId, uint32_t ui32IOMode)
+{
+ uint32_t ui32Reg;
+ uint32_t ui32Config;
+
+ // Check the arguments.
+ ASSERT(ui32IOId <= IOID_31);
+ ASSERT((ui32IOMode == IOC_IOMODE_NORMAL) ||
+ (ui32IOMode == IOC_IOMODE_INV) ||
+ (ui32IOMode == IOC_IOMODE_OPEN_DRAIN_NORMAL) ||
+ (ui32IOMode == IOC_IOMODE_OPEN_DRAIN_INV) ||
+ (ui32IOMode == IOC_IOMODE_OPEN_SRC_NORMAL) ||
+ (ui32IOMode == IOC_IOMODE_OPEN_SRC_INV));
+
+ // Get the register address.
+ ui32Reg = IOC_BASE + ( ui32IOId << 2 );
+
+ // Configure the IO.
+ ui32Config = HWREG(ui32Reg);
+ ui32Config &= ~IOC_IOCFG0_IOMODE_M;
+ HWREG(ui32Reg) = ui32Config | ui32IOMode;
+}
+
+//*****************************************************************************
+//
+// Setup interrupt detection on an IO Port
+//
+//*****************************************************************************
+void
+IOCIOIntSet(uint32_t ui32IOId, uint32_t ui32Int, uint32_t ui32EdgeDet)
+{
+ uint32_t ui32IOReg;
+ uint32_t ui32Config;
+
+ // Check the arguments.
+ ASSERT(ui32IOId <= IOID_31);
+ ASSERT((ui32Int == IOC_INT_ENABLE) ||
+ (ui32Int == IOC_INT_DISABLE));
+ ASSERT((ui32EdgeDet == IOC_NO_EDGE) ||
+ (ui32EdgeDet == IOC_FALLING_EDGE) ||
+ (ui32EdgeDet == IOC_RISING_EDGE) ||
+ (ui32EdgeDet == IOC_BOTH_EDGES));
+
+ // Get the register address.
+ ui32IOReg = IOC_BASE + ( ui32IOId << 2 );
+
+ // Configure the IO.
+ ui32Config = HWREG(ui32IOReg);
+ ui32Config &= ~(IOC_IOCFG0_EDGE_IRQ_EN | IOC_IOCFG0_EDGE_DET_M);
+ HWREG(ui32IOReg) = ui32Config | ((ui32Int ? IOC_IOCFG0_EDGE_IRQ_EN : 0) | ui32EdgeDet);
+}
+
+//*****************************************************************************
+//
+// Setup event generation on IO edge detection
+//
+//*****************************************************************************
+void
+IOCIOEvtSet(uint32_t ui32IOId, uint32_t ui32Evt)
+{
+ uint32_t ui32IOReg;
+ uint32_t ui32Config;
+
+ // Check the arguments.
+ ASSERT(ui32IOId <= IOID_31);
+ ASSERT( (ui32Evt & ~(IOC_IOCFG0_IOEV_AON_PROG2_EN_M |
+ IOC_IOCFG0_IOEV_AON_PROG1_EN_M |
+ IOC_IOCFG0_IOEV_AON_PROG0_EN_M |
+ IOC_IOCFG0_IOEV_RTC_EN_M |
+ IOC_IOCFG0_IOEV_MCU_WU_EN_M) ) == 0x00000000);
+
+ // Get the register address.
+ ui32IOReg = IOC_BASE + ( ui32IOId << 2 );
+
+ // Read current configuration.
+ ui32Config = HWREG(ui32IOReg);
+
+ // Disable generation of all events.
+ ui32Config &= ~(IOC_IOCFG0_IOEV_AON_PROG2_EN_M |
+ IOC_IOCFG0_IOEV_AON_PROG1_EN_M |
+ IOC_IOCFG0_IOEV_AON_PROG0_EN_M |
+ IOC_IOCFG0_IOEV_RTC_EN_M |
+ IOC_IOCFG0_IOEV_MCU_WU_EN_M);
+
+ // Enable the required events.
+ HWREG(ui32IOReg) = ui32Config | ui32Evt;
+}
+
+//*****************************************************************************
+//
+// Set the pull on an IO port
+//
+//*****************************************************************************
+void
+IOCIOPortPullSet(uint32_t ui32IOId, uint32_t ui32Pull)
+{
+ uint32_t ui32IOReg;
+ uint32_t ui32Config;
+
+ // Check the argument.
+ ASSERT(ui32IOId <= IOID_31);
+ ASSERT((ui32Pull == IOC_NO_IOPULL) ||
+ (ui32Pull == IOC_IOPULL_UP) ||
+ (ui32Pull == IOC_IOPULL_DOWN));
+
+ // Get the register address.
+ ui32IOReg = IOC_BASE + ( ui32IOId << 2 );
+
+ // Configure the IO.
+ ui32Config = HWREG(ui32IOReg);
+ ui32Config &= ~IOC_IOCFG0_PULL_CTL_M;
+ HWREG(ui32IOReg) = ui32Config | ui32Pull;
+}
+
+//*****************************************************************************
+//
+// Configure hysteresis on and IO port
+//
+//*****************************************************************************
+void
+IOCIOHystSet(uint32_t ui32IOId, uint32_t ui32Hysteresis)
+{
+ uint32_t ui32IOReg;
+ uint32_t ui32Config;
+
+ // Check the arguments.
+ ASSERT(ui32IOId <= IOID_31);
+ ASSERT((ui32Hysteresis == IOC_HYST_ENABLE) ||
+ (ui32Hysteresis == IOC_HYST_DISABLE));
+
+ // Get the register address.
+ ui32IOReg = IOC_BASE + ( ui32IOId << 2 );
+
+ // Configure the IO.
+ ui32Config = HWREG(ui32IOReg);
+ ui32Config &= ~IOC_IOCFG0_HYST_EN;
+ HWREG(ui32IOReg) = ui32Config | ui32Hysteresis;
+}
+
+//*****************************************************************************
+//
+// Enable/disable IO port as input
+//
+//*****************************************************************************
+void
+IOCIOInputSet(uint32_t ui32IOId, uint32_t ui32Input)
+{
+ uint32_t ui32IOReg;
+ uint32_t ui32Config;
+
+ // Check the arguments.
+ ASSERT(ui32IOId <= IOID_31);
+ ASSERT((ui32Input == IOC_INPUT_ENABLE) ||
+ (ui32Input == IOC_INPUT_DISABLE));
+
+ // Get the register address.
+ ui32IOReg = IOC_BASE + ( ui32IOId << 2 );
+
+ // Configure the IO.
+ ui32Config = HWREG(ui32IOReg);
+ ui32Config &= ~IOC_IOCFG0_IE;
+ HWREG(ui32IOReg) = ui32Config | ui32Input;
+}
+
+//*****************************************************************************
+//
+// Enable/disable the slew control on an IO port
+//
+//*****************************************************************************
+void
+IOCIOSlewCtrlSet(uint32_t ui32IOId, uint32_t ui32SlewEnable)
+{
+ uint32_t ui32IOReg;
+ uint32_t ui32Config;
+
+ // Check the arguments.
+ ASSERT(ui32IOId <= IOID_31);
+ ASSERT((ui32SlewEnable == IOC_SLEW_ENABLE) ||
+ (ui32SlewEnable == IOC_SLEW_DISABLE));
+
+ // Get the register address.
+ ui32IOReg = IOC_BASE + ( ui32IOId << 2 );
+
+ // Configure the IO.
+ ui32Config = HWREG(ui32IOReg);
+ ui32Config &= ~IOC_IOCFG0_SLEW_RED;
+ HWREG(ui32IOReg) = ui32Config | ui32SlewEnable;
+}
+
+//*****************************************************************************
+//
+// Configure the drive strength and maximum current of an IO port
+//
+//*****************************************************************************
+void
+IOCIODrvStrengthSet(uint32_t ui32IOId, uint32_t ui32IOCurrent,
+ uint32_t ui32DrvStrength)
+{
+ uint32_t ui32IOReg;
+ uint32_t ui32Config;
+
+ // Check the arguments.
+ ASSERT(ui32IOId <= IOID_31);
+ ASSERT((ui32IOCurrent == IOC_CURRENT_2MA) ||
+ (ui32IOCurrent == IOC_CURRENT_4MA) ||
+ (ui32IOCurrent == IOC_CURRENT_8MA));
+ ASSERT((ui32DrvStrength == IOC_STRENGTH_MIN) ||
+ (ui32DrvStrength == IOC_STRENGTH_MAX) ||
+ (ui32DrvStrength == IOC_STRENGTH_MED) ||
+ (ui32DrvStrength == IOC_STRENGTH_AUTO));
+
+ // Get the register address.
+ ui32IOReg = IOC_BASE + ( ui32IOId << 2 );
+
+ // Configure the IO.
+ ui32Config = HWREG(ui32IOReg);
+ ui32Config &= ~(IOC_IOCFG0_IOCURR_M | IOC_IOCFG0_IOSTR_M);
+ HWREG(ui32IOReg) = ui32Config | (ui32IOCurrent | ui32DrvStrength);
+}
+
+//*****************************************************************************
+//
+// Setup the Port ID for this IO
+//
+//*****************************************************************************
+void
+IOCIOPortIdSet(uint32_t ui32IOId, uint32_t ui32PortId)
+{
+ uint32_t ui32IOReg;
+ uint32_t ui32Config;
+
+ // Check the arguments.
+ ASSERT(ui32IOId <= IOID_31);
+ ASSERT(ui32PortId <= IOC_PORT_RFC_GPI1);
+
+ // Get the register address.
+ ui32IOReg = IOC_BASE + ( ui32IOId << 2 );
+
+ // Configure the IO.
+ ui32Config = HWREG(ui32IOReg);
+ ui32Config &= ~IOC_IOCFG0_PORT_ID_M;
+ HWREG(ui32IOReg) = ui32Config | ui32PortId;
+}
+
+//*****************************************************************************
+//
+// Enables individual IO edge detect interrupt
+//
+//*****************************************************************************
+void
+IOCIntEnable(uint32_t ui32IOId)
+{
+ uint32_t ui32IOReg;
+ uint32_t ui32Config;
+
+ // Check the arguments.
+ ASSERT(ui32IOId <= IOID_31);
+
+ // Get the register address.
+ ui32IOReg = IOC_BASE + ( ui32IOId << 2 );
+
+ // Enable the specified interrupt.
+ ui32Config = HWREG(ui32IOReg);
+ ui32Config |= IOC_IOCFG0_EDGE_IRQ_EN;
+ HWREG(ui32IOReg) = ui32Config;
+}
+
+//*****************************************************************************
+//
+// Disables individual IO edge interrupt sources
+//
+//*****************************************************************************
+void
+IOCIntDisable(uint32_t ui32IOId)
+{
+ uint32_t ui32IOReg;
+ uint32_t ui32Config;
+
+ // Check the arguments.
+ ASSERT(ui32IOId <= IOID_31);
+
+ // Get the register address.
+ ui32IOReg = IOC_BASE + ( ui32IOId << 2 );
+
+ // Disable the specified interrupt.
+ ui32Config = HWREG(ui32IOReg);
+ ui32Config &= ~IOC_IOCFG0_EDGE_IRQ_EN;
+ HWREG(ui32IOReg) = ui32Config;
+}
+
+//*****************************************************************************
+//
+// Setup an IO for standard GPIO input
+//
+//*****************************************************************************
+void
+IOCPinTypeGpioInput(uint32_t ui32IOId)
+{
+ // Check the arguments.
+ ASSERT(ui32IOId <= IOID_31);
+
+ // Setup the IO for standard input.
+ IOCPortConfigureSet(ui32IOId, IOC_PORT_GPIO, IOC_STD_INPUT);
+
+ // Enable input mode in the GPIO module.
+ GPIO_setOutputEnableDio(ui32IOId, GPIO_OUTPUT_DISABLE);
+}
+
+//*****************************************************************************
+//
+// Setup an IO for standard GPIO output
+//
+//*****************************************************************************
+void
+IOCPinTypeGpioOutput(uint32_t ui32IOId)
+{
+ // Check the arguments.
+ ASSERT(ui32IOId <= IOID_31);
+
+ // Setup the IO for standard input.
+ IOCPortConfigureSet(ui32IOId, IOC_PORT_GPIO, IOC_STD_OUTPUT);
+
+ // Enable output mode in the GPIO module.
+ GPIO_setOutputEnableDio(ui32IOId, GPIO_OUTPUT_ENABLE);
+}
+
+//*****************************************************************************
+//
+// Configure a set of IOs for standard UART peripheral control
+//
+//*****************************************************************************
+void
+IOCPinTypeUart(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx,
+ uint32_t ui32Cts, uint32_t ui32Rts)
+{
+ // Check the arguments.
+ ASSERT(ui32Base == UART0_BASE);
+ ASSERT((ui32Rx <= IOID_31) || (ui32Rx == IOID_UNUSED));
+ ASSERT((ui32Tx <= IOID_31) || (ui32Tx == IOID_UNUSED));
+ ASSERT((ui32Cts <= IOID_31) || (ui32Cts == IOID_UNUSED));
+ ASSERT((ui32Rts <= IOID_31) || (ui32Rts == IOID_UNUSED));
+
+ // Setup the IOs in the desired configuration.
+ if(ui32Rx != IOID_UNUSED)
+ {
+ IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_UART0_RX, IOC_STD_INPUT);
+ }
+ if(ui32Tx != IOID_UNUSED)
+ {
+ IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_UART0_TX, IOC_STD_OUTPUT);
+ }
+ if(ui32Cts != IOID_UNUSED)
+ {
+ IOCPortConfigureSet(ui32Cts, IOC_PORT_MCU_UART0_CTS, IOC_STD_INPUT);
+ }
+ if(ui32Rts != IOID_UNUSED)
+ {
+ IOCPortConfigureSet(ui32Rts, IOC_PORT_MCU_UART0_RTS, IOC_STD_OUTPUT);
+ }
+}
+
+//*****************************************************************************
+//
+// Configure a set of IOs for standard SSI peripheral master control
+//
+//*****************************************************************************
+void
+IOCPinTypeSsiMaster(uint32_t ui32Base, uint32_t ui32Rx,
+ uint32_t ui32Tx, uint32_t ui32Fss,
+ uint32_t ui32Clk)
+{
+ // Check the arguments.
+ ASSERT((ui32Base == SSI0_BASE) || (ui32Base == SSI1_BASE));
+ ASSERT((ui32Rx <= IOID_31) || (ui32Rx == IOID_UNUSED));
+ ASSERT((ui32Tx <= IOID_31) || (ui32Tx == IOID_UNUSED));
+ ASSERT((ui32Fss <= IOID_31) || (ui32Fss == IOID_UNUSED));
+ ASSERT((ui32Clk <= IOID_31) || (ui32Clk == IOID_UNUSED));
+
+ // Setup the IOs in the desired configuration.
+ if(ui32Base == SSI0_BASE)
+ {
+ if(ui32Rx != IOID_UNUSED)
+ {
+ IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI0_RX, IOC_STD_INPUT);
+ }
+ if(ui32Tx != IOID_UNUSED)
+ {
+ IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI0_TX, IOC_STD_OUTPUT);
+ }
+ if(ui32Fss != IOID_UNUSED)
+ {
+ IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI0_FSS, IOC_STD_OUTPUT);
+ }
+ if(ui32Clk != IOID_UNUSED)
+ {
+ IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI0_CLK, IOC_STD_OUTPUT);
+ }
+ }
+ else
+ {
+ if(ui32Rx != IOID_UNUSED)
+ {
+ IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI1_RX, IOC_STD_INPUT);
+ }
+ if(ui32Tx != IOID_UNUSED)
+ {
+ IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI1_TX, IOC_STD_OUTPUT);
+ }
+ if(ui32Fss != IOID_UNUSED)
+ {
+ IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI1_FSS, IOC_STD_OUTPUT);
+ }
+ if(ui32Clk != IOID_UNUSED)
+ {
+ IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI1_CLK, IOC_STD_OUTPUT);
+ }
+ }
+}
+
+//*****************************************************************************
+//
+// Configure a set of IOs for standard SSI peripheral slave control
+//
+//*****************************************************************************
+void
+IOCPinTypeSsiSlave(uint32_t ui32Base, uint32_t ui32Rx,
+ uint32_t ui32Tx, uint32_t ui32Fss,
+ uint32_t ui32Clk)
+{
+ // Check the arguments.
+ ASSERT((ui32Base == SSI0_BASE) || (ui32Base == SSI1_BASE));
+ ASSERT((ui32Rx <= IOID_31) || (ui32Rx == IOID_UNUSED));
+ ASSERT((ui32Tx <= IOID_31) || (ui32Tx == IOID_UNUSED));
+ ASSERT((ui32Fss <= IOID_31) || (ui32Fss == IOID_UNUSED));
+ ASSERT((ui32Clk <= IOID_31) || (ui32Clk == IOID_UNUSED));
+
+ // Setup the IOs in the desired configuration.
+ if(ui32Base == SSI0_BASE)
+ {
+ if(ui32Rx != IOID_UNUSED)
+ {
+ IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI0_RX, IOC_STD_INPUT);
+ }
+ if(ui32Tx != IOID_UNUSED)
+ {
+ IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI0_TX, IOC_STD_OUTPUT);
+ }
+ if(ui32Fss != IOID_UNUSED)
+ {
+ IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI0_FSS, IOC_STD_INPUT);
+ }
+ if(ui32Clk != IOID_UNUSED)
+ {
+ IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI0_CLK, IOC_STD_INPUT);
+ }
+ }
+ else
+ {
+ if(ui32Rx != IOID_UNUSED)
+ {
+ IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI1_RX, IOC_STD_INPUT);
+ }
+ if(ui32Tx != IOID_UNUSED)
+ {
+ IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI1_TX, IOC_STD_OUTPUT);
+ }
+ if(ui32Fss != IOID_UNUSED)
+ {
+ IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI1_FSS, IOC_STD_INPUT);
+ }
+ if(ui32Clk != IOID_UNUSED)
+ {
+ IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI1_CLK, IOC_STD_INPUT);
+ }
+ }
+}
+
+//*****************************************************************************
+//
+// Configure a set of IOs for standard I2C peripheral control
+//
+//*****************************************************************************
+void
+IOCPinTypeI2c(uint32_t ui32Base, uint32_t ui32Data, uint32_t ui32Clk)
+{
+ uint32_t ui32IOConfig;
+
+ // Check the arguments.
+ ASSERT((ui32Data <= IOID_31) || (ui32Data == IOID_UNUSED));
+ ASSERT((ui32Clk <= IOID_31) || (ui32Clk == IOID_UNUSED));
+
+ // Define the IO configuration parameters.
+ ui32IOConfig = IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | IOC_IOPULL_UP |
+ IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE |
+ IOC_INT_DISABLE | IOC_IOMODE_OPEN_DRAIN_NORMAL |
+ IOC_NO_WAKE_UP | IOC_INPUT_ENABLE;
+
+ // Setup the IOs in the desired configuration.
+ IOCPortConfigureSet(ui32Data, IOC_PORT_MCU_I2C_MSSDA, ui32IOConfig);
+ IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_I2C_MSSCL, ui32IOConfig);
+}
+
+
+//*****************************************************************************
+//
+// Configure an IO for AUX control
+//
+//*****************************************************************************
+void
+IOCPinTypeAux(uint32_t ui32IOId)
+{
+ // Check the arguments.
+ ASSERT((ui32IOId <= IOID_31) || (ui32IOId == IOID_UNUSED));
+
+ // Setup the IO.
+ IOCPortConfigureSet(ui32IOId, IOC_PORT_AUX_IO, IOC_STD_INPUT);
+}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ioc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ioc.h
new file mode 100644
index 0000000..6e4caaa
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ioc.h
@@ -0,0 +1,1225 @@
+/******************************************************************************
+* Filename: ioc.h
+* Revised: 2017-11-02 14:16:14 +0100 (Thu, 02 Nov 2017)
+* Revision: 50156
+*
+* Description: Defines and prototypes for the IO Controller.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup peripheral_group
+//! @{
+//! \addtogroup ioc_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __IOC_H__
+#define __IOC_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "../inc/hw_types.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_ioc.h"
+#include "../inc/hw_ints.h"
+#include "interrupt.h"
+#include "debug.h"
+#include "gpio.h"
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// This section renames all functions that are not "static inline", so that
+// calling these functions will default to implementation in flash. At the end
+// of this file a second renaming will change the defaults to implementation in
+// ROM for available functions.
+//
+// To force use of the implementation in flash, e.g. for debugging:
+// - Globally: Define DRIVERLIB_NOROM at project level
+// - Per function: Use prefix "NOROM_" when calling the function
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #define IOCPortConfigureSet NOROM_IOCPortConfigureSet
+ #define IOCPortConfigureGet NOROM_IOCPortConfigureGet
+ #define IOCIOShutdownSet NOROM_IOCIOShutdownSet
+ #define IOCIOModeSet NOROM_IOCIOModeSet
+ #define IOCIOIntSet NOROM_IOCIOIntSet
+ #define IOCIOEvtSet NOROM_IOCIOEvtSet
+ #define IOCIOPortPullSet NOROM_IOCIOPortPullSet
+ #define IOCIOHystSet NOROM_IOCIOHystSet
+ #define IOCIOInputSet NOROM_IOCIOInputSet
+ #define IOCIOSlewCtrlSet NOROM_IOCIOSlewCtrlSet
+ #define IOCIODrvStrengthSet NOROM_IOCIODrvStrengthSet
+ #define IOCIOPortIdSet NOROM_IOCIOPortIdSet
+ #define IOCIntEnable NOROM_IOCIntEnable
+ #define IOCIntDisable NOROM_IOCIntDisable
+ #define IOCPinTypeGpioInput NOROM_IOCPinTypeGpioInput
+ #define IOCPinTypeGpioOutput NOROM_IOCPinTypeGpioOutput
+ #define IOCPinTypeUart NOROM_IOCPinTypeUart
+ #define IOCPinTypeSsiMaster NOROM_IOCPinTypeSsiMaster
+ #define IOCPinTypeSsiSlave NOROM_IOCPinTypeSsiSlave
+ #define IOCPinTypeI2c NOROM_IOCPinTypeI2c
+ #define IOCPinTypeAux NOROM_IOCPinTypeAux
+#endif
+
+//*****************************************************************************
+//
+// Number of IOs (max. total of 32)
+//
+//*****************************************************************************
+#define NUM_IO_MAX 32
+
+//*****************************************************************************
+//
+// The following fields are IO Id for the IOC module
+//
+//*****************************************************************************
+#define IOID_0 0x00000000 // IO Id 0
+#define IOID_1 0x00000001 // IO Id 1
+#define IOID_2 0x00000002 // IO Id 2
+#define IOID_3 0x00000003 // IO Id 3
+#define IOID_4 0x00000004 // IO Id 4
+#define IOID_5 0x00000005 // IO Id 5
+#define IOID_6 0x00000006 // IO Id 6
+#define IOID_7 0x00000007 // IO Id 7
+#define IOID_8 0x00000008 // IO Id 8
+#define IOID_9 0x00000009 // IO Id 9
+#define IOID_10 0x0000000A // IO Id 10
+#define IOID_11 0x0000000B // IO Id 11
+#define IOID_12 0x0000000C // IO Id 12
+#define IOID_13 0x0000000D // IO Id 13
+#define IOID_14 0x0000000E // IO Id 14
+#define IOID_15 0x0000000F // IO Id 15
+#define IOID_16 0x00000010 // IO Id 16
+#define IOID_17 0x00000011 // IO Id 17
+#define IOID_18 0x00000012 // IO Id 18
+#define IOID_19 0x00000013 // IO Id 19
+#define IOID_20 0x00000014 // IO Id 20
+#define IOID_21 0x00000015 // IO Id 21
+#define IOID_22 0x00000016 // IO Id 22
+#define IOID_23 0x00000017 // IO Id 23
+#define IOID_24 0x00000018 // IO Id 24
+#define IOID_25 0x00000019 // IO Id 25
+#define IOID_26 0x0000001A // IO Id 26
+#define IOID_27 0x0000001B // IO Id 27
+#define IOID_28 0x0000001C // IO Id 28
+#define IOID_29 0x0000001D // IO Id 29
+#define IOID_30 0x0000001E // IO Id 30
+#define IOID_31 0x0000001F // IO Id 31
+#define IOID_UNUSED 0xFFFFFFFF // Unused IO Id
+
+#define IOC_IOID_MASK 0x000000FF // IOC IO Id bit mask
+
+//*****************************************************************************
+//
+// Number of IO ports
+//
+//*****************************************************************************
+#define NUM_IO_PORTS 56
+
+//*****************************************************************************
+//
+// IOC Peripheral Port Mapping
+//
+//*****************************************************************************
+#define IOC_PORT_GPIO 0x00000000 // Default general purpose IO usage
+#define IOC_PORT_AON_CLK32K 0x00000007 // AON External 32kHz clock
+#define IOC_PORT_AUX_IO 0x00000008 // AUX IO Pin
+#define IOC_PORT_MCU_SSI0_RX 0x00000009 // MCU SSI0 Receive Pin
+#define IOC_PORT_MCU_SSI0_TX 0x0000000A // MCU SSI0 Transmit Pin
+#define IOC_PORT_MCU_SSI0_FSS 0x0000000B // MCU SSI0 FSS Pin
+#define IOC_PORT_MCU_SSI0_CLK 0x0000000C // MCU SSI0 Clock Pin
+#define IOC_PORT_MCU_I2C_MSSDA 0x0000000D // MCU I2C Data Pin
+#define IOC_PORT_MCU_I2C_MSSCL 0x0000000E // MCU I2C Clock Pin
+#define IOC_PORT_MCU_UART0_RX 0x0000000F // MCU UART0 Receive Pin
+#define IOC_PORT_MCU_UART0_TX 0x00000010 // MCU UART0 Transmit Pin
+#define IOC_PORT_MCU_UART0_CTS 0x00000011 // MCU UART0 Clear To Send Pin
+#define IOC_PORT_MCU_UART0_RTS 0x00000012 // MCU UART0 Request To Send Pin
+#define IOC_PORT_MCU_UART1_RX 0x00000013 // MCU UART1 Receive Pin
+#define IOC_PORT_MCU_UART1_TX 0x00000014 // MCU UART1 Transmit Pin
+#define IOC_PORT_MCU_UART1_CTS 0x00000015 // MCU UART1 Clear To Send Pin
+#define IOC_PORT_MCU_UART1_RTS 0x00000016 // MCU UART1 Request To Send Pin
+#define IOC_PORT_MCU_PORT_EVENT0 0x00000017 // MCU PORT EVENT 0
+#define IOC_PORT_MCU_PORT_EVENT1 0x00000018 // MCU PORT EVENT 1
+#define IOC_PORT_MCU_PORT_EVENT2 0x00000019 // MCU PORT EVENT 2
+#define IOC_PORT_MCU_PORT_EVENT3 0x0000001A // MCU PORT EVENT 3
+#define IOC_PORT_MCU_PORT_EVENT4 0x0000001B // MCU PORT EVENT 4
+#define IOC_PORT_MCU_PORT_EVENT5 0x0000001C // MCU PORT EVENT 5
+#define IOC_PORT_MCU_PORT_EVENT6 0x0000001D // MCU PORT EVENT 6
+#define IOC_PORT_MCU_PORT_EVENT7 0x0000001E // MCU PORT EVENT 7
+#define IOC_PORT_MCU_SWV 0x00000020 // Serial Wire Viewer
+#define IOC_PORT_MCU_SSI1_RX 0x00000021 // MCU SSI1 Receive Pin
+#define IOC_PORT_MCU_SSI1_TX 0x00000022 // MCU SSI1 Transmit Pin
+#define IOC_PORT_MCU_SSI1_FSS 0x00000023 // MCU SSI1 FSS Pin
+#define IOC_PORT_MCU_SSI1_CLK 0x00000024 // MCU SSI1 Clock Pin
+#define IOC_PORT_MCU_I2S_AD0 0x00000025 // MCU I2S Data Pin 0
+#define IOC_PORT_MCU_I2S_AD1 0x00000026 // MCU I2S Data Pin 1
+#define IOC_PORT_MCU_I2S_WCLK 0x00000027 // MCU I2S Frame/Word Clock
+#define IOC_PORT_MCU_I2S_BCLK 0x00000028 // MCU I2S Bit Clock
+#define IOC_PORT_MCU_I2S_MCLK 0x00000029 // MCU I2S Master clock 2
+#define IOC_PORT_RFC_TRC 0x0000002E // RF Core Tracer
+#define IOC_PORT_RFC_GPO0 0x0000002F // RC Core Data Out Pin 0
+#define IOC_PORT_RFC_GPO1 0x00000030 // RC Core Data Out Pin 1
+#define IOC_PORT_RFC_GPO2 0x00000031 // RC Core Data Out Pin 2
+#define IOC_PORT_RFC_GPO3 0x00000032 // RC Core Data Out Pin 3
+#define IOC_PORT_RFC_GPI0 0x00000033 // RC Core Data In Pin 0
+#define IOC_PORT_RFC_GPI1 0x00000034 // RC Core Data In Pin 1
+#define IOC_PORT_RFC_SMI_DL_OUT 0x00000035 // RF Core SMI Data Link Out
+#define IOC_PORT_RFC_SMI_DL_IN 0x00000036 // RF Core SMI Data Link in
+#define IOC_PORT_RFC_SMI_CL_OUT 0x00000037 // RF Core SMI Command Link Out
+#define IOC_PORT_RFC_SMI_CL_IN 0x00000038 // RF Core SMI Command Link In
+
+//*****************************************************************************
+//
+// Defines for enabling/disabling an IO
+//
+//*****************************************************************************
+#define IOC_SLEW_ENABLE 0x00001000
+#define IOC_SLEW_DISABLE 0x00000000
+#define IOC_INPUT_ENABLE 0x20000000
+#define IOC_INPUT_DISABLE 0x00000000
+#define IOC_HYST_ENABLE 0x40000000
+#define IOC_HYST_DISABLE 0x00000000
+
+//*****************************************************************************
+//
+// Defines that can be used to set the shutdown mode of an IO
+//
+//*****************************************************************************
+#define IOC_NO_WAKE_UP 0x00000000
+#define IOC_WAKE_ON_LOW 0x10000000
+#define IOC_WAKE_ON_HIGH 0x18000000
+
+//*****************************************************************************
+//
+// Defines that can be used to set the IO Mode of an IO
+//
+//*****************************************************************************
+#define IOC_IOMODE_NORMAL 0x00000000 // Normal Input/Output
+#define IOC_IOMODE_INV 0x01000000 // Inverted Input/Output
+#define IOC_IOMODE_OPEN_DRAIN_NORMAL \
+ 0x04000000 // Open Drain, Normal Input/Output
+#define IOC_IOMODE_OPEN_DRAIN_INV \
+ 0x05000000 // Open Drain, Inverted
+ // Input/Output
+#define IOC_IOMODE_OPEN_SRC_NORMAL \
+ 0x06000000 // Open Source, Normal Input/Output
+#define IOC_IOMODE_OPEN_SRC_INV \
+ 0x07000000 // Open Source, Inverted
+ // Input/Output
+
+//*****************************************************************************
+//
+// Defines that can be used to set the edge detection on an IO
+//
+//*****************************************************************************
+#define IOC_NO_EDGE 0x00000000 // No edge detection
+#define IOC_FALLING_EDGE 0x00010000 // Edge detection on falling edge
+#define IOC_RISING_EDGE 0x00020000 // Edge detection on rising edge
+#define IOC_BOTH_EDGES 0x00030000 // Edge detection on both edges
+#define IOC_INT_ENABLE 0x00040000 // Enable interrupt on edge detect
+#define IOC_INT_DISABLE 0x00000000 // Disable interrupt on edge detect
+#define IOC_INT_M 0x00070000 // Int config mask
+
+//*****************************************************************************
+//
+// Defines that be used to set pull on an IO
+//
+//*****************************************************************************
+#define IOC_NO_IOPULL 0x00006000 // No IO pull
+#define IOC_IOPULL_UP 0x00004000 // Pull up
+#define IOC_IOPULL_DOWN 0x00002000 // Pull down
+#define IOC_IOPULL_M 0x00006000 // Pull config mask
+#define IOC_IOPULL_M 0x00006000
+
+//*****************************************************************************
+//
+// Defines that can be used to select the drive strength of an IO
+//
+//*****************************************************************************
+#define IOC_CURRENT_2MA 0x00000000 // 2mA drive strength
+#define IOC_CURRENT_4MA 0x00000400 // 4mA drive strength
+#define IOC_CURRENT_8MA 0x00000800 // 4 or 8mA drive strength
+
+#define IOC_STRENGTH_AUTO 0x00000000 // Automatic Drive Strength
+ // (2/4/8 mA @ VVDS)
+#define IOC_STRENGTH_MAX 0x00000300 // Maximum Drive Strength
+ // (2/4/8 mA @ 1.8V)
+#define IOC_STRENGTH_MED 0x00000200 // Medium Drive Strength
+ // (2/4/8 mA @ 2.5V)
+#define IOC_STRENGTH_MIN 0x00000100 // Minimum Drive Strength
+ // (2/4/8 mA @ 3.3V)
+
+//*****************************************************************************
+//
+// Defines that can be used to enable event generation on edge detect
+//
+//*****************************************************************************
+#define IOC_EVT_AON_PROG2_DISABLE 0x00000000
+#define IOC_EVT_AON_PROG2_ENABLE 0x00800000
+#define IOC_EVT_AON_PROG1_DISABLE 0x00000000
+#define IOC_EVT_AON_PROG1_ENABLE 0x00400000
+#define IOC_EVT_AON_PROG0_DISABLE 0x00000000
+#define IOC_EVT_AON_PROG0_ENABLE 0x00200000
+#define IOC_EVT_RTC_DISABLE 0x00000000
+#define IOC_EVT_RTC_ENABLE 0x00000080
+#define IOC_EVT_MCU_WU_DISABLE 0x00000000
+#define IOC_EVT_MCU_WU_ENABLE 0x00000040
+
+//*****************************************************************************
+//
+// Defines for standard IO setup
+//
+//*****************************************************************************
+#define IOC_STD_INPUT (IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | \
+ IOC_NO_IOPULL | IOC_SLEW_DISABLE | \
+ IOC_HYST_DISABLE | IOC_NO_EDGE | \
+ IOC_INT_DISABLE | IOC_IOMODE_NORMAL | \
+ IOC_NO_WAKE_UP | IOC_INPUT_ENABLE )
+#define IOC_STD_OUTPUT (IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | \
+ IOC_NO_IOPULL | IOC_SLEW_DISABLE | \
+ IOC_HYST_DISABLE | IOC_NO_EDGE | \
+ IOC_INT_DISABLE | IOC_IOMODE_NORMAL | \
+ IOC_NO_WAKE_UP | IOC_INPUT_DISABLE )
+
+//*****************************************************************************
+//
+// API Functions and prototypes
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \brief Set the configuration of an IO port.
+//!
+//! This function is used to configure the functionality of an IO.
+//!
+//! The \c ui32IOId parameter specifies which IO to configure.
+//!
+//! The \c ui32PortId parameter specifies which functional peripheral to hook
+//! up to this IO.
+//!
+//! The \c ui32IOConfig parameter consists of a bitwise OR'ed value of all
+//! the available configuration modes
+//!
+//! \note All IO Ports are tied to a specific functionality in a sub module
+//! except for the \ref IOC_PORT_AUX_IO. Each of the IOs in the AUX domain are
+//! hardcoded to a specific IO. When enabling one or more pins for the AUX
+//! domain, they should all be configured to using \ref IOC_PORT_AUX_IO.
+//!
+//! \param ui32IOId defines the IO to configure and must be one of the following:
+//! - \ref IOID_0
+//! - ...
+//! - \ref IOID_31
+//! \param ui32PortId selects the functional IO port to connect.
+//! The available IO ports are:
+//! - \ref IOC_PORT_GPIO
+//! - \ref IOC_PORT_AON_CLK32K
+//! - \ref IOC_PORT_AUX_IO
+//! - \ref IOC_PORT_MCU_SSI0_RX
+//! - \ref IOC_PORT_MCU_SSI0_TX
+//! - \ref IOC_PORT_MCU_SSI0_FSS
+//! - \ref IOC_PORT_MCU_SSI0_CLK
+//! - \ref IOC_PORT_MCU_I2C_MSSDA
+//! - \ref IOC_PORT_MCU_I2C_MSSCL
+//! - \ref IOC_PORT_MCU_UART0_RX
+//! - \ref IOC_PORT_MCU_UART0_TX
+//! - \ref IOC_PORT_MCU_UART0_CTS
+//! - \ref IOC_PORT_MCU_UART0_RTS
+//! - \ref IOC_PORT_MCU_UART1_RX
+//! - \ref IOC_PORT_MCU_UART1_TX
+//! - \ref IOC_PORT_MCU_UART1_CTS
+//! - \ref IOC_PORT_MCU_UART1_RTS
+//! - \ref IOC_PORT_MCU_PORT_EVENT0
+//! - \ref IOC_PORT_MCU_PORT_EVENT1
+//! - \ref IOC_PORT_MCU_PORT_EVENT2
+//! - \ref IOC_PORT_MCU_PORT_EVENT3
+//! - \ref IOC_PORT_MCU_PORT_EVENT4
+//! - \ref IOC_PORT_MCU_PORT_EVENT5
+//! - \ref IOC_PORT_MCU_PORT_EVENT6
+//! - \ref IOC_PORT_MCU_PORT_EVENT7
+//! - \ref IOC_PORT_MCU_SWV
+//! - \ref IOC_PORT_MCU_SSI1_RX
+//! - \ref IOC_PORT_MCU_SSI1_TX
+//! - \ref IOC_PORT_MCU_SSI1_FSS
+//! - \ref IOC_PORT_MCU_SSI1_CLK
+//! - \ref IOC_PORT_MCU_I2S_AD0
+//! - \ref IOC_PORT_MCU_I2S_AD1
+//! - \ref IOC_PORT_MCU_I2S_WCLK
+//! - \ref IOC_PORT_MCU_I2S_BCLK
+//! - \ref IOC_PORT_MCU_I2S_MCLK
+//! - \ref IOC_PORT_RFC_TRC
+//! - \ref IOC_PORT_RFC_GPO0
+//! - \ref IOC_PORT_RFC_GPO1
+//! - \ref IOC_PORT_RFC_GPO2
+//! - \ref IOC_PORT_RFC_GPO3
+//! - \ref IOC_PORT_RFC_GPI0
+//! - \ref IOC_PORT_RFC_GPI1
+//! \param ui32IOConfig is the IO configuration consisting of
+//! the bitwise OR of all configuration modes:
+//! - Input/output mode:
+//! - \ref IOC_IOMODE_NORMAL
+//! - \ref IOC_IOMODE_INV
+//! - \ref IOC_IOMODE_OPEN_DRAIN_NORMAL
+//! - \ref IOC_IOMODE_OPEN_DRAIN_INV
+//! - \ref IOC_IOMODE_OPEN_SRC_NORMAL
+//! - \ref IOC_IOMODE_OPEN_SRC_INV
+//! - Wake-up mode (from shutdown):
+//! - \ref IOC_NO_WAKE_UP
+//! - \ref IOC_WAKE_ON_LOW
+//! - \ref IOC_WAKE_ON_HIGH
+//! - Edge detection mode:
+//! - \ref IOC_NO_EDGE
+//! - \ref IOC_FALLING_EDGE
+//! - \ref IOC_RISING_EDGE
+//! - \ref IOC_BOTH_EDGES
+//! - Interrupt mode on edge detection:
+//! - \ref IOC_INT_ENABLE
+//! - \ref IOC_INT_DISABLE
+//! - Pull mode:
+//! - \ref IOC_NO_IOPULL
+//! - \ref IOC_IOPULL_UP
+//! - \ref IOC_IOPULL_DOWN
+//! - Input mode:
+//! - \ref IOC_INPUT_ENABLE
+//! - \ref IOC_INPUT_DISABLE
+//! - Hysteresis mode:
+//! - \ref IOC_HYST_ENABLE
+//! - \ref IOC_HYST_DISABLE
+//! - Slew rate reduction mode:
+//! - \ref IOC_SLEW_ENABLE
+//! - \ref IOC_SLEW_DISABLE
+//! - Current mode (see \ref IOCIODrvStrengthSet() for more details):
+//! - \ref IOC_CURRENT_2MA : Low-Current mode. Min 2 mA when \ti_code{ui32DrvStrength} is set to \ref IOC_STRENGTH_AUTO.
+//! - \ref IOC_CURRENT_4MA : High-Current mode. Min 4 mA when \ti_code{ui32DrvStrength} is set to \ref IOC_STRENGTH_AUTO.
+//! - \ref IOC_CURRENT_8MA : Extended-Current mode. Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when \ti_code{ui32DrvStrength} is set to \ref IOC_STRENGTH_AUTO.
+//! - Drive strength mode:
+//! - \ref IOC_STRENGTH_AUTO : Automatic drive strength based on battery voltage.
+//! - \ref IOC_STRENGTH_MAX : Maximum drive strength, used for low supply levels. Controlled by AON IOC (see \ref AONIOCDriveStrengthSet()).
+//! - \ref IOC_STRENGTH_MED : Medium drive strength, used for medium supply levels. Controlled by AON IOC (see \ref AONIOCDriveStrengthSet()).
+//! - \ref IOC_STRENGTH_MIN : Minimum drive strength, used for high supply levels. Controlled by AON IOC (see \ref AONIOCDriveStrengthSet()).
+//! - Assert AON_PROG2 event on edge detection:
+//! - \ref IOC_EVT_AON_PROG2_DISABLE
+//! - \ref IOC_EVT_AON_PROG2_ENABLE
+//! - Assert AON_PROG1 event on edge detection:
+//! - \ref IOC_EVT_AON_PROG1_DISABLE
+//! - \ref IOC_EVT_AON_PROG1_ENABLE
+//! - Assert AON_PROG0 event on edge detection:
+//! - \ref IOC_EVT_AON_PROG0_DISABLE
+//! - \ref IOC_EVT_AON_PROG0_ENABLE
+//! - Assert RTC event on edge detection:
+//! - \ref IOC_EVT_RTC_DISABLE
+//! - \ref IOC_EVT_RTC_ENABLE
+//! - Assert MCU_WU event on edge detection:
+//! - \ref IOC_EVT_MCU_WU_DISABLE
+//! - \ref IOC_EVT_MCU_WU_ENABLE
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void IOCPortConfigureSet(uint32_t ui32IOId, uint32_t ui32PortId,
+ uint32_t ui32IOConfig);
+
+//*****************************************************************************
+//
+//! \brief Get the configuration of an IO port.
+//!
+//! This function is used for getting the configuration of an IO.
+//!
+//! Each IO port has a dedicated register for setting up the IO. This function
+//! returns the current configuration for the given IO.
+//!
+//! \param ui32IOId selects the IO to return the configuration for.
+//! - \ref IOID_0
+//! - ...
+//! - \ref IOID_31
+//!
+//! \return Returns the IO Port configuration.
+//! See \ref IOCPortConfigureSet() for configuration options.
+//
+//*****************************************************************************
+extern uint32_t IOCPortConfigureGet(uint32_t ui32IOId);
+
+//*****************************************************************************
+//
+//! \brief Set wake-up mode from shutdown on an IO port.
+//!
+//! This function is used to set the wake-up mode from shutdown of an IO.
+//!
+//! IO must be configured as input in order for wakeup to work. See \ref IOCIOInputSet().
+//!
+//! \param ui32IOId defines the IO to configure.
+//! - \ref IOID_0
+//! - ...
+//! - \ref IOID_31
+//! \param ui32IOShutdown enables wake-up from shutdown on LOW/HIGH by this IO port.
+//! - \ref IOC_NO_WAKE_UP
+//! - \ref IOC_WAKE_ON_LOW
+//! - \ref IOC_WAKE_ON_HIGH
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void IOCIOShutdownSet(uint32_t ui32IOId, uint32_t ui32IOShutdown);
+
+
+//*****************************************************************************
+//
+//! \brief Set the IO Mode of an IO Port.
+//!
+//! This function is used to set the input/output mode of an IO.
+//!
+//! \param ui32IOId defines the IO to configure.
+//! - \ref IOID_0
+//! - ...
+//! - \ref IOID_31
+//! \param ui32IOMode sets the port IO Mode.
+//! - \ref IOC_IOMODE_NORMAL
+//! - \ref IOC_IOMODE_INV
+//! - \ref IOC_IOMODE_OPEN_DRAIN_NORMAL
+//! - \ref IOC_IOMODE_OPEN_DRAIN_INV
+//! - \ref IOC_IOMODE_OPEN_SRC_NORMAL
+//! - \ref IOC_IOMODE_OPEN_SRC_INV
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void IOCIOModeSet(uint32_t ui32IOId, uint32_t ui32IOMode);
+
+//*****************************************************************************
+//
+//! \brief Setup edge detection and interrupt generation on an IO Port.
+//!
+//! This function is used to setup the edge detection and interrupt generation on an IO.
+//!
+//! \param ui32IOId defines the IO to configure.
+//! - \ref IOID_0
+//! - ...
+//! - \ref IOID_31
+//! \param ui32Int enables/disables interrupt generation on this IO port.
+//! - \ref IOC_INT_ENABLE
+//! - \ref IOC_INT_DISABLE
+//! \param ui32EdgeDet enables/disables edge detection events on this IO port.
+//! - \ref IOC_NO_EDGE
+//! - \ref IOC_FALLING_EDGE
+//! - \ref IOC_RISING_EDGE
+//! - \ref IOC_BOTH_EDGES
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void IOCIOIntSet(uint32_t ui32IOId, uint32_t ui32Int,
+ uint32_t ui32EdgeDet);
+
+//*****************************************************************************
+//
+//! \brief Setup event generation on IO edge detection.
+//!
+//! This function is used to setup event generation for specific events
+//! when an IO edge detection occurs.
+//!
+//! \param ui32IOId defines the IO to configure.
+//! - \ref IOID_0
+//! - ...
+//! - \ref IOID_31
+//! \param ui32Evt is a bitwise OR of the IO events to generate when an IO edge detection occurs.
+//! All other IO event generations are disabled.
+//! - \ref IOC_EVT_AON_PROG2_ENABLE : AON_PROG2 event.
+//! - \ref IOC_EVT_AON_PROG1_ENABLE : AON_PROG1 event.
+//! - \ref IOC_EVT_AON_PROG0_ENABLE : AON_PROG0 event.
+//! - \ref IOC_EVT_RTC_ENABLE : RTC event.
+//! - \ref IOC_EVT_MCU_WU_ENABLE : MCU_WU event.
+//!
+//
+//*****************************************************************************
+extern void IOCIOEvtSet(uint32_t ui32IOId, uint32_t ui32Evt);
+
+//*****************************************************************************
+//
+//! \brief Set the pull on an IO port.
+//!
+//! This function is used to configure the pull on an IO.
+//!
+//! \param ui32IOId defines the IO to configure.
+//! - \ref IOID_0
+//! - ...
+//! - \ref IOID_31
+//! \param ui32Pull enables/disables pull on this IO port.
+//! - \ref IOC_NO_IOPULL
+//! - \ref IOC_IOPULL_UP
+//! - \ref IOC_IOPULL_DOWN
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void IOCIOPortPullSet(uint32_t ui32IOId, uint32_t ui32Pull);
+
+//*****************************************************************************
+//
+//! \brief Configure hysteresis on and IO port.
+//!
+//! This function is used to enable/disable hysteresis on an IO.
+//!
+//! \param ui32IOId defines the IO to configure.
+//! - \ref IOID_0
+//! - ...
+//! - \ref IOID_31
+//! \param ui32Hysteresis enable/disable input hysteresis on IO.
+//! - \ref IOC_HYST_ENABLE
+//! - \ref IOC_HYST_DISABLE
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void IOCIOHystSet(uint32_t ui32IOId, uint32_t ui32Hysteresis);
+
+//*****************************************************************************
+//
+//! \brief Enable/disable IO port as input.
+//!
+//! This function is used to enable/disable input on an IO.
+//!
+//! \param ui32IOId defines the IO to configure.
+//! - \ref IOID_0
+//! - ...
+//! - \ref IOID_31
+//! \param ui32Input enable/disable input on IO.
+//! - \ref IOC_INPUT_ENABLE
+//! - \ref IOC_INPUT_DISABLE
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void IOCIOInputSet(uint32_t ui32IOId, uint32_t ui32Input);
+
+//*****************************************************************************
+//
+//! \brief Configure slew rate on an IO port.
+//!
+//! This function is used to enable/disable reduced slew rate on an IO.
+//!
+//! \param ui32IOId defines the IO to configure.
+//! - \ref IOID_0
+//! - ...
+//! - \ref IOID_31
+//! \param ui32SlewEnable enables/disables reduced slew rate on an output.
+//! - \ref IOC_SLEW_ENABLE
+//! - \ref IOC_SLEW_DISABLE
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void IOCIOSlewCtrlSet(uint32_t ui32IOId, uint32_t ui32SlewEnable);
+
+//*****************************************************************************
+//
+//! \brief Configure the drive strength source and current mode of an IO port.
+//!
+//! The drive strength of an IO is configured by a combination of multiple settings
+//! in several modules. The drive strength source \ti_code{ui32DrvStrength} is used for controlling
+//! drive strength at different supply levels. When set to AUTO the battery monitor
+//! (BATMON) adjusts the drive strength to compensate for changes in supply voltage
+//! in order to keep IO current constant. Alternatively, drive strength source can
+//! be controlled manually by selecting one of three options each of which is configurable
+//! in the AON IOC by \ref AONIOCDriveStrengthSet().
+//!
+//! Each drive strength source has three current modes: Low-Current (LC), High-Current (HC), and
+//! Extended-Current (EC), and typically drive strength doubles when selecting a higher mode.
+//! I.e. EC = 2 x HC = 4 x LC.
+//!
+//! \note Not all IOs support Extended-Current mode. See datasheet for more information
+//! on the specific device.
+//!
+//! \param ui32IOId defines the IO to configure.
+//! - \ref IOID_0
+//! - ...
+//! - \ref IOID_31
+//! \param ui32IOCurrent selects the IO current mode.
+//! - \ref IOC_CURRENT_2MA : Low-Current mode. Min 2 mA when \ti_code{ui32DrvStrength} is set to \ref IOC_STRENGTH_AUTO.
+//! - \ref IOC_CURRENT_4MA : High-Current mode. Min 4 mA when \ti_code{ui32DrvStrength} is set to \ref IOC_STRENGTH_AUTO.
+//! - \ref IOC_CURRENT_8MA : Extended-Current mode. Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when \ti_code{ui32DrvStrength} is set to \ref IOC_STRENGTH_AUTO.
+//! \param ui32DrvStrength sets the source for drive strength control of the IO port.
+//! - \ref IOC_STRENGTH_AUTO : Automatic drive strength based on battery voltage.
+//! - \ref IOC_STRENGTH_MAX : Maximum drive strength, used for low supply levels. Controlled by AON IOC (see \ref AONIOCDriveStrengthSet()).
+//! - \ref IOC_STRENGTH_MED : Medium drive strength, used for medium supply levels. Controlled by AON IOC (see \ref AONIOCDriveStrengthSet()).
+//! - \ref IOC_STRENGTH_MIN : Minimum drive strength, used for high supply levels. Controlled by AON IOC (see \ref AONIOCDriveStrengthSet()).
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void IOCIODrvStrengthSet(uint32_t ui32IOId, uint32_t ui32IOCurrent,
+ uint32_t ui32DrvStrength);
+
+//*****************************************************************************
+//
+//! \brief Setup the Port ID for this IO.
+//!
+//! The \c ui32PortId specifies which functional peripheral to hook up to this
+//! IO.
+//!
+//! \param ui32IOId defines the IO to configure.
+//! - \ref IOID_0
+//! - ...
+//! - \ref IOID_31
+//! \param ui32PortId selects the port to map to the IO.
+//! - \ref IOC_PORT_GPIO
+//! - \ref IOC_PORT_AON_CLK32K
+//! - \ref IOC_PORT_AUX_IO
+//! - \ref IOC_PORT_MCU_SSI0_RX
+//! - \ref IOC_PORT_MCU_SSI0_TX
+//! - \ref IOC_PORT_MCU_SSI0_FSS
+//! - \ref IOC_PORT_MCU_SSI0_CLK
+//! - \ref IOC_PORT_MCU_I2C_MSSDA
+//! - \ref IOC_PORT_MCU_I2C_MSSCL
+//! - \ref IOC_PORT_MCU_UART0_RX
+//! - \ref IOC_PORT_MCU_UART0_TX
+//! - \ref IOC_PORT_MCU_UART0_CTS
+//! - \ref IOC_PORT_MCU_UART0_RTS
+//! - \ref IOC_PORT_MCU_UART1_RX
+//! - \ref IOC_PORT_MCU_UART1_TX
+//! - \ref IOC_PORT_MCU_UART1_CTS
+//! - \ref IOC_PORT_MCU_UART1_RTS
+//! - \ref IOC_PORT_MCU_PORT_EVENT0
+//! - \ref IOC_PORT_MCU_PORT_EVENT1
+//! - \ref IOC_PORT_MCU_PORT_EVENT2
+//! - \ref IOC_PORT_MCU_PORT_EVENT3
+//! - \ref IOC_PORT_MCU_PORT_EVENT4
+//! - \ref IOC_PORT_MCU_PORT_EVENT5
+//! - \ref IOC_PORT_MCU_PORT_EVENT6
+//! - \ref IOC_PORT_MCU_PORT_EVENT7
+//! - \ref IOC_PORT_MCU_SWV
+//! - \ref IOC_PORT_MCU_SSI1_RX
+//! - \ref IOC_PORT_MCU_SSI1_TX
+//! - \ref IOC_PORT_MCU_SSI1_FSS
+//! - \ref IOC_PORT_MCU_SSI1_CLK
+//! - \ref IOC_PORT_MCU_I2S_AD0
+//! - \ref IOC_PORT_MCU_I2S_AD1
+//! - \ref IOC_PORT_MCU_I2S_WCLK
+//! - \ref IOC_PORT_MCU_I2S_BCLK
+//! - \ref IOC_PORT_MCU_I2S_MCLK
+//! - \ref IOC_PORT_RFC_TRC
+//! - \ref IOC_PORT_RFC_GPO0
+//! - \ref IOC_PORT_RFC_GPO1
+//! - \ref IOC_PORT_RFC_GPO2
+//! - \ref IOC_PORT_RFC_GPO3
+//! - \ref IOC_PORT_RFC_GPI0
+//! - \ref IOC_PORT_RFC_GPI1
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void IOCIOPortIdSet(uint32_t ui32IOId, uint32_t ui32PortId);
+
+//*****************************************************************************
+//
+//! \brief Register an interrupt handler for an IO edge interrupt in the dynamic interrupt table.
+//!
+//! \note Only use this function if you want to use the dynamic vector table (in SRAM)!
+//!
+//! This function registers a function as the interrupt handler for a specific
+//! interrupt and enables the corresponding interrupt in the interrupt controller.
+//!
+//! Specific IO interrupts must be enabled via \ref IOCIntEnable(). It is the interrupt
+//! handler's responsibility to clear the interrupt source.
+//!
+//! \param pfnHandler is a pointer to the function to be called when the
+//! IOC interrupt occurs.
+//!
+//! \return None
+//!
+//! \sa \ref IntRegister() for important information about registering interrupt
+//! handlers.
+//
+//*****************************************************************************
+__STATIC_INLINE void
+IOCIntRegister(void (*pfnHandler)(void))
+{
+ // Register the interrupt handler.
+ IntRegister(INT_AON_GPIO_EDGE, pfnHandler);
+
+ // Enable the IO edge interrupt.
+ IntEnable(INT_AON_GPIO_EDGE);
+}
+
+//*****************************************************************************
+//
+//! \brief Unregisters an interrupt handler for a IO edge interrupt in the dynamic interrupt table.
+//!
+//! This function does the actual unregistering of the interrupt handler. It
+//! clears the handler to be called when an IO edge interrupt occurs.
+//!
+//! \return None
+//!
+//! \sa \ref IntRegister() for important information about registering interrupt
+//! handlers.
+//
+//*****************************************************************************
+__STATIC_INLINE void
+IOCIntUnregister(void)
+{
+ // Disable the interrupts.
+ IntDisable(INT_AON_GPIO_EDGE);
+
+ // Unregister the interrupt handler.
+ IntUnregister(INT_AON_GPIO_EDGE);
+}
+
+//*****************************************************************************
+//
+//! \brief Enables individual IO edge detect interrupt.
+//!
+//! This function enables the indicated IO edge interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! \param ui32IOId is the IO to enable edge detect interrupt for.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void IOCIntEnable(uint32_t ui32IOId);
+
+//*****************************************************************************
+//
+//! \brief Disables individual IO edge interrupt sources.
+//!
+//! This function disables the indicated IO edge interrupt source. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! \param ui32IOId is the IO edge interrupt source to be disabled.
+//! - \ref IOID_0
+//! - ...
+//! - \ref IOID_31
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void IOCIntDisable(uint32_t ui32IOId);
+
+//*****************************************************************************
+//
+//! \brief Clears the IO edge interrupt source.
+//!
+//! The specified IO edge interrupt source is cleared, so that it no longer
+//! asserts. This function must be called in the interrupt handler to keep the
+//! interrupt from being recognized again immediately upon exit.
+//!
+//! \note Due to write buffers and synchronizers in the system it may take several
+//! clock cycles from a register write clearing an event in a module and until the
+//! event is actually cleared in the NVIC of the system CPU. It is recommended to
+//! clear the event source early in the interrupt service routine (ISR) to allow
+//! the event clear to propagate to the NVIC before returning from the ISR.
+//! At the same time, an early event clear allows new events of the same type to be
+//! pended instead of ignored if the event is cleared later in the ISR.
+//! It is the responsibility of the programmer to make sure that enough time has passed
+//! before returning from the ISR to avoid false re-triggering of the cleared event.
+//! A simple, although not necessarily optimal, way of clearing an event before
+//! returning from the ISR is:
+//! -# Write to clear event (interrupt source). (buffered write)
+//! -# Dummy read from the event source module. (making sure the write has propagated)
+//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers)
+//!
+//! \param ui32IOId is the IO causing the interrupt.
+//! - \ref IOID_0
+//! - ...
+//! - \ref IOID_31
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+IOCIntClear(uint32_t ui32IOId)
+{
+ // Check the arguments.
+ ASSERT(ui32IOId <= IOID_31);
+
+ // Clear the requested interrupt source by clearing the event.
+ GPIO_clearEventDio(ui32IOId);
+}
+
+//*****************************************************************************
+//
+//! \brief Returns the status of the IO interrupts.
+//!
+//! \param ui32IOId is the IO to get the status for.
+//! - \ref IOID_0
+//! - ...
+//! - \ref IOID_31
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+IOCIntStatus(uint32_t ui32IOId)
+{
+ // Check the arguments.
+ ASSERT(ui32IOId <= IOID_31);
+
+ // Get the event status.
+ return (GPIO_getEventDio(ui32IOId));
+}
+
+
+//*****************************************************************************
+//
+//! \brief Setup an IO for standard GPIO input.
+//!
+//! Setup an IO for standard GPIO input with the following configuration:
+//! - Port ID:
+//! - \ref IOC_PORT_GPIO
+//! - Configuration:
+//! - \ref IOC_CURRENT_2MA
+//! - \ref IOC_STRENGTH_AUTO
+//! - \ref IOC_NO_IOPULL
+//! - \ref IOC_SLEW_DISABLE
+//! - \ref IOC_HYST_DISABLE
+//! - \ref IOC_NO_EDGE
+//! - \ref IOC_INT_DISABLE
+//! - \ref IOC_IOMODE_NORMAL
+//! - \ref IOC_NO_WAKE_UP
+//! - \ref IOC_INPUT_ENABLE
+//!
+//! \param ui32IOId is the IO to setup for GPIO input
+//! - \ref IOID_0
+//! - ...
+//! - \ref IOID_31
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void IOCPinTypeGpioInput(uint32_t ui32IOId);
+
+//*****************************************************************************
+//
+//! \brief Setup an IO for standard GPIO output.
+//!
+//! Setup an IO for standard GPIO output with the following configuration:
+//! - Port ID:
+//! - \ref IOC_PORT_GPIO
+//! - Configuration:
+//! - \ref IOC_CURRENT_2MA
+//! - \ref IOC_STRENGTH_AUTO
+//! - \ref IOC_NO_IOPULL
+//! - \ref IOC_SLEW_DISABLE
+//! - \ref IOC_HYST_DISABLE
+//! - \ref IOC_NO_EDGE
+//! - \ref IOC_INT_DISABLE
+//! - \ref IOC_IOMODE_NORMAL
+//! - \ref IOC_NO_WAKE_UP
+//! - \ref IOC_INPUT_DISABLE
+//!
+//! \param ui32IOId is the IO to setup for GPIO output
+//! - \ref IOID_0
+//! - ...
+//! - \ref IOID_31
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void IOCPinTypeGpioOutput(uint32_t ui32IOId);
+
+//*****************************************************************************
+//
+//! \brief Configure a set of IOs for standard UART peripheral control.
+//!
+//! The UART pins must be properly configured for the UART peripheral to
+//! function correctly. This function provides a typical configuration for
+//! those pin(s). Other configurations may work as well depending upon the
+//! board setup (for example, using the on-chip pull-ups).
+//!
+//! \note If a UART pin is not intended to be used, then the parameter in the
+//! function should be \ref IOID_UNUSED.
+//!
+//! \param ui32Base is the base address of the UART module.
+//! \param ui32Rx is the IO Id of the IO to use as UART Receive.
+//! - \ref IOID_0
+//! - ...
+//! - \ref IOID_31
+//! - \ref IOID_UNUSED
+//! \param ui32Tx is the IO Id of the IO to use as UART Transmit.
+//! - \ref IOID_0
+//! - ...
+//! - \ref IOID_31
+//! - \ref IOID_UNUSED
+//! \param ui32Cts is the IO Id of the IO to use for UART Clear to send.
+//! - \ref IOID_0
+//! - ...
+//! - \ref IOID_31
+//! - \ref IOID_UNUSED
+//! \param ui32Rts is the IO Id of the IO to use for UART Request to send.
+//! - \ref IOID_0
+//! - ...
+//! - \ref IOID_31
+//! - \ref IOID_UNUSED
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void IOCPinTypeUart(uint32_t ui32Base, uint32_t ui32Rx,
+ uint32_t ui32Tx, uint32_t ui32Cts,
+ uint32_t ui32Rts);
+
+//*****************************************************************************
+//
+//! \brief Configure a set of IOs for standard SSI peripheral master control.
+//!
+//! \param ui32Base is the base address of the SSI module to connect to the IOs
+//! \param ui32Rx is the IO to connect to the SSI MISO line.
+//! - \ref IOID_0
+//! - ...
+//! - \ref IOID_31
+//! - \ref IOID_UNUSED
+//! \param ui32Tx is the IO to connect to the SSI MOSI line.
+//! - \ref IOID_0
+//! - ...
+//! - \ref IOID_31
+//! - \ref IOID_UNUSED
+//! \param ui32Fss is the IO to connect to the SSI FSS line.
+//! - \ref IOID_0
+//! - ...
+//! - \ref IOID_31
+//! - \ref IOID_UNUSED
+//! \param ui32Clk is the IO to connect to the SSI Clock output line.
+//! - \ref IOID_0
+//! - ...
+//! - \ref IOID_31
+//! - \ref IOID_UNUSED
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void IOCPinTypeSsiMaster(uint32_t ui32Base, uint32_t ui32Rx,
+ uint32_t ui32Tx, uint32_t ui32Fss,
+ uint32_t ui32Clk);
+
+//*****************************************************************************
+//
+//! \brief Configure a set of IOs for standard SSI peripheral slave control.
+//!
+//! \param ui32Base is the base address of the SSI module to connect to the IOs
+//! \param ui32Rx is the IO to connect to the SSI MOSI line.
+//! - \ref IOID_0
+//! - ...
+//! - \ref IOID_31
+//! - \ref IOID_UNUSED
+//! \param ui32Tx is the IO to connect to the SSI MISO line.
+//! - \ref IOID_0
+//! - ...
+//! - \ref IOID_31
+//! - \ref IOID_UNUSED
+//! \param ui32Fss is the IO to connect to the SSI FSS line.
+//! - \ref IOID_0
+//! - ...
+//! - \ref IOID_31
+//! - \ref IOID_UNUSED
+//! \param ui32Clk is the IO to connect to the SSI Clock input line.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void IOCPinTypeSsiSlave(uint32_t ui32Base, uint32_t ui32Rx,
+ uint32_t ui32Tx, uint32_t ui32Fss,
+ uint32_t ui32Clk);
+
+//*****************************************************************************
+//
+//! \brief Configure a set of IOs for standard I2C peripheral control.
+//!
+//! \param ui32Base is the base address of the I2C module to connect to the IOs
+//! \param ui32Data is the I2C data line
+//! - \ref IOID_0
+//! - ...
+//! - \ref IOID_31
+//! - \ref IOID_UNUSED
+//! \param ui32Clk is the I2C input clock
+//! - \ref IOID_0
+//! - ...
+//! - \ref IOID_31
+//! - \ref IOID_UNUSED
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void IOCPinTypeI2c(uint32_t ui32Base, uint32_t ui32Data,
+ uint32_t ui32Clk);
+
+
+//*****************************************************************************
+//
+//! \brief Configure an IO for AUX control.
+//!
+//! Use this function to enable AUX to control a specific IO. Please note, that
+//! when using AUX to control the IO, the input/output control in the IOC is
+//! bypassed and completely controlled by AUX, so enabling or disabling input
+//! in the IOC has no effect.
+//!
+//! \note The IOs available for AUX control can vary from device to device.
+//!
+//! \param ui32IOId is the IO to setup for AUX usage.
+//! - \ref IOID_0
+//! - ...
+//! - \ref IOID_31
+//! - \ref IOID_UNUSED
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void IOCPinTypeAux(uint32_t ui32IOId);
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// Redirect to implementation in ROM when available.
+//
+//*****************************************************************************
+#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
+ #include "../driverlib/rom.h"
+ #ifdef ROM_IOCPortConfigureSet
+ #undef IOCPortConfigureSet
+ #define IOCPortConfigureSet ROM_IOCPortConfigureSet
+ #endif
+ #ifdef ROM_IOCPortConfigureGet
+ #undef IOCPortConfigureGet
+ #define IOCPortConfigureGet ROM_IOCPortConfigureGet
+ #endif
+ #ifdef ROM_IOCIOShutdownSet
+ #undef IOCIOShutdownSet
+ #define IOCIOShutdownSet ROM_IOCIOShutdownSet
+ #endif
+ #ifdef ROM_IOCIOModeSet
+ #undef IOCIOModeSet
+ #define IOCIOModeSet ROM_IOCIOModeSet
+ #endif
+ #ifdef ROM_IOCIOIntSet
+ #undef IOCIOIntSet
+ #define IOCIOIntSet ROM_IOCIOIntSet
+ #endif
+ #ifdef ROM_IOCIOEvtSet
+ #undef IOCIOEvtSet
+ #define IOCIOEvtSet ROM_IOCIOEvtSet
+ #endif
+ #ifdef ROM_IOCIOPortPullSet
+ #undef IOCIOPortPullSet
+ #define IOCIOPortPullSet ROM_IOCIOPortPullSet
+ #endif
+ #ifdef ROM_IOCIOHystSet
+ #undef IOCIOHystSet
+ #define IOCIOHystSet ROM_IOCIOHystSet
+ #endif
+ #ifdef ROM_IOCIOInputSet
+ #undef IOCIOInputSet
+ #define IOCIOInputSet ROM_IOCIOInputSet
+ #endif
+ #ifdef ROM_IOCIOSlewCtrlSet
+ #undef IOCIOSlewCtrlSet
+ #define IOCIOSlewCtrlSet ROM_IOCIOSlewCtrlSet
+ #endif
+ #ifdef ROM_IOCIODrvStrengthSet
+ #undef IOCIODrvStrengthSet
+ #define IOCIODrvStrengthSet ROM_IOCIODrvStrengthSet
+ #endif
+ #ifdef ROM_IOCIOPortIdSet
+ #undef IOCIOPortIdSet
+ #define IOCIOPortIdSet ROM_IOCIOPortIdSet
+ #endif
+ #ifdef ROM_IOCIntEnable
+ #undef IOCIntEnable
+ #define IOCIntEnable ROM_IOCIntEnable
+ #endif
+ #ifdef ROM_IOCIntDisable
+ #undef IOCIntDisable
+ #define IOCIntDisable ROM_IOCIntDisable
+ #endif
+ #ifdef ROM_IOCPinTypeGpioInput
+ #undef IOCPinTypeGpioInput
+ #define IOCPinTypeGpioInput ROM_IOCPinTypeGpioInput
+ #endif
+ #ifdef ROM_IOCPinTypeGpioOutput
+ #undef IOCPinTypeGpioOutput
+ #define IOCPinTypeGpioOutput ROM_IOCPinTypeGpioOutput
+ #endif
+ #ifdef ROM_IOCPinTypeUart
+ #undef IOCPinTypeUart
+ #define IOCPinTypeUart ROM_IOCPinTypeUart
+ #endif
+ #ifdef ROM_IOCPinTypeSsiMaster
+ #undef IOCPinTypeSsiMaster
+ #define IOCPinTypeSsiMaster ROM_IOCPinTypeSsiMaster
+ #endif
+ #ifdef ROM_IOCPinTypeSsiSlave
+ #undef IOCPinTypeSsiSlave
+ #define IOCPinTypeSsiSlave ROM_IOCPinTypeSsiSlave
+ #endif
+ #ifdef ROM_IOCPinTypeI2c
+ #undef IOCPinTypeI2c
+ #define IOCPinTypeI2c ROM_IOCPinTypeI2c
+ #endif
+ #ifdef ROM_IOCPinTypeAux
+ #undef IOCPinTypeAux
+ #define IOCPinTypeAux ROM_IOCPinTypeAux
+ #endif
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __IOC_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ioc_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ioc_doc.h
new file mode 100644
index 0000000..dcd74ca
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ioc_doc.h
@@ -0,0 +1,92 @@
+/******************************************************************************
+* Filename: ioc_doc.h
+* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016)
+* Revision: 45971
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+//! \addtogroup ioc_api
+//! @{
+//! \section sec_ioc Introduction
+//!
+//! The Input/Output Controller (IOC) controls the functionality of the pins (called DIO).
+//! The IOC consists of two APIs:
+//! - MCU IOC API selects which peripheral module is connected to the individual DIO and thus allowed to control it.
+//! It also controls individual drive strength, slew rate, pull-up/pull-down, edge detection, etc.
+//! - AON IOC API controls the general drive strength definitions, IO latches, and if the LF clock is
+//! routed to a DIO for external use.
+//!
+//! For more information on the AON IOC see the [AON IOC API](\ref aonioc_api).
+//!
+//! \note The output driver of a DIO is not configured by the IOC API (except for drive strength); instead, it is controlled by the
+//! peripheral module which is selected to control the DIO.
+//!
+//! A DIO is considered "software controlled" if it is configured for GPIO control which allows the
+//! System CPU to set the value of the DIO via the [GPIO API](\ref gpio_api). Alternatively, a DIO
+//! can be "hardware controlled" if it is controlled by other modules than GPIO.
+//!
+//! \section sec_ioc_api API
+//!
+//! The API functions can be grouped like this:
+//!
+//! Configure all settings at the same time:
+//! - \ref IOCPortConfigureSet()
+//! - \ref IOCPortConfigureGet()
+//!
+//! Configure individual settings:
+//! - \ref IOCIODrvStrengthSet()
+//! - \ref IOCIOHystSet()
+//! - \ref IOCIOInputSet()
+//! - \ref IOCIOIntSet()
+//! - \ref IOCIOModeSet()
+//! - \ref IOCIOPortIdSet()
+//! - \ref IOCIOPortPullSet()
+//! - \ref IOCIOShutdownSet()
+//! - \ref IOCIOSlewCtrlSet()
+//!
+//! Handle edge detection events:
+//! - \ref IOCIntEnable()
+//! - \ref IOCIntDisable()
+//! - \ref IOCIntClear()
+//! - \ref IOCIntStatus()
+//! - \ref IOCIntRegister()
+//! - \ref IOCIntUnregister()
+//!
+//! Configure IOCs for typical use cases (can also be used as example code):
+//! - \ref IOCPinTypeAux()
+//! - \ref IOCPinTypeGpioInput()
+//! - \ref IOCPinTypeGpioOutput()
+//! - \ref IOCPinTypeI2c()
+//! - \ref IOCPinTypeSsiMaster()
+//! - \ref IOCPinTypeSsiSlave()
+//! - \ref IOCPinTypeUart()
+//!
+//! @}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/osc.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/osc.c
new file mode 100644
index 0000000..1212d01
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/osc.c
@@ -0,0 +1,625 @@
+/******************************************************************************
+* Filename: osc.c
+* Revised: 2019-02-14 09:35:31 +0100 (Thu, 14 Feb 2019)
+* Revision: 54539
+*
+* Description: Driver for setting up the system Oscillators
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "../inc/hw_types.h"
+#include "../inc/hw_ccfg.h"
+#include "../inc/hw_fcfg1.h"
+#include "aon_batmon.h"
+#include "aon_rtc.h"
+#include "osc.h"
+#include "setup_rom.h"
+
+//*****************************************************************************
+//
+// Handle support for DriverLib in ROM:
+// This section will undo prototype renaming made in the header file
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #undef OSCClockSourceSet
+ #define OSCClockSourceSet NOROM_OSCClockSourceSet
+ #undef OSCClockSourceGet
+ #define OSCClockSourceGet NOROM_OSCClockSourceGet
+ #undef OSCHF_GetStartupTime
+ #define OSCHF_GetStartupTime NOROM_OSCHF_GetStartupTime
+ #undef OSCHF_TurnOnXosc
+ #define OSCHF_TurnOnXosc NOROM_OSCHF_TurnOnXosc
+ #undef OSCHF_AttemptToSwitchToXosc
+ #define OSCHF_AttemptToSwitchToXosc NOROM_OSCHF_AttemptToSwitchToXosc
+ #undef OSCHF_SwitchToRcOscTurnOffXosc
+ #define OSCHF_SwitchToRcOscTurnOffXosc NOROM_OSCHF_SwitchToRcOscTurnOffXosc
+ #undef OSCHF_DebugGetCrystalAmplitude
+ #define OSCHF_DebugGetCrystalAmplitude NOROM_OSCHF_DebugGetCrystalAmplitude
+ #undef OSCHF_DebugGetExpectedAverageCrystalAmplitude
+ #define OSCHF_DebugGetExpectedAverageCrystalAmplitude NOROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude
+ #undef OSC_HPOSC_Debug_InitFreqOffsetParams
+ #define OSC_HPOSC_Debug_InitFreqOffsetParams NOROM_OSC_HPOSC_Debug_InitFreqOffsetParams
+ #undef OSC_HPOSCInitializeFrequencyOffsetParameters
+ #define OSC_HPOSCInitializeFrequencyOffsetParameters NOROM_OSC_HPOSCInitializeFrequencyOffsetParameters
+ #undef OSC_HPOSCRelativeFrequencyOffsetGet
+ #define OSC_HPOSCRelativeFrequencyOffsetGet NOROM_OSC_HPOSCRelativeFrequencyOffsetGet
+ #undef OSC_AdjustXoscHfCapArray
+ #define OSC_AdjustXoscHfCapArray NOROM_OSC_AdjustXoscHfCapArray
+ #undef OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert
+ #define OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert NOROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert
+ #undef OSC_HPOSCRtcCompensate
+ #define OSC_HPOSCRtcCompensate NOROM_OSC_HPOSCRtcCompensate
+#endif
+
+//*****************************************************************************
+//
+// Global HPOSC curve fitting polynomials
+// Parameters found/calculated when calling function
+// OSC_HPOSCInitializeFrequencyOffsetParameters()
+// (or OSC_HPOSC_Debug_InitFreqOffsetParams() used for debugging only)
+// These global variables must be updated before using HPOSC
+//
+//*****************************************************************************
+
+static int16_t _hpOscPolynomials[ 4 ];
+
+//*****************************************************************************
+//
+// OSCHF switch time calculator defines and globals
+//
+//*****************************************************************************
+
+#define RTC_CV_TO_MS(x) (( 1000 * ( x )) >> 16 )
+#define RTC_CV_TO_US(x) (( 1000000 * ( x )) >> 16 )
+
+typedef struct {
+ uint32_t previousStartupTimeInUs ;
+ uint32_t timeXoscOff_CV ;
+ uint32_t timeXoscOn_CV ;
+ uint32_t timeXoscStable_CV ;
+ int32_t tempXoscOff ;
+} OscHfGlobals_t;
+
+static OscHfGlobals_t oscHfGlobals;
+
+//*****************************************************************************
+//
+// Configure the oscillator input to the a source clock.
+//
+//*****************************************************************************
+void
+OSCClockSourceSet(uint32_t ui32SrcClk, uint32_t ui32Osc)
+{
+ // Check the arguments.
+ ASSERT((ui32SrcClk & OSC_SRC_CLK_LF) ||
+ (ui32SrcClk & OSC_SRC_CLK_HF));
+ ASSERT((ui32Osc == OSC_RCOSC_HF) ||
+ (ui32Osc == OSC_RCOSC_LF) ||
+ (ui32Osc == OSC_XOSC_HF) ||
+ (ui32Osc == OSC_XOSC_LF));
+
+ // Request the high frequency source clock (using 24 MHz XTAL)
+ if(ui32SrcClk & OSC_SRC_CLK_HF)
+ {
+ // Enable the HF XTAL as HF clock source
+ DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0,
+ DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_M,
+ DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_S,
+ ui32Osc);
+ }
+
+ // Configure the low frequency source clock.
+ if(ui32SrcClk & OSC_SRC_CLK_LF)
+ {
+ // Change the clock source.
+ DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0,
+ DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_M,
+ DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_S,
+ ui32Osc);
+ }
+}
+
+//*****************************************************************************
+//
+// Get the source clock settings
+//
+//*****************************************************************************
+uint32_t
+OSCClockSourceGet(uint32_t ui32SrcClk)
+{
+ uint32_t ui32ClockSource;
+
+ // Check the arguments.
+ ASSERT((ui32SrcClk & OSC_SRC_CLK_LF) ||
+ (ui32SrcClk & OSC_SRC_CLK_HF));
+
+ // Return the source for the selected clock.
+ if(ui32SrcClk == OSC_SRC_CLK_LF)
+ {
+ ui32ClockSource = DDI16BitfieldRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_STAT0,
+ DDI_0_OSC_STAT0_SCLK_LF_SRC_M,
+ DDI_0_OSC_STAT0_SCLK_LF_SRC_S);
+ }
+ else
+ {
+ ui32ClockSource = DDI16BitfieldRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_STAT0,
+ DDI_0_OSC_STAT0_SCLK_HF_SRC_M,
+ DDI_0_OSC_STAT0_SCLK_HF_SRC_S);
+ }
+ return (ui32ClockSource);
+}
+
+//*****************************************************************************
+//
+// Returns maximum startup time (in microseconds) of XOSC_HF
+//
+//*****************************************************************************
+uint32_t
+OSCHF_GetStartupTime( uint32_t timeUntilWakeupInMs )
+{
+ uint32_t deltaTimeSinceXoscOnInMs ;
+ int32_t deltaTempSinceXoscOn ;
+ uint32_t newStartupTimeInUs ;
+
+ deltaTimeSinceXoscOnInMs = RTC_CV_TO_MS( AONRTCCurrentCompareValueGet() - oscHfGlobals.timeXoscOn_CV );
+ deltaTempSinceXoscOn = AONBatMonTemperatureGetDegC() - oscHfGlobals.tempXoscOff;
+
+ if ( deltaTempSinceXoscOn < 0 ) {
+ deltaTempSinceXoscOn = -deltaTempSinceXoscOn;
+ }
+
+ if ( (( timeUntilWakeupInMs + deltaTimeSinceXoscOnInMs ) > 3000 ) ||
+ ( deltaTempSinceXoscOn > 5 ) ||
+ ( oscHfGlobals.timeXoscStable_CV < oscHfGlobals.timeXoscOn_CV ) ||
+ ( oscHfGlobals.previousStartupTimeInUs == 0 ) )
+ {
+ newStartupTimeInUs = 2000;
+ if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M ) == 0 ) {
+ newStartupTimeInUs = (( HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ) &
+ CCFG_MODE_CONF_1_XOSC_MAX_START_M ) >>
+ CCFG_MODE_CONF_1_XOSC_MAX_START_S ) * 125;
+ // Note: CCFG startup time is "in units of 100us" adding 25% margin results in *125
+ }
+ } else {
+ newStartupTimeInUs = RTC_CV_TO_US( oscHfGlobals.timeXoscStable_CV - oscHfGlobals.timeXoscOn_CV );
+ newStartupTimeInUs += ( newStartupTimeInUs >> 2 ); // Add 25 percent margin
+ if ( newStartupTimeInUs < oscHfGlobals.previousStartupTimeInUs ) {
+ newStartupTimeInUs = oscHfGlobals.previousStartupTimeInUs;
+ }
+ }
+
+ if ( newStartupTimeInUs < 200 ) {
+ newStartupTimeInUs = 200;
+ }
+ if ( newStartupTimeInUs > 4000 ) {
+ newStartupTimeInUs = 4000;
+ }
+ return ( newStartupTimeInUs );
+}
+
+
+//*****************************************************************************
+//
+// Turns on XOSC_HF (but without switching to XOSC_HF)
+//
+//*****************************************************************************
+void
+OSCHF_TurnOnXosc( void )
+{
+#if ( defined( ROM_OSCClockSourceSet ))
+ ROM_OSCClockSourceSet( OSC_SRC_CLK_HF, OSC_XOSC_HF );
+#else
+ OSCClockSourceSet( OSC_SRC_CLK_HF, OSC_XOSC_HF );
+#endif
+ oscHfGlobals.timeXoscOn_CV = AONRTCCurrentCompareValueGet();
+}
+
+
+//*****************************************************************************
+//
+// Switch to XOSC_HF if XOSC_HF is ready.
+//
+//*****************************************************************************
+bool
+OSCHF_AttemptToSwitchToXosc( void )
+{
+ uint32_t startupTimeInUs;
+ uint32_t prevLimmit25InUs;
+
+#if ( defined( ROM_OSCClockSourceGet ))
+ if ( ROM_OSCClockSourceGet( OSC_SRC_CLK_HF ) == OSC_XOSC_HF )
+#else
+ if ( OSCClockSourceGet( OSC_SRC_CLK_HF ) == OSC_XOSC_HF )
+#endif
+ {
+ // Already on XOSC - nothing to do
+ return ( 1 );
+ }
+ if ( OSCHfSourceReady()) {
+ OSCHfSourceSwitch();
+
+ // Store startup time, but limit to 25 percent reduction each time.
+ oscHfGlobals.timeXoscStable_CV = AONRTCCurrentCompareValueGet();
+ startupTimeInUs = RTC_CV_TO_US( oscHfGlobals.timeXoscStable_CV - oscHfGlobals.timeXoscOn_CV );
+ prevLimmit25InUs = oscHfGlobals.previousStartupTimeInUs;
+ prevLimmit25InUs -= ( prevLimmit25InUs >> 2 ); // 25 percent margin
+ oscHfGlobals.previousStartupTimeInUs = startupTimeInUs;
+ if ( prevLimmit25InUs > startupTimeInUs ) {
+ oscHfGlobals.previousStartupTimeInUs = prevLimmit25InUs;
+ }
+ return ( 1 );
+ }
+ return ( 0 );
+}
+
+
+//*****************************************************************************
+//
+// Switch to RCOSC_HF and turn off XOSC_HF
+//
+//*****************************************************************************
+void
+OSCHF_SwitchToRcOscTurnOffXosc( void )
+{
+#if ( defined( ROM_OSCClockSourceSet ))
+ ROM_OSCClockSourceSet( OSC_SRC_CLK_HF, OSC_RCOSC_HF );
+#else
+ OSCClockSourceSet( OSC_SRC_CLK_HF, OSC_RCOSC_HF );
+#endif
+
+ // Do the switching if not already running on RCOSC_HF
+#if ( defined( ROM_OSCClockSourceGet ))
+ if ( ROM_OSCClockSourceGet( OSC_SRC_CLK_HF ) != OSC_RCOSC_HF )
+#else
+ if ( OSCClockSourceGet( OSC_SRC_CLK_HF ) != OSC_RCOSC_HF )
+#endif
+ {
+ OSCHfSourceSwitch();
+ }
+
+ oscHfGlobals.timeXoscOff_CV = AONRTCCurrentCompareValueGet();
+ oscHfGlobals.tempXoscOff = AONBatMonTemperatureGetDegC();
+}
+
+//*****************************************************************************
+//
+// Adjust the XOSC HF cap array relative to the factory setting
+//
+//*****************************************************************************
+void
+OSC_AdjustXoscHfCapArray( int32_t capArrDelta )
+{
+ // read the MODE_CONF register in CCFG
+ uint32_t ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF );
+ // Clear CAP_MODE and the CAPARRAY_DELATA field
+ ccfg_ModeConfReg &= ~( CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M | CCFG_MODE_CONF_XOSC_CAP_MOD_M );
+ // Insert new delta value
+ ccfg_ModeConfReg |= ((((uint32_t)capArrDelta) << CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S ) & CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M );
+ // Update the HW register with the new delta value
+ DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL1, SetupGetTrimForAnabypassValue1( ccfg_ModeConfReg ));
+}
+
+//*****************************************************************************
+//
+// Initialize the frequency offset curve fitting parameters
+// These are either picked diretly from FCFG1:FREQ_OFFSET & FCFG1:MISC_CONF_2 or
+// calculated based on the FCFG1:HPOSC_MEAS_x parameters.
+//
+//*****************************************************************************
+
+// Using the following hardcoded constants (Using temporary constants for now)
+#define D1OFFSET_p25C -24
+#define D2OFFSET_p85C -36
+#define D3OFFSET_m40C 18
+#define P3_POLYNOMIAL -47
+#define N_INSERTIONS 3
+
+typedef struct {
+ int32_t dFreq ;
+ int32_t temp ;
+} insertion_t ;
+
+static void
+InitializeMeasurmentSet( insertion_t * pInsertion, uint32_t registerAddress, int32_t deltaOffset, int32_t p3PolOffset )
+{
+ // Doing the following adjustment to the deltaFrequence before finding the polynomials P0, P1, P2
+ // Dx = Dx + DxOFFSET - ((P3*Tx^3)/2^18)
+ uint32_t insertionData = HWREG( registerAddress );
+ pInsertion->dFreq = (((int32_t)( insertionData << ( 32 - FCFG1_HPOSC_MEAS_1_HPOSC_D1_W - FCFG1_HPOSC_MEAS_1_HPOSC_D1_S )))
+ >> ( 32 - FCFG1_HPOSC_MEAS_1_HPOSC_D1_W ));
+ pInsertion->temp = (((int32_t)( insertionData << ( 32 - FCFG1_HPOSC_MEAS_1_HPOSC_T1_W - FCFG1_HPOSC_MEAS_1_HPOSC_T1_S )))
+ >> ( 32 - FCFG1_HPOSC_MEAS_1_HPOSC_T1_W ));
+ pInsertion->dFreq = pInsertion->dFreq + deltaOffset - (( p3PolOffset * pInsertion->temp * pInsertion->temp * pInsertion->temp ) >> 18 );
+}
+
+static void
+FindPolynomialsAndUpdateGlobals( insertion_t * pMeasurment )
+{
+ uint32_t loopCount ;
+ int32_t polynomial_0 ;
+ int32_t polynomial_1 ;
+ int32_t polynomial_2 ;
+
+ int32_t Syi_ = 0 ;
+ int32_t Sxi_ = 0 ;
+ int32_t Sxi2_ = 0 ;
+ int32_t Sxiyi_ = 0 ;
+ int32_t Sxi2yi_ = 0 ;
+ int32_t Sxi3_ = 0 ;
+ int32_t Sxi4_ = 0 ;
+
+ for ( loopCount = 0 ; loopCount < N_INSERTIONS ; loopCount++ ) {
+ int32_t x ;
+ int32_t x2 ;
+ int32_t y ;
+
+ x = pMeasurment[ loopCount ].temp ;
+ x2 = ( x * x );
+ y = pMeasurment[ loopCount ].dFreq ;
+
+ Syi_ += ( y );
+ Sxi_ += ( x );
+ Sxi2_ += ( x2 );
+ Sxiyi_ += ( x * y );
+ Sxi2yi_ += ( x2 * y );
+ Sxi3_ += ( x2 * x );
+ Sxi4_ += ( x2 * x2 );
+ }
+
+ int32_t Sxx_ = ( Sxi2_ * N_INSERTIONS ) - ( Sxi_ * Sxi_ );
+ int32_t Sxy_ = ( Sxiyi_ * N_INSERTIONS ) - ( Sxi_ * Syi_ );
+ int32_t Sxx2_ = ( Sxi3_ * N_INSERTIONS ) - ( Sxi_ * Sxi2_ );
+ int32_t Sx2y_ = ( Sxi2yi_ * N_INSERTIONS ) - ( Sxi2_ * Syi_ );
+ int32_t Sx2x2_ = ( Sxi4_ * N_INSERTIONS ) - ( Sxi2_ * Sxi2_ );
+
+ int32_t divisor = ((((int64_t) Sxx_ * Sx2x2_ ) - ((int64_t) Sxx2_ * Sxx2_ )) + (1<<9)) >> 10 ;
+ if ( divisor == 0 ) {
+ polynomial_2 = 0 ;
+ polynomial_1 = 0 ;
+ } else {
+ polynomial_2 = (((int64_t) Sx2y_ * Sxx_ ) - ((int64_t) Sxy_ * Sxx2_ )) / divisor ;
+ polynomial_1 = (((int64_t) Sxy_ * Sx2x2_ ) - ((int64_t) Sx2y_ * Sxx2_ )) / divisor ;
+ }
+ polynomial_0 = ( Syi_ - (((( polynomial_1 * Sxi_ ) + ( polynomial_2 * Sxi2_ )) + (1<<9)) >> 10 )) / N_INSERTIONS ;
+ polynomial_1 = ( polynomial_1 + (1<<6)) >> 7 ;
+
+ _hpOscPolynomials[ 0 ] = polynomial_0 ;
+ _hpOscPolynomials[ 1 ] = polynomial_1 ;
+ _hpOscPolynomials[ 2 ] = polynomial_2 ;
+ _hpOscPolynomials[ 3 ] = P3_POLYNOMIAL ;
+}
+
+//*****************************************************************************
+// Degub function to calculate the HPOSC polynomials for experimental data sets.
+//*****************************************************************************
+void
+OSC_HPOSC_Debug_InitFreqOffsetParams( HposcDebugData_t * pDebugData )
+{
+ // Calculate the curve fitting parameters from temp insertion measurements
+ // But first adjust the measurements with constants found in characterization
+ insertion_t pMeasurment[ 3 ];
+
+ InitializeMeasurmentSet( &pMeasurment[ 0 ], (uint32_t)&pDebugData->meas_1, pDebugData->offsetD1, pDebugData->polyP3 );
+ InitializeMeasurmentSet( &pMeasurment[ 1 ], (uint32_t)&pDebugData->meas_2, pDebugData->offsetD2, pDebugData->polyP3 );
+ InitializeMeasurmentSet( &pMeasurment[ 2 ], (uint32_t)&pDebugData->meas_3, pDebugData->offsetD3, pDebugData->polyP3 );
+
+ FindPolynomialsAndUpdateGlobals( pMeasurment );
+}
+
+//*****************************************************************************
+// The general HPOSC initialization function - Must always be called before using HPOSC
+//*****************************************************************************
+void
+OSC_HPOSCInitializeFrequencyOffsetParameters( void )
+{
+ {
+ // Calculate the curve fitting parameters from temp insertion measurements
+ // But first adjust the measurements with constants found in characterization
+ insertion_t pMeasurment[ 3 ];
+
+ InitializeMeasurmentSet( &pMeasurment[ 0 ], FCFG1_BASE + FCFG1_O_HPOSC_MEAS_1, D1OFFSET_p25C, P3_POLYNOMIAL );
+ InitializeMeasurmentSet( &pMeasurment[ 1 ], FCFG1_BASE + FCFG1_O_HPOSC_MEAS_2, D2OFFSET_p85C, P3_POLYNOMIAL );
+ InitializeMeasurmentSet( &pMeasurment[ 2 ], FCFG1_BASE + FCFG1_O_HPOSC_MEAS_3, D3OFFSET_m40C, P3_POLYNOMIAL );
+
+ FindPolynomialsAndUpdateGlobals( pMeasurment );
+ }
+}
+
+//*****************************************************************************
+//
+// Calculate the temperature dependent relative frequency offset of HPOSC
+//
+//*****************************************************************************
+int32_t
+OSC_HPOSCRelativeFrequencyOffsetGet( int32_t tempDegC )
+{
+ // Estimate HPOSC frequency, using temperature and curve fitting parameters
+
+ int32_t paramP0 = _hpOscPolynomials[ 0 ];
+ int32_t paramP1 = _hpOscPolynomials[ 1 ];
+ int32_t paramP2 = _hpOscPolynomials[ 2 ];
+ int32_t paramP3 = _hpOscPolynomials[ 3 ];
+
+ // Now we can find the HPOSC freq offset, given as a signed variable d, expressed by:
+ //
+ // F_HPOSC = F_nom * (1 + d/(2^22)) , where: F_HPOSC = HPOSC frequency
+ // F_nom = nominal clock source frequency (e.g. 48.000 MHz)
+ // d = describes relative freq offset
+
+ // We can estimate the d variable, using temperature compensation parameters:
+ //
+ // d = P0 + P1*(t - T0) + P2*(t - T0)^2 + P3*(t - T0)^3, where: P0,P1,P2,P3 are curve fitting parameters from FCFG1
+ // t = current temperature (from temp sensor) in deg C
+ // T0 = 27 deg C (fixed temperature constant)
+ int32_t tempDelta = (tempDegC - 27);
+ int32_t tempDeltaX2 = tempDelta * tempDelta;
+ int32_t d = paramP0 + ((tempDelta*paramP1)>>3) + ((tempDeltaX2*paramP2)>>10) + ((tempDeltaX2*tempDelta*paramP3)>>18);
+
+ return ( d );
+}
+
+//*****************************************************************************
+//
+// Converts the relative frequency offset of HPOSC to the RF Core parameter format.
+//
+//*****************************************************************************
+int16_t
+OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert( int32_t HPOSC_RelFreqOffset )
+{
+ // The input argument, hereby referred to simply as "d", describes the frequency offset
+ // of the HPOSC relative to the nominal frequency in this way:
+ //
+ // F_HPOSC = F_nom * (1 + d/(2^22))
+ //
+ // But for use by the radio, to compensate the frequency error, we need to find the
+ // frequency offset "rfcFreqOffset" defined in the following format:
+ //
+ // F_nom = F_HPOSC * (1 + rfCoreFreqOffset/(2^22))
+ //
+ // To derive "rfCoreFreqOffset" from "d" we combine the two above equations and get:
+ //
+ // (1 + rfCoreFreqOffset/(2^22)) = (1 + d/(2^22))^-1
+ //
+ // Which can be rewritten into:
+ //
+ // rfCoreFreqOffset = -d*(2^22) / ((2^22) + d)
+ //
+ // = -d * [ 1 / (1 + d/(2^22)) ]
+ //
+ // To avoid doing a 64-bit division due to the (1 + d/(2^22))^-1 expression,
+ // we can use Taylor series (Maclaurin series) to approximate it:
+ //
+ // 1 / (1 - x) ~= 1 + x + x^2 + x^3 + x^4 + ... etc (Maclaurin series)
+ //
+ // In our case, we have x = - d/(2^22), and we only include up to the first
+ // order term of the series, as the second order term ((d^2)/(2^44)) is very small:
+ //
+ // freqError ~= -d + d^2/(2^22) (+ small approximation error)
+ //
+ // The approximation error is negligible for our use.
+
+ int32_t rfCoreFreqOffset = -HPOSC_RelFreqOffset + (( HPOSC_RelFreqOffset * HPOSC_RelFreqOffset ) >> 22 );
+
+ return ( rfCoreFreqOffset );
+}
+
+//*****************************************************************************
+//
+// Compensate the RTC increment based on the relative frequency offset of HPOSC
+//
+//*****************************************************************************
+void
+OSC_HPOSCRtcCompensate( int32_t relFreqOffset )
+{
+ uint32_t rtcSubSecInc;
+ uint32_t lfClkFrequency;
+ uint32_t hfFreq;
+ int64_t calcFactor;
+
+ // Calculate SCLK_HF frequency, defined as:
+ // hfFreq = 48000000 * (1 + relFreqOffset/(2^22))
+ if( relFreqOffset >= 0 )
+ {
+ calcFactor = ( ( 48000000 * (int64_t)relFreqOffset ) + 0x200000 ) / 0x400000;
+ }
+ else
+ {
+ calcFactor = ( ( 48000000 * (int64_t)relFreqOffset ) - 0x200000 ) / 0x400000;
+ }
+ hfFreq = 48000000 + calcFactor;
+
+ // Calculate SCLK_LF frequency, defined as SCLK_LF_FREQ = SCLK_HF_FREQ / 1536
+ lfClkFrequency = ( hfFreq + 768 ) / 1536;
+
+ // Calculate SUBSECINC, defined as: SUBSECINC = 2^38 / SCLK_LF_FREQ
+ rtcSubSecInc = 0x4000000000 / lfClkFrequency;
+
+ /* Update SUBSECINC value */
+ SetupSetAonRtcSubSecInc(rtcSubSecInc);
+}
+
+//*****************************************************************************
+//
+// Get crystal amplitude (assuming crystal is running).
+//
+//*****************************************************************************
+uint32_t
+OSCHF_DebugGetCrystalAmplitude( void )
+{
+ uint32_t oscCfgRegCopy ;
+ uint32_t startTime ;
+ uint32_t deltaTime ;
+ uint32_t ampValue ;
+
+ // The specified method is as follows:
+ // 1. Set minimum interval between oscillator amplitude calibrations.
+ // (Done by setting PER_M=0 and PER_E=1)
+ // 2. Wait approximately 4 milliseconds in order to measure over a
+ // moderately large number of calibrations.
+ // 3. Read out the crystal amplitude value from the peek detector.
+ // 4. Restore original oscillator amplitude calibrations interval.
+ // 5. Return crystal amplitude value converted to millivolt.
+ oscCfgRegCopy = HWREG( AON_PMCTL_BASE + AON_PMCTL_O_OSCCFG );
+ HWREG( AON_PMCTL_BASE + AON_PMCTL_O_OSCCFG ) = ( 1 << AON_PMCTL_OSCCFG_PER_E_S );
+ startTime = AONRTCCurrentCompareValueGet();
+ do {
+ deltaTime = AONRTCCurrentCompareValueGet() - startTime;
+ } while ( deltaTime < ((uint32_t)( 0.004 * FACTOR_SEC_TO_COMP_VAL_FORMAT )));
+ ampValue = ( HWREG( AUX_DDI0_OSC_BASE + DDI_0_OSC_O_STAT1 ) &
+ DDI_0_OSC_STAT1_HPM_UPDATE_AMP_M ) >>
+ DDI_0_OSC_STAT1_HPM_UPDATE_AMP_S ;
+ HWREG( AON_PMCTL_BASE + AON_PMCTL_O_OSCCFG ) = oscCfgRegCopy;
+
+ return ( ampValue * 15 );
+}
+
+//*****************************************************************************
+//
+// Get the expected average crystal amplitude.
+//
+//*****************************************************************************
+uint32_t
+OSCHF_DebugGetExpectedAverageCrystalAmplitude( void )
+{
+ uint32_t ampCompTh1 ;
+ uint32_t highThreshold ;
+ uint32_t lowThreshold ;
+
+ ampCompTh1 = HWREG( AUX_DDI0_OSC_BASE + DDI_0_OSC_O_AMPCOMPTH1 );
+ highThreshold = ( ampCompTh1 & DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_M ) >>
+ DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_S ;
+ lowThreshold = ( ampCompTh1 & DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_M ) >>
+ DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_S ;
+
+ return ((( highThreshold + lowThreshold ) * 15 ) >> 1 );
+}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/osc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/osc.h
new file mode 100644
index 0000000..52fe0f3
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/osc.h
@@ -0,0 +1,730 @@
+/******************************************************************************
+* Filename: osc.h
+* Revised: 2019-02-14 09:35:31 +0100 (Thu, 14 Feb 2019)
+* Revision: 54539
+*
+* Description: Defines and prototypes for the system oscillator control.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup system_control_group
+//! @{
+//! \addtogroup osc_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __OSC_H__
+#define __OSC_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "../inc/hw_aon_pmctl.h"
+#include "../inc/hw_ccfg.h"
+#include "../inc/hw_fcfg1.h"
+#include "../inc/hw_types.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_ddi.h"
+#include "../inc/hw_ddi_0_osc.h"
+#include "rom.h"
+#include "ddi.h"
+#include "debug.h"
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// This section renames all functions that are not "static inline", so that
+// calling these functions will default to implementation in flash. At the end
+// of this file a second renaming will change the defaults to implementation in
+// ROM for available functions.
+//
+// To force use of the implementation in flash, e.g. for debugging:
+// - Globally: Define DRIVERLIB_NOROM at project level
+// - Per function: Use prefix "NOROM_" when calling the function
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #define OSCClockSourceSet NOROM_OSCClockSourceSet
+ #define OSCClockSourceGet NOROM_OSCClockSourceGet
+ #define OSCHF_GetStartupTime NOROM_OSCHF_GetStartupTime
+ #define OSCHF_TurnOnXosc NOROM_OSCHF_TurnOnXosc
+ #define OSCHF_AttemptToSwitchToXosc NOROM_OSCHF_AttemptToSwitchToXosc
+ #define OSCHF_SwitchToRcOscTurnOffXosc NOROM_OSCHF_SwitchToRcOscTurnOffXosc
+ #define OSCHF_DebugGetCrystalAmplitude NOROM_OSCHF_DebugGetCrystalAmplitude
+ #define OSCHF_DebugGetExpectedAverageCrystalAmplitude NOROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude
+ #define OSC_HPOSC_Debug_InitFreqOffsetParams NOROM_OSC_HPOSC_Debug_InitFreqOffsetParams
+ #define OSC_HPOSCInitializeFrequencyOffsetParameters NOROM_OSC_HPOSCInitializeFrequencyOffsetParameters
+ #define OSC_HPOSCRelativeFrequencyOffsetGet NOROM_OSC_HPOSCRelativeFrequencyOffsetGet
+ #define OSC_AdjustXoscHfCapArray NOROM_OSC_AdjustXoscHfCapArray
+ #define OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert NOROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert
+ #define OSC_HPOSCRtcCompensate NOROM_OSC_HPOSCRtcCompensate
+#endif
+
+//*****************************************************************************
+//
+// Defines for the High Frequency XTAL Power mode
+//
+//*****************************************************************************
+#define LOW_POWER_XOSC 1
+#define HIGH_POWER_XOSC 0
+
+//*****************************************************************************
+//
+// Defines for the High Frequency XTAL Power mode
+//
+//*****************************************************************************
+#define OSC_SRC_CLK_HF 0x00000001
+#define OSC_SRC_CLK_LF 0x00000004
+
+#define OSC_RCOSC_HF 0x00000000
+#define OSC_XOSC_HF 0x00000001
+#define OSC_RCOSC_LF 0x00000002
+#define OSC_XOSC_LF 0x00000003
+
+#define SCLK_HF_RCOSC_HF 0
+#define SCLK_HF_XOSC_HF 1
+
+#define SCLK_LF_FROM_RCOSC_HF 0
+#define SCLK_LF_FROM_XOSC_HF 1
+#define SCLK_LF_FROM_RCOSC_LF 2
+#define SCLK_LF_FROM_XOSC_LF 3
+
+//*****************************************************************************
+//
+// API Functions and prototypes
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \brief Set Power Mode for High Frequency XTAL Oscillator.
+//!
+//! \param ui32Mode is the power mode for the HF XTAL.
+//! - \ref LOW_POWER_XOSC
+//! - \ref HIGH_POWER_XOSC
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+OSCXHfPowerModeSet(uint32_t ui32Mode)
+{
+ // Check the arguments.
+ ASSERT((ui32Mode == LOW_POWER_XOSC) ||
+ (ui32Mode == HIGH_POWER_XOSC));
+
+ // Change the power mode.
+ DDI16BitWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE,
+ ui32Mode);
+}
+
+//*****************************************************************************
+//
+//! \brief Enables OSC clock loss event detection.
+//!
+//! Enables the clock loss event flag to be raised if a clock loss is detected.
+//!
+//! \note OSC clock loss event must be disabled before SCLK_LF clock source is
+//! changed (by calling \ref OSCClockSourceSet()) and remain disabled until the
+//! change is confirmed (by calling \ref OSCClockSourceGet()).
+//!
+//! \return None
+//!
+//! \sa \ref OSCClockLossEventDisable()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+OSCClockLossEventEnable( void )
+{
+ DDI16BitfieldWrite( AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0,
+ DDI_0_OSC_CTL0_CLK_LOSS_EN_M,
+ DDI_0_OSC_CTL0_CLK_LOSS_EN_S, 1 );
+}
+
+//*****************************************************************************
+//
+//! \brief Disables OSC clock loss event detection.
+//!
+//! Disabling the OSC clock loss event does also clear the clock loss event flag.
+//!
+//! \note OSC clock loss event must be disabled before SCLK_LF clock source is
+//! changed (by calling \ref OSCClockSourceSet()) and remain disabled until the
+//! change is confirmed (by calling \ref OSCClockSourceGet()).
+//!
+//! \return None
+//!
+//! \sa \ref OSCClockLossEventEnable()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+OSCClockLossEventDisable( void )
+{
+ DDI16BitfieldWrite( AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0,
+ DDI_0_OSC_CTL0_CLK_LOSS_EN_M,
+ DDI_0_OSC_CTL0_CLK_LOSS_EN_S, 0 );
+}
+
+//*****************************************************************************
+//
+//! \brief Configure the oscillator input to the a source clock.
+//!
+//! Use this function to set the oscillator source for one or more of the
+//! system source clocks.
+//!
+//! When selecting the high frequency clock source (OSC_SRC_CLK_HF), this function will not do
+//! the actual switch. Enabling the high frequency XTAL can take several hundred
+//! micro seconds, so the actual switch is done in a separate function, \ref OSCHfSourceSwitch(),
+//! leaving System CPU free to perform other tasks as the XTAL starts up.
+//!
+//! \note The High Frequency (\ref OSC_SRC_CLK_HF) can only be derived from the
+//! high frequency oscillator. The Low Frequency source clock (\ref OSC_SRC_CLK_LF)
+//! can be derived from all 4 oscillators.
+//!
+//! \note If enabling \ref OSC_XOSC_LF it is not safe to go to powerdown/shutdown
+//! until the LF clock is running which can be checked using \ref OSCClockSourceGet().
+//!
+//! \note Clock loss reset generation must be disabled before SCLK_LF (\ref OSC_SRC_CLK_LF)
+//! clock source is changed and remain disabled until the change is confirmed.
+//!
+//! \param ui32SrcClk is the source clocks to configure.
+//! - \ref OSC_SRC_CLK_HF
+//! - \ref OSC_SRC_CLK_LF
+//! \param ui32Osc is the oscillator that drives the source clock.
+//! - \ref OSC_RCOSC_HF
+//! - \ref OSC_XOSC_HF
+//! - \ref OSC_RCOSC_LF (only when ui32SrcClk is \ref OSC_SRC_CLK_LF)
+//! - \ref OSC_XOSC_LF (only when ui32SrcClk is \ref OSC_SRC_CLK_LF)
+//!
+//! \sa \ref OSCClockSourceGet(), \ref OSCHfSourceSwitch()
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void OSCClockSourceSet(uint32_t ui32SrcClk, uint32_t ui32Osc);
+
+//*****************************************************************************
+//
+//! \brief Get the source clock settings.
+//!
+//! Use this function to get the oscillator source for one of the system source
+//! clocks.
+//!
+//! \param ui32SrcClk is the source clock to check.
+//! - \ref OSC_SRC_CLK_HF
+//! - \ref OSC_SRC_CLK_LF
+//!
+//! \return Returns the type of oscillator that drives the clock source.
+//! - \ref OSC_RCOSC_HF
+//! - \ref OSC_XOSC_HF
+//! - \ref OSC_RCOSC_LF
+//! - \ref OSC_XOSC_LF
+//!
+//! \sa \ref OSCClockSourceSet(), \ref OSCHfSourceSwitch()
+//
+//*****************************************************************************
+extern uint32_t OSCClockSourceGet(uint32_t ui32SrcClk);
+
+//*****************************************************************************
+//
+//! \brief Check if the HF clock source is ready to be switched.
+//!
+//! If a request to switch the HF clock source has been made, this function
+//! can be used to check if the clock source is ready to be switched.
+//!
+//! Once the HF clock source is ready the switch can be performed by calling
+//! the \ref OSCHfSourceSwitch()
+//!
+//! \return Returns status of HF clock source:
+//! - \c true : HF clock source is ready.
+//! - \c false : HF clock source is \b not ready.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+OSCHfSourceReady(void)
+{
+ // Return the readiness of the HF clock source
+ return (DDI16BitfieldRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_STAT0,
+ DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_M,
+ DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_S)) ?
+ true : false;
+}
+
+//*****************************************************************************
+//
+//! \brief Switch the high frequency clock.
+//!
+//! When switching the HF clock source the clock period might be prolonged
+//! leaving the clock 'stuck-at' high or low for a few cycles. To ensure that
+//! this does not coincide with a read access to the Flash, potentially
+//! freezing the device, the HF clock source switch must be executed from ROM.
+//!
+//! \note This function will not return until the clock source has been
+//! switched. It is left to the programmer to ensure, that there is a pending
+//! request for a HF clock source switch before this function is called.
+//!
+//! \return None
+//!
+//! \sa \ref OSCClockSourceSet()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+OSCHfSourceSwitch(void)
+{
+ // Read target clock (lower half of the 32-bit CTL0 register)
+ uint16_t hfSrc = HWREGH(AUX_DDI0_OSC_BASE + DDI_0_OSC_O_CTL0) & DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_M;
+
+ // If target clock source is RCOSC, change clock source for DCDC to RCOSC
+ if(hfSrc == DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_RCOSC)
+ {
+ // Force DCDC to use RCOSC before switching SCLK_HF to RCOSC
+ HWREG(AUX_DDI0_OSC_BASE + DDI_O_MASK16B + (DDI_0_OSC_O_CTL0 << 1) + 4) = DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M | (DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M >> 16);
+ // Dummy read to ensure that the write has propagated
+ HWREGH(AUX_DDI0_OSC_BASE + DDI_0_OSC_O_CTL0);
+ }
+
+ // Switch the HF clock source
+ HapiHFSourceSafeSwitch();
+
+ // If target clock source is XOSC, change clock source for DCDC to "auto"
+ if(hfSrc == DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_XOSC)
+ {
+ // Set DCDC clock source back to "auto" after SCLK_HF was switched to XOSC
+ HWREG(AUX_DDI0_OSC_BASE + DDI_O_MASK16B + (DDI_0_OSC_O_CTL0 << 1) + 4) = DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M;
+ }
+}
+
+//*****************************************************************************
+//
+//! \brief Identifies if HPOSC is enabled.
+//!
+//! This function checks if the device supports HPOSC and that HPOSC is selected
+//! as HF oscillator for use when the radio is active.
+//!
+//! \return Returns status of HPOSC functionality:
+//! - \c true : HPOSC is enabled.
+//! - \c false : HPOSC is not enabled.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+OSC_IsHPOSCEnabled(void)
+{
+ bool enabled = false;
+
+ if((( HWREG(CCFG_BASE + CCFG_O_MODE_CONF) & CCFG_MODE_CONF_XOSC_FREQ_M) == CCFG_MODE_CONF_XOSC_FREQ_HPOSC) &&
+ (( HWREG(FCFG1_BASE + FCFG1_O_OSC_CONF) & FCFG1_OSC_CONF_HPOSC_OPTION) == 0))
+ {
+ enabled = true;
+ }
+
+ return (enabled);
+}
+
+//*****************************************************************************
+//
+//! \brief Identifies if HPOSC is enabled and that SCLK_LF is derived from XOSC_HF.
+//!
+//! This function checks if the device supports HPOSC and that HPOSC is selected
+//! as HF oscillator for use when the radio is active and also that SCLK_LF is
+//! derived from XOSC_HF.
+//!
+//! \return Returns status of HPOSC and SCLK_LF configuration:
+//! - \c true : HPOSC is enabled and SCLK_LF is derived from XOSC_HF.
+//! - \c false : Either HPOSC not enabled or SCLK_LF is not derived from XOSC_HF.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+OSC_IsHPOSCEnabledWithHfDerivedLfClock(void)
+{
+ bool enabled = false;
+
+ // Check configuration by reading lower half of the 32-bit CTL0 register
+ uint16_t regVal = HWREGH(AUX_DDI0_OSC_BASE + DDI_0_OSC_O_CTL0);
+ if( ( ( regVal & DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_M ) == DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCHFDLF ) &&
+ ( ( regVal & DDI_0_OSC_CTL0_HPOSC_MODE_EN_M ) == DDI_0_OSC_CTL0_HPOSC_MODE_EN ) )
+ {
+ enabled = true;
+ }
+
+ return (enabled);
+}
+
+//*****************************************************************************
+//
+//! \brief Returns maximum startup time (in microseconds) of XOSC_HF.
+//!
+//! The startup time depends on several factors. This function calculates the
+//! maximum startup time based on statistical information.
+//!
+//! \param timeUntilWakeupInMs indicates how long time (milliseconds) to the
+//! startup will occur.
+//!
+//! \return Time margin to use in microseconds.
+//
+//*****************************************************************************
+extern uint32_t OSCHF_GetStartupTime( uint32_t timeUntilWakeupInMs );
+
+//*****************************************************************************
+//
+//! \brief Turns on XOSC_HF (but without switching to XOSC_HF).
+//!
+//! This function simply indicates the need for XOSC_HF to the hardware which
+//! initiates the XOSC_HF startup.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void OSCHF_TurnOnXosc( void );
+
+//*****************************************************************************
+//
+//! \brief Switch to XOSC_HF if XOSC_HF is ready.
+//!
+//! This is a non-blocking function checking if the XOSC_HF is ready and
+//! performs the switching if ready. The function is somewhat blocking in the
+//! case where switching is performed.
+//!
+//! \return Returns status of the XOSC_HF switching:
+//! - \c true : Switching to XOSC_HF has occurred.
+//! - \c false : Switching has not occurred.
+//
+//*****************************************************************************
+extern bool OSCHF_AttemptToSwitchToXosc( void );
+
+//*****************************************************************************
+//
+//! \brief Switch to RCOSC_HF and turn off XOSC_HF.
+//!
+//! This operation takes approximately 50 microseconds (can be shorter if
+//! RCOSC_HF already was running).
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void OSCHF_SwitchToRcOscTurnOffXosc( void );
+
+//*****************************************************************************
+//
+//! \brief Get crystal amplitude (assuming crystal is running).
+//!
+//! \note This is a debug function only.
+//! It is hence not recommended to call this function in normal operation.
+//!
+//! This function uses an on-chip ADC and peak detector for reading the crystal
+//! amplitude. The measurement time is set to 4 milliseconds and this function
+//! does not return before the measurement is done.
+//!
+//! Expected value is \ref OSCHF_DebugGetExpectedAverageCrystalAmplitude +/- 50 millivolt.
+//!
+//! \return Returns crystal amplitude in millivolt.
+//!
+//! \sa OSCHF_DebugGetExpectedAverageCrystalAmplitude()
+//
+//*****************************************************************************
+extern uint32_t OSCHF_DebugGetCrystalAmplitude( void );
+
+//*****************************************************************************
+//
+//! \brief Get the expected average crystal amplitude.
+//!
+//! \note This is a debug function only.
+//! It is hence not recommended to call this function in normal operation.
+//!
+//! This function read the configured high and low thresholds and returns
+//! the mean value converted to millivolt.
+//!
+//! \return Returns expected average crystal amplitude in millivolt.
+//!
+//! \sa OSCHF_DebugGetCrystalAmplitude()
+//
+//*****************************************************************************
+extern uint32_t OSCHF_DebugGetExpectedAverageCrystalAmplitude( void );
+
+//*****************************************************************************
+//
+//! \brief Data structure for experimental HPOSC polynomials calculation.
+//!
+//! The structure of the meas_1, meas_2 and meas_3 parameter is
+//! as defined in FCFG1_O_HPOSC_MEAS_1, 2 and 3.
+//!
+//! \sa OSC_HPOSC_Debug_InitFreqOffsetParams()
+//
+//*****************************************************************************
+typedef struct {
+ uint32_t meas_1 ; //!< Measurement set 1 (typically at room temp)
+ uint32_t meas_2 ; //!< Measurement set 2 (typically at high temp)
+ uint32_t meas_3 ; //!< Measurement set 3 (typically at low temp)
+ int32_t offsetD1 ; //!< Offset to measurement set 1
+ int32_t offsetD2 ; //!< Offset to measurement set 2
+ int32_t offsetD3 ; //!< Offset to measurement set 3
+ int32_t polyP3 ; //!< The P3 polynomial
+} HposcDebugData_t;
+
+//*****************************************************************************
+//
+//! \brief Debug function to calculate the HPOSC polynomials for experimental data sets.
+//!
+//! \param pDebugData pointer to the input data collected in \ref HposcDebugData_t
+//!
+//! \return None
+//!
+//! \sa OSC_HPOSCInitializeFrequencyOffsetParameters()
+//
+//*****************************************************************************
+extern void OSC_HPOSC_Debug_InitFreqOffsetParams( HposcDebugData_t * pDebugData );
+
+//*****************************************************************************
+//
+//! \brief HPOSC initialization function. Must always be called before using HPOSC.
+//!
+//! Calculates the fitting curve parameters (polynomials) to used by the
+//! HPOSC temperature compensation.
+//!
+//! \return None
+//!
+//! \sa OSC_HPOSC_Debug_InitFreqOffsetParams()
+//
+//*****************************************************************************
+extern void OSC_HPOSCInitializeFrequencyOffsetParameters( void );
+
+//*****************************************************************************
+//
+//! \brief Calculate the temperature dependent relative frequency offset of HPOSC
+//!
+//! The HPOSC (High Precision Oscillator) frequency will vary slightly with chip temperature.
+//! The frequency offset from the nominal value can be predicted based on
+//! second order linear interpolation using coefficients measured in chip
+//! production and stored as factory configuration parameters.
+//!
+//! This function calculates the relative frequency offset, defined as:
+//! <pre>
+//! F_HPOSC = F_nom * (1 + d/(2^22))
+//! </pre>
+//! where
+//! - F_HPOSC is the current HPOSC frequency.
+//! - F_nom is the nominal oscillator frequency, assumed to be 48.000 MHz.
+//! - d is the relative frequency offset (the value returned).
+//!
+//! By knowing the relative frequency offset it is then possible to compensate
+//! any timing related values accordingly.
+//!
+//! \param tempDegC is the chip temperature in degrees Celsius. Use the
+//! function \ref AONBatMonTemperatureGetDegC() to get current chip temperature.
+//!
+//! \return Returns the relative frequency offset parameter d.
+//!
+//! \sa OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert(), AONBatMonTemperatureGetDegC()
+//
+//*****************************************************************************
+extern int32_t OSC_HPOSCRelativeFrequencyOffsetGet( int32_t tempDegC );
+
+//*****************************************************************************
+//
+//! \brief Adjust the XOSC HF cap array relative to the factory setting
+//!
+//! The cap array factory setting (FCFG) can be converted to a number in the range 0 - 63.
+//! Both this function and the customer configuration (CCFG) setting can apply a delta to the FCFG setting.
+//! The CCFG setting is automatically applied at boot time (See ../startup_files/ccfg.c).
+//! Calling this function will discard the CCFG setting and adjust relative to the FCFG setting.
+//!
+//! \note Adjusted value will not take effect before XOSC_HF is stopped and restarted
+//!
+//! \param capArrDelta specifies number of step to adjust the cap array relative to the factory setting.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void OSC_AdjustXoscHfCapArray( int32_t capArrDelta );
+
+//*****************************************************************************
+//
+//! \brief Converts the relative frequency offset of HPOSC to the RF Core parameter format.
+//!
+//! The HPOSC (High Precision Oscillator) clock is used by the RF Core.
+//! To compensate for a frequency offset in the frequency of the clock source,
+//! a frequency offset parameter can be provided as part of the radio configuration
+//! override setting list to enable compensation of the RF synthesizer frequency,
+//! symbol timing, and radio timer to still achieve correct frequencies.
+//!
+//! The RF Core takes a relative frequency offset parameter defined differently
+//! compared to the relative frequency offset parameter returned from function
+//! \ref OSC_HPOSCRelativeFrequencyOffsetGet() and thus needs to be converted:
+//! <pre>
+//! F_nom = F_HPOSC * (1 + RfCoreRelFreqOffset/(2^22))
+//! </pre>
+//! where
+//! - F_nom is the nominal oscillator frequency, assumed to be 48.000 MHz.
+//! - F_HPOSC is the current HPOSC frequency.
+//! - RfCoreRelFreqOffset is the relative frequency offset in the "RF Core" format (the value returned).
+//!
+//! \param HPOSC_RelFreqOffset is the relative frequency offset parameter d returned from \ref OSC_HPOSCRelativeFrequencyOffsetGet()
+//!
+//! \return Returns the relative frequency offset in RF Core format.
+//!
+//! \sa OSC_HPOSCRelativeFrequencyOffsetGet()
+//
+//*****************************************************************************
+extern int16_t OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert( int32_t HPOSC_RelFreqOffset );
+
+//*****************************************************************************
+//
+//! \brief Compensate the RTC increment based on the relative frequency offset of HPOSC
+//!
+//! The HPOSC (High Precision Oscillator) frequency will vary slightly with chip temperature.
+//! This variation forces the RTC increment to be compensated if SCLK_LF is configured
+//! to be derived from the HF clock of HPOSC.
+//! This function must only be called if SCLK_LF is configured to be derived from
+//! the HF clock of HPOSC. The status of this configuration can be determined
+//! by calling the \ref OSC_IsHPOSCEnabledWithHfDerivedLfClock() function.
+//!
+//! This function first calculates the HPOSC frequency, defined as:
+//! <pre>
+//! F_HPOSC = F_nom * (1 + d/(2^22))
+//! </pre>
+//! where
+//! - F_HPOSC is the current HPOSC frequency.
+//! - F_nom is the nominal oscillator frequency, assumed to be 48.000 MHz.
+//! - d is the relative frequency offset given by the input argument relFreqOffset.
+//! Then the SCLK_LF frequency is calculated, defined as:
+//! <pre>
+//! F_SCLK_LF = F_HPOSC / 1536
+//! </pre>
+//! Then the RTC increment SUBSECINC is calculated, defined as;
+//! <pre>
+//! SUBSECINC = (2^38) / F_SCLK_LF
+//! </pre>
+//! Finally the RTC module is updated with the calculated SUBSECINC value.
+//!
+//! \param relFreqOffset is the relative frequency offset parameter d returned from \ref OSC_HPOSCRelativeFrequencyOffsetGet()
+//!
+//! \return None
+//!
+//
+//*****************************************************************************
+extern void OSC_HPOSCRtcCompensate( int32_t relFreqOffset );
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// Redirect to implementation in ROM when available.
+//
+//*****************************************************************************
+#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
+ #include "../driverlib/rom.h"
+ #ifdef ROM_OSCClockSourceSet
+ #undef OSCClockSourceSet
+ #define OSCClockSourceSet ROM_OSCClockSourceSet
+ #endif
+ #ifdef ROM_OSCClockSourceGet
+ #undef OSCClockSourceGet
+ #define OSCClockSourceGet ROM_OSCClockSourceGet
+ #endif
+ #ifdef ROM_OSCHF_GetStartupTime
+ #undef OSCHF_GetStartupTime
+ #define OSCHF_GetStartupTime ROM_OSCHF_GetStartupTime
+ #endif
+ #ifdef ROM_OSCHF_TurnOnXosc
+ #undef OSCHF_TurnOnXosc
+ #define OSCHF_TurnOnXosc ROM_OSCHF_TurnOnXosc
+ #endif
+ #ifdef ROM_OSCHF_AttemptToSwitchToXosc
+ #undef OSCHF_AttemptToSwitchToXosc
+ #define OSCHF_AttemptToSwitchToXosc ROM_OSCHF_AttemptToSwitchToXosc
+ #endif
+ #ifdef ROM_OSCHF_SwitchToRcOscTurnOffXosc
+ #undef OSCHF_SwitchToRcOscTurnOffXosc
+ #define OSCHF_SwitchToRcOscTurnOffXosc ROM_OSCHF_SwitchToRcOscTurnOffXosc
+ #endif
+ #ifdef ROM_OSCHF_DebugGetCrystalAmplitude
+ #undef OSCHF_DebugGetCrystalAmplitude
+ #define OSCHF_DebugGetCrystalAmplitude ROM_OSCHF_DebugGetCrystalAmplitude
+ #endif
+ #ifdef ROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude
+ #undef OSCHF_DebugGetExpectedAverageCrystalAmplitude
+ #define OSCHF_DebugGetExpectedAverageCrystalAmplitude ROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude
+ #endif
+ #ifdef ROM_OSC_HPOSC_Debug_InitFreqOffsetParams
+ #undef OSC_HPOSC_Debug_InitFreqOffsetParams
+ #define OSC_HPOSC_Debug_InitFreqOffsetParams ROM_OSC_HPOSC_Debug_InitFreqOffsetParams
+ #endif
+ #ifdef ROM_OSC_HPOSCInitializeFrequencyOffsetParameters
+ #undef OSC_HPOSCInitializeFrequencyOffsetParameters
+ #define OSC_HPOSCInitializeFrequencyOffsetParameters ROM_OSC_HPOSCInitializeFrequencyOffsetParameters
+ #endif
+ #ifdef ROM_OSC_HPOSCRelativeFrequencyOffsetGet
+ #undef OSC_HPOSCRelativeFrequencyOffsetGet
+ #define OSC_HPOSCRelativeFrequencyOffsetGet ROM_OSC_HPOSCRelativeFrequencyOffsetGet
+ #endif
+ #ifdef ROM_OSC_AdjustXoscHfCapArray
+ #undef OSC_AdjustXoscHfCapArray
+ #define OSC_AdjustXoscHfCapArray ROM_OSC_AdjustXoscHfCapArray
+ #endif
+ #ifdef ROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert
+ #undef OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert
+ #define OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert ROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert
+ #endif
+ #ifdef ROM_OSC_HPOSCRtcCompensate
+ #undef OSC_HPOSCRtcCompensate
+ #define OSC_HPOSCRtcCompensate ROM_OSC_HPOSCRtcCompensate
+ #endif
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __OSC_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/pka.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/pka.c
new file mode 100644
index 0000000..57e4b58
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/pka.c
@@ -0,0 +1,1661 @@
+/******************************************************************************
+* Filename: pka.c
+* Revised: 2018-07-19 15:07:05 +0200 (Thu, 19 Jul 2018)
+* Revision: 52294
+*
+* Description: Driver for the PKA module
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "pka.h"
+
+//*****************************************************************************
+//
+// Handle support for DriverLib in ROM:
+// This section will undo prototype renaming made in the header file
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #undef PKAClearPkaRam
+ #define PKAClearPkaRam NOROM_PKAClearPkaRam
+ #undef PKAGetOpsStatus
+ #define PKAGetOpsStatus NOROM_PKAGetOpsStatus
+ #undef PKAArrayAllZeros
+ #define PKAArrayAllZeros NOROM_PKAArrayAllZeros
+ #undef PKAZeroOutArray
+ #define PKAZeroOutArray NOROM_PKAZeroOutArray
+ #undef PKABigNumModStart
+ #define PKABigNumModStart NOROM_PKABigNumModStart
+ #undef PKABigNumModGetResult
+ #define PKABigNumModGetResult NOROM_PKABigNumModGetResult
+ #undef PKABigNumDivideStart
+ #define PKABigNumDivideStart NOROM_PKABigNumDivideStart
+ #undef PKABigNumDivideGetQuotient
+ #define PKABigNumDivideGetQuotient NOROM_PKABigNumDivideGetQuotient
+ #undef PKABigNumDivideGetRemainder
+ #define PKABigNumDivideGetRemainder NOROM_PKABigNumDivideGetRemainder
+ #undef PKABigNumCmpStart
+ #define PKABigNumCmpStart NOROM_PKABigNumCmpStart
+ #undef PKABigNumCmpGetResult
+ #define PKABigNumCmpGetResult NOROM_PKABigNumCmpGetResult
+ #undef PKABigNumInvModStart
+ #define PKABigNumInvModStart NOROM_PKABigNumInvModStart
+ #undef PKABigNumInvModGetResult
+ #define PKABigNumInvModGetResult NOROM_PKABigNumInvModGetResult
+ #undef PKABigNumMultiplyStart
+ #define PKABigNumMultiplyStart NOROM_PKABigNumMultiplyStart
+ #undef PKABigNumMultGetResult
+ #define PKABigNumMultGetResult NOROM_PKABigNumMultGetResult
+ #undef PKABigNumAddStart
+ #define PKABigNumAddStart NOROM_PKABigNumAddStart
+ #undef PKABigNumAddGetResult
+ #define PKABigNumAddGetResult NOROM_PKABigNumAddGetResult
+ #undef PKABigNumSubStart
+ #define PKABigNumSubStart NOROM_PKABigNumSubStart
+ #undef PKABigNumSubGetResult
+ #define PKABigNumSubGetResult NOROM_PKABigNumSubGetResult
+ #undef PKAEccMultiplyStart
+ #define PKAEccMultiplyStart NOROM_PKAEccMultiplyStart
+ #undef PKAEccMontgomeryMultiplyStart
+ #define PKAEccMontgomeryMultiplyStart NOROM_PKAEccMontgomeryMultiplyStart
+ #undef PKAEccMultiplyGetResult
+ #define PKAEccMultiplyGetResult NOROM_PKAEccMultiplyGetResult
+ #undef PKAEccAddStart
+ #define PKAEccAddStart NOROM_PKAEccAddStart
+ #undef PKAEccAddGetResult
+ #define PKAEccAddGetResult NOROM_PKAEccAddGetResult
+ #undef PKAEccVerifyPublicKeyWeierstrassStart
+ #define PKAEccVerifyPublicKeyWeierstrassStart NOROM_PKAEccVerifyPublicKeyWeierstrassStart
+#endif
+
+//*****************************************************************************
+//
+// Handle support for DriverLib in ROM:
+// This section will undo prototype renaming made in the header file
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #undef PKAClearPkaRam
+ #define PKAClearPkaRam NOROM_PKAClearPkaRam
+ #undef PKAGetOpsStatus
+ #define PKAGetOpsStatus NOROM_PKAGetOpsStatus
+ #undef PKAArrayAllZeros
+ #define PKAArrayAllZeros NOROM_PKAArrayAllZeros
+ #undef PKAZeroOutArray
+ #define PKAZeroOutArray NOROM_PKAZeroOutArray
+ #undef PKABigNumModStart
+ #define PKABigNumModStart NOROM_PKABigNumModStart
+ #undef PKABigNumModGetResult
+ #define PKABigNumModGetResult NOROM_PKABigNumModGetResult
+ #undef PKABigNumDivideStart
+ #define PKABigNumDivideStart NOROM_PKABigNumDivideStart
+ #undef PKABigNumDivideGetQuotient
+ #define PKABigNumDivideGetQuotient NOROM_PKABigNumDivideGetQuotient
+ #undef PKABigNumDivideGetRemainder
+ #define PKABigNumDivideGetRemainder NOROM_PKABigNumDivideGetRemainder
+ #undef PKABigNumCmpStart
+ #define PKABigNumCmpStart NOROM_PKABigNumCmpStart
+ #undef PKABigNumCmpGetResult
+ #define PKABigNumCmpGetResult NOROM_PKABigNumCmpGetResult
+ #undef PKABigNumInvModStart
+ #define PKABigNumInvModStart NOROM_PKABigNumInvModStart
+ #undef PKABigNumInvModGetResult
+ #define PKABigNumInvModGetResult NOROM_PKABigNumInvModGetResult
+ #undef PKABigNumMultiplyStart
+ #define PKABigNumMultiplyStart NOROM_PKABigNumMultiplyStart
+ #undef PKABigNumMultGetResult
+ #define PKABigNumMultGetResult NOROM_PKABigNumMultGetResult
+ #undef PKABigNumAddStart
+ #define PKABigNumAddStart NOROM_PKABigNumAddStart
+ #undef PKABigNumAddGetResult
+ #define PKABigNumAddGetResult NOROM_PKABigNumAddGetResult
+ #undef PKABigNumSubStart
+ #define PKABigNumSubStart NOROM_PKABigNumSubStart
+ #undef PKABigNumSubGetResult
+ #define PKABigNumSubGetResult NOROM_PKABigNumSubGetResult
+ #undef PKAEccMultiplyStart
+ #define PKAEccMultiplyStart NOROM_PKAEccMultiplyStart
+ #undef PKAEccMontgomeryMultiplyStart
+ #define PKAEccMontgomeryMultiplyStart NOROM_PKAEccMontgomeryMultiplyStart
+ #undef PKAEccMultiplyGetResult
+ #define PKAEccMultiplyGetResult NOROM_PKAEccMultiplyGetResult
+ #undef PKAEccAddStart
+ #define PKAEccAddStart NOROM_PKAEccAddStart
+ #undef PKAEccAddGetResult
+ #define PKAEccAddGetResult NOROM_PKAEccAddGetResult
+ #undef PKAEccVerifyPublicKeyWeierstrassStart
+ #define PKAEccVerifyPublicKeyWeierstrassStart NOROM_PKAEccVerifyPublicKeyWeierstrassStart
+#endif
+
+
+
+#define MAX(x,y) (((x) > (y)) ? (x) : (y))
+#define MIN(x,y) (((x) < (y)) ? (x) : (y))
+#define INRANGE(x,y,z) ((x) > (y) && (x) < (z))
+
+
+//*****************************************************************************
+//
+// Define for the maximum curve size supported by the PKA module in 32 bit
+// word.
+// \note PKA hardware module can support up to 384 bit curve size due to the
+// 2K of PKA RAM.
+//
+//*****************************************************************************
+#define PKA_MAX_CURVE_SIZE_32_BIT_WORD 12
+
+//*****************************************************************************
+//
+// Define for the maximum length of the big number supported by the PKA module
+// in 32 bit word.
+//
+//*****************************************************************************
+#define PKA_MAX_LEN_IN_32_BIT_WORD PKA_MAX_CURVE_SIZE_32_BIT_WORD
+
+//*****************************************************************************
+//
+// Used in PKAWritePkaParam() and PKAWritePkaParamExtraOffset() to specify that
+// the base address of the parameter should not be written to a NPTR register.
+//
+//*****************************************************************************
+#define PKA_NO_POINTER_REG 0xFF
+
+//*****************************************************************************
+//
+// NIST P224 constants in little endian format. byte[0] is the least
+// significant byte and byte[NISTP224_PARAM_SIZE_BYTES - 1] is the most
+// significant.
+//
+//*****************************************************************************
+const PKA_EccPoint224 NISTP224_generator = {
+ .x = {.byte = {0x21, 0x1D, 0x5C, 0x11, 0xD6, 0x80, 0x32, 0x34,
+ 0x22, 0x11, 0xC2, 0x56, 0xD3, 0xC1, 0x03, 0x4A,
+ 0xB9, 0x90, 0x13, 0x32, 0x7F, 0xBF, 0xB4, 0x6B,
+ 0xBD, 0x0C, 0x0E, 0xB7, }},
+ .y = {.byte = {0x34, 0x7E, 0x00, 0x85, 0x99, 0x81, 0xD5, 0x44,
+ 0x64, 0x47, 0x07, 0x5A, 0xA0, 0x75, 0x43, 0xCD,
+ 0xE6, 0xDF, 0x22, 0x4C, 0xFB, 0x23, 0xF7, 0xB5,
+ 0x88, 0x63, 0x37, 0xBD, }},
+};
+
+const PKA_EccParam224 NISTP224_prime = {.byte = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF}};
+
+const PKA_EccParam224 NISTP224_a = {.byte = {0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF}};
+
+const PKA_EccParam224 NISTP224_b = {.byte = {0xB4, 0xFF, 0x55, 0x23, 0x43, 0x39, 0x0B, 0x27,
+ 0xBA, 0xD8, 0xBF, 0xD7, 0xB7, 0xB0, 0x44, 0x50,
+ 0x56, 0x32, 0x41, 0xF5, 0xAB, 0xB3, 0x04, 0x0C,
+ 0x85, 0x0A, 0x05, 0xB4}};
+
+const PKA_EccParam224 NISTP224_order = {.byte = {0x3D, 0x2A, 0x5C, 0x5C, 0x45, 0x29, 0xDD, 0x13,
+ 0x3E, 0xF0, 0xB8, 0xE0, 0xA2, 0x16, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF}};
+
+//*****************************************************************************
+//
+// NIST P256 constants in little endian format. byte[0] is the least
+// significant byte and byte[NISTP256_PARAM_SIZE_BYTES - 1] is the most
+// significant.
+//
+//*****************************************************************************
+const PKA_EccPoint256 NISTP256_generator = {
+ .x = {.byte = {0x96, 0xc2, 0x98, 0xd8, 0x45, 0x39, 0xa1, 0xf4,
+ 0xa0, 0x33, 0xeb, 0x2d, 0x81, 0x7d, 0x03, 0x77,
+ 0xf2, 0x40, 0xa4, 0x63, 0xe5, 0xe6, 0xbc, 0xf8,
+ 0x47, 0x42, 0x2c, 0xe1, 0xf2, 0xd1, 0x17, 0x6b}},
+ .y = {.byte = {0xf5, 0x51, 0xbf, 0x37, 0x68, 0x40, 0xb6, 0xcb,
+ 0xce, 0x5e, 0x31, 0x6b, 0x57, 0x33, 0xce, 0x2b,
+ 0x16, 0x9e, 0x0f, 0x7c, 0x4a, 0xeb, 0xe7, 0x8e,
+ 0x9b, 0x7f, 0x1a, 0xfe, 0xe2, 0x42, 0xe3, 0x4f}},
+};
+
+const PKA_EccParam256 NISTP256_prime = {.byte = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff}};
+
+const PKA_EccParam256 NISTP256_a = {.byte = {0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff}};
+
+const PKA_EccParam256 NISTP256_b = {.byte = {0x4b, 0x60, 0xd2, 0x27, 0x3e, 0x3c, 0xce, 0x3b,
+ 0xf6, 0xb0, 0x53, 0xcc, 0xb0, 0x06, 0x1d, 0x65,
+ 0xbc, 0x86, 0x98, 0x76, 0x55, 0xbd, 0xeb, 0xb3,
+ 0xe7, 0x93, 0x3a, 0xaa, 0xd8, 0x35, 0xc6, 0x5a}};
+
+const PKA_EccParam256 NISTP256_order = {.byte = {0x51, 0x25, 0x63, 0xfc, 0xc2, 0xca, 0xb9, 0xf3,
+ 0x84, 0x9e, 0x17, 0xa7, 0xad, 0xfa, 0xe6, 0xbc,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff}};
+
+//*****************************************************************************
+//
+// NIST P384 constants in little endian format. byte[0] is the least
+// significant byte and byte[NISTP384_PARAM_SIZE_BYTES - 1] is the most
+// significant.
+//
+//*****************************************************************************
+const PKA_EccPoint384 NISTP384_generator = {
+ .x = {.byte = {0xb7, 0x0a, 0x76, 0x72, 0x38, 0x5e, 0x54, 0x3a,
+ 0x6c, 0x29, 0x55, 0xbf, 0x5d, 0xf2, 0x02, 0x55,
+ 0x38, 0x2a, 0x54, 0x82, 0xe0, 0x41, 0xf7, 0x59,
+ 0x98, 0x9b, 0xa7, 0x8b, 0x62, 0x3b, 0x1d, 0x6e,
+ 0x74, 0xad, 0x20, 0xf3, 0x1e, 0xc7, 0xb1, 0x8e,
+ 0x37, 0x05, 0x8b, 0xbe, 0x22, 0xca, 0x87, 0xaa}},
+ .y = {.byte = {0x5f, 0x0e, 0xea, 0x90, 0x7c, 0x1d, 0x43, 0x7a,
+ 0x9d, 0x81, 0x7e, 0x1d, 0xce, 0xb1, 0x60, 0x0a,
+ 0xc0, 0xb8, 0xf0, 0xb5, 0x13, 0x31, 0xda, 0xe9,
+ 0x7c, 0x14, 0x9a, 0x28, 0xbd, 0x1d, 0xf4, 0xf8,
+ 0x29, 0xdc, 0x92, 0x92, 0xbf, 0x98, 0x9e, 0x5d,
+ 0x6f, 0x2c, 0x26, 0x96, 0x4a, 0xde, 0x17, 0x36,}},
+};
+
+const PKA_EccParam384 NISTP384_prime = {.byte = {0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+ 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
+
+const PKA_EccParam384 NISTP384_a = {.byte = {0xfc, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+ 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
+
+const PKA_EccParam384 NISTP384_b = {.byte = {0xef, 0x2a, 0xec, 0xd3, 0xed, 0xc8, 0x85, 0x2a,
+ 0x9d, 0xd1, 0x2e, 0x8a, 0x8d, 0x39, 0x56, 0xc6,
+ 0x5a, 0x87, 0x13, 0x50, 0x8f, 0x08, 0x14, 0x03,
+ 0x12, 0x41, 0x81, 0xfe, 0x6e, 0x9c, 0x1d, 0x18,
+ 0x19, 0x2d, 0xf8, 0xe3, 0x6b, 0x05, 0x8e, 0x98,
+ 0xe4, 0xe7, 0x3e, 0xe2, 0xa7, 0x2f, 0x31, 0xb3}};
+
+const PKA_EccParam384 NISTP384_order = {.byte = {0x73, 0x29, 0xc5, 0xcc, 0x6a, 0x19, 0xec, 0xec,
+ 0x7a, 0xa7, 0xb0, 0x48, 0xb2, 0x0d, 0x1a, 0x58,
+ 0xdf, 0x2d, 0x37, 0xf4, 0x81, 0x4d, 0x63, 0xc7,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
+
+
+//*****************************************************************************
+//
+// NIST P521 constants in little endian format. byte[0] is the least
+// significant byte and byte[NISTP521_PARAM_SIZE_BYTES - 1] is the most
+// significant.
+//
+//*****************************************************************************
+const PKA_EccPoint521 NISTP521_generator = {
+ .x = {.byte = {0x66, 0xbd, 0xe5, 0xc2, 0x31, 0x7e, 0x7e, 0xf9,
+ 0x9b, 0x42, 0x6a, 0x85, 0xc1, 0xb3, 0x48, 0x33,
+ 0xde, 0xa8, 0xff, 0xa2, 0x27, 0xc1, 0x1d, 0xfe,
+ 0x28, 0x59, 0xe7, 0xef, 0x77, 0x5e, 0x4b, 0xa1,
+ 0xba, 0x3d, 0x4d, 0x6b, 0x60, 0xaf, 0x28, 0xf8,
+ 0x21, 0xb5, 0x3f, 0x05, 0x39, 0x81, 0x64, 0x9c,
+ 0x42, 0xb4, 0x95, 0x23, 0x66, 0xcb, 0x3e, 0x9e,
+ 0xcd, 0xe9, 0x04, 0x04, 0xb7, 0x06, 0x8e, 0x85,
+ 0xc6, 0x00}},
+ .y = {.byte = {0x50, 0x66, 0xd1, 0x9f, 0x76, 0x94, 0xbe, 0x88,
+ 0x40, 0xc2, 0x72, 0xa2, 0x86, 0x70, 0x3c, 0x35,
+ 0x61, 0x07, 0xad, 0x3f, 0x01, 0xb9, 0x50, 0xc5,
+ 0x40, 0x26, 0xf4, 0x5e, 0x99, 0x72, 0xee, 0x97,
+ 0x2c, 0x66, 0x3e, 0x27, 0x17, 0xbd, 0xaf, 0x17,
+ 0x68, 0x44, 0x9b, 0x57, 0x49, 0x44, 0xf5, 0x98,
+ 0xd9, 0x1b, 0x7d, 0x2c, 0xb4, 0x5f, 0x8a, 0x5c,
+ 0x04, 0xc0, 0x3b, 0x9a, 0x78, 0x6a, 0x29, 0x39,
+ 0x18, 0x01}},
+};
+
+const PKA_EccParam521 NISTP521_prime = {.byte = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0x01}};
+
+const PKA_EccParam521 NISTP521_a = {.byte = {0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0x01}};
+
+const PKA_EccParam521 NISTP521_b = {.byte = {0x00, 0x3f, 0x50, 0x6b, 0xd4, 0x1f, 0x45, 0xef,
+ 0xf1, 0x34, 0x2c, 0x3d, 0x88, 0xdf, 0x73, 0x35,
+ 0x07, 0xbf, 0xb1, 0x3b, 0xbd, 0xc0, 0x52, 0x16,
+ 0x7b, 0x93, 0x7e, 0xec, 0x51, 0x39, 0x19, 0x56,
+ 0xe1, 0x09, 0xf1, 0x8e, 0x91, 0x89, 0xb4, 0xb8,
+ 0xf3, 0x15, 0xb3, 0x99, 0x5b, 0x72, 0xda, 0xa2,
+ 0xee, 0x40, 0x85, 0xb6, 0xa0, 0x21, 0x9a, 0x92,
+ 0x1f, 0x9a, 0x1c, 0x8e, 0x61, 0xb9, 0x3e, 0x95,
+ 0x51, 0x00}};
+
+const PKA_EccParam521 NISTP521_order = {.byte = {0x09, 0x64, 0x38, 0x91, 0x1e, 0xb7, 0x6f, 0xbb,
+ 0xae, 0x47, 0x9c, 0x89, 0xb8, 0xc9, 0xb5, 0x3b,
+ 0xd0, 0xa5, 0x09, 0xf7, 0x48, 0x01, 0xcc, 0x7f,
+ 0x6b, 0x96, 0x2f, 0xbf, 0x83, 0x87, 0x86, 0x51,
+ 0xfa, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0x01}};
+
+
+//*****************************************************************************
+//
+// Brainpool P256r1 constants in little endian format. byte[0] is the least
+// significant byte and byte[BrainpoolP256R1_PARAM_SIZE_BYTES - 1] is the most
+// significant.
+//
+//*****************************************************************************
+const PKA_EccPoint256 BrainpoolP256R1_generator = {
+ .x = {.byte = {0x62, 0x32, 0xCE, 0x9A, 0xBD, 0x53, 0x44, 0x3A,
+ 0xC2, 0x23, 0xBD, 0xE3, 0xE1, 0x27, 0xDE, 0xB9,
+ 0xAF, 0xB7, 0x81, 0xFC, 0x2F, 0x48, 0x4B, 0x2C,
+ 0xCB, 0x57, 0x7E, 0xCB, 0xB9, 0xAE, 0xD2, 0x8B}},
+ .y = {.byte = {0x97, 0x69, 0x04, 0x2F, 0xC7, 0x54, 0x1D, 0x5C,
+ 0x54, 0x8E, 0xED, 0x2D, 0x13, 0x45, 0x77, 0xC2,
+ 0xC9, 0x1D, 0x61, 0x14, 0x1A, 0x46, 0xF8, 0x97,
+ 0xFD, 0xC4, 0xDA, 0xC3, 0x35, 0xF8, 0x7E, 0x54}},
+};
+
+const PKA_EccParam256 BrainpoolP256R1_prime = {.byte = {0x77, 0x53, 0x6E, 0x1F, 0x1D, 0x48, 0x13, 0x20,
+ 0x28, 0x20, 0x26, 0xD5, 0x23, 0xF6, 0x3B, 0x6E,
+ 0x72, 0x8D, 0x83, 0x9D, 0x90, 0x0A, 0x66, 0x3E,
+ 0xBC, 0xA9, 0xEE, 0xA1, 0xDB, 0x57, 0xFB, 0xA9}};
+
+const PKA_EccParam256 BrainpoolP256R1_a = {.byte = {0xD9, 0xB5, 0x30, 0xF3, 0x44, 0x4B, 0x4A, 0xE9,
+ 0x6C, 0x5C, 0xDC, 0x26, 0xC1, 0x55, 0x80, 0xFB,
+ 0xE7, 0xFF, 0x7A, 0x41, 0x30, 0x75, 0xF6, 0xEE,
+ 0x57, 0x30, 0x2C, 0xFC, 0x75, 0x09, 0x5A, 0x7D}};
+
+const PKA_EccParam256 BrainpoolP256R1_b = {.byte = {0xB6, 0x07, 0x8C, 0xFF, 0x18, 0xDC, 0xCC, 0x6B,
+ 0xCE, 0xE1, 0xF7, 0x5C, 0x29, 0x16, 0x84, 0x95,
+ 0xBF, 0x7C, 0xD7, 0xBB, 0xD9, 0xB5, 0x30, 0xF3,
+ 0x44, 0x4B, 0x4A, 0xE9, 0x6C, 0x5C, 0xDC, 0x26,}};
+
+const PKA_EccParam256 BrainpoolP256R1_order = {.byte = {0xA7, 0x56, 0x48, 0x97, 0x82, 0x0E, 0x1E, 0x90,
+ 0xF7, 0xA6, 0x61, 0xB5, 0xA3, 0x7A, 0x39, 0x8C,
+ 0x71, 0x8D, 0x83, 0x9D, 0x90, 0x0A, 0x66, 0x3E,
+ 0xBC, 0xA9, 0xEE, 0xA1, 0xDB, 0x57, 0xFB, 0xA9}};
+
+//*****************************************************************************
+//
+// Brainpool P384r1 constants in little endian format. byte[0] is the least
+// significant byte and byte[BrainpoolP384R1_PARAM_SIZE_BYTES - 1] is the most
+// significant.
+//
+//*****************************************************************************
+const PKA_EccPoint384 BrainpoolP384R1_generator = {
+ .x = {.byte = {0x1E, 0xAF, 0xD4, 0x47, 0xE2, 0xB2, 0x87, 0xEF,
+ 0xAA, 0x46, 0xD6, 0x36, 0x34, 0xE0, 0x26, 0xE8,
+ 0xE8, 0x10, 0xBD, 0x0C, 0xFE, 0xCA, 0x7F, 0xDB,
+ 0xE3, 0x4F, 0xF1, 0x7E, 0xE7, 0xA3, 0x47, 0x88,
+ 0x6B, 0x3F, 0xC1, 0xB7, 0x81, 0x3A, 0xA6, 0xA2,
+ 0xFF, 0x45, 0xCF, 0x68, 0xF0, 0x64, 0x1C, 0x1D}},
+ .y = {.byte = {0x15, 0x53, 0x3C, 0x26, 0x41, 0x03, 0x82, 0x42,
+ 0x11, 0x81, 0x91, 0x77, 0x21, 0x46, 0x46, 0x0E,
+ 0x28, 0x29, 0x91, 0xF9, 0x4F, 0x05, 0x9C, 0xE1,
+ 0x64, 0x58, 0xEC, 0xFE, 0x29, 0x0B, 0xB7, 0x62,
+ 0x52, 0xD5, 0xCF, 0x95, 0x8E, 0xEB, 0xB1, 0x5C,
+ 0xA4, 0xC2, 0xF9, 0x20, 0x75, 0x1D, 0xBE, 0x8A}},
+};
+
+const PKA_EccParam384 BrainpoolP384R1_prime = {.byte = {0x53, 0xEC, 0x07, 0x31, 0x13, 0x00, 0x47, 0x87,
+ 0x71, 0x1A, 0x1D, 0x90, 0x29, 0xA7, 0xD3, 0xAC,
+ 0x23, 0x11, 0xB7, 0x7F, 0x19, 0xDA, 0xB1, 0x12,
+ 0xB4, 0x56, 0x54, 0xED, 0x09, 0x71, 0x2F, 0x15,
+ 0xDF, 0x41, 0xE6, 0x50, 0x7E, 0x6F, 0x5D, 0x0F,
+ 0x28, 0x6D, 0x38, 0xA3, 0x82, 0x1E, 0xB9, 0x8C}};
+
+const PKA_EccParam384 BrainpoolP384R1_a = {.byte = {0x26, 0x28, 0xCE, 0x22, 0xDD, 0xC7, 0xA8, 0x04,
+ 0xEB, 0xD4, 0x3A, 0x50, 0x4A, 0x81, 0xA5, 0x8A,
+ 0x0F, 0xF9, 0x91, 0xBA, 0xEF, 0x65, 0x91, 0x13,
+ 0x87, 0x27, 0xB2, 0x4F, 0x8E, 0xA2, 0xBE, 0xC2,
+ 0xA0, 0xAF, 0x05, 0xCE, 0x0A, 0x08, 0x72, 0x3C,
+ 0x0C, 0x15, 0x8C, 0x3D, 0xC6, 0x82, 0xC3, 0x7B}};
+
+const PKA_EccParam384 BrainpoolP384R1_b = {.byte = {0x11, 0x4C, 0x50, 0xFA, 0x96, 0x86, 0xB7, 0x3A,
+ 0x94, 0xC9, 0xDB, 0x95, 0x02, 0x39, 0xB4, 0x7C,
+ 0xD5, 0x62, 0xEB, 0x3E, 0xA5, 0x0E, 0x88, 0x2E,
+ 0xA6, 0xD2, 0xDC, 0x07, 0xE1, 0x7D, 0xB7, 0x2F,
+ 0x7C, 0x44, 0xF0, 0x16, 0x54, 0xB5, 0x39, 0x8B,
+ 0x26, 0x28, 0xCE, 0x22, 0xDD, 0xC7, 0xA8, 0x04}};
+
+const PKA_EccParam384 BrainpoolP384R1_order = {.byte = {0x65, 0x65, 0x04, 0xE9, 0x02, 0x32, 0x88, 0x3B,
+ 0x10, 0xC3, 0x7F, 0x6B, 0xAF, 0xB6, 0x3A, 0xCF,
+ 0xA7, 0x25, 0x04, 0xAC, 0x6C, 0x6E, 0x16, 0x1F,
+ 0xB3, 0x56, 0x54, 0xED, 0x09, 0x71, 0x2F, 0x15,
+ 0xDF, 0x41, 0xE6, 0x50, 0x7E, 0x6F, 0x5D, 0x0F,
+ 0x28, 0x6D, 0x38, 0xA3, 0x82, 0x1E, 0xB9, 0x8C}};
+
+//*****************************************************************************
+//
+// Brainpool P512r1 constants in little endian format. byte[0] is the least
+// significant byte and byte[BrainpoolP512R1_PARAM_SIZE_BYTES - 1] is the most
+// significant.
+//
+//*****************************************************************************
+const PKA_EccPoint512 BrainpoolP512R1_generator = {
+ .x = {.byte = {0x22, 0xF8, 0xB9, 0xBC, 0x09, 0x22, 0x35, 0x8B,
+ 0x68, 0x5E, 0x6A, 0x40, 0x47, 0x50, 0x6D, 0x7C,
+ 0x5F, 0x7D, 0xB9, 0x93, 0x7B, 0x68, 0xD1, 0x50,
+ 0x8D, 0xD4, 0xD0, 0xE2, 0x78, 0x1F, 0x3B, 0xFF,
+ 0x8E, 0x09, 0xD0, 0xF4, 0xEE, 0x62, 0x3B, 0xB4,
+ 0xC1, 0x16, 0xD9, 0xB5, 0x70, 0x9F, 0xED, 0x85,
+ 0x93, 0x6A, 0x4C, 0x9C, 0x2E, 0x32, 0x21, 0x5A,
+ 0x64, 0xD9, 0x2E, 0xD8, 0xBD, 0xE4, 0xAE, 0x81}},
+ .y = {.byte = {0x92, 0x08, 0xD8, 0x3A, 0x0F, 0x1E, 0xCD, 0x78,
+ 0x06, 0x54, 0xF0, 0xA8, 0x2F, 0x2B, 0xCA, 0xD1,
+ 0xAE, 0x63, 0x27, 0x8A, 0xD8, 0x4B, 0xCA, 0x5B,
+ 0x5E, 0x48, 0x5F, 0x4A, 0x49, 0xDE, 0xDC, 0xB2,
+ 0x11, 0x81, 0x1F, 0x88, 0x5B, 0xC5, 0x00, 0xA0,
+ 0x1A, 0x7B, 0xA5, 0x24, 0x00, 0xF7, 0x09, 0xF2,
+ 0xFD, 0x22, 0x78, 0xCF, 0xA9, 0xBF, 0xEA, 0xC0,
+ 0xEC, 0x32, 0x63, 0x56, 0x5D, 0x38, 0xDE, 0x7D}},
+};
+
+const PKA_EccParam512 BrainpoolP512R1_prime = {.byte = {0xF3, 0x48, 0x3A, 0x58, 0x56, 0x60, 0xAA, 0x28,
+ 0x85, 0xC6, 0x82, 0x2D, 0x2F, 0xFF, 0x81, 0x28,
+ 0xE6, 0x80, 0xA3, 0xE6, 0x2A, 0xA1, 0xCD, 0xAE,
+ 0x42, 0x68, 0xC6, 0x9B, 0x00, 0x9B, 0x4D, 0x7D,
+ 0x71, 0x08, 0x33, 0x70, 0xCA, 0x9C, 0x63, 0xD6,
+ 0x0E, 0xD2, 0xC9, 0xB3, 0xB3, 0x8D, 0x30, 0xCB,
+ 0x07, 0xFC, 0xC9, 0x33, 0xAE, 0xE6, 0xD4, 0x3F,
+ 0x8B, 0xC4, 0xE9, 0xDB, 0xB8, 0x9D, 0xDD, 0xAA}};
+
+const PKA_EccParam512 BrainpoolP512R1_a = {.byte = {0xCA, 0x94, 0xFC, 0x77, 0x4D, 0xAC, 0xC1, 0xE7,
+ 0xB9, 0xC7, 0xF2, 0x2B, 0xA7, 0x17, 0x11, 0x7F,
+ 0xB5, 0xC8, 0x9A, 0x8B, 0xC9, 0xF1, 0x2E, 0x0A,
+ 0xA1, 0x3A, 0x25, 0xA8, 0x5A, 0x5D, 0xED, 0x2D,
+ 0xBC, 0x63, 0x98, 0xEA, 0xCA, 0x41, 0x34, 0xA8,
+ 0x10, 0x16, 0xF9, 0x3D, 0x8D, 0xDD, 0xCB, 0x94,
+ 0xC5, 0x4C, 0x23, 0xAC, 0x45, 0x71, 0x32, 0xE2,
+ 0x89, 0x3B, 0x60, 0x8B, 0x31, 0xA3, 0x30, 0x78}};
+
+const PKA_EccParam512 BrainpoolP512R1_b = {.byte = {0x23, 0xF7, 0x16, 0x80, 0x63, 0xBD, 0x09, 0x28,
+ 0xDD, 0xE5, 0xBA, 0x5E, 0xB7, 0x50, 0x40, 0x98,
+ 0x67, 0x3E, 0x08, 0xDC, 0xCA, 0x94, 0xFC, 0x77,
+ 0x4D, 0xAC, 0xC1, 0xE7, 0xB9, 0xC7, 0xF2, 0x2B,
+ 0xA7, 0x17, 0x11, 0x7F, 0xB5, 0xC8, 0x9A, 0x8B,
+ 0xC9, 0xF1, 0x2E, 0x0A, 0xA1, 0x3A, 0x25, 0xA8,
+ 0x5A, 0x5D, 0xED, 0x2D, 0xBC, 0x63, 0x98, 0xEA,
+ 0xCA, 0x41, 0x34, 0xA8, 0x10, 0x16, 0xF9, 0x3D}};
+
+const PKA_EccParam512 BrainpoolP512R1_order = {.byte = {0x69, 0x00, 0xA9, 0x9C, 0x82, 0x96, 0x87, 0xB5,
+ 0xDD, 0xDA, 0x5D, 0x08, 0x81, 0xD3, 0xB1, 0x1D,
+ 0x47, 0x10, 0xAC, 0x7F, 0x19, 0x61, 0x86, 0x41,
+ 0x19, 0x26, 0xA9, 0x4C, 0x41, 0x5C, 0x3E, 0x55,
+ 0x70, 0x08, 0x33, 0x70, 0xCA, 0x9C, 0x63, 0xD6,
+ 0x0E, 0xD2, 0xC9, 0xB3, 0xB3, 0x8D, 0x30, 0xCB,
+ 0x07, 0xFC, 0xC9, 0x33, 0xAE, 0xE6, 0xD4, 0x3F,
+ 0x8B, 0xC4, 0xE9, 0xDB, 0xB8, 0x9D, 0xDD, 0xAA}};
+
+//*****************************************************************************
+//
+// Curve25519 constants in little endian format. byte[0] is the least
+// significant byte and byte[Curve25519_PARAM_SIZE_BYTES - 1] is the most
+// significant.
+//
+//*****************************************************************************
+const PKA_EccPoint256 Curve25519_generator = {
+ .x = {.byte = {0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,}},
+ .y = {.byte = {0xd9, 0xd3, 0xce, 0x7e, 0xa2, 0xc5, 0xe9, 0x29,
+ 0xb2, 0x61, 0x7c, 0x6d, 0x7e, 0x4d, 0x3d, 0x92,
+ 0x4c, 0xd1, 0x48, 0x77, 0x2c, 0xdd, 0x1e, 0xe0,
+ 0xb4, 0x86, 0xa0, 0xb8, 0xa1, 0x19, 0xae, 0x20}},
+};
+
+const PKA_EccParam256 Curve25519_prime = {.byte = {0xed, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f}};
+
+const PKA_EccParam256 Curve25519_a = {.byte = {0x06, 0x6d, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,}};
+
+const PKA_EccParam256 Curve25519_b = {.byte = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,}};
+
+const PKA_EccParam256 Curve25519_order = {.byte = {0xb9, 0xdc, 0xf5, 0x5c, 0x1a, 0x63, 0x12, 0x58,
+ 0xd6, 0x9c, 0xf7, 0xa2, 0xde, 0xf9, 0xde, 0x14,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,}};
+
+
+//*****************************************************************************
+//
+// Zeroize PKA RAM. Not threadsafe.
+//
+//*****************************************************************************
+void PKAClearPkaRam(void){
+ // Get initial state
+ uint32_t secdmaclkgr = HWREG(PRCM_BASE + PRCM_O_SECDMACLKGR);
+
+ // OR in zeroize bit
+ secdmaclkgr |= PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N;
+
+ // Start zeroization
+ HWREG(PRCM_BASE + PRCM_O_SECDMACLKGR) = secdmaclkgr;
+
+ // Wait 256 cycles for PKA RAM to be cleared
+ CPUdelay(256 / 4);
+
+ // Turn off zeroization
+ HWREG(PRCM_BASE + PRCM_O_SECDMACLKGR) = secdmaclkgr & (~PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N);
+}
+
+//*****************************************************************************
+//
+// Write a PKA parameter to the PKA module, set required registers, and add an offset.
+//
+//*****************************************************************************
+static uint32_t PKAWritePkaParam(const uint8_t *param, uint32_t paramLength, uint32_t paramOffset, uint32_t ptrRegOffset)
+{
+ uint32_t i;
+ uint32_t *paramWordAlias = (uint32_t *)param;
+ // Take the floor of paramLength in 32-bit words
+ uint32_t paramLengthInWords = paramLength / sizeof(uint32_t);
+
+ // Only copy data if it is specified. We may wish to simply allocate another buffer and get
+ // the required offset.
+ if (param) {
+ // Load the number in PKA RAM
+ for (i = 0; i < paramLengthInWords; i++) {
+ HWREG(PKA_RAM_BASE + paramOffset + sizeof(uint32_t) * i) = paramWordAlias[i];
+ }
+
+ // If the length is not a word-multiple, fill up a temporary word and copy that in
+ // to avoid a bus error. The extra zeros at the end should not matter, as the large
+ // number is little-endian and thus has no effect.
+ // We could have correctly calculated ceiling(paramLength / sizeof(uint32_t)) above.
+ // However, we would not have been able to zero-out the extra few most significant
+ // bytes of the most significant word. That would have resulted in doing maths operations
+ // on whatever follows param in RAM.
+ if (paramLength % sizeof(uint32_t)) {
+ uint32_t temp = 0;
+ uint8_t j;
+
+ // Load the entire word line of the param remainder
+ temp = paramWordAlias[i];
+
+ // Zero-out all bytes beyond the end of the param
+ for (j = paramLength % sizeof(uint32_t); j < sizeof(uint32_t); j++) {
+ ((uint8_t *)&temp)[j] = 0;
+ }
+
+ HWREG(PKA_RAM_BASE + paramOffset + sizeof(uint32_t) * i) = temp;
+
+ // Increment paramLengthInWords since we take the ceiling of length / sizeof(uint32_t)
+ paramLengthInWords++;
+ }
+ }
+
+ // Update the A, B, C, or D pointer with the offset address of the PKA RAM location
+ // where the number will be stored.
+ switch (ptrRegOffset) {
+ case PKA_O_APTR:
+ HWREG(PKA_BASE + PKA_O_APTR) = paramOffset >> 2;
+ HWREG(PKA_BASE + PKA_O_ALENGTH) = paramLengthInWords;
+ break;
+ case PKA_O_BPTR:
+ HWREG(PKA_BASE + PKA_O_BPTR) = paramOffset >> 2;
+ HWREG(PKA_BASE + PKA_O_BLENGTH) = paramLengthInWords;
+ break;
+ case PKA_O_CPTR:
+ HWREG(PKA_BASE + PKA_O_CPTR) = paramOffset >> 2;
+ break;
+ case PKA_O_DPTR:
+ HWREG(PKA_BASE + PKA_O_DPTR) = paramOffset >> 2;
+ break;
+ }
+
+ // Ensure 8-byte alignment of next parameter.
+ // Returns the offset for the next parameter.
+ return paramOffset + sizeof(uint32_t) * (paramLengthInWords + (paramLengthInWords % 2));
+}
+
+//*****************************************************************************
+//
+// Write a PKA parameter to the PKA module but return a larger offset.
+//
+//*****************************************************************************
+static uint32_t PKAWritePkaParamExtraOffset(const uint8_t *param, uint32_t paramLength, uint32_t paramOffset, uint32_t ptrRegOffset)
+{
+ // Ensure 16-byte alignment.
+ return (sizeof(uint32_t) * 2) + PKAWritePkaParam(param, paramLength, paramOffset, ptrRegOffset);
+}
+
+//*****************************************************************************
+//
+// Writes the result of a large number arithmetic operation to a provided buffer.
+//
+//*****************************************************************************
+static uint32_t PKAGetBigNumResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr)
+{
+ uint32_t mswOffset;
+ uint32_t lswOffset;
+ uint32_t lengthInWords;
+ uint32_t i;
+ uint32_t *resultWordAlias = (uint32_t *)resultBuf;
+
+ // Check the arguments.
+ ASSERT(resultBuf);
+ ASSERT((resultPKAMemAddr > PKA_RAM_BASE) &&
+ (resultPKAMemAddr < (PKA_RAM_BASE + PKA_RAM_TOT_BYTE_SIZE)));
+
+ // Verify that the operation is complete.
+ if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) {
+ return PKA_STATUS_OPERATION_BUSY;
+ }
+
+ // Get the MSW register value.
+ mswOffset = HWREG(PKA_BASE + PKA_O_MSW);
+
+ // If the result vector is zero, write back one zero byte so the caller does not need
+ // to handle a special error for the perhaps valid result of zero.
+ // They will only get the error status if they do not provide a buffer
+ if (mswOffset & PKA_MSW_RESULT_IS_ZERO_M) {
+ if (*resultLength){
+ if(resultBuf){
+ resultBuf[0] = 0;
+ }
+
+ *resultLength = 1;
+
+ return PKA_STATUS_SUCCESS;
+ }
+ else {
+ return PKA_STATUS_BUF_UNDERFLOW;
+ }
+ }
+
+ // Get the length of the result
+ mswOffset = ((mswOffset & PKA_MSW_MSW_ADDRESS_M) + 1);
+ lswOffset = ((resultPKAMemAddr - PKA_RAM_BASE) >> 2);
+
+ if (mswOffset >= lswOffset) {
+ lengthInWords = mswOffset - lswOffset;
+ }
+ else {
+ return PKA_STATUS_RESULT_ADDRESS_INCORRECT;
+ }
+
+ // Check if the provided buffer length is adequate to store the result data.
+ if (*resultLength < lengthInWords * sizeof(uint32_t)) {
+ return PKA_STATUS_BUF_UNDERFLOW;
+ }
+
+ // Copy the resultant length.
+ *resultLength = lengthInWords * sizeof(uint32_t);
+
+
+ if (resultBuf) {
+ // Copy the result into the resultBuf.
+ for (i = 0; i < lengthInWords; i++) {
+ resultWordAlias[i]= HWREG(resultPKAMemAddr + sizeof(uint32_t) * i);
+ }
+ }
+
+ return PKA_STATUS_SUCCESS;
+}
+
+//*****************************************************************************
+//
+// Retrieve the result of a modulo operation or the remainder of a division.
+//
+//*****************************************************************************
+static uint32_t PKAGetBigNumResultRemainder(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr)
+{
+ uint32_t regMSWVal;
+ uint32_t lengthInWords;
+ uint32_t i;
+ uint32_t *resultWordAlias = (uint32_t *)resultBuf;
+
+ // Check the arguments.
+ ASSERT(resultBuf);
+ ASSERT((resultPKAMemAddr > PKA_RAM_BASE) &&
+ (resultPKAMemAddr < (PKA_RAM_BASE + PKA_RAM_TOT_BYTE_SIZE)));
+
+ // Verify that the operation is complete.
+ if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) {
+ return PKA_STATUS_OPERATION_BUSY;
+ }
+
+ // Get the MSW register value.
+ regMSWVal = HWREG(PKA_BASE + PKA_O_DIVMSW);
+
+ // If the result vector is zero, write back one zero byte so the caller does not need
+ // to handle a special error for the perhaps valid result of zero.
+ // They will only get the error status if they do not provide a buffer
+ if (regMSWVal & PKA_DIVMSW_RESULT_IS_ZERO_M) {
+ if (*resultLength){
+ if(resultBuf){
+ resultBuf[0] = 0;
+ }
+
+ *resultLength = 1;
+
+ return PKA_STATUS_SUCCESS;
+ }
+ else {
+ return PKA_STATUS_BUF_UNDERFLOW;
+ }
+ }
+
+ // Get the length of the result
+ lengthInWords = ((regMSWVal & PKA_DIVMSW_MSW_ADDRESS_M) + 1) - ((resultPKAMemAddr - PKA_RAM_BASE) >> 2);
+
+ // Check if the provided buffer length is adequate to store the result data.
+ if (*resultLength < lengthInWords * sizeof(uint32_t)) {
+ return PKA_STATUS_BUF_UNDERFLOW;
+ }
+
+ // Copy the resultant length.
+ *resultLength = lengthInWords * sizeof(uint32_t);
+
+ if (resultBuf) {
+ // Copy the result into the resultBuf.
+ for (i = 0; i < lengthInWords; i++) {
+ resultWordAlias[i] = HWREG(resultPKAMemAddr + sizeof(uint32_t) * i);
+ }
+ }
+
+ return PKA_STATUS_SUCCESS;
+}
+
+//*****************************************************************************
+//
+// Writes the resultant curve point of an ECC operation to the provided buffer.
+//
+//*****************************************************************************
+static uint32_t PKAGetECCResult(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length)
+{
+ uint32_t i = 0;
+ uint32_t *xWordAlias = (uint32_t *)curvePointX;
+ uint32_t *yWordAlias = (uint32_t *)curvePointY;
+ uint32_t lengthInWordsCeiling = 0;
+
+ // Check for the arguments.
+ ASSERT(curvePointX);
+ ASSERT(curvePointY);
+ ASSERT((resultPKAMemAddr > PKA_RAM_BASE) &&
+ (resultPKAMemAddr < (PKA_RAM_BASE + PKA_RAM_TOT_BYTE_SIZE)));
+
+ // Verify that the operation is completed.
+ if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) {
+ return PKA_STATUS_OPERATION_BUSY;
+ }
+
+ if (HWREG(PKA_BASE + PKA_O_SHIFT)) {
+ return PKA_STATUS_FAILURE;
+ }
+
+ // Check to make sure that the result vector is not the point at infinity.
+ if (HWREG(PKA_BASE + PKA_O_MSW) & PKA_MSW_RESULT_IS_ZERO) {
+ return PKA_STATUS_POINT_AT_INFINITY;
+ }
+
+ if (curvePointX != NULL) {
+ // Copy the x co-ordinate value of the result from vector D into
+ // the curvePoint.
+ for (i = 0; i < (length / sizeof(uint32_t)); i++) {
+ xWordAlias[i] = HWREG(resultPKAMemAddr + sizeof(uint32_t) * i);
+ }
+
+ // If the length is not a word-multiple, fill up a temporary word and copy that in
+ // to avoid a bus error.
+ if (length % sizeof(uint32_t)) {
+ uint32_t temp = 0;
+ uint8_t j;
+
+ // Load the entire word line of the coordinate remainder
+ temp = HWREG(resultPKAMemAddr + sizeof(uint32_t) * i);
+
+ // Write all remaining bytes to the coordinate
+ for (j = 0; j < length % sizeof(uint32_t); j++) {
+ curvePointX[i * sizeof(uint32_t) + j] = ((uint8_t *)&temp)[j];
+ }
+
+ }
+ }
+
+ lengthInWordsCeiling = (length % sizeof(uint32_t)) ? length / sizeof(uint32_t) + 1 : length / sizeof(uint32_t);
+
+ resultPKAMemAddr += sizeof(uint32_t) * (2 + lengthInWordsCeiling + (lengthInWordsCeiling % 2));
+
+ if (curvePointY != NULL) {
+ // Copy the y co-ordinate value of the result from vector D into
+ // the curvePoint.
+ for (i = 0; i < (length / sizeof(uint32_t)); i++) {
+ yWordAlias[i] = HWREG(resultPKAMemAddr + sizeof(uint32_t) * i);
+ }
+
+ // If the length is not a word-multiple, fill up a temporary word and copy that in
+ // to avoid a bus error.
+ if (length % sizeof(uint32_t)) {
+ uint32_t temp = 0;
+ uint8_t j;
+
+ // Load the entire word line of the coordinate remainder
+ temp = HWREG(resultPKAMemAddr + sizeof(uint32_t) * i);
+
+ // Write all remaining bytes to the coordinate
+ for (j = 0; j < length % sizeof(uint32_t); j++) {
+ curvePointY[i * sizeof(uint32_t) + j] = ((uint8_t *)&temp)[j];
+ }
+ }
+ }
+
+
+ return PKA_STATUS_SUCCESS;
+}
+
+
+//*****************************************************************************
+//
+// Provides the PKA operation status.
+//
+//*****************************************************************************
+uint32_t PKAGetOpsStatus(void)
+{
+ if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN_M) {
+ return PKA_STATUS_OPERATION_BUSY;
+ }
+ else {
+ return PKA_STATUS_OPERATION_RDY;
+ }
+}
+
+//*****************************************************************************
+//
+// Check if an array consists only of zeros.
+//
+//*****************************************************************************
+bool PKAArrayAllZeros(const uint8_t *array, uint32_t arrayLength)
+{
+ uint32_t i;
+ uint8_t arrayBits = 0;
+
+ // We could speed things up by comparing word-wise rather than byte-wise.
+ // However, this extra overhead is inconsequential compared to running an
+ // actual PKA operation. Especially ECC operations.
+ for (i = 0; i < arrayLength; i++) {
+ arrayBits |= array[i];
+ }
+
+ if (arrayBits) {
+ return false;
+ }
+ else {
+ return true;
+ }
+
+}
+
+//*****************************************************************************
+//
+// Fill an array with zeros
+//
+//*****************************************************************************
+void PKAZeroOutArray(const uint8_t *array, uint32_t arrayLength)
+{
+ uint32_t i;
+ // Take the floor of paramLength in 32-bit words
+ uint32_t arrayLengthInWords = arrayLength / sizeof(uint32_t);
+
+ // Zero-out the array word-wise until i >= arrayLength
+ for (i = 0; i < arrayLengthInWords * sizeof(uint32_t); i += 4) {
+ HWREG(array + i) = 0;
+ }
+
+ // If i != arrayLength, there are some remaining bytes to zero-out
+ if (arrayLength % sizeof(uint32_t)) {
+ // Subtract 4 from i, since i has already overshot the array
+ for (i -= 4; i < arrayLength; i++) {
+ HWREGB(array + i * sizeof(uint32_t));
+ }
+ }
+}
+
+//*****************************************************************************
+//
+// Start the big number modulus operation.
+//
+//*****************************************************************************
+uint32_t PKABigNumModStart(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr)
+{
+ uint32_t offset = 0;
+
+ // Check the arguments.
+ ASSERT(bigNum);
+ ASSERT(modulus);
+ ASSERT(resultPKAMemAddr);
+
+ // Make sure no operation is in progress.
+ if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) {
+ return PKA_STATUS_OPERATION_BUSY;
+ }
+
+ offset = PKAWritePkaParam(bigNum, bigNumLength, offset, PKA_O_APTR);
+
+ offset = PKAWritePkaParamExtraOffset(modulus, modulusLength, offset, PKA_O_BPTR);
+
+ // Copy the result vector address location.
+ *resultPKAMemAddr = PKA_RAM_BASE + offset;
+
+ // Load C pointer with the result location in PKA RAM
+ HWREG(PKA_BASE + PKA_O_CPTR) = offset >> 2;
+
+ // Start the PKCP modulo operation by setting the PKA Function register.
+ HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_MODULO);
+
+ return PKA_STATUS_SUCCESS;
+}
+
+//*****************************************************************************
+//
+// Get the result of the big number modulus operation.
+//
+//*****************************************************************************
+uint32_t PKABigNumModGetResult(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr)
+{
+ // Zero-out array in case modulo result is shorter than length
+ PKAZeroOutArray(resultBuf, length);
+
+ return PKAGetBigNumResultRemainder(resultBuf, &length, resultPKAMemAddr);
+}
+
+//*****************************************************************************
+//
+// Start the big number divide operation.
+//
+//*****************************************************************************
+uint32_t PKABigNumDivideStart(const uint8_t *dividend, uint32_t dividendLength, const uint8_t *divisor, uint32_t divisorLength, uint32_t *resultQuotientMemAddr, uint32_t *resultRemainderMemAddr)
+{
+ uint32_t offset = 0;
+
+ // Check the arguments.
+ ASSERT(dividend);
+ ASSERT(divisor);
+ ASSERT(resultQuotientMemAddr);
+ ASSERT(resultRemainderMemAddr);
+
+ // Make sure no operation is in progress.
+ if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) {
+ return PKA_STATUS_OPERATION_BUSY;
+ }
+
+ offset = PKAWritePkaParam(dividend, dividendLength, offset, PKA_O_APTR);
+
+ offset = PKAWritePkaParamExtraOffset(divisor, divisorLength, offset, PKA_O_BPTR);
+
+ // Copy the remainder result vector address location.
+ if (resultRemainderMemAddr) {
+ *resultRemainderMemAddr = PKA_RAM_BASE + offset;
+ }
+
+ // The remainder cannot ever be larger than the divisor. It should fit inside
+ // a buffer of that size.
+ offset = PKAWritePkaParamExtraOffset(0, divisorLength, offset, PKA_O_CPTR);
+
+ // Copy the remainder result vector address location.
+ if (resultQuotientMemAddr) {
+ *resultQuotientMemAddr = PKA_RAM_BASE + offset;
+ }
+
+ // Load D pointer with the quotient location in PKA RAM
+ HWREG(PKA_BASE + PKA_O_DPTR) = offset >> 2;
+
+ // Start the PKCP modulo operation by setting the PKA Function register.
+ HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_DIVIDE);
+
+ return PKA_STATUS_SUCCESS;
+}
+
+//*****************************************************************************
+//
+// Get the quotient of the big number divide operation.
+//
+//*****************************************************************************
+uint32_t PKABigNumDivideGetQuotient(uint8_t *resultBuf, uint32_t *length, uint32_t resultQuotientMemAddr)
+{
+ return PKAGetBigNumResult(resultBuf, length, resultQuotientMemAddr);
+}
+
+//*****************************************************************************
+//
+// Get the remainder of the big number divide operation.
+//
+//*****************************************************************************
+uint32_t PKABigNumDivideGetRemainder(uint8_t *resultBuf, uint32_t *length, uint32_t resultQuotientMemAddr)
+{
+ return PKAGetBigNumResultRemainder(resultBuf, length, resultQuotientMemAddr);
+}
+
+
+//*****************************************************************************
+//
+// Start the comparison of two big numbers.
+//
+//*****************************************************************************
+uint32_t PKABigNumCmpStart(const uint8_t *bigNum1, const uint8_t *bigNum2, uint32_t length)
+{
+ uint32_t offset = 0;
+
+ // Check the arguments.
+ ASSERT(bigNum1);
+ ASSERT(bigNum2);
+
+ // Make sure no operation is in progress.
+ if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) {
+ return PKA_STATUS_OPERATION_BUSY;
+ }
+
+ offset = PKAWritePkaParam(bigNum1, length, offset, PKA_O_APTR);
+
+ offset = PKAWritePkaParam(bigNum2, length, offset, PKA_O_BPTR);
+
+ // Set the PKA Function register for the Compare operation
+ // and start the operation.
+ HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_COMPARE);
+
+ return PKA_STATUS_SUCCESS;
+}
+
+//*****************************************************************************
+//
+// Get the result of the comparison operation of two big numbers.
+//
+//*****************************************************************************
+uint32_t PKABigNumCmpGetResult(void)
+{
+ uint32_t status;
+
+ // verify that the operation is complete.
+ if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) {
+ return PKA_STATUS_OPERATION_BUSY;
+ }
+
+ // Check the COMPARE register.
+ switch(HWREG(PKA_BASE + PKA_O_COMPARE)) {
+ case PKA_COMPARE_A_EQUALS_B:
+ status = PKA_STATUS_EQUAL;
+ break;
+
+ case PKA_COMPARE_A_GREATER_THAN_B:
+ status = PKA_STATUS_A_GREATER_THAN_B;
+ break;
+
+ case PKA_COMPARE_A_LESS_THAN_B:
+ status = PKA_STATUS_A_LESS_THAN_B;
+ break;
+
+ default:
+ status = PKA_STATUS_FAILURE;
+ break;
+ }
+
+ return status;
+}
+
+//*****************************************************************************
+//
+// Start the big number inverse modulo operation.
+//
+//*****************************************************************************
+uint32_t PKABigNumInvModStart(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr)
+{
+ uint32_t offset = 0;
+
+ // Check the arguments.
+ ASSERT(bigNum);
+ ASSERT(modulus);
+ ASSERT(resultPKAMemAddr);
+
+ // Make sure no operation is in progress.
+ if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) {
+ return PKA_STATUS_OPERATION_BUSY;
+ }
+
+ offset = PKAWritePkaParam(bigNum, bigNumLength, offset, PKA_O_APTR);
+
+ offset = PKAWritePkaParam(modulus, modulusLength, offset, PKA_O_BPTR);
+
+ // Copy the result vector address location.
+ *resultPKAMemAddr = PKA_RAM_BASE + offset;
+
+ // Load D pointer with the result location in PKA RAM.
+ HWREG(PKA_BASE + PKA_O_DPTR) = offset >> 2;
+
+ // set the PKA function to InvMod operation and the start the operation.
+ HWREG(PKA_BASE + PKA_O_FUNCTION) = 0x0000F000;
+
+ return PKA_STATUS_SUCCESS;
+}
+
+//*****************************************************************************
+//
+// Get the result of the big number inverse modulo operation.
+//
+//*****************************************************************************
+uint32_t PKABigNumInvModGetResult(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr)
+{
+ // Zero-out array in case modulo result is shorter than length
+ PKAZeroOutArray(resultBuf, length);
+
+ return PKAGetBigNumResult(resultBuf, &length, resultPKAMemAddr);
+}
+
+//*****************************************************************************
+//
+// Start the big number multiplication.
+//
+//*****************************************************************************
+uint32_t PKABigNumMultiplyStart(const uint8_t *multiplicand, uint32_t multiplicandLength, const uint8_t *multiplier, uint32_t multiplierLength, uint32_t *resultPKAMemAddr)
+{
+ uint32_t offset = 0;
+
+ // Check for the arguments.
+ ASSERT(multiplicand);
+ ASSERT(multiplier);
+ ASSERT(resultPKAMemAddr);
+
+ // Make sure no operation is in progress.
+ if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) {
+ return PKA_STATUS_OPERATION_BUSY;
+ }
+
+ offset = PKAWritePkaParam(multiplicand, multiplicandLength, offset, PKA_O_APTR);
+
+ offset = PKAWritePkaParam(multiplier, multiplierLength, offset, PKA_O_BPTR);
+
+
+ // Copy the result vector address location.
+ *resultPKAMemAddr = PKA_RAM_BASE + offset;
+
+ // Load C pointer with the result location in PKA RAM.
+ HWREG(PKA_BASE + PKA_O_CPTR) = offset >> 2;
+
+ // Set the PKA function to the multiplication and start it.
+ HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_MULTIPLY);
+
+ return PKA_STATUS_SUCCESS;
+}
+
+//*****************************************************************************
+//
+// Get the results of the big number multiplication.
+//
+//*****************************************************************************
+uint32_t PKABigNumMultGetResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr)
+{
+ return PKAGetBigNumResult(resultBuf, resultLength, resultPKAMemAddr);
+}
+
+//*****************************************************************************
+//
+// Start the addition of two big number.
+//
+//*****************************************************************************
+uint32_t PKABigNumAddStart(const uint8_t *bigNum1, uint32_t bigNum1Length, const uint8_t *bigNum2, uint32_t bigNum2Length, uint32_t *resultPKAMemAddr)
+{
+ uint32_t offset = 0;
+
+ // Check for arguments.
+ ASSERT(bigNum1);
+ ASSERT(bigNum2);
+ ASSERT(resultPKAMemAddr);
+
+ // Make sure no operation is in progress.
+ if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) {
+ return PKA_STATUS_OPERATION_BUSY;
+ }
+
+ offset = PKAWritePkaParam(bigNum1, bigNum1Length, offset, PKA_O_APTR);
+
+ offset = PKAWritePkaParam(bigNum2, bigNum2Length, offset, PKA_O_BPTR);
+
+ // Copy the result vector address location.
+ *resultPKAMemAddr = PKA_RAM_BASE + offset;
+
+ // Load C pointer with the result location in PKA RAM.
+ HWREG(PKA_BASE + PKA_O_CPTR) = offset >> 2;
+
+ // Set the function for the add operation and start the operation.
+ HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_ADD);
+
+ return PKA_STATUS_SUCCESS;
+}
+
+//*****************************************************************************
+//
+// Get the result of the addition operation on two big number.
+//
+//*****************************************************************************
+uint32_t PKABigNumSubGetResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr)
+{
+ return PKAGetBigNumResult(resultBuf, resultLength, resultPKAMemAddr);
+}
+
+//*****************************************************************************
+//
+// Start the addition of two big number.
+//
+//*****************************************************************************
+uint32_t PKABigNumSubStart(const uint8_t *minuend, uint32_t minuendLength, const uint8_t *subtrahend, uint32_t subtrahendLength, uint32_t *resultPKAMemAddr)
+{
+ uint32_t offset = 0;
+
+ // Check for arguments.
+ ASSERT(minuend);
+ ASSERT(subtrahend);
+ ASSERT(resultPKAMemAddr);
+
+
+ // Make sure no operation is in progress.
+ if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) {
+ return PKA_STATUS_OPERATION_BUSY;
+ }
+
+ offset = PKAWritePkaParam(minuend, minuendLength, offset, PKA_O_APTR);
+
+ offset = PKAWritePkaParam(subtrahend, subtrahendLength, offset, PKA_O_BPTR);
+
+ // Copy the result vector address location.
+ *resultPKAMemAddr = PKA_RAM_BASE + offset;
+
+ // Load C pointer with the result location in PKA RAM.
+ HWREG(PKA_BASE + PKA_O_CPTR) = offset >> 2;
+
+ // Set the function for the add operation and start the operation.
+ HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_SUBTRACT);
+
+ return PKA_STATUS_SUCCESS;
+}
+
+//*****************************************************************************
+//
+// Get the result of the addition operation on two big number.
+//
+//*****************************************************************************
+uint32_t PKABigNumAddGetResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr)
+{
+ return PKAGetBigNumResult(resultBuf, resultLength, resultPKAMemAddr);
+}
+
+
+//*****************************************************************************
+//
+// Start ECC Multiplication.
+//
+//*****************************************************************************
+uint32_t PKAEccMultiplyStart(const uint8_t *scalar, const uint8_t *curvePointX, const uint8_t *curvePointY, const uint8_t *prime, const uint8_t *a, const uint8_t *b, uint32_t length, uint32_t *resultPKAMemAddr)
+{
+ uint32_t offset = 0;
+
+ // Check for the arguments.
+ ASSERT(scalar);
+ ASSERT(curvePointX);
+ ASSERT(curvePointY);
+ ASSERT(prime);
+ ASSERT(a);
+ ASSERT(b);
+ ASSERT(length <= PKA_MAX_CURVE_SIZE_32_BIT_WORD * sizeof(uint32_t));
+ ASSERT(resultPKAMemAddr);
+
+ // Make sure no PKA operation is in progress.
+ if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) {
+ return PKA_STATUS_OPERATION_BUSY;
+ }
+
+ offset = PKAWritePkaParam(scalar, length, offset, PKA_O_APTR);
+
+ offset = PKAWritePkaParamExtraOffset(prime, length, offset, PKA_O_BPTR);
+ offset = PKAWritePkaParamExtraOffset(a, length, offset, PKA_NO_POINTER_REG);
+ offset = PKAWritePkaParamExtraOffset(b, length, offset, PKA_NO_POINTER_REG);
+
+ offset = PKAWritePkaParamExtraOffset(curvePointX, length, offset, PKA_O_CPTR);
+ offset = PKAWritePkaParamExtraOffset(curvePointY, length, offset, PKA_NO_POINTER_REG);
+
+ // Update the result location.
+ // The resultPKAMemAddr may be 0 if we only want to check that we generated the point at infinity
+ if (resultPKAMemAddr) {
+ *resultPKAMemAddr = PKA_RAM_BASE + offset;
+ }
+
+ // Load D pointer with the result location in PKA RAM.
+ HWREG(PKA_BASE + PKA_O_DPTR) = offset >> 2;
+
+ // Set the PKA function to ECC-MULT and start the operation.
+ HWREG(PKA_BASE + PKA_O_FUNCTION) = PKA_FUNCTION_RUN_M | (0x05 << PKA_FUNCTION_SEQUENCER_OPERATIONS_S);
+
+ return PKA_STATUS_SUCCESS;
+}
+
+
+//*****************************************************************************
+//
+// Start ECC Montgomery Multiplication.
+//
+//*****************************************************************************
+uint32_t PKAEccMontgomeryMultiplyStart(const uint8_t *scalar, const uint8_t *curvePointX, const uint8_t *prime, const uint8_t *a, uint32_t length, uint32_t *resultPKAMemAddr)
+{
+ uint32_t offset = 0;
+
+ // Check for the arguments.
+ ASSERT(scalar);
+ ASSERT(curvePointX);
+ ASSERT(prime);
+ ASSERT(a);
+ ASSERT(length <= PKA_MAX_CURVE_SIZE_32_BIT_WORD * sizeof(uint32_t));
+ ASSERT(resultPKAMemAddr);
+
+ // Make sure no PKA operation is in progress.
+ if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) {
+ return PKA_STATUS_OPERATION_BUSY;
+ }
+
+ offset = PKAWritePkaParam(scalar, length, offset, PKA_O_APTR);
+
+ offset = PKAWritePkaParamExtraOffset(prime, length, offset, PKA_O_BPTR);
+ offset = PKAWritePkaParamExtraOffset(a, length, offset, PKA_NO_POINTER_REG);
+
+ offset = PKAWritePkaParamExtraOffset(curvePointX, length, offset, PKA_O_CPTR);
+
+ // Update the result location.
+ // The resultPKAMemAddr may be 0 if we only want to check that we generated the point at infinity
+ if (resultPKAMemAddr) {
+ *resultPKAMemAddr = PKA_RAM_BASE + offset;
+ }
+
+ // Load D pointer with the result location in PKA RAM.
+ HWREG(PKA_BASE + PKA_O_DPTR) = offset >> 2;
+
+ // Set the PKA function to Montgomery ECC-MULT and start the operation.
+ HWREG(PKA_BASE + PKA_O_FUNCTION) = PKA_FUNCTION_RUN_M | (0x02 << PKA_FUNCTION_SEQUENCER_OPERATIONS_S);
+
+ return PKA_STATUS_SUCCESS;
+}
+
+
+//*****************************************************************************
+//
+// Get the result of ECC Multiplication
+//
+//*****************************************************************************
+uint32_t PKAEccMultiplyGetResult(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length)
+{
+ return PKAGetECCResult(curvePointX, curvePointY, resultPKAMemAddr, length);
+}
+
+//*****************************************************************************
+//
+// Start the ECC Addition.
+//
+//*****************************************************************************
+uint32_t PKAEccAddStart(const uint8_t *curvePoint1X, const uint8_t *curvePoint1Y, const uint8_t *curvePoint2X, const uint8_t *curvePoint2Y, const uint8_t *prime, const uint8_t *a, uint32_t length, uint32_t *resultPKAMemAddr)
+{
+ uint32_t offset = 0;
+
+ // Check for the arguments.
+ ASSERT(curvePoint1X);
+ ASSERT(curvePoint1Y);
+ ASSERT(curvePoint2X);
+ ASSERT(curvePoint2Y);
+ ASSERT(prime);
+ ASSERT(a);
+ ASSERT(resultPKAMemAddr);
+
+ // Make sure no operation is in progress.
+ if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) {
+ return PKA_STATUS_OPERATION_BUSY;
+ }
+
+ offset = PKAWritePkaParamExtraOffset(curvePoint1X, length, offset, PKA_O_APTR);
+ offset = PKAWritePkaParamExtraOffset(curvePoint1Y, length, offset, PKA_NO_POINTER_REG);
+
+
+ offset = PKAWritePkaParamExtraOffset(prime, length, offset, PKA_O_BPTR);
+ offset = PKAWritePkaParamExtraOffset(a, length, offset, PKA_NO_POINTER_REG);
+
+ offset = PKAWritePkaParamExtraOffset(curvePoint2X, length, offset, PKA_O_CPTR);
+ offset = PKAWritePkaParamExtraOffset(curvePoint2Y, length, offset, PKA_NO_POINTER_REG);
+
+ // Copy the result vector location.
+ *resultPKAMemAddr = PKA_RAM_BASE + offset;
+
+ // Load D pointer with the result location in PKA RAM.
+ HWREG(PKA_BASE + PKA_O_DPTR) = offset >> 2;
+
+ // Set the PKA Function to ECC-ADD and start the operation.
+ HWREG(PKA_BASE + PKA_O_FUNCTION ) = PKA_FUNCTION_RUN_M | (0x03 << PKA_FUNCTION_SEQUENCER_OPERATIONS_S);
+
+ return PKA_STATUS_SUCCESS;
+}
+
+//*****************************************************************************
+//
+// Get the result of the ECC Addition
+//
+//*****************************************************************************
+uint32_t PKAEccAddGetResult(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length)
+{
+ return PKAGetECCResult(curvePointX, curvePointY, resultPKAMemAddr, length);
+}
+
+//*****************************************************************************
+//
+// Verify a public key against the supplied elliptic curve equation
+//
+//*****************************************************************************
+uint32_t PKAEccVerifyPublicKeyWeierstrassStart(const uint8_t *curvePointX, const uint8_t *curvePointY, const uint8_t *prime, const uint8_t *a, const uint8_t *b, const uint8_t *order, uint32_t length)
+{
+ uint32_t pkaResult;
+ uint32_t resultAddress;
+ uint32_t resultLength;
+ uint8_t *scratchBuffer = (uint8_t *)(PKA_RAM_BASE + PKA_RAM_TOT_BYTE_SIZE / 2);
+ uint8_t *scratchBuffer2 = scratchBuffer + 512;
+
+
+ // Verify X in range [0, prime - 1]
+ PKABigNumCmpStart(curvePointX,
+ prime,
+ length);
+
+ while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY);
+
+ pkaResult = PKABigNumCmpGetResult();
+
+ if (pkaResult != PKA_STATUS_A_LESS_THAN_B) {
+ return PKA_STATUS_X_LARGER_THAN_PRIME;
+ }
+
+ // Verify Y in range [0, prime - 1]
+ PKABigNumCmpStart(curvePointY,
+ prime,
+ length);
+
+ while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY);
+
+ pkaResult = PKABigNumCmpGetResult();
+
+ if (pkaResult != PKA_STATUS_A_LESS_THAN_B) {
+ return PKA_STATUS_Y_LARGER_THAN_PRIME;
+ }
+
+ // Verify point on curve
+ // Short-Weierstrass equation: Y ^ 2 = X ^3 + a * X + b mod P
+ // Reduced: Y ^ 2 = X * (X ^ 2 + a) + b
+
+ // tmp = X ^ 2
+ PKABigNumMultiplyStart(curvePointX, length, curvePointX, length, &resultAddress);
+
+ while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY);
+
+ resultLength = 200;
+ pkaResult = PKABigNumMultGetResult(scratchBuffer, &resultLength, resultAddress);
+
+ if (pkaResult != PKA_STATUS_SUCCESS) {
+ return PKA_STATUS_FAILURE;
+ }
+
+ // tmp += a
+ PKABigNumAddStart(scratchBuffer, resultLength, a, length, &resultAddress);
+
+ while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY);
+
+ resultLength = 200;
+ pkaResult = PKABigNumAddGetResult(scratchBuffer, &resultLength, resultAddress);
+
+ if (pkaResult != PKA_STATUS_SUCCESS) {
+ return PKA_STATUS_FAILURE;
+ }
+
+ // tmp *= x
+ PKABigNumMultiplyStart(scratchBuffer, resultLength, curvePointX, length, &resultAddress);
+
+ while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY);
+
+ resultLength = 200;
+ pkaResult = PKABigNumMultGetResult(scratchBuffer, &resultLength, resultAddress);
+
+ if (pkaResult != PKA_STATUS_SUCCESS) {
+ return PKA_STATUS_FAILURE;
+ }
+
+ // tmp += b
+ PKABigNumAddStart(scratchBuffer, resultLength, b, length, &resultAddress);
+
+ while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY);
+
+ resultLength = 200;
+ pkaResult = PKABigNumAddGetResult(scratchBuffer, &resultLength, resultAddress);
+
+ if (pkaResult != PKA_STATUS_SUCCESS) {
+ return PKA_STATUS_FAILURE;
+ }
+
+
+ // tmp2 = tmp % prime to ensure we have no fraction in the division.
+ // The number will only shrink from here on out.
+ PKABigNumModStart(scratchBuffer, resultLength, prime, length, &resultAddress);
+
+ while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY);
+
+ // If the result is not a multiple of the word-length, the PKA HW will round up
+ // because it deals in words only. That means that using 'length' directly
+ // would cause and underflow, since length refers to the actual length in bytes of
+ // the curve parameters while the PKA HW reports that rounded up to the next
+ // word boundary.
+ // Use 200 as the resultLength instead since we are copying to the scratch buffer
+ // anyway.
+ // Practically, this only happens with curves such as NIST-P521 that are not word
+ // multiples.
+ resultLength = 200;
+ pkaResult = PKABigNumModGetResult(scratchBuffer2, resultLength, resultAddress);
+
+ if (pkaResult != PKA_STATUS_SUCCESS) {
+ return PKA_STATUS_FAILURE;
+ }
+
+ // tmp = y^2
+ PKABigNumMultiplyStart(curvePointY, length, curvePointY, length, &resultAddress);
+
+ while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY);
+
+ resultLength = 200;
+ pkaResult = PKABigNumMultGetResult(scratchBuffer, &resultLength, resultAddress);
+
+ if (pkaResult != PKA_STATUS_SUCCESS) {
+ return PKA_STATUS_FAILURE;
+ }
+
+ // tmp %= prime
+ PKABigNumModStart(scratchBuffer, resultLength, prime, length, &resultAddress);
+
+ while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY);
+
+ // If the result is not a multiple of the word-length, the PKA HW will round up
+ // because it deals in words only. That means that using 'length' directly
+ // would cause and underflow, since length refers to the actual length in bytes of
+ // the curve parameters while the PKA HW reports that rounded up to the next
+ // word boundary.
+ // Use 200 as the resultLength instead since we are copying to the scratch buffer
+ // anyway.
+ // Practically, this only happens with curves such as NIST-P521 that are not word
+ // multiples.
+ resultLength = 200;
+ pkaResult = PKABigNumModGetResult(scratchBuffer, resultLength, resultAddress);
+
+ if (pkaResult != PKA_STATUS_SUCCESS) {
+ return PKA_STATUS_FAILURE;
+ }
+
+ // tmp ?= tmp2
+ PKABigNumCmpStart(scratchBuffer,
+ scratchBuffer2,
+ length);
+
+ while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY);
+
+ pkaResult = PKABigNumCmpGetResult();
+
+ if (pkaResult != PKA_STATUS_EQUAL) {
+ return PKA_STATUS_POINT_NOT_ON_CURVE;
+ }
+ else {
+ return PKA_STATUS_SUCCESS;
+ }
+}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/pka.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/pka.h
new file mode 100644
index 0000000..e175ada
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/pka.h
@@ -0,0 +1,1455 @@
+/******************************************************************************
+* Filename: pka.h
+* Revised: 2018-07-19 15:07:05 +0200 (Thu, 19 Jul 2018)
+* Revision: 52294
+*
+* Description: PKA header file.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup peripheral_group
+//! @{
+//! \addtogroup pka_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __PKA_H__
+#define __PKA_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "../inc/hw_types.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_ints.h"
+#include "../inc/hw_pka.h"
+#include "../inc/hw_pka_ram.h"
+#include "interrupt.h"
+#include "sys_ctrl.h"
+#include "debug.h"
+#include <string.h>
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// This section renames all functions that are not "static inline", so that
+// calling these functions will default to implementation in flash. At the end
+// of this file a second renaming will change the defaults to implementation in
+// ROM for available functions.
+//
+// To force use of the implementation in flash, e.g. for debugging:
+// - Globally: Define DRIVERLIB_NOROM at project level
+// - Per function: Use prefix "NOROM_" when calling the function
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #define PKAClearPkaRam NOROM_PKAClearPkaRam
+ #define PKAGetOpsStatus NOROM_PKAGetOpsStatus
+ #define PKAArrayAllZeros NOROM_PKAArrayAllZeros
+ #define PKAZeroOutArray NOROM_PKAZeroOutArray
+ #define PKABigNumModStart NOROM_PKABigNumModStart
+ #define PKABigNumModGetResult NOROM_PKABigNumModGetResult
+ #define PKABigNumDivideStart NOROM_PKABigNumDivideStart
+ #define PKABigNumDivideGetQuotient NOROM_PKABigNumDivideGetQuotient
+ #define PKABigNumDivideGetRemainder NOROM_PKABigNumDivideGetRemainder
+ #define PKABigNumCmpStart NOROM_PKABigNumCmpStart
+ #define PKABigNumCmpGetResult NOROM_PKABigNumCmpGetResult
+ #define PKABigNumInvModStart NOROM_PKABigNumInvModStart
+ #define PKABigNumInvModGetResult NOROM_PKABigNumInvModGetResult
+ #define PKABigNumMultiplyStart NOROM_PKABigNumMultiplyStart
+ #define PKABigNumMultGetResult NOROM_PKABigNumMultGetResult
+ #define PKABigNumAddStart NOROM_PKABigNumAddStart
+ #define PKABigNumAddGetResult NOROM_PKABigNumAddGetResult
+ #define PKABigNumSubStart NOROM_PKABigNumSubStart
+ #define PKABigNumSubGetResult NOROM_PKABigNumSubGetResult
+ #define PKAEccMultiplyStart NOROM_PKAEccMultiplyStart
+ #define PKAEccMontgomeryMultiplyStart NOROM_PKAEccMontgomeryMultiplyStart
+ #define PKAEccMultiplyGetResult NOROM_PKAEccMultiplyGetResult
+ #define PKAEccAddStart NOROM_PKAEccAddStart
+ #define PKAEccAddGetResult NOROM_PKAEccAddGetResult
+ #define PKAEccVerifyPublicKeyWeierstrassStart NOROM_PKAEccVerifyPublicKeyWeierstrassStart
+#endif
+
+
+
+
+//*****************************************************************************
+//
+// Function return values
+//
+//*****************************************************************************
+#define PKA_STATUS_SUCCESS 0 //!< Success
+#define PKA_STATUS_FAILURE 1 //!< Failure
+#define PKA_STATUS_INVALID_PARAM 2 //!< Invalid parameter
+#define PKA_STATUS_BUF_UNDERFLOW 3 //!< Buffer underflow
+#define PKA_STATUS_RESULT_0 4 //!< Result is all zeros
+#define PKA_STATUS_A_GREATER_THAN_B 5 //!< Big number compare return status if the first big number is greater than the second.
+#define PKA_STATUS_A_LESS_THAN_B 6 //!< Big number compare return status if the first big number is less than the second.
+#define PKA_STATUS_EQUAL 7 //!< Big number compare return status if the first big number is equal to the second.
+#define PKA_STATUS_OPERATION_BUSY 8 //!< PKA operation is in progress.
+#define PKA_STATUS_OPERATION_RDY 9 //!< No PKA operation is in progress.
+#define PKA_STATUS_LOCATION_IN_USE 10 //!< Location in PKA RAM is not available
+#define PKA_STATUS_X_ZERO 11 //!< X coordinate of public key is 0
+#define PKA_STATUS_Y_ZERO 12 //!< Y coordinate of public key is 0
+#define PKA_STATUS_X_LARGER_THAN_PRIME 13 //!< X coordinate of public key is larger than the curve prime
+#define PKA_STATUS_Y_LARGER_THAN_PRIME 14 //!< Y coordinate of public key is larger than the curve prime
+#define PKA_STATUS_POINT_NOT_ON_CURVE 15 //!< The public key is not on the specified elliptic curve
+#define PKA_STATUS_RESULT_ADDRESS_INCORRECT 16 //!< The address of the result passed into one of the PKA*GetResult functions is incorrect
+#define PKA_STATUS_POINT_AT_INFINITY 17 //!< The ECC operation resulted in the point at infinity
+
+
+//*****************************************************************************
+//
+// Length in bytes of NISTP224 parameters.
+//
+//*****************************************************************************
+#define NISTP224_PARAM_SIZE_BYTES 28
+
+//*****************************************************************************
+//
+// Length in bytes of NISTP256 parameters.
+//
+//*****************************************************************************
+#define NISTP256_PARAM_SIZE_BYTES 32
+
+//*****************************************************************************
+//
+// Length in bytes of NISTP384 parameters.
+//
+//*****************************************************************************
+#define NISTP384_PARAM_SIZE_BYTES 48
+
+//*****************************************************************************
+//
+// Length in bytes of NISTP521 parameters.
+//
+//*****************************************************************************
+#define NISTP521_PARAM_SIZE_BYTES 66
+
+//*****************************************************************************
+//
+// Length in bytes of BrainpoolP256R1 parameters.
+//
+//*****************************************************************************
+#define BrainpoolP256R1_PARAM_SIZE_BYTES 32
+
+//*****************************************************************************
+//
+// Length in bytes of BrainpoolP384R1 parameters.
+//
+//*****************************************************************************
+#define BrainpoolP384R1_PARAM_SIZE_BYTES 48
+
+//*****************************************************************************
+//
+// Length in bytes of BrainpoolP512R1 parameters.
+//
+//*****************************************************************************
+#define BrainpoolP512R1_PARAM_SIZE_BYTES 64
+
+//*****************************************************************************
+//
+// Length in bytes of Curve25519 parameters.
+//
+//*****************************************************************************
+#define Curve25519_PARAM_SIZE_BYTES 32
+
+//*****************************************************************************
+//
+// Union for parameters that forces 32-bit alignment on the byte array.
+//
+//*****************************************************************************
+typedef union {
+ uint8_t byte[28];
+ uint32_t word[28 / sizeof(uint32_t)];
+} PKA_EccParam224;
+
+typedef union {
+ uint8_t byte[32];
+ uint32_t word[32 / sizeof(uint32_t)];
+} PKA_EccParam256;
+
+typedef union {
+ uint8_t byte[48];
+ uint32_t word[48 / sizeof(uint32_t)];
+} PKA_EccParam384;
+
+typedef union {
+ uint8_t byte[64];
+ uint32_t word[64 / sizeof(uint32_t)];
+} PKA_EccParam512;
+
+typedef union {
+ uint8_t byte[68];
+ uint32_t word[68 / sizeof(uint32_t)];
+} PKA_EccParam521;
+
+//*****************************************************************************
+//
+// Struct to keep points in that forces adjacency of X and Y coordinates in
+// memmory.
+//
+//*****************************************************************************
+
+
+typedef struct PKA_EccPoint224_ {
+ PKA_EccParam224 x;
+ PKA_EccParam224 y;
+} PKA_EccPoint224;
+
+typedef struct PKA_EccPoint256_ {
+ PKA_EccParam256 x;
+ PKA_EccParam256 y;
+} PKA_EccPoint256;
+
+typedef struct PKA_EccPoint384_ {
+ PKA_EccParam384 x;
+ PKA_EccParam384 y;
+} PKA_EccPoint384;
+
+typedef struct PKA_EccPoint512_ {
+ PKA_EccParam512 x;
+ PKA_EccParam512 y;
+} PKA_EccPoint512;
+
+typedef struct PKA_EccPoint521_ {
+ PKA_EccParam521 x;
+ PKA_EccParam521 y;
+} PKA_EccPoint521;
+
+
+//*****************************************************************************
+//
+//! \brief X coordinate of the generator point of the NISTP224 curve.
+//
+//*****************************************************************************
+extern const PKA_EccPoint224 NISTP224_generator;
+
+//*****************************************************************************
+//
+//! \brief Prime of the NISTP224 curve.
+//
+//*****************************************************************************
+extern const PKA_EccParam224 NISTP224_prime;
+
+
+//*****************************************************************************
+//
+//! \brief a constant of the NISTP224 curve when expressed in short
+//! Weierstrass form (y^3 = x^2 + a*x + b).
+//
+//*****************************************************************************
+extern const PKA_EccParam224 NISTP224_a;
+
+
+//*****************************************************************************
+//
+//! \brief b constant of the NISTP224 curve when expressed in short
+//! Weierstrass form (y^3 = x^2 + a*x + b).
+//
+//*****************************************************************************
+extern const PKA_EccParam224 NISTP224_b;
+
+
+//*****************************************************************************
+//
+//! \brief Order of the NISTP224 curve.
+//
+//*****************************************************************************
+extern const PKA_EccParam224 NISTP224_order;
+
+
+
+
+//*****************************************************************************
+//
+//! \brief X coordinate of the generator point of the NISTP256 curve.
+//
+//*****************************************************************************
+extern const PKA_EccPoint256 NISTP256_generator;
+
+//*****************************************************************************
+//
+//! \brief Prime of the NISTP256 curve.
+//
+//*****************************************************************************
+extern const PKA_EccParam256 NISTP256_prime;
+
+
+//*****************************************************************************
+//
+//! \brief a constant of the NISTP256 curve when expressed in short
+//! Weierstrass form (y^3 = x^2 + a*x + b).
+//
+//*****************************************************************************
+extern const PKA_EccParam256 NISTP256_a;
+
+
+//*****************************************************************************
+//
+//! \brief b constant of the NISTP256 curve when expressed in short
+//! Weierstrass form (y^3 = x^2 + a*x + b).
+//
+//*****************************************************************************
+extern const PKA_EccParam256 NISTP256_b;
+
+
+//*****************************************************************************
+//
+//! \brief Order of the NISTP256 curve.
+//
+//*****************************************************************************
+extern const PKA_EccParam256 NISTP256_order;
+
+
+
+
+
+//*****************************************************************************
+//
+//! \brief X coordinate of the generator point of the NISTP384 curve.
+//
+//*****************************************************************************
+extern const PKA_EccPoint384 NISTP384_generator;
+
+//*****************************************************************************
+//
+//! \brief Prime of the NISTP384 curve.
+//
+//*****************************************************************************
+extern const PKA_EccParam384 NISTP384_prime;
+
+
+//*****************************************************************************
+//
+//! \brief a constant of the NISTP384 curve when expressed in short
+//! Weierstrass form (y^3 = x^2 + a*x + b).
+//
+//*****************************************************************************
+extern const PKA_EccParam384 NISTP384_a;
+
+
+//*****************************************************************************
+//
+//! \brief b constant of the NISTP384 curve when expressed in short
+//! Weierstrass form (y^3 = x^2 + a*x + b).
+//
+//*****************************************************************************
+extern const PKA_EccParam384 NISTP384_b;
+
+
+//*****************************************************************************
+//
+//! \brief Order of the NISTP384 curve.
+//
+//*****************************************************************************
+extern const PKA_EccParam384 NISTP384_order;
+
+
+
+
+//*****************************************************************************
+//
+//! \brief X coordinate of the generator point of the NISTP521 curve.
+//
+//*****************************************************************************
+extern const PKA_EccPoint521 NISTP521_generator;
+
+//*****************************************************************************
+//
+//! \brief Prime of the NISTP521 curve.
+//
+//*****************************************************************************
+extern const PKA_EccParam521 NISTP521_prime;
+
+
+//*****************************************************************************
+//
+//! \brief a constant of the NISTP521 curve when expressed in short
+//! Weierstrass form (y^3 = x^2 + a*x + b).
+//
+//*****************************************************************************
+extern const PKA_EccParam521 NISTP521_a;
+
+
+//*****************************************************************************
+//
+//! \brief b constant of the NISTP521 curve when expressed in short
+//! Weierstrass form (y^3 = x^2 + a*x + b).
+//
+//*****************************************************************************
+extern const PKA_EccParam521 NISTP521_b;
+
+
+//*****************************************************************************
+//
+//! \brief Order of the NISTP521 curve.
+//
+//*****************************************************************************
+extern const PKA_EccParam521 NISTP521_order;
+
+
+
+
+//*****************************************************************************
+//
+//! \brief X coordinate of the generator point of the BrainpoolP256R1 curve.
+//
+//*****************************************************************************
+extern const PKA_EccPoint256 BrainpoolP256R1_generator;
+
+//*****************************************************************************
+//
+//! \brief Prime of the BrainpoolP256R1 curve.
+//
+//*****************************************************************************
+extern const PKA_EccParam256 BrainpoolP256R1_prime;
+
+
+//*****************************************************************************
+//
+//! \brief a constant of the BrainpoolP256R1 curve when expressed in short
+//! Weierstrass form (y^3 = x^2 + a*x + b).
+//
+//*****************************************************************************
+extern const PKA_EccParam256 BrainpoolP256R1_a;
+
+
+//*****************************************************************************
+//
+//! \brief b constant of the BrainpoolP256R1 curve when expressed in short
+//! Weierstrass form (y^3 = x^2 + a*x + b).
+//
+//*****************************************************************************
+extern const PKA_EccParam256 BrainpoolP256R1_b;
+
+
+//*****************************************************************************
+//
+//! \brief Order of the BrainpoolP256R1 curve.
+//
+//*****************************************************************************
+extern const PKA_EccParam256 BrainpoolP256R1_order;
+
+
+
+
+//*****************************************************************************
+//
+//! \brief X coordinate of the generator point of the BrainpoolP384R1 curve.
+//
+//*****************************************************************************
+extern const PKA_EccPoint384 BrainpoolP384R1_generator;
+
+//*****************************************************************************
+//
+//! \brief Prime of the BrainpoolP384R1 curve.
+//
+//*****************************************************************************
+extern const PKA_EccParam384 BrainpoolP384R1_prime;
+
+
+//*****************************************************************************
+//
+//! \brief a constant of the BrainpoolP384R1 curve when expressed in short
+//! Weierstrass form (y^3 = x^2 + a*x + b).
+//
+//*****************************************************************************
+extern const PKA_EccParam384 BrainpoolP384R1_a;
+
+
+//*****************************************************************************
+//
+//! \brief b constant of the BrainpoolP384R1 curve when expressed in short
+//! Weierstrass form (y^3 = x^2 + a*x + b).
+//
+//*****************************************************************************
+extern const PKA_EccParam384 BrainpoolP384R1_b;
+
+
+//*****************************************************************************
+//
+//! \brief Order of the BrainpoolP384R1 curve.
+//
+//*****************************************************************************
+extern const PKA_EccParam384 BrainpoolP384R1_order;
+
+
+
+//*****************************************************************************
+//
+//! \brief X coordinate of the generator point of the BrainpoolP512R1 curve.
+//
+//*****************************************************************************
+extern const PKA_EccPoint512 BrainpoolP512R1_generator;
+
+//*****************************************************************************
+//
+//! \brief Prime of the BrainpoolP512R1 curve.
+//
+//*****************************************************************************
+extern const PKA_EccParam512 BrainpoolP512R1_prime;
+
+
+//*****************************************************************************
+//
+//! \brief a constant of the BrainpoolP512R1 curve when expressed in short
+//! Weierstrass form (y^3 = x^2 + a*x + b).
+//
+//*****************************************************************************
+extern const PKA_EccParam512 BrainpoolP512R1_a;
+
+
+//*****************************************************************************
+//
+//! \brief b constant of the BrainpoolP512R1 curve when expressed in short
+//! Weierstrass form (y^3 = x^2 + a*x + b).
+//
+//*****************************************************************************
+extern const PKA_EccParam512 BrainpoolP512R1_b;
+
+
+//*****************************************************************************
+//
+//! \brief Order of the BrainpoolP512R1 curve.
+//
+//*****************************************************************************
+extern const PKA_EccParam512 BrainpoolP512R1_order;
+
+
+
+//*****************************************************************************
+//
+//! \brief X coordinate of the generator point of the Curve25519 curve.
+//
+//*****************************************************************************
+extern const PKA_EccPoint256 Curve25519_generator;
+
+//*****************************************************************************
+//
+//! \brief Prime of the Curve25519 curve.
+//
+//*****************************************************************************
+extern const PKA_EccParam256 Curve25519_prime;
+
+
+//*****************************************************************************
+//
+//! \brief a constant of the Curve25519 curve when expressed in Montgomery
+//! form (By^2 = x^3 + a*x^2 + x).
+//
+//*****************************************************************************
+extern const PKA_EccParam256 Curve25519_a;
+
+
+//*****************************************************************************
+//
+//! \brief b constant of the Curve25519 curve when expressed in Montgomery
+//! form (By^2 = x^3 + a*x^2 + x).
+//
+//*****************************************************************************
+extern const PKA_EccParam256 Curve25519_b;
+
+
+//*****************************************************************************
+//
+//! \brief Order of the Curve25519 curve.
+//
+//*****************************************************************************
+extern const PKA_EccParam256 Curve25519_order;
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \brief Zeroizes PKA RAM.
+//!
+//! This function uses the zeroization function in PRCM to clear the PKA RAM.
+//
+//*****************************************************************************
+extern void PKAClearPkaRam(void);
+
+//*****************************************************************************
+//
+//! \brief Gets the PKA operation status.
+//!
+//! This function gets information on whether any PKA operation is in
+//! progress or not. This function allows to check the PKA operation status
+//! before starting any new PKA operation.
+//!
+//! \return Returns a status code.
+//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA operation is in progress.
+//! - \ref PKA_STATUS_OPERATION_RDY if the PKA operation is not in progress.
+//
+//*****************************************************************************
+extern uint32_t PKAGetOpsStatus(void);
+
+//*****************************************************************************
+//
+//! \brief Checks whether and array only consists of zeros
+//!
+//! \param [in] array is the array to check.
+//!
+//! \param [in] arrayLength is the length of the array.
+//!
+//! \return Returns true if the array contains only zeros and false if one
+//! or more bits are set.
+//
+//*****************************************************************************
+extern bool PKAArrayAllZeros(const uint8_t *array, uint32_t arrayLength);
+
+//*****************************************************************************
+//
+//! \brief Zeros-out an array
+//!
+//! \param [in] array is the array to zero-out.
+//!
+//! \param [in] arrayLength is the length of the array.
+//
+//*****************************************************************************
+extern void PKAZeroOutArray(const uint8_t *array, uint32_t arrayLength);
+
+//*****************************************************************************
+//
+//! \brief Starts a big number modulus operation.
+//!
+//! This function starts the modulo operation on the big number \c bigNum
+//! using the divisor \c modulus. The PKA RAM location where the result
+//! will be available is stored in \c resultPKAMemAddr.
+//!
+//! \param [in] bigNum is the pointer to the big number on which modulo operation
+//! needs to be carried out.
+//!
+//! \param [in] bigNumLength is the size of the big number \c bigNum in bytes.
+//!
+//! \param [in] modulus is the pointer to the divisor.
+//!
+//! \param [in] modulusLength is the size of the divisor \c modulus in bytes.
+//!
+//! \param [out] resultPKAMemAddr is the pointer to the result vector location
+//! which will be set by this function.
+//!
+//!\return Returns a status code.
+//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation.
+//! - \ref PKA_STATUS_OPERATION_BUSY, if the PKA module is busy doing
+//! some other operation.
+//!
+//! \sa PKABigNumModGetResult()
+//
+//*****************************************************************************
+extern uint32_t PKABigNumModStart(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr);
+
+//*****************************************************************************
+//
+//! \brief Gets the result of the big number modulus operation.
+//!
+//! This function gets the result of the big number modulus operation which was
+//! previously started using the function PKABigNumModStart().
+//! The function will zero-out \c resultBuf prior to copying in the result of
+//! the modulo operation.
+//!
+//! \param [out] resultBuf is the pointer to buffer where the result needs to
+//! be stored.
+//!
+//! \param [in] length is the size of the provided buffer in bytes.
+//!
+//! \param [in] resultPKAMemAddr is the address of the result location which
+//! was provided by the start function PKABigNumModStart().
+//!
+//! \return Returns a status code.
+//! - \ref PKA_STATUS_SUCCESS if successful.
+//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing
+//! the operation.
+//! - \ref PKA_STATUS_RESULT_0 if the result is all zeros.
+//! - \ref PKA_STATUS_BUF_UNDERFLOW if the \c length is less than the length
+//! of the result.
+//!
+//! \sa PKABigNumModStart()
+//
+//*****************************************************************************
+extern uint32_t PKABigNumModGetResult(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr);
+
+//*****************************************************************************
+//
+//! \brief Starts a big number divide operation.
+//!
+//! This function starts the dive operation on the big number \c bigNum
+//! using the \c divisor. The PKA RAM location where the result
+//! will be available is stored in \c resultPKAMemAddr.
+//!
+//! \param [in] dividend is the pointer to the big number to be divided.
+//!
+//! \param [in] dividendLength is the size of the big number \c dividend in bytes.
+//!
+//! \param [in] divisor is the pointer to the divisor.
+//!
+//! \param [in] divisorLength is the size of the \c divisor in bytes.
+//!
+//! \param [out] resultQuotientMemAddr is the pointer to the quotient vector location
+//! which will be set by this function.
+//!
+//! \param [out] resultRemainderMemAddr is the pointer to the remainder vector location
+//! which will be set by this function.
+//!
+//!\return Returns a status code.
+//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation.
+//! - \ref PKA_STATUS_OPERATION_BUSY, if the PKA module is busy doing
+//! some other operation.
+//!
+//! \sa PKABigNumDivideGetResult()
+//
+//*****************************************************************************
+extern uint32_t PKABigNumDivideStart(const uint8_t *dividend,
+ uint32_t dividendLength,
+ const uint8_t *divisor,
+ uint32_t divisorLength,
+ uint32_t *resultQuotientMemAddr,
+ uint32_t *resultRemainderMemAddr);
+
+//*****************************************************************************
+//
+//! \brief Gets the quotient of the big number divide operation.
+//!
+//! This function gets the quotient of the big number divide operation which was
+//! previously started using the function PKABigNumDivideStart().
+//!
+//! \param [out] resultBuf is the pointer to buffer where the result needs to
+//! be stored.
+//!
+//! \param [in] length is the size of the provided buffer in bytes.
+//!
+//! \param [in] resultQuotientMemAddr is the address of the result location which
+//! was provided by the start function PKABigNumDivideStart().
+//!
+//! \return Returns a status code.
+//! - \ref PKA_STATUS_SUCCESS if successful.
+//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing
+//! the operation.
+//! - \ref PKA_STATUS_RESULT_0 if the result is all zeros.
+//! - \ref PKA_STATUS_BUF_UNDERFLOW if the \c length is less than the length
+//! of the result.
+//!
+//! \sa PKABigNumDivideStart()
+//
+//*****************************************************************************
+extern uint32_t PKABigNumDivideGetQuotient(uint8_t *resultBuf, uint32_t *length, uint32_t resultQuotientMemAddr);
+
+//*****************************************************************************
+//
+//! \brief Gets the remainder of the big number divide operation.
+//!
+//! This function gets the remainder of the big number divide operation which was
+//! previously started using the function PKABigNumDivideStart().
+//!
+//! \param [out] resultBuf is the pointer to buffer where the result needs to
+//! be stored.
+//!
+//! \param [in] length is the size of the provided buffer in bytes.
+//!
+//! \param [in] resultRemainderMemAddr is the address of the result location which
+//! was provided by the start function PKABigNumDivideStart().
+//!
+//! \return Returns a status code.
+//! - \ref PKA_STATUS_SUCCESS if successful.
+//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing
+//! the operation.
+//! - \ref PKA_STATUS_RESULT_0 if the result is all zeros.
+//! - \ref PKA_STATUS_BUF_UNDERFLOW if the \c length is less than the length
+//! of the result.
+//!
+//! \sa PKABigNumDivideStart()
+//
+//*****************************************************************************
+extern uint32_t PKABigNumDivideGetRemainder(uint8_t *resultBuf, uint32_t *length, uint32_t resultRemainderMemAddr);
+
+//*****************************************************************************
+//
+//! \brief Starts the comparison of two big numbers.
+//!
+//! This function starts the comparison of two big numbers pointed by
+//! \c bigNum1 and \c bigNum2.
+//!
+//! \note \c bigNum1 and \c bigNum2 must have same size.
+//!
+//! \param [in] bigNum1 is the pointer to the first big number.
+//!
+//! \param [in] bigNum2 is the pointer to the second big number.
+//!
+//! \param [in] length is the size of the big numbers in bytes.
+//!
+//!\return Returns a status code.
+//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation.
+//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing
+//! some other operation.
+//!
+//! \sa PKABigNumCmpGetResult()
+//
+//*****************************************************************************
+extern uint32_t PKABigNumCmpStart(const uint8_t *bigNum1, const uint8_t *bigNum2, uint32_t length);
+
+//*****************************************************************************
+//
+//! \brief Gets the result of the comparison operation of two big numbers.
+//!
+//! This function provides the results of the comparison of two big numbers
+//! which was started using the PKABigNumCmpStart().
+//!
+//! \return Returns a status code.
+//! - \ref PKA_STATUS_OPERATION_BUSY if the operation is in progress.
+//! - \ref PKA_STATUS_SUCCESS if the two big numbers are equal.
+//! - \ref PKA_STATUS_A_GREATER_THAN_B if the first number is greater than the second.
+//! - \ref PKA_STATUS_A_LESS_THAN_B if the first number is less than the second.
+//!
+//! \sa PKABigNumCmpStart()
+//
+//*****************************************************************************
+extern uint32_t PKABigNumCmpGetResult(void);
+
+//*****************************************************************************
+//
+//! \brief Starts a big number inverse modulo operation.
+//!
+//! This function starts the inverse modulo operation on \c bigNum
+//! using the divisor \c modulus.
+//!
+//! \param [in] bigNum is the pointer to the buffer containing the big number
+//! (dividend).
+//!
+//! \param [in] bigNumLength is the size of the \c bigNum in bytes.
+//!
+//! \param [in] modulus is the pointer to the buffer containing the divisor.
+//!
+//! \param [in] modulusLength is the size of the divisor in bytes.
+//!
+//! \param [out] resultPKAMemAddr is the pointer to the result vector location
+//! which will be set by this function.
+//!
+//!
+//!\return Returns a status code.
+//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation.
+//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing
+//! some other operation.
+//!
+//! \sa PKABigNumInvModGetResult()
+//
+//*****************************************************************************
+extern uint32_t PKABigNumInvModStart(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr);
+
+
+//*****************************************************************************
+//
+//! \brief Gets the result of the big number inverse modulo operation.
+//!
+//! This function gets the result of the big number inverse modulo operation
+//! previously started using the function PKABigNumInvModStart().
+//! The function will zero-out \c resultBuf prior to copying in the result of
+//! the inverse modulo operation.
+//!
+//! \param [out] resultBuf is the pointer to buffer where the result needs to be
+//! stored.
+//!
+//! \param [in] length is the size of the provided buffer in bytes.
+//!
+//! \param [in] resultPKAMemAddr is the address of the result location which
+//! was provided by the start function PKABigNumInvModStart().
+//!
+//! \return Returns a status code.
+//! - \ref PKA_STATUS_SUCCESS if the operation is successful.
+//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy performing
+//! the operation.
+//! - \ref PKA_STATUS_RESULT_0 if the result is all zeros.
+//! - \ref PKA_STATUS_BUF_UNDERFLOW if the length of the provided buffer is less
+//! than the result.
+//!
+//! \sa PKABigNumInvModStart()
+//
+//*****************************************************************************
+extern uint32_t PKABigNumInvModGetResult(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr);
+
+
+//*****************************************************************************
+//
+//! \brief Starts the multiplication of two big numbers.
+//!
+//! \param [in] multiplicand is the pointer to the buffer containing the big
+//! number multiplicand.
+//!
+//! \param [in] multiplicandLength is the size of the multiplicand in bytes.
+//!
+//! \param [in] multiplier is the pointer to the buffer containing the big
+//! number multiplier.
+//!
+//! \param [in] multiplierLength is the size of the multiplier in bytes.
+//!
+//! \param [out] resultPKAMemAddr is the pointer to the result vector location
+//! which will be set by this function.
+//!
+//!\return Returns a status code.
+//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation.
+//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing
+//! some other operation.
+//!
+//! \sa PKABigNumMultGetResult()
+//
+//*****************************************************************************
+extern uint32_t PKABigNumMultiplyStart(const uint8_t *multiplicand, uint32_t multiplicandLength, const uint8_t *multiplier, uint32_t multiplierLength, uint32_t *resultPKAMemAddr);
+
+
+//*****************************************************************************
+//
+//! \brief Gets the result of the big number multiplication.
+//!
+//! This function gets the result of the multiplication of two big numbers
+//! operation previously started using the function PKABigNumMultiplyStart().
+//!
+//! \param [out] resultBuf is the pointer to buffer where the result needs to be
+//! stored.
+//!
+//! \param [in, out] resultLength is the address of the variable containing the length of the
+//! buffer in bytes. After the operation, the actual length of the resultant is stored
+//! at this address.
+//!
+//! \param [in] resultPKAMemAddr is the address of the result location which
+//! was provided by the start function PKABigNumMultiplyStart().
+//!
+//! \return Returns a status code.
+//! - \ref PKA_STATUS_SUCCESS if the operation is successful.
+//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy performing
+//! the operation.
+//! - \ref PKA_STATUS_RESULT_0 if the result is all zeros.
+//! - \ref PKA_STATUS_FAILURE if the operation is not successful.
+//! - \ref PKA_STATUS_BUF_UNDERFLOW if the length of the provided buffer is less
+//! then the length of the result.
+//!
+//! \sa PKABigNumMultiplyStart()
+//
+//*****************************************************************************
+extern uint32_t PKABigNumMultGetResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr);
+
+//*****************************************************************************
+//
+//! \brief Starts the addition of two big numbers.
+//!
+//! \param [in] bigNum1 is the pointer to the buffer containing the first
+//! big number.
+//!
+//! \param [in] bigNum1Length is the size of the first big number in bytes.
+//!
+//! \param [in] bigNum2 is the pointer to the buffer containing the second
+//! big number.
+//!
+//! \param [in] bigNum2Length is the size of the second big number in bytes.
+//!
+//! \param [out] resultPKAMemAddr is the pointer to the result vector location
+//! which will be set by this function.
+//!
+//!\return Returns a status code.
+//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation.
+//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing
+//! some other operation.
+//!
+//! \sa PKABigNumAddGetResult()
+//
+//*****************************************************************************
+extern uint32_t PKABigNumAddStart(const uint8_t *bigNum1, uint32_t bigNum1Length, const uint8_t *bigNum2, uint32_t bigNum2Length, uint32_t *resultPKAMemAddr);
+
+//*****************************************************************************
+//
+//! \brief Gets the result of the addition operation on two big numbers.
+//!
+//! \param [out] resultBuf is the pointer to buffer where the result
+//! needs to be stored.
+//!
+//! \param [in, out] resultLength is the address of the variable containing
+//! the length of the buffer. After the operation the actual length of the
+//! resultant is stored at this address.
+//!
+//! \param [in] resultPKAMemAddr is the address of the result location which
+//! was provided by the start function PKABigNumAddStart().
+//!
+//!
+//! \return Returns a status code.
+//! - \ref PKA_STATUS_SUCCESS if the operation is successful.
+//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy performing
+//! the operation.
+//! - \ref PKA_STATUS_RESULT_0 if the result is all zeros.
+//! - \ref PKA_STATUS_FAILURE if the operation is not successful.
+//! - \ref PKA_STATUS_BUF_UNDERFLOW if the length of the provided buffer is less
+//! then the length of the result.
+//!
+//! \sa PKABigNumAddStart()
+//
+//*****************************************************************************
+extern uint32_t PKABigNumAddGetResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr);
+
+//*****************************************************************************
+//
+//! \brief Starts the subtraction of one big number from another.
+//!
+//! \param [in] minuend is the pointer to the buffer containing the big number
+//! to be subtracted from.
+//!
+//! \param [in] minuendLength is the size of the minuend in bytes.
+//!
+//! \param [in] subtrahend is the pointer to the buffer containing the big
+//! number to subtract from the \c minuend.
+//!
+//! \param [in] subtrahendLength is the size of the subtrahend in bytes.
+//!
+//! \param [out] resultPKAMemAddr is the pointer to the result vector location
+//! which will be set by this function.
+//!
+//!\return Returns a status code.
+//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation.
+//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing
+//! some other operation.
+//!
+//! \sa PKABigNumSubGetResult()
+//
+//*****************************************************************************
+extern uint32_t PKABigNumSubStart(const uint8_t *minuend, uint32_t minuendLength, const uint8_t *subtrahend, uint32_t subtrahendLength, uint32_t *resultPKAMemAddr);
+
+//*****************************************************************************
+//
+//! \brief Gets the result of the subtraction operation on two big numbers.
+//!
+//! \param [out] resultBuf is the pointer to buffer where the result
+//! needs to be stored.
+//!
+//! \param [in, out] resultLength is the address of the variable containing
+//! the length of the buffer. After the operation the actual length of the
+//! resultant is stored at this address.
+//!
+//! \param [in] resultPKAMemAddr is the address of the result location which
+//! was provided by the start function PKABigNumAddStart().
+//!
+//!
+//! \return Returns a status code.
+//! - \ref PKA_STATUS_SUCCESS if the operation is successful.
+//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy performing
+//! the operation.
+//! - \ref PKA_STATUS_RESULT_0 if the result is all zeros.
+//! - \ref PKA_STATUS_FAILURE if the operation is not successful.
+//! - \ref PKA_STATUS_BUF_UNDERFLOW if the length of the provided buffer is less
+//! then the length of the result.
+//!
+//! \sa PKABigNumSubStart()
+//
+//*****************************************************************************
+extern uint32_t PKABigNumSubGetResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr);
+
+//*****************************************************************************
+//
+//! \brief Starts ECC multiplication.
+//!
+//! \param [in] scalar is pointer to the buffer containing the scalar
+//! value to be multiplied.
+//!
+//! \param [in] curvePointX is the pointer to the buffer containing the
+//! X coordinate of the elliptic curve point to be multiplied.
+//! The point must be on the given curve.
+//!
+//! \param [in] curvePointY is the pointer to the buffer containing the
+//! Y coordinate of the elliptic curve point to be multiplied.
+//! The point must be on the given curve.
+//!
+//! \param [in] prime is the prime of the curve.
+//!
+//! \param [in] a is the a constant of the curve when the curve equation is expressed
+//! in short Weierstrass form (y^3 = x^2 + a*x + b).
+//!
+//! \param [in] b is the b constant of the curve when the curve equation is expressed
+//! in short Weierstrass form (y^3 = x^2 + a*x + b).
+//!
+//! \param [in] length is the length of the curve parameters in bytes.
+//!
+//! \param [out] resultPKAMemAddr is the pointer to the result vector location
+//! which will be set by this function.
+//!
+//!\return Returns a status code.
+//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation.
+//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing
+//! some other operation.
+//!
+//! \sa PKAEccMultiplyGetResult()
+//
+//*****************************************************************************
+extern uint32_t PKAEccMultiplyStart(const uint8_t *scalar,
+ const uint8_t *curvePointX,
+ const uint8_t *curvePointY,
+ const uint8_t *prime,
+ const uint8_t *a,
+ const uint8_t *b,
+ uint32_t length,
+ uint32_t *resultPKAMemAddr);
+
+//*****************************************************************************
+//
+//! \brief Starts ECC Montgomery multiplication.
+//!
+//! \param [in] scalar is pointer to the buffer containing the scalar
+//! value to be multiplied.
+//!
+//! \param [in] curvePointX is the pointer to the buffer containing the
+//! X coordinate of the elliptic curve point to be multiplied.
+//! The point must be on the given curve.
+//!
+//! \param [in] prime is the prime of the curve.
+//!
+//! \param [in] a is the a constant of the curve when the curve equation is expressed
+//! in short Weierstrass form (y^3 = x^2 + a*x + b).
+//!
+//! \param [in] length is the length of the curve parameters in bytes.
+//!
+//! \param [out] resultPKAMemAddr is the pointer to the result vector location
+//! which will be set by this function.
+//!
+//!\return Returns a status code.
+//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation.
+//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing
+//! some other operation.
+//!
+//! \sa PKAEccMultiplyGetResult()
+//
+//*****************************************************************************
+extern uint32_t PKAEccMontgomeryMultiplyStart(const uint8_t *scalar,
+ const uint8_t *curvePointX,
+ const uint8_t *prime,
+ const uint8_t *a,
+ uint32_t length,
+ uint32_t *resultPKAMemAddr);
+
+//*****************************************************************************
+//
+//! \brief Gets the result of ECC multiplication
+//!
+//! This function gets the result of ECC point multiplication operation on the
+//! EC point and the scalar value, previously started using the function
+//! PKAEccMultiplyStart().
+//!
+//! \param [out] curvePointX is the pointer to the structure where the X coordinate
+//! of the resultant EC point will be stored.
+//!
+//! \param [out] curvePointY is the pointer to the structure where the Y coordinate
+//! of the resultant EC point will be stored.
+//!
+//! \param [in] resultPKAMemAddr is the address of the result location which
+//! was provided by the start function PKAEccMultiplyStart().
+//!
+//! \param [in] length is the length of the curve parameters in bytes.
+//!
+//! \return Returns a status code.
+//! - \ref PKA_STATUS_SUCCESS if the operation is successful.
+//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy performing
+//! the operation.
+//! - \ref PKA_STATUS_RESULT_0 if the result is all zeros.
+//! - \ref PKA_STATUS_FAILURE if the operation is not successful.
+//!
+//! \sa PKAEccMultiplyStart()
+//
+//*****************************************************************************
+extern uint32_t PKAEccMultiplyGetResult(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length);
+
+//*****************************************************************************
+//
+//! \brief Starts the ECC addition.
+//!
+//! \param [in] curvePoint1X is the pointer to the buffer containing the
+//! X coordinate of the first elliptic curve point to be added.
+//! The point must be on the given curve.
+//!
+//! \param [in] curvePoint1Y is the pointer to the buffer containing the
+//! Y coordinate of the first elliptic curve point to be added.
+//! The point must be on the given curve.
+//!
+//! \param [in] curvePoint2X is the pointer to the buffer containing the
+//! X coordinate of the second elliptic curve point to be added.
+//! The point must be on the given curve.
+//!
+//! \param [in] curvePoint2Y is the pointer to the buffer containing the
+//! Y coordinate of the second elliptic curve point to be added.
+//! The point must be on the given curve.
+//!
+//! \param [in] prime is the prime of the curve.
+//!
+//! \param [in] a is the a constant of the curve when the curve equation is expressed
+//! in short Weierstrass form (y^3 = x^2 + a*x + b).
+//!
+//! \param [in] length is the length of the curve parameters in bytes.
+//!
+//! \param [out] resultPKAMemAddr is the pointer to the result vector location
+//! which will be set by this function.
+//!
+//!\return Returns a status code.
+//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation.
+//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing
+//! some other operation.
+//!
+//! \sa PKAEccAddGetResult()
+//
+//*****************************************************************************
+extern uint32_t PKAEccAddStart(const uint8_t *curvePoint1X,
+ const uint8_t *curvePoint1Y,
+ const uint8_t *curvePoint2X,
+ const uint8_t *curvePoint2Y,
+ const uint8_t *prime,
+ const uint8_t *a,
+ uint32_t length,
+ uint32_t *resultPKAMemAddr);
+
+//*****************************************************************************
+//
+//! \brief Gets the result of the ECC addition
+//!
+//! This function gets the result of ECC point addition operation on the
+//! on the two given EC points, previously started using the function
+//! PKAEccAddStart().
+//!
+//! \param [out] curvePointX is the pointer to the structure where the X coordinate
+//! of the resultant EC point will be stored.
+//!
+//! \param [out] curvePointY is the pointer to the structure where the Y coordinate
+//! of the resultant EC point will be stored.
+//!
+//! \param [in] resultPKAMemAddr is the address of the result location which
+//! was provided by the start function PKAEccAddGetResult().
+//!
+//! \param [in] length is the length of the curve parameters in bytes.
+//!
+//! \return Returns a status code.
+//! - \ref PKA_STATUS_SUCCESS if the operation is successful.
+//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy performing the operation.
+//! - \ref PKA_STATUS_RESULT_0 if the result is all zeros.
+//! - \ref PKA_STATUS_FAILURE if the operation is not successful.
+//!
+//! \sa PKAEccAddStart()
+//
+//*****************************************************************************
+extern uint32_t PKAEccAddGetResult(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length);
+
+
+//*****************************************************************************
+//
+//! \brief Begins the validation of a public key against a Short-Weierstrass curve
+//!
+//! This function validates a public key against a curve.
+//! After performing multiple smaller PKA operations in polling mode,
+//! it starts an ECC scalar multiplication.
+//!
+//! The function verifies that:
+//! - X and Y are in the range [1, prime - 1]
+//! - The point is not the point at infinity
+//! - X and Y satisfy the Short-Weierstrass curve equation Y^2 = X^3 + a*X + b mod P
+//! - Multiplying the point by the order of the curve yields the point at infinity
+//!
+//! \param [in] curvePointX is the pointer to the buffer containing the
+//! X coordinate of the elliptic curve point to verify.
+//!
+//! \param [in] curvePointY is the pointer to the buffer containing the
+//! Y coordinate of the elliptic curve point to verify.
+//!
+//! \param [in] prime is the prime of the curve.
+//!
+//! \param [in] a is the a constant of the curve when the curve equation is expressed
+//! in Short-Weierstrass form (y^3 = x^2 + a*x + b).
+//!
+//! \param [in] b is the b constant of the curve when the curve equation is expressed
+//! in Short-Weierstrass form (y^3 = x^2 + a*x + b).
+//!
+//! \param [in] order is the order of the curve.
+//!
+//! \param [in] length is the length of the curve parameters in bytes.
+//!
+//! \return Returns a status code.
+//! - \ref PKA_STATUS_SUCCESS if the operation is successful.
+//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy performing the operation.
+//! - \ref PKA_STATUS_FAILURE if the operation is not successful.
+//! - \ref PKA_STATUS_X_ZERO if X is zero.
+//! - \ref PKA_STATUS_Y_ZERO if Y is zero.
+//! - \ref PKA_STATUS_X_LARGER_THAN_PRIME if X is larger than the curve prime
+//! - \ref PKA_STATUS_Y_LARGER_THAN_PRIME if Y is larger than the curve prime
+//! - \ref PKA_STATUS_POINT_NOT_ON_CURVE if X and Y do not satisfy the curve equation
+//!
+//! \sa PKAEccVerifyPublicKeyGetResult()
+//
+//*****************************************************************************
+extern uint32_t PKAEccVerifyPublicKeyWeierstrassStart(const uint8_t *curvePointX,
+ const uint8_t *curvePointY,
+ const uint8_t *prime,
+ const uint8_t *a,
+ const uint8_t *b,
+ const uint8_t *order,
+ uint32_t length);
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// Redirect to implementation in ROM when available.
+//
+//*****************************************************************************
+#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
+ #include "../driverlib/rom.h"
+ #ifdef ROM_PKAClearPkaRam
+ #undef PKAClearPkaRam
+ #define PKAClearPkaRam ROM_PKAClearPkaRam
+ #endif
+ #ifdef ROM_PKAGetOpsStatus
+ #undef PKAGetOpsStatus
+ #define PKAGetOpsStatus ROM_PKAGetOpsStatus
+ #endif
+ #ifdef ROM_PKAArrayAllZeros
+ #undef PKAArrayAllZeros
+ #define PKAArrayAllZeros ROM_PKAArrayAllZeros
+ #endif
+ #ifdef ROM_PKAZeroOutArray
+ #undef PKAZeroOutArray
+ #define PKAZeroOutArray ROM_PKAZeroOutArray
+ #endif
+ #ifdef ROM_PKABigNumModStart
+ #undef PKABigNumModStart
+ #define PKABigNumModStart ROM_PKABigNumModStart
+ #endif
+ #ifdef ROM_PKABigNumModGetResult
+ #undef PKABigNumModGetResult
+ #define PKABigNumModGetResult ROM_PKABigNumModGetResult
+ #endif
+ #ifdef ROM_PKABigNumDivideStart
+ #undef PKABigNumDivideStart
+ #define PKABigNumDivideStart ROM_PKABigNumDivideStart
+ #endif
+ #ifdef ROM_PKABigNumDivideGetQuotient
+ #undef PKABigNumDivideGetQuotient
+ #define PKABigNumDivideGetQuotient ROM_PKABigNumDivideGetQuotient
+ #endif
+ #ifdef ROM_PKABigNumDivideGetRemainder
+ #undef PKABigNumDivideGetRemainder
+ #define PKABigNumDivideGetRemainder ROM_PKABigNumDivideGetRemainder
+ #endif
+ #ifdef ROM_PKABigNumCmpStart
+ #undef PKABigNumCmpStart
+ #define PKABigNumCmpStart ROM_PKABigNumCmpStart
+ #endif
+ #ifdef ROM_PKABigNumCmpGetResult
+ #undef PKABigNumCmpGetResult
+ #define PKABigNumCmpGetResult ROM_PKABigNumCmpGetResult
+ #endif
+ #ifdef ROM_PKABigNumInvModStart
+ #undef PKABigNumInvModStart
+ #define PKABigNumInvModStart ROM_PKABigNumInvModStart
+ #endif
+ #ifdef ROM_PKABigNumInvModGetResult
+ #undef PKABigNumInvModGetResult
+ #define PKABigNumInvModGetResult ROM_PKABigNumInvModGetResult
+ #endif
+ #ifdef ROM_PKABigNumMultiplyStart
+ #undef PKABigNumMultiplyStart
+ #define PKABigNumMultiplyStart ROM_PKABigNumMultiplyStart
+ #endif
+ #ifdef ROM_PKABigNumMultGetResult
+ #undef PKABigNumMultGetResult
+ #define PKABigNumMultGetResult ROM_PKABigNumMultGetResult
+ #endif
+ #ifdef ROM_PKABigNumAddStart
+ #undef PKABigNumAddStart
+ #define PKABigNumAddStart ROM_PKABigNumAddStart
+ #endif
+ #ifdef ROM_PKABigNumAddGetResult
+ #undef PKABigNumAddGetResult
+ #define PKABigNumAddGetResult ROM_PKABigNumAddGetResult
+ #endif
+ #ifdef ROM_PKABigNumSubStart
+ #undef PKABigNumSubStart
+ #define PKABigNumSubStart ROM_PKABigNumSubStart
+ #endif
+ #ifdef ROM_PKABigNumSubGetResult
+ #undef PKABigNumSubGetResult
+ #define PKABigNumSubGetResult ROM_PKABigNumSubGetResult
+ #endif
+ #ifdef ROM_PKAEccMultiplyStart
+ #undef PKAEccMultiplyStart
+ #define PKAEccMultiplyStart ROM_PKAEccMultiplyStart
+ #endif
+ #ifdef ROM_PKAEccMontgomeryMultiplyStart
+ #undef PKAEccMontgomeryMultiplyStart
+ #define PKAEccMontgomeryMultiplyStart ROM_PKAEccMontgomeryMultiplyStart
+ #endif
+ #ifdef ROM_PKAEccMultiplyGetResult
+ #undef PKAEccMultiplyGetResult
+ #define PKAEccMultiplyGetResult ROM_PKAEccMultiplyGetResult
+ #endif
+ #ifdef ROM_PKAEccAddStart
+ #undef PKAEccAddStart
+ #define PKAEccAddStart ROM_PKAEccAddStart
+ #endif
+ #ifdef ROM_PKAEccAddGetResult
+ #undef PKAEccAddGetResult
+ #define PKAEccAddGetResult ROM_PKAEccAddGetResult
+ #endif
+ #ifdef ROM_PKAEccVerifyPublicKeyWeierstrassStart
+ #undef PKAEccVerifyPublicKeyWeierstrassStart
+ #define PKAEccVerifyPublicKeyWeierstrassStart ROM_PKAEccVerifyPublicKeyWeierstrassStart
+ #endif
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __PKA_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/pka_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/pka_doc.h
new file mode 100644
index 0000000..c780a53
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/pka_doc.h
@@ -0,0 +1,80 @@
+/******************************************************************************
+* Filename: pka_doc.h
+* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017)
+* Revision: 49096
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+//! \addtogroup pka_api
+//! @{
+//! \section sec_pka Introduction
+//!
+//! The PKA (Public Key Accelerator) API provides access to the Large Number
+//! Engine (LNME). The LNME allows for efficient math operations on numbers
+//! larger than those that fit within the ALU of the system CPU. It is significantly faster
+//! to perform these operations using the LNME than implementing the same
+//! functionality in software using regular word-wise math operations. While the
+//! LNME runs in the background, the system CPU may perform other operations
+//! or be turned off.
+//!
+//! The LNME supports both primitive math operations and serialized primitive
+//! operations (sequencer operations).
+//! - Addition
+//! - Multiplication
+//! - Comparison
+//! - Modulo
+//! - Inverse Modulo
+//! - ECC Point Addition (including point doubling)
+//! - ECC Scalar Multiplication
+//!
+//! These primitives and sequencer operations can be used to implement various
+//! public key encryption schemes.
+//! It is possible to implement the following schemes using the operations mentioned above:
+//! - RSA encryption and decryption
+//! - RSA sign and verify
+//! - DHE (Diffie-Hellman Key Exchange)
+//! - ECDH (Elliptic Curve Diffie-Hellman Key Exchange)
+//! - ECDSA (Elliptic Curve Digital Signature Algorithm)
+//! - ECIES (Elliptic Curve Integrated Encryption Scheme)
+//!
+//! The DriverLib PKA functions copy the relevant parameters into the dedicated
+//! PKA RAM. The LNME requires these parameters be present and correctly
+//! formatted in the PKA RAM and not system RAM. They are copied word-wise as
+//! the PKA RAM does not support byte-wise access. The CPU handles the alignment differences
+//! during the memory copy operation. Forcing buffer alignment in system RAM results
+//! in a significant speedup of the copy operation compared to unaligned buffers.
+//!
+//! When the operation completes, the result is copied back into
+//! a buffer in system RAM specified by the application. The PKA RAM is then cleared
+//! to prevent sensitive keying material from remaining in PKA RAM.
+//!
+//!
+//! @}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/prcm.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/prcm.c
new file mode 100644
index 0000000..e81df8f
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/prcm.c
@@ -0,0 +1,647 @@
+/******************************************************************************
+* Filename: prcm.c
+* Revised: 2018-10-18 17:33:32 +0200 (Thu, 18 Oct 2018)
+* Revision: 52954
+*
+* Description: Driver for the PRCM.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "prcm.h"
+
+//*****************************************************************************
+//
+// Handle support for DriverLib in ROM:
+// This section will undo prototype renaming made in the header file
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #undef PRCMInfClockConfigureSet
+ #define PRCMInfClockConfigureSet NOROM_PRCMInfClockConfigureSet
+ #undef PRCMInfClockConfigureGet
+ #define PRCMInfClockConfigureGet NOROM_PRCMInfClockConfigureGet
+ #undef PRCMAudioClockConfigSet
+ #define PRCMAudioClockConfigSet NOROM_PRCMAudioClockConfigSet
+ #undef PRCMAudioClockConfigSetOverride
+ #define PRCMAudioClockConfigSetOverride NOROM_PRCMAudioClockConfigSetOverride
+ #undef PRCMAudioClockInternalSource
+ #define PRCMAudioClockInternalSource NOROM_PRCMAudioClockInternalSource
+ #undef PRCMAudioClockExternalSource
+ #define PRCMAudioClockExternalSource NOROM_PRCMAudioClockExternalSource
+ #undef PRCMPowerDomainOn
+ #define PRCMPowerDomainOn NOROM_PRCMPowerDomainOn
+ #undef PRCMPowerDomainOff
+ #define PRCMPowerDomainOff NOROM_PRCMPowerDomainOff
+ #undef PRCMPeripheralRunEnable
+ #define PRCMPeripheralRunEnable NOROM_PRCMPeripheralRunEnable
+ #undef PRCMPeripheralRunDisable
+ #define PRCMPeripheralRunDisable NOROM_PRCMPeripheralRunDisable
+ #undef PRCMPeripheralSleepEnable
+ #define PRCMPeripheralSleepEnable NOROM_PRCMPeripheralSleepEnable
+ #undef PRCMPeripheralSleepDisable
+ #define PRCMPeripheralSleepDisable NOROM_PRCMPeripheralSleepDisable
+ #undef PRCMPeripheralDeepSleepEnable
+ #define PRCMPeripheralDeepSleepEnable NOROM_PRCMPeripheralDeepSleepEnable
+ #undef PRCMPeripheralDeepSleepDisable
+ #define PRCMPeripheralDeepSleepDisable NOROM_PRCMPeripheralDeepSleepDisable
+ #undef PRCMPowerDomainStatus
+ #define PRCMPowerDomainStatus NOROM_PRCMPowerDomainStatus
+ #undef PRCMDeepSleep
+ #define PRCMDeepSleep NOROM_PRCMDeepSleep
+#endif
+
+
+//*****************************************************************************
+//
+// Arrays that maps the "peripheral set" number (which is stored in
+// bits[11:8] of the PRCM_PERIPH_* defines) to the PRCM register that
+// contains the relevant bit for that peripheral.
+//
+//*****************************************************************************
+
+// Run mode registers
+static const uint32_t g_pui32RCGCRegs[] =
+{
+ PRCM_O_GPTCLKGR , // Index 0
+ PRCM_O_SSICLKGR , // Index 1
+ PRCM_O_UARTCLKGR , // Index 2
+ PRCM_O_I2CCLKGR , // Index 3
+ PRCM_O_SECDMACLKGR , // Index 4
+ PRCM_O_GPIOCLKGR , // Index 5
+ PRCM_O_I2SCLKGR // Index 6
+};
+
+// Sleep mode registers
+static const uint32_t g_pui32SCGCRegs[] =
+{
+ PRCM_O_GPTCLKGS , // Index 0
+ PRCM_O_SSICLKGS , // Index 1
+ PRCM_O_UARTCLKGS , // Index 2
+ PRCM_O_I2CCLKGS , // Index 3
+ PRCM_O_SECDMACLKGS , // Index 4
+ PRCM_O_GPIOCLKGS , // Index 5
+ PRCM_O_I2SCLKGS // Index 6
+};
+
+// Deep sleep mode registers
+static const uint32_t g_pui32DCGCRegs[] =
+{
+ PRCM_O_GPTCLKGDS , // Index 0
+ PRCM_O_SSICLKGDS , // Index 1
+ PRCM_O_UARTCLKGDS , // Index 2
+ PRCM_O_I2CCLKGDS , // Index 3
+ PRCM_O_SECDMACLKGDS , // Index 4
+ PRCM_O_GPIOCLKGDS , // Index 5
+ PRCM_O_I2SCLKGDS // Index 6
+};
+
+//*****************************************************************************
+//
+// This macro extracts the array index out of the peripheral number
+//
+//*****************************************************************************
+#define PRCM_PERIPH_INDEX(a) (((a) >> 8) & 0xf)
+
+//*****************************************************************************
+//
+// This macro extracts the peripheral instance number and generates bit mask
+//
+//*****************************************************************************
+#define PRCM_PERIPH_MASKBIT(a) (0x00000001 << ((a) & 0x1f))
+
+
+//*****************************************************************************
+//
+// Configure the infrastructure clock.
+//
+//*****************************************************************************
+void
+PRCMInfClockConfigureSet(uint32_t ui32ClkDiv, uint32_t ui32PowerMode)
+{
+ uint32_t ui32Divisor;
+
+ // Check the arguments.
+ ASSERT((ui32ClkDiv == PRCM_CLOCK_DIV_1) ||
+ (ui32ClkDiv == PRCM_CLOCK_DIV_2) ||
+ (ui32ClkDiv == PRCM_CLOCK_DIV_8) ||
+ (ui32ClkDiv == PRCM_CLOCK_DIV_32));
+ ASSERT((ui32PowerMode == PRCM_RUN_MODE) ||
+ (ui32PowerMode == PRCM_SLEEP_MODE) ||
+ (ui32PowerMode == PRCM_DEEP_SLEEP_MODE));
+
+ ui32Divisor = 0;
+
+ // Find the correct division factor.
+ if(ui32ClkDiv == PRCM_CLOCK_DIV_1)
+ {
+ ui32Divisor = 0x0;
+ }
+ else if(ui32ClkDiv == PRCM_CLOCK_DIV_2)
+ {
+ ui32Divisor = 0x1;
+ }
+ else if(ui32ClkDiv == PRCM_CLOCK_DIV_8)
+ {
+ ui32Divisor = 0x2;
+ }
+ else if(ui32ClkDiv == PRCM_CLOCK_DIV_32)
+ {
+ ui32Divisor = 0x3;
+ }
+
+ // Determine the correct power mode set the division factor accordingly.
+ if(ui32PowerMode == PRCM_RUN_MODE)
+ {
+ HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVR) = ui32Divisor;
+ }
+ else if(ui32PowerMode == PRCM_SLEEP_MODE)
+ {
+ HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVS) = ui32Divisor;
+ }
+ else if(ui32PowerMode == PRCM_DEEP_SLEEP_MODE)
+ {
+ HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVDS) = ui32Divisor;
+ }
+}
+
+//*****************************************************************************
+//
+// Use this function to get the infrastructure clock configuration
+//
+//*****************************************************************************
+uint32_t
+PRCMInfClockConfigureGet(uint32_t ui32PowerMode)
+{
+ uint32_t ui32ClkDiv;
+ uint32_t ui32Divisor;
+
+ // Check the arguments.
+ ASSERT((ui32PowerMode == PRCM_RUN_MODE) ||
+ (ui32PowerMode == PRCM_SLEEP_MODE) ||
+ (ui32PowerMode == PRCM_DEEP_SLEEP_MODE));
+
+ ui32ClkDiv = 0;
+ ui32Divisor = 0;
+
+ // Determine the correct power mode.
+ if(ui32PowerMode == PRCM_RUN_MODE)
+ {
+ ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVR);
+ }
+ else if(ui32PowerMode == PRCM_SLEEP_MODE)
+ {
+ ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVS);
+ }
+ else if(ui32PowerMode == PRCM_DEEP_SLEEP_MODE)
+ {
+ ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVDS);
+ }
+
+ // Find the correct division factor.
+ if(ui32ClkDiv == 0x0)
+ {
+ ui32Divisor = PRCM_CLOCK_DIV_1;
+ }
+ else if(ui32ClkDiv == 0x1)
+ {
+ ui32Divisor = PRCM_CLOCK_DIV_2;
+ }
+ else if(ui32ClkDiv == 0x2)
+ {
+ ui32Divisor = PRCM_CLOCK_DIV_8;
+ }
+ else if(ui32ClkDiv == 0x3)
+ {
+ ui32Divisor = PRCM_CLOCK_DIV_32;
+ }
+
+ // Return the clock division factor.
+ return ui32Divisor;
+}
+
+
+//*****************************************************************************
+//
+// Configure the audio clock generation
+//
+//*****************************************************************************
+void
+PRCMAudioClockConfigSet(uint32_t ui32ClkConfig, uint32_t ui32SampleRate)
+{
+ uint32_t ui32Reg;
+ uint32_t ui32MstDiv;
+ uint32_t ui32BitDiv;
+ uint32_t ui32WordDiv;
+
+ // Check the arguments.
+ ASSERT(!(ui32ClkConfig & (PRCM_I2SCLKCTL_WCLK_PHASE_M | PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M)));
+ ASSERT((ui32SampleRate == I2S_SAMPLE_RATE_16K) ||
+ (ui32SampleRate == I2S_SAMPLE_RATE_24K) ||
+ (ui32SampleRate == I2S_SAMPLE_RATE_32K) ||
+ (ui32SampleRate == I2S_SAMPLE_RATE_48K));
+
+ ui32MstDiv = 0;
+ ui32BitDiv = 0;
+ ui32WordDiv = 0;
+
+ // Make sure the audio clock generation is disabled before reconfiguring.
+ PRCMAudioClockDisable();
+
+ // Define the clock division factors for the audio interface.
+ switch(ui32SampleRate)
+ {
+ case I2S_SAMPLE_RATE_16K :
+ ui32MstDiv = 6;
+ ui32BitDiv = 60;
+ ui32WordDiv = 25;
+ break;
+ case I2S_SAMPLE_RATE_24K :
+ ui32MstDiv = 4;
+ ui32BitDiv = 40;
+ ui32WordDiv = 25;
+ break;
+ case I2S_SAMPLE_RATE_32K :
+ ui32MstDiv = 3;
+ ui32BitDiv = 30;
+ ui32WordDiv = 25;
+ break;
+ case I2S_SAMPLE_RATE_48K :
+ ui32MstDiv = 2;
+ ui32BitDiv = 20;
+ ui32WordDiv = 25;
+ break;
+ }
+
+ // Make sure to compensate the Frame clock division factor if using single
+ // phase format.
+ if((ui32ClkConfig & PRCM_I2SCLKCTL_WCLK_PHASE_M) == PRCM_WCLK_SINGLE_PHASE)
+ {
+ ui32WordDiv -= 1;
+ }
+
+ // Write the clock division factors.
+ HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv;
+ HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv;
+ HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv;
+
+ // Configure the Word clock format and polarity.
+ ui32Reg = HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) & ~(PRCM_I2SCLKCTL_WCLK_PHASE_M |
+ PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M);
+ HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = ui32Reg | ui32ClkConfig;
+}
+
+//*****************************************************************************
+//
+// Configure the audio clock generation with manual setting of clock divider.
+//
+//*****************************************************************************
+void
+PRCMAudioClockConfigSetOverride(uint32_t ui32ClkConfig, uint32_t ui32MstDiv,
+ uint32_t ui32BitDiv, uint32_t ui32WordDiv)
+{
+ uint32_t ui32Reg;
+
+ // Check the arguments.
+ ASSERT(!(ui32ClkConfig & (PRCM_I2SCLKCTL_WCLK_PHASE_M | PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M)));
+
+ // Make sure the audio clock generation is disabled before reconfiguring.
+ PRCMAudioClockDisable();
+
+ // Make sure to compensate the Frame clock division factor if using single
+ // phase format.
+ if((ui32ClkConfig & PRCM_I2SCLKCTL_WCLK_PHASE_M) == PRCM_WCLK_SINGLE_PHASE)
+ {
+ ui32WordDiv -= 1;
+ }
+
+ // Write the clock division factors.
+ HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv;
+ HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv;
+ HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv;
+
+ // Configure the Word clock format and polarity.
+ ui32Reg = HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) & ~(PRCM_I2SCLKCTL_WCLK_PHASE_M |
+ PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M);
+ HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = ui32Reg | ui32ClkConfig;
+}
+
+//*****************************************************************************
+//
+// Configure the audio clocks for I2S module
+//
+//*****************************************************************************
+void
+PRCMAudioClockConfigOverride(uint8_t ui8SamplingEdge,
+ uint8_t ui8WCLKPhase,
+ uint32_t ui32MstDiv,
+ uint32_t ui32BitDiv,
+ uint32_t ui32WordDiv)
+{
+ // Check the arguments.
+ ASSERT( ui8BitsPerSample == PRCM_WCLK_SINGLE_PHASE
+ || ui8BitsPerSample == PRCM_WCLK_DUAL_PHASE
+ || ui8BitsPerSample == PRCM_WCLK_USER_DEF);
+
+ // Make sure the audio clock generation is disabled before reconfiguring.
+ PRCMAudioClockDisable();
+
+ // Make sure to compensate the Frame clock division factor if using single
+ // phase format.
+ if((ui8WCLKPhase) == PRCM_WCLK_SINGLE_PHASE)
+ {
+ ui32WordDiv -= 1;
+ }
+
+ // Write the clock division factors.
+ HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv;
+ HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv;
+ HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv;
+
+ // Configure the Word clock format and polarity and enable it.
+ HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = (ui8SamplingEdge << PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_S) |
+ (ui8WCLKPhase << PRCM_I2SCLKCTL_WCLK_PHASE_S ) |
+ (1 << PRCM_I2SCLKCTL_EN_S );
+}
+
+//*****************************************************************************
+//
+// Configure the clocks as "internally generated".
+//
+//*****************************************************************************
+void PRCMAudioClockInternalSource(void)
+{
+ HWREGBITW(PRCM_BASE + PRCM_O_I2SBCLKSEL, PRCM_I2SBCLKSEL_SRC_BITN) = 1;
+}
+
+//*****************************************************************************
+//
+// Configure the clocks as "externally generated".
+//
+//*****************************************************************************
+void PRCMAudioClockExternalSource(void)
+{
+ HWREGBITW(PRCM_BASE + PRCM_O_I2SBCLKSEL, PRCM_I2SBCLKSEL_SRC_BITN) = 0;
+}
+
+//*****************************************************************************
+//
+// Turn power on in power domains in the MCU domain
+//
+//*****************************************************************************
+void
+PRCMPowerDomainOn(uint32_t ui32Domains)
+{
+ // Check the arguments.
+ ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) ||
+ (ui32Domains & PRCM_DOMAIN_SERIAL) ||
+ (ui32Domains & PRCM_DOMAIN_PERIPH) ||
+ (ui32Domains & PRCM_DOMAIN_CPU) ||
+ (ui32Domains & PRCM_DOMAIN_VIMS));
+
+ // Assert the request to power on the right domains.
+ if(ui32Domains & PRCM_DOMAIN_RFCORE)
+ {
+ HWREG(PRCM_BASE + PRCM_O_PDCTL0RFC ) = 1;
+ }
+ if(ui32Domains & PRCM_DOMAIN_SERIAL)
+ {
+ HWREG(PRCM_BASE + PRCM_O_PDCTL0SERIAL) = 1;
+ }
+ if(ui32Domains & PRCM_DOMAIN_PERIPH)
+ {
+ HWREG(PRCM_BASE + PRCM_O_PDCTL0PERIPH) = 1;
+ }
+ if(ui32Domains & PRCM_DOMAIN_VIMS)
+ {
+ HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS ) = 1;
+ }
+ if(ui32Domains & PRCM_DOMAIN_CPU)
+ {
+ HWREG(PRCM_BASE + PRCM_O_PDCTL1CPU ) = 1;
+ }
+}
+
+//*****************************************************************************
+//
+// Turn off a specific power domain
+//
+//*****************************************************************************
+void
+PRCMPowerDomainOff(uint32_t ui32Domains)
+{
+ // Check the arguments.
+ ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) ||
+ (ui32Domains & PRCM_DOMAIN_SERIAL) ||
+ (ui32Domains & PRCM_DOMAIN_PERIPH) ||
+ (ui32Domains & PRCM_DOMAIN_CPU) ||
+ (ui32Domains & PRCM_DOMAIN_VIMS));
+
+ // Assert the request to power off the right domains.
+ if(ui32Domains & PRCM_DOMAIN_RFCORE)
+ {
+ HWREG(PRCM_BASE + PRCM_O_PDCTL0RFC ) = 0;
+ }
+ if(ui32Domains & PRCM_DOMAIN_SERIAL)
+ {
+ HWREG(PRCM_BASE + PRCM_O_PDCTL0SERIAL) = 0;
+ }
+ if(ui32Domains & PRCM_DOMAIN_PERIPH)
+ {
+ HWREG(PRCM_BASE + PRCM_O_PDCTL0PERIPH) = 0;
+ }
+ if(ui32Domains & PRCM_DOMAIN_VIMS)
+ {
+ // Write bits ui32Domains[17:16] to the VIMS_MODE alias register.
+ // PRCM_DOMAIN_VIMS sets VIMS_MODE=0b00, PRCM_DOMAIN_VIMS_OFF_NO_WAKEUP sets VIMS_MODE=0b10.
+ ASSERT(!(ui32Domains & 0x00010000));
+ HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS ) = ( ui32Domains >> 16 ) & 3;
+ }
+ if(ui32Domains & PRCM_DOMAIN_CPU)
+ {
+ HWREG(PRCM_BASE + PRCM_O_PDCTL1CPU ) = 0;
+ }
+}
+
+//*****************************************************************************
+//
+// Enables a peripheral in Run mode
+//
+//*****************************************************************************
+void
+PRCMPeripheralRunEnable(uint32_t ui32Peripheral)
+{
+ // Check the arguments.
+ ASSERT(PRCMPeripheralValid(ui32Peripheral));
+
+ // Enable module in Run Mode.
+ HWREG(PRCM_BASE + g_pui32RCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |=
+ PRCM_PERIPH_MASKBIT(ui32Peripheral);
+}
+
+//*****************************************************************************
+//
+// Disables a peripheral in Run mode
+//
+//*****************************************************************************
+void
+PRCMPeripheralRunDisable(uint32_t ui32Peripheral)
+{
+ // Check the arguments.
+ ASSERT(PRCMPeripheralValid(ui32Peripheral));
+
+ // Disable module in Run Mode.
+ HWREG(PRCM_BASE + g_pui32RCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &=
+ ~PRCM_PERIPH_MASKBIT(ui32Peripheral);
+}
+
+//*****************************************************************************
+//
+// Enables a peripheral in sleep mode
+//
+//*****************************************************************************
+void
+PRCMPeripheralSleepEnable(uint32_t ui32Peripheral)
+{
+ // Check the arguments.
+ ASSERT(PRCMPeripheralValid(ui32Peripheral));
+
+ // Enable this peripheral in sleep mode.
+ HWREG(PRCM_BASE + g_pui32SCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |=
+ PRCM_PERIPH_MASKBIT(ui32Peripheral);
+}
+
+//*****************************************************************************
+//
+// Disables a peripheral in sleep mode
+//
+//*****************************************************************************
+void
+PRCMPeripheralSleepDisable(uint32_t ui32Peripheral)
+{
+ // Check the arguments.
+ ASSERT(PRCMPeripheralValid(ui32Peripheral));
+
+ // Disable this peripheral in sleep mode
+ HWREG(PRCM_BASE + g_pui32SCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &=
+ ~PRCM_PERIPH_MASKBIT(ui32Peripheral);
+}
+
+//*****************************************************************************
+//
+// Enables a peripheral in deep-sleep mode
+//
+//*****************************************************************************
+void
+PRCMPeripheralDeepSleepEnable(uint32_t ui32Peripheral)
+{
+ // Check the arguments.
+ ASSERT(PRCMPeripheralValid(ui32Peripheral));
+
+ // Enable this peripheral in deep-sleep mode.
+ HWREG(PRCM_BASE + g_pui32DCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |=
+ PRCM_PERIPH_MASKBIT(ui32Peripheral);
+}
+
+//*****************************************************************************
+//
+// Disables a peripheral in deep-sleep mode
+//
+//*****************************************************************************
+void
+PRCMPeripheralDeepSleepDisable(uint32_t ui32Peripheral)
+{
+ // Check the arguments.
+ ASSERT(PRCMPeripheralValid(ui32Peripheral));
+
+ // Disable this peripheral in Deep Sleep mode.
+ HWREG(PRCM_BASE + g_pui32DCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &=
+ ~PRCM_PERIPH_MASKBIT(ui32Peripheral);
+}
+
+//*****************************************************************************
+//
+// Get the status for a specific power domain
+//
+//*****************************************************************************
+uint32_t
+PRCMPowerDomainStatus(uint32_t ui32Domains)
+{
+ bool bStatus;
+ uint32_t ui32StatusRegister0;
+ uint32_t ui32StatusRegister1;
+
+ // Check the arguments.
+ ASSERT((ui32Domains & (PRCM_DOMAIN_RFCORE |
+ PRCM_DOMAIN_SERIAL |
+ PRCM_DOMAIN_PERIPH)));
+
+ bStatus = true;
+ ui32StatusRegister0 = HWREG(PRCM_BASE + PRCM_O_PDSTAT0);
+ ui32StatusRegister1 = HWREG(PRCM_BASE + PRCM_O_PDSTAT1);
+
+ // Return the correct power status.
+ if(ui32Domains & PRCM_DOMAIN_RFCORE)
+ {
+ bStatus = bStatus &&
+ ((ui32StatusRegister0 & PRCM_PDSTAT0_RFC_ON) ||
+ (ui32StatusRegister1 & PRCM_PDSTAT1_RFC_ON));
+ }
+ if(ui32Domains & PRCM_DOMAIN_SERIAL)
+ {
+ bStatus = bStatus && (ui32StatusRegister0 & PRCM_PDSTAT0_SERIAL_ON);
+ }
+ if(ui32Domains & PRCM_DOMAIN_PERIPH)
+ {
+ bStatus = bStatus && (ui32StatusRegister0 & PRCM_PDSTAT0_PERIPH_ON);
+ }
+
+ // Return the status.
+ return (bStatus ? PRCM_DOMAIN_POWER_ON : PRCM_DOMAIN_POWER_OFF);
+}
+
+//*****************************************************************************
+//
+// Put the processor into deep-sleep mode
+//
+//*****************************************************************************
+void
+PRCMDeepSleep(void)
+{
+ // Enable deep-sleep.
+ HWREG(NVIC_SYS_CTRL) |= NVIC_SYS_CTRL_SLEEPDEEP;
+
+ // Wait for an interrupt.
+ CPUwfi();
+
+ // Disable deep-sleep so that a future sleep will work correctly.
+ HWREG(NVIC_SYS_CTRL) &= ~(NVIC_SYS_CTRL_SLEEPDEEP);
+}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/prcm.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/prcm.h
new file mode 100644
index 0000000..783ca42
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/prcm.h
@@ -0,0 +1,1234 @@
+/******************************************************************************
+* Filename: prcm.h
+* Revised: 2018-10-23 10:19:14 +0200 (Tue, 23 Oct 2018)
+* Revision: 52979
+*
+* Description: Defines and prototypes for the PRCM
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup system_control_group
+//! @{
+//! \addtogroup prcm_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __PRCM_H__
+#define __PRCM_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "../inc/hw_types.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_ints.h"
+#include "../inc/hw_prcm.h"
+#include "../inc/hw_nvic.h"
+#include "../inc/hw_aon_rtc.h"
+#include "interrupt.h"
+#include "debug.h"
+#include "cpu.h"
+
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// This section renames all functions that are not "static inline", so that
+// calling these functions will default to implementation in flash. At the end
+// of this file a second renaming will change the defaults to implementation in
+// ROM for available functions.
+//
+// To force use of the implementation in flash, e.g. for debugging:
+// - Globally: Define DRIVERLIB_NOROM at project level
+// - Per function: Use prefix "NOROM_" when calling the function
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #define PRCMInfClockConfigureSet NOROM_PRCMInfClockConfigureSet
+ #define PRCMInfClockConfigureGet NOROM_PRCMInfClockConfigureGet
+ #define PRCMAudioClockConfigSet NOROM_PRCMAudioClockConfigSet
+ #define PRCMAudioClockConfigSetOverride NOROM_PRCMAudioClockConfigSetOverride
+ #define PRCMAudioClockInternalSource NOROM_PRCMAudioClockInternalSource
+ #define PRCMAudioClockExternalSource NOROM_PRCMAudioClockExternalSource
+ #define PRCMPowerDomainOn NOROM_PRCMPowerDomainOn
+ #define PRCMPowerDomainOff NOROM_PRCMPowerDomainOff
+ #define PRCMPeripheralRunEnable NOROM_PRCMPeripheralRunEnable
+ #define PRCMPeripheralRunDisable NOROM_PRCMPeripheralRunDisable
+ #define PRCMPeripheralSleepEnable NOROM_PRCMPeripheralSleepEnable
+ #define PRCMPeripheralSleepDisable NOROM_PRCMPeripheralSleepDisable
+ #define PRCMPeripheralDeepSleepEnable NOROM_PRCMPeripheralDeepSleepEnable
+ #define PRCMPeripheralDeepSleepDisable NOROM_PRCMPeripheralDeepSleepDisable
+ #define PRCMPowerDomainStatus NOROM_PRCMPowerDomainStatus
+ #define PRCMDeepSleep NOROM_PRCMDeepSleep
+#endif
+
+//*****************************************************************************
+//
+// Defines for the different System CPU power modes.
+//
+//*****************************************************************************
+#define PRCM_RUN_MODE 0x00000001
+#define PRCM_SLEEP_MODE 0x00000002
+#define PRCM_DEEP_SLEEP_MODE 0x00000004
+
+//*****************************************************************************
+//
+// Defines used for setting the clock division factors
+//
+//*****************************************************************************
+#define PRCM_CLOCK_DIV_1 PRCM_GPTCLKDIV_RATIO_DIV1
+#define PRCM_CLOCK_DIV_2 PRCM_GPTCLKDIV_RATIO_DIV2
+#define PRCM_CLOCK_DIV_4 PRCM_GPTCLKDIV_RATIO_DIV4
+#define PRCM_CLOCK_DIV_8 PRCM_GPTCLKDIV_RATIO_DIV8
+#define PRCM_CLOCK_DIV_16 PRCM_GPTCLKDIV_RATIO_DIV16
+#define PRCM_CLOCK_DIV_32 PRCM_GPTCLKDIV_RATIO_DIV32
+#define PRCM_CLOCK_DIV_64 PRCM_GPTCLKDIV_RATIO_DIV64
+#define PRCM_CLOCK_DIV_128 PRCM_GPTCLKDIV_RATIO_DIV128
+#define PRCM_CLOCK_DIV_256 PRCM_GPTCLKDIV_RATIO_DIV256
+
+//*****************************************************************************
+//
+// Defines used for enabling and disabling domains and memories in the MCU
+// domain
+//
+//*****************************************************************************
+#define PRCM_DOMAIN_RFCORE 0x00000001 // RF Core domain ID for
+ // clock/power control.
+#define PRCM_DOMAIN_SERIAL 0x00000002 // Serial domain ID for
+ // clock/power control.
+#define PRCM_DOMAIN_PERIPH 0x00000004 // Peripheral domain ID for
+ // clock/power control.
+#define PRCM_DOMAIN_SYSBUS 0x00000008 // Bus domain ID for clock/power
+ // control.
+#define PRCM_DOMAIN_VIMS 0x00000010 // VIMS domain ID for clock/power
+ // control.
+#define PRCM_DOMAIN_VIMS_OFF_NO_WAKEUP \
+ 0x00020010 // For function PRCMPowerDomainOff() it is an option to
+ // select that VIMS power domain shall not power up
+ // during the next wake up from uLDO (VIMS_MODE=0b10).
+#define PRCM_DOMAIN_CPU 0x00000020 // CPU domain ID for clock/power
+ // control.
+#define PRCM_DOMAIN_TIMER 0x00000040 // GPT domain ID for clock
+ // control.
+#define PRCM_DOMAIN_CLKCTRL 0x00000080 // Clock Control domain ID for
+ // clock/power control.
+#define PRCM_DOMAIN_MCU 0x00000100 // Reset control for entire MCU
+ // domain.
+#define PRCM_DOMAIN_POWER_OFF 0x00000002 // The domain is powered off
+#define PRCM_DOMAIN_POWER_ON 0x00000001 // The domain is powered on
+#define PRCM_DOMAIN_POWER_DOWN_READY \
+ 0x00000000 // The domain is ready to be
+ // powered down.
+
+//*****************************************************************************
+//
+// Defines for setting up the audio interface in the I2S module.
+//
+//*****************************************************************************
+#define PRCM_WCLK_NEG_EDGE 0x00000008
+#define PRCM_WCLK_POS_EDGE 0x00000000
+#define PRCM_WCLK_SINGLE_PHASE 0x00000000
+#define PRCM_WCLK_DUAL_PHASE 0x00000002
+#define PRCM_WCLK_USER_DEF 0x00000004
+#define PRCM_I2S_WCLK_NEG_EDGE 0
+#define PRCM_I2S_WCLK_POS_EDGE 1
+#define PRCM_I2S_WCLK_SINGLE_PHASE 0
+#define PRCM_I2S_WCLK_DUAL_PHASE 1
+#define PRCM_I2S_WCLK_USER_DEF 2
+
+#define I2S_SAMPLE_RATE_16K 0x00000001
+#define I2S_SAMPLE_RATE_24K 0x00000002
+#define I2S_SAMPLE_RATE_32K 0x00000004
+#define I2S_SAMPLE_RATE_48K 0x00000008
+
+//*****************************************************************************
+//
+// Defines used for enabling and disabling peripheral modules in the MCU domain
+// bits[11:8] Defines the index into the register offset constant tables:
+// g_pui32RCGCRegs, g_pui32SCGCRegs and g_pui32DCGCRegs
+// bits[4:0] Defines the bit position within the register pointet on in [11:8]
+//
+//*****************************************************************************
+#define PRCM_PERIPH_TIMER0 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S )) // Peripheral ID for GPT module 0
+#define PRCM_PERIPH_TIMER1 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S + 1 )) // Peripheral ID for GPT module 1
+#define PRCM_PERIPH_TIMER2 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S + 2 )) // Peripheral ID for GPT module 2
+#define PRCM_PERIPH_TIMER3 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S + 3 )) // Peripheral ID for GPT module 3
+#define PRCM_PERIPH_SSI0 ( 0x00000100 | ( PRCM_SSICLKGR_CLK_EN_S )) // Peripheral ID for SSI module 0
+#define PRCM_PERIPH_SSI1 ( 0x00000100 | ( PRCM_SSICLKGR_CLK_EN_S + 1 )) // Peripheral ID for SSI module 1
+#define PRCM_PERIPH_UART0 ( 0x00000200 | ( PRCM_UARTCLKGR_CLK_EN_S )) // Peripheral ID for UART module 0
+#define PRCM_PERIPH_UART1 ( 0x00000200 | ( PRCM_UARTCLKGR_CLK_EN_S + 1 )) // Peripheral ID for UART module 1
+#define PRCM_PERIPH_I2C0 ( 0x00000300 | ( PRCM_I2CCLKGR_CLK_EN_S )) // Peripheral ID for I2C module 0
+#define PRCM_PERIPH_CRYPTO ( 0x00000400 | ( PRCM_SECDMACLKGR_CRYPTO_CLK_EN_S )) // Peripheral ID for CRYPTO module
+#define PRCM_PERIPH_TRNG ( 0x00000400 | ( PRCM_SECDMACLKGR_TRNG_CLK_EN_S )) // Peripheral ID for TRNG module
+#define PRCM_PERIPH_PKA ( 0x00000400 | ( PRCM_SECDMACLKGR_PKA_CLK_EN_S )) // Peripheral ID for PKA module
+#define PRCM_PERIPH_UDMA ( 0x00000400 | ( PRCM_SECDMACLKGR_DMA_CLK_EN_S )) // Peripheral ID for UDMA module
+#define PRCM_PERIPH_GPIO ( 0x00000500 | ( PRCM_GPIOCLKGR_CLK_EN_S )) // Peripheral ID for GPIO module
+#define PRCM_PERIPH_I2S ( 0x00000600 | ( PRCM_I2SCLKGR_CLK_EN_S )) // Peripheral ID for I2S module
+
+//*****************************************************************************
+//
+// API Functions and prototypes
+//
+//*****************************************************************************
+
+#ifdef DRIVERLIB_DEBUG
+//*****************************************************************************
+//
+//! \brief Checks a peripheral identifier.
+//!
+//! This function determines if a peripheral identifier is valid.
+//!
+//! \param ui32Peripheral is the peripheral identifier.
+//!
+//! \return Returns status of peripheral identifier:
+//! - \b true : Peripheral identifier is valid.
+//! - \b false : Peripheral identifier is invalid.
+//
+//*****************************************************************************
+static bool
+PRCMPeripheralValid(uint32_t ui32Peripheral)
+{
+ return((ui32Peripheral == PRCM_PERIPH_TIMER0) ||
+ (ui32Peripheral == PRCM_PERIPH_TIMER1) ||
+ (ui32Peripheral == PRCM_PERIPH_TIMER2) ||
+ (ui32Peripheral == PRCM_PERIPH_TIMER3) ||
+ (ui32Peripheral == PRCM_PERIPH_SSI0) ||
+ (ui32Peripheral == PRCM_PERIPH_SSI1) ||
+ (ui32Peripheral == PRCM_PERIPH_UART0) ||
+ (ui32Peripheral == PRCM_PERIPH_UART1) ||
+ (ui32Peripheral == PRCM_PERIPH_I2C0) ||
+ (ui32Peripheral == PRCM_PERIPH_CRYPTO) ||
+ (ui32Peripheral == PRCM_PERIPH_TRNG) ||
+ (ui32Peripheral == PRCM_PERIPH_PKA) ||
+ (ui32Peripheral == PRCM_PERIPH_UDMA) ||
+ (ui32Peripheral == PRCM_PERIPH_GPIO) ||
+ (ui32Peripheral == PRCM_PERIPH_I2S));
+}
+#endif
+
+//*****************************************************************************
+//
+//! \brief Configure the infrastructure clock.
+//!
+//! Each System CPU power mode has its own infrastructure clock division factor. This
+//! function can be used for setting up the division factor for the
+//! infrastructure clock in the available power modes for the System CPU. The
+//! infrastructure clock is used for all internal logic in the PRCM, and is
+//! always running as long as power is on in the MCU voltage domain.
+//! This can be enabled and disabled from the AON Wake Up Controller.
+//!
+//! \note If source clock is 48 MHz, minimum clock divider is \ref PRCM_CLOCK_DIV_2.
+//!
+//! \param ui32ClkDiv determines the division ratio for the infrastructure
+//! clock when the device is in the specified mode.
+//! Allowed division factors for all three System CPU power modes are:
+//! - \ref PRCM_CLOCK_DIV_1
+//! - \ref PRCM_CLOCK_DIV_2
+//! - \ref PRCM_CLOCK_DIV_8
+//! - \ref PRCM_CLOCK_DIV_32
+//! \param ui32PowerMode determines the System CPU operation mode for which to
+//! modify the clock division factor.
+//! The three allowed power modes are:
+//! - \ref PRCM_RUN_MODE
+//! - \ref PRCM_SLEEP_MODE
+//! - \ref PRCM_DEEP_SLEEP_MODE
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void PRCMInfClockConfigureSet(uint32_t ui32ClkDiv,
+ uint32_t ui32PowerMode);
+
+//*****************************************************************************
+//
+//! \brief Use this function to get the infrastructure clock configuration.
+//!
+//! \param ui32PowerMode determines which System CPU power mode to return the
+//! infrastructure clock division ratio for.
+//! The three allowed power modes are:
+//! - \ref PRCM_RUN_MODE
+//! - \ref PRCM_SLEEP_MODE
+//! - \ref PRCM_DEEP_SLEEP_MODE
+//!
+//! \return Returns the infrastructure clock division factor for the specified
+//! power mode.
+//! - \ref PRCM_CLOCK_DIV_1
+//! - \ref PRCM_CLOCK_DIV_2
+//! - \ref PRCM_CLOCK_DIV_8
+//! - \ref PRCM_CLOCK_DIV_32
+//!
+//! \sa \ref PRCMInfClockConfigureSet().
+//
+//*****************************************************************************
+extern uint32_t PRCMInfClockConfigureGet(uint32_t ui32PowerMode);
+
+//*****************************************************************************
+//
+//! \brief Assert or de-assert a request for the uLDO.
+//!
+//! Use this function to request to switch to the micro Low Voltage Dropout
+//! regulator (uLDO). The uLDO has a much lower capacity for supplying power
+//! to the system. It is therefore imperative and solely the programmers
+//! responsibility to ensure that a sufficient amount of peripheral modules
+//! have been turned of before requesting a switch to the uLDO.
+//!
+//! \note Asserting this bit has no effect until:
+//! 1. FLASH has accepted to be powered down
+//! 2. Deepsleep must be asserted
+//!
+//! \param ui32Enable
+//! - 0 : Disable uLDO request
+//! - 1 : Enable uLDO request
+//!
+//! \return None
+//!
+//! \sa \ref PRCMDeepSleep()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+PRCMMcuUldoConfigure(uint32_t ui32Enable)
+{
+ // Enable or disable the uLDO request signal.
+ HWREGBITW(PRCM_BASE + PRCM_O_VDCTL, PRCM_VDCTL_ULDO_BITN) = ui32Enable;
+}
+
+//*****************************************************************************
+//
+//! \brief Setup the clock division factor for the GP-Timer domain.
+//!
+//! Use this function to set up the clock division factor on the GP-Timer.
+//!
+//! The division rate will be constant and ungated for Run / Sleep / DeepSleep mode when
+//! it is slower than PRCM_GPTCLKDIV_RATIO setting.
+//! When set faster than PRCM_GPTCLKDIV_RATIO setting PRCM_GPTCLKDIV_RATIO will be used.
+//! Note that the register will contain the written content even though the setting is
+//! faster than PRCM_GPTCLKDIV_RATIO setting.
+//!
+//! \note For change to take effect, \ref PRCMLoadSet() needs to be called
+//!
+//! \param clkDiv is the division factor to set.
+//! The argument must be only one of the following values:
+//! - \ref PRCM_CLOCK_DIV_1
+//! - \ref PRCM_CLOCK_DIV_2
+//! - \ref PRCM_CLOCK_DIV_4
+//! - \ref PRCM_CLOCK_DIV_8
+//! - \ref PRCM_CLOCK_DIV_16
+//! - \ref PRCM_CLOCK_DIV_32
+//! - \ref PRCM_CLOCK_DIV_64
+//! - \ref PRCM_CLOCK_DIV_128
+//! - \ref PRCM_CLOCK_DIV_256
+//!
+//! \return None
+//!
+//! \sa \ref PRCMGPTimerClockDivisionGet()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+PRCMGPTimerClockDivisionSet( uint32_t clkDiv )
+{
+ ASSERT( clkDiv <= PRCM_GPTCLKDIV_RATIO_DIV256 );
+
+ HWREG( PRCM_BASE + PRCM_O_GPTCLKDIV ) = clkDiv;
+}
+
+//*****************************************************************************
+//
+//! \brief Get the clock division factor for the GP-Timer domain.
+//!
+//! Use this function to get the clock division factor set for the GP-Timer.
+//!
+//! \return Returns one of the following values:
+//! - \ref PRCM_CLOCK_DIV_1
+//! - \ref PRCM_CLOCK_DIV_2
+//! - \ref PRCM_CLOCK_DIV_4
+//! - \ref PRCM_CLOCK_DIV_8
+//! - \ref PRCM_CLOCK_DIV_16
+//! - \ref PRCM_CLOCK_DIV_32
+//! - \ref PRCM_CLOCK_DIV_64
+//! - \ref PRCM_CLOCK_DIV_128
+//! - \ref PRCM_CLOCK_DIV_256
+//!
+//! \sa \ref PRCMGPTimerClockDivisionSet()
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+PRCMGPTimerClockDivisionGet( void )
+{
+ return ( HWREG( PRCM_BASE + PRCM_O_GPTCLKDIV ));
+}
+
+
+//*****************************************************************************
+//
+//! \brief Enable the audio clock generation.
+//!
+//! Use this function to enable the audio clock generation.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+PRCMAudioClockEnable(void)
+{
+ // Enable the audio clock generation.
+ HWREGBITW(PRCM_BASE + PRCM_O_I2SCLKCTL, PRCM_I2SCLKCTL_EN_BITN) = 1;
+}
+
+//*****************************************************************************
+//
+//! \brief Disable the audio clock generation.
+//!
+//! Use this function to disable the audio clock generation.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+PRCMAudioClockDisable(void)
+{
+ // Disable the audio clock generation
+ HWREGBITW(PRCM_BASE + PRCM_O_I2SCLKCTL, PRCM_I2SCLKCTL_EN_BITN) = 0;
+}
+
+//*****************************************************************************
+//
+//! \brief Configure the audio clock generation.
+//!
+//! \deprecated This function will be removed in a future release.
+//!
+//! Use this function to set the sample rate when using internal audio clock
+//! generation for the I2S module.
+//!
+//! \note While other clocks are possible, the stability of the four sample
+//! rates defined here are only guaranteed if the clock input to the I2S module
+//! is 48MHz.
+//!
+//! \param ui32ClkConfig is the audio clock configuration.
+//! The parameter is a bitwise OR'ed value consisting of:
+//! - Phase
+//! - \ref PRCM_WCLK_SINGLE_PHASE
+//! - \ref PRCM_WCLK_DUAL_PHASE
+//! - Clock polarity
+//! - \ref PRCM_WCLK_NEG_EDGE
+//! - \ref PRCM_WCLK_POS_EDGE
+//! \param ui32SampleRate is the desired audio clock sample rate.
+//! The supported sample rate configurations are:
+//! - \ref I2S_SAMPLE_RATE_16K
+//! - \ref I2S_SAMPLE_RATE_24K
+//! - \ref I2S_SAMPLE_RATE_32K
+//! - \ref I2S_SAMPLE_RATE_48K
+//!
+//! \return None
+//!
+//! \sa \ref PRCMAudioClockConfigSetOverride()
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+extern void PRCMAudioClockConfigSet(uint32_t ui32ClkConfig,
+ uint32_t ui32SampleRate);
+#endif
+
+//*****************************************************************************
+//
+//! \brief Configure the audio clock generation with manual setting of clock divider.
+//!
+//! \deprecated This function will be removed in a future release.
+//!
+//! Use this function to set the audio clock divider values manually.
+//!
+//! \note See hardware documentation before setting audio clock dividers manually.
+//!
+//! \param ui32ClkConfig is the audio clock configuration.
+//! The parameter is a bitwise OR'ed value consisting of:
+//! - Phase
+//! - \ref PRCM_WCLK_SINGLE_PHASE
+//! - \ref PRCM_WCLK_DUAL_PHASE
+//! - Clock polarity
+//! - \ref PRCM_WCLK_NEG_EDGE
+//! - \ref PRCM_WCLK_POS_EDGE
+//! \param ui32MstDiv is the desired master clock divider.
+//! \param ui32WordDiv is the desired word clock divider.
+//! \param ui32BitDiv is the desired bit clock divider.
+//!
+//! \return None
+//!
+//! \sa \ref PRCMAudioClockConfigSet()
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+extern void PRCMAudioClockConfigSetOverride(uint32_t ui32ClkConfig, uint32_t ui32MstDiv,
+ uint32_t ui32BitDiv, uint32_t ui32WordDiv);
+#endif
+
+//*****************************************************************************
+//
+//! \brief Configure the audio clocks for I2S module.
+//!
+//! \note See hardware documentation before setting audio clock dividers.
+//! This is user's responsability to provide valid clock dividers.
+//!
+//! \param ui8SamplingEdge Define the clock polarity:
+//! - \ref PRCM_I2S_WCLK_NEG_EDGE
+//! - \ref PRCM_I2S_WCLK_POS_EDGE
+//! \param ui8WCLKPhase Define I2S phase used
+//! - PRCM_I2S_WCLK_SINGLE_PHASE
+//! - PRCM_I2S_WCLK_DUAL_PHASE
+//! - PRCM_I2S_WCLK_USER_DEF
+//! \param ui32MstDiv is the desired master clock divider.
+//! \param ui32BitDiv is the desired bit clock divider.
+//! \param ui32WordDiv is the desired word clock divider.
+//!
+//! \return None
+//!
+//*****************************************************************************
+extern void PRCMAudioClockConfigOverride
+ (uint8_t ui8SamplingEdge,
+ uint8_t ui8WCLKPhase,
+ uint32_t ui32MstDiv,
+ uint32_t ui32BitDiv,
+ uint32_t ui32WordDiv);
+
+//*****************************************************************************
+//
+//! \brief Configure the audio clocks to be internally generated.
+//!
+//! Use this function to set the audio clocks as internal.
+//!
+//! \return None
+//!
+//! \sa \ref PRCMAudioClockExternalSource()
+//
+//*****************************************************************************
+extern void PRCMAudioClockInternalSource(void);
+
+//*****************************************************************************
+//
+//! \brief Configure the audio clocks to be externally generated.
+//!
+//! Use this function to set the audio clocks as external.
+//!
+//! \return None
+//!
+//! \sa \ref PRCMAudioClockInternalSource()
+//
+//*****************************************************************************
+extern void PRCMAudioClockExternalSource(void);
+
+//*****************************************************************************
+//
+//! \brief Use this function to synchronize the load settings.
+//!
+//! Most of the clock settings in the PRCM module should be updated
+//! synchronously. This is ensured by the implementation of a load registers
+//! that, when written to, will let the previous written update values for all
+//! the relevant registers propagate through to hardware.
+//!
+//! The functions that require a synchronization of the clock settings are:
+//! - \ref PRCMAudioClockConfigSet()
+//! - \ref PRCMAudioClockConfigSetOverride()
+//! - \ref PRCMAudioClockDisable()
+//! - \ref PRCMDomainEnable()
+//! - \ref PRCMDomainDisable()
+//! - \ref PRCMPeripheralRunEnable()
+//! - \ref PRCMPeripheralRunDisable()
+//! - \ref PRCMPeripheralSleepEnable()
+//! - \ref PRCMPeripheralSleepDisable()
+//! - \ref PRCMPeripheralDeepSleepEnable()
+//! - \ref PRCMPeripheralDeepSleepDisable()
+//!
+//! \return None
+//!
+//! \sa \ref PRCMLoadGet()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+PRCMLoadSet(void)
+{
+ // Enable the update of all load related registers.
+ HWREG(PRCM_NONBUF_BASE + PRCM_O_CLKLOADCTL) = PRCM_CLKLOADCTL_LOAD;
+}
+
+//*****************************************************************************
+//
+//! \brief Check if any of the load sensitive register has been updated.
+//!
+//! \return Returns status of the load sensitive register:
+//! - \c true : No registers have changed since the last load.
+//! - \c false : Any register has changed.
+//!
+//! \sa \ref PRCMLoadSet()
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+PRCMLoadGet(void)
+{
+ // Return the load status.
+ return ((HWREG(PRCM_BASE + PRCM_O_CLKLOADCTL) & PRCM_CLKLOADCTL_LOAD_DONE) ?
+ true : false);
+}
+
+//*****************************************************************************
+//
+//! \brief Enable clock domains in the MCU voltage domain.
+//!
+//! \note A call to this function will only setup the shadow registers in the
+//! MCU domain for the PRCM module. For the changes to propagate to the system
+//! controller in the AON domain a call to this function should always be
+//! followed by a call to \ref PRCMLoadSet().
+//!
+//! \note Clocks will only be running if the domain is powered.
+//!
+//! \param ui32Domains is a bit mask containing the clock domains to enable.
+//! The independent clock domains inside the MCU voltage domain which can be
+//! configured are:
+//! - \ref PRCM_DOMAIN_RFCORE
+//! - \ref PRCM_DOMAIN_VIMS
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+PRCMDomainEnable(uint32_t ui32Domains)
+{
+ // Check the arguments.
+ ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) ||
+ (ui32Domains & PRCM_DOMAIN_VIMS));
+
+ // Enable the clock domain(s).
+ if(ui32Domains & PRCM_DOMAIN_RFCORE)
+ {
+ HWREG(PRCM_BASE + PRCM_O_RFCCLKG) = PRCM_RFCCLKG_CLK_EN;
+ }
+ if(ui32Domains & PRCM_DOMAIN_VIMS)
+ {
+ HWREG(PRCM_BASE + PRCM_O_VIMSCLKG) = PRCM_VIMSCLKG_CLK_EN_M;
+ }
+}
+
+//*****************************************************************************
+//
+//! \brief Disable clock domains in the MCU voltage domain.
+//!
+//! \note A call to this function will only setup the shadow registers in the
+//! MCU domain for the PRCM module. For the changes to propagate to the system
+//! controller in the AON domain a call to this function should always be
+//! followed by a call to \ref PRCMLoadSet().
+//!
+//! \note Clocks will only be running if the domain is powered.
+//!
+//! \param ui32Domains is a bit mask containing the clock domains to disable.
+//! The independent clock domains inside the MCU voltage domain are:
+//! - \ref PRCM_DOMAIN_RFCORE
+//! - \ref PRCM_DOMAIN_VIMS
+//!
+//! \return None
+//!
+//! \sa PRCMDomainEnable()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+PRCMDomainDisable(uint32_t ui32Domains)
+{
+ // Check the arguments.
+ ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) ||
+ (ui32Domains & PRCM_DOMAIN_VIMS));
+
+ // Disable the power domains.
+ if(ui32Domains & PRCM_DOMAIN_RFCORE)
+ {
+ HWREG(PRCM_BASE + PRCM_O_RFCCLKG) = 0x0;
+ }
+ if(ui32Domains & PRCM_DOMAIN_VIMS)
+ {
+ HWREG(PRCM_BASE + PRCM_O_VIMSCLKG) = 0x0;
+ }
+}
+
+//*****************************************************************************
+//
+//! \brief Turn power on in power domains in the MCU domain.
+//!
+//! Use this function to turn on power domains inside the MCU voltage domain.
+//!
+//! Power on and power off request has different implications for the
+//! different power domains.
+//! - RF Core power domain:
+//! - Power On : Domain is on or in the process of turning on.
+//! - Power Off : Domain is powered down when System CPU is in deep sleep. The third
+//! option for the RF Core is to power down when the it is idle.
+//! This can be set using \b PRCMRfPowerDownWhenIdle()
+//! - SERIAL power domain:
+//! - Power on : Domain is powered on.
+//! - Power off : Domain is powered off.
+//! - PERIPHERIAL power domain:
+//! - Power on : Domain is powered on.
+//! - Power off : Domain is powered off.
+//! - VIMS power domain:
+//! - Power On : Domain is powered if Bus domain is powered.
+//! - Power Off : Domain is only powered when CPU domain is on.
+//! - BUS power domain:
+//! - Power On : Domain is on.
+//! - Power Off : Domain is on if requested by RF Core or if CPU domain is on.
+//! - CPU power domain:
+//! - Power On : Domain is on.
+//! - Power Off : Domain is powering down if System CPU is idle. This will also
+//! initiate a power down of the SRAM and BUS power domains, unless
+//! RF Core is requesting them to be on.
+//!
+//! \note After a call to this function the status of the power domain should
+//! be checked using either \ref PRCMPowerDomainStatus().
+//! Any write operation to a power domain which is still not operational can
+//! result in unexpected behavior.
+//!
+//! \param ui32Domains determines which power domains to turn on.
+//! The domains that can be turned on/off are:
+//! - \b PRCM_DOMAIN_RFCORE : RF Core
+//! - \b PRCM_DOMAIN_SERIAL : SSI0, UART0, I2C0
+//! - \b PRCM_DOMAIN_PERIPH : GPT0, GPT1, GPT2, GPT3, GPIO, SSI1, I2S, DMA, UART1
+//! - \b PRCM_DOMAIN_VIMS : SRAM, FLASH, ROM
+//! - \b PRCM_DOMAIN_SYSBUS
+//! - \b PRCM_DOMAIN_CPU
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void PRCMPowerDomainOn(uint32_t ui32Domains);
+
+//*****************************************************************************
+//
+//! \brief Turn off a specific power domain.
+//!
+//! Use this function to power down domains inside the MCU voltage domain.
+//!
+//! \note For specifics regarding on/off configuration please see
+//! \ref PRCMPowerDomainOn().
+//!
+//! \param ui32Domains determines which domain to request a power down for.
+//! The domains that can be turned on/off are:
+//! - \b PRCM_DOMAIN_RFCORE : RF Core
+//! - \b PRCM_DOMAIN_SERIAL : SSI0, UART0, I2C0
+//! - \b PRCM_DOMAIN_PERIPH : GPT0, GPT1, GPT2, GPT3, GPIO, SSI1, I2S, DMA, UART1
+//! - \b PRCM_DOMAIN_VIMS : SRAM, FLASH, ROM
+//! - \b PRCM_DOMAIN_VIMS_OFF_NO_WAKEUP : SRAM, FLASH, ROM
+//! - \b PRCM_DOMAIN_SYSBUS
+//! - \b PRCM_DOMAIN_CPU
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void PRCMPowerDomainOff(uint32_t ui32Domains);
+
+//*****************************************************************************
+//
+//! \brief Configure RF core to power down when idle.
+//!
+//! Use this function to configure the RF core to power down when Idle. This
+//! is handled automatically in hardware if the RF Core reports that it is
+//! idle.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+PRCMRfPowerDownWhenIdle(void)
+{
+ // Configure the RF power domain.
+ HWREGBITW(PRCM_BASE + PRCM_O_PDCTL0RFC, PRCM_PDCTL0RFC_ON_BITN) = 0;
+}
+
+//*****************************************************************************
+//
+//! \brief Enables a peripheral in Run mode.
+//!
+//! Peripherals are enabled with this function. At power-up, some peripherals
+//! are disabled; they must be enabled in order to operate or respond to
+//! register reads/writes.
+//!
+//! \note The actual enabling of the peripheral may be delayed until some
+//! time after this function returns. Care should be taken to ensure that the
+//! peripheral is not accessed until it is enabled.
+//! When enabling Timers always make sure that the division factor for the
+//! \b PERBUSCPUCLK is set. This will guarantee that the timers run at a
+//! continuous rate even if the \b SYSBUSCLK is gated.
+//!
+//! \note A call to this function will only setup the shadow registers in the
+//! MCU domain for the PRCM module. For the changes to propagate to the system
+//! controller in the AON domain a call to this function should always be
+//! followed by a call to \ref PRCMLoadSet().
+//!
+//! \param ui32Peripheral is the peripheral to enable.
+//! The parameter must be one of the following:
+//! - \ref PRCM_PERIPH_TIMER0
+//! - \ref PRCM_PERIPH_TIMER1
+//! - \ref PRCM_PERIPH_TIMER2
+//! - \ref PRCM_PERIPH_TIMER3
+//! - \ref PRCM_PERIPH_SSI0
+//! - \ref PRCM_PERIPH_SSI1
+//! - \ref PRCM_PERIPH_UART0
+//! - \ref PRCM_PERIPH_UART1
+//! - \ref PRCM_PERIPH_I2C0
+//! - \ref PRCM_PERIPH_CRYPTO
+//! - \ref PRCM_PERIPH_TRNG
+//! - \ref PRCM_PERIPH_PKA
+//! - \ref PRCM_PERIPH_UDMA
+//! - \ref PRCM_PERIPH_GPIO
+//! - \ref PRCM_PERIPH_I2S
+//!
+//! \return None
+//!
+//! \sa \ref PRCMLoadSet()
+//
+//*****************************************************************************
+extern void PRCMPeripheralRunEnable(uint32_t ui32Peripheral);
+
+//*****************************************************************************
+//
+//! \brief Disables a peripheral in Run mode
+//!
+//! Peripherals are disabled with this function. Once disabled, they will not
+//! operate or respond to register reads/writes.
+//!
+//! \note A call to this function will only setup the shadow registers in the
+//! MCU domain for the PRCM module. For the changes to propagate to the system
+//! controller in the AON domain a call to this function should always be
+//! followed by a call to \ref PRCMLoadSet().
+//!
+//! \note The actual disabling of the peripheral may be delayed until some
+//! time after this function returns. Care should be taken by the user to
+//! ensure that the peripheral is not accessed in this interval as this might
+//! cause the system to hang.
+//!
+//! \param ui32Peripheral is the peripheral to disable.
+//! The parameter must be one of the following:
+//! - \ref PRCM_PERIPH_TIMER0
+//! - \ref PRCM_PERIPH_TIMER1
+//! - \ref PRCM_PERIPH_TIMER2
+//! - \ref PRCM_PERIPH_TIMER3
+//! - \ref PRCM_PERIPH_SSI0
+//! - \ref PRCM_PERIPH_SSI1
+//! - \ref PRCM_PERIPH_UART0
+//! - \ref PRCM_PERIPH_UART1
+//! - \ref PRCM_PERIPH_I2C0
+//! - \ref PRCM_PERIPH_CRYPTO
+//! - \ref PRCM_PERIPH_TRNG
+//! - \ref PRCM_PERIPH_PKA
+//! - \ref PRCM_PERIPH_UDMA
+//! - \ref PRCM_PERIPH_GPIO
+//! - \ref PRCM_PERIPH_I2S
+//!
+//! \return None
+//!
+//! \sa \ref PRCMLoadSet()
+//
+//*****************************************************************************
+extern void PRCMPeripheralRunDisable(uint32_t ui32Peripheral);
+
+//*****************************************************************************
+//
+//! \brief Enables a peripheral in sleep mode.
+//!
+//! This function allows a peripheral to continue operating when the processor
+//! goes into sleep mode. Since the clocking configuration of the device does
+//! not change, any peripheral can safely continue operating while the
+//! processor is in sleep mode, and can therefore wake the processor from sleep
+//! mode.
+//!
+//! \note A call to this function will only setup the shadow registers in the
+//! MCU domain for the PRCM module. For the changes to propagate to the system
+//! controller in the AON domain a call to this function should always be
+//! followed by a call to \ref PRCMLoadSet().
+//!
+//! \param ui32Peripheral is the peripheral to enable in sleep mode.
+//! The parameter must be one of the following:
+//! - \ref PRCM_PERIPH_TIMER0
+//! - \ref PRCM_PERIPH_TIMER1
+//! - \ref PRCM_PERIPH_TIMER2
+//! - \ref PRCM_PERIPH_TIMER3
+//! - \ref PRCM_PERIPH_SSI0
+//! - \ref PRCM_PERIPH_SSI1
+//! - \ref PRCM_PERIPH_UART0
+//! - \ref PRCM_PERIPH_UART1
+//! - \ref PRCM_PERIPH_I2C0
+//! - \ref PRCM_PERIPH_CRYPTO
+//! - \ref PRCM_PERIPH_TRNG
+//! - \ref PRCM_PERIPH_PKA
+//! - \ref PRCM_PERIPH_UDMA
+//! - \ref PRCM_PERIPH_GPIO
+//! - \ref PRCM_PERIPH_I2S
+//!
+//! \return None
+//!
+//! \sa \ref PRCMLoadSet()
+//
+//*****************************************************************************
+extern void PRCMPeripheralSleepEnable(uint32_t ui32Peripheral);
+
+//*****************************************************************************
+//
+//! \brief Disables a peripheral in sleep mode.
+//!
+//! This function causes a peripheral to stop operating when the processor goes
+//! into sleep mode. Disabling peripherals while in sleep mode helps to lower
+//! the current draw of the device. If enabled (via \ref PRCMPeripheralRunEnable()),
+//! the peripheral will automatically resume operation when the processor
+//! leaves sleep mode, maintaining its entire state from before sleep mode was
+//! entered.
+//!
+//! \note A call to this function will only setup the shadow registers in the
+//! MCU domain for the PRCM module. For the changes to propagate to the system
+//! controller in the AON domain a call to this function should always be
+//! followed by a call to \ref PRCMLoadSet().
+//!
+//! \param ui32Peripheral is the peripheral to disable in sleep mode.
+//! The parameter must be one of the following:
+//! - \ref PRCM_PERIPH_TIMER0
+//! - \ref PRCM_PERIPH_TIMER1
+//! - \ref PRCM_PERIPH_TIMER2
+//! - \ref PRCM_PERIPH_TIMER3
+//! - \ref PRCM_PERIPH_SSI0
+//! - \ref PRCM_PERIPH_SSI1
+//! - \ref PRCM_PERIPH_UART0
+//! - \ref PRCM_PERIPH_UART1
+//! - \ref PRCM_PERIPH_I2C0
+//! - \ref PRCM_PERIPH_CRYPTO
+//! - \ref PRCM_PERIPH_TRNG
+//! - \ref PRCM_PERIPH_PKA
+//! - \ref PRCM_PERIPH_UDMA
+//! - \ref PRCM_PERIPH_GPIO
+//! - \ref PRCM_PERIPH_I2S
+//!
+//! \return None
+//!
+//! \sa \ref PRCMLoadSet()
+//
+//*****************************************************************************
+extern void PRCMPeripheralSleepDisable(uint32_t ui32Peripheral);
+
+//*****************************************************************************
+//
+//! \brief Enables a peripheral in deep-sleep mode.
+//!
+//! This function allows a peripheral to continue operating when the processor
+//! goes into deep-sleep mode. Since the clocking configuration of the device
+//! may change, not all peripherals can safely continue operating while the
+//! processor is in sleep mode. This in turn depends on the chosen power mode.
+//! It is the responsibility of the caller to make sensible choices.
+//!
+//! \note A call to this function will only setup the shadow registers in the
+//! MCU domain for the PRCM module. For the changes to propagate to the system
+//! controller in the AON domain a call to this function should always be
+//! followed by a call to \ref PRCMLoadSet().
+//!
+//! \param ui32Peripheral is the peripheral to enable in deep-sleep mode.
+//! The parameter must be one of the following:
+//! - \ref PRCM_PERIPH_TIMER0
+//! - \ref PRCM_PERIPH_TIMER1
+//! - \ref PRCM_PERIPH_TIMER2
+//! - \ref PRCM_PERIPH_TIMER3
+//! - \ref PRCM_PERIPH_SSI0
+//! - \ref PRCM_PERIPH_SSI1
+//! - \ref PRCM_PERIPH_UART0
+//! - \ref PRCM_PERIPH_UART1
+//! - \ref PRCM_PERIPH_I2C0
+//! - \ref PRCM_PERIPH_CRYPTO
+//! - \ref PRCM_PERIPH_TRNG
+//! - \ref PRCM_PERIPH_PKA
+//! - \ref PRCM_PERIPH_UDMA
+//! - \ref PRCM_PERIPH_GPIO
+//! - \ref PRCM_PERIPH_I2S
+//!
+//! \return None
+//!
+//! \sa \ref PRCMLoadSet()
+//
+//*****************************************************************************
+extern void PRCMPeripheralDeepSleepEnable(uint32_t ui32Peripheral);
+
+//*****************************************************************************
+//
+//! \brief Disables a peripheral in deep-sleep mode.
+//!
+//! This function causes a peripheral to stop operating when the processor goes
+//! into deep-sleep mode. Disabling peripherals while in deep-sleep mode helps
+//! to lower the current draw of the device, and can keep peripherals that
+//! require a particular clock frequency from operating when the clock changes
+//! as a result of entering deep-sleep mode. If enabled (via
+//! \ref PRCMPeripheralRunEnable()), the peripheral will automatically resume
+//! operation when the processor leaves deep-sleep mode, maintaining its entire
+//! state from before deep-sleep mode was entered.
+//!
+//! \note A call to this function will only setup the shadow registers in the
+//! MCU domain for the PRCM module. For the changes to propagate to the system
+//! controller in the AON domain a call to this function should always be
+//! followed by a call to \ref PRCMLoadSet().
+//!
+//! \param ui32Peripheral is the peripheral to disable in deep-sleep mode.
+//! The parameter must be one of the following:
+//! - \ref PRCM_PERIPH_TIMER0
+//! - \ref PRCM_PERIPH_TIMER1
+//! - \ref PRCM_PERIPH_TIMER2
+//! - \ref PRCM_PERIPH_TIMER3
+//! - \ref PRCM_PERIPH_SSI0
+//! - \ref PRCM_PERIPH_SSI1
+//! - \ref PRCM_PERIPH_UART0
+//! - \ref PRCM_PERIPH_UART1
+//! - \ref PRCM_PERIPH_I2C0
+//! - \ref PRCM_PERIPH_CRYPTO
+//! - \ref PRCM_PERIPH_TRNG
+//! - \ref PRCM_PERIPH_PKA
+//! - \ref PRCM_PERIPH_UDMA
+//! - \ref PRCM_PERIPH_GPIO
+//! - \ref PRCM_PERIPH_I2S
+//!
+//! \return None
+//!
+//! \sa \ref PRCMLoadSet()
+//
+//*****************************************************************************
+extern void PRCMPeripheralDeepSleepDisable(uint32_t ui32Peripheral);
+
+//*****************************************************************************
+//
+//! \brief Get the status for a specific power domain.
+//!
+//! Use this function to retrieve the current power status of one or more
+//! power domains.
+//!
+//! \param ui32Domains determines which domain to get the power status for.
+//! The parameter must be an OR'ed combination of one or several of:
+//! - \ref PRCM_DOMAIN_RFCORE : RF Core.
+//! - \ref PRCM_DOMAIN_SERIAL : SSI0, UART0, I2C0
+//! - \ref PRCM_DOMAIN_PERIPH : GPT0, GPT1, GPT2, GPT3, GPIO, SSI1, I2S, DMA, UART1
+//!
+//! \return Returns status of the requested domains:
+//! - \ref PRCM_DOMAIN_POWER_ON : The specified domains are \b all powered up.
+//! This status is unconditional and the powered up status is guaranteed.
+//! - \ref PRCM_DOMAIN_POWER_OFF : Any of the domains are powered down.
+//
+//*****************************************************************************
+extern uint32_t PRCMPowerDomainStatus(uint32_t ui32Domains);
+
+//*****************************************************************************
+//
+//! \brief Return the access status of the RF Core.
+//!
+//! Use this function to check if the RF Core is on and ready to be accessed.
+//! Accessing register or memories that are not powered and clocked will
+//! cause a bus fault.
+//!
+//! \return Returns access status of the RF Core.
+//! - \c true : RF Core can be accessed.
+//! - \c false : RF Core domain is not ready for access.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+PRCMRfReady(void)
+{
+ // Return the ready status of the RF Core.
+ return ((HWREG(PRCM_BASE + PRCM_O_PDSTAT1RFC) &
+ PRCM_PDSTAT1RFC_ON) ? true : false);
+}
+
+
+//*****************************************************************************
+//
+//! \brief Put the processor into sleep mode.
+//!
+//! This function places the processor into sleep mode; it does not return
+//! until the processor returns to run mode. The peripherals that are enabled
+//! via PRCMPeripheralSleepEnable() continue to operate and can wake up the
+//! processor.
+//!
+//! \return None
+//!
+//! \sa \ref PRCMPeripheralSleepEnable()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+PRCMSleep(void)
+{
+ // Wait for an interrupt.
+ CPUwfi();
+}
+
+//*****************************************************************************
+//
+//! \brief Put the processor into deep-sleep mode.
+//!
+//! This function places the processor into deep-sleep mode; it does not return
+//! until the processor returns to run mode. The peripherals that are enabled
+//! via \ref PRCMPeripheralDeepSleepEnable() continue to operate and can wake up
+//! the processor.
+//!
+//! \return None
+//!
+//! \sa \ref PRCMPeripheralDeepSleepEnable()
+//
+//*****************************************************************************
+extern void PRCMDeepSleep(void);
+
+//*****************************************************************************
+//
+//! \brief Enable CACHE RAM retention
+//!
+//! Enables CACHE RAM retention on both VIMS_TRAM and VIMS_CRAM
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+PRCMCacheRetentionEnable( void )
+{
+ HWREG( PRCM_BASE + PRCM_O_RAMRETEN ) |= PRCM_RAMRETEN_VIMS_M;
+}
+
+//*****************************************************************************
+//
+//! \brief Disable CACHE RAM retention
+//!
+//! Disables CACHE RAM retention on both VIMS_TRAM and VIMS_CRAM
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+PRCMCacheRetentionDisable( void )
+{
+ HWREG( PRCM_BASE + PRCM_O_RAMRETEN ) &= ~PRCM_RAMRETEN_VIMS_M;
+}
+
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// Redirect to implementation in ROM when available.
+//
+//*****************************************************************************
+#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
+ #include "../driverlib/rom.h"
+ #ifdef ROM_PRCMInfClockConfigureSet
+ #undef PRCMInfClockConfigureSet
+ #define PRCMInfClockConfigureSet ROM_PRCMInfClockConfigureSet
+ #endif
+ #ifdef ROM_PRCMInfClockConfigureGet
+ #undef PRCMInfClockConfigureGet
+ #define PRCMInfClockConfigureGet ROM_PRCMInfClockConfigureGet
+ #endif
+ #ifdef ROM_PRCMAudioClockConfigSet
+ #undef PRCMAudioClockConfigSet
+ #define PRCMAudioClockConfigSet ROM_PRCMAudioClockConfigSet
+ #endif
+ #ifdef ROM_PRCMAudioClockConfigSetOverride
+ #undef PRCMAudioClockConfigSetOverride
+ #define PRCMAudioClockConfigSetOverride ROM_PRCMAudioClockConfigSetOverride
+ #endif
+ #ifdef ROM_PRCMAudioClockInternalSource
+ #undef PRCMAudioClockInternalSource
+ #define PRCMAudioClockInternalSource ROM_PRCMAudioClockInternalSource
+ #endif
+ #ifdef ROM_PRCMAudioClockExternalSource
+ #undef PRCMAudioClockExternalSource
+ #define PRCMAudioClockExternalSource ROM_PRCMAudioClockExternalSource
+ #endif
+ #ifdef ROM_PRCMPowerDomainOn
+ #undef PRCMPowerDomainOn
+ #define PRCMPowerDomainOn ROM_PRCMPowerDomainOn
+ #endif
+ #ifdef ROM_PRCMPowerDomainOff
+ #undef PRCMPowerDomainOff
+ #define PRCMPowerDomainOff ROM_PRCMPowerDomainOff
+ #endif
+ #ifdef ROM_PRCMPeripheralRunEnable
+ #undef PRCMPeripheralRunEnable
+ #define PRCMPeripheralRunEnable ROM_PRCMPeripheralRunEnable
+ #endif
+ #ifdef ROM_PRCMPeripheralRunDisable
+ #undef PRCMPeripheralRunDisable
+ #define PRCMPeripheralRunDisable ROM_PRCMPeripheralRunDisable
+ #endif
+ #ifdef ROM_PRCMPeripheralSleepEnable
+ #undef PRCMPeripheralSleepEnable
+ #define PRCMPeripheralSleepEnable ROM_PRCMPeripheralSleepEnable
+ #endif
+ #ifdef ROM_PRCMPeripheralSleepDisable
+ #undef PRCMPeripheralSleepDisable
+ #define PRCMPeripheralSleepDisable ROM_PRCMPeripheralSleepDisable
+ #endif
+ #ifdef ROM_PRCMPeripheralDeepSleepEnable
+ #undef PRCMPeripheralDeepSleepEnable
+ #define PRCMPeripheralDeepSleepEnable ROM_PRCMPeripheralDeepSleepEnable
+ #endif
+ #ifdef ROM_PRCMPeripheralDeepSleepDisable
+ #undef PRCMPeripheralDeepSleepDisable
+ #define PRCMPeripheralDeepSleepDisable ROM_PRCMPeripheralDeepSleepDisable
+ #endif
+ #ifdef ROM_PRCMPowerDomainStatus
+ #undef PRCMPowerDomainStatus
+ #define PRCMPowerDomainStatus ROM_PRCMPowerDomainStatus
+ #endif
+ #ifdef ROM_PRCMDeepSleep
+ #undef PRCMDeepSleep
+ #define PRCMDeepSleep ROM_PRCMDeepSleep
+ #endif
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __PRCM_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/pwr_ctrl.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/pwr_ctrl.c
new file mode 100644
index 0000000..92e7955
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/pwr_ctrl.c
@@ -0,0 +1,80 @@
+/******************************************************************************
+* Filename: pwr_ctrl.c
+* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017)
+* Revision: 49096
+*
+* Description: Power Control driver.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "pwr_ctrl.h"
+
+//*****************************************************************************
+//
+// Handle support for DriverLib in ROM:
+// This section will undo prototype renaming made in the header file
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #undef PowerCtrlSourceSet
+ #define PowerCtrlSourceSet NOROM_PowerCtrlSourceSet
+#endif
+
+
+//*****************************************************************************
+//
+// Set (Request) the main power source
+//
+//*****************************************************************************
+void
+PowerCtrlSourceSet(uint32_t ui32PowerConfig)
+{
+ // Check the arguments.
+ ASSERT((ui32PowerConfig == PWRCTRL_PWRSRC_DCDC) ||
+ (ui32PowerConfig == PWRCTRL_PWRSRC_GLDO) ||
+ (ui32PowerConfig == PWRCTRL_PWRSRC_ULDO));
+
+ // Configure the power.
+ if(ui32PowerConfig == PWRCTRL_PWRSRC_DCDC) {
+ HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) |=
+ (AON_PMCTL_PWRCTL_DCDC_EN | AON_PMCTL_PWRCTL_DCDC_ACTIVE);
+ }
+ else if (ui32PowerConfig == PWRCTRL_PWRSRC_GLDO)
+ {
+ HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) &=
+ ~(AON_PMCTL_PWRCTL_DCDC_EN | AON_PMCTL_PWRCTL_DCDC_ACTIVE);
+ }
+ else
+ {
+ PRCMMcuUldoConfigure(true);
+ }
+}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/pwr_ctrl.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/pwr_ctrl.h
new file mode 100644
index 0000000..fe98972
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/pwr_ctrl.h
@@ -0,0 +1,301 @@
+/******************************************************************************
+* Filename: pwr_ctrl.h
+* Revised: 2017-11-02 15:41:14 +0100 (Thu, 02 Nov 2017)
+* Revision: 50165
+*
+* Description: Defines and prototypes for the System Power Control.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup system_control_group
+//! @{
+//! \addtogroup pwrctrl_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __PWR_CTRL_H__
+#define __PWR_CTRL_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "../inc/hw_types.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_ints.h"
+#include "../inc/hw_aon_pmctl.h"
+#include "../inc/hw_aon_rtc.h"
+#include "../inc/hw_adi_2_refsys.h"
+#include "debug.h"
+#include "interrupt.h"
+#include "osc.h"
+#include "cpu.h"
+#include "prcm.h"
+#include "aon_ioc.h"
+#include "adi.h"
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// This section renames all functions that are not "static inline", so that
+// calling these functions will default to implementation in flash. At the end
+// of this file a second renaming will change the defaults to implementation in
+// ROM for available functions.
+//
+// To force use of the implementation in flash, e.g. for debugging:
+// - Globally: Define DRIVERLIB_NOROM at project level
+// - Per function: Use prefix "NOROM_" when calling the function
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #define PowerCtrlSourceSet NOROM_PowerCtrlSourceSet
+#endif
+
+//*****************************************************************************
+//
+// Defines for the system power states
+//
+//*****************************************************************************
+#define PWRCTRL_ACTIVE 0x00000001
+#define PWRCTRL_STANDBY 0x00000002
+#define PWRCTRL_POWER_DOWN 0x00000004
+#define PWRCTRL_SHUTDOWN 0x00000008
+
+//*****************************************************************************
+//
+// Defines for the power configuration in the AON System Control 1.2 V
+//
+//*****************************************************************************
+#define PWRCTRL_IOSEG3_ENABLE 0x00000800
+#define PWRCTRL_IOSEG2_ENABLE 0x00000400
+#define PWRCTRL_IOSEG3_DISABLE 0x00000200
+#define PWRCTRL_IOSEG2_DISABLE 0x00000100
+#define PWRCTRL_PWRSRC_DCDC 0x00000001
+#define PWRCTRL_PWRSRC_GLDO 0x00000000
+#define PWRCTRL_PWRSRC_ULDO 0x00000002
+
+//*****************************************************************************
+//
+// The following are defines for the various reset source for the device.
+//
+//*****************************************************************************
+#define PWRCTRL_RST_POWER_ON 0x00000000 // Reset by power on
+#define PWRCTRL_RST_PIN 0x00000001 // Pin reset
+#define PWRCTRL_RST_VDDS_BOD 0x00000002 // VDDS Brown Out Detect
+#define PWRCTRL_RST_VDD_BOD 0x00000003 // VDD Brown Out Detect
+#define PWRCTRL_RST_VDDR_BOD 0x00000004 // VDDR Brown Out Detect
+#define PWRCTRL_RST_CLK_LOSS 0x00000005 // Clock loss Reset
+#define PWRCTRL_RST_SW_PIN 0x00000006 // SYSRESET or pin reset
+#define PWRCTRL_RST_WARM 0x00000007 // Reset via PRCM warm reset request
+
+//*****************************************************************************
+//
+// API Functions and prototypes
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \brief Set (Request) the main power source.
+//!
+//! \note The system will never allow a switch to the \ref PWRCTRL_PWRSRC_ULDO
+//! when in active mode. This is only allowed when the system is in lower power
+//! mode where no code is executing and no peripherals are active.
+//! Assuming that there is an external capacitor available for the
+//! \ref PWRCTRL_PWRSRC_DCDC the system can dynamically switch back and forth
+//! between the two when in active mode.
+//!
+//! \note The system will automatically switch to the GLDO / DCDC when waking
+//! up from a low power mode.
+//!
+//! \param ui32PowerConfig is a bitmask indicating the target power source.
+//! - \ref PWRCTRL_PWRSRC_DCDC
+//! - \ref PWRCTRL_PWRSRC_GLDO
+//! - \ref PWRCTRL_PWRSRC_ULDO
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void PowerCtrlSourceSet(uint32_t ui32PowerConfig);
+
+//*****************************************************************************
+//
+//! \brief Get the main power source.
+//!
+//! Use this function to retrieve the current active power source.
+//!
+//! When the System CPU is active it can never be powered by uLDO as this
+//! is too weak a power source.
+//!
+//! \note Using the DCDC power supply requires an external inductor.
+//!
+//! \return Returns the main power source.
+//! - \ref PWRCTRL_PWRSRC_DCDC
+//! - \ref PWRCTRL_PWRSRC_GLDO
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+PowerCtrlSourceGet(void)
+{
+ uint32_t ui32PowerConfig;
+
+ // Return the current power source
+ ui32PowerConfig = HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL);
+ if(ui32PowerConfig & AON_PMCTL_PWRCTL_DCDC_ACTIVE)
+ {
+ return (PWRCTRL_PWRSRC_DCDC);
+ }
+ else
+ {
+ return (PWRCTRL_PWRSRC_GLDO);
+ }
+}
+
+//*****************************************************************************
+//
+//! \brief OBSOLETE: Get the last known reset source of the system.
+//!
+//! \deprecated This function will be removed in a future release.
+//! Use \ref SysCtrlResetSourceGet() instead.
+//!
+//! This function returns reset source but does not cover if waking up from shutdown.
+//! This function can be seen as a subset of function \ref SysCtrlResetSourceGet()
+//! and will be removed in a future release.
+//!
+//! \return Returns one of the known reset values.
+//! The possible reset sources are:
+//! - \ref PWRCTRL_RST_POWER_ON
+//! - \ref PWRCTRL_RST_PIN
+//! - \ref PWRCTRL_RST_VDDS_BOD
+//! - \ref PWRCTRL_RST_VDD_BOD
+//! - \ref PWRCTRL_RST_VDDR_BOD
+//! - \ref PWRCTRL_RST_CLK_LOSS
+//! - \ref PWRCTRL_RST_SW_PIN
+//! - \ref PWRCTRL_RST_WARM
+//!
+//! \sa \ref SysCtrlResetSourceGet()
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+PowerCtrlResetSourceGet(void)
+{
+ // Get the reset source.
+ return (( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) &
+ AON_PMCTL_RESETCTL_RESET_SRC_M ) >>
+ AON_PMCTL_RESETCTL_RESET_SRC_S ) ;
+}
+
+//*****************************************************************************
+//
+//! \brief Enables pad sleep in order to latch device outputs before shutdown.
+//!
+//! See \ref SysCtrlShutdown() for more information about how to enter
+//! shutdown and how to wake up from shutdown.
+//!
+//! \return None
+//!
+//! \sa \ref PowerCtrlPadSleepDisable()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+PowerCtrlPadSleepEnable(void)
+{
+ HWREG(AON_PMCTL_BASE + AON_PMCTL_O_SLEEPCTL) = 0;
+ HWREG(AON_RTC_BASE + AON_RTC_O_SYNC);
+}
+
+//*****************************************************************************
+//
+//! \brief Disables pad sleep in order to unlatch device outputs after wakeup from shutdown.
+//!
+//! This function must be called by the application after the device wakes up
+//! from shutdown.
+//!
+//! See \ref SysCtrlShutdown() for more information about how to enter
+//! shutdown and how to wake up from shutdown.
+//!
+//! \return None
+//!
+//! \sa \ref PowerCtrlPadSleepEnable()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+PowerCtrlPadSleepDisable(void)
+{
+ HWREG(AON_PMCTL_BASE + AON_PMCTL_O_SLEEPCTL) = 1;
+ HWREG(AON_RTC_BASE + AON_RTC_O_SYNC);
+}
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// Redirect to implementation in ROM when available.
+//
+//*****************************************************************************
+#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
+ #include "../driverlib/rom.h"
+ #ifdef ROM_PowerCtrlSourceSet
+ #undef PowerCtrlSourceSet
+ #define PowerCtrlSourceSet ROM_PowerCtrlSourceSet
+ #endif
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __PWR_CTRL_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_cmd.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_cmd.h
new file mode 100644
index 0000000..d8517d0
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_cmd.h
@@ -0,0 +1,2674 @@
+/******************************************************************************
+* Filename: rf_ble_cmd.h
+* Revised: 2018-07-31 20:13:42 +0200 (Tue, 31 Jul 2018)
+* Revision: 18572
+*
+* Description: CC13x2/CC26x2 API for Bluetooth Low Energy commands
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __BLE_CMD_H
+#define __BLE_CMD_H
+
+#ifndef __RFC_STRUCT
+#define __RFC_STRUCT
+#endif
+
+#ifndef __RFC_STRUCT_ATTR
+#if defined(__GNUC__)
+#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4)))
+#elif defined(__TI_ARM__)
+#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4)))
+#else
+#define __RFC_STRUCT_ATTR
+#endif
+#endif
+
+//! \addtogroup rfc
+//! @{
+
+//! \addtogroup ble_cmd
+//! @{
+
+#include <stdint.h>
+#include "rf_mailbox.h"
+#include "rf_common_cmd.h"
+
+typedef struct __RFC_STRUCT rfc_bleRadioOp_s rfc_bleRadioOp_t;
+typedef struct __RFC_STRUCT rfc_ble5RadioOp_s rfc_ble5RadioOp_t;
+typedef struct __RFC_STRUCT rfc_ble5Tx20RadioOp_s rfc_ble5Tx20RadioOp_t;
+typedef struct __RFC_STRUCT rfc_CMD_BLE_SLAVE_s rfc_CMD_BLE_SLAVE_t;
+typedef struct __RFC_STRUCT rfc_CMD_BLE_MASTER_s rfc_CMD_BLE_MASTER_t;
+typedef struct __RFC_STRUCT rfc_CMD_BLE_ADV_s rfc_CMD_BLE_ADV_t;
+typedef struct __RFC_STRUCT rfc_CMD_BLE_ADV_DIR_s rfc_CMD_BLE_ADV_DIR_t;
+typedef struct __RFC_STRUCT rfc_CMD_BLE_ADV_NC_s rfc_CMD_BLE_ADV_NC_t;
+typedef struct __RFC_STRUCT rfc_CMD_BLE_ADV_SCAN_s rfc_CMD_BLE_ADV_SCAN_t;
+typedef struct __RFC_STRUCT rfc_CMD_BLE_SCANNER_s rfc_CMD_BLE_SCANNER_t;
+typedef struct __RFC_STRUCT rfc_CMD_BLE_INITIATOR_s rfc_CMD_BLE_INITIATOR_t;
+typedef struct __RFC_STRUCT rfc_CMD_BLE_GENERIC_RX_s rfc_CMD_BLE_GENERIC_RX_t;
+typedef struct __RFC_STRUCT rfc_CMD_BLE_TX_TEST_s rfc_CMD_BLE_TX_TEST_t;
+typedef struct __RFC_STRUCT rfc_CMD_BLE_ADV_PAYLOAD_s rfc_CMD_BLE_ADV_PAYLOAD_t;
+typedef struct __RFC_STRUCT rfc_CMD_BLE5_RADIO_SETUP_s rfc_CMD_BLE5_RADIO_SETUP_t;
+typedef struct __RFC_STRUCT rfc_CMD_BLE5_SLAVE_s rfc_CMD_BLE5_SLAVE_t;
+typedef struct __RFC_STRUCT rfc_CMD_BLE5_MASTER_s rfc_CMD_BLE5_MASTER_t;
+typedef struct __RFC_STRUCT rfc_CMD_BLE5_ADV_EXT_s rfc_CMD_BLE5_ADV_EXT_t;
+typedef struct __RFC_STRUCT rfc_CMD_BLE5_ADV_AUX_s rfc_CMD_BLE5_ADV_AUX_t;
+typedef struct __RFC_STRUCT rfc_CMD_BLE5_SCANNER_s rfc_CMD_BLE5_SCANNER_t;
+typedef struct __RFC_STRUCT rfc_CMD_BLE5_INITIATOR_s rfc_CMD_BLE5_INITIATOR_t;
+typedef struct __RFC_STRUCT rfc_CMD_BLE5_GENERIC_RX_s rfc_CMD_BLE5_GENERIC_RX_t;
+typedef struct __RFC_STRUCT rfc_CMD_BLE5_TX_TEST_s rfc_CMD_BLE5_TX_TEST_t;
+typedef struct __RFC_STRUCT rfc_CMD_BLE5_ADV_s rfc_CMD_BLE5_ADV_t;
+typedef struct __RFC_STRUCT rfc_CMD_BLE5_ADV_DIR_s rfc_CMD_BLE5_ADV_DIR_t;
+typedef struct __RFC_STRUCT rfc_CMD_BLE5_ADV_NC_s rfc_CMD_BLE5_ADV_NC_t;
+typedef struct __RFC_STRUCT rfc_CMD_BLE5_ADV_SCAN_s rfc_CMD_BLE5_ADV_SCAN_t;
+typedef struct __RFC_STRUCT rfc_CMD_BLE5_RADIO_SETUP_PA_s rfc_CMD_BLE5_RADIO_SETUP_PA_t;
+typedef struct __RFC_STRUCT rfc_bleMasterSlavePar_s rfc_bleMasterSlavePar_t;
+typedef struct __RFC_STRUCT rfc_bleSlavePar_s rfc_bleSlavePar_t;
+typedef struct __RFC_STRUCT rfc_bleMasterPar_s rfc_bleMasterPar_t;
+typedef struct __RFC_STRUCT rfc_bleAdvPar_s rfc_bleAdvPar_t;
+typedef struct __RFC_STRUCT rfc_bleScannerPar_s rfc_bleScannerPar_t;
+typedef struct __RFC_STRUCT rfc_bleInitiatorPar_s rfc_bleInitiatorPar_t;
+typedef struct __RFC_STRUCT rfc_bleGenericRxPar_s rfc_bleGenericRxPar_t;
+typedef struct __RFC_STRUCT rfc_bleTxTestPar_s rfc_bleTxTestPar_t;
+typedef struct __RFC_STRUCT rfc_ble5SlavePar_s rfc_ble5SlavePar_t;
+typedef struct __RFC_STRUCT rfc_ble5MasterPar_s rfc_ble5MasterPar_t;
+typedef struct __RFC_STRUCT rfc_ble5AdvExtPar_s rfc_ble5AdvExtPar_t;
+typedef struct __RFC_STRUCT rfc_ble5AdvAuxPar_s rfc_ble5AdvAuxPar_t;
+typedef struct __RFC_STRUCT rfc_ble5AuxChRes_s rfc_ble5AuxChRes_t;
+typedef struct __RFC_STRUCT rfc_ble5ScannerPar_s rfc_ble5ScannerPar_t;
+typedef struct __RFC_STRUCT rfc_ble5InitiatorPar_s rfc_ble5InitiatorPar_t;
+typedef struct __RFC_STRUCT rfc_bleMasterSlaveOutput_s rfc_bleMasterSlaveOutput_t;
+typedef struct __RFC_STRUCT rfc_bleAdvOutput_s rfc_bleAdvOutput_t;
+typedef struct __RFC_STRUCT rfc_bleScannerOutput_s rfc_bleScannerOutput_t;
+typedef struct __RFC_STRUCT rfc_bleInitiatorOutput_s rfc_bleInitiatorOutput_t;
+typedef struct __RFC_STRUCT rfc_ble5ScanInitOutput_s rfc_ble5ScanInitOutput_t;
+typedef struct __RFC_STRUCT rfc_bleGenericRxOutput_s rfc_bleGenericRxOutput_t;
+typedef struct __RFC_STRUCT rfc_bleTxTestOutput_s rfc_bleTxTestOutput_t;
+typedef struct __RFC_STRUCT rfc_ble5ExtAdvEntry_s rfc_ble5ExtAdvEntry_t;
+typedef struct __RFC_STRUCT rfc_bleWhiteListEntry_s rfc_bleWhiteListEntry_t;
+typedef struct __RFC_STRUCT rfc_ble5AdiEntry_s rfc_ble5AdiEntry_t;
+typedef struct __RFC_STRUCT rfc_bleRxStatus_s rfc_bleRxStatus_t;
+typedef struct __RFC_STRUCT rfc_ble5RxStatus_s rfc_ble5RxStatus_t;
+
+//! \addtogroup bleRadioOp
+//! @{
+struct __RFC_STRUCT rfc_bleRadioOp_s {
+ uint16_t commandNo; //!< The command ID number
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint8_t channel; //!< \brief Channel to use<br>
+ //!< 0--39: BLE advertising/data channel index<br>
+ //!< 60--207: Custom frequency; (2300 + <code>channel</code>) MHz<br>
+ //!< 255: Use existing frequency<br>
+ //!< Others: <i>Reserved</i>
+ struct {
+ uint8_t init:7; //!< \brief If <code>bOverride</code> = 1 or custom frequency is used:<br>
+ //!< 0: Do not use whitening<br>
+ //!< Other value: Initialization for 7-bit LFSR whitener
+ uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels<br>
+ //!< 1: Override whitening initialization with value of init
+ } whitening;
+ uint8_t* pParams; //!< Pointer to command specific parameter structure
+ uint8_t* pOutput; //!< Pointer to command specific output structure
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup ble5RadioOp
+//! @{
+struct __RFC_STRUCT rfc_ble5RadioOp_s {
+ uint16_t commandNo; //!< The command ID number
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint8_t channel; //!< \brief Channel to use<br>
+ //!< 0--39: BLE advertising/data channel index<br>
+ //!< 60--207: Custom frequency; (2300 + <code>channel</code>) MHz<br>
+ //!< 255: Use existing frequency<br>
+ //!< Others: <i>Reserved</i>
+ struct {
+ uint8_t init:7; //!< \brief If <code>bOverride</code> = 1 or custom frequency is used:<br>
+ //!< 0: Do not use whitening<br>
+ //!< Other value: Initialization for 7-bit LFSR whitener
+ uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels<br>
+ //!< 1: Override whitening initialization with value of init
+ } whitening;
+ struct {
+ uint8_t mainMode:2; //!< \brief PHY to use:<br>
+ //!< 0: 1 Mbps<br>
+ //!< 1: 2 Mbps<br>
+ //!< 2: Coded<br>
+ //!< 3: <i>Reserved</i>
+ uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected.
+ //!< See the Technical Reference Manual for details.
+ } phyMode;
+ uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS
+ uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup) <br>
+ //!< 0x0000: Use default TX power<br>
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from <code>tx20Power</code> field (command
+ //!< structure that includes <code>tx20Power</code> must be used)
+ uint8_t* pParams; //!< Pointer to command specific parameter structure
+ uint8_t* pOutput; //!< Pointer to command specific output structure
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup ble5Tx20RadioOp
+//! @{
+//! Command structure for Bluetooth commands which includes the optional field for 20-dBm PA TX power
+struct __RFC_STRUCT rfc_ble5Tx20RadioOp_s {
+ uint16_t commandNo; //!< The command ID number
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint8_t channel; //!< \brief Channel to use<br>
+ //!< 0--39: BLE advertising/data channel index<br>
+ //!< 60--207: Custom frequency; (2300 + <code>channel</code>) MHz<br>
+ //!< 255: Use existing frequency<br>
+ //!< Others: <i>Reserved</i>
+ struct {
+ uint8_t init:7; //!< \brief If <code>bOverride</code> = 1 or custom frequency is used:<br>
+ //!< 0: Do not use whitening<br>
+ //!< Other value: Initialization for 7-bit LFSR whitener
+ uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels<br>
+ //!< 1: Override whitening initialization with value of init
+ } whitening;
+ struct {
+ uint8_t mainMode:2; //!< \brief PHY to use:<br>
+ //!< 0: 1 Mbps<br>
+ //!< 1: 2 Mbps<br>
+ //!< 2: Coded<br>
+ //!< 3: <i>Reserved</i>
+ uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected.
+ //!< See the Technical Reference Manual for details.
+ } phyMode;
+ uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS
+ uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup) <br>
+ //!< 0x0000: Use default TX power<br>
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from <code>tx20Power</code> field (command
+ //!< structure that includes <code>tx20Power</code> must be used)
+ uint8_t* pParams; //!< Pointer to command specific parameter structure
+ uint8_t* pOutput; //!< Pointer to command specific output structure
+ uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF:<br>
+ //!< If <code>tx20Power</code> < 0x10000000: Transmit power to use for the 20-dBm PA;
+ //!< overrides the one given in radio setup for the duration of the command. <br>
+ //!< If <code>tx20Power</code> >= 0x10000000: Pointer to PA change override structure
+ //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.<br>
+ //!< For other values of <code>txPower</code>, this field is not accessed by the radio
+ //!< CPU and may be omitted from the structure.
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_BLE_SLAVE
+//! @{
+#define CMD_BLE_SLAVE 0x1801
+//! BLE Slave Command
+struct __RFC_STRUCT rfc_CMD_BLE_SLAVE_s {
+ uint16_t commandNo; //!< The command ID number 0x1801
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint8_t channel; //!< \brief Channel to use<br>
+ //!< 0--39: BLE advertising/data channel index<br>
+ //!< 60--207: Custom frequency; (2300 + <code>channel</code>) MHz<br>
+ //!< 255: Use existing frequency<br>
+ //!< Others: <i>Reserved</i>
+ struct {
+ uint8_t init:7; //!< \brief If <code>bOverride</code> = 1 or custom frequency is used:<br>
+ //!< 0: Do not use whitening<br>
+ //!< Other value: Initialization for 7-bit LFSR whitener
+ uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels<br>
+ //!< 1: Override whitening initialization with value of init
+ } whitening;
+ rfc_bleSlavePar_t *pParams; //!< Pointer to command specific parameter structure
+ rfc_bleMasterSlaveOutput_t *pOutput; //!< Pointer to command specific output structure
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_BLE_MASTER
+//! @{
+#define CMD_BLE_MASTER 0x1802
+//! BLE Master Command
+struct __RFC_STRUCT rfc_CMD_BLE_MASTER_s {
+ uint16_t commandNo; //!< The command ID number 0x1802
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint8_t channel; //!< \brief Channel to use<br>
+ //!< 0--39: BLE advertising/data channel index<br>
+ //!< 60--207: Custom frequency; (2300 + <code>channel</code>) MHz<br>
+ //!< 255: Use existing frequency<br>
+ //!< Others: <i>Reserved</i>
+ struct {
+ uint8_t init:7; //!< \brief If <code>bOverride</code> = 1 or custom frequency is used:<br>
+ //!< 0: Do not use whitening<br>
+ //!< Other value: Initialization for 7-bit LFSR whitener
+ uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels<br>
+ //!< 1: Override whitening initialization with value of init
+ } whitening;
+ rfc_bleMasterPar_t *pParams; //!< Pointer to command specific parameter structure
+ rfc_bleMasterSlaveOutput_t *pOutput; //!< Pointer to command specific output structure
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_BLE_ADV
+//! @{
+#define CMD_BLE_ADV 0x1803
+//! BLE Connectable Undirected Advertiser Command
+struct __RFC_STRUCT rfc_CMD_BLE_ADV_s {
+ uint16_t commandNo; //!< The command ID number 0x1803
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint8_t channel; //!< \brief Channel to use<br>
+ //!< 0--39: BLE advertising/data channel index<br>
+ //!< 60--207: Custom frequency; (2300 + <code>channel</code>) MHz<br>
+ //!< 255: Use existing frequency<br>
+ //!< Others: <i>Reserved</i>
+ struct {
+ uint8_t init:7; //!< \brief If <code>bOverride</code> = 1 or custom frequency is used:<br>
+ //!< 0: Do not use whitening<br>
+ //!< Other value: Initialization for 7-bit LFSR whitener
+ uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels<br>
+ //!< 1: Override whitening initialization with value of init
+ } whitening;
+ rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure
+ rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_BLE_ADV_DIR
+//! @{
+#define CMD_BLE_ADV_DIR 0x1804
+//! BLE Connectable Directed Advertiser Command
+struct __RFC_STRUCT rfc_CMD_BLE_ADV_DIR_s {
+ uint16_t commandNo; //!< The command ID number 0x1804
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint8_t channel; //!< \brief Channel to use<br>
+ //!< 0--39: BLE advertising/data channel index<br>
+ //!< 60--207: Custom frequency; (2300 + <code>channel</code>) MHz<br>
+ //!< 255: Use existing frequency<br>
+ //!< Others: <i>Reserved</i>
+ struct {
+ uint8_t init:7; //!< \brief If <code>bOverride</code> = 1 or custom frequency is used:<br>
+ //!< 0: Do not use whitening<br>
+ //!< Other value: Initialization for 7-bit LFSR whitener
+ uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels<br>
+ //!< 1: Override whitening initialization with value of init
+ } whitening;
+ rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure
+ rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_BLE_ADV_NC
+//! @{
+#define CMD_BLE_ADV_NC 0x1805
+//! BLE Non-Connectable Advertiser Command
+struct __RFC_STRUCT rfc_CMD_BLE_ADV_NC_s {
+ uint16_t commandNo; //!< The command ID number 0x1805
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint8_t channel; //!< \brief Channel to use<br>
+ //!< 0--39: BLE advertising/data channel index<br>
+ //!< 60--207: Custom frequency; (2300 + <code>channel</code>) MHz<br>
+ //!< 255: Use existing frequency<br>
+ //!< Others: <i>Reserved</i>
+ struct {
+ uint8_t init:7; //!< \brief If <code>bOverride</code> = 1 or custom frequency is used:<br>
+ //!< 0: Do not use whitening<br>
+ //!< Other value: Initialization for 7-bit LFSR whitener
+ uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels<br>
+ //!< 1: Override whitening initialization with value of init
+ } whitening;
+ rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure
+ rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_BLE_ADV_SCAN
+//! @{
+#define CMD_BLE_ADV_SCAN 0x1806
+//! BLE Scannable Undirected Advertiser Command
+struct __RFC_STRUCT rfc_CMD_BLE_ADV_SCAN_s {
+ uint16_t commandNo; //!< The command ID number 0x1806
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint8_t channel; //!< \brief Channel to use<br>
+ //!< 0--39: BLE advertising/data channel index<br>
+ //!< 60--207: Custom frequency; (2300 + <code>channel</code>) MHz<br>
+ //!< 255: Use existing frequency<br>
+ //!< Others: <i>Reserved</i>
+ struct {
+ uint8_t init:7; //!< \brief If <code>bOverride</code> = 1 or custom frequency is used:<br>
+ //!< 0: Do not use whitening<br>
+ //!< Other value: Initialization for 7-bit LFSR whitener
+ uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels<br>
+ //!< 1: Override whitening initialization with value of init
+ } whitening;
+ rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure
+ rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_BLE_SCANNER
+//! @{
+#define CMD_BLE_SCANNER 0x1807
+//! BLE Scanner Command
+struct __RFC_STRUCT rfc_CMD_BLE_SCANNER_s {
+ uint16_t commandNo; //!< The command ID number 0x1807
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint8_t channel; //!< \brief Channel to use<br>
+ //!< 0--39: BLE advertising/data channel index<br>
+ //!< 60--207: Custom frequency; (2300 + <code>channel</code>) MHz<br>
+ //!< 255: Use existing frequency<br>
+ //!< Others: <i>Reserved</i>
+ struct {
+ uint8_t init:7; //!< \brief If <code>bOverride</code> = 1 or custom frequency is used:<br>
+ //!< 0: Do not use whitening<br>
+ //!< Other value: Initialization for 7-bit LFSR whitener
+ uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels<br>
+ //!< 1: Override whitening initialization with value of init
+ } whitening;
+ rfc_bleScannerPar_t *pParams; //!< Pointer to command specific parameter structure
+ rfc_bleScannerOutput_t *pOutput; //!< Pointer to command specific output structure
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_BLE_INITIATOR
+//! @{
+#define CMD_BLE_INITIATOR 0x1808
+//! BLE Initiator Command
+struct __RFC_STRUCT rfc_CMD_BLE_INITIATOR_s {
+ uint16_t commandNo; //!< The command ID number 0x1808
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint8_t channel; //!< \brief Channel to use<br>
+ //!< 0--39: BLE advertising/data channel index<br>
+ //!< 60--207: Custom frequency; (2300 + <code>channel</code>) MHz<br>
+ //!< 255: Use existing frequency<br>
+ //!< Others: <i>Reserved</i>
+ struct {
+ uint8_t init:7; //!< \brief If <code>bOverride</code> = 1 or custom frequency is used:<br>
+ //!< 0: Do not use whitening<br>
+ //!< Other value: Initialization for 7-bit LFSR whitener
+ uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels<br>
+ //!< 1: Override whitening initialization with value of init
+ } whitening;
+ rfc_bleInitiatorPar_t *pParams; //!< Pointer to command specific parameter structure
+ rfc_bleInitiatorOutput_t *pOutput; //!< Pointer to command specific output structure
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_BLE_GENERIC_RX
+//! @{
+#define CMD_BLE_GENERIC_RX 0x1809
+//! BLE Generic Receiver Command
+struct __RFC_STRUCT rfc_CMD_BLE_GENERIC_RX_s {
+ uint16_t commandNo; //!< The command ID number 0x1809
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint8_t channel; //!< \brief Channel to use<br>
+ //!< 0--39: BLE advertising/data channel index<br>
+ //!< 60--207: Custom frequency; (2300 + <code>channel</code>) MHz<br>
+ //!< 255: Use existing frequency<br>
+ //!< Others: <i>Reserved</i>
+ struct {
+ uint8_t init:7; //!< \brief If <code>bOverride</code> = 1 or custom frequency is used:<br>
+ //!< 0: Do not use whitening<br>
+ //!< Other value: Initialization for 7-bit LFSR whitener
+ uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels<br>
+ //!< 1: Override whitening initialization with value of init
+ } whitening;
+ rfc_bleGenericRxPar_t *pParams; //!< Pointer to command specific parameter structure
+ rfc_bleGenericRxOutput_t *pOutput; //!< Pointer to command specific output structure
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_BLE_TX_TEST
+//! @{
+#define CMD_BLE_TX_TEST 0x180A
+//! BLE PHY Test Transmitter Command
+struct __RFC_STRUCT rfc_CMD_BLE_TX_TEST_s {
+ uint16_t commandNo; //!< The command ID number 0x180A
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint8_t channel; //!< \brief Channel to use<br>
+ //!< 0--39: BLE advertising/data channel index<br>
+ //!< 60--207: Custom frequency; (2300 + <code>channel</code>) MHz<br>
+ //!< 255: Use existing frequency<br>
+ //!< Others: <i>Reserved</i>
+ struct {
+ uint8_t init:7; //!< \brief If <code>bOverride</code> = 1 or custom frequency is used:<br>
+ //!< 0: Do not use whitening<br>
+ //!< Other value: Initialization for 7-bit LFSR whitener
+ uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels<br>
+ //!< 1: Override whitening initialization with value of init
+ } whitening;
+ rfc_bleTxTestPar_t *pParams; //!< Pointer to command specific parameter structure
+ rfc_bleTxTestOutput_t *pOutput; //!< Pointer to command specific output structure
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_BLE_ADV_PAYLOAD
+//! @{
+#define CMD_BLE_ADV_PAYLOAD 0x1001
+//! BLE Update Advertising Payload Command
+struct __RFC_STRUCT rfc_CMD_BLE_ADV_PAYLOAD_s {
+ uint16_t commandNo; //!< The command ID number 0x1001
+ uint8_t payloadType; //!< \brief 0: Advertising data<br>
+ //!< 1: Scan response data
+ uint8_t newLen; //!< Length of the new payload
+ uint8_t* pNewData; //!< Pointer to the buffer containing the new data
+ rfc_bleAdvPar_t *pParams; //!< Pointer to the parameter structure to update
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_BLE5_RADIO_SETUP
+//! @{
+#define CMD_BLE5_RADIO_SETUP 0x1820
+//! Bluetooth 5 Radio Setup Command for all PHYs
+struct __RFC_STRUCT rfc_CMD_BLE5_RADIO_SETUP_s {
+ uint16_t commandNo; //!< The command ID number 0x1820
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ struct {
+ uint8_t mainMode:2; //!< \brief PHY to use for non-BLE commands:<br>
+ //!< 0: 1 Mbps<br>
+ //!< 1: 2 Mbps<br>
+ //!< 2: Coded<br>
+ //!< 3: <i>Reserved</i>
+ uint8_t coding:1; //!< \brief Coding to use for TX if coded PHY is selected for non-BLE commands<br>
+ //!< 0: S = 8 (125 kbps)<br>
+ //!< 1: S = 2 (500 kbps)
+ } defaultPhy;
+ uint8_t loDivider; //!< LO divider setting to use. Supported values: 0 or 2.
+ struct {
+ uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode<br>
+ //!< 0x01: Single-ended mode RFP<br>
+ //!< 0x02: Single-ended mode RFN<br>
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)<br>
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)<br>
+ //!< Others: <i>Reserved</i>
+ uint16_t biasMode:1; //!< \brief 0: Internal bias<br>
+ //!< 1: External bias
+ uint16_t analogCfgMode:6; //!< \brief 0x00: Write analog configuration.<br>
+ //!< Required first time after boot and when changing frequency band
+ //!< or front-end configuration<br>
+ //!< 0x2D: Keep analog configuration.<br>
+ //!< May be used after standby or when changing mode with the same frequency
+ //!< band and front-end configuration<br>
+ //!< Others: <i>Reserved</i>
+ uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth<br>
+ //!< 1: Do not power up frequency synth
+ } config; //!< Configuration options
+ uint16_t txPower; //!< Default transmit power
+ uint32_t* pRegOverrideCommon; //!< \brief Pointer to a list of hardware and configuration registers to override during common
+ //!< initialization. If NULL, no override is used.
+ uint32_t* pRegOverride1Mbps; //!< \brief Pointer to a list of hardware and configuration registers to override when selecting
+ //!< 1 Mbps PHY mode. If NULL, no override is used.
+ uint32_t* pRegOverride2Mbps; //!< \brief Pointer to a list of hardware and configuration registers to override when selecting
+ //!< 2 Mbps PHY mode. If NULL, no override is used.
+ uint32_t* pRegOverrideCoded; //!< \brief Pointer to a list of hardware and configuration registers to override when selecting
+ //!< coded PHY mode. If NULL, no override is used.
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_BLE5_SLAVE
+//! @{
+#define CMD_BLE5_SLAVE 0x1821
+//! Bluetooth 5 Slave Command
+struct __RFC_STRUCT rfc_CMD_BLE5_SLAVE_s {
+ uint16_t commandNo; //!< The command ID number 0x1821
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint8_t channel; //!< \brief Channel to use<br>
+ //!< 0--39: BLE advertising/data channel index<br>
+ //!< 60--207: Custom frequency; (2300 + <code>channel</code>) MHz<br>
+ //!< 255: Use existing frequency<br>
+ //!< Others: <i>Reserved</i>
+ struct {
+ uint8_t init:7; //!< \brief If <code>bOverride</code> = 1 or custom frequency is used:<br>
+ //!< 0: Do not use whitening<br>
+ //!< Other value: Initialization for 7-bit LFSR whitener
+ uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels<br>
+ //!< 1: Override whitening initialization with value of init
+ } whitening;
+ struct {
+ uint8_t mainMode:2; //!< \brief PHY to use:<br>
+ //!< 0: 1 Mbps<br>
+ //!< 1: 2 Mbps<br>
+ //!< 2: Coded<br>
+ //!< 3: <i>Reserved</i>
+ uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected.
+ //!< See the Technical Reference Manual for details.
+ } phyMode;
+ uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS
+ uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup) <br>
+ //!< 0x0000: Use default TX power<br>
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from <code>tx20Power</code> field (command
+ //!< structure that includes <code>tx20Power</code> must be used)
+ rfc_ble5SlavePar_t *pParams; //!< Pointer to command specific parameter structure
+ rfc_bleMasterSlaveOutput_t *pOutput; //!< Pointer to command specific output structure
+ uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF:<br>
+ //!< If <code>tx20Power</code> < 0x10000000: Transmit power to use for the 20-dBm PA;
+ //!< overrides the one given in radio setup for the duration of the command. <br>
+ //!< If <code>tx20Power</code> >= 0x10000000: Pointer to PA change override structure
+ //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.<br>
+ //!< For other values of <code>txPower</code>, this field is not accessed by the radio
+ //!< CPU and may be omitted from the structure.
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_BLE5_MASTER
+//! @{
+#define CMD_BLE5_MASTER 0x1822
+//! Bluetooth 5 Master Command
+struct __RFC_STRUCT rfc_CMD_BLE5_MASTER_s {
+ uint16_t commandNo; //!< The command ID number 0x1822
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint8_t channel; //!< \brief Channel to use<br>
+ //!< 0--39: BLE advertising/data channel index<br>
+ //!< 60--207: Custom frequency; (2300 + <code>channel</code>) MHz<br>
+ //!< 255: Use existing frequency<br>
+ //!< Others: <i>Reserved</i>
+ struct {
+ uint8_t init:7; //!< \brief If <code>bOverride</code> = 1 or custom frequency is used:<br>
+ //!< 0: Do not use whitening<br>
+ //!< Other value: Initialization for 7-bit LFSR whitener
+ uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels<br>
+ //!< 1: Override whitening initialization with value of init
+ } whitening;
+ struct {
+ uint8_t mainMode:2; //!< \brief PHY to use:<br>
+ //!< 0: 1 Mbps<br>
+ //!< 1: 2 Mbps<br>
+ //!< 2: Coded<br>
+ //!< 3: <i>Reserved</i>
+ uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected.
+ //!< See the Technical Reference Manual for details.
+ } phyMode;
+ uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS
+ uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup) <br>
+ //!< 0x0000: Use default TX power<br>
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from <code>tx20Power</code> field (command
+ //!< structure that includes <code>tx20Power</code> must be used)
+ rfc_ble5MasterPar_t *pParams; //!< Pointer to command specific parameter structure
+ rfc_bleMasterSlaveOutput_t *pOutput; //!< Pointer to command specific output structure
+ uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF:<br>
+ //!< If <code>tx20Power</code> < 0x10000000: Transmit power to use for the 20-dBm PA;
+ //!< overrides the one given in radio setup for the duration of the command. <br>
+ //!< If <code>tx20Power</code> >= 0x10000000: Pointer to PA change override structure
+ //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.<br>
+ //!< For other values of <code>txPower</code>, this field is not accessed by the radio
+ //!< CPU and may be omitted from the structure.
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_BLE5_ADV_EXT
+//! @{
+#define CMD_BLE5_ADV_EXT 0x1823
+//! Bluetooth 5 Extended Advertiser Command
+struct __RFC_STRUCT rfc_CMD_BLE5_ADV_EXT_s {
+ uint16_t commandNo; //!< The command ID number 0x1823
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint8_t channel; //!< \brief Channel to use<br>
+ //!< 0--39: BLE advertising/data channel index<br>
+ //!< 60--207: Custom frequency; (2300 + <code>channel</code>) MHz<br>
+ //!< 255: Use existing frequency<br>
+ //!< Others: <i>Reserved</i>
+ struct {
+ uint8_t init:7; //!< \brief If <code>bOverride</code> = 1 or custom frequency is used:<br>
+ //!< 0: Do not use whitening<br>
+ //!< Other value: Initialization for 7-bit LFSR whitener
+ uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels<br>
+ //!< 1: Override whitening initialization with value of init
+ } whitening;
+ struct {
+ uint8_t mainMode:2; //!< \brief PHY to use:<br>
+ //!< 0: 1 Mbps<br>
+ //!< 1: 2 Mbps<br>
+ //!< 2: Coded<br>
+ //!< 3: <i>Reserved</i>
+ uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected.
+ //!< See the Technical Reference Manual for details.
+ } phyMode;
+ uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS
+ uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup) <br>
+ //!< 0x0000: Use default TX power<br>
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from <code>tx20Power</code> field (command
+ //!< structure that includes <code>tx20Power</code> must be used)
+ rfc_ble5AdvExtPar_t *pParams; //!< Pointer to command specific parameter structure
+ rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure
+ uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF:<br>
+ //!< If <code>tx20Power</code> < 0x10000000: Transmit power to use for the 20-dBm PA;
+ //!< overrides the one given in radio setup for the duration of the command. <br>
+ //!< If <code>tx20Power</code> >= 0x10000000: Pointer to PA change override structure
+ //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.<br>
+ //!< For other values of <code>txPower</code>, this field is not accessed by the radio
+ //!< CPU and may be omitted from the structure.
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_BLE5_ADV_AUX
+//! @{
+#define CMD_BLE5_ADV_AUX 0x1824
+//! Bluetooth 5 Secondary Channel Advertiser Command
+struct __RFC_STRUCT rfc_CMD_BLE5_ADV_AUX_s {
+ uint16_t commandNo; //!< The command ID number 0x1824
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint8_t channel; //!< \brief Channel to use<br>
+ //!< 0--39: BLE advertising/data channel index<br>
+ //!< 60--207: Custom frequency; (2300 + <code>channel</code>) MHz<br>
+ //!< 255: Use existing frequency<br>
+ //!< Others: <i>Reserved</i>
+ struct {
+ uint8_t init:7; //!< \brief If <code>bOverride</code> = 1 or custom frequency is used:<br>
+ //!< 0: Do not use whitening<br>
+ //!< Other value: Initialization for 7-bit LFSR whitener
+ uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels<br>
+ //!< 1: Override whitening initialization with value of init
+ } whitening;
+ struct {
+ uint8_t mainMode:2; //!< \brief PHY to use:<br>
+ //!< 0: 1 Mbps<br>
+ //!< 1: 2 Mbps<br>
+ //!< 2: Coded<br>
+ //!< 3: <i>Reserved</i>
+ uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected.
+ //!< See the Technical Reference Manual for details.
+ } phyMode;
+ uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS
+ uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup) <br>
+ //!< 0x0000: Use default TX power<br>
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from <code>tx20Power</code> field (command
+ //!< structure that includes <code>tx20Power</code> must be used)
+ rfc_ble5AdvAuxPar_t *pParams; //!< Pointer to command specific parameter structure
+ rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure
+ uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF:<br>
+ //!< If <code>tx20Power</code> < 0x10000000: Transmit power to use for the 20-dBm PA;
+ //!< overrides the one given in radio setup for the duration of the command. <br>
+ //!< If <code>tx20Power</code> >= 0x10000000: Pointer to PA change override structure
+ //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.<br>
+ //!< For other values of <code>txPower</code>, this field is not accessed by the radio
+ //!< CPU and may be omitted from the structure.
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_BLE5_SCANNER
+//! @{
+#define CMD_BLE5_SCANNER 0x1827
+//! Bluetooth 5 Scanner Command
+struct __RFC_STRUCT rfc_CMD_BLE5_SCANNER_s {
+ uint16_t commandNo; //!< The command ID number 0x1827
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint8_t channel; //!< \brief Channel to use<br>
+ //!< 0--39: BLE advertising/data channel index<br>
+ //!< 60--207: Custom frequency; (2300 + <code>channel</code>) MHz<br>
+ //!< 255: Use existing frequency<br>
+ //!< Others: <i>Reserved</i>
+ struct {
+ uint8_t init:7; //!< \brief If <code>bOverride</code> = 1 or custom frequency is used:<br>
+ //!< 0: Do not use whitening<br>
+ //!< Other value: Initialization for 7-bit LFSR whitener
+ uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels<br>
+ //!< 1: Override whitening initialization with value of init
+ } whitening;
+ struct {
+ uint8_t mainMode:2; //!< \brief PHY to use:<br>
+ //!< 0: 1 Mbps<br>
+ //!< 1: 2 Mbps<br>
+ //!< 2: Coded<br>
+ //!< 3: <i>Reserved</i>
+ uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected.
+ //!< See the Technical Reference Manual for details.
+ } phyMode;
+ uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS
+ uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup) <br>
+ //!< 0x0000: Use default TX power<br>
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from <code>tx20Power</code> field (command
+ //!< structure that includes <code>tx20Power</code> must be used)
+ rfc_ble5ScannerPar_t *pParams; //!< Pointer to command specific parameter structure
+ rfc_ble5ScanInitOutput_t *pOutput; //!< Pointer to command specific output structure
+ uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF:<br>
+ //!< If <code>tx20Power</code> < 0x10000000: Transmit power to use for the 20-dBm PA;
+ //!< overrides the one given in radio setup for the duration of the command. <br>
+ //!< If <code>tx20Power</code> >= 0x10000000: Pointer to PA change override structure
+ //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.<br>
+ //!< For other values of <code>txPower</code>, this field is not accessed by the radio
+ //!< CPU and may be omitted from the structure.
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_BLE5_INITIATOR
+//! @{
+#define CMD_BLE5_INITIATOR 0x1828
+//! Bluetooth 5 Initiator Command
+struct __RFC_STRUCT rfc_CMD_BLE5_INITIATOR_s {
+ uint16_t commandNo; //!< The command ID number 0x1828
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint8_t channel; //!< \brief Channel to use<br>
+ //!< 0--39: BLE advertising/data channel index<br>
+ //!< 60--207: Custom frequency; (2300 + <code>channel</code>) MHz<br>
+ //!< 255: Use existing frequency<br>
+ //!< Others: <i>Reserved</i>
+ struct {
+ uint8_t init:7; //!< \brief If <code>bOverride</code> = 1 or custom frequency is used:<br>
+ //!< 0: Do not use whitening<br>
+ //!< Other value: Initialization for 7-bit LFSR whitener
+ uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels<br>
+ //!< 1: Override whitening initialization with value of init
+ } whitening;
+ struct {
+ uint8_t mainMode:2; //!< \brief PHY to use:<br>
+ //!< 0: 1 Mbps<br>
+ //!< 1: 2 Mbps<br>
+ //!< 2: Coded<br>
+ //!< 3: <i>Reserved</i>
+ uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected.
+ //!< See the Technical Reference Manual for details.
+ } phyMode;
+ uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS
+ uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup) <br>
+ //!< 0x0000: Use default TX power<br>
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from <code>tx20Power</code> field (command
+ //!< structure that includes <code>tx20Power</code> must be used)
+ rfc_ble5InitiatorPar_t *pParams; //!< Pointer to command specific parameter structure
+ rfc_ble5ScanInitOutput_t *pOutput; //!< Pointer to command specific output structure
+ uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF:<br>
+ //!< If <code>tx20Power</code> < 0x10000000: Transmit power to use for the 20-dBm PA;
+ //!< overrides the one given in radio setup for the duration of the command. <br>
+ //!< If <code>tx20Power</code> >= 0x10000000: Pointer to PA change override structure
+ //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.<br>
+ //!< For other values of <code>txPower</code>, this field is not accessed by the radio
+ //!< CPU and may be omitted from the structure.
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_BLE5_GENERIC_RX
+//! @{
+#define CMD_BLE5_GENERIC_RX 0x1829
+//! Bluetooth 5 Generic Receiver Command
+struct __RFC_STRUCT rfc_CMD_BLE5_GENERIC_RX_s {
+ uint16_t commandNo; //!< The command ID number 0x1829
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint8_t channel; //!< \brief Channel to use<br>
+ //!< 0--39: BLE advertising/data channel index<br>
+ //!< 60--207: Custom frequency; (2300 + <code>channel</code>) MHz<br>
+ //!< 255: Use existing frequency<br>
+ //!< Others: <i>Reserved</i>
+ struct {
+ uint8_t init:7; //!< \brief If <code>bOverride</code> = 1 or custom frequency is used:<br>
+ //!< 0: Do not use whitening<br>
+ //!< Other value: Initialization for 7-bit LFSR whitener
+ uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels<br>
+ //!< 1: Override whitening initialization with value of init
+ } whitening;
+ struct {
+ uint8_t mainMode:2; //!< \brief PHY to use:<br>
+ //!< 0: 1 Mbps<br>
+ //!< 1: 2 Mbps<br>
+ //!< 2: Coded<br>
+ //!< 3: <i>Reserved</i>
+ uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected.
+ //!< See the Technical Reference Manual for details.
+ } phyMode;
+ uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS
+ uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup) <br>
+ //!< 0x0000: Use default TX power<br>
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from <code>tx20Power</code> field (command
+ //!< structure that includes <code>tx20Power</code> must be used)
+ rfc_bleGenericRxPar_t *pParams; //!< Pointer to command specific parameter structure
+ rfc_bleGenericRxOutput_t *pOutput; //!< Pointer to command specific output structure
+ uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF:<br>
+ //!< If <code>tx20Power</code> < 0x10000000: Transmit power to use for the 20-dBm PA;
+ //!< overrides the one given in radio setup for the duration of the command. <br>
+ //!< If <code>tx20Power</code> >= 0x10000000: Pointer to PA change override structure
+ //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.<br>
+ //!< For other values of <code>txPower</code>, this field is not accessed by the radio
+ //!< CPU and may be omitted from the structure.
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_BLE5_TX_TEST
+//! @{
+#define CMD_BLE5_TX_TEST 0x182A
+//! Bluetooth 5 PHY Test Transmitter Command
+struct __RFC_STRUCT rfc_CMD_BLE5_TX_TEST_s {
+ uint16_t commandNo; //!< The command ID number 0x182A
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint8_t channel; //!< \brief Channel to use<br>
+ //!< 0--39: BLE advertising/data channel index<br>
+ //!< 60--207: Custom frequency; (2300 + <code>channel</code>) MHz<br>
+ //!< 255: Use existing frequency<br>
+ //!< Others: <i>Reserved</i>
+ struct {
+ uint8_t init:7; //!< \brief If <code>bOverride</code> = 1 or custom frequency is used:<br>
+ //!< 0: Do not use whitening<br>
+ //!< Other value: Initialization for 7-bit LFSR whitener
+ uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels<br>
+ //!< 1: Override whitening initialization with value of init
+ } whitening;
+ struct {
+ uint8_t mainMode:2; //!< \brief PHY to use:<br>
+ //!< 0: 1 Mbps<br>
+ //!< 1: 2 Mbps<br>
+ //!< 2: Coded<br>
+ //!< 3: <i>Reserved</i>
+ uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected.
+ //!< See the Technical Reference Manual for details.
+ } phyMode;
+ uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS
+ uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup) <br>
+ //!< 0x0000: Use default TX power<br>
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from <code>tx20Power</code> field (command
+ //!< structure that includes <code>tx20Power</code> must be used)
+ rfc_bleTxTestPar_t *pParams; //!< Pointer to command specific parameter structure
+ rfc_bleTxTestOutput_t *pOutput; //!< Pointer to command specific output structure
+ uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF:<br>
+ //!< If <code>tx20Power</code> < 0x10000000: Transmit power to use for the 20-dBm PA;
+ //!< overrides the one given in radio setup for the duration of the command. <br>
+ //!< If <code>tx20Power</code> >= 0x10000000: Pointer to PA change override structure
+ //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.<br>
+ //!< For other values of <code>txPower</code>, this field is not accessed by the radio
+ //!< CPU and may be omitted from the structure.
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_BLE5_ADV
+//! @{
+#define CMD_BLE5_ADV 0x182B
+//! Bluetooth 5 Connectable Undirected Advertiser Command
+struct __RFC_STRUCT rfc_CMD_BLE5_ADV_s {
+ uint16_t commandNo; //!< The command ID number 0x182B
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint8_t channel; //!< \brief Channel to use<br>
+ //!< 0--39: BLE advertising/data channel index<br>
+ //!< 60--207: Custom frequency; (2300 + <code>channel</code>) MHz<br>
+ //!< 255: Use existing frequency<br>
+ //!< Others: <i>Reserved</i>
+ struct {
+ uint8_t init:7; //!< \brief If <code>bOverride</code> = 1 or custom frequency is used:<br>
+ //!< 0: Do not use whitening<br>
+ //!< Other value: Initialization for 7-bit LFSR whitener
+ uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels<br>
+ //!< 1: Override whitening initialization with value of init
+ } whitening;
+ struct {
+ uint8_t mainMode:2; //!< \brief PHY to use:<br>
+ //!< 0: 1 Mbps<br>
+ //!< 1: 2 Mbps<br>
+ //!< 2: Coded<br>
+ //!< 3: <i>Reserved</i>
+ uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected.
+ //!< See the Technical Reference Manual for details.
+ } phyMode;
+ uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS
+ uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup) <br>
+ //!< 0x0000: Use default TX power<br>
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from <code>tx20Power</code> field (command
+ //!< structure that includes <code>tx20Power</code> must be used)
+ rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure
+ rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure
+ uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF:<br>
+ //!< If <code>tx20Power</code> < 0x10000000: Transmit power to use for the 20-dBm PA;
+ //!< overrides the one given in radio setup for the duration of the command. <br>
+ //!< If <code>tx20Power</code> >= 0x10000000: Pointer to PA change override structure
+ //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.<br>
+ //!< For other values of <code>txPower</code>, this field is not accessed by the radio
+ //!< CPU and may be omitted from the structure.
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_BLE5_ADV_DIR
+//! @{
+#define CMD_BLE5_ADV_DIR 0x182C
+//! Bluetooth 5 Connectable Directed Advertiser Command
+struct __RFC_STRUCT rfc_CMD_BLE5_ADV_DIR_s {
+ uint16_t commandNo; //!< The command ID number 0x182C
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint8_t channel; //!< \brief Channel to use<br>
+ //!< 0--39: BLE advertising/data channel index<br>
+ //!< 60--207: Custom frequency; (2300 + <code>channel</code>) MHz<br>
+ //!< 255: Use existing frequency<br>
+ //!< Others: <i>Reserved</i>
+ struct {
+ uint8_t init:7; //!< \brief If <code>bOverride</code> = 1 or custom frequency is used:<br>
+ //!< 0: Do not use whitening<br>
+ //!< Other value: Initialization for 7-bit LFSR whitener
+ uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels<br>
+ //!< 1: Override whitening initialization with value of init
+ } whitening;
+ struct {
+ uint8_t mainMode:2; //!< \brief PHY to use:<br>
+ //!< 0: 1 Mbps<br>
+ //!< 1: 2 Mbps<br>
+ //!< 2: Coded<br>
+ //!< 3: <i>Reserved</i>
+ uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected.
+ //!< See the Technical Reference Manual for details.
+ } phyMode;
+ uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS
+ uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup) <br>
+ //!< 0x0000: Use default TX power<br>
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from <code>tx20Power</code> field (command
+ //!< structure that includes <code>tx20Power</code> must be used)
+ rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure
+ rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure
+ uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF:<br>
+ //!< If <code>tx20Power</code> < 0x10000000: Transmit power to use for the 20-dBm PA;
+ //!< overrides the one given in radio setup for the duration of the command. <br>
+ //!< If <code>tx20Power</code> >= 0x10000000: Pointer to PA change override structure
+ //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.<br>
+ //!< For other values of <code>txPower</code>, this field is not accessed by the radio
+ //!< CPU and may be omitted from the structure.
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_BLE5_ADV_NC
+//! @{
+#define CMD_BLE5_ADV_NC 0x182D
+//! Bluetooth 5 Non-Connectable Advertiser Command
+struct __RFC_STRUCT rfc_CMD_BLE5_ADV_NC_s {
+ uint16_t commandNo; //!< The command ID number 0x182D
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint8_t channel; //!< \brief Channel to use<br>
+ //!< 0--39: BLE advertising/data channel index<br>
+ //!< 60--207: Custom frequency; (2300 + <code>channel</code>) MHz<br>
+ //!< 255: Use existing frequency<br>
+ //!< Others: <i>Reserved</i>
+ struct {
+ uint8_t init:7; //!< \brief If <code>bOverride</code> = 1 or custom frequency is used:<br>
+ //!< 0: Do not use whitening<br>
+ //!< Other value: Initialization for 7-bit LFSR whitener
+ uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels<br>
+ //!< 1: Override whitening initialization with value of init
+ } whitening;
+ struct {
+ uint8_t mainMode:2; //!< \brief PHY to use:<br>
+ //!< 0: 1 Mbps<br>
+ //!< 1: 2 Mbps<br>
+ //!< 2: Coded<br>
+ //!< 3: <i>Reserved</i>
+ uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected.
+ //!< See the Technical Reference Manual for details.
+ } phyMode;
+ uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS
+ uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup) <br>
+ //!< 0x0000: Use default TX power<br>
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from <code>tx20Power</code> field (command
+ //!< structure that includes <code>tx20Power</code> must be used)
+ rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure
+ rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure
+ uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF:<br>
+ //!< If <code>tx20Power</code> < 0x10000000: Transmit power to use for the 20-dBm PA;
+ //!< overrides the one given in radio setup for the duration of the command. <br>
+ //!< If <code>tx20Power</code> >= 0x10000000: Pointer to PA change override structure
+ //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.<br>
+ //!< For other values of <code>txPower</code>, this field is not accessed by the radio
+ //!< CPU and may be omitted from the structure.
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_BLE5_ADV_SCAN
+//! @{
+#define CMD_BLE5_ADV_SCAN 0x182E
+//! Bluetooth 5 Scannable Undirected Advertiser Command
+struct __RFC_STRUCT rfc_CMD_BLE5_ADV_SCAN_s {
+ uint16_t commandNo; //!< The command ID number 0x182E
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint8_t channel; //!< \brief Channel to use<br>
+ //!< 0--39: BLE advertising/data channel index<br>
+ //!< 60--207: Custom frequency; (2300 + <code>channel</code>) MHz<br>
+ //!< 255: Use existing frequency<br>
+ //!< Others: <i>Reserved</i>
+ struct {
+ uint8_t init:7; //!< \brief If <code>bOverride</code> = 1 or custom frequency is used:<br>
+ //!< 0: Do not use whitening<br>
+ //!< Other value: Initialization for 7-bit LFSR whitener
+ uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels<br>
+ //!< 1: Override whitening initialization with value of init
+ } whitening;
+ struct {
+ uint8_t mainMode:2; //!< \brief PHY to use:<br>
+ //!< 0: 1 Mbps<br>
+ //!< 1: 2 Mbps<br>
+ //!< 2: Coded<br>
+ //!< 3: <i>Reserved</i>
+ uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected.
+ //!< See the Technical Reference Manual for details.
+ } phyMode;
+ uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS
+ uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup) <br>
+ //!< 0x0000: Use default TX power<br>
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from <code>tx20Power</code> field (command
+ //!< structure that includes <code>tx20Power</code> must be used)
+ rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure
+ rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure
+ uint32_t tx20Power; //!< \brief If <code>txPower</code> = 0xFFFF:<br>
+ //!< If <code>tx20Power</code> < 0x10000000: Transmit power to use for the 20-dBm PA;
+ //!< overrides the one given in radio setup for the duration of the command. <br>
+ //!< If <code>tx20Power</code> >= 0x10000000: Pointer to PA change override structure
+ //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.<br>
+ //!< For other values of <code>txPower</code>, this field is not accessed by the radio
+ //!< CPU and may be omitted from the structure.
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_BLE5_RADIO_SETUP_PA
+//! @{
+//! Bluetooth 5 Radio Setup Command for all PHYs with PA Switching Fields
+struct __RFC_STRUCT rfc_CMD_BLE5_RADIO_SETUP_PA_s {
+ uint16_t commandNo; //!< The command ID number
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ struct {
+ uint8_t mainMode:2; //!< \brief PHY to use for non-BLE commands:<br>
+ //!< 0: 1 Mbps<br>
+ //!< 1: 2 Mbps<br>
+ //!< 2: Coded<br>
+ //!< 3: <i>Reserved</i>
+ uint8_t coding:1; //!< \brief Coding to use for TX if coded PHY is selected for non-BLE commands<br>
+ //!< 0: S = 8 (125 kbps)<br>
+ //!< 1: S = 2 (500 kbps)
+ } defaultPhy;
+ uint8_t loDivider; //!< LO divider setting to use. Supported values: 0 or 2.
+ struct {
+ uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode<br>
+ //!< 0x01: Single-ended mode RFP<br>
+ //!< 0x02: Single-ended mode RFN<br>
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)<br>
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)<br>
+ //!< Others: <i>Reserved</i>
+ uint16_t biasMode:1; //!< \brief 0: Internal bias<br>
+ //!< 1: External bias
+ uint16_t analogCfgMode:6; //!< \brief 0x00: Write analog configuration.<br>
+ //!< Required first time after boot and when changing frequency band
+ //!< or front-end configuration<br>
+ //!< 0x2D: Keep analog configuration.<br>
+ //!< May be used after standby or when changing mode with the same frequency
+ //!< band and front-end configuration<br>
+ //!< Others: <i>Reserved</i>
+ uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth<br>
+ //!< 1: Do not power up frequency synth
+ } config; //!< Configuration options
+ uint16_t txPower; //!< Default transmit power
+ uint32_t* pRegOverrideCommon; //!< \brief Pointer to a list of hardware and configuration registers to override during common
+ //!< initialization. If NULL, no override is used.
+ uint32_t* pRegOverride1Mbps; //!< \brief Pointer to a list of hardware and configuration registers to override when selecting
+ //!< 1 Mbps PHY mode. If NULL, no override is used.
+ uint32_t* pRegOverride2Mbps; //!< \brief Pointer to a list of hardware and configuration registers to override when selecting
+ //!< 2 Mbps PHY mode. If NULL, no override is used.
+ uint32_t* pRegOverrideCoded; //!< \brief Pointer to a list of hardware and configuration registers to override when selecting
+ //!< coded PHY mode. If NULL, no override is used.
+ uint32_t* pRegOverrideTxStd; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to
+ //!< standard PA. Used by RF driver only, not radio CPU.
+ uint32_t* pRegOverrideTx20; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to
+ //!< 20-dBm PA. Used by RF driver only, not radio CPU.
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup bleMasterSlavePar
+//! @{
+struct __RFC_STRUCT rfc_bleMasterSlavePar_s {
+ dataQueue_t* pRxQ; //!< Pointer to receive queue
+ dataQueue_t* pTxQ; //!< Pointer to transmit queue
+ struct {
+ uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue
+ uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue
+ uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue
+ uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it
+ uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it
+ uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue
+ uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue
+ uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue
+ } rxConfig; //!< Configuration bits for the receive queue entries
+ struct {
+ uint8_t lastRxSn:1; //!< The SN bit of the header of the last packet received with CRC OK
+ uint8_t lastTxSn:1; //!< The SN bit of the header of the last transmitted packet
+ uint8_t nextTxSn:1; //!< The SN bit of the header of the next packet to transmit
+ uint8_t bFirstPkt:1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise
+ uint8_t bAutoEmpty:1; //!< 1 if the last transmitted packet was an auto-empty packet
+ uint8_t bLlCtrlTx:1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11)
+ uint8_t bLlCtrlAckRx:1; //!< 1 if the last received packet was the ACK of an LL control packet
+ uint8_t bLlCtrlAckPending:1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed
+ } seqStat; //!< Sequence number status
+ uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit
+ uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit
+ uint32_t accessAddress; //!< Access address used on the connection
+ uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte
+ uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte
+ uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup bleSlavePar
+//! @{
+//! Parameter structure for legacy slave (CMD_BLE_SLAVE)
+
+struct __RFC_STRUCT rfc_bleSlavePar_s {
+ dataQueue_t* pRxQ; //!< Pointer to receive queue
+ dataQueue_t* pTxQ; //!< Pointer to transmit queue
+ struct {
+ uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue
+ uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue
+ uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue
+ uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it
+ uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it
+ uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue
+ uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue
+ uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue
+ } rxConfig; //!< Configuration bits for the receive queue entries
+ struct {
+ uint8_t lastRxSn:1; //!< The SN bit of the header of the last packet received with CRC OK
+ uint8_t lastTxSn:1; //!< The SN bit of the header of the last transmitted packet
+ uint8_t nextTxSn:1; //!< The SN bit of the header of the next packet to transmit
+ uint8_t bFirstPkt:1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise
+ uint8_t bAutoEmpty:1; //!< 1 if the last transmitted packet was an auto-empty packet
+ uint8_t bLlCtrlTx:1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11)
+ uint8_t bLlCtrlAckRx:1; //!< 1 if the last received packet was the ACK of an LL control packet
+ uint8_t bLlCtrlAckPending:1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed
+ } seqStat; //!< Sequence number status
+ uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit
+ uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit
+ uint32_t accessAddress; //!< Access address used on the connection
+ uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte
+ uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte
+ uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } timeoutTrigger; //!< Trigger that defines timeout of the first receive operation
+ ratmr_t timeoutTime; //!< \brief Time used together with <code>timeoutTrigger</code> that defines timeout of the first
+ //!< receive operation
+ uint16_t __dummy0;
+ uint8_t __dummy1;
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } endTrigger; //!< Trigger that causes the device to end the connection event as soon as allowed
+ ratmr_t endTime; //!< \brief Time used together with <code>endTrigger</code> that causes the device to end the
+ //!< connection event as soon as allowed
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup bleMasterPar
+//! @{
+//! Parameter structure for legacy master (CMD_BLE_MASTER)
+
+struct __RFC_STRUCT rfc_bleMasterPar_s {
+ dataQueue_t* pRxQ; //!< Pointer to receive queue
+ dataQueue_t* pTxQ; //!< Pointer to transmit queue
+ struct {
+ uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue
+ uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue
+ uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue
+ uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it
+ uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it
+ uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue
+ uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue
+ uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue
+ } rxConfig; //!< Configuration bits for the receive queue entries
+ struct {
+ uint8_t lastRxSn:1; //!< The SN bit of the header of the last packet received with CRC OK
+ uint8_t lastTxSn:1; //!< The SN bit of the header of the last transmitted packet
+ uint8_t nextTxSn:1; //!< The SN bit of the header of the next packet to transmit
+ uint8_t bFirstPkt:1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise
+ uint8_t bAutoEmpty:1; //!< 1 if the last transmitted packet was an auto-empty packet
+ uint8_t bLlCtrlTx:1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11)
+ uint8_t bLlCtrlAckRx:1; //!< 1 if the last received packet was the ACK of an LL control packet
+ uint8_t bLlCtrlAckPending:1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed
+ } seqStat; //!< Sequence number status
+ uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit
+ uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit
+ uint32_t accessAddress; //!< Access address used on the connection
+ uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte
+ uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte
+ uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } endTrigger; //!< Trigger that causes the device to end the connection event as soon as allowed
+ ratmr_t endTime; //!< \brief Time used together with <code>endTrigger</code> that causes the device to end the
+ //!< connection event as soon as allowed
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup bleAdvPar
+//! @{
+//! Parameter structure for legacy advertiser (CMD_BLE_ADV* and CMD_BLE5_ADV*)
+
+struct __RFC_STRUCT rfc_bleAdvPar_s {
+ dataQueue_t* pRxQ; //!< Pointer to receive queue
+ struct {
+ uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue
+ uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue
+ uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue
+ uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it
+ uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it
+ uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue
+ uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue
+ uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue
+ } rxConfig; //!< Configuration bits for the receive queue entries
+ struct {
+ uint8_t advFilterPolicy:2; //!< \brief Advertiser filter policy<br>
+ //!< 0: Process scan and connect requests from all devices<br>
+ //!< 1: Process connect requests from all devices and only scan requests from
+ //!< devices that are in the white list<br>
+ //!< 2: Process scan requests from all devices and only connect requests from
+ //!< devices that are in the white list<br>
+ //!< 3: Process scan and connect requests only from devices in the white list
+ uint8_t deviceAddrType:1; //!< The type of the device address -- public (0) or random (1)
+ uint8_t peerAddrType:1; //!< Directed advertiser: The type of the peer address -- public (0) or random (1)
+ uint8_t bStrictLenFilter:1; //!< \brief 0: Accept any packet with a valid advertising packet length<br>
+ //!< 1: Discard messages with illegal length for the given packet type
+ uint8_t chSel:1; //!< \brief 0: Do not report support of Channel Selection Algorithm #2<br>
+ //!< 1: Report support of Channel Selection Algorithm #2
+ uint8_t privIgnMode:1; //!< \brief 0: Filter on bPrivIgn only when white list is used
+ //!< 1: Filter on bPrivIgn always
+ uint8_t rpaMode:1; //!< \brief Resolvable private address mode<br>
+ //!< 0: Normal operation<br>
+ //!< 1: Use white list for a received RPA regardless of filter policy
+ } advConfig;
+ uint8_t advLen; //!< Size of advertiser data
+ uint8_t scanRspLen; //!< Size of scan response data
+ uint8_t* pAdvData; //!< Pointer to buffer containing ADV*_IND data
+ uint8_t* pScanRspData; //!< Pointer to buffer containing SCAN_RSP data
+ uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device.
+ //!< If least significant bit is 1, the address type given by
+ //!< <code>advConfig.deviceAddrType</code> is inverted.
+ rfc_bleWhiteListEntry_t *pWhiteList; //!< \brief Pointer (with least significant bit set to 0) to white list or peer address (directed
+ //!< advertiser). If least significant bit is 1, the address type given by
+ //!< <code>advConfig.peerAddrType</code> is inverted.
+ struct {
+ uint8_t scanRspEndType:1; //!< \brief Command status at end if SCAN_RSP was sent:<br>
+ //!< 0: End with BLE_DONE_OK and result True<br>
+ //!< 1: End with BLE_DONE_SCAN_RSP and result False
+ } behConfig;
+ uint8_t __dummy0;
+ uint8_t __dummy1;
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } endTrigger; //!< Trigger that causes the device to end the advertiser event as soon as allowed
+ ratmr_t endTime; //!< \brief Time used together with <code>endTrigger</code> that causes the device to end the
+ //!< advertiser event as soon as allowed
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup bleScannerPar
+//! @{
+//! Parameter structure for legacy scanner (CMD_BLE_SCANNER)
+
+struct __RFC_STRUCT rfc_bleScannerPar_s {
+ dataQueue_t* pRxQ; //!< Pointer to receive queue
+ struct {
+ uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue
+ uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue
+ uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue
+ uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it
+ uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it
+ uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue
+ uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue
+ uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue
+ } rxConfig; //!< Configuration bits for the receive queue entries
+ struct {
+ uint8_t scanFilterPolicy:1; //!< \brief Scanning filter policy regarding advertiser address<br>
+ //!< 0: Accept all advertisement packets<br>
+ //!< 1: Accept only advertisement packets from devices where the advertiser's address
+ //!< is in the white list
+ uint8_t bActiveScan:1; //!< \brief 0: Passive scan<br>
+ //!< 1: Active scan
+ uint8_t deviceAddrType:1; //!< The type of the device address -- public (0) or random (1)
+ uint8_t rpaFilterPolicy:1; //!< \brief Filter policy for initA for ADV_DIRECT_IND messages<br>
+ //!< 0: Accept only initA that matches own address<br>
+ //!< 1: Also accept all resolvable private addresses
+ uint8_t bStrictLenFilter:1; //!< \brief 0: Accept any packet with a valid advertising packet length<br>
+ //!< 1: Discard messages with illegal length for the given packet type
+ uint8_t bAutoWlIgnore:1; //!< \brief 0: Do not set ignore bit in white list from radio CPU<br>
+ //!< 1: Automatically set ignore bit in white list
+ uint8_t bEndOnRpt:1; //!< \brief 0: Continue scanner operation after each reporting ADV*_IND or sending SCAN_RSP<br>
+ //!< 1: End scanner operation after each reported ADV*_IND and potentially SCAN_RSP
+ uint8_t rpaMode:1; //!< \brief Resolvable private address mode<br>
+ //!< 0: Normal operation<br>
+ //!< 1: Use white list for a received RPA regardless of filter policy
+ } scanConfig;
+ uint16_t randomState; //!< State for pseudo-random number generation used in backoff procedure
+ uint16_t backoffCount; //!< Parameter <i>backoffCount</i> used in backoff procedure, cf. Bluetooth spec
+ struct {
+ uint8_t logUpperLimit:4; //!< Binary logarithm of parameter upperLimit used in scanner backoff procedure
+ uint8_t bLastSucceeded:1; //!< \brief 1 if the last SCAN_RSP was successfully received and <code>upperLimit</code>
+ //!< not changed
+ uint8_t bLastFailed:1; //!< \brief 1 if reception of the last SCAN_RSP failed and <code>upperLimit</code> was not
+ //!< changed
+ } backoffPar;
+ uint8_t scanReqLen; //!< Size of scan request data
+ uint8_t* pScanReqData; //!< Pointer to buffer containing SCAN_REQ data
+ uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device.
+ //!< If least significant bit is 1, the address type given by
+ //!< <code>scanConfig.deviceAddrType</code> is inverted.
+ rfc_bleWhiteListEntry_t *pWhiteList; //!< Pointer to white list
+ uint16_t __dummy0;
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } timeoutTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } endTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed
+ ratmr_t timeoutTime; //!< \brief Time used together with <code>timeoutTrigger</code> that causes the device to stop
+ //!< receiving as soon as allowed, ending with BLE_DONE_RXTIMEOUT
+ ratmr_t endTime; //!< \brief Time used together with <code>endTrigger</code> that causes the device to stop
+ //!< receiving as soon as allowed, ending with BLE_DONE_ENDED
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup bleInitiatorPar
+//! @{
+//! Parameter structure for legacy initiator (CMD_BLE_INITIATOR)
+
+struct __RFC_STRUCT rfc_bleInitiatorPar_s {
+ dataQueue_t* pRxQ; //!< Pointer to receive queue
+ struct {
+ uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue
+ uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue
+ uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue
+ uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it
+ uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it
+ uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue
+ uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue
+ uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue
+ } rxConfig; //!< Configuration bits for the receive queue entries
+ struct {
+ uint8_t bUseWhiteList:1; //!< \brief Initiator filter policy<br>
+ //!< 0: Use specific peer address<br>
+ //!< 1: Use white list
+ uint8_t bDynamicWinOffset:1; //!< \brief 0: No dynamic WinOffset insertion<br>
+ //!< 1: Use dynamic WinOffset insertion
+ uint8_t deviceAddrType:1; //!< The type of the device address -- public (0) or random (1)
+ uint8_t peerAddrType:1; //!< The type of the peer address -- public (0) or random (1)
+ uint8_t bStrictLenFilter:1; //!< \brief 0: Accept any packet with a valid advertising packet length<br>
+ //!< 1: Discard messages with illegal length for the given packet type
+ uint8_t chSel:1; //!< \brief 0: Do not report support of Channel Selection Algorithm #2<br>
+ //!< 1: Report support of Channel Selection Algorithm #2
+ } initConfig;
+ uint8_t __dummy0;
+ uint8_t connectReqLen; //!< Size of connect request data
+ uint8_t* pConnectReqData; //!< Pointer to buffer containing LLData to go in the CONNECT_IND (CONNECT_REQ)
+ uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device.
+ //!< If least significant bit is 1, the address type given by
+ //!< <code>initConfig.deviceAddrType</code> is inverted.
+ rfc_bleWhiteListEntry_t *pWhiteList; //!< \brief Pointer (with least significant bit set to 0) to white list or peer address. If least
+ //!< significant bit is 1, the address type given by <code>initConfig.peerAddrType</code>
+ //!< is inverted.
+ ratmr_t connectTime; //!< \brief Indication of timer value of the first possible start time of the first connection event.
+ //!< Set to the calculated value if a connection is made and to the next possible connection
+ //!< time if not.
+ uint16_t __dummy1;
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } timeoutTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } endTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed
+ ratmr_t timeoutTime; //!< \brief Time used together with <code>timeoutTrigger</code> that causes the device to stop
+ //!< receiving as soon as allowed, ending with BLE_DONE_RXTIMEOUT
+ ratmr_t endTime; //!< \brief Time used together with <code>endTrigger</code> that causes the device to stop
+ //!< receiving as soon as allowed, ending with BLE_DONE_ENDED
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup bleGenericRxPar
+//! @{
+//! Parameter structure for generic Rx (CMD_BLE_GENERIC_RX and CMD_BLE5_GENERIC_RX)
+
+struct __RFC_STRUCT rfc_bleGenericRxPar_s {
+ dataQueue_t* pRxQ; //!< Pointer to receive queue. May be NULL; if so, received packets are not stored
+ struct {
+ uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue
+ uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue
+ uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue
+ uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it
+ uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it
+ uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue
+ uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue
+ uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue
+ } rxConfig; //!< Configuration bits for the receive queue entries
+ uint8_t bRepeat; //!< \brief 0: End operation after receiving a packet<br>
+ //!< 1: Restart receiver after receiving a packet
+ uint16_t __dummy0;
+ uint32_t accessAddress; //!< Access address used on the connection
+ uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte
+ uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte
+ uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } endTrigger; //!< Trigger that causes the device to end the Rx operation
+ ratmr_t endTime; //!< \brief Time used together with <code>endTrigger</code> that causes the device to end the
+ //!< Rx operation
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup bleTxTestPar
+//! @{
+//! Parameter structure for Tx test (CMD_BLE_TX_TEST and CMD_BLE5_TX_TEST)
+
+struct __RFC_STRUCT rfc_bleTxTestPar_s {
+ uint16_t numPackets; //!< \brief Number of packets to transmit<br>
+ //!< 0: Transmit unlimited number of packets
+ uint8_t payloadLength; //!< The number of payload bytes in each packet.
+ uint8_t packetType; //!< \brief The packet type to be used, encoded according to the Bluetooth 5.0 spec, Volume 6, Part F,
+ //!< Section 4.1.4
+ ratmr_t period; //!< Number of radio timer cycles between the start of each packet
+ struct {
+ uint8_t bOverrideDefault:1; //!< \brief 0: Use default packet encoding<br>
+ //!< 1: Override packet contents
+ uint8_t bUsePrbs9:1; //!< \brief If <code>bOverride</code> is 1:<br>
+ //!< 0: No PRBS9 encoding of packet<br>
+ //!< 1: Use PRBS9 encoding of packet
+ uint8_t bUsePrbs15:1; //!< \brief If <code>bOverride</code> is 1:<br>
+ //!< 0: No PRBS15 encoding of packet<br>
+ //!< 1: Use PRBS15 encoding of packet
+ } config;
+ uint8_t byteVal; //!< If <code>config.bOverride</code> is 1, value of each byte to be sent
+ uint8_t __dummy0;
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } endTrigger; //!< Trigger that causes the device to end the Test Tx operation
+ ratmr_t endTime; //!< \brief Time used together with <code>endTrigger</code> that causes the device to end the
+ //!< Test Tx operation
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup ble5SlavePar
+//! @{
+//! Parameter structure for Bluetooth 5 slave (CMD_BLE5_SLAVE)
+
+struct __RFC_STRUCT rfc_ble5SlavePar_s {
+ dataQueue_t* pRxQ; //!< Pointer to receive queue
+ dataQueue_t* pTxQ; //!< Pointer to transmit queue
+ struct {
+ uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue
+ uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue
+ uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue
+ uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it
+ uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it
+ uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue
+ uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue
+ uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue
+ } rxConfig; //!< Configuration bits for the receive queue entries
+ struct {
+ uint8_t lastRxSn:1; //!< The SN bit of the header of the last packet received with CRC OK
+ uint8_t lastTxSn:1; //!< The SN bit of the header of the last transmitted packet
+ uint8_t nextTxSn:1; //!< The SN bit of the header of the next packet to transmit
+ uint8_t bFirstPkt:1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise
+ uint8_t bAutoEmpty:1; //!< 1 if the last transmitted packet was an auto-empty packet
+ uint8_t bLlCtrlTx:1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11)
+ uint8_t bLlCtrlAckRx:1; //!< 1 if the last received packet was the ACK of an LL control packet
+ uint8_t bLlCtrlAckPending:1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed
+ } seqStat; //!< Sequence number status
+ uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit
+ uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit
+ uint32_t accessAddress; //!< Access address used on the connection
+ uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte
+ uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte
+ uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } timeoutTrigger; //!< Trigger that defines timeout of the first receive operation
+ ratmr_t timeoutTime; //!< \brief Time used together with <code>timeoutTrigger</code> that defines timeout of the first
+ //!< receive operation
+ uint8_t maxRxPktLen; //!< Maximum packet length currently allowed for received packets on the connection
+ uint8_t maxLenLowRate; //!< Maximum packet length for which using S = 8 (125 kbps) is allowed when transmitting. 0: no limit.
+ uint8_t __dummy0;
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } endTrigger; //!< Trigger that causes the device to end the connection event as soon as allowed
+ ratmr_t endTime; //!< \brief Time used together with <code>endTrigger</code> that causes the device to end the
+ //!< connection event as soon as allowed
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup ble5MasterPar
+//! @{
+//! Parameter structure for Bluetooth 5 master (CMD_BLE5_MASTER)
+
+struct __RFC_STRUCT rfc_ble5MasterPar_s {
+ dataQueue_t* pRxQ; //!< Pointer to receive queue
+ dataQueue_t* pTxQ; //!< Pointer to transmit queue
+ struct {
+ uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue
+ uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue
+ uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue
+ uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it
+ uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it
+ uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue
+ uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue
+ uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue
+ } rxConfig; //!< Configuration bits for the receive queue entries
+ struct {
+ uint8_t lastRxSn:1; //!< The SN bit of the header of the last packet received with CRC OK
+ uint8_t lastTxSn:1; //!< The SN bit of the header of the last transmitted packet
+ uint8_t nextTxSn:1; //!< The SN bit of the header of the next packet to transmit
+ uint8_t bFirstPkt:1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise
+ uint8_t bAutoEmpty:1; //!< 1 if the last transmitted packet was an auto-empty packet
+ uint8_t bLlCtrlTx:1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11)
+ uint8_t bLlCtrlAckRx:1; //!< 1 if the last received packet was the ACK of an LL control packet
+ uint8_t bLlCtrlAckPending:1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed
+ } seqStat; //!< Sequence number status
+ uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit
+ uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit
+ uint32_t accessAddress; //!< Access address used on the connection
+ uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte
+ uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte
+ uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } endTrigger; //!< Trigger that causes the device to end the connection event as soon as allowed
+ ratmr_t endTime; //!< \brief Time used together with <code>endTrigger</code> that causes the device to end the
+ //!< connection event as soon as allowed
+ uint8_t maxRxPktLen; //!< Maximum packet length currently allowed for received packets on the connection
+ uint8_t maxLenLowRate; //!< Maximum packet length for which using S = 8 (125 kbps) is allowed when transmitting. 0: no limit.
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup ble5AdvExtPar
+//! @{
+//! Parameter structure for extended advertiser (CMD_BLE5_ADV_EXT)
+
+struct __RFC_STRUCT rfc_ble5AdvExtPar_s {
+ struct {
+ uint8_t :2;
+ uint8_t deviceAddrType:1; //!< The type of the device address -- public (0) or random (1)
+ } advConfig;
+ uint8_t __dummy0;
+ uint8_t __dummy1;
+ uint8_t auxPtrTargetType; //!< \brief Number indicating reference for auxPtrTargetTime. Takes same values as trigger types,
+ //!< but only TRIG_ABSTIME and TRIG_REL_* are allowed
+ ratmr_t auxPtrTargetTime; //!< Time of start of packet to which auxPtr points
+ uint8_t* pAdvPkt; //!< Pointer to extended advertising packet for the ADV_EXT_IND packet
+ uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device.
+ //!< If least significant bit is 1, the address type given by
+ //!< <code>advConfig.deviceAddrType</code> is inverted.
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup ble5AdvAuxPar
+//! @{
+//! Parameter structure for secondary channel advertiser (CMD_BLE5_ADV_AUX)
+
+struct __RFC_STRUCT rfc_ble5AdvAuxPar_s {
+ dataQueue_t* pRxQ; //!< Pointer to receive queue
+ struct {
+ uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue
+ uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue
+ uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue
+ uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it
+ uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it
+ uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue
+ uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue
+ uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue
+ } rxConfig; //!< Configuration bits for the receive queue entries
+ struct {
+ uint8_t advFilterPolicy:2; //!< \brief Advertiser filter policy<br>
+ //!< 0: Process scan and connect requests from all devices<br>
+ //!< 1: Process connect requests from all devices and only scan requests from
+ //!< devices that are in the white list<br>
+ //!< 2: Process scan requests from all devices and only connect requests from
+ //!< devices that are in the white list<br>
+ //!< 3: Process scan and connect requests only from devices in the white list
+ uint8_t deviceAddrType:1; //!< The type of the device address -- public (0) or random (1)
+ uint8_t targetAddrType:1; //!< Directed secondary advertiser: The type of the target address -- public (0) or random (1)
+ uint8_t bStrictLenFilter:1; //!< \brief 0: Accept any packet with a valid advertising packet length<br>
+ //!< 1: Discard messages with illegal length for the given packet type
+ uint8_t bDirected:1; //!< \brief 0: Advertiser is undirected: pWhiteList points to a white list
+ //!< 1: Advertiser is directed: pWhiteList points to a single device address
+ uint8_t privIgnMode:1; //!< \brief 0: Filter on bPrivIgn only when white list is used
+ //!< 1: Filter on bPrivIgn always
+ uint8_t rpaMode:1; //!< \brief Resolvable private address mode<br>
+ //!< 0: Normal operation<br>
+ //!< 1: Use white list for a received RPA regardless of filter policy
+ } advConfig;
+ struct {
+ uint8_t scanRspEndType:1; //!< \brief Command status at end if AUX_SCAN_RSP was sent:<br>
+ //!< 0: End with BLE_DONE_OK and result True<br>
+ //!< 1: End with BLE_DONE_SCAN_RSP and result False
+ } behConfig;
+ uint8_t auxPtrTargetType; //!< \brief Number indicating reference for auxPtrTargetTime. Takes same values as trigger types,
+ //!< but only TRIG_ABSTIME and TRIG_REL_* are allowed
+ ratmr_t auxPtrTargetTime; //!< Time of start of packet to which auxPtr points
+ uint8_t* pAdvPkt; //!< Pointer to extended advertising packet for the ADV_AUX_IND packet
+ uint8_t* pRspPkt; //!< \brief Pointer to extended advertising packet for the AUX_SCAN_RSP or AUX_CONNECT_RSP packet
+ //!< (may be NULL if not applicable)
+ uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device.
+ //!< If least significant bit is 1, the address type given by
+ //!< <code>advConfig.deviceAddrType</code> is inverted.
+ rfc_bleWhiteListEntry_t *pWhiteList; //!< \brief Pointer (with least significant bit set to 0) to white list or peer address (directed
+ //!< advertiser). If least significant bit is 1, the address type given by
+ //!< <code>advConfig.peerAddrType</code> is inverted.
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup ble5AuxChRes
+//! @{
+struct __RFC_STRUCT rfc_ble5AuxChRes_s {
+ ratmr_t rxStartTime; //!< The time needed to start RX in order to receive the packet
+ uint16_t rxListenTime; //!< The time needed to listen in order to receive the packet. 0: No AUX packet
+ uint8_t channelNo; //!< The channel index used for secondary advertising
+ uint8_t phyMode; //!< \brief PHY to use on secondary channel:<br>
+ //!< 0: 1 Mbps<br>
+ //!< 1: 2 Mbps<br>
+ //!< 2: Coded<br>
+ //!< Others: <i>Reserved</i>
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup ble5ScannerPar
+//! @{
+//! Parameter structure for Bluetooth 5 scanner (CMD_BLE5_SCANNER)
+
+struct __RFC_STRUCT rfc_ble5ScannerPar_s {
+ dataQueue_t* pRxQ; //!< Pointer to receive queue
+ struct {
+ uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue
+ uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue
+ uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue
+ uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it
+ uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it
+ uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue
+ uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue
+ uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue
+ } rxConfig; //!< Configuration bits for the receive queue entries
+ struct {
+ uint8_t scanFilterPolicy:1; //!< \brief Scanning filter policy regarding advertiser address<br>
+ //!< 0: Accept all advertisement packets<br>
+ //!< 1: Accept only advertisement packets from devices where the advertiser's address
+ //!< is in the White list.
+ uint8_t bActiveScan:1; //!< \brief 0: Passive scan<br>
+ //!< 1: Active scan
+ uint8_t deviceAddrType:1; //!< The type of the device address -- public (0) or random (1)
+ uint8_t rpaFilterPolicy:1; //!< \brief Filter policy for initA of ADV_DIRECT_IND messages<br>
+ //!< 0: Accept only initA that matches own address<br>
+ //!< 1: Also accept all resolvable private addresses
+ uint8_t bStrictLenFilter:1; //!< \brief 0: Accept any packet with a valid advertising packet length<br>
+ //!< 1: Discard messages with illegal length for the given packet type
+ uint8_t bAutoWlIgnore:1; //!< \brief 0: Do not set ignore bit in white list from radio CPU for legacy packets<br>
+ //!< 1: Automatically set ignore bit in white list for legacy packets
+ uint8_t bEndOnRpt:1; //!< \brief 0: Continue scanner operation after each reporting ADV*_IND or sending SCAN_RSP<br>
+ //!< 1: End scanner operation after each reported ADV*_IND and potentially SCAN_RSP
+ uint8_t rpaMode:1; //!< \brief Resolvable private address mode<br>
+ //!< 0: Normal operation<br>
+ //!< 1: Use white list for a received RPA regardless of filter policy
+ } scanConfig;
+ uint16_t randomState; //!< State for pseudo-random number generation used in backoff procedure
+ uint16_t backoffCount; //!< Parameter <i>backoffCount</i> used in backoff procedure, cf. Bluetooth spec
+ struct {
+ uint8_t logUpperLimit:4; //!< Binary logarithm of parameter upperLimit used in scanner backoff procedure
+ uint8_t bLastSucceeded:1; //!< \brief 1 if the last SCAN_RSP was successfully received and <code>upperLimit</code>
+ //!< not changed
+ uint8_t bLastFailed:1; //!< \brief 1 if reception of the last SCAN_RSP failed and <code>upperLimit</code> was not
+ //!< changed
+ } backoffPar;
+ struct {
+ uint8_t bCheckAdi:1; //!< \brief 0: Do not perform ADI filtering<br>
+ //!< 1: Perform ADI filtering on packets where ADI is present
+ uint8_t bAutoAdiUpdate:1; //!< \brief 0: Do not update ADI entries in radio CPU using legacy mode (recommended)<br>
+ //!< 1: Legacy mode: Automatically update ADI entry for received packets with
+ //!< AdvDataInfo after first occurrence
+ uint8_t bApplyDuplicateFiltering:1;//!< \brief 0: Do not apply duplicate filtering based on device address for extended
+ //!< advertiser packets (recommended)<br>
+ //!< 1: Apply duplicate filtering based on device address for extended advertiser
+ //!< packets with no ADI field
+ uint8_t bAutoWlIgnore:1; //!< \brief 0: Do not set ignore bit in white list from radio CPU for extended advertising packets<br>
+ //!< 1: Automatically set ignore bit in white list for extended advertising packets
+ uint8_t bAutoAdiProcess:1; //!< \brief 0: Do not use automatic ADI processing<br>
+ //!< 1: Automatically update ADI entry for received packets so that only the same
+ //!< ADI is accepted for the rest of the chain and the SID/DID combination is
+ //!< ignored after the entire chain is received.
+ uint8_t bExclusiveSid:1; //!< \brief 0: Set <code>adiStatus.state</code> to 0 when command starts so that all
+ //!< valid SIDs are accepted<br>
+ //!< 1: Do not modify adiStatus.state when command starts<br>
+ } extFilterConfig;
+ struct {
+ uint8_t lastAcceptedSid:4; //!< Indication of SID of last successfully received packet that was not ignored
+ uint8_t state:3; //!< \brief 0: No extended packet received, or last extended packet didn't have an ADI;
+ //!< <code>lastAcceptedSid</code> field is not valid<br>
+ //!< 1: A message with ADI has been received, but no chain is under reception;
+ //!< ADI filtering to be performed normally<br>
+ //!< 2: A message with SID as given in <code>lastAcceptedSid</code> has been
+ //!< received, and chained messages are still pending. Messages without this
+ //!< SID will be ignored<br>
+ //!< 3: An AUX_SCAN_RSP message has been received after receiving messages with SID
+ //!< as given in <code>lastAcceptedSid</code>, and chained messages are
+ //!< pending. Messages with an ADI field will be ignored.<br>
+ //!< 4: A message with no ADI has been received, and chained messages are still
+ //!< pending. Messages with an ADI field will be ignored.<br>
+ //!< Others: <i>Reserved</i>
+ } adiStatus;
+ uint8_t __dummy0;
+ uint16_t __dummy1;
+ uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device.
+ //!< If least significant bit is 1, the address type given by
+ //!< <code>scanConfig.deviceAddrType</code> is inverted.
+ rfc_bleWhiteListEntry_t *pWhiteList; //!< Pointer to white list
+ rfc_ble5AdiEntry_t *pAdiList; //!< Pointer to advDataInfo list
+ uint16_t maxWaitTimeForAuxCh; //!< \brief Maximum wait time for switching to secondary scanning withing the command. If the time
+ //!< to the start of the event is greater than this, the command will end with BLE_DONE_AUX.
+ //!< If it is smaller, the radio will automatically switch to the correct channel and PHY.
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } timeoutTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } endTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed
+ ratmr_t timeoutTime; //!< \brief Time used together with <code>timeoutTrigger</code> that causes the device to stop
+ //!< receiving as soon as allowed, ending with BLE_DONE_RXTIMEOUT
+ ratmr_t endTime; //!< \brief Time used together with <code>endTrigger</code> that causes the device to stop
+ //!< receiving as soon as allowed, ending with BLE_DONE_ENDED
+ ratmr_t rxStartTime; //!< The time needed to start RX in order to receive the packet
+ uint16_t rxListenTime; //!< The time needed to listen in order to receive the packet. 0: No AUX packet
+ uint8_t channelNo; //!< The channel index used for secondary advertising
+ uint8_t phyMode; //!< \brief PHY to use on secondary channel:<br>
+ //!< 0: 1 Mbps<br>
+ //!< 1: 2 Mbps<br>
+ //!< 2: Coded<br>
+ //!< Others: <i>Reserved</i>
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup ble5InitiatorPar
+//! @{
+//! Parameter structure for Bluetooth 5 initiator (CMD_BLE5_INITIATOR)
+
+struct __RFC_STRUCT rfc_ble5InitiatorPar_s {
+ dataQueue_t* pRxQ; //!< Pointer to receive queue
+ struct {
+ uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue
+ uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue
+ uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue
+ uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it
+ uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it
+ uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue
+ uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue
+ uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue
+ } rxConfig; //!< Configuration bits for the receive queue entries
+ struct {
+ uint8_t bUseWhiteList:1; //!< \brief Initiator filter policy<br>
+ //!< 0: Use specific peer address<br>
+ //!< 1: Use white list
+ uint8_t bDynamicWinOffset:1; //!< 1: Use dynamic WinOffset insertion
+ uint8_t deviceAddrType:1; //!< The type of the device address -- public (0) or random (1)
+ uint8_t peerAddrType:1; //!< The type of the peer address -- public (0) or random (1)
+ uint8_t bStrictLenFilter:1; //!< \brief 0: Accept any packet with a valid advertising packet length<br>
+ //!< 1: Discard messages with illegal length for the given packet type
+ uint8_t chSel:1; //!< \brief 0: Do not report support of Channel Selection Algorithm #2 in CONNECT_IND<br>
+ //!< 1: Report support of Channel Selection Algorithm #2 in CONNECT_IND
+ } initConfig;
+ uint16_t randomState; //!< State for pseudo-random number generation used in backoff procedure
+ uint16_t backoffCount; //!< Parameter <i>backoffCount</i> used in backoff procedure, cf. Bluetooth spec
+ struct {
+ uint8_t logUpperLimit:4; //!< Binary logarithm of parameter upperLimit used in scanner backoff procedure
+ uint8_t bLastSucceeded:1; //!< \brief 1 if the last SCAN_RSP was successfully received and <code>upperLimit</code>
+ //!< not changed
+ uint8_t bLastFailed:1; //!< \brief 1 if reception of the last SCAN_RSP failed and <code>upperLimit</code> was not
+ //!< changed
+ } backoffPar;
+ uint8_t connectReqLen; //!< Size of connect request data
+ uint8_t* pConnectReqData; //!< Pointer to buffer containing LLData to go in the CONNECT_IND or AUX_CONNECT_REQ packet
+ uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device.
+ //!< If least significant bit is 1, the address type given by
+ //!< <code>initConfig.deviceAddrType</code> is inverted.
+ rfc_bleWhiteListEntry_t *pWhiteList; //!< \brief Pointer (with least significant bit set to 0) to white list or peer address. If least
+ //!< significant bit is 1, the address type given by <code>initConfig.peerAddrType</code>
+ //!< is inverted.
+ ratmr_t connectTime; //!< \brief Indication of timer value of the first possible start time of the first connection event.
+ //!< Set to the calculated value if a connection is made and to the next possible connection
+ //!< time if not.
+ uint16_t maxWaitTimeForAuxCh; //!< \brief Maximum wait time for switching to secondary scanning withing the command. If the time
+ //!< to the start of the event is greater than this, the command will end with BLE_DONE_AUX.
+ //!< If it is smaller, the radio will automatically switch to the correct channel and PHY.
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } timeoutTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } endTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed
+ ratmr_t timeoutTime; //!< \brief Time used together with <code>timeoutTrigger</code> that causes the device to stop
+ //!< receiving as soon as allowed, ending with BLE_DONE_RXTIMEOUT
+ ratmr_t endTime; //!< \brief Time used together with <code>endTrigger</code> that causes the device to stop
+ //!< receiving as soon as allowed, ending with BLE_DONE_ENDED
+ ratmr_t rxStartTime; //!< The time needed to start RX in order to receive the packet
+ uint16_t rxListenTime; //!< The time needed to listen in order to receive the packet. 0: No AUX packet
+ uint8_t channelNo; //!< The channel index used for secondary advertising
+ uint8_t phyMode; //!< \brief PHY to use on secondary channel:<br>
+ //!< 0: 1 Mbps<br>
+ //!< 1: 2 Mbps<br>
+ //!< 2: Coded<br>
+ //!< Others: <i>Reserved</i>
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup bleMasterSlaveOutput
+//! @{
+//! Output structure for master and slave (CMD_BLE_MASTER/CMD_BLE_SLAVE/CMD_BLE5_MASTER/CMD_BLE5_SLAVE)
+
+struct __RFC_STRUCT rfc_bleMasterSlaveOutput_s {
+ uint8_t nTx; //!< \brief Total number of packets (including auto-empty and retransmissions) that have been
+ //!< transmitted
+ uint8_t nTxAck; //!< Total number of transmitted packets (including auto-empty) that have been ACK'ed
+ uint8_t nTxCtrl; //!< Number of unique LL control packets from the Tx queue that have been transmitted
+ uint8_t nTxCtrlAck; //!< Number of LL control packets from the Tx queue that have been finished (ACK'ed)
+ uint8_t nTxCtrlAckAck; //!< \brief Number of LL control packets that have been ACK'ed and where an ACK has been sent in
+ //!< response
+ uint8_t nTxRetrans; //!< Number of retransmissions that has been done
+ uint8_t nTxEntryDone; //!< Number of packets from the Tx queue that have been finished (ACK'ed)
+ uint8_t nRxOk; //!< Number of packets that have been received with payload, CRC OK and not ignored
+ uint8_t nRxCtrl; //!< Number of LL control packets that have been received with CRC OK and not ignored
+ uint8_t nRxCtrlAck; //!< \brief Number of LL control packets that have been received with CRC OK and not ignored, and
+ //!< then ACK'ed
+ uint8_t nRxNok; //!< Number of packets that have been received with CRC error
+ uint8_t nRxIgnored; //!< \brief Number of packets that have been received with CRC OK and ignored due to repeated
+ //!< sequence number
+ uint8_t nRxEmpty; //!< Number of packets that have been received with CRC OK and no payload
+ uint8_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space
+ int8_t lastRssi; //!< RSSI of last received packet (signed)
+ struct {
+ uint8_t bTimeStampValid:1; //!< 1 if a valid time stamp has been written to timeStamp; 0 otherwise
+ uint8_t bLastCrcErr:1; //!< 1 if the last received packet had CRC error; 0 otherwise
+ uint8_t bLastIgnored:1; //!< 1 if the last received packet with CRC OK was ignored; 0 otherwise
+ uint8_t bLastEmpty:1; //!< 1 if the last received packet with CRC OK was empty; 0 otherwise
+ uint8_t bLastCtrl:1; //!< 1 if the last received packet with CRC OK was an LL control packet; 0 otherwise
+ uint8_t bLastMd:1; //!< 1 if the last received packet with CRC OK had MD = 1; 0 otherwise
+ uint8_t bLastAck:1; //!< \brief 1 if the last received packet with CRC OK was an ACK of a transmitted packet;
+ //!< 0 otherwise
+ } pktStatus; //!< Status of received packets
+ ratmr_t timeStamp; //!< Slave operation: Time stamp of first received packet
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup bleAdvOutput
+//! @{
+//! Output structure for advertiser (CMD_BLE_ADV* and CMD_BLE5_ADV*)
+
+struct __RFC_STRUCT rfc_bleAdvOutput_s {
+ uint16_t nTxAdvInd; //!< Number of ADV*_IND packets completely transmitted
+ uint8_t nTxScanRsp; //!< Number of AUX_SCAN_RSP or SCAN_RSP packets transmitted
+ uint8_t nRxScanReq; //!< Number of AUX_SCAN_REQ or SCAN_REQ packets received OK and not ignored
+ uint8_t nRxConnectReq; //!< Number of AUX_CONNECT_REQ or CONNECT_IND (CONNECT_REQ) packets received OK and not ignored
+ uint8_t nTxConnectRsp; //!< Number of AUX_CONNECT_RSP packets transmitted
+ uint16_t nRxNok; //!< Number of packets received with CRC error
+ uint16_t nRxIgnored; //!< Number of packets received with CRC OK, but ignored
+ uint8_t nRxBufFull; //!< Number of packets received that did not fit in Rx queue
+ int8_t lastRssi; //!< The RSSI of the last received packet (signed)
+ ratmr_t timeStamp; //!< Time stamp of the last received packet
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup bleScannerOutput
+//! @{
+//! Output structure for legacy scanner (CMD_BLE_SCANNER)
+
+struct __RFC_STRUCT rfc_bleScannerOutput_s {
+ uint16_t nTxScanReq; //!< Number of transmitted SCAN_REQ packets
+ uint16_t nBackedOffScanReq; //!< Number of SCAN_REQ packets not sent due to backoff procedure
+ uint16_t nRxAdvOk; //!< Number of ADV*_IND packets received with CRC OK and not ignored
+ uint16_t nRxAdvIgnored; //!< Number of ADV*_IND packets received with CRC OK, but ignored
+ uint16_t nRxAdvNok; //!< Number of ADV*_IND packets received with CRC error
+ uint16_t nRxScanRspOk; //!< Number of SCAN_RSP packets received with CRC OK and not ignored
+ uint16_t nRxScanRspIgnored; //!< Number of SCAN_RSP packets received with CRC OK, but ignored
+ uint16_t nRxScanRspNok; //!< Number of SCAN_RSP packets received with CRC error
+ uint8_t nRxAdvBufFull; //!< Number of ADV*_IND packets received that did not fit in Rx queue
+ uint8_t nRxScanRspBufFull; //!< Number of SCAN_RSP packets received that did not fit in Rx queue
+ int8_t lastRssi; //!< The RSSI of the last received packet (signed)
+ uint8_t __dummy0;
+ ratmr_t timeStamp; //!< Time stamp of the last successfully received ADV*_IND packet that was not ignored
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup bleInitiatorOutput
+//! @{
+//! Output structure for legacy initiator (CMD_BLE_INITIATOR)
+
+struct __RFC_STRUCT rfc_bleInitiatorOutput_s {
+ uint8_t nTxConnectReq; //!< Number of transmitted CONNECT_IND (CONNECT_REQ) packets
+ uint8_t nRxAdvOk; //!< Number of ADV*_IND packets received with CRC OK and not ignored
+ uint16_t nRxAdvIgnored; //!< Number of ADV*_IND packets received with CRC OK, but ignored
+ uint16_t nRxAdvNok; //!< Number of ADV*_IND packets received with CRC error
+ uint8_t nRxAdvBufFull; //!< Number of ADV*_IND packets received that did not fit in Rx queue
+ int8_t lastRssi; //!< The RSSI of the last received packet (signed)
+ ratmr_t timeStamp; //!< Time stamp of the received ADV*_IND packet that caused transmission of CONNECT_IND (CONNECT_REQ)
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup ble5ScanInitOutput
+//! @{
+//! Output structure for BLE scanner and initiator (CMD_BLE5_SCANNER and CMD_BLE5_INITIATOR)
+
+struct __RFC_STRUCT rfc_ble5ScanInitOutput_s {
+ uint16_t nTxReq; //!< Number of transmitted AUX_SCAN_REQ, SCAN_REQ, AUX_CONNECT_REQ, or CONNECT_IND packets
+ uint16_t nBackedOffReq; //!< Number of AUX_SCAN_REQ, SCAN_REQ, or AUX_CONNECT_REQ packets not sent due to backoff procedure
+ uint16_t nRxAdvOk; //!< Number of ADV*_IND packets received with CRC OK and not ignored
+ uint16_t nRxAdvIgnored; //!< Number of ADV*_IND packets received with CRC OK, but ignored
+ uint16_t nRxAdvNok; //!< Number of ADV*_IND packets received with CRC error
+ uint16_t nRxRspOk; //!< Number of AUX_SCAN_RSP, SCAN_RSP, or AUX_CONNECT_RSP packets received with CRC OK and not ignored
+ uint16_t nRxRspIgnored; //!< Number of AUX_SCAN_RSP, SCAN_RSP, or AUX_CONNECT_RSP packets received with CRC OK, but ignored
+ uint16_t nRxRspNok; //!< Number of AUX_SCAN_RSP, SCAN_RSP, or AUX_CONNECT_RSP packets received with CRC error
+ uint8_t nRxAdvBufFull; //!< Number of ADV*_IND packets received that did not fit in Rx queue
+ uint8_t nRxRspBufFull; //!< Number of AUX_SCAN_RSP, SCAN_RSP, or AUX_CONNECT_RSP packets received that did not fit in Rx queue
+ int8_t lastRssi; //!< The RSSI of the last received packet (signed)
+ uint8_t __dummy0;
+ ratmr_t timeStamp; //!< Time stamp of the last successfully received *ADV*_IND packet that was not ignored
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup bleGenericRxOutput
+//! @{
+//! Output structure for generic Rx (CMD_BLE_GENERIC_RX and CMD_BLE5_GENERIC_RX)
+
+struct __RFC_STRUCT rfc_bleGenericRxOutput_s {
+ uint16_t nRxOk; //!< Number of packets received with CRC OK
+ uint16_t nRxNok; //!< Number of packets received with CRC error
+ uint16_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space
+ int8_t lastRssi; //!< The RSSI of the last received packet (signed)
+ uint8_t __dummy0;
+ ratmr_t timeStamp; //!< Time stamp of the last received packet
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup bleTxTestOutput
+//! @{
+//! Output structure for Tx test (CMD_BLE_TX_TEST and CMD_BLE5_TX_TEST)
+
+struct __RFC_STRUCT rfc_bleTxTestOutput_s {
+ uint16_t nTx; //!< Number of packets transmitted
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup ble5ExtAdvEntry
+//! @{
+//! Common Extended Packet Entry Format
+
+struct __RFC_STRUCT rfc_ble5ExtAdvEntry_s {
+ struct {
+ uint8_t length:6; //!< Extended header length
+ uint8_t advMode:2; //!< \brief Advertiser mode as defined in BLE:<br>
+ //!< 0: Non-connectable, non-scannable<br>
+ //!< 1: Connectable, non-scannable<br>
+ //!< 2: Non-connectable, scannable<br>
+ //!< 3: <i>Reserved</i>
+ } extHdrInfo;
+ uint8_t extHdrFlags; //!< Extended header flags as defined in BLE
+ struct {
+ uint8_t bSkipAdvA:1; //!< \brief 0: AdvA is present in extended payload if configured in
+ //!< <code>extHdrFlags</code><br>
+ //!< 1: AdvA is inserted automatically from command structure if configured in
+ //!< <code>extHdrFlags</code> and is omitted from extended header
+ uint8_t bSkipTargetA:1; //!< \brief 0: TargetA is present in extended payload if configured in
+ //!< <code>extHdrFlags</code>. For response messages, the value is replaced
+ //!< by the received address when sending<br>
+ //!< 1: TargetA is inserted automatically from command structure or received
+ //!< address if configured in <code>extHdrFlags</code> and is omitted from
+ //!< extended header. Not supported with CMD_BLE5_ADV_EXT.
+ uint8_t deviceAddrType:1; //!< \brief If <code>bSkipAdvA</code> = 0: The type of the device address in extended
+ //!< header buffer -- public (0) or random (1)
+ uint8_t targetAddrType:1; //!< \brief If <code>bSkipAdvA</code> = 0: The type of the target address in extended
+ //!< header buffer -- public (0) or random (1)
+ } extHdrConfig;
+ uint8_t advDataLen; //!< Size of payload buffer
+ uint8_t* pExtHeader; //!< \brief Pointer to buffer containing extended header. If no fields except extended
+ //!< header flags, automatic advertiser address, or automatic target address are
+ //!< present, pointer may be NULL.
+ uint8_t* pAdvData; //!< \brief Pointer to buffer containing advData. If <code>advDataLen</code> = 0,
+ //!< pointer may be NULL.
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup bleWhiteListEntry
+//! @{
+//! White list entry structure
+
+struct __RFC_STRUCT rfc_bleWhiteListEntry_s {
+ uint8_t size; //!< Number of while list entries. Used in the first entry of the list only
+ struct {
+ uint8_t bEnable:1; //!< 1 if the entry is in use, 0 if the entry is not in use
+ uint8_t addrType:1; //!< The type address in the entry -- public (0) or random (1)
+ uint8_t bWlIgn:1; //!< \brief 1 if the entry is to be ignored by a scanner if the AdvDataInfo
+ //!< field is not present, 0 otherwise. Used to mask out entries that
+ //!< have already been scanned and reported.
+ uint8_t :1;
+ uint8_t bPrivIgn:1; //!< \brief 1 if the entry is to be ignored as part of a privacy algorithm,
+ //!< 0 otherwise
+ } conf;
+ uint16_t address; //!< Least significant 16 bits of the address contained in the entry
+ uint32_t addressHi; //!< Most significant 32 bits of the address contained in the entry
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup ble5AdiEntry
+//! @{
+//! AdvDataInfo list entry structure
+
+struct __RFC_STRUCT rfc_ble5AdiEntry_s {
+ struct {
+ uint16_t advDataId:12; //!< \brief If <code>bValid</code> = 1: Last Advertising Data ID (DID) for the
+ //!< Advertising Set ID (SID) corresponding to the entry number in the array
+ uint16_t mode:2; //!< \brief 0: Entry is invalid (always receive packet with the given SID)<br>
+ //!< 1: Entry is valid (ignore packets with the given SID where DID equals
+ //!< <code>advDataId</code>)<br>
+ //!< 2: Entry is blocked (always ignore packet with the given SID)<br>
+ //!< 3: <i>Reserved</i>
+ } advDataInfo;
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup bleRxStatus
+//! @{
+//! Receive status byte that may be appended to message in receive buffer for legacy commands
+
+struct __RFC_STRUCT rfc_bleRxStatus_s {
+ struct {
+ uint8_t channel:6; //!< \brief The channel on which the packet was received, provided channel is in the range
+ //!< 0--39; otherwise 0x3F
+ uint8_t bIgnore:1; //!< 1 if the packet is marked as ignored, 0 otherwise
+ uint8_t bCrcErr:1; //!< 1 if the packet was received with CRC error, 0 otherwise
+ } status;
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup ble5RxStatus
+//! @{
+//! Receive status field that may be appended to message in receive buffer for Bluetooth 5 commands
+
+struct __RFC_STRUCT rfc_ble5RxStatus_s {
+ struct {
+ uint16_t channel:6; //!< \brief The channel on which the packet was received, provided channel is in the range
+ //!< 0--39; otherwise 0x3F
+ uint16_t bIgnore:1; //!< 1 if the packet is marked as ignored, 0 otherwise
+ uint16_t bCrcErr:1; //!< 1 if the packet was received with CRC error, 0 otherwise
+ uint16_t phyMode:2; //!< \brief The PHY on which the packet was received<br>
+ //!< 0: 1 Mbps<br>
+ //!< 1: 2 Mbps<br>
+ //!< 2: Coded, S = 8 (125 kbps)<br>
+ //!< 3: Coded, S = 2 (500 kbps)
+ } status;
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! @}
+//! @}
+#endif
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_mailbox.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_mailbox.h
new file mode 100644
index 0000000..b43d099
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_mailbox.h
@@ -0,0 +1,76 @@
+/******************************************************************************
+* Filename: rf_ble_mailbox.h
+* Revised: 2018-01-15 15:58:36 +0100 (Mon, 15 Jan 2018)
+* Revision: 18171
+*
+* Description: Definitions for BLE interface
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef _BLE_MAILBOX_H
+#define _BLE_MAILBOX_H
+
+/// \name Radio operation status
+///@{
+/// \name Operation finished normally
+///@{
+#define BLE_DONE_OK 0x1400 ///< Operation ended normally
+#define BLE_DONE_RXTIMEOUT 0x1401 ///< Timeout of first Rx of slave operation or end of scan window
+#define BLE_DONE_NOSYNC 0x1402 ///< Timeout of subsequent Rx
+#define BLE_DONE_RXERR 0x1403 ///< Operation ended because of receive error (CRC or other)
+#define BLE_DONE_CONNECT 0x1404 ///< CONNECT_IND or AUX_CONNECT_RSP received or transmitted
+#define BLE_DONE_MAXNACK 0x1405 ///< Maximum number of retransmissions exceeded
+#define BLE_DONE_ENDED 0x1406 ///< Operation stopped after end trigger
+#define BLE_DONE_ABORT 0x1407 ///< Operation aborted by command
+#define BLE_DONE_STOPPED 0x1408 ///< Operation stopped after stop command
+#define BLE_DONE_AUX 0x1409 ///< Operation ended after following aux pointer pointing far ahead
+#define BLE_DONE_CONNECT_CHSEL0 0x140A ///< CONNECT_IND received or transmitted; peer does not support channel selection algorithm #2
+#define BLE_DONE_SCAN_RSP 0x140B ///< SCAN_RSP or AUX_SCAN_RSP transmitted
+///@}
+/// \name Operation finished with error
+///@{
+#define BLE_ERROR_PAR 0x1800 ///< Illegal parameter
+#define BLE_ERROR_RXBUF 0x1801 ///< No available Rx buffer (Advertiser, Scanner, Initiator)
+#define BLE_ERROR_NO_SETUP 0x1802 ///< Operation using Rx or Tx attempted when not in BLE mode
+#define BLE_ERROR_NO_FS 0x1803 ///< Operation using Rx or Tx attempted without frequency synth configured
+#define BLE_ERROR_SYNTH_PROG 0x1804 ///< Synthesizer programming failed to complete on time
+#define BLE_ERROR_RXOVF 0x1805 ///< Receiver overflowed during operation
+#define BLE_ERROR_TXUNF 0x1806 ///< Transmitter underflowed during operation
+#define BLE_ERROR_AUX 0x1807 ///< Calculated AUX pointer was too far into the future or in the past
+///@}
+///@}
+
+
+/// Special trigger for BLE slave command
+#define BLE_TRIG_REL_SYNC 15
+
+#endif
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_common_cmd.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_common_cmd.h
new file mode 100644
index 0000000..b479f88
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_common_cmd.h
@@ -0,0 +1,1089 @@
+/******************************************************************************
+* Filename: rf_common_cmd.h
+* Revised: 2018-11-02 11:52:02 +0100 (Fri, 02 Nov 2018)
+* Revision: 18756
+*
+* Description: CC13x2/CC26x2 API for common/generic commands
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __COMMON_CMD_H
+#define __COMMON_CMD_H
+
+#ifndef __RFC_STRUCT
+#define __RFC_STRUCT
+#endif
+
+#ifndef __RFC_STRUCT_ATTR
+#if defined(__GNUC__)
+#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4)))
+#elif defined(__TI_ARM__)
+#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4)))
+#else
+#define __RFC_STRUCT_ATTR
+#endif
+#endif
+
+//! \addtogroup rfc
+//! @{
+
+//! \addtogroup common_cmd
+//! @{
+
+#include <stdint.h>
+#include "rf_mailbox.h"
+
+typedef struct __RFC_STRUCT rfc_command_s rfc_command_t;
+typedef struct __RFC_STRUCT rfc_radioOp_s rfc_radioOp_t;
+typedef struct __RFC_STRUCT rfc_CMD_NOP_s rfc_CMD_NOP_t;
+typedef struct __RFC_STRUCT rfc_CMD_RADIO_SETUP_s rfc_CMD_RADIO_SETUP_t;
+typedef struct __RFC_STRUCT rfc_CMD_FS_s rfc_CMD_FS_t;
+typedef struct __RFC_STRUCT rfc_CMD_FS_OFF_s rfc_CMD_FS_OFF_t;
+typedef struct __RFC_STRUCT rfc_CMD_RX_TEST_s rfc_CMD_RX_TEST_t;
+typedef struct __RFC_STRUCT rfc_CMD_TX_TEST_s rfc_CMD_TX_TEST_t;
+typedef struct __RFC_STRUCT rfc_CMD_SYNC_STOP_RAT_s rfc_CMD_SYNC_STOP_RAT_t;
+typedef struct __RFC_STRUCT rfc_CMD_SYNC_START_RAT_s rfc_CMD_SYNC_START_RAT_t;
+typedef struct __RFC_STRUCT rfc_CMD_RESYNC_RAT_s rfc_CMD_RESYNC_RAT_t;
+typedef struct __RFC_STRUCT rfc_CMD_COUNT_s rfc_CMD_COUNT_t;
+typedef struct __RFC_STRUCT rfc_CMD_FS_POWERUP_s rfc_CMD_FS_POWERUP_t;
+typedef struct __RFC_STRUCT rfc_CMD_FS_POWERDOWN_s rfc_CMD_FS_POWERDOWN_t;
+typedef struct __RFC_STRUCT rfc_CMD_SCH_IMM_s rfc_CMD_SCH_IMM_t;
+typedef struct __RFC_STRUCT rfc_CMD_COUNT_BRANCH_s rfc_CMD_COUNT_BRANCH_t;
+typedef struct __RFC_STRUCT rfc_CMD_PATTERN_CHECK_s rfc_CMD_PATTERN_CHECK_t;
+typedef struct __RFC_STRUCT rfc_CMD_RADIO_SETUP_PA_s rfc_CMD_RADIO_SETUP_PA_t;
+typedef struct __RFC_STRUCT rfc_CMD_ABORT_s rfc_CMD_ABORT_t;
+typedef struct __RFC_STRUCT rfc_CMD_STOP_s rfc_CMD_STOP_t;
+typedef struct __RFC_STRUCT rfc_CMD_GET_RSSI_s rfc_CMD_GET_RSSI_t;
+typedef struct __RFC_STRUCT rfc_CMD_UPDATE_RADIO_SETUP_s rfc_CMD_UPDATE_RADIO_SETUP_t;
+typedef struct __RFC_STRUCT rfc_CMD_TRIGGER_s rfc_CMD_TRIGGER_t;
+typedef struct __RFC_STRUCT rfc_CMD_GET_FW_INFO_s rfc_CMD_GET_FW_INFO_t;
+typedef struct __RFC_STRUCT rfc_CMD_START_RAT_s rfc_CMD_START_RAT_t;
+typedef struct __RFC_STRUCT rfc_CMD_PING_s rfc_CMD_PING_t;
+typedef struct __RFC_STRUCT rfc_CMD_READ_RFREG_s rfc_CMD_READ_RFREG_t;
+typedef struct __RFC_STRUCT rfc_CMD_ADD_DATA_ENTRY_s rfc_CMD_ADD_DATA_ENTRY_t;
+typedef struct __RFC_STRUCT rfc_CMD_REMOVE_DATA_ENTRY_s rfc_CMD_REMOVE_DATA_ENTRY_t;
+typedef struct __RFC_STRUCT rfc_CMD_FLUSH_QUEUE_s rfc_CMD_FLUSH_QUEUE_t;
+typedef struct __RFC_STRUCT rfc_CMD_CLEAR_RX_s rfc_CMD_CLEAR_RX_t;
+typedef struct __RFC_STRUCT rfc_CMD_REMOVE_PENDING_ENTRIES_s rfc_CMD_REMOVE_PENDING_ENTRIES_t;
+typedef struct __RFC_STRUCT rfc_CMD_SET_RAT_CMP_s rfc_CMD_SET_RAT_CMP_t;
+typedef struct __RFC_STRUCT rfc_CMD_SET_RAT_CPT_s rfc_CMD_SET_RAT_CPT_t;
+typedef struct __RFC_STRUCT rfc_CMD_DISABLE_RAT_CH_s rfc_CMD_DISABLE_RAT_CH_t;
+typedef struct __RFC_STRUCT rfc_CMD_SET_RAT_OUTPUT_s rfc_CMD_SET_RAT_OUTPUT_t;
+typedef struct __RFC_STRUCT rfc_CMD_ARM_RAT_CH_s rfc_CMD_ARM_RAT_CH_t;
+typedef struct __RFC_STRUCT rfc_CMD_DISARM_RAT_CH_s rfc_CMD_DISARM_RAT_CH_t;
+typedef struct __RFC_STRUCT rfc_CMD_SET_TX_POWER_s rfc_CMD_SET_TX_POWER_t;
+typedef struct __RFC_STRUCT rfc_CMD_SET_TX20_POWER_s rfc_CMD_SET_TX20_POWER_t;
+typedef struct __RFC_STRUCT rfc_CMD_CHANGE_PA_s rfc_CMD_CHANGE_PA_t;
+typedef struct __RFC_STRUCT rfc_CMD_UPDATE_HPOSC_FREQ_s rfc_CMD_UPDATE_HPOSC_FREQ_t;
+typedef struct __RFC_STRUCT rfc_CMD_UPDATE_FS_s rfc_CMD_UPDATE_FS_t;
+typedef struct __RFC_STRUCT rfc_CMD_MODIFY_FS_s rfc_CMD_MODIFY_FS_t;
+typedef struct __RFC_STRUCT rfc_CMD_BUS_REQUEST_s rfc_CMD_BUS_REQUEST_t;
+typedef struct __RFC_STRUCT rfc_CMD_SET_CMD_START_IRQ_s rfc_CMD_SET_CMD_START_IRQ_t;
+
+//! \addtogroup command
+//! @{
+struct __RFC_STRUCT rfc_command_s {
+ uint16_t commandNo; //!< The command ID number
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup radioOp
+//! @{
+//! Common definition for radio operation commands
+
+struct __RFC_STRUCT rfc_radioOp_s {
+ uint16_t commandNo; //!< The command ID number
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_NOP
+//! @{
+#define CMD_NOP 0x0801
+//! No Operation Command
+struct __RFC_STRUCT rfc_CMD_NOP_s {
+ uint16_t commandNo; //!< The command ID number 0x0801
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_RADIO_SETUP
+//! @{
+#define CMD_RADIO_SETUP 0x0802
+//! Radio Setup Command for Pre-Defined Schemes
+struct __RFC_STRUCT rfc_CMD_RADIO_SETUP_s {
+ uint16_t commandNo; //!< The command ID number 0x0802
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint8_t mode; //!< \brief The main mode to use<br>
+ //!< 0x00: BLE<br>
+ //!< 0x01: IEEE 802.15.4<br>
+ //!< 0x02: 2 Mbps GFSK<br>
+ //!< 0x05: 5 Mbps coded 8-FSK<br>
+ //!< 0xFF: Keep existing mode; update overrides only<br>
+ //!< Others: <i>Reserved</i>
+ uint8_t loDivider; //!< \brief LO divider setting to use. Supported values: 0, 2, 4,
+ //!< 5, 6, 10, 12, 15, and 30.
+ struct {
+ uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode<br>
+ //!< 0x01: Single-ended mode RFP<br>
+ //!< 0x02: Single-ended mode RFN<br>
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)<br>
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)<br>
+ //!< Others: <i>Reserved</i>
+ uint16_t biasMode:1; //!< \brief 0: Internal bias<br>
+ //!< 1: External bias
+ uint16_t analogCfgMode:6; //!< \brief 0x00: Write analog configuration.<br>
+ //!< Required first time after boot and when changing frequency band
+ //!< or front-end configuration<br>
+ //!< 0x2D: Keep analog configuration.<br>
+ //!< May be used after standby or when changing mode with the same frequency
+ //!< band and front-end configuration<br>
+ //!< Others: <i>Reserved</i>
+ uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth<br>
+ //!< 1: Do not power up frequency synth
+ } config; //!< Configuration options
+ uint16_t txPower; //!< Transmit power
+ uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no
+ //!< override is used.
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_FS
+//! @{
+#define CMD_FS 0x0803
+//! Frequency Synthesizer Programming Command
+struct __RFC_STRUCT rfc_CMD_FS_s {
+ uint16_t commandNo; //!< The command ID number 0x0803
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint16_t frequency; //!< The frequency in MHz to tune to
+ uint16_t fractFreq; //!< Fractional part of the frequency to tune to
+ struct {
+ uint8_t bTxMode:1; //!< \brief 0: Start synth in RX mode<br>
+ //!< 1: Start synth in TX mode
+ uint8_t refFreq:6; //!< \brief 0: Use default reference frequency<br>
+ //!< Others: Use reference frequency 48 MHz/<code>refFreq</code>
+ } synthConf;
+ uint8_t __dummy0; //!< <i>Reserved</i>, always write 0
+ uint8_t __dummy1; //!< <i>Reserved</i>
+ uint8_t __dummy2; //!< <i>Reserved</i>
+ uint16_t __dummy3; //!< <i>Reserved</i>
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_FS_OFF
+//! @{
+#define CMD_FS_OFF 0x0804
+//! Command for Turning off Frequency Synthesizer
+struct __RFC_STRUCT rfc_CMD_FS_OFF_s {
+ uint16_t commandNo; //!< The command ID number 0x0804
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_RX_TEST
+//! @{
+#define CMD_RX_TEST 0x0807
+//! Receiver Test Command
+struct __RFC_STRUCT rfc_CMD_RX_TEST_s {
+ uint16_t commandNo; //!< The command ID number 0x0807
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ struct {
+ uint8_t bEnaFifo:1; //!< \brief 0: Do not enable FIFO in modem, so that received data is not available<br>
+ //!< 1: Enable FIFO in modem -- the data must be read out by the application
+ uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command<br>
+ //!< 1: Turn frequency synth off after command
+ uint8_t bNoSync:1; //!< \brief 0: Run sync search as normal for the configured mode<br>
+ //!< 1: Write correlation thresholds to the maximum value to avoid getting sync
+ } config;
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } endTrigger; //!< Trigger classifier for ending the operation
+ uint32_t syncWord; //!< Sync word to use for receiver
+ ratmr_t endTime; //!< Time to end the operation
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_TX_TEST
+//! @{
+#define CMD_TX_TEST 0x0808
+//! Transmitter Test Command
+struct __RFC_STRUCT rfc_CMD_TX_TEST_s {
+ uint16_t commandNo; //!< The command ID number 0x0808
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ struct {
+ uint8_t bUseCw:1; //!< \brief 0: Send modulated signal<br>
+ //!< 1: Send continuous wave
+ uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command<br>
+ //!< 1: Turn frequency synth off after command
+ uint8_t whitenMode:2; //!< \brief 0: No whitening<br>
+ //!< 1: Default whitening<br>
+ //!< 2: PRBS-15<br>
+ //!< 3: PRBS-32
+ } config;
+ uint8_t __dummy0;
+ uint16_t txWord; //!< Value to send to the modem before whitening
+ uint8_t __dummy1;
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } endTrigger; //!< Trigger classifier for ending the operation
+ uint32_t syncWord; //!< Sync word to use for transmitter
+ ratmr_t endTime; //!< Time to end the operation
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_SYNC_STOP_RAT
+//! @{
+#define CMD_SYNC_STOP_RAT 0x0809
+//! Synchronize and Stop Radio Timer Command
+struct __RFC_STRUCT rfc_CMD_SYNC_STOP_RAT_s {
+ uint16_t commandNo; //!< The command ID number 0x0809
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint16_t __dummy0;
+ ratmr_t rat0; //!< \brief The returned RAT timer value corresponding to the value the RAT would have had when the
+ //!< RTC was zero
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_SYNC_START_RAT
+//! @{
+#define CMD_SYNC_START_RAT 0x080A
+//! Synchrously Start Radio Timer Command
+struct __RFC_STRUCT rfc_CMD_SYNC_START_RAT_s {
+ uint16_t commandNo; //!< The command ID number 0x080A
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint16_t __dummy0;
+ ratmr_t rat0; //!< \brief The desired RAT timer value corresponding to the value the RAT would have had when the
+ //!< RTC was zero. This parameter is returned by CMD_SYNC_STOP_RAT
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_RESYNC_RAT
+//! @{
+#define CMD_RESYNC_RAT 0x0816
+//! Re-calculate rat0 value while RAT is running
+struct __RFC_STRUCT rfc_CMD_RESYNC_RAT_s {
+ uint16_t commandNo; //!< The command ID number 0x0816
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint16_t __dummy0;
+ ratmr_t rat0; //!< \brief The desired RAT timer value corresponding to the value the RAT would have had when the
+ //!< RTC was zero
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_COUNT
+//! @{
+#define CMD_COUNT 0x080B
+//! Counter Command
+struct __RFC_STRUCT rfc_CMD_COUNT_s {
+ uint16_t commandNo; //!< The command ID number 0x080B
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint16_t counter; //!< \brief Counter. On start, the radio CPU decrements the value, and the end status of the operation
+ //!< differs if the result is zero
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_FS_POWERUP
+//! @{
+#define CMD_FS_POWERUP 0x080C
+//! Power up Frequency Syntheszier Command
+struct __RFC_STRUCT rfc_CMD_FS_POWERUP_s {
+ uint16_t commandNo; //!< The command ID number 0x080C
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint16_t __dummy0;
+ uint32_t* pRegOverride; //!< Pointer to a list of hardware and configuration registers to override. If NULL, no override is used.
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_FS_POWERDOWN
+//! @{
+#define CMD_FS_POWERDOWN 0x080D
+//! Power down Frequency Syntheszier Command
+struct __RFC_STRUCT rfc_CMD_FS_POWERDOWN_s {
+ uint16_t commandNo; //!< The command ID number 0x080D
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_SCH_IMM
+//! @{
+#define CMD_SCH_IMM 0x0810
+//! Run Immidiate Command as Radio Operation Command
+struct __RFC_STRUCT rfc_CMD_SCH_IMM_s {
+ uint16_t commandNo; //!< The command ID number 0x0810
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint16_t __dummy0;
+ uint32_t cmdrVal; //!< Value as would be written to CMDR
+ uint32_t cmdstaVal; //!< Value as would be returned in CMDSTA
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_COUNT_BRANCH
+//! @{
+#define CMD_COUNT_BRANCH 0x0812
+//! Counter Command with Branch of Command Chain
+struct __RFC_STRUCT rfc_CMD_COUNT_BRANCH_s {
+ uint16_t commandNo; //!< The command ID number 0x0812
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint16_t counter; //!< \brief Counter. On start, the radio CPU decrements the value, and the end status of the operation
+ //!< differs if the result is zero
+ rfc_radioOp_t *pNextOpIfOk; //!< Pointer to next operation if counter did not expire
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_PATTERN_CHECK
+//! @{
+#define CMD_PATTERN_CHECK 0x0813
+//! Command for Checking a Value in Memory aginst a Pattern
+struct __RFC_STRUCT rfc_CMD_PATTERN_CHECK_s {
+ uint16_t commandNo; //!< The command ID number 0x0813
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ struct {
+ uint16_t operation:2; //!< \brief Operation to perform<br>
+ //!< 0: True if value == <code>compareVal</code><br>
+ //!< 1: True if value < <code>compareVal</code><br>
+ //!< 2: True if value > <code>compareVal</code><br>
+ //!< 3: <i>Reserved</i>
+ uint16_t bByteRev:1; //!< \brief If 1, interchange the four bytes of the value, so that they are read
+ //!< most-significant-byte-first.
+ uint16_t bBitRev:1; //!< If 1, perform bit reversal of the value
+ uint16_t signExtend:5; //!< \brief 0: Treat value and <code>compareVal</code> as unsigned<br>
+ //!< 1--31: Treat value and <code>compareVal</code> as signed, where the value
+ //!< gives the number of the most significant bit in the signed number.
+ uint16_t bRxVal:1; //!< \brief 0: Use <code>pValue</code> as a pointer<br>
+ //!< 1: Use <code>pValue</code> as a signed offset to the start of the last
+ //!< committed RX entry element
+ } patternOpt; //!< Options for comparison
+ rfc_radioOp_t *pNextOpIfOk; //!< Pointer to next operation if comparison result was true
+ uint8_t* pValue; //!< Pointer to read from, or offset from last RX entry if <code>patternOpt.bRxVal</code> == 1
+ uint32_t mask; //!< Bit mask to apply before comparison
+ uint32_t compareVal; //!< Value to compare to
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_RADIO_SETUP_PA
+//! @{
+//! Radio Setup Command for Pre-Defined Schemes with PA Switching Fields
+struct __RFC_STRUCT rfc_CMD_RADIO_SETUP_PA_s {
+ uint16_t commandNo; //!< The command ID number
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint8_t mode; //!< \brief The main mode to use<br>
+ //!< 0x00: BLE<br>
+ //!< 0x01: IEEE 802.15.4<br>
+ //!< 0x02: 2 Mbps GFSK<br>
+ //!< 0x05: 5 Mbps coded 8-FSK<br>
+ //!< 0xFF: Keep existing mode; update overrides only<br>
+ //!< Others: <i>Reserved</i>
+ uint8_t loDivider; //!< \brief LO divider setting to use. Supported values: 0, 2, 4,
+ //!< 5, 6, 10, 12, 15, and 30.
+ struct {
+ uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode<br>
+ //!< 0x01: Single-ended mode RFP<br>
+ //!< 0x02: Single-ended mode RFN<br>
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)<br>
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)<br>
+ //!< Others: <i>Reserved</i>
+ uint16_t biasMode:1; //!< \brief 0: Internal bias<br>
+ //!< 1: External bias
+ uint16_t analogCfgMode:6; //!< \brief 0x00: Write analog configuration.<br>
+ //!< Required first time after boot and when changing frequency band
+ //!< or front-end configuration<br>
+ //!< 0x2D: Keep analog configuration.<br>
+ //!< May be used after standby or when changing mode with the same frequency
+ //!< band and front-end configuration<br>
+ //!< Others: <i>Reserved</i>
+ uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth<br>
+ //!< 1: Do not power up frequency synth
+ } config; //!< Configuration options
+ uint16_t txPower; //!< Transmit power
+ uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no
+ //!< override is used.
+ uint32_t* pRegOverrideTxStd; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to
+ //!< standard PA. Used by RF driver only, not radio CPU.
+ uint32_t* pRegOverrideTx20; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to
+ //!< 20-dBm PA. Used by RF driver only, not radio CPU.
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_ABORT
+//! @{
+#define CMD_ABORT 0x0401
+//! Abort Running Radio Operation Command
+struct __RFC_STRUCT rfc_CMD_ABORT_s {
+ uint16_t commandNo; //!< The command ID number 0x0401
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_STOP
+//! @{
+#define CMD_STOP 0x0402
+//! Stop Running Radio Operation Command Gracefully
+struct __RFC_STRUCT rfc_CMD_STOP_s {
+ uint16_t commandNo; //!< The command ID number 0x0402
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_GET_RSSI
+//! @{
+#define CMD_GET_RSSI 0x0403
+//! Read RSSI Command
+struct __RFC_STRUCT rfc_CMD_GET_RSSI_s {
+ uint16_t commandNo; //!< The command ID number 0x0403
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_UPDATE_RADIO_SETUP
+//! @{
+#define CMD_UPDATE_RADIO_SETUP 0x0001
+//! Update Radio Settings Command
+struct __RFC_STRUCT rfc_CMD_UPDATE_RADIO_SETUP_s {
+ uint16_t commandNo; //!< The command ID number 0x0001
+ uint16_t __dummy0;
+ uint32_t* pRegOverride; //!< Pointer to a list of hardware and configuration registers to override
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_TRIGGER
+//! @{
+#define CMD_TRIGGER 0x0404
+//! Generate Command Trigger
+struct __RFC_STRUCT rfc_CMD_TRIGGER_s {
+ uint16_t commandNo; //!< The command ID number 0x0404
+ uint8_t triggerNo; //!< Command trigger number
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_GET_FW_INFO
+//! @{
+#define CMD_GET_FW_INFO 0x0002
+//! Request Information on the RF Core ROM Firmware
+struct __RFC_STRUCT rfc_CMD_GET_FW_INFO_s {
+ uint16_t commandNo; //!< The command ID number 0x0002
+ uint16_t versionNo; //!< Firmware version number
+ uint16_t startOffset; //!< The start of free RAM
+ uint16_t freeRamSz; //!< The size of free RAM
+ uint16_t availRatCh; //!< Bitmap of available RAT channels
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_START_RAT
+//! @{
+#define CMD_START_RAT 0x0405
+//! Asynchronously Start Radio Timer Command
+struct __RFC_STRUCT rfc_CMD_START_RAT_s {
+ uint16_t commandNo; //!< The command ID number 0x0405
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_PING
+//! @{
+#define CMD_PING 0x0406
+//! Respond with Command ACK Only
+struct __RFC_STRUCT rfc_CMD_PING_s {
+ uint16_t commandNo; //!< The command ID number 0x0406
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_READ_RFREG
+//! @{
+#define CMD_READ_RFREG 0x0601
+//! Read RF Core Hardware Register
+struct __RFC_STRUCT rfc_CMD_READ_RFREG_s {
+ uint16_t commandNo; //!< The command ID number 0x0601
+ uint16_t address; //!< The offset from the start of the RF core HW register bank (0x40040000)
+ uint32_t value; //!< Returned value of the register
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_ADD_DATA_ENTRY
+//! @{
+#define CMD_ADD_DATA_ENTRY 0x0005
+//! Add Data Entry to Queue
+struct __RFC_STRUCT rfc_CMD_ADD_DATA_ENTRY_s {
+ uint16_t commandNo; //!< The command ID number 0x0005
+ uint16_t __dummy0;
+ dataQueue_t* pQueue; //!< Pointer to the queue structure to which the entry will be added
+ uint8_t* pEntry; //!< Pointer to the entry
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_REMOVE_DATA_ENTRY
+//! @{
+#define CMD_REMOVE_DATA_ENTRY 0x0006
+//! Remove First Data Entry from Queue
+struct __RFC_STRUCT rfc_CMD_REMOVE_DATA_ENTRY_s {
+ uint16_t commandNo; //!< The command ID number 0x0006
+ uint16_t __dummy0;
+ dataQueue_t* pQueue; //!< Pointer to the queue structure from which the entry will be removed
+ uint8_t* pEntry; //!< Pointer to the entry that was removed
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_FLUSH_QUEUE
+//! @{
+#define CMD_FLUSH_QUEUE 0x0007
+//! Flush Data Queue
+struct __RFC_STRUCT rfc_CMD_FLUSH_QUEUE_s {
+ uint16_t commandNo; //!< The command ID number 0x0007
+ uint16_t __dummy0;
+ dataQueue_t* pQueue; //!< Pointer to the queue structure to be flushed
+ uint8_t* pFirstEntry; //!< Pointer to the first entry that was removed
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_CLEAR_RX
+//! @{
+#define CMD_CLEAR_RX 0x0008
+//! Clear all RX Queue Entries
+struct __RFC_STRUCT rfc_CMD_CLEAR_RX_s {
+ uint16_t commandNo; //!< The command ID number 0x0008
+ uint16_t __dummy0;
+ dataQueue_t* pQueue; //!< Pointer to the queue structure to be cleared
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_REMOVE_PENDING_ENTRIES
+//! @{
+#define CMD_REMOVE_PENDING_ENTRIES 0x0009
+//! Remove Pending Entries from Queue
+struct __RFC_STRUCT rfc_CMD_REMOVE_PENDING_ENTRIES_s {
+ uint16_t commandNo; //!< The command ID number 0x0009
+ uint16_t __dummy0;
+ dataQueue_t* pQueue; //!< Pointer to the queue structure to be flushed
+ uint8_t* pFirstEntry; //!< Pointer to the first entry that was removed
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_SET_RAT_CMP
+//! @{
+#define CMD_SET_RAT_CMP 0x000A
+//! Set Radio Timer Channel in Compare Mode
+struct __RFC_STRUCT rfc_CMD_SET_RAT_CMP_s {
+ uint16_t commandNo; //!< The command ID number 0x000A
+ uint8_t ratCh; //!< The radio timer channel number
+ uint8_t __dummy0;
+ ratmr_t compareTime; //!< The time at which the compare occurs
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_SET_RAT_CPT
+//! @{
+#define CMD_SET_RAT_CPT 0x0603
+//! Set Radio Timer Channel in Capture Mode
+struct __RFC_STRUCT rfc_CMD_SET_RAT_CPT_s {
+ uint16_t commandNo; //!< The command ID number 0x0603
+ struct {
+ uint16_t :3;
+ uint16_t inputSrc:5; //!< Input source indicator
+ uint16_t ratCh:4; //!< The radio timer channel number
+ uint16_t bRepeated:1; //!< \brief 0: Single capture mode<br>
+ //!< 1: Repeated capture mode
+ uint16_t inputMode:2; //!< \brief Input mode:<br>
+ //!< 0: Capture on rising edge<br>
+ //!< 1: Capture on falling edge<br>
+ //!< 2: Capture on both edges<br>
+ //!< 3: <i>Reserved</i>
+ } config;
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_DISABLE_RAT_CH
+//! @{
+#define CMD_DISABLE_RAT_CH 0x0408
+//! Disable Radio Timer Channel
+struct __RFC_STRUCT rfc_CMD_DISABLE_RAT_CH_s {
+ uint16_t commandNo; //!< The command ID number 0x0408
+ uint8_t ratCh; //!< The radio timer channel number
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_SET_RAT_OUTPUT
+//! @{
+#define CMD_SET_RAT_OUTPUT 0x0604
+//! Set Radio Timer Output to a Specified Mode
+struct __RFC_STRUCT rfc_CMD_SET_RAT_OUTPUT_s {
+ uint16_t commandNo; //!< The command ID number 0x0604
+ struct {
+ uint16_t :2;
+ uint16_t outputSel:3; //!< Output event indicator
+ uint16_t outputMode:3; //!< \brief 0: Set output line low as default; and pulse on event. Duration of pulse is one RF Core clock period (ca. 41.67 ns).<br>
+ //!< 1: Set output line high on event<br>
+ //!< 2: Set output line low on event<br>
+ //!< 3: Toggle (invert) output line state on event<br>
+ //!< 4: Immediately set output line to low (does not change upon event)<br>
+ //!< 5: Immediately set output line to high (does not change upon event)<br>
+ //!< Others: <i>Reserved</i>
+ uint16_t ratCh:4; //!< The radio timer channel number
+ } config;
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_ARM_RAT_CH
+//! @{
+#define CMD_ARM_RAT_CH 0x0409
+//! Arm Radio Timer Channel
+struct __RFC_STRUCT rfc_CMD_ARM_RAT_CH_s {
+ uint16_t commandNo; //!< The command ID number 0x0409
+ uint8_t ratCh; //!< The radio timer channel number
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_DISARM_RAT_CH
+//! @{
+#define CMD_DISARM_RAT_CH 0x040A
+//! Disarm Radio Timer Channel
+struct __RFC_STRUCT rfc_CMD_DISARM_RAT_CH_s {
+ uint16_t commandNo; //!< The command ID number 0x040A
+ uint8_t ratCh; //!< The radio timer channel number
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_SET_TX_POWER
+//! @{
+#define CMD_SET_TX_POWER 0x0010
+//! Set Transmit Power
+struct __RFC_STRUCT rfc_CMD_SET_TX_POWER_s {
+ uint16_t commandNo; //!< The command ID number 0x0010
+ uint16_t txPower; //!< New TX power setting
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_SET_TX20_POWER
+//! @{
+#define CMD_SET_TX20_POWER 0x0014
+//! Set Transmit Power for 20-dBm PA
+struct __RFC_STRUCT rfc_CMD_SET_TX20_POWER_s {
+ uint16_t commandNo; //!< The command ID number 0x0014
+ uint16_t __dummy0;
+ uint32_t tx20Power; //!< New TX power setting
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_CHANGE_PA
+//! @{
+#define CMD_CHANGE_PA 0x0015
+//! Set TX power with possibility to switch between PAs
+struct __RFC_STRUCT rfc_CMD_CHANGE_PA_s {
+ uint16_t commandNo; //!< The command ID number 0x0015
+ uint16_t __dummy0;
+ uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override as part of the
+ //!< change, including new TX power
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_UPDATE_HPOSC_FREQ
+//! @{
+#define CMD_UPDATE_HPOSC_FREQ 0x0608
+//! Set New Frequency Offset for HPOSC
+struct __RFC_STRUCT rfc_CMD_UPDATE_HPOSC_FREQ_s {
+ uint16_t commandNo; //!< The command ID number 0x0608
+ int16_t freqOffset; //!< Relative frequency offset, signed, scaled by 2<sup>-22</sup>
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_UPDATE_FS
+//! @{
+#define CMD_UPDATE_FS 0x0011
+//! Set New Synthesizer Frequency without Recalibration (Deprecated; use CMD_MODIFY_FS)
+struct __RFC_STRUCT rfc_CMD_UPDATE_FS_s {
+ uint16_t commandNo; //!< The command ID number 0x0011
+ uint16_t __dummy0;
+ uint32_t __dummy1;
+ uint32_t __dummy2;
+ uint16_t __dummy3;
+ uint16_t frequency; //!< The frequency in MHz to tune to
+ uint16_t fractFreq; //!< Fractional part of the frequency to tune to
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_MODIFY_FS
+//! @{
+#define CMD_MODIFY_FS 0x0013
+//! Set New Synthesizer Frequency without Recalibration
+struct __RFC_STRUCT rfc_CMD_MODIFY_FS_s {
+ uint16_t commandNo; //!< The command ID number 0x0013
+ uint16_t frequency; //!< The frequency in MHz to tune to
+ uint16_t fractFreq; //!< Fractional part of the frequency to tune to
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_BUS_REQUEST
+//! @{
+#define CMD_BUS_REQUEST 0x040E
+//! Request System Bus to be Availbale
+struct __RFC_STRUCT rfc_CMD_BUS_REQUEST_s {
+ uint16_t commandNo; //!< The command ID number 0x040E
+ uint8_t bSysBusNeeded; //!< \brief 0: System bus may sleep<br>
+ //!< 1: System bus access needed
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_SET_CMD_START_IRQ
+//! @{
+#define CMD_SET_CMD_START_IRQ 0x0411
+//! Enable or disable generation of IRQ when a radio operation command starts
+struct __RFC_STRUCT rfc_CMD_SET_CMD_START_IRQ_s {
+ uint16_t commandNo; //!< The command ID number 0x0411
+ uint8_t bEna; //!< 1 to enable interrupt generation; 0 to disable it
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! @}
+//! @}
+#endif
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_data_entry.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_data_entry.h
new file mode 100644
index 0000000..c79465c
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_data_entry.h
@@ -0,0 +1,219 @@
+/******************************************************************************
+* Filename: rf_data_entry.h
+* Revised: 2018-01-15 06:15:14 +0100 (Mon, 15 Jan 2018)
+* Revision: 18170
+*
+* Description: Definition of API for data exchange
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __DATA_ENTRY_H
+#define __DATA_ENTRY_H
+
+#ifndef __RFC_STRUCT
+#define __RFC_STRUCT
+#endif
+
+#ifndef __RFC_STRUCT_ATTR
+#if defined(__GNUC__)
+#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4)))
+#elif defined(__TI_ARM__)
+#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4)))
+#else
+#define __RFC_STRUCT_ATTR
+#endif
+#endif
+
+//! \addtogroup rfc
+//! @{
+
+//! \addtogroup data_entry
+//! @{
+
+#include <stdint.h>
+#include "rf_mailbox.h"
+
+typedef struct __RFC_STRUCT rfc_dataEntry_s rfc_dataEntry_t;
+typedef struct __RFC_STRUCT rfc_dataEntryGeneral_s rfc_dataEntryGeneral_t;
+typedef struct __RFC_STRUCT rfc_dataEntryMulti_s rfc_dataEntryMulti_t;
+typedef struct __RFC_STRUCT rfc_dataEntryPointer_s rfc_dataEntryPointer_t;
+typedef struct __RFC_STRUCT rfc_dataEntryPartial_s rfc_dataEntryPartial_t;
+
+//! \addtogroup dataEntry
+//! @{
+struct __RFC_STRUCT rfc_dataEntry_s {
+ uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry
+ uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to
+ struct {
+ uint8_t type:2; //!< \brief Type of data entry structure<br>
+ //!< 0: General data entry <br>
+ //!< 1: Multi-element Rx entry<br>
+ //!< 2: Pointer entry<br>
+ //!< 3: Partial read Rx entry
+ uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element<br>
+ //!< 0: No length indicator<br>
+ //!< 1: One byte length indicator<br>
+ //!< 2: Two bytes length indicator<br>
+ //!< 3: <i>Reserved</i>
+ uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated
+ //!< by the radio CPU (0: 16 bytes)
+ } config;
+ uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to<br>
+ //!< For other entries: Number of bytes following this length field
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup dataEntryGeneral
+//! @{
+//! General data entry structure (type = 0)
+
+struct __RFC_STRUCT rfc_dataEntryGeneral_s {
+ uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry
+ uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to
+ struct {
+ uint8_t type:2; //!< \brief Type of data entry structure<br>
+ //!< 0: General data entry <br>
+ //!< 1: Multi-element Rx entry<br>
+ //!< 2: Pointer entry<br>
+ //!< 3: Partial read Rx entry
+ uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element<br>
+ //!< 0: No length indicator<br>
+ //!< 1: One byte length indicator<br>
+ //!< 2: Two bytes length indicator<br>
+ //!< 3: <i>Reserved</i>
+ uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated
+ //!< by the radio CPU (0: 16 bytes)
+ } config;
+ uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to<br>
+ //!< For other entries: Number of bytes following this length field
+ uint8_t data; //!< First byte of the data array to be received or transmitted
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup dataEntryMulti
+//! @{
+//! Multi-element data entry structure (type = 1)
+
+struct __RFC_STRUCT rfc_dataEntryMulti_s {
+ uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry
+ uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to
+ struct {
+ uint8_t type:2; //!< \brief Type of data entry structure<br>
+ //!< 0: General data entry <br>
+ //!< 1: Multi-element Rx entry<br>
+ //!< 2: Pointer entry<br>
+ //!< 3: Partial read Rx entry
+ uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element<br>
+ //!< 0: No length indicator<br>
+ //!< 1: One byte length indicator<br>
+ //!< 2: Two bytes length indicator<br>
+ //!< 3: <i>Reserved</i>
+ uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated
+ //!< by the radio CPU (0: 16 bytes)
+ } config;
+ uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to<br>
+ //!< For other entries: Number of bytes following this length field
+ uint16_t numElements; //!< Number of entry elements committed in the entry
+ uint16_t nextIndex; //!< Index to the byte after the last byte of the last entry element committed by the radio CPU
+ uint8_t rxData; //!< First byte of the data array of received data entry elements
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup dataEntryPointer
+//! @{
+//! Pointer data entry structure (type = 2)
+
+struct __RFC_STRUCT rfc_dataEntryPointer_s {
+ uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry
+ uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to
+ struct {
+ uint8_t type:2; //!< \brief Type of data entry structure<br>
+ //!< 0: General data entry <br>
+ //!< 1: Multi-element Rx entry<br>
+ //!< 2: Pointer entry<br>
+ //!< 3: Partial read Rx entry
+ uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element<br>
+ //!< 0: No length indicator<br>
+ //!< 1: One byte length indicator<br>
+ //!< 2: Two bytes length indicator<br>
+ //!< 3: <i>Reserved</i>
+ uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated
+ //!< by the radio CPU (0: 16 bytes)
+ } config;
+ uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to<br>
+ //!< For other entries: Number of bytes following this length field
+ uint8_t* pData; //!< Pointer to data buffer of data to be received ro transmitted
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup dataEntryPartial
+//! @{
+//! Partial read data entry structure (type = 3)
+
+struct __RFC_STRUCT rfc_dataEntryPartial_s {
+ uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry
+ uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to
+ struct {
+ uint8_t type:2; //!< \brief Type of data entry structure<br>
+ //!< 0: General data entry <br>
+ //!< 1: Multi-element Rx entry<br>
+ //!< 2: Pointer entry<br>
+ //!< 3: Partial read Rx entry
+ uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element<br>
+ //!< 0: No length indicator<br>
+ //!< 1: One byte length indicator<br>
+ //!< 2: Two bytes length indicator<br>
+ //!< 3: <i>Reserved</i>
+ uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated
+ //!< by the radio CPU (0: 16 bytes)
+ } config;
+ uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to<br>
+ //!< For other entries: Number of bytes following this length field
+ struct {
+ uint16_t numElements:13; //!< Number of entry elements committed in the entry
+ uint16_t bEntryOpen:1; //!< 1 if the entry contains an element that is still open for appending data
+ uint16_t bFirstCont:1; //!< 1 if the first element is a continuation of the last packet from the previous entry
+ uint16_t bLastCont:1; //!< 1 if the packet in the last element continues in the next entry
+ } pktStatus;
+ uint16_t nextIndex; //!< Index to the byte after the last byte of the last entry element committed by the radio CPU
+ uint8_t rxData; //!< First byte of the data array of received data entry elements
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! @}
+//! @}
+#endif
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_cmd.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_cmd.h
new file mode 100644
index 0000000..e681acc
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_cmd.h
@@ -0,0 +1,210 @@
+/******************************************************************************
+* Filename: rf_hs_cmd.h
+* Revised: 2018-01-15 06:15:14 +0100 (Mon, 15 Jan 2018)
+* Revision: 18170
+*
+* Description: CC13x2/CC26x2 API for high-speed mode commands
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HS_CMD_H
+#define __HS_CMD_H
+
+#ifndef __RFC_STRUCT
+#define __RFC_STRUCT
+#endif
+
+#ifndef __RFC_STRUCT_ATTR
+#if defined(__GNUC__)
+#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4)))
+#elif defined(__TI_ARM__)
+#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4)))
+#else
+#define __RFC_STRUCT_ATTR
+#endif
+#endif
+
+//! \addtogroup rfc
+//! @{
+
+//! \addtogroup hs_cmd
+//! @{
+
+#include <stdint.h>
+#include "rf_mailbox.h"
+#include "rf_common_cmd.h"
+
+typedef struct __RFC_STRUCT rfc_CMD_HS_TX_s rfc_CMD_HS_TX_t;
+typedef struct __RFC_STRUCT rfc_CMD_HS_RX_s rfc_CMD_HS_RX_t;
+typedef struct __RFC_STRUCT rfc_hsRxOutput_s rfc_hsRxOutput_t;
+typedef struct __RFC_STRUCT rfc_hsRxStatus_s rfc_hsRxStatus_t;
+
+//! \addtogroup CMD_HS_TX
+//! @{
+#define CMD_HS_TX 0x3841
+//! High-Speed Transmit Command
+struct __RFC_STRUCT rfc_CMD_HS_TX_s {
+ uint16_t commandNo; //!< The command ID number 0x3841
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ struct {
+ uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command<br>
+ //!< 1: Turn frequency synth off after command
+ uint8_t bUseCrc:1; //!< \brief 0: Do not append CRC<br>
+ //!< 1: Append CRC
+ uint8_t bVarLen:1; //!< \brief 0: Fixed length<br>
+ //!< 1: Transmit length as first half-word
+ uint8_t bCheckQAtEnd:1; //!< \brief 0: Always end with HS_DONE_OK when packet has been transmitted<br>
+ //!< 1: Check if Tx queue is empty when packet has been transmitted
+ } pktConf;
+ uint8_t __dummy0;
+ dataQueue_t* pQueue; //!< Pointer to Tx queue
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_HS_RX
+//! @{
+#define CMD_HS_RX 0x3842
+//! High-Speed Receive Command
+struct __RFC_STRUCT rfc_CMD_HS_RX_s {
+ uint16_t commandNo; //!< The command ID number 0x3842
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ struct {
+ uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command<br>
+ //!< 1: Turn frequency synth off after command
+ uint8_t bUseCrc:1; //!< \brief 0: Do not receive or check CRC<br>
+ //!< 1: Receive and check CRC
+ uint8_t bVarLen:1; //!< \brief 0: Fixed length<br>
+ //!< 1: Receive length as first byte
+ uint8_t bRepeatOk:1; //!< \brief 0: End operation after receiving a packet correctly<br>
+ //!< 1: Go back to sync search after receiving a packet correctly
+ uint8_t bRepeatNok:1; //!< \brief 0: End operation after receiving a packet with CRC error<br>
+ //!< 1: Go back to sync search after receiving a packet with CRC error
+ uint8_t addressMode:2; //!< \brief 0: No address check<br>
+ //!< 1: Accept <code>address0</code> and <code>address1</code><br>
+ //!< 2: Accept <code>address0</code>, <code>address1</code>, and 0x0000<br>
+ //!< 3: Accept <code>address0</code>, <code>address1</code>, 0x0000, and 0xFFFF
+ } pktConf;
+ struct {
+ uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue
+ uint8_t bIncludeLen:1; //!< If 1, include the received length field in the stored packet; otherwise discard it
+ uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise 3scard it
+ uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue
+ uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue
+ } rxConf;
+ uint16_t maxPktLen; //!< Packet length for fixed length; maximum packet length for variable length
+ uint16_t address0; //!< Address
+ uint16_t address1; //!< Address (set equal to <code>address0</code> to accept only one address)
+ uint8_t __dummy0;
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } endTrigger; //!< Trigger classifier for ending the operation
+ ratmr_t endTime; //!< Time used together with <code>endTrigger</code> for ending the operation
+ dataQueue_t* pQueue; //!< Pointer to receive queue
+ rfc_hsRxOutput_t *pOutput; //!< Pointer to output structure
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup hsRxOutput
+//! @{
+//! Output structure for CMD_HS_RX
+
+struct __RFC_STRUCT rfc_hsRxOutput_s {
+ uint16_t nRxOk; //!< Number of packets that have been received with CRC OK
+ uint16_t nRxNok; //!< Number of packets that have been received with CRC error
+ uint16_t nRxAborted; //!< Number of packets not received due to illegal length or address mismatch
+ uint8_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space
+ int8_t lastRssi; //!< RSSI of last received packet
+ ratmr_t timeStamp; //!< Time stamp of last received packet
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup hsRxStatus
+//! @{
+//! Receive status word that may be appended to message in receive buffer
+
+struct __RFC_STRUCT rfc_hsRxStatus_s {
+ struct {
+ uint16_t rssi:8; //!< RSSI of the received packet in dBm (signed)
+ uint16_t bCrcErr:1; //!< \brief 0: Packet received OK<br>
+ //!< 1: Packet received with CRC error
+ uint16_t addressInd:2; //!< \brief 0: Received <code>address0</code> (or no address check)<br>
+ //!< 1: Received <code>address1</code><br>
+ //!< 2: Received address 0x0000<br>
+ //!< 3: Received address 0xFFFF
+ } status;
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! @}
+//! @}
+#endif
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_mailbox.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_mailbox.h
new file mode 100644
index 0000000..e1fb7a0
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_mailbox.h
@@ -0,0 +1,65 @@
+/******************************************************************************
+* Filename: rf_hs_mailbox.h
+* Revised: 2018-01-15 15:58:36 +0100 (Mon, 15 Jan 2018)
+* Revision: 18171
+*
+* Description: Definitions for high-speed mode radio interface
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef _HS_MAILBOX_H
+#define _HS_MAILBOX_H
+
+/// \name Radio operation status
+///@{
+/// \name Operation finished normally
+///@{
+#define HS_DONE_OK 0x3440 ///< Operation ended normally
+#define HS_DONE_RXTIMEOUT 0x3441 ///< Operation stopped after end trigger while waiting for sync
+#define HS_DONE_RXERR 0x3442 ///< Operation ended after CRC error
+#define HS_DONE_TXBUF 0x3443 ///< Tx queue was empty at start of operation
+#define HS_DONE_ENDED 0x3444 ///< Operation stopped after end trigger during reception
+#define HS_DONE_STOPPED 0x3445 ///< Operation stopped after stop command
+#define HS_DONE_ABORT 0x3446 ///< Operation aborted by abort command
+///@}
+/// \name Operation finished with error
+///@{
+#define HS_ERROR_PAR 0x3840 ///< Illegal parameter
+#define HS_ERROR_RXBUF 0x3841 ///< No available Rx buffer at the start of a packet
+#define HS_ERROR_NO_SETUP 0x3842 ///< Radio was not set up in a compatible mode
+#define HS_ERROR_NO_FS 0x3843 ///< Synth was not programmed when running Rx or Tx
+#define HS_ERROR_RXOVF 0x3844 ///< Rx overflow observed during operation
+#define HS_ERROR_TXUNF 0x3845 ///< Tx underflow observed during operation
+///@}
+///@}
+
+#endif
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ieee_cmd.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ieee_cmd.h
new file mode 100644
index 0000000..f33facd
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ieee_cmd.h
@@ -0,0 +1,628 @@
+/******************************************************************************
+* Filename: rf_ieee_cmd.h
+* Revised: 2018-01-15 06:15:14 +0100 (Mon, 15 Jan 2018)
+* Revision: 18170
+*
+* Description: CC13x2/CC26x2 API for IEEE 802.15.4 commands
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __IEEE_CMD_H
+#define __IEEE_CMD_H
+
+#ifndef __RFC_STRUCT
+#define __RFC_STRUCT
+#endif
+
+#ifndef __RFC_STRUCT_ATTR
+#if defined(__GNUC__)
+#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4)))
+#elif defined(__TI_ARM__)
+#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4)))
+#else
+#define __RFC_STRUCT_ATTR
+#endif
+#endif
+
+//! \addtogroup rfc
+//! @{
+
+//! \addtogroup ieee_cmd
+//! @{
+
+#include <stdint.h>
+#include "rf_mailbox.h"
+#include "rf_common_cmd.h"
+
+typedef struct __RFC_STRUCT rfc_CMD_IEEE_RX_s rfc_CMD_IEEE_RX_t;
+typedef struct __RFC_STRUCT rfc_CMD_IEEE_ED_SCAN_s rfc_CMD_IEEE_ED_SCAN_t;
+typedef struct __RFC_STRUCT rfc_CMD_IEEE_TX_s rfc_CMD_IEEE_TX_t;
+typedef struct __RFC_STRUCT rfc_CMD_IEEE_CSMA_s rfc_CMD_IEEE_CSMA_t;
+typedef struct __RFC_STRUCT rfc_CMD_IEEE_RX_ACK_s rfc_CMD_IEEE_RX_ACK_t;
+typedef struct __RFC_STRUCT rfc_CMD_IEEE_ABORT_BG_s rfc_CMD_IEEE_ABORT_BG_t;
+typedef struct __RFC_STRUCT rfc_CMD_IEEE_MOD_CCA_s rfc_CMD_IEEE_MOD_CCA_t;
+typedef struct __RFC_STRUCT rfc_CMD_IEEE_MOD_FILT_s rfc_CMD_IEEE_MOD_FILT_t;
+typedef struct __RFC_STRUCT rfc_CMD_IEEE_MOD_SRC_MATCH_s rfc_CMD_IEEE_MOD_SRC_MATCH_t;
+typedef struct __RFC_STRUCT rfc_CMD_IEEE_ABORT_FG_s rfc_CMD_IEEE_ABORT_FG_t;
+typedef struct __RFC_STRUCT rfc_CMD_IEEE_STOP_FG_s rfc_CMD_IEEE_STOP_FG_t;
+typedef struct __RFC_STRUCT rfc_CMD_IEEE_CCA_REQ_s rfc_CMD_IEEE_CCA_REQ_t;
+typedef struct __RFC_STRUCT rfc_ieeeRxOutput_s rfc_ieeeRxOutput_t;
+typedef struct __RFC_STRUCT rfc_shortAddrEntry_s rfc_shortAddrEntry_t;
+typedef struct __RFC_STRUCT rfc_ieeeRxCorrCrc_s rfc_ieeeRxCorrCrc_t;
+
+//! \addtogroup CMD_IEEE_RX
+//! @{
+#define CMD_IEEE_RX 0x2801
+//! IEEE 802.15.4 Receive Command
+struct __RFC_STRUCT rfc_CMD_IEEE_RX_s {
+ uint16_t commandNo; //!< The command ID number 0x2801
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint8_t channel; //!< \brief Channel to tune to in the start of the operation<br>
+ //!< 0: Use existing channel<br>
+ //!< 11--26: Use as IEEE 802.15.4 channel, i.e. frequency is (2405 + 5 × (channel - 11)) MHz<br>
+ //!< 60--207: Frequency is (2300 + channel) MHz<br>
+ //!< Others: <i>Reserved</i>
+ struct {
+ uint8_t bAutoFlushCrc:1; //!< If 1, automatically remove packets with CRC error from Rx queue
+ uint8_t bAutoFlushIgn:1; //!< If 1, automatically remove packets that can be ignored according to frame filtering from Rx queue
+ uint8_t bIncludePhyHdr:1; //!< If 1, include the received PHY header field in the stored packet; otherwise discard it
+ uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it
+ uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue
+ uint8_t bAppendCorrCrc:1; //!< If 1, append a correlation value and CRC result byte to the packet in the Rx queue
+ uint8_t bAppendSrcInd:1; //!< If 1, append an index from the source matching algorithm
+ uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue
+ } rxConfig;
+ dataQueue_t* pRxQ; //!< Pointer to receive queue
+ rfc_ieeeRxOutput_t *pOutput; //!< Pointer to output structure (NULL: Do not store results)
+ struct {
+ uint16_t frameFiltEn:1; //!< \brief 0: Disable frame filtering<br>
+ //!< 1: Enable frame filtering
+ uint16_t frameFiltStop:1; //!< \brief 0: Receive all packets to the end<br>
+ //!< 1: Stop receiving frame once frame filtering has caused the frame to be rejected.
+ uint16_t autoAckEn:1; //!< \brief 0: Disable auto ACK<br>
+ //!< 1: Enable auto ACK.
+ uint16_t slottedAckEn:1; //!< \brief 0: Non-slotted ACK<br>
+ //!< 1: Slotted ACK.
+ uint16_t autoPendEn:1; //!< \brief 0: Auto-pend disabled<br>
+ //!< 1: Auto-pend enabled
+ uint16_t defaultPend:1; //!< The value of the pending data bit in auto ACK packets that are not subject to auto-pend
+ uint16_t bPendDataReqOnly:1; //!< \brief 0: Use auto-pend for any packet<br>
+ //!< 1: Use auto-pend for data request packets only
+ uint16_t bPanCoord:1; //!< \brief 0: Device is not PAN coordinator<br>
+ //!< 1: Device is PAN coordinator
+ uint16_t maxFrameVersion:2; //!< Reject frames where the frame version field in the FCF is greater than this value
+ uint16_t fcfReservedMask:3; //!< Value to be AND-ed with the reserved part of the FCF; frame rejected if result is non-zero
+ uint16_t modifyFtFilter:2; //!< \brief Treatment of MSB of frame type field before frame-type filtering:<br>
+ //!< 0: No modification<br>
+ //!< 1: Invert MSB<br>
+ //!< 2: Set MSB to 0<br>
+ //!< 3: Set MSB to 1
+ uint16_t bStrictLenFilter:1; //!< \brief 0: Accept acknowledgement frames of any length >= 5<br>
+ //!< 1: Accept only acknowledgement frames of length 5
+ } frameFiltOpt; //!< Frame filtering options
+ struct {
+ uint8_t bAcceptFt0Beacon:1; //!< \brief Treatment of frames with frame type 000 (beacon):<br>
+ //!< 0: Reject<br>
+ //!< 1: Accept
+ uint8_t bAcceptFt1Data:1; //!< \brief Treatment of frames with frame type 001 (data):<br>
+ //!< 0: Reject<br>
+ //!< 1: Accept
+ uint8_t bAcceptFt2Ack:1; //!< \brief Treatment of frames with frame type 010 (ACK):<br>
+ //!< 0: Reject, unless running ACK receive command<br>
+ //!< 1: Always accept
+ uint8_t bAcceptFt3MacCmd:1; //!< \brief Treatment of frames with frame type 011 (MAC command):<br>
+ //!< 0: Reject<br>
+ //!< 1: Accept
+ uint8_t bAcceptFt4Reserved:1; //!< \brief Treatment of frames with frame type 100 (reserved):<br>
+ //!< 0: Reject<br>
+ //!< 1: Accept
+ uint8_t bAcceptFt5Reserved:1; //!< \brief Treatment of frames with frame type 101 (reserved):<br>
+ //!< 0: Reject<br>
+ //!< 1: Accept
+ uint8_t bAcceptFt6Reserved:1; //!< \brief Treatment of frames with frame type 110 (reserved):<br>
+ //!< 0: Reject<br>
+ //!< 1: Accept
+ uint8_t bAcceptFt7Reserved:1; //!< \brief Treatment of frames with frame type 111 (reserved):<br>
+ //!< 0: Reject<br>
+ //!< 1: Accept
+ } frameTypes; //!< Frame types to receive in frame filtering
+ struct {
+ uint8_t ccaEnEnergy:1; //!< Enable energy scan as CCA source
+ uint8_t ccaEnCorr:1; //!< Enable correlator based carrier sense as CCA source
+ uint8_t ccaEnSync:1; //!< Enable sync found based carrier sense as CCA source
+ uint8_t ccaCorrOp:1; //!< \brief Operator to use between energy based and correlator based CCA<br>
+ //!< 0: Report busy channel if either ccaEnergy or ccaCorr are busy<br>
+ //!< 1: Report busy channel if both ccaEnergy and ccaCorr are busy
+ uint8_t ccaSyncOp:1; //!< \brief Operator to use between sync found based CCA and the others<br>
+ //!< 0: Always report busy channel if ccaSync is busy<br>
+ //!< 1: Always report idle channel if ccaSync is idle
+ uint8_t ccaCorrThr:2; //!< Threshold for number of correlation peaks in correlator based carrier sense
+ } ccaOpt; //!< CCA options
+ int8_t ccaRssiThr; //!< RSSI threshold for CCA
+ uint8_t __dummy0;
+ uint8_t numExtEntries; //!< Number of extended address entries
+ uint8_t numShortEntries; //!< Number of short address entries
+ uint32_t* pExtEntryList; //!< Pointer to list of extended address entries
+ uint32_t* pShortEntryList; //!< Pointer to list of short address entries
+ uint64_t localExtAddr; //!< The extended address of the local device
+ uint16_t localShortAddr; //!< The short address of the local device
+ uint16_t localPanID; //!< The PAN ID of the local device
+ uint16_t __dummy1;
+ uint8_t __dummy2;
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } endTrigger; //!< Trigger that causes the device to end the Rx operation
+ ratmr_t endTime; //!< \brief Time used together with <code>endTrigger</code> that causes the device to end the Rx
+ //!< operation
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_IEEE_ED_SCAN
+//! @{
+#define CMD_IEEE_ED_SCAN 0x2802
+//! IEEE 802.15.4 Energy Detect Scan Command
+struct __RFC_STRUCT rfc_CMD_IEEE_ED_SCAN_s {
+ uint16_t commandNo; //!< The command ID number 0x2802
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint8_t channel; //!< \brief Channel to tune to in the start of the operation<br>
+ //!< 0: Use existing channel<br>
+ //!< 11--26: Use as IEEE 802.15.4 channel, i.e. frequency is (2405 + 5 × (channel - 11)) MHz<br>
+ //!< 60--207: Frequency is (2300 + channel) MHz<br>
+ //!< Others: <i>Reserved</i>
+ struct {
+ uint8_t ccaEnEnergy:1; //!< Enable energy scan as CCA source
+ uint8_t ccaEnCorr:1; //!< Enable correlator based carrier sense as CCA source
+ uint8_t ccaEnSync:1; //!< Enable sync found based carrier sense as CCA source
+ uint8_t ccaCorrOp:1; //!< \brief Operator to use between energy based and correlator based CCA<br>
+ //!< 0: Report busy channel if either ccaEnergy or ccaCorr are busy<br>
+ //!< 1: Report busy channel if both ccaEnergy and ccaCorr are busy
+ uint8_t ccaSyncOp:1; //!< \brief Operator to use between sync found based CCA and the others<br>
+ //!< 0: Always report busy channel if ccaSync is busy<br>
+ //!< 1: Always report idle channel if ccaSync is idle
+ uint8_t ccaCorrThr:2; //!< Threshold for number of correlation peaks in correlator based carrier sense
+ } ccaOpt; //!< CCA options
+ int8_t ccaRssiThr; //!< RSSI threshold for CCA
+ uint8_t __dummy0;
+ int8_t maxRssi; //!< The maximum RSSI recorded during the ED scan
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } endTrigger; //!< Trigger that causes the device to end the Rx operation
+ ratmr_t endTime; //!< \brief Time used together with <code>endTrigger</code> that causes the device to end the Rx
+ //!< operation
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_IEEE_TX
+//! @{
+#define CMD_IEEE_TX 0x2C01
+//! IEEE 802.15.4 Transmit Command
+struct __RFC_STRUCT rfc_CMD_IEEE_TX_s {
+ uint16_t commandNo; //!< The command ID number 0x2C01
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ struct {
+ uint8_t bIncludePhyHdr:1; //!< \brief 0: Find PHY header automatically<br>
+ //!< 1: Insert PHY header from the buffer
+ uint8_t bIncludeCrc:1; //!< \brief 0: Append automatically calculated CRC<br>
+ //!< 1: Insert FCS (CRC) from the buffer
+ uint8_t :1;
+ uint8_t payloadLenMsb:5; //!< \brief Most significant bits of payload length. Should only be non-zero to create long
+ //!< non-standard packets for test purposes
+ } txOpt;
+ uint8_t payloadLen; //!< Number of bytes in the payload
+ uint8_t* pPayload; //!< Pointer to payload buffer of size <code>payloadLen</code>
+ ratmr_t timeStamp; //!< Time stamp of transmitted frame
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_IEEE_CSMA
+//! @{
+#define CMD_IEEE_CSMA 0x2C02
+//! IEEE 802.15.4 CSMA-CA Command
+struct __RFC_STRUCT rfc_CMD_IEEE_CSMA_s {
+ uint16_t commandNo; //!< The command ID number 0x2C02
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint16_t randomState; //!< The state of the pseudo-random generator
+ uint8_t macMaxBE; //!< The IEEE 802.15.4 MAC parameter <i>macMaxBE</i>
+ uint8_t macMaxCSMABackoffs; //!< The IEEE 802.15.4 MAC parameter <i>macMaxCSMABackoffs</i>
+ struct {
+ uint8_t initCW:5; //!< The initialization value for the CW parameter
+ uint8_t bSlotted:1; //!< \brief 0: non-slotted CSMA<br>
+ //!< 1: slotted CSMA
+ uint8_t rxOffMode:2; //!< \brief 0: RX stays on during CSMA backoffs<br>
+ //!< 1: The CSMA-CA algorithm will suspend the receiver if no frame is being received<br>
+ //!< 2: The CSMA-CA algorithm will suspend the receiver if no frame is being received,
+ //!< or after finishing it (including auto ACK) otherwise<br>
+ //!< 3: The CSMA-CA algorithm will suspend the receiver immediately during back-offs
+ } csmaConfig;
+ uint8_t NB; //!< The NB parameter from the IEEE 802.15.4 CSMA-CA algorithm
+ uint8_t BE; //!< The BE parameter from the IEEE 802.15.4 CSMA-CA algorithm
+ uint8_t remainingPeriods; //!< The number of remaining periods from a paused backoff countdown
+ int8_t lastRssi; //!< RSSI measured at the last CCA operation
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } endTrigger; //!< Trigger that causes the device to end the CSMA-CA operation
+ ratmr_t lastTimeStamp; //!< Time of the last CCA operation
+ ratmr_t endTime; //!< \brief Time used together with <code>endTrigger</code> that causes the device to end the
+ //!< CSMA-CA operation
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_IEEE_RX_ACK
+//! @{
+#define CMD_IEEE_RX_ACK 0x2C03
+//! IEEE 802.15.4 Receive Acknowledgement Command
+struct __RFC_STRUCT rfc_CMD_IEEE_RX_ACK_s {
+ uint16_t commandNo; //!< The command ID number 0x2C03
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ uint8_t seqNo; //!< Sequence number to expect
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } endTrigger; //!< Trigger that causes the device to give up acknowledgement reception
+ ratmr_t endTime; //!< \brief Time used together with <code>endTrigger</code> that causes the device to give up
+ //!< acknowledgement reception
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_IEEE_ABORT_BG
+//! @{
+#define CMD_IEEE_ABORT_BG 0x2C04
+//! IEEE 802.15.4 Abort Background Level Command
+struct __RFC_STRUCT rfc_CMD_IEEE_ABORT_BG_s {
+ uint16_t commandNo; //!< The command ID number 0x2C04
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_IEEE_MOD_CCA
+//! @{
+#define CMD_IEEE_MOD_CCA 0x2001
+//! IEEE 802.15.4 Modify CCA Parameter Command
+struct __RFC_STRUCT rfc_CMD_IEEE_MOD_CCA_s {
+ uint16_t commandNo; //!< The command ID number 0x2001
+ struct {
+ uint8_t ccaEnEnergy:1; //!< Enable energy scan as CCA source
+ uint8_t ccaEnCorr:1; //!< Enable correlator based carrier sense as CCA source
+ uint8_t ccaEnSync:1; //!< Enable sync found based carrier sense as CCA source
+ uint8_t ccaCorrOp:1; //!< \brief Operator to use between energy based and correlator based CCA<br>
+ //!< 0: Report busy channel if either ccaEnergy or ccaCorr are busy<br>
+ //!< 1: Report busy channel if both ccaEnergy and ccaCorr are busy
+ uint8_t ccaSyncOp:1; //!< \brief Operator to use between sync found based CCA and the others<br>
+ //!< 0: Always report busy channel if ccaSync is busy<br>
+ //!< 1: Always report idle channel if ccaSync is idle
+ uint8_t ccaCorrThr:2; //!< Threshold for number of correlation peaks in correlator based carrier sense
+ } newCcaOpt; //!< New value of <code>ccaOpt</code> for the running background level operation
+ int8_t newCcaRssiThr; //!< New value of <code>ccaRssiThr</code> for the running background level operation
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_IEEE_MOD_FILT
+//! @{
+#define CMD_IEEE_MOD_FILT 0x2002
+//! IEEE 802.15.4 Modify Frame Filtering Parameter Command
+struct __RFC_STRUCT rfc_CMD_IEEE_MOD_FILT_s {
+ uint16_t commandNo; //!< The command ID number 0x2002
+ struct {
+ uint16_t frameFiltEn:1; //!< \brief 0: Disable frame filtering<br>
+ //!< 1: Enable frame filtering
+ uint16_t frameFiltStop:1; //!< \brief 0: Receive all packets to the end<br>
+ //!< 1: Stop receiving frame once frame filtering has caused the frame to be rejected.
+ uint16_t autoAckEn:1; //!< \brief 0: Disable auto ACK<br>
+ //!< 1: Enable auto ACK.
+ uint16_t slottedAckEn:1; //!< \brief 0: Non-slotted ACK<br>
+ //!< 1: Slotted ACK.
+ uint16_t autoPendEn:1; //!< \brief 0: Auto-pend disabled<br>
+ //!< 1: Auto-pend enabled
+ uint16_t defaultPend:1; //!< The value of the pending data bit in auto ACK packets that are not subject to auto-pend
+ uint16_t bPendDataReqOnly:1; //!< \brief 0: Use auto-pend for any packet<br>
+ //!< 1: Use auto-pend for data request packets only
+ uint16_t bPanCoord:1; //!< \brief 0: Device is not PAN coordinator<br>
+ //!< 1: Device is PAN coordinator
+ uint16_t maxFrameVersion:2; //!< Reject frames where the frame version field in the FCF is greater than this value
+ uint16_t fcfReservedMask:3; //!< Value to be AND-ed with the reserved part of the FCF; frame rejected if result is non-zero
+ uint16_t modifyFtFilter:2; //!< \brief Treatment of MSB of frame type field before frame-type filtering:<br>
+ //!< 0: No modification<br>
+ //!< 1: Invert MSB<br>
+ //!< 2: Set MSB to 0<br>
+ //!< 3: Set MSB to 1
+ uint16_t bStrictLenFilter:1; //!< \brief 0: Accept acknowledgement frames of any length >= 5<br>
+ //!< 1: Accept only acknowledgement frames of length 5
+ } newFrameFiltOpt; //!< New value of <code>frameFiltOpt</code> for the running background level operation
+ struct {
+ uint8_t bAcceptFt0Beacon:1; //!< \brief Treatment of frames with frame type 000 (beacon):<br>
+ //!< 0: Reject<br>
+ //!< 1: Accept
+ uint8_t bAcceptFt1Data:1; //!< \brief Treatment of frames with frame type 001 (data):<br>
+ //!< 0: Reject<br>
+ //!< 1: Accept
+ uint8_t bAcceptFt2Ack:1; //!< \brief Treatment of frames with frame type 010 (ACK):<br>
+ //!< 0: Reject, unless running ACK receive command<br>
+ //!< 1: Always accept
+ uint8_t bAcceptFt3MacCmd:1; //!< \brief Treatment of frames with frame type 011 (MAC command):<br>
+ //!< 0: Reject<br>
+ //!< 1: Accept
+ uint8_t bAcceptFt4Reserved:1; //!< \brief Treatment of frames with frame type 100 (reserved):<br>
+ //!< 0: Reject<br>
+ //!< 1: Accept
+ uint8_t bAcceptFt5Reserved:1; //!< \brief Treatment of frames with frame type 101 (reserved):<br>
+ //!< 0: Reject<br>
+ //!< 1: Accept
+ uint8_t bAcceptFt6Reserved:1; //!< \brief Treatment of frames with frame type 110 (reserved):<br>
+ //!< 0: Reject<br>
+ //!< 1: Accept
+ uint8_t bAcceptFt7Reserved:1; //!< \brief Treatment of frames with frame type 111 (reserved):<br>
+ //!< 0: Reject<br>
+ //!< 1: Accept
+ } newFrameTypes; //!< New value of <code>frameTypes</code> for the running background level operation
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_IEEE_MOD_SRC_MATCH
+//! @{
+#define CMD_IEEE_MOD_SRC_MATCH 0x2003
+//! IEEE 802.15.4 Enable/Disable Source Matching Entry Command
+struct __RFC_STRUCT rfc_CMD_IEEE_MOD_SRC_MATCH_s {
+ uint16_t commandNo; //!< The command ID number 0x2003
+ struct {
+ uint8_t bEnable:1; //!< \brief 0: Disable entry<br>
+ //!< 1: Enable entry
+ uint8_t srcPend:1; //!< New value of the pending bit for the entry
+ uint8_t entryType:1; //!< \brief 0: Short address<br>
+ //!< 1: Extended address
+ } options;
+ uint8_t entryNo; //!< Index of entry to enable or disable
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_IEEE_ABORT_FG
+//! @{
+#define CMD_IEEE_ABORT_FG 0x2401
+//! IEEE 802.15.4 Abort Foreground Level Command
+struct __RFC_STRUCT rfc_CMD_IEEE_ABORT_FG_s {
+ uint16_t commandNo; //!< The command ID number 0x2401
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_IEEE_STOP_FG
+//! @{
+#define CMD_IEEE_STOP_FG 0x2402
+//! IEEE 802.15.4 Gracefully Stop Foreground Level Command
+struct __RFC_STRUCT rfc_CMD_IEEE_STOP_FG_s {
+ uint16_t commandNo; //!< The command ID number 0x2402
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_IEEE_CCA_REQ
+//! @{
+#define CMD_IEEE_CCA_REQ 0x2403
+//! IEEE 802.15.4 CCA and RSSI Information Request Command
+struct __RFC_STRUCT rfc_CMD_IEEE_CCA_REQ_s {
+ uint16_t commandNo; //!< The command ID number 0x2403
+ int8_t currentRssi; //!< The RSSI currently observed on the channel
+ int8_t maxRssi; //!< The maximum RSSI observed on the channel since Rx was started
+ struct {
+ uint8_t ccaState:2; //!< \brief Value of the current CCA state<br>
+ //!< 0: Idle<br>
+ //!< 1: Busy<br>
+ //!< 2: Invalid
+ uint8_t ccaEnergy:2; //!< \brief Value of the current energy detect CCA state<br>
+ //!< 0: Idle<br>
+ //!< 1: Busy<br>
+ //!< 2: Invalid
+ uint8_t ccaCorr:2; //!< \brief Value of the current correlator based carrier sense CCA state<br>
+ //!< 0: Idle<br>
+ //!< 1: Busy<br>
+ //!< 2: Invalid
+ uint8_t ccaSync:1; //!< \brief Value of the current sync found based carrier sense CCA state<br>
+ //!< 0: Idle<br>
+ //!< 1: Busy
+ } ccaInfo;
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup ieeeRxOutput
+//! @{
+//! Output structure for CMD_IEEE_RX
+
+struct __RFC_STRUCT rfc_ieeeRxOutput_s {
+ uint8_t nTxAck; //!< Total number of transmitted ACK frames
+ uint8_t nRxBeacon; //!< Number of received beacon frames
+ uint8_t nRxData; //!< Number of received data frames
+ uint8_t nRxAck; //!< Number of received acknowledgement frames
+ uint8_t nRxMacCmd; //!< Number of received MAC command frames
+ uint8_t nRxReserved; //!< Number of received frames with reserved frame type
+ uint8_t nRxNok; //!< Number of received frames with CRC error
+ uint8_t nRxIgnored; //!< Number of frames received that are to be ignored
+ uint8_t nRxBufFull; //!< Number of received frames discarded because the Rx buffer was full
+ int8_t lastRssi; //!< RSSI of last received frame
+ int8_t maxRssi; //!< Highest RSSI observed in the operation
+ uint8_t __dummy0;
+ ratmr_t beaconTimeStamp; //!< Time stamp of last received beacon frame
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup shortAddrEntry
+//! @{
+//! Structure for short address entries
+
+struct __RFC_STRUCT rfc_shortAddrEntry_s {
+ uint16_t shortAddr; //!< Short address
+ uint16_t panId; //!< PAN ID
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup ieeeRxCorrCrc
+//! @{
+//! Receive status byte that may be appended to message in receive buffer
+
+struct __RFC_STRUCT rfc_ieeeRxCorrCrc_s {
+ struct {
+ uint8_t corr:6; //!< The correlation value
+ uint8_t bIgnore:1; //!< 1 if the packet should be rejected by frame filtering, 0 otherwise
+ uint8_t bCrcErr:1; //!< 1 if the packet was received with CRC error, 0 otherwise
+ } status;
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! @}
+//! @}
+#endif
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ieee_mailbox.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ieee_mailbox.h
new file mode 100644
index 0000000..a9fc221
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ieee_mailbox.h
@@ -0,0 +1,73 @@
+/******************************************************************************
+* Filename: rf_ieee_mailbox.h
+* Revised: 2018-01-23 19:51:42 +0100 (Tue, 23 Jan 2018)
+* Revision: 18189
+*
+* Description: Definitions for IEEE 802.15.4 interface
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef _IEEE_MAILBOX_H
+#define _IEEE_MAILBOX_H
+
+#include "rf_mailbox.h"
+
+/// \name Radio operation status
+///@{
+/// \name Operation not finished
+///@{
+#define IEEE_SUSPENDED 0x2001 ///< Operation suspended
+///@}
+/// \name Operation finished normally
+///@{
+#define IEEE_DONE_OK 0x2400 ///< Operation ended normally
+#define IEEE_DONE_BUSY 0x2401 ///< CSMA-CA operation ended with failure
+#define IEEE_DONE_STOPPED 0x2402 ///< Operation stopped after stop command
+#define IEEE_DONE_ACK 0x2403 ///< ACK packet received with pending data bit cleared
+#define IEEE_DONE_ACKPEND 0x2404 ///< ACK packet received with pending data bit set
+#define IEEE_DONE_TIMEOUT 0x2405 ///< Operation ended due to timeout
+#define IEEE_DONE_BGEND 0x2406 ///< FG operation ended because necessary background level
+ ///< operation ended
+#define IEEE_DONE_ABORT 0x2407 ///< Operation aborted by command
+///@}
+/// \name Operation finished with error
+///@{
+#define IEEE_ERROR_PAR 0x2800 ///< Illegal parameter
+#define IEEE_ERROR_NO_SETUP 0x2801 ///< Operation using Rx or Tx attempted when not in 15.4 mode
+#define IEEE_ERROR_NO_FS 0x2802 ///< Operation using Rx or Tx attempted without frequency synth configured
+#define IEEE_ERROR_SYNTH_PROG 0x2803 ///< Synthesizer programming failed to complete on time
+#define IEEE_ERROR_RXOVF 0x2804 ///< Receiver overflowed during operation
+#define IEEE_ERROR_TXUNF 0x2805 ///< Transmitter underflowed during operation
+///@}
+///@}
+
+#endif
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_mailbox.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_mailbox.h
new file mode 100644
index 0000000..a23d71a
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_mailbox.h
@@ -0,0 +1,364 @@
+/******************************************************************************
+* Filename: rf_mailbox.h
+* Revised: 2018-11-02 11:52:02 +0100 (Fri, 02 Nov 2018)
+* Revision: 18756
+*
+* Description: Definitions for interface between system and radio CPU
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef _MAILBOX_H
+#define _MAILBOX_H
+
+#include <stdint.h>
+#include <string.h>
+
+
+/// \name RF mode values
+/// Defines used to indicate mode of operation to radio core.
+///@{
+#define RF_MODE_AUTO 0x00
+#define RF_MODE_BLE 0x00
+#define RF_MODE_IEEE_15_4 0x00
+#define RF_MODE_PROPRIETARY_2_4 0x00
+#define RF_MODE_PROPRIETARY RF_MODE_PROPRIETARY_2_4
+#define RF_MODE_MULTIPLE 0x00
+///@}
+
+
+/// Type definition for RAT
+typedef uint32_t ratmr_t;
+
+
+
+/// Type definition for a data queue
+typedef struct {
+ uint8_t *pCurrEntry; ///< Pointer to the data queue entry to be used, NULL for an empty queue
+ uint8_t *pLastEntry; ///< Pointer to the last entry in the queue, NULL for a circular queue
+} dataQueue_t;
+
+
+
+/// \name CPE interrupt definitions
+/// Interrupt masks for the CPE interrupt in RDBELL.
+///@{
+#define IRQN_COMMAND_DONE 0 ///< Radio operation command finished
+#define IRQN_LAST_COMMAND_DONE 1 ///< Last radio operation command in a chain finished
+#define IRQN_FG_COMMAND_DONE 2 ///< FG level Radio operation command finished
+#define IRQN_LAST_FG_COMMAND_DONE 3 ///< Last FG level radio operation command in a chain finished
+#define IRQN_TX_DONE 4 ///< Packet transmitted
+#define IRQN_TX_ACK 5 ///< ACK packet transmitted
+#define IRQN_TX_CTRL 6 ///< Control packet transmitted
+#define IRQN_TX_CTRL_ACK 7 ///< Acknowledgement received on a transmitted control packet
+#define IRQN_TX_CTRL_ACK_ACK 8 ///< Acknowledgement received on a transmitted control packet, and acknowledgement transmitted for that packet
+#define IRQN_TX_RETRANS 9 ///< Packet retransmitted
+#define IRQN_TX_ENTRY_DONE 10 ///< Tx queue data entry state changed to Finished
+#define IRQN_TX_BUFFER_CHANGED 11 ///< A buffer change is complete
+#define IRQN_COMMAND_STARTED 12 ///< A radio operation command has gone into active state
+#define IRQN_FG_COMMAND_STARTED 13 ///< FG level radio operation command has gone into active state
+#define IRQN_PA_CHANGED 14 ///< PA is changed
+#define IRQN_RX_OK 16 ///< Packet received with CRC OK, payload, and not to be ignored
+#define IRQN_RX_NOK 17 ///< Packet received with CRC error
+#define IRQN_RX_IGNORED 18 ///< Packet received with CRC OK, but to be ignored
+#define IRQN_RX_EMPTY 19 ///< Packet received with CRC OK, not to be ignored, no payload
+#define IRQN_RX_CTRL 20 ///< Control packet received with CRC OK, not to be ignored
+#define IRQN_RX_CTRL_ACK 21 ///< Control packet received with CRC OK, not to be ignored, then ACK sent
+#define IRQN_RX_BUF_FULL 22 ///< Packet received that did not fit in the Rx queue
+#define IRQN_RX_ENTRY_DONE 23 ///< Rx queue data entry changing state to Finished
+#define IRQN_RX_DATA_WRITTEN 24 ///< Data written to partial read Rx buffer
+#define IRQN_RX_N_DATA_WRITTEN 25 ///< Specified number of bytes written to partial read Rx buffer
+#define IRQN_RX_ABORTED 26 ///< Packet reception stopped before packet was done
+#define IRQN_RX_COLLISION_DETECTED 27 ///< A collision was indicated during packet reception
+#define IRQN_SYNTH_NO_LOCK 28 ///< The synth has gone out of lock after calibration
+#define IRQN_MODULES_UNLOCKED 29 ///< As part of the boot process, the CM0 has opened access to RF core modules and memories
+#define IRQN_BOOT_DONE 30 ///< The RF core CPU boot is finished
+
+#define IRQN_INTERNAL_ERROR 31 ///< Internal error observed
+
+#define IRQ_COMMAND_DONE (1U << IRQN_COMMAND_DONE)
+#define IRQ_LAST_COMMAND_DONE (1U << IRQN_LAST_COMMAND_DONE)
+#define IRQ_FG_COMMAND_DONE (1U << IRQN_FG_COMMAND_DONE)
+#define IRQ_LAST_FG_COMMAND_DONE (1U << IRQN_LAST_FG_COMMAND_DONE)
+
+#define IRQ_TX_DONE (1U << IRQN_TX_DONE)
+#define IRQ_TX_ACK (1U << IRQN_TX_ACK)
+#define IRQ_TX_CTRL (1U << IRQN_TX_CTRL)
+#define IRQ_TX_CTRL_ACK (1U << IRQN_TX_CTRL_ACK)
+#define IRQ_TX_CTRL_ACK_ACK (1U << IRQN_TX_CTRL_ACK_ACK)
+#define IRQ_TX_RETRANS (1U << IRQN_TX_RETRANS)
+
+#define IRQ_TX_ENTRY_DONE (1U << IRQN_TX_ENTRY_DONE)
+#define IRQ_TX_BUFFER_CHANGED (1U << IRQN_TX_BUFFER_CHANGED)
+
+#define IRQ_COMMAND_STARTED (1U << IRQN_COMMAND_STARTED)
+#define IRQ_FG_COMMAND_STARTED (1U << IRQN_FG_COMMAND_STARTED)
+#define IRQ_PA_CHANGED (1U << IRQN_PA_CHANGED)
+
+#define IRQ_RX_OK (1U << IRQN_RX_OK)
+#define IRQ_RX_NOK (1U << IRQN_RX_NOK)
+#define IRQ_RX_IGNORED (1U << IRQN_RX_IGNORED)
+#define IRQ_RX_EMPTY (1U << IRQN_RX_EMPTY)
+#define IRQ_RX_CTRL (1U << IRQN_RX_CTRL)
+#define IRQ_RX_CTRL_ACK (1U << IRQN_RX_CTRL_ACK)
+#define IRQ_RX_BUF_FULL (1U << IRQN_RX_BUF_FULL)
+#define IRQ_RX_ENTRY_DONE (1U << IRQN_RX_ENTRY_DONE)
+#define IRQ_RX_DATA_WRITTEN (1U << IRQN_RX_DATA_WRITTEN)
+#define IRQ_RX_N_DATA_WRITTEN (1U << IRQN_RX_N_DATA_WRITTEN)
+#define IRQ_RX_ABORTED (1U << IRQN_RX_ABORTED)
+#define IRQ_RX_COLLISION_DETECTED (1U << IRQN_RX_COLLISION_DETECTED)
+#define IRQ_SYNTH_NO_LOCK (1U << IRQN_SYNTH_NO_LOCK)
+#define IRQ_MODULES_UNLOCKED (1U << IRQN_MODULES_UNLOCKED)
+#define IRQ_BOOT_DONE (1U << IRQN_BOOT_DONE)
+#define IRQ_INTERNAL_ERROR (1U << IRQN_INTERNAL_ERROR)
+///@}
+
+
+
+/// \name CMDSTA values
+/// Values returned in result byte of CMDSTA
+///@{
+#define CMDSTA_Pending 0x00 ///< The command has not yet been parsed
+#define CMDSTA_Done 0x01 ///< Command successfully parsed
+
+#define CMDSTA_IllegalPointer 0x81 ///< The pointer signaled in CMDR is not valid
+#define CMDSTA_UnknownCommand 0x82 ///< The command number in the command structure is unknown
+#define CMDSTA_UnknownDirCommand 0x83 ///< The command number for a direct command is unknown, or the
+ ///< command is not a direct command
+#define CMDSTA_ContextError 0x85 ///< An immediate or direct command was issued in a context
+ ///< where it is not supported
+#define CMDSTA_SchedulingError 0x86 ///< A radio operation command was attempted to be scheduled
+ ///< while another operation was already running in the RF core
+#define CMDSTA_ParError 0x87 ///< There were errors in the command parameters that are parsed
+ ///< on submission.
+#define CMDSTA_QueueError 0x88 ///< An operation on a data entry queue was attempted that was
+ ///< not supported by the queue in its current state
+#define CMDSTA_QueueBusy 0x89 ///< An operation on a data entry was attempted while that entry
+ ///< was busy
+///@}
+
+
+
+/// \name Macros for sending direct commands
+///@{
+/// Direct command with no parameter
+#define CMDR_DIR_CMD(cmdId) (((cmdId) << 16) | 1)
+
+/// Direct command with 1-byte parameter
+#define CMDR_DIR_CMD_1BYTE(cmdId, par) (((cmdId) << 16) | ((par) << 8) | 1)
+
+/// Direct command with 2-byte parameter
+#define CMDR_DIR_CMD_2BYTE(cmdId, par) (((cmdId) << 16) | ((par) & 0xFFFC) | 1)
+
+///@}
+
+
+
+/// \name Definitions for trigger types
+///@{
+#define TRIG_NOW 0 ///< Triggers immediately
+#define TRIG_NEVER 1 ///< Never trigs
+#define TRIG_ABSTIME 2 ///< Trigs at an absolute time
+#define TRIG_REL_SUBMIT 3 ///< Trigs at a time relative to the command was submitted
+#define TRIG_REL_START 4 ///< Trigs at a time relative to the command started
+#define TRIG_REL_PREVSTART 5 ///< Trigs at a time relative to the previous command in the chain started
+#define TRIG_REL_FIRSTSTART 6 ///< Trigs at a time relative to the first command in the chain started
+#define TRIG_REL_PREVEND 7 ///< Trigs at a time relative to the previous command in the chain ended
+#define TRIG_REL_EVT1 8 ///< Trigs at a time relative to the context defined "Event 1"
+#define TRIG_REL_EVT2 9 ///< Trigs at a time relative to the context defined "Event 2"
+#define TRIG_EXTERNAL 10 ///< Trigs at an external event to the radio timer
+#define TRIG_PAST_BM 0x80 ///< Bitmask for setting pastTrig bit in order to trig immediately if
+ ///< trigger happened in the past
+///@}
+
+
+/// \name Definitions for conditional execution
+///@{
+#define COND_ALWAYS 0 ///< Always run next command (except in case of Abort)
+#define COND_NEVER 1 ///< Never run next command
+#define COND_STOP_ON_FALSE 2 ///< Run next command if this command returned True, stop if it returned
+ ///< False
+#define COND_STOP_ON_TRUE 3 ///< Stop if this command returned True, run next command if it returned
+ ///< False
+#define COND_SKIP_ON_FALSE 4 ///< Run next command if this command returned True, skip a number of
+ ///< commands if it returned False
+#define COND_SKIP_ON_TRUE 5 ///< Skip a number of commands if this command returned True, run next
+ ///< command if it returned False
+///@}
+
+
+
+/// \name Radio operation status
+///@{
+/// \name Operation not finished
+///@{
+#define IDLE 0x0000 ///< Operation not started
+#define PENDING 0x0001 ///< Start of command is pending
+#define ACTIVE 0x0002 ///< Running
+#define SKIPPED 0x0003 ///< Operation skipped due to condition in another command
+///@}
+/// \name Operation finished normally
+///@{
+#define DONE_OK 0x0400 ///< Operation ended normally
+#define DONE_COUNTDOWN 0x0401 ///< Counter reached zero
+#define DONE_RXERR 0x0402 ///< Operation ended with CRC error
+#define DONE_TIMEOUT 0x0403 ///< Operation ended with timeout
+#define DONE_STOPPED 0x0404 ///< Operation stopped after CMD_STOP command
+#define DONE_ABORT 0x0405 ///< Operation aborted by CMD_ABORT command
+#define DONE_FAILED 0x0406 ///< Scheduled immediate command failed
+///@}
+/// \name Operation finished with error
+///@{
+#define ERROR_PAST_START 0x0800 ///< The start trigger occurred in the past
+#define ERROR_START_TRIG 0x0801 ///< Illegal start trigger parameter
+#define ERROR_CONDITION 0x0802 ///< Illegal condition for next operation
+#define ERROR_PAR 0x0803 ///< Error in a command specific parameter
+#define ERROR_POINTER 0x0804 ///< Invalid pointer to next operation
+#define ERROR_CMDID 0x0805 ///< Next operation has a command ID that is undefined or not a radio
+ ///< operation command
+#define ERROR_WRONG_BG 0x0806 ///< FG level command not compatible with running BG level command
+#define ERROR_NO_SETUP 0x0807 ///< Operation using Rx or Tx attempted without CMD_RADIO_SETUP
+#define ERROR_NO_FS 0x0808 ///< Operation using Rx or Tx attempted without frequency synth configured
+#define ERROR_SYNTH_PROG 0x0809 ///< Synthesizer calibration failed
+#define ERROR_TXUNF 0x080A ///< Tx underflow observed
+#define ERROR_RXOVF 0x080B ///< Rx overflow observed
+#define ERROR_NO_RX 0x080C ///< Attempted to access data from Rx when no such data was yet received
+#define ERROR_PENDING 0x080D ///< Command submitted in the future with another command at different level pending
+///@}
+///@}
+
+
+/// \name Data entry types
+///@{
+#define DATA_ENTRY_TYPE_GEN 0 ///< General type: Tx entry or single element Rx entry
+#define DATA_ENTRY_TYPE_MULTI 1 ///< Multi-element Rx entry type
+#define DATA_ENTRY_TYPE_PTR 2 ///< Pointer entry type
+#define DATA_ENTRY_TYPE_PARTIAL 3 ///< Partial read entry type
+///@
+
+
+/// \name Data entry statuses
+///@{
+#define DATA_ENTRY_PENDING 0 ///< Entry not yet used
+#define DATA_ENTRY_ACTIVE 1 ///< Entry in use by radio CPU
+#define DATA_ENTRY_BUSY 2 ///< Entry being updated
+#define DATA_ENTRY_FINISHED 3 ///< Radio CPU is finished accessing the entry
+#define DATA_ENTRY_UNFINISHED 4 ///< Radio CPU is finished accessing the entry, but packet could not be finished
+///@}
+
+
+/// \name Macros for RF register override
+///@{
+/// Macro for ADI half-size value-mask combination
+#define ADI_VAL_MASK(addr, mask, value) \
+(((addr) & 1) ? (((mask) & 0x0F) | (((value) & 0x0F) << 4)) : \
+ ((((mask) & 0x0F) << 4) | ((value) & 0x0F)))
+/// 32-bit write of 16-bit value
+#define HW_REG_OVERRIDE(addr, val) ((((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(val) << 16))
+/// ADI register, full-size write
+#define ADI_REG_OVERRIDE(adiNo, addr, val) (2 | ((uint32_t)(val) << 16) | \
+(((addr) & 0x3F) << 24) | (((adiNo) ? 1U : 0) << 31))
+/// 2 ADI registers, full-size write
+#define ADI_2REG_OVERRIDE(adiNo, addr, val, addr2, val2) \
+(2 | ((uint32_t)(val2) << 2) | (((addr2) & 0x3F) << 10) | ((uint32_t)(val) << 16) | \
+(((addr) & 0x3F) << 24) | (((adiNo) ? 1U : 0) << 31))
+/// ADI register, half-size read-modify-write
+#define ADI_HALFREG_OVERRIDE(adiNo, addr, mask, val) (2 | (ADI_VAL_MASK(addr, mask, val) << 16) | \
+(((addr) & 0x3F) << 24) | (1U << 30) | (((adiNo) ? 1U : 0) << 31))
+/// 2 ADI registers, half-size read-modify-write
+#define ADI_2HALFREG_OVERRIDE(adiNo, addr, mask, val, addr2, mask2, val2) \
+(2 | (ADI_VAL_MASK(addr2, mask2, val2) << 2) | (((addr2) & 0x3F) << 10) | \
+(ADI_VAL_MASK(addr, mask, val) << 16) | (((addr) & 0x3F) << 24) | (1U << 30) | (((adiNo) ? 1U : 0) << 31))
+
+/// 16-bit SW register as defined in radio_par_def.txt
+#define SW_REG_OVERRIDE(cmd, field, val) (3 | ((_POSITION_##cmd##_##field) << 4) | ((uint32_t)(val) << 16))
+/// SW register as defined in radio_par_def.txt with added index (for use with registers > 16 bits).
+#define SW_REG_IND_OVERRIDE(cmd, field, offset, val) (3 | \
+(((_POSITION_##cmd##_##field) + ((offset) << 1)) << 4) | ((uint32_t)(val) << 16))
+/// 8-bit SW register as defined in radio_par_def.txt
+#define SW_REG_BYTE_OVERRIDE(cmd, field, val) (0x8003 | ((_POSITION_##cmd##_##field) << 4) | \
+(((uint32_t)(val) & 0xFF) << 16))
+/// Two 8-bit SW registers as defined in radio_par_def.txt; the one given by field and the next byte.
+#define SW_REG_2BYTE_OVERRIDE(cmd, field, val0, val1) (3 | (((_POSITION_##cmd##_##field) & 0xFFFE) << 4) | \
+ (((uint32_t)(val0) << 16) & 0x00FF0000) | ((uint32_t)(val1) << 24))
+#define SW_REG_MASK_OVERRIDE(cmd, field, offset, mask, val) (0x8003 | \
+((_POSITION_##cmd##_##field + (offset)) << 4) | (((uint32_t)(val) & 0xFF) << 16) | (((uint32_t)(mask) & 0xFF) << 24))
+
+#define HW16_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(length) << 16))
+#define HW32_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t) (addr)) & 0xFFFC) | \
+((uint32_t)(length) << 16) | (1U << 30))
+#define HW16_MASK_ARRAY_OVERRIDE(addr, length) (0x20000001 | (((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(length) << 16))
+#define HW32_MASK_ARRAY_OVERRIDE(addr, length) (0x60000001 | (((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(length) << 16))
+#define HW16_MASK_VAL(mask, val) ((mask) << 16 | (val))
+#define ADI_ARRAY_OVERRIDE(adiNo, addr, bHalfSize, length) (1 | ((((addr) & 0x3F) << 2)) | \
+((!!(bHalfSize)) << 8) | ((!!(adiNo)) << 9) | ((uint32_t)(length) << 16) | (2U << 30))
+#define SW_ARRAY_OVERRIDE(cmd, firstfield, length) (1 | (((_POSITION_##cmd##_##firstfield)) << 2) | \
+((uint32_t)(length) << 16) | (3U << 30))
+#define MCE_RFE_OVERRIDE(mceCfg, mceRomBank, mceMode, rfeCfg, rfeRomBank, rfeMode) \
+ (7 | ((mceCfg & 2) << 3) | ((rfeCfg & 2) << 4) |\
+ ((mceCfg & 1) << 6) | (((mceRomBank) & 0x0F) << 7) | \
+ ((rfeCfg & 1) << 11) | (((rfeRomBank) & 0x0F) << 12) | \
+ (((mceMode) & 0x00FF) << 16) | (((rfeMode) & 0x00FF) << 24))
+#define HPOSC_OVERRIDE(freqOffset) (0x000B | ((freqOffset) << 16))
+#define TX20_POWER_OVERRIDE(tx20Power) (0x002B | (((uint32_t) tx20Power) << 10))
+#define TX_STD_POWER_OVERRIDE(txPower) (0x022B | (((uint32_t) txPower) << 10))
+#define MCE_RFE_SPLIT_OVERRIDE(mceRxCfg, mceTxCfg, rfeRxCfg, rfeTxCfg) \
+ (0x003B | ((mceRxCfg) << 12) | ((mceTxCfg) << 17) | ((rfeRxCfg) << 22) | ((rfeTxCfg) << 27))
+#define CENTER_FREQ_OVERRIDE(centerFreq, flags) (0x004B | ((flags & 0x03) << 18) | \
+ ((centerFreq) << 20))
+#define MOD_TYPE_OVERRIDE(modType, deviation, stepSz, flags) (0x005B | ((flags & 0x01) << 15) | \
+ ((modType) << 16) | ((deviation) << 19) |((stepSz) << 30) )
+#define NEW_OVERRIDE_SEGMENT(address) (((((uintptr_t)(address)) & 0x03FFFFFC) << 6) | 0x000F | \
+ (((((uintptr_t)(address) >> 24) == 0x20) ? 0x01 : \
+ (((uintptr_t)(address) >> 24) == 0x21) ? 0x02 : \
+ (((uintptr_t)(address) >> 24) == 0xA0) ? 0x03 : \
+ (((uintptr_t)(address) >> 24) == 0x00) ? 0x04 : \
+ (((uintptr_t)(address) >> 24) == 0x10) ? 0x05 : \
+ (((uintptr_t)(address) >> 24) == 0x11) ? 0x06 : \
+ (((uintptr_t)(address) >> 24) == 0x40) ? 0x07 : \
+ (((uintptr_t)(address) >> 24) == 0x50) ? 0x08 : \
+ 0x09) << 4)) // Use illegal value for illegal address range
+/// End of string for override register
+#define END_OVERRIDE 0xFFFFFFFF
+
+
+/// ADI address-value pair
+#define ADI_ADDR_VAL(addr, value) ((((addr) & 0x7F) << 8) | ((value) & 0xFF))
+#define ADI_ADDR_VAL_MASK(addr, mask, value) ((((addr) & 0x7F) << 8) | ADI_VAL_MASK(addr, mask, value))
+
+/// Low half-word
+#define LOWORD(value) ((value) & 0xFFFF)
+/// High half-word
+#define HIWORD(value) ((value) >> 16)
+///@}
+
+
+#endif
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_prop_cmd.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_prop_cmd.h
new file mode 100644
index 0000000..6dbccd6
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_prop_cmd.h
@@ -0,0 +1,1171 @@
+/******************************************************************************
+* Filename: rf_prop_cmd.h
+* Revised: 2018-07-31 20:13:42 +0200 (Tue, 31 Jul 2018)
+* Revision: 18572
+*
+* Description: CC13x2/CC26x2 API for Proprietary mode commands
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __PROP_CMD_H
+#define __PROP_CMD_H
+
+#ifndef __RFC_STRUCT
+#define __RFC_STRUCT
+#endif
+
+#ifndef __RFC_STRUCT_ATTR
+#if defined(__GNUC__)
+#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4)))
+#elif defined(__TI_ARM__)
+#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4)))
+#else
+#define __RFC_STRUCT_ATTR
+#endif
+#endif
+
+//! \addtogroup rfc
+//! @{
+
+//! \addtogroup prop_cmd
+//! @{
+
+#include <stdint.h>
+#include "rf_mailbox.h"
+#include "rf_common_cmd.h"
+
+typedef struct __RFC_STRUCT rfc_carrierSense_s rfc_carrierSense_t;
+typedef struct __RFC_STRUCT rfc_CMD_PROP_TX_s rfc_CMD_PROP_TX_t;
+typedef struct __RFC_STRUCT rfc_CMD_PROP_RX_s rfc_CMD_PROP_RX_t;
+typedef struct __RFC_STRUCT rfc_CMD_PROP_TX_ADV_s rfc_CMD_PROP_TX_ADV_t;
+typedef struct __RFC_STRUCT rfc_CMD_PROP_RX_ADV_s rfc_CMD_PROP_RX_ADV_t;
+typedef struct __RFC_STRUCT rfc_CMD_PROP_CS_s rfc_CMD_PROP_CS_t;
+typedef struct __RFC_STRUCT rfc_CMD_PROP_RADIO_SETUP_s rfc_CMD_PROP_RADIO_SETUP_t;
+typedef struct __RFC_STRUCT rfc_CMD_PROP_RADIO_DIV_SETUP_s rfc_CMD_PROP_RADIO_DIV_SETUP_t;
+typedef struct __RFC_STRUCT rfc_CMD_PROP_RX_SNIFF_s rfc_CMD_PROP_RX_SNIFF_t;
+typedef struct __RFC_STRUCT rfc_CMD_PROP_RX_ADV_SNIFF_s rfc_CMD_PROP_RX_ADV_SNIFF_t;
+typedef struct __RFC_STRUCT rfc_CMD_PROP_RADIO_SETUP_PA_s rfc_CMD_PROP_RADIO_SETUP_PA_t;
+typedef struct __RFC_STRUCT rfc_CMD_PROP_RADIO_DIV_SETUP_PA_s rfc_CMD_PROP_RADIO_DIV_SETUP_PA_t;
+typedef struct __RFC_STRUCT rfc_CMD_PROP_SET_LEN_s rfc_CMD_PROP_SET_LEN_t;
+typedef struct __RFC_STRUCT rfc_CMD_PROP_RESTART_RX_s rfc_CMD_PROP_RESTART_RX_t;
+typedef struct __RFC_STRUCT rfc_propRxOutput_s rfc_propRxOutput_t;
+typedef struct __RFC_STRUCT rfc_propRxStatus_s rfc_propRxStatus_t;
+
+//! \addtogroup carrierSense
+//! @{
+struct __RFC_STRUCT rfc_carrierSense_s {
+ struct {
+ uint8_t bEnaRssi:1; //!< If 1, enable RSSI as a criterion
+ uint8_t bEnaCorr:1; //!< If 1, enable correlation as a criterion
+ uint8_t operation:1; //!< \brief 0: Busy if either RSSI or correlation indicates Busy<br>
+ //!< 1: Busy if both RSSI and correlation indicates Busy
+ uint8_t busyOp:1; //!< \brief 0: Continue carrier sense on channel Busy<br>
+ //!< 1: End carrier sense on channel Busy<br>
+ //!< For an RX command, the receiver will continue when carrier sense ends, but it will then not end if channel goes Idle
+ uint8_t idleOp:1; //!< \brief 0: Continue on channel Idle<br>
+ //!< 1: End on channel Idle
+ uint8_t timeoutRes:1; //!< \brief 0: Timeout with channel state Invalid treated as Busy<br>
+ //!< 1: Timeout with channel state Invalid treated as Idle
+ } csConf;
+ int8_t rssiThr; //!< RSSI threshold
+ uint8_t numRssiIdle; //!< \brief Number of consecutive RSSI measurements below the threshold needed before the channel is
+ //!< declared Idle
+ uint8_t numRssiBusy; //!< \brief Number of consecutive RSSI measurements above the threshold needed before the channel is
+ //!< declared Busy
+ uint16_t corrPeriod; //!< Number of RAT ticks for a correlation observation periods
+ struct {
+ uint8_t numCorrInv:4; //!< \brief Number of subsequent correlation tops with maximum <code>corrPeriod</code> RAT
+ //!< ticks between them needed to go from Idle to Invalid
+ uint8_t numCorrBusy:4; //!< \brief Number of subsequent correlation tops with maximum <code>corrPeriod</code> RAT
+ //!< ticks between them needed to go from Invalid to Busy
+ } corrConfig;
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } csEndTrigger; //!< Trigger classifier for ending the carrier sense
+ ratmr_t csEndTime; //!< Time used together with <code>csEndTrigger</code> for ending the operation
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_PROP_TX
+//! @{
+#define CMD_PROP_TX 0x3801
+//! Proprietary Mode Transmit Command
+struct __RFC_STRUCT rfc_CMD_PROP_TX_s {
+ uint16_t commandNo; //!< The command ID number 0x3801
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ struct {
+ uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command<br>
+ //!< 1: Turn frequency synth off after command
+ uint8_t :2;
+ uint8_t bUseCrc:1; //!< \brief 0: Do not append CRC<br>
+ //!< 1: Append CRC
+ uint8_t bVarLen:1; //!< \brief 0: Fixed length<br>
+ //!< 1: Transmit length as first byte
+ } pktConf;
+ uint8_t pktLen; //!< Packet length
+ uint32_t syncWord; //!< Sync word to transmit
+ uint8_t* pPkt; //!< Pointer to packet
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_PROP_RX
+//! @{
+#define CMD_PROP_RX 0x3802
+//! Proprietary Mode Receive Command
+struct __RFC_STRUCT rfc_CMD_PROP_RX_s {
+ uint16_t commandNo; //!< The command ID number 0x3802
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ struct {
+ uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command<br>
+ //!< 1: Turn frequency synth off after command
+ uint8_t bRepeatOk:1; //!< \brief 0: End operation after receiving a packet correctly<br>
+ //!< 1: Go back to sync search after receiving a packet correctly
+ uint8_t bRepeatNok:1; //!< \brief 0: End operation after receiving a packet with CRC error<br>
+ //!< 1: Go back to sync search after receiving a packet with CRC error
+ uint8_t bUseCrc:1; //!< \brief 0: Do not check CRC<br>
+ //!< 1: Check CRC
+ uint8_t bVarLen:1; //!< \brief 0: Fixed length<br>
+ //!< 1: Receive length as first byte
+ uint8_t bChkAddress:1; //!< \brief 0: No address check<br>
+ //!< 1: Check address
+ uint8_t endType:1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained<br>
+ //!< 1: Packet reception is stopped if end trigger happens
+ uint8_t filterOp:1; //!< \brief 0: Stop receiver and restart sync search on address mismatch<br>
+ //!< 1: Receive packet and mark it as ignored on address mismatch
+ } pktConf;
+ struct {
+ uint8_t bAutoFlushIgnored:1; //!< If 1, automatically discard ignored packets from RX queue
+ uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically discard packets with CRC error from RX queue
+ uint8_t :1;
+ uint8_t bIncludeHdr:1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it
+ uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it
+ uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the RX queue
+ uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the RX queue
+ uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the RX queue
+ } rxConf; //!< RX configuration
+ uint32_t syncWord; //!< Sync word to listen for
+ uint8_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length<br>
+ //!< 0: Unlimited or unknown length
+ uint8_t address0; //!< Address
+ uint8_t address1; //!< \brief Address (set equal to <code>address0</code> to accept only one address. If 0xFF, accept
+ //!< 0x00 as well)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } endTrigger; //!< Trigger classifier for ending the operation
+ ratmr_t endTime; //!< Time used together with <code>endTrigger</code> for ending the operation
+ dataQueue_t* pQueue; //!< Pointer to receive queue
+ uint8_t* pOutput; //!< Pointer to output structure
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_PROP_TX_ADV
+//! @{
+#define CMD_PROP_TX_ADV 0x3803
+//! Proprietary Mode Advanced Transmit Command
+struct __RFC_STRUCT rfc_CMD_PROP_TX_ADV_s {
+ uint16_t commandNo; //!< The command ID number 0x3803
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ struct {
+ uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command<br>
+ //!< 1: Turn frequency synth off after command
+ uint8_t :2;
+ uint8_t bUseCrc:1; //!< \brief 0: Do not append CRC<br>
+ //!< 1: Append CRC
+ uint8_t bCrcIncSw:1; //!< \brief 0:Do not include sync word in CRC calculation<br>
+ //!< 1: Include sync word in CRC calculation
+ uint8_t bCrcIncHdr:1; //!< \brief 0: Do not include header in CRC calculation<br>
+ //!< 1: Include header in CRC calculation
+ } pktConf;
+ uint8_t numHdrBits; //!< Number of bits in header (0--32)
+ uint16_t pktLen; //!< Packet length. 0: Unlimited
+ struct {
+ uint8_t bExtTxTrig:1; //!< \brief 0: Start packet on a fixed time from the command start trigger<br>
+ //!< 1: Start packet on an external trigger (input event to RAT)
+ uint8_t inputMode:2; //!< \brief Input mode if external trigger is used for TX start<br>
+ //!< 0: Rising edge<br>
+ //!< 1: Falling edge<br>
+ //!< 2: Both edges<br>
+ //!< 3: <i>Reserved</i>
+ uint8_t source:5; //!< RAT input event number used for capture if external trigger is used for TX start
+ } startConf;
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } preTrigger; //!< Trigger for transition from preamble to sync word
+ ratmr_t preTime; //!< \brief Time used together with <code>preTrigger</code> for transition from preamble to sync
+ //!< word. If <code>preTrigger.triggerType</code> is set to "now", one preamble as
+ //!< configured in the setup will be sent. Otherwise, the preamble will be repeated until
+ //!< this trigger is observed.
+ uint32_t syncWord; //!< Sync word to transmit
+ uint8_t* pPkt; //!< Pointer to packet, or TX queue for unlimited length
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_PROP_RX_ADV
+//! @{
+#define CMD_PROP_RX_ADV 0x3804
+//! Proprietary Mode Advanced Receive Command
+struct __RFC_STRUCT rfc_CMD_PROP_RX_ADV_s {
+ uint16_t commandNo; //!< The command ID number 0x3804
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ struct {
+ uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command<br>
+ //!< 1: Turn frequency synth off after command
+ uint8_t bRepeatOk:1; //!< \brief 0: End operation after receiving a packet correctly<br>
+ //!< 1: Go back to sync search after receiving a packet correctly
+ uint8_t bRepeatNok:1; //!< \brief 0: End operation after receiving a packet with CRC error<br>
+ //!< 1: Go back to sync search after receiving a packet with CRC error
+ uint8_t bUseCrc:1; //!< \brief 0: Do not check CRC<br>
+ //!< 1: Check CRC
+ uint8_t bCrcIncSw:1; //!< \brief 0: Do not include sync word in CRC calculation<br>
+ //!< 1: Include sync word in CRC calculation
+ uint8_t bCrcIncHdr:1; //!< \brief 0: Do not include header in CRC calculation <br>
+ //!< 1: Include header in CRC calculation
+ uint8_t endType:1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained<br>
+ //!< 1: Packet reception is stopped if end trigger happens
+ uint8_t filterOp:1; //!< \brief 0: Stop receiver and restart sync search on address mismatch<br>
+ //!< 1: Receive packet and mark it as ignored on address mismatch
+ } pktConf;
+ struct {
+ uint8_t bAutoFlushIgnored:1; //!< If 1, automatically discard ignored packets from RX queue
+ uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically discard packets with CRC error from RX queue
+ uint8_t :1;
+ uint8_t bIncludeHdr:1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it
+ uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it
+ uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the RX queue
+ uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the RX queue
+ uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the RX queue
+ } rxConf; //!< RX configuration
+ uint32_t syncWord0; //!< Sync word to listen for
+ uint32_t syncWord1; //!< Alternative sync word if non-zero
+ uint16_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length<br>
+ //!< 0: Unlimited or unknown length
+ struct {
+ uint16_t numHdrBits:6; //!< Number of bits in header (0--32)
+ uint16_t lenPos:5; //!< Position of length field in header (0--31)
+ uint16_t numLenBits:5; //!< Number of bits in length field (0--16)
+ } hdrConf;
+ struct {
+ uint16_t addrType:1; //!< \brief 0: Address after header<br>
+ //!< 1: Address in header
+ uint16_t addrSize:5; //!< \brief If <code>addrType</code> = 0: Address size in bytes<br>
+ //!< If <code>addrType</code> = 1: Address size in bits
+ uint16_t addrPos:5; //!< \brief If <code>addrType</code> = 1: Bit position of address in header<br>
+ //!< If <code>addrType</code> = 0: Non-zero to extend address with sync word identifier
+ uint16_t numAddr:5; //!< Number of addresses in address list
+ } addrConf;
+ int8_t lenOffset; //!< Signed value to add to length field
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } endTrigger; //!< Trigger classifier for ending the operation
+ ratmr_t endTime; //!< Time used together with <code>endTrigger</code> for ending the operation
+ uint8_t* pAddr; //!< Pointer to address list
+ dataQueue_t* pQueue; //!< Pointer to receive queue
+ uint8_t* pOutput; //!< Pointer to output structure
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_PROP_CS
+//! @{
+#define CMD_PROP_CS 0x3805
+//! Carrier Sense Command
+struct __RFC_STRUCT rfc_CMD_PROP_CS_s {
+ uint16_t commandNo; //!< The command ID number 0x3805
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ struct {
+ uint8_t bFsOffIdle:1; //!< \brief 0: Keep synth running if command ends with channel Idle<br>
+ //!< 1: Turn off synth if command ends with channel Idle
+ uint8_t bFsOffBusy:1; //!< \brief 0: Keep synth running if command ends with channel Busy<br>
+ //!< 1: Turn off synth if command ends with channel Busy
+ } csFsConf;
+ uint8_t __dummy0;
+ struct {
+ uint8_t bEnaRssi:1; //!< If 1, enable RSSI as a criterion
+ uint8_t bEnaCorr:1; //!< If 1, enable correlation as a criterion
+ uint8_t operation:1; //!< \brief 0: Busy if either RSSI or correlation indicates Busy<br>
+ //!< 1: Busy if both RSSI and correlation indicates Busy
+ uint8_t busyOp:1; //!< \brief 0: Continue carrier sense on channel Busy<br>
+ //!< 1: End carrier sense on channel Busy<br>
+ //!< For an RX command, the receiver will continue when carrier sense ends, but it will then not end if channel goes Idle
+ uint8_t idleOp:1; //!< \brief 0: Continue on channel Idle<br>
+ //!< 1: End on channel Idle
+ uint8_t timeoutRes:1; //!< \brief 0: Timeout with channel state Invalid treated as Busy<br>
+ //!< 1: Timeout with channel state Invalid treated as Idle
+ } csConf;
+ int8_t rssiThr; //!< RSSI threshold
+ uint8_t numRssiIdle; //!< \brief Number of consecutive RSSI measurements below the threshold needed before the channel is
+ //!< declared Idle
+ uint8_t numRssiBusy; //!< \brief Number of consecutive RSSI measurements above the threshold needed before the channel is
+ //!< declared Busy
+ uint16_t corrPeriod; //!< Number of RAT ticks for a correlation observation periods
+ struct {
+ uint8_t numCorrInv:4; //!< \brief Number of subsequent correlation tops with maximum <code>corrPeriod</code> RAT
+ //!< ticks between them needed to go from Idle to Invalid
+ uint8_t numCorrBusy:4; //!< \brief Number of subsequent correlation tops with maximum <code>corrPeriod</code> RAT
+ //!< ticks between them needed to go from Invalid to Busy
+ } corrConfig;
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } csEndTrigger; //!< Trigger classifier for ending the carrier sense
+ ratmr_t csEndTime; //!< Time used together with <code>csEndTrigger</code> for ending the operation
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_PROP_RADIO_SETUP
+//! @{
+#define CMD_PROP_RADIO_SETUP 0x3806
+//! Proprietary Mode Radio Setup Command for 2.4 GHz
+struct __RFC_STRUCT rfc_CMD_PROP_RADIO_SETUP_s {
+ uint16_t commandNo; //!< The command ID number 0x3806
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ struct {
+ uint16_t modType:3; //!< \brief 0: FSK<br>
+ //!< 1: GFSK<br>
+ //!< 2: OOK<br>
+ //!< Others: <i>Reserved</i>
+ uint16_t deviation:11; //!< Deviation (specified in number of steps, with step size given by <code>deviationStepSz</code>)
+ uint16_t deviationStepSz:2; //!< \brief Deviation step size<br>
+ //!< 0: 250 Hz<br>
+ //!< 1: 1000 Hz<br>
+ //!< 2: 15.625 Hz<br>
+ //!< 3: 62.5 Hz
+ } modulation;
+ struct {
+ uint32_t preScale:8; //!< Prescaler value
+ uint32_t rateWord:21; //!< Rate word
+ uint32_t decimMode:3; //!< \brief 0: Use automatic PDIF decimation<br>
+ //!< 1: Force PDIF decimation to 0<br>
+ //!< 3: Force PDIF decimation to 1<br>
+ //!< 5: Force PDIF decimation to 2<br>
+ //!< Others: <i>Reserved</i>
+ } symbolRate; //!< Symbol rate setting
+ uint8_t rxBw; //!< Receiver bandwidth
+ struct {
+ uint8_t nPreamBytes:6; //!< \brief 0: 1 preamble bit<br>
+ //!< 1--16: Number of preamble bytes<br>
+ //!< 18, 20, ..., 30: Number of preamble bytes<br>
+ //!< 31: 4 preamble bits<br>
+ //!< 32: 32 preamble bytes<br>
+ //!< Others: <i>Reserved</i>
+ uint8_t preamMode:2; //!< \brief 0: Send 0 as the first preamble bit<br>
+ //!< 1: Send 1 as the first preamble bit<br>
+ //!< 2: Send same first bit in preamble and sync word<br>
+ //!< 3: Send different first bit in preamble and sync word
+ } preamConf;
+ struct {
+ uint16_t nSwBits:6; //!< Number of sync word bits (8--32)
+ uint16_t bBitReversal:1; //!< \brief 0: Use positive deviation for 1<br>
+ //!< 1: Use positive deviation for 0
+ uint16_t bMsbFirst:1; //!< \brief 0: Least significant bit transmitted first<br>
+ //!< 1: Most significant bit transmitted first
+ uint16_t fecMode:4; //!< \brief Select coding<br>
+ //!< 0: Uncoded binary modulation<br>
+ //!< 10: Manchester coded binary modulation<br>
+ //!< Others: <i>Reserved</i>
+ uint16_t :1;
+ uint16_t whitenMode:3; //!< \brief 0: No whitening<br>
+ //!< 1: CC1101/CC2500 compatible whitening<br>
+ //!< 2: PN9 whitening without byte reversal<br>
+ //!< 3: <i>Reserved</i><br>
+ //!< 4: No whitener, 32-bit IEEE 802.15.4g compatible CRC<br>
+ //!< 5: IEEE 802.15.4g compatible whitener and 32-bit CRC<br>
+ //!< 6: No whitener, dynamically IEEE 802.15.4g compatible 16-bit or 32-bit CRC<br>
+ //!< 7: Dynamically IEEE 802.15.4g compatible whitener and 16-bit or 32-bit CRC
+ } formatConf;
+ struct {
+ uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode<br>
+ //!< 0x01: Single-ended mode RFP<br>
+ //!< 0x02: Single-ended mode RFN<br>
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)<br>
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)<br>
+ //!< Others: <i>Reserved</i>
+ uint16_t biasMode:1; //!< \brief 0: Internal bias<br>
+ //!< 1: External bias
+ uint16_t analogCfgMode:6; //!< \brief 0x00: Write analog configuration.<br>
+ //!< Required first time after boot and when changing frequency band
+ //!< or front-end configuration<br>
+ //!< 0x2D: Keep analog configuration.<br>
+ //!< May be used after standby or when changing mode with the same frequency
+ //!< band and front-end configuration<br>
+ //!< Others: <i>Reserved</i>
+ uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth<br>
+ //!< 1: Do not power up frequency synth
+ } config; //!< Configuration options
+ uint16_t txPower; //!< Transmit power
+ uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no
+ //!< override is used.
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_PROP_RADIO_DIV_SETUP
+//! @{
+#define CMD_PROP_RADIO_DIV_SETUP 0x3807
+//! Proprietary Mode Radio Setup Command for All Frequency Bands
+struct __RFC_STRUCT rfc_CMD_PROP_RADIO_DIV_SETUP_s {
+ uint16_t commandNo; //!< The command ID number 0x3807
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ struct {
+ uint16_t modType:3; //!< \brief 0: FSK<br>
+ //!< 1: GFSK<br>
+ //!< 2: OOK<br>
+ //!< Others: <i>Reserved</i>
+ uint16_t deviation:11; //!< Deviation (specified in number of steps, with step size given by <code>deviationStepSz</code>)
+ uint16_t deviationStepSz:2; //!< \brief Deviation step size<br>
+ //!< 0: 250 Hz<br>
+ //!< 1: 1000 Hz<br>
+ //!< 2: 15.625 Hz<br>
+ //!< 3: 62.5 Hz
+ } modulation;
+ struct {
+ uint32_t preScale:8; //!< Prescaler value
+ uint32_t rateWord:21; //!< Rate word
+ uint32_t decimMode:3; //!< \brief 0: Use automatic PDIF decimation<br>
+ //!< 1: Force PDIF decimation to 0<br>
+ //!< 3: Force PDIF decimation to 1<br>
+ //!< 5: Force PDIF decimation to 2<br>
+ //!< Others: <i>Reserved</i>
+ } symbolRate; //!< Symbol rate setting
+ uint8_t rxBw; //!< Receiver bandwidth
+ struct {
+ uint8_t nPreamBytes:6; //!< \brief 0: 1 preamble bit<br>
+ //!< 1--16: Number of preamble bytes<br>
+ //!< 18, 20, ..., 30: Number of preamble bytes<br>
+ //!< 31: 4 preamble bits<br>
+ //!< 32: 32 preamble bytes<br>
+ //!< Others: <i>Reserved</i>
+ uint8_t preamMode:2; //!< \brief 0: Send 0 as the first preamble bit<br>
+ //!< 1: Send 1 as the first preamble bit<br>
+ //!< 2: Send same first bit in preamble and sync word<br>
+ //!< 3: Send different first bit in preamble and sync word
+ } preamConf;
+ struct {
+ uint16_t nSwBits:6; //!< Number of sync word bits (8--32)
+ uint16_t bBitReversal:1; //!< \brief 0: Use positive deviation for 1<br>
+ //!< 1: Use positive deviation for 0
+ uint16_t bMsbFirst:1; //!< \brief 0: Least significant bit transmitted first<br>
+ //!< 1: Most significant bit transmitted first
+ uint16_t fecMode:4; //!< \brief Select coding<br>
+ //!< 0: Uncoded binary modulation<br>
+ //!< 10: Manchester coded binary modulation<br>
+ //!< Others: <i>Reserved</i>
+ uint16_t :1;
+ uint16_t whitenMode:3; //!< \brief 0: No whitening<br>
+ //!< 1: CC1101/CC2500 compatible whitening<br>
+ //!< 2: PN9 whitening without byte reversal<br>
+ //!< 3: <i>Reserved</i><br>
+ //!< 4: No whitener, 32-bit IEEE 802.15.4g compatible CRC<br>
+ //!< 5: IEEE 802.15.4g compatible whitener and 32-bit CRC<br>
+ //!< 6: No whitener, dynamically IEEE 802.15.4g compatible 16-bit or 32-bit CRC<br>
+ //!< 7: Dynamically IEEE 802.15.4g compatible whitener and 16-bit or 32-bit CRC
+ } formatConf;
+ struct {
+ uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode<br>
+ //!< 0x01: Single-ended mode RFP<br>
+ //!< 0x02: Single-ended mode RFN<br>
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)<br>
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)<br>
+ //!< Others: <i>Reserved</i>
+ uint16_t biasMode:1; //!< \brief 0: Internal bias<br>
+ //!< 1: External bias
+ uint16_t analogCfgMode:6; //!< \brief 0x00: Write analog configuration.<br>
+ //!< Required first time after boot and when changing frequency band
+ //!< or front-end configuration<br>
+ //!< 0x2D: Keep analog configuration.<br>
+ //!< May be used after standby or when changing mode with the same frequency
+ //!< band and front-end configuration<br>
+ //!< Others: <i>Reserved</i>
+ uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth<br>
+ //!< 1: Do not power up frequency synth
+ } config; //!< Configuration options
+ uint16_t txPower; //!< Transmit power
+ uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no
+ //!< override is used.
+ uint16_t centerFreq; //!< \brief Center frequency of the frequency band used, in MHz; used for calculating some internal TX and RX parameters.
+ //!< For a single channel RF system, this should be set equal to the RF frequency used.
+ //!< For a multi channel RF system (e.g. frequency hopping spread spectrum), this should be set equal
+ //!< to the center frequency of the frequency band used.
+ int16_t intFreq; //!< \brief Intermediate frequency to use for RX, in MHz on 4.12 signed format. TX will use same
+ //!< intermediate frequency if supported, otherwise 0.<br>
+ //!< 0x8000: Use default.
+ uint8_t loDivider; //!< LO frequency divider setting to use. Supported values: 0, 2, 4, 5, 6, 10, 12, 15, and 30
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_PROP_RX_SNIFF
+//! @{
+#define CMD_PROP_RX_SNIFF 0x3808
+//! Proprietary Mode Receive Command with Sniff Mode
+struct __RFC_STRUCT rfc_CMD_PROP_RX_SNIFF_s {
+ uint16_t commandNo; //!< The command ID number 0x3808
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ struct {
+ uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command<br>
+ //!< 1: Turn frequency synth off after command
+ uint8_t bRepeatOk:1; //!< \brief 0: End operation after receiving a packet correctly<br>
+ //!< 1: Go back to sync search after receiving a packet correctly
+ uint8_t bRepeatNok:1; //!< \brief 0: End operation after receiving a packet with CRC error<br>
+ //!< 1: Go back to sync search after receiving a packet with CRC error
+ uint8_t bUseCrc:1; //!< \brief 0: Do not check CRC<br>
+ //!< 1: Check CRC
+ uint8_t bVarLen:1; //!< \brief 0: Fixed length<br>
+ //!< 1: Receive length as first byte
+ uint8_t bChkAddress:1; //!< \brief 0: No address check<br>
+ //!< 1: Check address
+ uint8_t endType:1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained<br>
+ //!< 1: Packet reception is stopped if end trigger happens
+ uint8_t filterOp:1; //!< \brief 0: Stop receiver and restart sync search on address mismatch<br>
+ //!< 1: Receive packet and mark it as ignored on address mismatch
+ } pktConf;
+ struct {
+ uint8_t bAutoFlushIgnored:1; //!< If 1, automatically discard ignored packets from RX queue
+ uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically discard packets with CRC error from RX queue
+ uint8_t :1;
+ uint8_t bIncludeHdr:1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it
+ uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it
+ uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the RX queue
+ uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the RX queue
+ uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the RX queue
+ } rxConf; //!< RX configuration
+ uint32_t syncWord; //!< Sync word to listen for
+ uint8_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length<br>
+ //!< 0: Unlimited or unknown length
+ uint8_t address0; //!< Address
+ uint8_t address1; //!< \brief Address (set equal to <code>address0</code> to accept only one address. If 0xFF, accept
+ //!< 0x00 as well)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } endTrigger; //!< Trigger classifier for ending the operation
+ ratmr_t endTime; //!< Time used together with <code>endTrigger</code> for ending the operation
+ dataQueue_t* pQueue; //!< Pointer to receive queue
+ uint8_t* pOutput; //!< Pointer to output structure
+ struct {
+ uint8_t bEnaRssi:1; //!< If 1, enable RSSI as a criterion
+ uint8_t bEnaCorr:1; //!< If 1, enable correlation as a criterion
+ uint8_t operation:1; //!< \brief 0: Busy if either RSSI or correlation indicates Busy<br>
+ //!< 1: Busy if both RSSI and correlation indicates Busy
+ uint8_t busyOp:1; //!< \brief 0: Continue carrier sense on channel Busy<br>
+ //!< 1: End carrier sense on channel Busy<br>
+ //!< For an RX command, the receiver will continue when carrier sense ends, but it will then not end if channel goes Idle
+ uint8_t idleOp:1; //!< \brief 0: Continue on channel Idle<br>
+ //!< 1: End on channel Idle
+ uint8_t timeoutRes:1; //!< \brief 0: Timeout with channel state Invalid treated as Busy<br>
+ //!< 1: Timeout with channel state Invalid treated as Idle
+ } csConf;
+ int8_t rssiThr; //!< RSSI threshold
+ uint8_t numRssiIdle; //!< \brief Number of consecutive RSSI measurements below the threshold needed before the channel is
+ //!< declared Idle
+ uint8_t numRssiBusy; //!< \brief Number of consecutive RSSI measurements above the threshold needed before the channel is
+ //!< declared Busy
+ uint16_t corrPeriod; //!< Number of RAT ticks for a correlation observation periods
+ struct {
+ uint8_t numCorrInv:4; //!< \brief Number of subsequent correlation tops with maximum <code>corrPeriod</code> RAT
+ //!< ticks between them needed to go from Idle to Invalid
+ uint8_t numCorrBusy:4; //!< \brief Number of subsequent correlation tops with maximum <code>corrPeriod</code> RAT
+ //!< ticks between them needed to go from Invalid to Busy
+ } corrConfig;
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } csEndTrigger; //!< Trigger classifier for ending the carrier sense
+ ratmr_t csEndTime; //!< Time used together with <code>csEndTrigger</code> for ending the operation
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_PROP_RX_ADV_SNIFF
+//! @{
+#define CMD_PROP_RX_ADV_SNIFF 0x3809
+//! Proprietary Mode Advanced Receive Command with Sniff Mode
+struct __RFC_STRUCT rfc_CMD_PROP_RX_ADV_SNIFF_s {
+ uint16_t commandNo; //!< The command ID number 0x3809
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ struct {
+ uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command<br>
+ //!< 1: Turn frequency synth off after command
+ uint8_t bRepeatOk:1; //!< \brief 0: End operation after receiving a packet correctly<br>
+ //!< 1: Go back to sync search after receiving a packet correctly
+ uint8_t bRepeatNok:1; //!< \brief 0: End operation after receiving a packet with CRC error<br>
+ //!< 1: Go back to sync search after receiving a packet with CRC error
+ uint8_t bUseCrc:1; //!< \brief 0: Do not check CRC<br>
+ //!< 1: Check CRC
+ uint8_t bCrcIncSw:1; //!< \brief 0: Do not include sync word in CRC calculation<br>
+ //!< 1: Include sync word in CRC calculation
+ uint8_t bCrcIncHdr:1; //!< \brief 0: Do not include header in CRC calculation <br>
+ //!< 1: Include header in CRC calculation
+ uint8_t endType:1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained<br>
+ //!< 1: Packet reception is stopped if end trigger happens
+ uint8_t filterOp:1; //!< \brief 0: Stop receiver and restart sync search on address mismatch<br>
+ //!< 1: Receive packet and mark it as ignored on address mismatch
+ } pktConf;
+ struct {
+ uint8_t bAutoFlushIgnored:1; //!< If 1, automatically discard ignored packets from RX queue
+ uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically discard packets with CRC error from RX queue
+ uint8_t :1;
+ uint8_t bIncludeHdr:1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it
+ uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it
+ uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the RX queue
+ uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the RX queue
+ uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the RX queue
+ } rxConf; //!< RX configuration
+ uint32_t syncWord0; //!< Sync word to listen for
+ uint32_t syncWord1; //!< Alternative sync word if non-zero
+ uint16_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length<br>
+ //!< 0: Unlimited or unknown length
+ struct {
+ uint16_t numHdrBits:6; //!< Number of bits in header (0--32)
+ uint16_t lenPos:5; //!< Position of length field in header (0--31)
+ uint16_t numLenBits:5; //!< Number of bits in length field (0--16)
+ } hdrConf;
+ struct {
+ uint16_t addrType:1; //!< \brief 0: Address after header<br>
+ //!< 1: Address in header
+ uint16_t addrSize:5; //!< \brief If <code>addrType</code> = 0: Address size in bytes<br>
+ //!< If <code>addrType</code> = 1: Address size in bits
+ uint16_t addrPos:5; //!< \brief If <code>addrType</code> = 1: Bit position of address in header<br>
+ //!< If <code>addrType</code> = 0: Non-zero to extend address with sync word identifier
+ uint16_t numAddr:5; //!< Number of addresses in address list
+ } addrConf;
+ int8_t lenOffset; //!< Signed value to add to length field
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } endTrigger; //!< Trigger classifier for ending the operation
+ ratmr_t endTime; //!< Time used together with <code>endTrigger</code> for ending the operation
+ uint8_t* pAddr; //!< Pointer to address list
+ dataQueue_t* pQueue; //!< Pointer to receive queue
+ uint8_t* pOutput; //!< Pointer to output structure
+ struct {
+ uint8_t bEnaRssi:1; //!< If 1, enable RSSI as a criterion
+ uint8_t bEnaCorr:1; //!< If 1, enable correlation as a criterion
+ uint8_t operation:1; //!< \brief 0: Busy if either RSSI or correlation indicates Busy<br>
+ //!< 1: Busy if both RSSI and correlation indicates Busy
+ uint8_t busyOp:1; //!< \brief 0: Continue carrier sense on channel Busy<br>
+ //!< 1: End carrier sense on channel Busy<br>
+ //!< For an RX command, the receiver will continue when carrier sense ends, but it will then not end if channel goes Idle
+ uint8_t idleOp:1; //!< \brief 0: Continue on channel Idle<br>
+ //!< 1: End on channel Idle
+ uint8_t timeoutRes:1; //!< \brief 0: Timeout with channel state Invalid treated as Busy<br>
+ //!< 1: Timeout with channel state Invalid treated as Idle
+ } csConf;
+ int8_t rssiThr; //!< RSSI threshold
+ uint8_t numRssiIdle; //!< \brief Number of consecutive RSSI measurements below the threshold needed before the channel is
+ //!< declared Idle
+ uint8_t numRssiBusy; //!< \brief Number of consecutive RSSI measurements above the threshold needed before the channel is
+ //!< declared Busy
+ uint16_t corrPeriod; //!< Number of RAT ticks for a correlation observation periods
+ struct {
+ uint8_t numCorrInv:4; //!< \brief Number of subsequent correlation tops with maximum <code>corrPeriod</code> RAT
+ //!< ticks between them needed to go from Idle to Invalid
+ uint8_t numCorrBusy:4; //!< \brief Number of subsequent correlation tops with maximum <code>corrPeriod</code> RAT
+ //!< ticks between them needed to go from Invalid to Busy
+ } corrConfig;
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } csEndTrigger; //!< Trigger classifier for ending the carrier sense
+ ratmr_t csEndTime; //!< Time used together with <code>csEndTrigger</code> for ending the operation
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_PROP_RADIO_SETUP_PA
+//! @{
+//! Proprietary Mode Radio Setup Command for 2.4 GHz with PA Switching Fields
+struct __RFC_STRUCT rfc_CMD_PROP_RADIO_SETUP_PA_s {
+ uint16_t commandNo; //!< The command ID number
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ struct {
+ uint16_t modType:3; //!< \brief 0: FSK<br>
+ //!< 1: GFSK<br>
+ //!< 2: OOK<br>
+ //!< Others: <i>Reserved</i>
+ uint16_t deviation:11; //!< Deviation (specified in number of steps, with step size given by <code>deviationStepSz</code>)
+ uint16_t deviationStepSz:2; //!< \brief Deviation step size<br>
+ //!< 0: 250 Hz<br>
+ //!< 1: 1000 Hz<br>
+ //!< 2: 15.625 Hz<br>
+ //!< 3: 62.5 Hz
+ } modulation;
+ struct {
+ uint32_t preScale:8; //!< Prescaler value
+ uint32_t rateWord:21; //!< Rate word
+ uint32_t decimMode:3; //!< \brief 0: Use automatic PDIF decimation<br>
+ //!< 1: Force PDIF decimation to 0<br>
+ //!< 3: Force PDIF decimation to 1<br>
+ //!< 5: Force PDIF decimation to 2<br>
+ //!< Others: <i>Reserved</i>
+ } symbolRate; //!< Symbol rate setting
+ uint8_t rxBw; //!< Receiver bandwidth
+ struct {
+ uint8_t nPreamBytes:6; //!< \brief 0: 1 preamble bit<br>
+ //!< 1--16: Number of preamble bytes<br>
+ //!< 18, 20, ..., 30: Number of preamble bytes<br>
+ //!< 31: 4 preamble bits<br>
+ //!< 32: 32 preamble bytes<br>
+ //!< Others: <i>Reserved</i>
+ uint8_t preamMode:2; //!< \brief 0: Send 0 as the first preamble bit<br>
+ //!< 1: Send 1 as the first preamble bit<br>
+ //!< 2: Send same first bit in preamble and sync word<br>
+ //!< 3: Send different first bit in preamble and sync word
+ } preamConf;
+ struct {
+ uint16_t nSwBits:6; //!< Number of sync word bits (8--32)
+ uint16_t bBitReversal:1; //!< \brief 0: Use positive deviation for 1<br>
+ //!< 1: Use positive deviation for 0
+ uint16_t bMsbFirst:1; //!< \brief 0: Least significant bit transmitted first<br>
+ //!< 1: Most significant bit transmitted first
+ uint16_t fecMode:4; //!< \brief Select coding<br>
+ //!< 0: Uncoded binary modulation<br>
+ //!< 10: Manchester coded binary modulation<br>
+ //!< Others: <i>Reserved</i>
+ uint16_t :1;
+ uint16_t whitenMode:3; //!< \brief 0: No whitening<br>
+ //!< 1: CC1101/CC2500 compatible whitening<br>
+ //!< 2: PN9 whitening without byte reversal<br>
+ //!< 3: <i>Reserved</i><br>
+ //!< 4: No whitener, 32-bit IEEE 802.15.4g compatible CRC<br>
+ //!< 5: IEEE 802.15.4g compatible whitener and 32-bit CRC<br>
+ //!< 6: No whitener, dynamically IEEE 802.15.4g compatible 16-bit or 32-bit CRC<br>
+ //!< 7: Dynamically IEEE 802.15.4g compatible whitener and 16-bit or 32-bit CRC
+ } formatConf;
+ struct {
+ uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode<br>
+ //!< 0x01: Single-ended mode RFP<br>
+ //!< 0x02: Single-ended mode RFN<br>
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)<br>
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)<br>
+ //!< Others: <i>Reserved</i>
+ uint16_t biasMode:1; //!< \brief 0: Internal bias<br>
+ //!< 1: External bias
+ uint16_t analogCfgMode:6; //!< \brief 0x00: Write analog configuration.<br>
+ //!< Required first time after boot and when changing frequency band
+ //!< or front-end configuration<br>
+ //!< 0x2D: Keep analog configuration.<br>
+ //!< May be used after standby or when changing mode with the same frequency
+ //!< band and front-end configuration<br>
+ //!< Others: <i>Reserved</i>
+ uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth<br>
+ //!< 1: Do not power up frequency synth
+ } config; //!< Configuration options
+ uint16_t txPower; //!< Transmit power
+ uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no
+ //!< override is used.
+ uint32_t* pRegOverrideTxStd; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to
+ //!< standard PA. Used by RF driver only, not radio CPU.
+ uint32_t* pRegOverrideTx20; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to
+ //!< 20-dBm PA. Used by RF driver only, not radio CPU.
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_PROP_RADIO_DIV_SETUP_PA
+//! @{
+//! Proprietary Mode Radio Setup Command for All Frequency Bands with PA Switching Fields
+struct __RFC_STRUCT rfc_CMD_PROP_RADIO_DIV_SETUP_PA_s {
+ uint16_t commandNo; //!< The command ID number
+ uint16_t status; //!< \brief An integer telling the status of the command. This value is
+ //!< updated by the radio CPU during operation and may be read by the
+ //!< system CPU at any time.
+ rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
+ ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
+ struct {
+ uint8_t triggerType:4; //!< The type of trigger
+ uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger
+ uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
+ uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
+ //!< 1: A trigger in the past is triggered as soon as possible
+ } startTrigger; //!< Identification of the trigger that starts the operation
+ struct {
+ uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
+ uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ...
+ } condition;
+ struct {
+ uint16_t modType:3; //!< \brief 0: FSK<br>
+ //!< 1: GFSK<br>
+ //!< 2: OOK<br>
+ //!< Others: <i>Reserved</i>
+ uint16_t deviation:11; //!< Deviation (specified in number of steps, with step size given by <code>deviationStepSz</code>)
+ uint16_t deviationStepSz:2; //!< \brief Deviation step size<br>
+ //!< 0: 250 Hz<br>
+ //!< 1: 1000 Hz<br>
+ //!< 2: 15.625 Hz<br>
+ //!< 3: 62.5 Hz
+ } modulation;
+ struct {
+ uint32_t preScale:8; //!< Prescaler value
+ uint32_t rateWord:21; //!< Rate word
+ uint32_t decimMode:3; //!< \brief 0: Use automatic PDIF decimation<br>
+ //!< 1: Force PDIF decimation to 0<br>
+ //!< 3: Force PDIF decimation to 1<br>
+ //!< 5: Force PDIF decimation to 2<br>
+ //!< Others: <i>Reserved</i>
+ } symbolRate; //!< Symbol rate setting
+ uint8_t rxBw; //!< Receiver bandwidth
+ struct {
+ uint8_t nPreamBytes:6; //!< \brief 0: 1 preamble bit<br>
+ //!< 1--16: Number of preamble bytes<br>
+ //!< 18, 20, ..., 30: Number of preamble bytes<br>
+ //!< 31: 4 preamble bits<br>
+ //!< 32: 32 preamble bytes<br>
+ //!< Others: <i>Reserved</i>
+ uint8_t preamMode:2; //!< \brief 0: Send 0 as the first preamble bit<br>
+ //!< 1: Send 1 as the first preamble bit<br>
+ //!< 2: Send same first bit in preamble and sync word<br>
+ //!< 3: Send different first bit in preamble and sync word
+ } preamConf;
+ struct {
+ uint16_t nSwBits:6; //!< Number of sync word bits (8--32)
+ uint16_t bBitReversal:1; //!< \brief 0: Use positive deviation for 1<br>
+ //!< 1: Use positive deviation for 0
+ uint16_t bMsbFirst:1; //!< \brief 0: Least significant bit transmitted first<br>
+ //!< 1: Most significant bit transmitted first
+ uint16_t fecMode:4; //!< \brief Select coding<br>
+ //!< 0: Uncoded binary modulation<br>
+ //!< 10: Manchester coded binary modulation<br>
+ //!< Others: <i>Reserved</i>
+ uint16_t :1;
+ uint16_t whitenMode:3; //!< \brief 0: No whitening<br>
+ //!< 1: CC1101/CC2500 compatible whitening<br>
+ //!< 2: PN9 whitening without byte reversal<br>
+ //!< 3: <i>Reserved</i><br>
+ //!< 4: No whitener, 32-bit IEEE 802.15.4g compatible CRC<br>
+ //!< 5: IEEE 802.15.4g compatible whitener and 32-bit CRC<br>
+ //!< 6: No whitener, dynamically IEEE 802.15.4g compatible 16-bit or 32-bit CRC<br>
+ //!< 7: Dynamically IEEE 802.15.4g compatible whitener and 16-bit or 32-bit CRC
+ } formatConf;
+ struct {
+ uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode<br>
+ //!< 0x01: Single-ended mode RFP<br>
+ //!< 0x02: Single-ended mode RFN<br>
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)<br>
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)<br>
+ //!< Others: <i>Reserved</i>
+ uint16_t biasMode:1; //!< \brief 0: Internal bias<br>
+ //!< 1: External bias
+ uint16_t analogCfgMode:6; //!< \brief 0x00: Write analog configuration.<br>
+ //!< Required first time after boot and when changing frequency band
+ //!< or front-end configuration<br>
+ //!< 0x2D: Keep analog configuration.<br>
+ //!< May be used after standby or when changing mode with the same frequency
+ //!< band and front-end configuration<br>
+ //!< Others: <i>Reserved</i>
+ uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth<br>
+ //!< 1: Do not power up frequency synth
+ } config; //!< Configuration options
+ uint16_t txPower; //!< Transmit power
+ uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no
+ //!< override is used.
+ uint16_t centerFreq; //!< \brief Center frequency of the frequency band used, in MHz; used for calculating some internal TX and RX parameters.
+ //!< For a single channel RF system, this should be set equal to the RF frequency used.
+ //!< For a multi channel RF system (e.g. frequency hopping spread spectrum), this should be set equal
+ //!< to the center frequency of the frequency band used.
+ int16_t intFreq; //!< \brief Intermediate frequency to use for RX, in MHz on 4.12 signed format. TX will use same
+ //!< intermediate frequency if supported, otherwise 0.<br>
+ //!< 0x8000: Use default.
+ uint8_t loDivider; //!< LO frequency divider setting to use. Supported values: 0, 2, 4, 5, 6, 10, 12, 15, and 30
+ uint8_t __dummy0;
+ uint16_t __dummy1;
+ uint32_t* pRegOverrideTxStd; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to
+ //!< standard PA. Used by RF driver only, not radio CPU.
+ uint32_t* pRegOverrideTx20; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to
+ //!< 20-dBm PA. Used by RF driver only, not radio CPU.
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_PROP_SET_LEN
+//! @{
+#define CMD_PROP_SET_LEN 0x3401
+//! Set Packet Length Command
+struct __RFC_STRUCT rfc_CMD_PROP_SET_LEN_s {
+ uint16_t commandNo; //!< The command ID number 0x3401
+ uint16_t rxLen; //!< Payload length to use
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup CMD_PROP_RESTART_RX
+//! @{
+#define CMD_PROP_RESTART_RX 0x3402
+//! Restart Packet Command
+struct __RFC_STRUCT rfc_CMD_PROP_RESTART_RX_s {
+ uint16_t commandNo; //!< The command ID number 0x3402
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup propRxOutput
+//! @{
+//! Output structure for RX operations
+
+struct __RFC_STRUCT rfc_propRxOutput_s {
+ uint16_t nRxOk; //!< Number of packets that have been received with payload, CRC OK and not ignored
+ uint16_t nRxNok; //!< Number of packets that have been received with CRC error
+ uint8_t nRxIgnored; //!< Number of packets that have been received with CRC OK and ignored due to address mismatch
+ uint8_t nRxStopped; //!< Number of packets not received due to illegal length or address mismatch with pktConf.filterOp = 1
+ uint8_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space
+ int8_t lastRssi; //!< RSSI of last received packet
+ ratmr_t timeStamp; //!< Time stamp of last received packet
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! \addtogroup propRxStatus
+//! @{
+//! Receive status byte that may be appended to message in receive buffer
+
+struct __RFC_STRUCT rfc_propRxStatus_s {
+ struct {
+ uint8_t addressInd:5; //!< Index of address found (0 if not applicable)
+ uint8_t syncWordId:1; //!< 0 for primary sync word, 1 for alternate sync word
+ uint8_t result:2; //!< \brief 0: Packet received correctly, not ignored<br>
+ //!< 1: Packet received with CRC error<br>
+ //!< 2: Packet received correctly, but can be ignored<br>
+ //!< 3: Packet reception was aborted
+ } status;
+} __RFC_STRUCT_ATTR;
+
+//! @}
+
+//! @}
+//! @}
+#endif
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_prop_mailbox.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_prop_mailbox.h
new file mode 100644
index 0000000..6819d8c
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_prop_mailbox.h
@@ -0,0 +1,71 @@
+/******************************************************************************
+* Filename: rf_prop_mailbox.h
+* Revised: 2018-01-15 15:58:36 +0100 (Mon, 15 Jan 2018)
+* Revision: 18171
+*
+* Description: Definitions for proprietary mode radio interface
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef _PROP_MAILBOX_H
+#define _PROP_MAILBOX_H
+
+/// \name Radio operation status
+///@{
+/// \name Operation finished normally
+///@{
+#define PROP_DONE_OK 0x3400 ///< Operation ended normally
+#define PROP_DONE_RXTIMEOUT 0x3401 ///< Operation stopped after end trigger while waiting for sync
+#define PROP_DONE_BREAK 0x3402 ///< Rx stopped due to timeout in the middle of a packet
+#define PROP_DONE_ENDED 0x3403 ///< Operation stopped after end trigger during reception
+#define PROP_DONE_STOPPED 0x3404 ///< Operation stopped after stop command
+#define PROP_DONE_ABORT 0x3405 ///< Operation aborted by abort command
+#define PROP_DONE_RXERR 0x3406 ///< Operation ended after receiving packet with CRC error
+#define PROP_DONE_IDLE 0x3407 ///< Carrier sense operation ended because of idle channel
+#define PROP_DONE_BUSY 0x3408 ///< Carrier sense operation ended because of busy channel
+#define PROP_DONE_IDLETIMEOUT 0x3409 ///< Carrier sense operation ended because of timeout with csConf.timeoutRes = 1
+#define PROP_DONE_BUSYTIMEOUT 0x340A ///< Carrier sense operation ended because of timeout with csConf.timeoutRes = 0
+
+///@}
+/// \name Operation finished with error
+///@{
+#define PROP_ERROR_PAR 0x3800 ///< Illegal parameter
+#define PROP_ERROR_RXBUF 0x3801 ///< No available Rx buffer at the start of a packet
+#define PROP_ERROR_RXFULL 0x3802 ///< Out of Rx buffer during reception in a partial read buffer
+#define PROP_ERROR_NO_SETUP 0x3803 ///< Radio was not set up in proprietary mode
+#define PROP_ERROR_NO_FS 0x3804 ///< Synth was not programmed when running Rx or Tx
+#define PROP_ERROR_RXOVF 0x3805 ///< Rx overflow observed during operation
+#define PROP_ERROR_TXUNF 0x3806 ///< Tx underflow observed during operation
+///@}
+///@}
+
+#endif
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rfc.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rfc.c
new file mode 100644
index 0000000..4747685
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rfc.c
@@ -0,0 +1,295 @@
+/******************************************************************************
+* Filename: rfc.c
+* Revised: 2018-08-08 11:04:37 +0200 (Wed, 08 Aug 2018)
+* Revision: 52334
+*
+* Description: Driver for the RF Core.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "rfc.h"
+#include "rf_mailbox.h"
+#include <string.h>
+
+//*****************************************************************************
+//
+// Handle support for DriverLib in ROM:
+// This section will undo prototype renaming made in the header file
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #undef RFCCpeIntGetAndClear
+ #define RFCCpeIntGetAndClear NOROM_RFCCpeIntGetAndClear
+ #undef RFCDoorbellSendTo
+ #define RFCDoorbellSendTo NOROM_RFCDoorbellSendTo
+ #undef RFCSynthPowerDown
+ #define RFCSynthPowerDown NOROM_RFCSynthPowerDown
+ #undef RFCCpePatchReset
+ #define RFCCpePatchReset NOROM_RFCCpePatchReset
+ #undef RFCOverrideSearch
+ #define RFCOverrideSearch NOROM_RFCOverrideSearch
+ #undef RFCOverrideUpdate
+ #define RFCOverrideUpdate NOROM_RFCOverrideUpdate
+ #undef RFCHwIntGetAndClear
+ #define RFCHwIntGetAndClear NOROM_RFCHwIntGetAndClear
+ #undef RFCAnaDivTxOverride
+ #define RFCAnaDivTxOverride NOROM_RFCAnaDivTxOverride
+#endif
+
+
+//*****************************************************************************
+//
+// Get and clear CPE interrupt flags which match the provided bitmask
+//
+//*****************************************************************************
+uint32_t
+RFCCpeIntGetAndClear(uint32_t ui32Mask)
+{
+ // Read the CPE interrupt flags which match the provided bitmask
+ uint32_t ui32Ifg = HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIFG) & ui32Mask;
+
+ // Clear the interrupt flags
+ RFCCpeIntClear(ui32Ifg);
+
+ // Return with the interrupt flags
+ return (ui32Ifg);
+}
+
+
+//*****************************************************************************
+//
+// Send a radio operation to the doorbell and wait for an acknowledgement
+//
+//*****************************************************************************
+uint32_t
+RFCDoorbellSendTo(uint32_t pOp)
+{
+ // Wait until the doorbell becomes available
+ while(HWREG(RFC_DBELL_BASE + RFC_DBELL_O_CMDR) != 0);
+ RFCAckIntClear();
+
+ // Submit the command to the CM0 through the doorbell
+ HWREG(RFC_DBELL_BASE + RFC_DBELL_O_CMDR) = pOp;
+
+ // Wait until the CM0 starts to parse the command
+ while(!HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFACKIFG));
+ RFCAckIntClear();
+
+ // Return with the content of status register
+ return(HWREG(RFC_DBELL_BASE + RFC_DBELL_O_CMDSTA));
+}
+
+
+//*****************************************************************************
+//
+// Turn off the RF synthesizer. The radio will no longer respond to commands!
+//
+//*****************************************************************************
+void
+RFCSynthPowerDown(void)
+{
+ // Definition of reserved words
+ const uint32_t RFC_RESERVED0 = 0x40046054;
+ const uint32_t RFC_RESERVED1 = 0x40046060;
+ const uint32_t RFC_RESERVED2 = 0x40046058;
+ const uint32_t RFC_RESERVED3 = 0x40044100;
+
+ // Disable CPE clock, enable FSCA clock.
+ HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = (HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN)
+ & ~RFC_PWR_PWMCLKEN_CPE_M) | RFC_PWR_PWMCLKEN_FSCA_M | RFC_PWR_PWMCLKEN_RFE_M;
+
+ HWREG(RFC_RESERVED0) = 3;
+ HWREG(RFC_RESERVED1) = 0x1030;
+ HWREG(RFC_RESERVED2) = 1;
+ HWREG(RFC_RESERVED1) = 0x50;
+ HWREG(RFC_RESERVED2) = 1;
+ HWREG(RFC_RESERVED1) = 0x650;
+ HWREG(RFC_RESERVED2) = 1;
+ HWREG(RFC_RESERVED1) = 0x10C0;
+ HWREG(RFC_RESERVED2) = 1;
+ HWREG(RFC_RESERVED3) = 1;
+}
+
+
+//*****************************************************************************
+//
+// Reset previously patched CPE RAM to a state where it can be patched again
+//
+//*****************************************************************************
+void
+RFCCpePatchReset(void)
+{
+ // Function is not complete
+}
+
+
+//*****************************************************************************
+//
+// Function to search an override list for the provided pattern within the search depth.
+//
+//*****************************************************************************
+uint8_t
+RFCOverrideSearch(const uint32_t *pOverride, const uint32_t pattern, const uint32_t mask, const uint8_t searchDepth)
+{
+ // Search from start of the override list, to look for first override entry that matches search pattern
+ uint8_t override_index;
+ for(override_index = 0; (override_index < searchDepth) && (pOverride[override_index] != END_OVERRIDE); override_index++)
+ {
+ // Compare the value to the given pattern
+ if((pOverride[override_index] & mask) == pattern)
+ {
+ // Return with the index of override in case of match
+ return override_index;
+ }
+ }
+
+ // Return with an invalid index
+ return 0xFF;
+}
+
+//*****************************************************************************
+//
+// Function to calculate the proper override run-time for the High Gain PA.
+//
+//*****************************************************************************
+uint32_t
+RFCAnaDivTxOverride(uint8_t loDivider, uint8_t frontEndMode)
+{
+ uint16_t fsOnly;
+ uint16_t txSetting;
+
+ switch (loDivider)
+ {
+ case 0: fsOnly = 0x0502;
+ break;
+ case 2:
+ fsOnly = 0x0102;
+ break;
+ case 4:
+ case 6:
+ case 12:
+ fsOnly = 0xF101;
+ break;
+ case 5:
+ case 10:
+ case 15:
+ case 30:
+ fsOnly = 0x1101;
+ break;
+ default:
+ // Error, should not occur!
+ fsOnly = 0;
+ break;
+ }
+
+ if (frontEndMode == 255)
+ {
+ // Special value meaning 20 dBm PA
+ txSetting = (fsOnly | 0x00C0) & ~0x0400;
+ }
+ else if (frontEndMode == 0)
+ {
+ // Differential
+ txSetting = fsOnly | 0x0030;
+ }
+ else if (frontEndMode & 1)
+ {
+ // Single ended on RFP
+ txSetting = fsOnly | 0x0010;
+ }
+ else
+ {
+ // Single ended on RFN
+ txSetting = fsOnly | 0x0020;
+ }
+
+ return ((((uint32_t) txSetting) << 16) | RFC_FE_OVERRIDE_ADDRESS);
+}
+
+//*****************************************************************************
+//
+// Update the override list based on values stored in FCFG1
+//
+//*****************************************************************************
+uint8_t
+RFCOverrideUpdate(rfc_radioOp_t *pOpSetup, uint32_t *pParams)
+{
+ // Function is left blank for compatibility reasons.
+ return 0;
+}
+
+
+//*****************************************************************************
+//
+// Get and clear HW interrupt flags
+//
+//*****************************************************************************
+uint32_t
+RFCHwIntGetAndClear(uint32_t ui32Mask)
+{
+ // Read the CPE interrupt flags which match the provided bitmask
+ uint32_t ui32Ifg = HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIFG) & ui32Mask;
+
+ // Clear the interupt flags
+ RFCHwIntClear(ui32Ifg);
+
+ // Return with the interrupt flags
+ return (ui32Ifg);
+}
+
+
+//*****************************************************************************
+//
+// Handle support for DriverLib in ROM:
+// This section will undo prototype renaming made in the header file
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #undef RFCCpeIntGetAndClear
+ #define RFCCpeIntGetAndClear NOROM_RFCCpeIntGetAndClear
+ #undef RFCDoorbellSendTo
+ #define RFCDoorbellSendTo NOROM_RFCDoorbellSendTo
+ #undef RFCSynthPowerDown
+ #define RFCSynthPowerDown NOROM_RFCSynthPowerDown
+ #undef RFCCpePatchReset
+ #define RFCCpePatchReset NOROM_RFCCpePatchReset
+ #undef RFCOverrideSearch
+ #define RFCOverrideSearch NOROM_RFCOverrideSearch
+ #undef RFCOverrideUpdate
+ #define RFCOverrideUpdate NOROM_RFCOverrideUpdate
+ #undef RFCHwIntGetAndClear
+ #define RFCHwIntGetAndClear NOROM_RFCHwIntGetAndClear
+ #undef RFCAnaDivTxOverride
+ #define RFCAnaDivTxOverride NOROM_RFCAnaDivTxOverride
+#endif
+
+// See rfc.h for implementation
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rfc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rfc.h
new file mode 100644
index 0000000..00d8f18
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rfc.h
@@ -0,0 +1,465 @@
+/******************************************************************************
+* Filename: rfc.h
+* Revised: 2018-08-08 14:03:25 +0200 (Wed, 08 Aug 2018)
+* Revision: 52338
+*
+* Description: Defines and prototypes for the RF Core.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup rfc_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __RFC_H__
+#define __RFC_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "../inc/hw_types.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_rfc_pwr.h"
+#include "../inc/hw_rfc_dbell.h"
+#include "../inc/hw_fcfg1.h"
+#include "../inc/hw_adi_3_refsys.h"
+#include "../inc/hw_adi.h"
+#include "rf_common_cmd.h"
+#include "rf_prop_cmd.h"
+#include "rf_ble_cmd.h"
+
+// Definition of RFTRIM container
+typedef struct {
+ uint32_t configIfAdc;
+ uint32_t configRfFrontend;
+ uint32_t configSynth;
+ uint32_t configMiscAdc;
+} rfTrim_t;
+
+// Definition of maximum search depth used by the RFCOverrideUpdate function
+#define RFC_MAX_SEARCH_DEPTH 5
+#define RFC_PA_TYPE_ADDRESS 0x21000345
+#define RFC_PA_TYPE_MASK 0x04
+#define RFC_PA_GAIN_ADDRESS 0x2100034C
+#define RFC_PA_GAIN_MASK 0x003FFFFF
+#define RFC_FE_MODE_ESCAPE_VALUE 0xFF
+#define RFC_FE_OVERRIDE_ADDRESS 0x0703
+#define RFC_FE_OVERRIDE_MASK 0x0000FFFF
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// This section renames all functions that are not "static inline", so that
+// calling these functions will default to implementation in flash. At the end
+// of this file a second renaming will change the defaults to implementation in
+// ROM for available functions.
+//
+// To force use of the implementation in flash, e.g. for debugging:
+// - Globally: Define DRIVERLIB_NOROM at project level
+// - Per function: Use prefix "NOROM_" when calling the function
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #define RFCCpeIntGetAndClear NOROM_RFCCpeIntGetAndClear
+ #define RFCDoorbellSendTo NOROM_RFCDoorbellSendTo
+ #define RFCSynthPowerDown NOROM_RFCSynthPowerDown
+ #define RFCCpePatchReset NOROM_RFCCpePatchReset
+ #define RFCOverrideSearch NOROM_RFCOverrideSearch
+ #define RFCOverrideUpdate NOROM_RFCOverrideUpdate
+ #define RFCHwIntGetAndClear NOROM_RFCHwIntGetAndClear
+ #define RFCAnaDivTxOverride NOROM_RFCAnaDivTxOverride
+#endif
+
+//*****************************************************************************
+//
+// API Functions and prototypes
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \brief Enable the RF core clocks.
+//!
+//! As soon as the RF core is started it will handle clock control
+//! autonomously. No check should be performed to check the clocks. Instead
+//! the radio can be ping'ed through the command interface.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+RFCClockEnable(void)
+{
+ // Enable basic clocks to get the CPE run
+ HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = RFC_PWR_PWMCLKEN_CPERAM
+ | RFC_PWR_PWMCLKEN_CPE
+ | RFC_PWR_PWMCLKEN_RFC;
+}
+
+
+//*****************************************************************************
+//
+//! \brief Disable the RF core clocks.
+//!
+//! As soon as the RF core is started it will handle clock control
+//! autonomously. No check should be performed to check the clocks. Instead
+//! the radio can be ping'ed through the command interface.
+//!
+//! When disabling clocks it is the programmers responsibility that the
+//! RF core clocks are safely gated. I.e. the RF core should be safely
+//! 'parked'.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+RFCClockDisable(void)
+{
+ // Disable all clocks
+ HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = 0x0;
+}
+
+
+//*****************************************************************************
+//
+//! Clear HW interrupt flags
+//
+//*****************************************************************************
+__STATIC_INLINE void
+RFCCpeIntClear(uint32_t ui32Mask)
+{
+ // Clear the masked pending interrupts.
+ HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIFG) = ~ui32Mask;
+}
+
+
+//*****************************************************************************
+//
+//! Clear CPE interrupt flags.
+//
+//*****************************************************************************
+__STATIC_INLINE void
+RFCHwIntClear(uint32_t ui32Mask)
+{
+ // Clear the masked pending interrupts.
+ HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIFG) = ~ui32Mask;
+}
+
+
+//*****************************************************************************
+//
+//! Select interrupt sources to CPE0 (assign to INT_RFC_CPE_0 interrupt vector).
+//
+//*****************************************************************************
+__STATIC_INLINE void
+RFCCpe0IntSelect(uint32_t ui32Mask)
+{
+ // Multiplex RF Core interrupts to CPE0 IRQ.
+ HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEISL) &= ~ui32Mask;
+}
+
+
+//*****************************************************************************
+//
+//! Select interrupt sources to CPE1 (assign to INT_RFC_CPE_1 interrupt vector).
+//
+//*****************************************************************************
+__STATIC_INLINE void
+RFCCpe1IntSelect(uint32_t ui32Mask)
+{
+ // Multiplex RF Core interrupts to CPE1 IRQ.
+ HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEISL) |= ui32Mask;
+}
+
+
+//*****************************************************************************
+//
+//! Enable CPEx interrupt sources.
+//
+//*****************************************************************************
+__STATIC_INLINE void
+RFCCpeIntEnable(uint32_t ui32Mask)
+{
+ // Enable CPE interrupts from RF Core.
+ HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIEN) |= ui32Mask;
+}
+
+
+//*****************************************************************************
+//
+//! Select, clear, and enable interrupt sources to CPE0.
+//
+//*****************************************************************************
+__STATIC_INLINE void
+RFCCpe0IntSelectClearEnable(uint32_t ui32Mask)
+{
+ // Multiplex RF Core interrupts to CPE0 IRQ.
+ RFCCpe0IntSelect(ui32Mask);
+
+ // Clear the masked interrupts.
+ RFCCpeIntClear(ui32Mask);
+
+ // Enable the masked interrupts.
+ RFCCpeIntEnable(ui32Mask);
+}
+
+
+//*****************************************************************************
+//
+//! Select, clear, and enable interrupt sources to CPE1.
+//
+//*****************************************************************************
+__STATIC_INLINE void
+RFCCpe1IntSelectClearEnable(uint32_t ui32Mask)
+{
+ // Multiplex RF Core interrupts to CPE1 IRQ.
+ RFCCpe1IntSelect(ui32Mask);
+
+ // Clear the masked interrupts.
+ RFCCpeIntClear(ui32Mask);
+
+ // Enable the masked interrupts.
+ RFCCpeIntEnable(ui32Mask);
+}
+
+
+//*****************************************************************************
+//
+//! Enable HW interrupt sources.
+//
+//*****************************************************************************
+__STATIC_INLINE void
+RFCHwIntEnable(uint32_t ui32Mask)
+{
+ // Enable the masked interrupts
+ HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIEN) |= ui32Mask;
+}
+
+
+//*****************************************************************************
+//
+//! Disable CPE interrupt sources.
+//
+//*****************************************************************************
+__STATIC_INLINE void
+RFCCpeIntDisable(uint32_t ui32Mask)
+{
+ // Disable the masked interrupts
+ HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIEN) &= ~ui32Mask;
+}
+
+
+//*****************************************************************************
+//
+//! Disable HW interrupt sources.
+//
+//*****************************************************************************
+__STATIC_INLINE void
+RFCHwIntDisable(uint32_t ui32Mask)
+{
+ // Disable the masked interrupts
+ HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIEN) &= ~ui32Mask;
+}
+
+
+//*****************************************************************************
+//
+//! Get and clear CPE interrupt flags.
+//
+//*****************************************************************************
+extern uint32_t RFCCpeIntGetAndClear(uint32_t ui32Mask);
+
+
+//*****************************************************************************
+//
+//! Clear ACK interrupt flag.
+//
+//*****************************************************************************
+__STATIC_INLINE void
+RFCAckIntClear(void)
+{
+ // Clear any pending interrupts.
+ HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFACKIFG) = 0x0;
+}
+
+
+//*****************************************************************************
+//
+//! Send a radio operation to the doorbell and wait for an acknowledgment.
+//
+//*****************************************************************************
+extern uint32_t RFCDoorbellSendTo(uint32_t pOp);
+
+
+//*****************************************************************************
+//
+//! This function implements a fast way to turn off the synthesizer.
+//
+//*****************************************************************************
+extern void RFCSynthPowerDown(void);
+
+
+//*****************************************************************************
+//
+//! Reset previously patched CPE RAM to a state where it can be patched again.
+//
+//*****************************************************************************
+extern void RFCCpePatchReset(void);
+
+
+//*****************************************************************************
+//
+// Function to search an override list for the provided pattern within the search depth.
+//
+//*****************************************************************************
+extern uint8_t RFCOverrideSearch(const uint32_t *pOverride, const uint32_t pattern, const uint32_t mask, const uint8_t searchDepth);
+
+
+//*****************************************************************************
+//
+//! Function to update override list
+//
+//*****************************************************************************
+extern uint8_t RFCOverrideUpdate(rfc_radioOp_t *pOpSetup, uint32_t *pParams);
+
+
+//*****************************************************************************
+//
+//! Get and clear HW interrupt flags.
+//
+//*****************************************************************************
+extern uint32_t RFCHwIntGetAndClear(uint32_t ui32Mask);
+
+
+//*****************************************************************************
+//
+//! Get the type of currently selected PA.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+RFCGetPaType(void)
+{
+ return (bool)(HWREGB(RFC_PA_TYPE_ADDRESS) & RFC_PA_TYPE_MASK);
+}
+
+//*****************************************************************************
+//
+//! Get the gain of currently selected PA.
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+RFCGetPaGain(void)
+{
+ return (HWREG(RFC_PA_GAIN_ADDRESS) & RFC_PA_GAIN_MASK);
+}
+
+
+//*****************************************************************************
+//
+//! Function to calculate the proper override run-time for the High Gain PA.
+//
+//*****************************************************************************
+extern uint32_t RFCAnaDivTxOverride(uint8_t loDivider, uint8_t frontEndMode);
+
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// Redirect to implementation in ROM when available.
+//
+//*****************************************************************************
+#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
+ #include "../driverlib/rom.h"
+ #ifdef ROM_RFCCpeIntGetAndClear
+ #undef RFCCpeIntGetAndClear
+ #define RFCCpeIntGetAndClear ROM_RFCCpeIntGetAndClear
+ #endif
+ #ifdef ROM_RFCDoorbellSendTo
+ #undef RFCDoorbellSendTo
+ #define RFCDoorbellSendTo ROM_RFCDoorbellSendTo
+ #endif
+ #ifdef ROM_RFCSynthPowerDown
+ #undef RFCSynthPowerDown
+ #define RFCSynthPowerDown ROM_RFCSynthPowerDown
+ #endif
+ #ifdef ROM_RFCCpePatchReset
+ #undef RFCCpePatchReset
+ #define RFCCpePatchReset ROM_RFCCpePatchReset
+ #endif
+ #ifdef ROM_RFCOverrideSearch
+ #undef RFCOverrideSearch
+ #define RFCOverrideSearch ROM_RFCOverrideSearch
+ #endif
+ #ifdef ROM_RFCOverrideUpdate
+ #undef RFCOverrideUpdate
+ #define RFCOverrideUpdate ROM_RFCOverrideUpdate
+ #endif
+ #ifdef ROM_RFCHwIntGetAndClear
+ #undef RFCHwIntGetAndClear
+ #define RFCHwIntGetAndClear ROM_RFCHwIntGetAndClear
+ #endif
+ #ifdef ROM_RFCAnaDivTxOverride
+ #undef RFCAnaDivTxOverride
+ #define RFCAnaDivTxOverride ROM_RFCAnaDivTxOverride
+ #endif
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __RFC_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rom.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rom.h
new file mode 100644
index 0000000..fc79556
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rom.h
@@ -0,0 +1,1055 @@
+/******************************************************************************
+* Filename: rom.h
+* Revised: 2018-11-02 13:54:49 +0100 (Fri, 02 Nov 2018)
+* Revision: 53196
+*
+* Description: Prototypes for the ROM utility functions.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __ROM_H__
+#define __ROM_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "../inc/hw_types.h"
+
+#ifndef __HAPI_H__
+#define __HAPI_H__
+
+// Start address of the ROM hard API access table (located after the ROM FW rev field)
+#define ROM_HAPI_TABLE_ADDR 0x10000048
+
+// ROM Hard-API function interface types
+typedef uint32_t (* FPTR_CRC32_T) ( uint8_t* /* pui8Data */,\
+ uint32_t /* ui32ByteCount */,\
+ uint32_t /* ui32RepeatCount */);
+
+typedef uint32_t (* FPTR_GETFLSIZE_T) ( void );
+
+typedef uint32_t (* FPTR_GETCHIPID_T) ( void );
+
+typedef uint32_t (* FPTR_RESERVED1_T) ( uint32_t );
+
+typedef uint32_t (* FPTR_RESERVED2_T) ( void );
+
+typedef uint32_t (* FPTR_RESERVED3_T) ( uint8_t* ,\
+ uint32_t ,\
+ uint32_t );
+typedef void (* FPTR_RESETDEV_T) ( void );
+
+typedef uint32_t (* FPTR_FLETCHER32_T) ( uint16_t* /* pui16Data */,\
+ uint16_t /* ui16WordCount */,\
+ uint16_t /* ui16RepeatCount */);
+
+typedef uint32_t (* FPTR_MINVAL_T) ( uint32_t* /* ulpDataBuffer */,\
+ uint32_t /* ui32DataCount */);
+
+typedef uint32_t (* FPTR_MAXVAL_T) ( uint32_t* /* pui32DataBuffer */,\
+ uint32_t /* ui32DataCount */);
+
+typedef uint32_t (* FPTR_MEANVAL_T) ( uint32_t* /* pui32DataBuffer */,\
+ uint32_t /* ui32DataCount */);
+
+typedef uint32_t (* FPTR_STDDVAL_T) ( uint32_t* /* pui32DataBuffer */,\
+ uint32_t /* ui32DataCount */);
+
+typedef void (* FPTR_HFSOURCESAFESWITCH_T) ( void );
+
+typedef void (* FPTR_RESERVED4_T) ( uint32_t );
+
+typedef void (* FPTR_RESERVED5_T) ( uint32_t );
+
+typedef void (* FPTR_COMPAIN_T) ( uint8_t /* ut8Signal */);
+
+typedef void (* FPTR_COMPAREF_T) ( uint8_t /* ut8Signal */);
+
+typedef void (* FPTR_ADCCOMPBIN_T) ( uint8_t /* ut8Signal */);
+
+typedef void (* FPTR_DACVREF_T) ( uint8_t /* ut8Signal */);
+
+extern uint32_t MemBusWrkAroundHapiProgramFlash(uint8_t *pui8DataBuffer,
+ uint32_t ui32Address,
+ uint32_t ui32Count);
+
+extern uint32_t MemBusWrkAroundHapiEraseSector(uint32_t ui32Address);
+
+// ROM Hard-API access table type
+typedef struct
+{
+ FPTR_CRC32_T Crc32;
+ FPTR_GETFLSIZE_T FlashGetSize;
+ FPTR_GETCHIPID_T GetChipId;
+ FPTR_RESERVED1_T ReservedLocation1;
+ FPTR_RESERVED2_T ReservedLocation2;
+ FPTR_RESERVED3_T ReservedLocation3;
+ FPTR_RESETDEV_T ResetDevice;
+ FPTR_FLETCHER32_T Fletcher32;
+ FPTR_MINVAL_T MinValue;
+ FPTR_MAXVAL_T MaxValue;
+ FPTR_MEANVAL_T MeanValue;
+ FPTR_STDDVAL_T StandDeviationValue;
+ FPTR_RESERVED4_T ReservedLocation4;
+ FPTR_RESERVED5_T ReservedLocation5;
+ FPTR_HFSOURCESAFESWITCH_T HFSourceSafeSwitch;
+ FPTR_COMPAIN_T SelectCompAInput;
+ FPTR_COMPAREF_T SelectCompARef;
+ FPTR_ADCCOMPBIN_T SelectADCCompBInput;
+ FPTR_DACVREF_T SelectDACVref;
+} HARD_API_T;
+
+// Pointer to the ROM HAPI table
+#define P_HARD_API ((HARD_API_T*) ROM_HAPI_TABLE_ADDR)
+
+#define HapiCrc32(a,b,c) P_HARD_API->Crc32(a,b,c)
+#define HapiGetFlashSize() P_HARD_API->FlashGetSize()
+#define HapiGetChipId() P_HARD_API->GetChipId()
+#define HapiSectorErase(a) MemBusWrkAroundHapiEraseSector(a)
+#define HapiProgramFlash(a,b,c) MemBusWrkAroundHapiProgramFlash(a,b,c)
+#define HapiResetDevice() P_HARD_API->ResetDevice()
+#define HapiFletcher32(a,b,c) P_HARD_API->Fletcher32(a,b,c)
+#define HapiMinValue(a,b) P_HARD_API->MinValue(a,b)
+#define HapiMaxValue(a,b) P_HARD_API->MaxValue(a,b)
+#define HapiMeanValue(a,b) P_HARD_API->MeanValue(a,b)
+#define HapiStandDeviationValue(a,b) P_HARD_API->StandDeviationValue(a,b)
+#define HapiHFSourceSafeSwitch() P_HARD_API->HFSourceSafeSwitch()
+#define HapiSelectCompAInput(a) P_HARD_API->SelectCompAInput(a)
+#define HapiSelectCompARef(a) P_HARD_API->SelectCompARef(a)
+#define HapiSelectADCCompBInput(a) P_HARD_API->SelectADCCompBInput(a)
+#define HapiSelectDACVref(a) P_HARD_API->SelectDACVref(a)
+
+// Defines for input parameter to the HapiSelectCompAInput function.
+#define COMPA_IN_NC 0x00
+// Defines used in CC13x0/CC26x0 devices
+#define COMPA_IN_AUXIO7 0x09
+#define COMPA_IN_AUXIO6 0x0A
+#define COMPA_IN_AUXIO5 0x0B
+#define COMPA_IN_AUXIO4 0x0C
+#define COMPA_IN_AUXIO3 0x0D
+#define COMPA_IN_AUXIO2 0x0E
+#define COMPA_IN_AUXIO1 0x0F
+#define COMPA_IN_AUXIO0 0x10
+// Defines used in CC13x2/CC26x2 devices
+#define COMPA_IN_AUXIO26 COMPA_IN_AUXIO7
+#define COMPA_IN_AUXIO25 COMPA_IN_AUXIO6
+#define COMPA_IN_AUXIO24 COMPA_IN_AUXIO5
+#define COMPA_IN_AUXIO23 COMPA_IN_AUXIO4
+#define COMPA_IN_AUXIO22 COMPA_IN_AUXIO3
+#define COMPA_IN_AUXIO21 COMPA_IN_AUXIO2
+#define COMPA_IN_AUXIO20 COMPA_IN_AUXIO1
+#define COMPA_IN_AUXIO19 COMPA_IN_AUXIO0
+
+// Defines for input parameter to the HapiSelectCompARef function.
+#define COMPA_REF_NC 0x00
+#define COMPA_REF_DCOUPL 0x01
+#define COMPA_REF_VSS 0x02
+#define COMPA_REF_VDDS 0x03
+#define COMPA_REF_ADCVREFP 0x04
+// Defines used in CC13x0/CC26x0 devices
+#define COMPA_REF_AUXIO7 0x09
+#define COMPA_REF_AUXIO6 0x0A
+#define COMPA_REF_AUXIO5 0x0B
+#define COMPA_REF_AUXIO4 0x0C
+#define COMPA_REF_AUXIO3 0x0D
+#define COMPA_REF_AUXIO2 0x0E
+#define COMPA_REF_AUXIO1 0x0F
+#define COMPA_REF_AUXIO0 0x10
+// Defines used in CC13x2/CC26x2 devices
+#define COMPA_REF_AUXIO26 COMPA_REF_AUXIO7
+#define COMPA_REF_AUXIO25 COMPA_REF_AUXIO6
+#define COMPA_REF_AUXIO24 COMPA_REF_AUXIO5
+#define COMPA_REF_AUXIO23 COMPA_REF_AUXIO4
+#define COMPA_REF_AUXIO22 COMPA_REF_AUXIO3
+#define COMPA_REF_AUXIO21 COMPA_REF_AUXIO2
+#define COMPA_REF_AUXIO20 COMPA_REF_AUXIO1
+#define COMPA_REF_AUXIO19 COMPA_REF_AUXIO0
+
+// Defines for input parameter to the HapiSelectADCCompBInput function.
+#define ADC_COMPB_IN_NC 0x00
+#define ADC_COMPB_IN_DCOUPL 0x03
+#define ADC_COMPB_IN_VSS 0x04
+#define ADC_COMPB_IN_VDDS 0x05
+// Defines used in CC13x0/CC26x0 devices
+#define ADC_COMPB_IN_AUXIO7 0x09
+#define ADC_COMPB_IN_AUXIO6 0x0A
+#define ADC_COMPB_IN_AUXIO5 0x0B
+#define ADC_COMPB_IN_AUXIO4 0x0C
+#define ADC_COMPB_IN_AUXIO3 0x0D
+#define ADC_COMPB_IN_AUXIO2 0x0E
+#define ADC_COMPB_IN_AUXIO1 0x0F
+#define ADC_COMPB_IN_AUXIO0 0x10
+// Defines used in CC13x2/CC26x2 devices
+#define ADC_COMPB_IN_AUXIO26 ADC_COMPB_IN_AUXIO7
+#define ADC_COMPB_IN_AUXIO25 ADC_COMPB_IN_AUXIO6
+#define ADC_COMPB_IN_AUXIO24 ADC_COMPB_IN_AUXIO5
+#define ADC_COMPB_IN_AUXIO23 ADC_COMPB_IN_AUXIO4
+#define ADC_COMPB_IN_AUXIO22 ADC_COMPB_IN_AUXIO3
+#define ADC_COMPB_IN_AUXIO21 ADC_COMPB_IN_AUXIO2
+#define ADC_COMPB_IN_AUXIO20 ADC_COMPB_IN_AUXIO1
+#define ADC_COMPB_IN_AUXIO19 ADC_COMPB_IN_AUXIO0
+
+// Defines for input parameter to the HapiSelectDACVref function.
+// The define values can not be changed!
+#define DAC_REF_NC 0x00
+#define DAC_REF_DCOUPL 0x01
+#define DAC_REF_VSS 0x02
+#define DAC_REF_VDDS 0x03
+
+#endif // __HAPI_H__
+
+//*****************************************************************************
+//
+// Pointers to the main API tables.
+//
+//*****************************************************************************
+#define ROM_API_TABLE ((uint32_t *) 0x10000180)
+#define ROM_VERSION (ROM_API_TABLE[0])
+
+
+#define ROM_API_AON_EVENT_TABLE ((uint32_t*) (ROM_API_TABLE[1]))
+#define ROM_API_AON_IOC_TABLE ((uint32_t*) (ROM_API_TABLE[2]))
+#define ROM_API_AON_RTC_TABLE ((uint32_t*) (ROM_API_TABLE[3]))
+#define ROM_API_AUX_CTRL_TABLE ((uint32_t*) (ROM_API_TABLE[5]))
+#define ROM_API_AUX_TDC_TABLE ((uint32_t*) (ROM_API_TABLE[6]))
+#define ROM_API_DDI_TABLE ((uint32_t*) (ROM_API_TABLE[9]))
+#define ROM_API_FLASH_TABLE ((uint32_t*) (ROM_API_TABLE[10]))
+#define ROM_API_I2C_TABLE ((uint32_t*) (ROM_API_TABLE[11]))
+#define ROM_API_INTERRUPT_TABLE ((uint32_t*) (ROM_API_TABLE[12]))
+#define ROM_API_IOC_TABLE ((uint32_t*) (ROM_API_TABLE[13]))
+#define ROM_API_PRCM_TABLE ((uint32_t*) (ROM_API_TABLE[14]))
+#define ROM_API_SMPH_TABLE ((uint32_t*) (ROM_API_TABLE[15]))
+#define ROM_API_SSI_TABLE ((uint32_t*) (ROM_API_TABLE[17]))
+#define ROM_API_TIMER_TABLE ((uint32_t*) (ROM_API_TABLE[18]))
+#define ROM_API_TRNG_TABLE ((uint32_t*) (ROM_API_TABLE[19]))
+#define ROM_API_UART_TABLE ((uint32_t*) (ROM_API_TABLE[20]))
+#define ROM_API_UDMA_TABLE ((uint32_t*) (ROM_API_TABLE[21]))
+#define ROM_API_VIMS_TABLE ((uint32_t*) (ROM_API_TABLE[22]))
+#define ROM_API_CRYPTO_TABLE ((uint32_t*) (ROM_API_TABLE[23]))
+#define ROM_API_OSC_TABLE ((uint32_t*) (ROM_API_TABLE[24]))
+#define ROM_API_AUX_ADC_TABLE ((uint32_t*) (ROM_API_TABLE[25]))
+#define ROM_API_SYS_CTRL_TABLE ((uint32_t*) (ROM_API_TABLE[26]))
+#define ROM_API_AON_BATMON_TABLE ((uint32_t*) (ROM_API_TABLE[27]))
+#define ROM_API_SETUP_ROM_TABLE ((uint32_t*) (ROM_API_TABLE[28]))
+#define ROM_API_I2S_TABLE ((uint32_t*) (ROM_API_TABLE[29]))
+#define ROM_API_PWR_CTRL_TABLE ((uint32_t*) (ROM_API_TABLE[30]))
+#define ROM_API_AES_TABLE ((uint32_t*) (ROM_API_TABLE[31]))
+#define ROM_API_PKA_TABLE ((uint32_t*) (ROM_API_TABLE[32]))
+#define ROM_API_SHA2_TABLE ((uint32_t*) (ROM_API_TABLE[33]))
+
+// AON_EVENT FUNCTIONS
+#define ROM_AONEventMcuWakeUpSet \
+ ((void (*)(uint32_t ui32MCUWUEvent, uint32_t ui32EventSrc)) \
+ ROM_API_AON_EVENT_TABLE[0])
+
+#define ROM_AONEventMcuWakeUpGet \
+ ((uint32_t (*)(uint32_t ui32MCUWUEvent)) \
+ ROM_API_AON_EVENT_TABLE[1])
+
+#define ROM_AONEventMcuSet \
+ ((void (*)(uint32_t ui32MCUEvent, uint32_t ui32EventSrc)) \
+ ROM_API_AON_EVENT_TABLE[4])
+
+#define ROM_AONEventMcuGet \
+ ((uint32_t (*)(uint32_t ui32MCUEvent)) \
+ ROM_API_AON_EVENT_TABLE[5])
+
+
+// AON_RTC FUNCTIONS
+#define ROM_AONRTCCurrent64BitValueGet \
+ ((uint64_t (*)(void)) \
+ ROM_API_AON_RTC_TABLE[12])
+
+
+// AUX_TDC FUNCTIONS
+#define ROM_AUXTDCConfigSet \
+ ((void (*)(uint32_t ui32Base, uint32_t ui32StartCondition, uint32_t ui32StopCondition)) \
+ ROM_API_AUX_TDC_TABLE[0])
+
+#define ROM_AUXTDCMeasurementDone \
+ ((uint32_t (*)(uint32_t ui32Base)) \
+ ROM_API_AUX_TDC_TABLE[1])
+
+
+// DDI FUNCTIONS
+#define ROM_DDI16BitWrite \
+ ((void (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32WrData)) \
+ ROM_API_DDI_TABLE[0])
+
+#define ROM_DDI16BitfieldWrite \
+ ((void (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32Shift, uint16_t ui32Data)) \
+ ROM_API_DDI_TABLE[1])
+
+#define ROM_DDI16BitRead \
+ ((uint16_t (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask)) \
+ ROM_API_DDI_TABLE[2])
+
+#define ROM_DDI16BitfieldRead \
+ ((uint16_t (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32Shift)) \
+ ROM_API_DDI_TABLE[3])
+
+#define ROM_DDI32RegWrite \
+ ((void (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val)) \
+ ROM_API_DDI_TABLE[4])
+
+
+// FLASH FUNCTIONS
+#define ROM_FlashPowerModeSet \
+ ((void (*)(uint32_t ui32PowerMode, uint32_t ui32BankGracePeriod, uint32_t ui32PumpGracePeriod)) \
+ ROM_API_FLASH_TABLE[0])
+
+#define ROM_FlashPowerModeGet \
+ ((uint32_t (*)(void)) \
+ ROM_API_FLASH_TABLE[1])
+
+#define ROM_FlashProtectionSet \
+ ((void (*)(uint32_t ui32SectorAddress, uint32_t ui32ProtectMode)) \
+ ROM_API_FLASH_TABLE[2])
+
+#define ROM_FlashProtectionGet \
+ ((uint32_t (*)(uint32_t ui32SectorAddress)) \
+ ROM_API_FLASH_TABLE[3])
+
+#define ROM_FlashProtectionSave \
+ ((uint32_t (*)(uint32_t ui32SectorAddress)) \
+ ROM_API_FLASH_TABLE[4])
+
+#define ROM_FlashEfuseReadRow \
+ ((bool (*)(uint32_t *pui32EfuseData, uint32_t ui32RowAddress)) \
+ ROM_API_FLASH_TABLE[8])
+
+#define ROM_FlashDisableSectorsForWrite \
+ ((void (*)(void)) \
+ ROM_API_FLASH_TABLE[9])
+
+
+// I2C FUNCTIONS
+#define ROM_I2CMasterInitExpClk \
+ ((void (*)(uint32_t ui32Base, uint32_t ui32I2CClk, bool bFast)) \
+ ROM_API_I2C_TABLE[0])
+
+#define ROM_I2CMasterErr \
+ ((uint32_t (*)(uint32_t ui32Base)) \
+ ROM_API_I2C_TABLE[1])
+
+
+// INTERRUPT FUNCTIONS
+#define ROM_IntPriorityGroupingSet \
+ ((void (*)(uint32_t ui32Bits)) \
+ ROM_API_INTERRUPT_TABLE[0])
+
+#define ROM_IntPriorityGroupingGet \
+ ((uint32_t (*)(void)) \
+ ROM_API_INTERRUPT_TABLE[1])
+
+#define ROM_IntPrioritySet \
+ ((void (*)(uint32_t ui32Interrupt, uint8_t ui8Priority)) \
+ ROM_API_INTERRUPT_TABLE[2])
+
+#define ROM_IntPriorityGet \
+ ((int32_t (*)(uint32_t ui32Interrupt)) \
+ ROM_API_INTERRUPT_TABLE[3])
+
+#define ROM_IntEnable \
+ ((void (*)(uint32_t ui32Interrupt)) \
+ ROM_API_INTERRUPT_TABLE[4])
+
+#define ROM_IntDisable \
+ ((void (*)(uint32_t ui32Interrupt)) \
+ ROM_API_INTERRUPT_TABLE[5])
+
+#define ROM_IntPendSet \
+ ((void (*)(uint32_t ui32Interrupt)) \
+ ROM_API_INTERRUPT_TABLE[6])
+
+#define ROM_IntPendGet \
+ ((bool (*)(uint32_t ui32Interrupt)) \
+ ROM_API_INTERRUPT_TABLE[7])
+
+#define ROM_IntPendClear \
+ ((void (*)(uint32_t ui32Interrupt)) \
+ ROM_API_INTERRUPT_TABLE[8])
+
+
+// IOC FUNCTIONS
+#define ROM_IOCPortConfigureSet \
+ ((void (*)(uint32_t ui32IOId, uint32_t ui32PortId, uint32_t ui32IOConfig)) \
+ ROM_API_IOC_TABLE[0])
+
+#define ROM_IOCPortConfigureGet \
+ ((uint32_t (*)(uint32_t ui32IOId)) \
+ ROM_API_IOC_TABLE[1])
+
+#define ROM_IOCIOShutdownSet \
+ ((void (*)(uint32_t ui32IOId, uint32_t ui32IOShutdown)) \
+ ROM_API_IOC_TABLE[2])
+
+#define ROM_IOCIOModeSet \
+ ((void (*)(uint32_t ui32IOId, uint32_t ui32IOMode)) \
+ ROM_API_IOC_TABLE[4])
+
+#define ROM_IOCIOIntSet \
+ ((void (*)(uint32_t ui32IOId, uint32_t ui32Int, uint32_t ui32EdgeDet)) \
+ ROM_API_IOC_TABLE[5])
+
+#define ROM_IOCIOPortPullSet \
+ ((void (*)(uint32_t ui32IOId, uint32_t ui32Pull)) \
+ ROM_API_IOC_TABLE[6])
+
+#define ROM_IOCIOHystSet \
+ ((void (*)(uint32_t ui32IOId, uint32_t ui32Hysteresis)) \
+ ROM_API_IOC_TABLE[7])
+
+#define ROM_IOCIOInputSet \
+ ((void (*)(uint32_t ui32IOId, uint32_t ui32Input)) \
+ ROM_API_IOC_TABLE[8])
+
+#define ROM_IOCIOSlewCtrlSet \
+ ((void (*)(uint32_t ui32IOId, uint32_t ui32SlewEnable)) \
+ ROM_API_IOC_TABLE[9])
+
+#define ROM_IOCIODrvStrengthSet \
+ ((void (*)(uint32_t ui32IOId, uint32_t ui32IOCurrent, uint32_t ui32DrvStrength)) \
+ ROM_API_IOC_TABLE[10])
+
+#define ROM_IOCIOPortIdSet \
+ ((void (*)(uint32_t ui32IOId, uint32_t ui32PortId)) \
+ ROM_API_IOC_TABLE[11])
+
+#define ROM_IOCIntEnable \
+ ((void (*)(uint32_t ui32IOId)) \
+ ROM_API_IOC_TABLE[12])
+
+#define ROM_IOCIntDisable \
+ ((void (*)(uint32_t ui32IOId)) \
+ ROM_API_IOC_TABLE[13])
+
+#define ROM_IOCPinTypeGpioInput \
+ ((void (*)(uint32_t ui32IOId)) \
+ ROM_API_IOC_TABLE[14])
+
+#define ROM_IOCPinTypeGpioOutput \
+ ((void (*)(uint32_t ui32IOId)) \
+ ROM_API_IOC_TABLE[15])
+
+#define ROM_IOCPinTypeUart \
+ ((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Cts, uint32_t ui32Rts)) \
+ ROM_API_IOC_TABLE[16])
+
+#define ROM_IOCPinTypeSsiMaster \
+ ((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Fss, uint32_t ui32Clk)) \
+ ROM_API_IOC_TABLE[17])
+
+#define ROM_IOCPinTypeSsiSlave \
+ ((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Fss, uint32_t ui32Clk)) \
+ ROM_API_IOC_TABLE[18])
+
+#define ROM_IOCPinTypeI2c \
+ ((void (*)(uint32_t ui32Base, uint32_t ui32Data, uint32_t ui32Clk)) \
+ ROM_API_IOC_TABLE[19])
+
+#define ROM_IOCPinTypeAux \
+ ((void (*)(uint32_t ui32IOId)) \
+ ROM_API_IOC_TABLE[21])
+
+
+// PRCM FUNCTIONS
+#define ROM_PRCMInfClockConfigureSet \
+ ((void (*)(uint32_t ui32ClkDiv, uint32_t ui32PowerMode)) \
+ ROM_API_PRCM_TABLE[0])
+
+#define ROM_PRCMInfClockConfigureGet \
+ ((uint32_t (*)(uint32_t ui32PowerMode)) \
+ ROM_API_PRCM_TABLE[1])
+
+#define ROM_PRCMAudioClockConfigSet \
+ ((void (*)(uint32_t ui32ClkConfig, uint32_t ui32SampleRate)) \
+ ROM_API_PRCM_TABLE[4])
+
+#define ROM_PRCMPowerDomainOn \
+ ((void (*)(uint32_t ui32Domains)) \
+ ROM_API_PRCM_TABLE[5])
+
+#define ROM_PRCMPowerDomainOff \
+ ((void (*)(uint32_t ui32Domains)) \
+ ROM_API_PRCM_TABLE[6])
+
+#define ROM_PRCMPeripheralRunEnable \
+ ((void (*)(uint32_t ui32Peripheral)) \
+ ROM_API_PRCM_TABLE[7])
+
+#define ROM_PRCMPeripheralRunDisable \
+ ((void (*)(uint32_t ui32Peripheral)) \
+ ROM_API_PRCM_TABLE[8])
+
+#define ROM_PRCMPeripheralSleepEnable \
+ ((void (*)(uint32_t ui32Peripheral)) \
+ ROM_API_PRCM_TABLE[9])
+
+#define ROM_PRCMPeripheralSleepDisable \
+ ((void (*)(uint32_t ui32Peripheral)) \
+ ROM_API_PRCM_TABLE[10])
+
+#define ROM_PRCMPeripheralDeepSleepEnable \
+ ((void (*)(uint32_t ui32Peripheral)) \
+ ROM_API_PRCM_TABLE[11])
+
+#define ROM_PRCMPeripheralDeepSleepDisable \
+ ((void (*)(uint32_t ui32Peripheral)) \
+ ROM_API_PRCM_TABLE[12])
+
+#define ROM_PRCMPowerDomainStatus \
+ ((uint32_t (*)(uint32_t ui32Domains)) \
+ ROM_API_PRCM_TABLE[13])
+
+#define ROM_PRCMDeepSleep \
+ ((void (*)(void)) \
+ ROM_API_PRCM_TABLE[14])
+
+#define ROM_PRCMAudioClockConfigSetOverride \
+ ((void (*)(uint32_t ui32ClkConfig, uint32_t ui32MstDiv, uint32_t ui32BitDiv, uint32_t ui32WordDiv)) \
+ ROM_API_PRCM_TABLE[17])
+
+
+// SMPH FUNCTIONS
+#define ROM_SMPHAcquire \
+ ((void (*)(uint32_t ui32Semaphore)) \
+ ROM_API_SMPH_TABLE[0])
+
+
+// SSI FUNCTIONS
+#define ROM_SSIConfigSetExpClk \
+ ((void (*)(uint32_t ui32Base, uint32_t ui32SSIClk, uint32_t ui32Protocol, uint32_t ui32Mode, uint32_t ui32BitRate, uint32_t ui32DataWidth)) \
+ ROM_API_SSI_TABLE[0])
+
+#define ROM_SSIDataPut \
+ ((void (*)(uint32_t ui32Base, uint32_t ui32Data)) \
+ ROM_API_SSI_TABLE[1])
+
+#define ROM_SSIDataPutNonBlocking \
+ ((int32_t (*)(uint32_t ui32Base, uint32_t ui32Data)) \
+ ROM_API_SSI_TABLE[2])
+
+#define ROM_SSIDataGet \
+ ((void (*)(uint32_t ui32Base, uint32_t *pui32Data)) \
+ ROM_API_SSI_TABLE[3])
+
+#define ROM_SSIDataGetNonBlocking \
+ ((int32_t (*)(uint32_t ui32Base, uint32_t *pui32Data)) \
+ ROM_API_SSI_TABLE[4])
+
+
+// TIMER FUNCTIONS
+#define ROM_TimerConfigure \
+ ((void (*)(uint32_t ui32Base, uint32_t ui32Config)) \
+ ROM_API_TIMER_TABLE[0])
+
+#define ROM_TimerLevelControl \
+ ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bInvert)) \
+ ROM_API_TIMER_TABLE[1])
+
+#define ROM_TimerStallControl \
+ ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bStall)) \
+ ROM_API_TIMER_TABLE[3])
+
+#define ROM_TimerWaitOnTriggerControl \
+ ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bWait)) \
+ ROM_API_TIMER_TABLE[4])
+
+#define ROM_TimerIntervalLoadMode \
+ ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode)) \
+ ROM_API_TIMER_TABLE[5])
+
+#define ROM_TimerMatchUpdateMode \
+ ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode)) \
+ ROM_API_TIMER_TABLE[6])
+
+
+// TRNG FUNCTIONS
+#define ROM_TRNGConfigure \
+ ((void (*)(uint32_t ui32MinSamplesPerCycle, uint32_t ui32MaxSamplesPerCycle, uint32_t ui32ClocksPerSample)) \
+ ROM_API_TRNG_TABLE[0])
+
+#define ROM_TRNGNumberGet \
+ ((uint32_t (*)(uint32_t ui32Word)) \
+ ROM_API_TRNG_TABLE[1])
+
+
+// UART FUNCTIONS
+#define ROM_UARTFIFOLevelGet \
+ ((void (*)(uint32_t ui32Base, uint32_t *pui32TxLevel, uint32_t *pui32RxLevel)) \
+ ROM_API_UART_TABLE[0])
+
+#define ROM_UARTConfigSetExpClk \
+ ((void (*)(uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t ui32Baud, uint32_t ui32Config)) \
+ ROM_API_UART_TABLE[1])
+
+#define ROM_UARTConfigGetExpClk \
+ ((void (*)(uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t *pui32Baud, uint32_t *pui32Config)) \
+ ROM_API_UART_TABLE[2])
+
+#define ROM_UARTDisable \
+ ((void (*)(uint32_t ui32Base)) \
+ ROM_API_UART_TABLE[3])
+
+#define ROM_UARTCharGetNonBlocking \
+ ((int32_t (*)(uint32_t ui32Base)) \
+ ROM_API_UART_TABLE[4])
+
+#define ROM_UARTCharGet \
+ ((int32_t (*)(uint32_t ui32Base)) \
+ ROM_API_UART_TABLE[5])
+
+#define ROM_UARTCharPutNonBlocking \
+ ((bool (*)(uint32_t ui32Base, uint8_t ui8Data)) \
+ ROM_API_UART_TABLE[6])
+
+#define ROM_UARTCharPut \
+ ((void (*)(uint32_t ui32Base, uint8_t ui8Data)) \
+ ROM_API_UART_TABLE[7])
+
+
+// UDMA FUNCTIONS
+#define ROM_uDMAChannelAttributeEnable \
+ ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32Attr)) \
+ ROM_API_UDMA_TABLE[0])
+
+#define ROM_uDMAChannelAttributeDisable \
+ ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32Attr)) \
+ ROM_API_UDMA_TABLE[1])
+
+#define ROM_uDMAChannelAttributeGet \
+ ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelNum)) \
+ ROM_API_UDMA_TABLE[2])
+
+#define ROM_uDMAChannelControlSet \
+ ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, uint32_t ui32Control)) \
+ ROM_API_UDMA_TABLE[3])
+
+#define ROM_uDMAChannelTransferSet \
+ ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, uint32_t ui32Mode, void *pvSrcAddr, void *pvDstAddr, uint32_t ui32TransferSize)) \
+ ROM_API_UDMA_TABLE[4])
+
+#define ROM_uDMAChannelScatterGatherSet \
+ ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32TaskCount, void *pvTaskList, uint32_t ui32IsPeriphSG)) \
+ ROM_API_UDMA_TABLE[5])
+
+#define ROM_uDMAChannelSizeGet \
+ ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)) \
+ ROM_API_UDMA_TABLE[6])
+
+#define ROM_uDMAChannelModeGet \
+ ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)) \
+ ROM_API_UDMA_TABLE[7])
+
+
+// VIMS FUNCTIONS
+#define ROM_VIMSConfigure \
+ ((void (*)(uint32_t ui32Base, bool bRoundRobin, bool bPrefetch)) \
+ ROM_API_VIMS_TABLE[0])
+
+#define ROM_VIMSModeSet \
+ ((void (*)(uint32_t ui32Base, uint32_t ui32Mode)) \
+ ROM_API_VIMS_TABLE[1])
+
+#define ROM_VIMSModeGet \
+ ((uint32_t (*)(uint32_t ui32Base)) \
+ ROM_API_VIMS_TABLE[2])
+
+#define ROM_VIMSModeSafeSet \
+ ((void (*)(uint32_t ui32Base, uint32_t ui32NewMode, bool blocking)) \
+ ROM_API_VIMS_TABLE[3])
+
+
+// OSC FUNCTIONS
+#define ROM_OSCClockSourceGet \
+ ((uint32_t (*)(uint32_t ui32SrcClk)) \
+ ROM_API_OSC_TABLE[0])
+
+#define ROM_OSCClockSourceSet \
+ ((void (*)(uint32_t ui32SrcClk, uint32_t ui32Osc)) \
+ ROM_API_OSC_TABLE[1])
+
+#define ROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert \
+ ((int16_t (*)(int32_t HPOSC_RelFreqOffset)) \
+ ROM_API_OSC_TABLE[3])
+
+
+// AUX_ADC FUNCTIONS
+#define ROM_AUXADCAdjustValueForGainAndOffset \
+ ((int32_t (*)(int32_t adcValue, int32_t gain, int32_t offset)) \
+ ROM_API_AUX_ADC_TABLE[0])
+
+#define ROM_AUXADCDisable \
+ ((void (*)(void)) \
+ ROM_API_AUX_ADC_TABLE[1])
+
+#define ROM_AUXADCDisableInputScaling \
+ ((void (*)(void)) \
+ ROM_API_AUX_ADC_TABLE[2])
+
+#define ROM_AUXADCEnableAsync \
+ ((void (*)(uint32_t refSource, uint32_t trigger)) \
+ ROM_API_AUX_ADC_TABLE[3])
+
+#define ROM_AUXADCEnableSync \
+ ((void (*)(uint32_t refSource, uint32_t sampleTime, uint32_t trigger)) \
+ ROM_API_AUX_ADC_TABLE[4])
+
+#define ROM_AUXADCFlushFifo \
+ ((void (*)(void)) \
+ ROM_API_AUX_ADC_TABLE[5])
+
+#define ROM_AUXADCGetAdjustmentGain \
+ ((int32_t (*)(uint32_t refSource)) \
+ ROM_API_AUX_ADC_TABLE[6])
+
+#define ROM_AUXADCGetAdjustmentOffset \
+ ((int32_t (*)(uint32_t refSource)) \
+ ROM_API_AUX_ADC_TABLE[7])
+
+#define ROM_AUXADCMicrovoltsToValue \
+ ((int32_t (*)(int32_t fixedRefVoltage, int32_t microvolts)) \
+ ROM_API_AUX_ADC_TABLE[8])
+
+#define ROM_AUXADCPopFifo \
+ ((uint32_t (*)(void)) \
+ ROM_API_AUX_ADC_TABLE[9])
+
+#define ROM_AUXADCReadFifo \
+ ((uint32_t (*)(void)) \
+ ROM_API_AUX_ADC_TABLE[10])
+
+#define ROM_AUXADCUnadjustValueForGainAndOffset \
+ ((int32_t (*)(int32_t adcValue, int32_t gain, int32_t offset)) \
+ ROM_API_AUX_ADC_TABLE[11])
+
+#define ROM_AUXADCValueToMicrovolts \
+ ((int32_t (*)(int32_t fixedRefVoltage, int32_t adcValue)) \
+ ROM_API_AUX_ADC_TABLE[12])
+
+
+// SYS_CTRL FUNCTIONS
+#define ROM_SysCtrlResetSourceGet \
+ ((uint32_t (*)(void)) \
+ ROM_API_SYS_CTRL_TABLE[0])
+
+#define ROM_SysCtrl_DCDC_VoltageConditionalControl \
+ ((void (*)(void)) \
+ ROM_API_SYS_CTRL_TABLE[1])
+
+
+// AON_BATMON FUNCTIONS
+#define ROM_AONBatMonTemperatureGetDegC \
+ ((int32_t (*)(void)) \
+ ROM_API_AON_BATMON_TABLE[0])
+
+
+// SETUP_ROM FUNCTIONS
+#define ROM_SetupAfterColdResetWakeupFromShutDownCfg1 \
+ ((void (*)(uint32_t ccfg_ModeConfReg)) \
+ ROM_API_SETUP_ROM_TABLE[0])
+
+#define ROM_SetupAfterColdResetWakeupFromShutDownCfg2 \
+ ((void (*)(uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg)) \
+ ROM_API_SETUP_ROM_TABLE[1])
+
+#define ROM_SetupAfterColdResetWakeupFromShutDownCfg3 \
+ ((void (*)(uint32_t ccfg_ModeConfReg)) \
+ ROM_API_SETUP_ROM_TABLE[2])
+
+#define ROM_SetupGetTrimForAdcShModeEn \
+ ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \
+ ROM_API_SETUP_ROM_TABLE[3])
+
+#define ROM_SetupGetTrimForAdcShVbufEn \
+ ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \
+ ROM_API_SETUP_ROM_TABLE[4])
+
+#define ROM_SetupGetTrimForAmpcompCtrl \
+ ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \
+ ROM_API_SETUP_ROM_TABLE[5])
+
+#define ROM_SetupGetTrimForAmpcompTh1 \
+ ((uint32_t (*)(void)) \
+ ROM_API_SETUP_ROM_TABLE[6])
+
+#define ROM_SetupGetTrimForAmpcompTh2 \
+ ((uint32_t (*)(void)) \
+ ROM_API_SETUP_ROM_TABLE[7])
+
+#define ROM_SetupGetTrimForAnabypassValue1 \
+ ((uint32_t (*)(uint32_t ccfg_ModeConfReg)) \
+ ROM_API_SETUP_ROM_TABLE[8])
+
+#define ROM_SetupGetTrimForDblrLoopFilterResetVoltage \
+ ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \
+ ROM_API_SETUP_ROM_TABLE[9])
+
+#define ROM_SetupGetTrimForRadcExtCfg \
+ ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \
+ ROM_API_SETUP_ROM_TABLE[10])
+
+#define ROM_SetupGetTrimForRcOscLfIBiasTrim \
+ ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \
+ ROM_API_SETUP_ROM_TABLE[11])
+
+#define ROM_SetupGetTrimForRcOscLfRtuneCtuneTrim \
+ ((uint32_t (*)(void)) \
+ ROM_API_SETUP_ROM_TABLE[12])
+
+#define ROM_SetupGetTrimForXoscHfCtl \
+ ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \
+ ROM_API_SETUP_ROM_TABLE[13])
+
+#define ROM_SetupGetTrimForXoscHfFastStart \
+ ((uint32_t (*)(void)) \
+ ROM_API_SETUP_ROM_TABLE[14])
+
+#define ROM_SetupGetTrimForXoscHfIbiastherm \
+ ((uint32_t (*)(void)) \
+ ROM_API_SETUP_ROM_TABLE[15])
+
+#define ROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio \
+ ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \
+ ROM_API_SETUP_ROM_TABLE[16])
+
+#define ROM_SetupSetAonRtcSubSecInc \
+ ((void (*)(uint32_t subSecInc)) \
+ ROM_API_SETUP_ROM_TABLE[17])
+
+#define ROM_SetupSetCacheModeAccordingToCcfgSetting \
+ ((void (*)(void)) \
+ ROM_API_SETUP_ROM_TABLE[18])
+
+#define ROM_SetupStepVddrTrimTo \
+ ((void (*)(uint32_t toCode)) \
+ ROM_API_SETUP_ROM_TABLE[19])
+
+
+// I2S FUNCTIONS
+#define ROM_I2SPointerSet \
+ ((void (*)(uint32_t ui32Base, bool bInput, void * pNextPointer)) \
+ ROM_API_I2S_TABLE[0])
+
+#define ROM_I2SSampleStampGet \
+ ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32Channel)) \
+ ROM_API_I2S_TABLE[1])
+
+
+// PWR_CTRL FUNCTIONS
+#define ROM_PowerCtrlSourceSet \
+ ((void (*)(uint32_t ui32PowerConfig)) \
+ ROM_API_PWR_CTRL_TABLE[0])
+
+
+// AES FUNCTIONS
+#define ROM_AESConfigureCCMCtrl \
+ ((void (*)(uint32_t nonceLength, uint32_t macLength, bool encrypt)) \
+ ROM_API_AES_TABLE[0])
+
+#define ROM_AESReadFromKeyStore \
+ ((uint32_t (*)(uint32_t keyStoreArea)) \
+ ROM_API_AES_TABLE[1])
+
+#define ROM_AESReadTag \
+ ((uint32_t (*)(uint8_t *tag, uint32_t tagLength)) \
+ ROM_API_AES_TABLE[2])
+
+#define ROM_AESSetInitializationVector \
+ ((void (*)(const uint32_t *initializationVector)) \
+ ROM_API_AES_TABLE[3])
+
+#define ROM_AESStartDMAOperation \
+ ((void (*)(const uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length)) \
+ ROM_API_AES_TABLE[4])
+
+#define ROM_AESVerifyTag \
+ ((uint32_t (*)(const uint8_t *tag, uint32_t tagLength)) \
+ ROM_API_AES_TABLE[5])
+
+#define ROM_AESWaitForIRQFlags \
+ ((uint32_t (*)(uint32_t irqFlags)) \
+ ROM_API_AES_TABLE[6])
+
+#define ROM_AESWriteCCMInitializationVector \
+ ((void (*)(const uint8_t *nonce, uint32_t nonceLength)) \
+ ROM_API_AES_TABLE[7])
+
+#define ROM_AESWriteToKeyStore \
+ ((uint32_t (*)(const uint8_t *aesKey, uint32_t aesKeyLength, uint32_t keyStoreArea)) \
+ ROM_API_AES_TABLE[8])
+
+
+// PKA FUNCTIONS
+#define ROM_PKABigNumAddGetResult \
+ ((uint32_t (*)(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr)) \
+ ROM_API_PKA_TABLE[0])
+
+#define ROM_PKABigNumCmpGetResult \
+ ((uint32_t (*)(void)) \
+ ROM_API_PKA_TABLE[1])
+
+#define ROM_PKABigNumInvModGetResult \
+ ((uint32_t (*)(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr)) \
+ ROM_API_PKA_TABLE[2])
+
+#define ROM_PKABigNumModGetResult \
+ ((uint32_t (*)(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr)) \
+ ROM_API_PKA_TABLE[3])
+
+#define ROM_PKABigNumMultGetResult \
+ ((uint32_t (*)(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr)) \
+ ROM_API_PKA_TABLE[4])
+
+#define ROM_PKAEccAddGetResult \
+ ((uint32_t (*)(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length)) \
+ ROM_API_PKA_TABLE[5])
+
+#define ROM_PKAEccAddStart \
+ ((uint32_t (*)(const uint8_t *curvePoint1X, const uint8_t *curvePoint1Y, const uint8_t *curvePoint2X, const uint8_t *curvePoint2Y, const uint8_t *prime, const uint8_t *a, uint32_t length, uint32_t *resultPKAMemAddr)) \
+ ROM_API_PKA_TABLE[6])
+
+#define ROM_PKAEccMultiplyGetResult \
+ ((uint32_t (*)(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length)) \
+ ROM_API_PKA_TABLE[7])
+
+#define ROM_PKAEccMultiplyStart \
+ ((uint32_t (*)(const uint8_t *scalar, const uint8_t *curvePointX, const uint8_t *curvePointY, const uint8_t *prime, const uint8_t *a, const uint8_t *b, uint32_t length, uint32_t *resultPKAMemAddr)) \
+ ROM_API_PKA_TABLE[8])
+
+#define ROM_PKAGetOpsStatus \
+ ((uint32_t (*)(void)) \
+ ROM_API_PKA_TABLE[9])
+
+#define ROM_PKABigNumAddStart \
+ ((uint32_t (*)(const uint8_t *bigNum1, uint32_t bigNum1Length, const uint8_t *bigNum2, uint32_t bigNum2Length, uint32_t *resultPKAMemAddr)) \
+ ROM_API_PKA_TABLE[10])
+
+#define ROM_PKABigNumCmpStart \
+ ((uint32_t (*)(const uint8_t *bigNum1, const uint8_t *bigNum2, uint32_t length)) \
+ ROM_API_PKA_TABLE[11])
+
+#define ROM_PKABigNumInvModStart \
+ ((uint32_t (*)(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr)) \
+ ROM_API_PKA_TABLE[12])
+
+#define ROM_PKABigNumModStart \
+ ((uint32_t (*)(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr)) \
+ ROM_API_PKA_TABLE[13])
+
+#define ROM_PKABigNumMultiplyStart \
+ ((uint32_t (*)(const uint8_t *multiplicand, uint32_t multiplicandLength, const uint8_t *multiplier, uint32_t multiplierLength, uint32_t *resultPKAMemAddr)) \
+ ROM_API_PKA_TABLE[14])
+
+#define ROM_PKABigNumSubGetResult \
+ ((uint32_t (*)(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr)) \
+ ROM_API_PKA_TABLE[15])
+
+#define ROM_PKABigNumSubStart \
+ ((uint32_t (*)(const uint8_t *minuend, uint32_t minuendLength, const uint8_t *subtrahend, uint32_t subtrahendLength, uint32_t *resultPKAMemAddr)) \
+ ROM_API_PKA_TABLE[16])
+
+#define ROM_PKAArrayAllZeros \
+ ((bool (*)(const uint8_t *array, uint32_t arrayLength)) \
+ ROM_API_PKA_TABLE[17])
+
+#define ROM_PKABigNumDivideGetQuotient \
+ ((uint32_t (*)(uint8_t *resultBuf, uint32_t *length, uint32_t resultQuotientMemAddr)) \
+ ROM_API_PKA_TABLE[18])
+
+#define ROM_PKABigNumDivideGetRemainder \
+ ((uint32_t (*)(uint8_t *resultBuf, uint32_t *length, uint32_t resultRemainderMemAddr)) \
+ ROM_API_PKA_TABLE[19])
+
+#define ROM_PKABigNumDivideStart \
+ ((uint32_t (*)(const uint8_t *dividend, uint32_t dividendLength, const uint8_t *divisor, uint32_t divisorLength, uint32_t *resultQuotientMemAddr, uint32_t *resultRemainderMemAddr)) \
+ ROM_API_PKA_TABLE[20])
+
+#define ROM_PKAEccVerifyPublicKeyWeierstrassStart \
+ ((uint32_t (*)(const uint8_t *curvePointX, const uint8_t *curvePointY, const uint8_t *prime, const uint8_t *a, const uint8_t *b, const uint8_t *order, uint32_t length)) \
+ ROM_API_PKA_TABLE[21])
+
+#define ROM_PKAZeroOutArray \
+ ((void (*)(const uint8_t *array, uint32_t arrayLength)) \
+ ROM_API_PKA_TABLE[22])
+
+#define ROM_PKAEccMontgomeryMultiplyStart \
+ ((uint32_t (*)(const uint8_t *scalar, const uint8_t *curvePointX, const uint8_t *prime, const uint8_t *a, uint32_t length, uint32_t *resultPKAMemAddr)) \
+ ROM_API_PKA_TABLE[23])
+
+
+// SHA2 FUNCTIONS
+#define ROM_SHA2ComputeFinalHash \
+ ((uint32_t (*)(const uint8_t *message, uint8_t *resultDigest, uint32_t *intermediateDigest, uint32_t totalMsgLength, uint32_t messageLength, uint32_t hashAlgorithm)) \
+ ROM_API_SHA2_TABLE[0])
+
+#define ROM_SHA2ComputeHash \
+ ((uint32_t (*)(const uint8_t *message, uint8_t *resultDigest, uint32_t totalMsgLength, uint32_t hashAlgorithm)) \
+ ROM_API_SHA2_TABLE[1])
+
+#define ROM_SHA2ComputeInitialHash \
+ ((uint32_t (*)(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t initialMessageLength)) \
+ ROM_API_SHA2_TABLE[2])
+
+#define ROM_SHA2ComputeIntermediateHash \
+ ((uint32_t (*)(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t intermediateMessageLength)) \
+ ROM_API_SHA2_TABLE[3])
+
+#define ROM_SHA2StartDMAOperation \
+ ((void (*)(uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length)) \
+ ROM_API_SHA2_TABLE[4])
+
+#define ROM_SHA2WaitForIRQFlags \
+ ((uint32_t (*)(uint32_t irqFlags)) \
+ ROM_API_SHA2_TABLE[5])
+
+
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __ROM_H__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rom_crypto.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rom_crypto.c
new file mode 100644
index 0000000..2f284cd
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rom_crypto.c
@@ -0,0 +1,159 @@
+/*******************************************************************************
+* Filename: rom_crypto.c
+* Revised: 2018-09-17 08:57:21 +0200 (Mon, 17 Sep 2018)
+* Revision: 52619
+*
+* Description: This is the implementation for the API to the ECC functions
+* built into ROM on the CC13x2/CC26x2.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+*******************************************************************************/
+
+#include <stdint.h>
+#include "rom_crypto.h"
+
+
+////////////////////////////////////* ECC *////////////////////////////////////
+#ifdef ECC_PRIME_NIST256_CURVE
+//#define TEST_NIST256
+//#define PARAM_P NIST256_p;
+#define PARAM_P 0x100257d4;
+
+//#define PARAM_R NIST256_r;
+#define PARAM_R 0x100257f8;
+
+//#define PARAM_A NIST256_a;
+#define PARAM_A 0x1002581c;
+
+//#define PARAM_B NIST256_b;
+#define PARAM_B 0x10025840;
+
+//#define PARAM_GX NIST256_Gx;
+#define PARAM_GX 0x10025864;
+
+//#define PARAM_GY NIST256_Gy;
+#define PARAM_GY 0x10025888;
+
+#endif
+
+
+//*****************************************************************************
+// ECC_initialize
+//*****************************************************************************
+void
+ECC_initialize(uint32_t *pWorkzone)
+{
+ // Initialize curve parameters
+ //data_p = (uint32_t *)PARAM_P;
+ *((uint32_t **)0x20000138) = (uint32_t *)PARAM_P;
+
+ //data_r = (uint32_t *)PARAM_R;
+ *((uint32_t **)0x2000013c) = (uint32_t *)PARAM_R;
+
+ //data_a = (uint32_t *)PARAM_A;
+ *((uint32_t **)0x20000140) = (uint32_t *)PARAM_A;
+
+ //data_b = (uint32_t *)PARAM_B;
+ *((uint32_t **)0x20000144) = (uint32_t *)PARAM_B;
+
+ //data_Gx = (uint32_t *)PARAM_GX;
+ *((uint32_t **)0x2000012c) = (uint32_t *)PARAM_GX;
+
+ //data_Gy = (uint32_t *)PARAM_GY;
+ *((uint32_t **)0x20000130) = (uint32_t *)PARAM_GY;
+
+ // Initialize window size
+ //win = (uint8_t) ECC_WINDOW_SIZE;
+ *((uint8_t *)0x20000148) = (uint8_t) ECC_WINDOW_SIZE;
+
+ // Initialize work zone
+ //workzone = (uint32_t *) pWorkzone;
+ *((uint32_t **)0x20000134) = (uint32_t *) pWorkzone;
+}
+
+typedef uint8_t(*ecc_keygen_t)(uint32_t *, uint32_t *,uint32_t *, uint32_t *);
+ecc_keygen_t ecc_generatekey = (ecc_keygen_t)(0x1001f94d);
+
+typedef uint8_t(*ecdsa_sign_t)(uint32_t *, uint32_t *,uint32_t *, uint32_t *, uint32_t *);
+ecdsa_sign_t ecc_ecdsa_sign = (ecdsa_sign_t)(0x10010381);
+
+typedef uint8_t(*ecdsa_verify_t)(uint32_t *, uint32_t *,uint32_t *, uint32_t *, uint32_t *);
+ecdsa_verify_t ecc_ecdsa_verify = (ecdsa_verify_t)(0x1000c805);
+
+typedef uint8_t(*ecdh_computeSharedSecret_t)(uint32_t *, uint32_t *,uint32_t *, uint32_t *, uint32_t *);
+ecdh_computeSharedSecret_t ecdh_computeSharedSecret = (ecdh_computeSharedSecret_t)(0x10023485);
+
+//*****************************************************************************
+// ECC_generateKey
+//*****************************************************************************
+uint8_t
+ECC_generateKey(uint32_t *randString, uint32_t *privateKey,
+ uint32_t *publicKey_x, uint32_t *publicKey_y)
+{
+ return (uint8_t)ecc_generatekey((uint32_t*)randString, (uint32_t*)privateKey,
+ (uint32_t*)publicKey_x, (uint32_t*)publicKey_y);
+
+}
+
+//*****************************************************************************
+// ECC_ECDSA_sign
+//*****************************************************************************
+uint8_t
+ECC_ECDSA_sign(uint32_t *secretKey, uint32_t *text, uint32_t *randString,
+ uint32_t *sign1, uint32_t *sign2)
+{
+ return (uint8_t)ecc_ecdsa_sign((uint32_t*)secretKey, (uint32_t*)text, (uint32_t*)randString,
+ (uint32_t*)sign1, (uint32_t*)sign2);
+}
+
+//*****************************************************************************
+// ECC_ECDSA_verify
+//*****************************************************************************
+uint8_t
+ECC_ECDSA_verify(uint32_t *publicKey_x, uint32_t *publicKey_y,
+ uint32_t *text, uint32_t *sign1, uint32_t *sign2)
+{
+ return (uint8_t)ecc_ecdsa_verify((uint32_t*)publicKey_x, (uint32_t*)publicKey_y, (uint32_t*)text,
+ (uint32_t*)sign1, (uint32_t*)sign2);
+}
+
+//*****************************************************************************
+// ECC_ECDH_computeSharedSecret
+//*****************************************************************************
+uint8_t
+ECC_ECDH_computeSharedSecret(uint32_t *privateKey, uint32_t *publicKey_x,
+ uint32_t *publicKey_y, uint32_t *sharedSecret_x,
+ uint32_t *sharedSecret_y)
+{
+ return (uint8_t)ecdh_computeSharedSecret((uint32_t*)privateKey, (uint32_t*)publicKey_x,
+ (uint32_t*)publicKey_y, (uint32_t*)sharedSecret_x,
+ (uint32_t*)sharedSecret_y);
+}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rom_crypto.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rom_crypto.h
new file mode 100644
index 0000000..eecafac
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rom_crypto.h
@@ -0,0 +1,212 @@
+/******************************************************************************
+* Filename: rom_crypto.h
+* Revised: 2018-09-17 09:24:56 +0200 (Mon, 17 Sep 2018)
+* Revision: 52624
+*
+* Description: This header file is the API to the crypto functions
+* built into ROM on the CC13xx/CC26xx.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+*******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup peripheral_group
+//! @{
+//! \addtogroup rom_crypto_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef ROM_CRYPTO_H
+#define ROM_CRYPTO_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+////////////////////////////////////* ECC */////////////////////////////////////
+
+/* Window size, valid values are 2,3,4,5.
+ * Higher the value, faster the computation at the expense of memory usage.
+ *
+ * Recommended workzone size (in 4-byte words)
+ * Window size: 3, Workzone size: 275
+ *
+ */
+#define ECC_WINDOW_SIZE 3
+
+/*
+ * ECC Supported Curves, define one:
+ * ECC_PRIME_NIST256_CURVE
+ */
+#define ECC_PRIME_NIST256_CURVE
+
+/*
+ * ECC Return Status Flags.
+ */
+// Scalar multiplication status
+#define ECC_MODULUS_EVEN 0xDC
+#define ECC_MODULUS_LARGER_THAN_255_WORDS 0xD2
+#define ECC_MODULUS_LENGTH_ZERO 0x08
+#define ECC_MODULUS_MSW_IS_ZERO 0x30
+#define ECC_SCALAR_TOO_LONG 0x35
+#define ECC_SCALAR_LENGTH_ZERO 0x53
+#define ECC_ORDER_TOO_LONG 0xC6
+#define ECC_ORDER_LENGTH_ZERO 0x6C
+#define ECC_X_COORD_TOO_LONG 0x3C
+#define ECC_X_COORD_LENGTH_ZERO 0xC3
+#define ECC_Y_COORD_TOO_LONG 0x65
+#define ECC_Y_COORD_LENGTH_ZERO 0x56
+#define ECC_A_COEF_TOO_LONG 0x5C
+#define ECC_A_COEF_LENGTH_ZERO 0xC5
+#define ECC_BAD_WINDOW_SIZE 0x66
+#define ECC_SCALAR_MUL_OK 0x99
+
+// ECDSA and ECDH status
+#define ECC_ORDER_LARGER_THAN_255_WORDS 0x28
+#define ECC_ORDER_EVEN 0x82
+#define ECC_ORDER_MSW_IS_ZERO 0x23
+#define ECC_ECC_KEY_TOO_LONG 0x25
+#define ECC_ECC_KEY_LENGTH_ZERO 0x52
+#define ECC_DIGEST_TOO_LONG 0x27
+#define ECC_DIGEST_LENGTH_ZERO 0x72
+#define ECC_ECDSA_SIGN_OK 0x32
+#define ECC_ECDSA_INVALID_SIGNATURE 0x5A
+#define ECC_ECDSA_VALID_SIGNATURE 0xA5
+#define ECC_SIG_P1_TOO_LONG 0x11
+#define ECC_SIG_P1_LENGTH_ZERO 0x12
+#define ECC_SIG_P2_TOO_LONG 0x22
+#define ECC_SIG_P2_LENGTH_ZERO 0x21
+
+#define ECC_ECDSA_KEYGEN_OK ECC_SCALAR_MUL_OK
+#define ECC_ECDH_KEYGEN_OK ECC_SCALAR_MUL_OK
+#define ECC_ECDH_COMMON_KEY_OK ECC_SCALAR_MUL_OK
+
+//*****************************************************************************
+/*!
+ * \brief Pass pointer to ECC memory allocation to ECC engine.
+ *
+ * This function can be called again to point the ECC workzone at
+ * a different memory buffer.
+ *
+ * \param pWorkzone Pointer to memory allocated for computations, input.
+ * See description at beginning of ECC section for
+ * memory requirements.
+ *
+ * \return None
+ */
+//*****************************************************************************
+ extern void ECC_initialize(uint32_t *pWorkzone);
+
+//*****************************************************************************
+ /*!
+ * \brief Generate a key.
+ *
+ * This is used for both ECDH and ECDSA.
+ *
+ * \param randString Pointer to random string, input.
+ * \param privateKey Pointer to the private key, output.
+ * \param publicKey_x Pointer to public key X-coordinate, output.
+ * \param publicKey_y Pointer to public key Y-coordinate, output.
+ *
+ * \return Status
+ */
+//*****************************************************************************
+extern uint8_t ECC_generateKey(uint32_t *randString, uint32_t *privateKey,
+ uint32_t *publicKey_x, uint32_t *publicKey_y);
+
+//*****************************************************************************
+/*!
+ * \brief Sign data.
+ *
+ * \param secretKey Pointer to the secret key, input.
+ * \param text Pointer to the message, input.
+ * \param randString Pointer to random string, input.
+ * \param sign1 Pointer to signature part 1, output.
+ * \param sign2 Pointer to signature part 2, output.
+ *
+ * \return Status
+ */
+//*****************************************************************************
+extern uint8_t ECC_ECDSA_sign(uint32_t *secretKey, uint32_t *text, uint32_t *randString,
+ uint32_t *sign1, uint32_t *sign2);
+
+//*****************************************************************************
+/*!
+ * \brief Verify signature.
+ *
+ * \param publicKey_x Pointer to public key X-coordinate, input.
+ * \param publicKey_y Pointer to public key Y-coordinate, input.
+ * \param text Pointer to message data, input.
+ * \param sign1 Pointer to signature part 1, input.
+ * \param sign2 Pointer to signature part 2, input.
+ *
+ * \return Status
+ */
+//*****************************************************************************
+extern uint8_t ECC_ECDSA_verify(uint32_t *publicKey_x, uint32_t *publicKey_y,
+ uint32_t *text, uint32_t *sign1, uint32_t *sign2);
+
+//*****************************************************************************
+/*!
+ * \brief Compute the shared secret.
+ *
+ * \param privateKey Pointer to private key, input.
+ * \param publicKey_x Pointer to public key X-coordinate, input.
+ * \param publicKey_y Pointer to public key Y-coordinate, input.
+ * \param sharedSecret_x Pointer to shared secret X-coordinate, output.
+ * \param sharedSecret_y Pointer to shared secret Y-coordinate, output.
+ *
+ * \return Status
+ */
+//*****************************************************************************
+extern uint8_t ECC_ECDH_computeSharedSecret(uint32_t *privateKey,
+ uint32_t *publicKey_x,
+ uint32_t *publicKey_y,
+ uint32_t *sharedSecret_x,
+ uint32_t *sharedSecret_y);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ROM_CRYPTO_H */
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/setup.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/setup.c
new file mode 100644
index 0000000..1f438be
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/setup.c
@@ -0,0 +1,344 @@
+/******************************************************************************
+* Filename: setup.c
+* Revised: 2018-11-06 15:08:57 +0100 (Tue, 06 Nov 2018)
+* Revision: 53239
+*
+* Description: Setup file for CC13xx/CC26xx devices.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+// Hardware headers
+#include "../inc/hw_types.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_adi.h"
+#include "../inc/hw_adi_2_refsys.h"
+#include "../inc/hw_adi_3_refsys.h"
+#include "../inc/hw_adi_4_aux.h"
+// Temporarily adding these defines as they are missing in hw_adi_4_aux.h
+#define ADI_4_AUX_O_LPMBIAS 0x0000000E
+#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_M 0x0000003F
+#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_S 0
+#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_M 0x00000038
+#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_S 3
+#include "../inc/hw_aon_ioc.h"
+#include "../inc/hw_aon_pmctl.h"
+#include "../inc/hw_aon_rtc.h"
+#include "../inc/hw_ddi_0_osc.h"
+#include "../inc/hw_ddi.h"
+#include "../inc/hw_ccfg.h"
+#include "../inc/hw_fcfg1.h"
+#include "../inc/hw_flash.h"
+#include "../inc/hw_prcm.h"
+#include "../inc/hw_vims.h"
+// Driverlib headers
+#include "aux_sysif.h"
+#include "chipinfo.h"
+#include "setup.h"
+#include "setup_rom.h"
+
+//*****************************************************************************
+//
+// Handle support for DriverLib in ROM:
+// This section will undo prototype renaming made in the header file
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #undef SetupTrimDevice
+ #define SetupTrimDevice NOROM_SetupTrimDevice
+#endif
+
+
+
+//*****************************************************************************
+//
+// Defined CPU delay macro with microseconds as input
+// Quick check shows: (To be further investigated)
+// At 48 MHz RCOSC and VIMS.CONTROL.PREFETCH = 0, there is 5 cycles
+// At 48 MHz RCOSC and VIMS.CONTROL.PREFETCH = 1, there is 4 cycles
+// At 24 MHz RCOSC and VIMS.CONTROL.PREFETCH = 0, there is 3 cycles
+//
+//*****************************************************************************
+#define CPU_DELAY_MICRO_SECONDS( x ) \
+ CPUdelay(((uint32_t)((( x ) * 48.0 ) / 5.0 )) - 1 )
+
+
+//*****************************************************************************
+//
+// Function declarations
+//
+//*****************************************************************************
+static void TrimAfterColdReset( void );
+static void TrimAfterColdResetWakeupFromShutDown( uint32_t ui32Fcfg1Revision );
+static void TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown( void );
+
+//*****************************************************************************
+//
+// Perform the necessary trim of the device which is not done in boot code
+//
+// This function should only execute coming from ROM boot. The current
+// implementation does not take soft reset into account. However, it does no
+// damage to execute it again. It only consumes time.
+//
+//*****************************************************************************
+void
+SetupTrimDevice(void)
+{
+ uint32_t ui32Fcfg1Revision;
+ uint32_t ui32AonSysResetctl;
+
+ // Get layout revision of the factory configuration area
+ // (Handle undefined revision as revision = 0)
+ ui32Fcfg1Revision = HWREG(FCFG1_BASE + FCFG1_O_FCFG1_REVISION);
+ if ( ui32Fcfg1Revision == 0xFFFFFFFF ) {
+ ui32Fcfg1Revision = 0;
+ }
+
+ // This driverlib version and setup file is for the CC13x2, CC26x2 PG2.0 or later chips.
+ // Halt if violated
+ ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated();
+
+ // Enable standby in flash bank
+ HWREGBITW( FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0;
+
+ // Select correct CACHE mode and set correct CACHE configuration
+#if ( CCFG_BASE == CCFG_BASE_DEFAULT )
+ SetupSetCacheModeAccordingToCcfgSetting();
+#else
+ NOROM_SetupSetCacheModeAccordingToCcfgSetting();
+#endif
+
+ // 1. Check for powerdown
+ // 2. Check for shutdown
+ // 3. Assume cold reset if none of the above.
+ //
+ // It is always assumed that the application will freeze the latches in
+ // AON_IOC when going to powerdown in order to retain the values on the IOs.
+ //
+ // NB. If this bit is not cleared before proceeding to powerdown, the IOs
+ // will all default to the reset configuration when restarting.
+ if( ! ( HWREGBITW( AON_IOC_BASE + AON_IOC_O_IOCLATCH, AON_IOC_IOCLATCH_EN_BITN )))
+ {
+ // NB. This should be calling a ROM implementation of required trim and
+ // compensation
+ // e.g. TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown()
+ TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown();
+ }
+ // Check for shutdown
+ //
+ // When device is going to shutdown the hardware will automatically clear
+ // the SLEEPDIS bit in the SLEEP register in the AON_PMCTL module.
+ // It is left for the application to assert this bit when waking back up,
+ // but not before the desired IO configuration has been re-established.
+ else if( ! ( HWREGBITW( AON_PMCTL_BASE + AON_PMCTL_O_SLEEPCTL, AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_BITN )))
+ {
+ // NB. This should be calling a ROM implementation of required trim and
+ // compensation
+ // e.g. TrimAfterColdResetWakeupFromShutDown() -->
+ // TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown();
+ TrimAfterColdResetWakeupFromShutDown(ui32Fcfg1Revision);
+ TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown();
+ }
+ else
+ {
+ // Consider adding a check for soft reset to allow debugging to skip
+ // this section!!!
+ //
+ // NB. This should be calling a ROM implementation of required trim and
+ // compensation
+ // e.g. TrimAfterColdReset() -->
+ // TrimAfterColdResetWakeupFromShutDown() -->
+ // TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown()
+ TrimAfterColdReset();
+ TrimAfterColdResetWakeupFromShutDown(ui32Fcfg1Revision);
+ TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown();
+
+ }
+
+ // Set VIMS power domain control.
+ // PDCTL1VIMS = 0 ==> VIMS power domain is only powered when CPU power domain is powered
+ HWREG( PRCM_BASE + PRCM_O_PDCTL1VIMS ) = 0;
+
+ // Configure optimal wait time for flash FSM in cases where flash pump
+ // wakes up from sleep
+ HWREG(FLASH_BASE + FLASH_O_FPAC1) = (HWREG(FLASH_BASE + FLASH_O_FPAC1) &
+ ~FLASH_FPAC1_PSLEEPTDIS_M) |
+ (0x139<<FLASH_FPAC1_PSLEEPTDIS_S);
+
+ // And finally at the end of the flash boot process:
+ // SET BOOT_DET bits in AON_PMCTL to 3 if already found to be 1
+ // Note: The BOOT_DET_x_CLR/SET bits must be manually cleared
+ if ((( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) &
+ ( AON_PMCTL_RESETCTL_BOOT_DET_1_M | AON_PMCTL_RESETCTL_BOOT_DET_0_M )) >>
+ AON_PMCTL_RESETCTL_BOOT_DET_0_S ) == 1 )
+ {
+ ui32AonSysResetctl = ( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) &
+ ~( AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_M | AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_M |
+ AON_PMCTL_RESETCTL_BOOT_DET_1_SET_M | AON_PMCTL_RESETCTL_BOOT_DET_0_SET_M | AON_PMCTL_RESETCTL_MCU_WARM_RESET_M ));
+ HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = ui32AonSysResetctl | AON_PMCTL_RESETCTL_BOOT_DET_1_SET_M;
+ HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = ui32AonSysResetctl;
+ }
+
+ // Make sure there are no ongoing VIMS mode change when leaving SetupTrimDevice()
+ // (There should typically be no wait time here, but need to be sure)
+ while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) {
+ // Do nothing - wait for an eventual ongoing mode change to complete.
+ }
+}
+
+//*****************************************************************************
+//
+//! \brief Trims to be applied when coming from POWER_DOWN (also called when
+//! coming from SHUTDOWN and PIN_RESET).
+//!
+//! \return None
+//
+//*****************************************************************************
+static void
+TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown( void )
+{
+ // Currently no specific trim for Powerdown
+}
+
+//*****************************************************************************
+//
+//! \brief Trims to be applied when coming from SHUTDOWN (also called when
+//! coming from PIN_RESET).
+//!
+//! \param ui32Fcfg1Revision
+//!
+//! \return None
+//
+//*****************************************************************************
+static void
+TrimAfterColdResetWakeupFromShutDown(uint32_t ui32Fcfg1Revision)
+{
+ uint32_t ccfg_ModeConfReg ;
+
+ // Check in CCFG for alternative DCDC setting
+ if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING ) == 0 ) {
+ // ADI_3_REFSYS:DCDCCTL5[3] (=DITHER_EN) = CCFG_MODE_CONF_1[19] (=ALT_DCDC_DITHER_EN)
+ // ADI_3_REFSYS:DCDCCTL5[2:0](=IPEAK ) = CCFG_MODE_CONF_1[18:16](=ALT_DCDC_IPEAK )
+ // Using a single 4-bit masked write since layout is equal for both source and destination
+ HWREGB( ADI3_BASE + ADI_O_MASK4B + ( ADI_3_REFSYS_O_DCDCCTL5 * 2 )) = ( 0xF0 |
+ ( HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ) >> CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S ));
+
+ }
+
+ // TBD - Temporarily removed for CC13x2 / CC26x2
+
+ // Force DCDC to use RCOSC before starting up XOSC.
+ // Clock loss detector does not use XOSC until SCLK_HF actually switches
+ // and thus DCDC is not protected from clock loss on XOSC in that time frame.
+ // The force must be released when the switch to XOSC has happened. This is done
+ // in OSCHfSourceSwitch().
+ HWREG(AUX_DDI0_OSC_BASE + DDI_O_MASK16B + (DDI_0_OSC_O_CTL0 << 1) + 4) = DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M | (DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M >> 16);
+ // Dummy read to ensure that the write has propagated
+ HWREGH(AUX_DDI0_OSC_BASE + DDI_0_OSC_O_CTL0);
+
+ // read the MODE_CONF register in CCFG
+ ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF );
+
+ // First part of trim done after cold reset and wakeup from shutdown:
+ // -Adjust the VDDR_TRIM_SLEEP value.
+ // -Configure DCDC.
+ SetupAfterColdResetWakeupFromShutDownCfg1( ccfg_ModeConfReg );
+
+ // Addition to the CC1352 boost mode for HWREV >= 2.0
+ // The combination VDDR_EXT_LOAD=0 and VDDS_BOD_LEVEL=1 is defined to select boost mode
+ if ((( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_EXT_LOAD ) == 0 ) &&
+ (( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDS_BOD_LEVEL ) != 0 ) )
+ {
+ HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL3 ) = ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_BOOST ;
+ }
+
+ // Second part of trim done after cold reset and wakeup from shutdown:
+ // -Configure XOSC.
+#if ( CCFG_BASE == CCFG_BASE_DEFAULT )
+ SetupAfterColdResetWakeupFromShutDownCfg2( ui32Fcfg1Revision, ccfg_ModeConfReg );
+#else
+ NOROM_SetupAfterColdResetWakeupFromShutDownCfg2( ui32Fcfg1Revision, ccfg_ModeConfReg );
+#endif
+
+ {
+ uint32_t trimReg ;
+ uint32_t ui32TrimValue ;
+
+ //--- Propagate the LPM_BIAS trim ---
+ trimReg = HWREG( FCFG1_BASE + FCFG1_O_DAC_BIAS_CNF );
+ ui32TrimValue = (( trimReg & FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_M ) >>
+ FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_S ) ;
+ HWREGB( AUX_ADI4_BASE + ADI_4_AUX_O_LPMBIAS ) = (( ui32TrimValue << ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_S ) &
+ ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_M ) ;
+ // Set LPM_BIAS_BACKUP_EN according to FCFG1 configuration
+ if ( trimReg & FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN ) {
+ HWREGB( ADI3_BASE + ADI_O_SET + ADI_3_REFSYS_O_AUX_DEBUG ) = ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN;
+ } else {
+ HWREGB( ADI3_BASE + ADI_O_CLR + ADI_3_REFSYS_O_AUX_DEBUG ) = ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN;
+ }
+ // Set LPM_BIAS_WIDTH_TRIM according to FCFG1 configuration
+ {
+ uint32_t widthTrim = (( trimReg & FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_M ) >> FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_S );
+ HWREGH( AUX_ADI4_BASE + ADI_O_MASK8B + ( ADI_4_AUX_O_COMP * 2 )) = // Set LPM_BIAS_WIDTH_TRIM = 3
+ (( ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_M << 8 ) | // Set mask (bits to be written) in [15:8]
+ ( widthTrim << ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_S ) ); // Set value (in correct bit pos) in [7:0]
+ }
+ }
+
+ // Third part of trim done after cold reset and wakeup from shutdown:
+ // -Configure HPOSC.
+ // -Setup the LF clock.
+#if ( CCFG_BASE == CCFG_BASE_DEFAULT )
+ SetupAfterColdResetWakeupFromShutDownCfg3( ccfg_ModeConfReg );
+#else
+ NOROM_SetupAfterColdResetWakeupFromShutDownCfg3( ccfg_ModeConfReg );
+#endif
+
+ // Set AUX into power down active mode
+ AUXSYSIFOpModeChange( AUX_SYSIF_OPMODE_TARGET_PDA );
+
+ // Disable EFUSE clock
+ HWREGBITW( FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_EFUSECLK_BITN ) = 1;
+}
+
+
+//*****************************************************************************
+//
+//! \brief Trims to be applied when coming from PIN_RESET.
+//!
+//! \return None
+//
+//*****************************************************************************
+static void
+TrimAfterColdReset( void )
+{
+ // Currently no specific trim for Cold Reset
+}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/setup.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/setup.h
new file mode 100644
index 0000000..c2093d7
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/setup.h
@@ -0,0 +1,141 @@
+/******************************************************************************
+* Filename: setup.h
+* Revised: 2018-10-24 11:23:04 +0200 (Wed, 24 Oct 2018)
+* Revision: 52993
+*
+* Description: Prototypes and defines for the setup API.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup system_control_group
+//! @{
+//! \addtogroup setup_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __SETUP_H__
+#define __SETUP_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+// Hardware headers
+#include "../inc/hw_types.h"
+// Driverlib headers
+// - None needed
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// This section renames all functions that are not "static inline", so that
+// calling these functions will default to implementation in flash. At the end
+// of this file a second renaming will change the defaults to implementation in
+// ROM for available functions.
+//
+// To force use of the implementation in flash, e.g. for debugging:
+// - Globally: Define DRIVERLIB_NOROM at project level
+// - Per function: Use prefix "NOROM_" when calling the function
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #define SetupTrimDevice NOROM_SetupTrimDevice
+#endif
+
+//*****************************************************************************
+//
+//! \brief Performs the necessary trim of the device which is not done in ROM boot code.
+//!
+//! This function should only execute coming from ROM boot.
+//!
+//! The following is handled by this function:
+//! - Checks if the driverlib variant used by the application is supported by the
+//! device. Execution is halted in case of unsupported driverlib variant.
+//! - Configures VIMS cache mode based on setting in CCFG.
+//! - Configures functionalities like DCDC and XOSC dependent on startup modes like
+//! cold reset, wakeup from shutdown and wakeup from from powerdown.
+//! - Configures VIMS power domain control.
+//! - Configures optimal wait time for flash FSM in cases where flash pump wakes up from sleep.
+//!
+//! \note The current implementation does not take soft reset into account. However,
+//! it does no damage to execute it again. It only consumes time.
+//!
+//! \note This function is called by the compiler specific device startup codes
+//! that are integrated in the SimpleLink SDKs for CC13xx/CC26XX devices.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void SetupTrimDevice( void );
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// Redirect to implementation in ROM when available.
+//
+//*****************************************************************************
+#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
+ #include "../driverlib/rom.h"
+ #ifdef ROM_SetupTrimDevice
+ #undef SetupTrimDevice
+ #define SetupTrimDevice ROM_SetupTrimDevice
+ #endif
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __SETUP_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/setup_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/setup_doc.h
new file mode 100644
index 0000000..4692799
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/setup_doc.h
@@ -0,0 +1,41 @@
+/******************************************************************************
+* Filename: setup_doc.h
+* Revised: 2017-06-05 12:13:49 +0200 (ma, 05 jun 2017)
+* Revision: 49096
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+//! \addtogroup setup_api
+//! @{
+//!
+//! This module contains functions for device setup which is not done in boot code.
+//!
+//! @}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/setup_rom.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/setup_rom.c
new file mode 100644
index 0000000..745204b
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/setup_rom.c
@@ -0,0 +1,943 @@
+/******************************************************************************
+* Filename: setup_rom.c
+* Revised: 2017-11-02 11:31:15 +0100 (Thu, 02 Nov 2017)
+* Revision: 50143
+*
+* Description: Setup file for CC13xx/CC26xx devices.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+// Hardware headers
+#include "../inc/hw_types.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_adi.h"
+#include "../inc/hw_adi_2_refsys.h"
+#include "../inc/hw_adi_3_refsys.h"
+#include "../inc/hw_adi_4_aux.h"
+#include "../inc/hw_aon_batmon.h"
+#include "../inc/hw_aux_sysif.h"
+#include "../inc/hw_ccfg.h"
+#include "../inc/hw_ddi_0_osc.h"
+#include "../inc/hw_fcfg1.h"
+// Driverlib headers
+#include "ddi.h"
+#include "ioc.h"
+#include "osc.h"
+#include "sys_ctrl.h"
+#include "setup_rom.h"
+
+//*****************************************************************************
+//
+// Handle support for DriverLib in ROM:
+// This section will undo prototype renaming made in the header file
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #undef SetupAfterColdResetWakeupFromShutDownCfg1
+ #define SetupAfterColdResetWakeupFromShutDownCfg1 NOROM_SetupAfterColdResetWakeupFromShutDownCfg1
+ #undef SetupAfterColdResetWakeupFromShutDownCfg2
+ #define SetupAfterColdResetWakeupFromShutDownCfg2 NOROM_SetupAfterColdResetWakeupFromShutDownCfg2
+ #undef SetupAfterColdResetWakeupFromShutDownCfg3
+ #define SetupAfterColdResetWakeupFromShutDownCfg3 NOROM_SetupAfterColdResetWakeupFromShutDownCfg3
+ #undef SetupGetTrimForAdcShModeEn
+ #define SetupGetTrimForAdcShModeEn NOROM_SetupGetTrimForAdcShModeEn
+ #undef SetupGetTrimForAdcShVbufEn
+ #define SetupGetTrimForAdcShVbufEn NOROM_SetupGetTrimForAdcShVbufEn
+ #undef SetupGetTrimForAmpcompCtrl
+ #define SetupGetTrimForAmpcompCtrl NOROM_SetupGetTrimForAmpcompCtrl
+ #undef SetupGetTrimForAmpcompTh1
+ #define SetupGetTrimForAmpcompTh1 NOROM_SetupGetTrimForAmpcompTh1
+ #undef SetupGetTrimForAmpcompTh2
+ #define SetupGetTrimForAmpcompTh2 NOROM_SetupGetTrimForAmpcompTh2
+ #undef SetupGetTrimForAnabypassValue1
+ #define SetupGetTrimForAnabypassValue1 NOROM_SetupGetTrimForAnabypassValue1
+ #undef SetupGetTrimForDblrLoopFilterResetVoltage
+ #define SetupGetTrimForDblrLoopFilterResetVoltage NOROM_SetupGetTrimForDblrLoopFilterResetVoltage
+ #undef SetupGetTrimForRadcExtCfg
+ #define SetupGetTrimForRadcExtCfg NOROM_SetupGetTrimForRadcExtCfg
+ #undef SetupGetTrimForRcOscLfIBiasTrim
+ #define SetupGetTrimForRcOscLfIBiasTrim NOROM_SetupGetTrimForRcOscLfIBiasTrim
+ #undef SetupGetTrimForRcOscLfRtuneCtuneTrim
+ #define SetupGetTrimForRcOscLfRtuneCtuneTrim NOROM_SetupGetTrimForRcOscLfRtuneCtuneTrim
+ #undef SetupGetTrimForXoscHfCtl
+ #define SetupGetTrimForXoscHfCtl NOROM_SetupGetTrimForXoscHfCtl
+ #undef SetupGetTrimForXoscHfFastStart
+ #define SetupGetTrimForXoscHfFastStart NOROM_SetupGetTrimForXoscHfFastStart
+ #undef SetupGetTrimForXoscHfIbiastherm
+ #define SetupGetTrimForXoscHfIbiastherm NOROM_SetupGetTrimForXoscHfIbiastherm
+ #undef SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio
+ #define SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio NOROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio
+ #undef SetupSetCacheModeAccordingToCcfgSetting
+ #define SetupSetCacheModeAccordingToCcfgSetting NOROM_SetupSetCacheModeAccordingToCcfgSetting
+ #undef SetupSetAonRtcSubSecInc
+ #define SetupSetAonRtcSubSecInc NOROM_SetupSetAonRtcSubSecInc
+ #undef SetupStepVddrTrimTo
+ #define SetupStepVddrTrimTo NOROM_SetupStepVddrTrimTo
+#endif
+
+//*****************************************************************************
+//
+// Function declarations
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// SetupStepVddrTrimTo
+//
+//*****************************************************************************
+void
+SetupStepVddrTrimTo( uint32_t toCode )
+{
+ uint32_t pmctlResetctl_reg ;
+ int32_t targetTrim ;
+ int32_t currentTrim ;
+
+ targetTrim = SetupSignExtendVddrTrimValue( toCode & ( ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M >> ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S ));
+ currentTrim = SetupSignExtendVddrTrimValue((
+ HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL0 ) &
+ ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M ) >>
+ ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S ) ;
+
+ if ( targetTrim != currentTrim ) {
+ pmctlResetctl_reg = ( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) & ~AON_PMCTL_RESETCTL_MCU_WARM_RESET_M );
+ if ( pmctlResetctl_reg & AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M ) {
+ HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = ( pmctlResetctl_reg & ~AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M );
+ HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ); // Wait for VDDR_LOSS_EN setting to propagate
+ }
+
+ while ( targetTrim != currentTrim ) {
+ HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative)
+
+ if ( targetTrim > currentTrim ) currentTrim++;
+ else currentTrim--;
+
+ HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL0 ) = (
+ ( HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL0 ) & ~ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M ) |
+ ((((uint32_t)currentTrim) << ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S ) &
+ ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M ) );
+ }
+
+ HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative)
+
+ if ( pmctlResetctl_reg & AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M ) {
+ HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative)
+ HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative)
+ HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = pmctlResetctl_reg;
+ HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ); // And finally wait for VDDR_LOSS_EN setting to propagate
+ }
+ }
+}
+
+//*****************************************************************************
+//
+// SetupAfterColdResetWakeupFromShutDownCfg1
+//
+//*****************************************************************************
+void
+SetupAfterColdResetWakeupFromShutDownCfg1( uint32_t ccfg_ModeConfReg )
+{
+ // Check for CC1352 boost mode
+ // The combination VDDR_EXT_LOAD=0 and VDDS_BOD_LEVEL=1 is defined to select boost mode
+ if ((( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_EXT_LOAD ) == 0 ) &&
+ (( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDS_BOD_LEVEL ) != 0 ) )
+ {
+ // Set VDDS_BOD trim - using masked write {MASK8:DATA8}
+ // - TRIM_VDDS_BOD is bits[7:3] of ADI3..REFSYSCTL1
+ // - Needs a positive transition on BOD_BG_TRIM_EN (bit[7] of REFSYSCTL3) to
+ // latch new VDDS BOD. Set to 0 first to guarantee a positive transition.
+ HWREGB( ADI3_BASE + ADI_O_CLR + ADI_3_REFSYS_O_REFSYSCTL3 ) = ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN;
+ //
+ // VDDS_BOD_LEVEL = 1 means that boost mode is selected
+ // - Max out the VDDS_BOD trim (=VDDS_BOD_POS_31)
+ HWREGH( ADI3_BASE + ADI_O_MASK8B + ( ADI_3_REFSYS_O_REFSYSCTL1 * 2 )) =
+ ( ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_M << 8 ) |
+ ( ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_31 ) ;
+ HWREGB( ADI3_BASE + ADI_O_SET + ADI_3_REFSYS_O_REFSYSCTL3 ) = ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN;
+
+ SetupStepVddrTrimTo(( HWREG( FCFG1_BASE + FCFG1_O_VOLT_TRIM ) &
+ FCFG1_VOLT_TRIM_VDDR_TRIM_HH_M ) >>
+ FCFG1_VOLT_TRIM_VDDR_TRIM_HH_S ) ;
+ }
+
+ // 1.
+ // Do not allow DCDC to be enabled if in external regulator mode.
+ // Preventing this by setting both the RECHARGE and the ACTIVE bits bit in the CCFG_MODE_CONF copy register (ccfg_ModeConfReg).
+ //
+ // 2.
+ // Adjusted battery monitor low limit in internal regulator mode.
+ // This is done by setting AON_BATMON_FLASHPUMPP0_LOWLIM=0 in internal regulator mode.
+ if ( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ) & AON_PMCTL_PWRCTL_EXT_REG_MODE ) {
+ ccfg_ModeConfReg |= ( CCFG_MODE_CONF_DCDC_RECHARGE_M | CCFG_MODE_CONF_DCDC_ACTIVE_M );
+ } else {
+ HWREGBITW( AON_BATMON_BASE + AON_BATMON_O_FLASHPUMPP0, AON_BATMON_FLASHPUMPP0_LOWLIM_BITN ) = 0;
+ }
+
+ // set the RECHARGE source based upon CCFG:MODE_CONF:DCDC_RECHARGE
+ // Note: Inverse polarity
+ HWREGBITW( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL, AON_PMCTL_PWRCTL_DCDC_EN_BITN ) =
+ ((( ccfg_ModeConfReg >> CCFG_MODE_CONF_DCDC_RECHARGE_S ) & 1 ) ^ 1 );
+
+ // set the ACTIVE source based upon CCFG:MODE_CONF:DCDC_ACTIVE
+ // Note: Inverse polarity
+ HWREGBITW( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL, AON_PMCTL_PWRCTL_DCDC_ACTIVE_BITN ) =
+ ((( ccfg_ModeConfReg >> CCFG_MODE_CONF_DCDC_ACTIVE_S ) & 1 ) ^ 1 );
+}
+
+//*****************************************************************************
+//
+// SetupAfterColdResetWakeupFromShutDownCfg2
+//
+//*****************************************************************************
+void
+SetupAfterColdResetWakeupFromShutDownCfg2( uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg )
+{
+ uint32_t ui32Trim;
+
+ // Following sequence is required for using XOSCHF, if not included
+ // devices crashes when trying to switch to XOSCHF.
+ //
+ // Trim CAP settings. Get and set trim value for the ANABYPASS_VALUE1
+ // register
+ ui32Trim = SetupGetTrimForAnabypassValue1( ccfg_ModeConfReg );
+ DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL1, ui32Trim);
+
+ // Trim RCOSC_LF. Get and set trim values for the RCOSCLF_RTUNE_TRIM and
+ // RCOSCLF_CTUNE_TRIM fields in the XOSCLF_RCOSCLF_CTRL register.
+ ui32Trim = SetupGetTrimForRcOscLfRtuneCtuneTrim();
+ DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_LFOSCCTL,
+ (DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_M |
+ DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_M),
+ DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S,
+ ui32Trim);
+
+ // Trim XOSCHF IBIAS THERM. Get and set trim value for the
+ // XOSCHF IBIAS THERM bit field in the ANABYPASS_VALUE2 register. Other
+ // register bit fields are set to 0.
+ ui32Trim = SetupGetTrimForXoscHfIbiastherm();
+ DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL2,
+ ui32Trim<<DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_S);
+
+ // Trim AMPCOMP settings required before switch to XOSCHF
+ ui32Trim = SetupGetTrimForAmpcompTh2();
+ DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_AMPCOMPTH2, ui32Trim);
+ ui32Trim = SetupGetTrimForAmpcompTh1();
+ DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_AMPCOMPTH1, ui32Trim);
+#if ( CCFG_BASE == CCFG_BASE_DEFAULT )
+ ui32Trim = SetupGetTrimForAmpcompCtrl( ui32Fcfg1Revision );
+#else
+ ui32Trim = NOROM_SetupGetTrimForAmpcompCtrl( ui32Fcfg1Revision );
+#endif
+ DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_AMPCOMPCTL, ui32Trim);
+
+ // Set trim for DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN in accordance to FCFG1 setting
+ // This is bit[5] in the DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL register
+ // Using MASK4 write + 1 => writing to bits[7:4]
+ ui32Trim = SetupGetTrimForAdcShModeEn( ui32Fcfg1Revision );
+ HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 1 ) =
+ ( 0x20 | ( ui32Trim << 1 ));
+
+ // Set trim for DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN in accordance to FCFG1 setting
+ // This is bit[4] in the DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL register
+ // Using MASK4 write + 1 => writing to bits[7:4]
+ ui32Trim = SetupGetTrimForAdcShVbufEn( ui32Fcfg1Revision );
+ HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 1 ) =
+ ( 0x10 | ( ui32Trim ));
+
+ // Set trim for the PEAK_DET_ITRIM, HP_BUF_ITRIM and LP_BUF_ITRIM bit fields
+ // in the DDI0_OSC_O_XOSCHFCTL register in accordance to FCFG1 setting.
+ // Remaining register bit fields are set to their reset values of 0.
+ ui32Trim = SetupGetTrimForXoscHfCtl(ui32Fcfg1Revision);
+ DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_XOSCHFCTL, ui32Trim);
+
+ // Set trim for DBLR_LOOP_FILTER_RESET_VOLTAGE in accordance to FCFG1 setting
+ // (This is bits [18:17] in DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL)
+ // (Using MASK4 write + 4 => writing to bits[19:16] => (4*4))
+ // (Assuming: DDI_0_OSC_ADCDOUBLERNANOAMPCTL_DBLR_LOOP_FILTER_RESET_VOLTAGE_S = 17 and
+ // that DDI_0_OSC_ADCDOUBLERNANOAMPCTL_DBLR_LOOP_FILTER_RESET_VOLTAGE_M = 0x00060000)
+ ui32Trim = SetupGetTrimForDblrLoopFilterResetVoltage( ui32Fcfg1Revision );
+ HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 4 ) =
+ ( 0x60 | ( ui32Trim << 1 ));
+
+ // Update DDI_0_OSC_ATESTCTL_ATESTLF_RCOSCLF_IBIAS_TRIM with data from
+ // FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM
+ // This is DDI_0_OSC_O_ATESTCTL bit[7]
+ // ( DDI_0_OSC_O_ATESTCTL is currently hidden (but=0x00000020))
+ // Using MASK4 write + 1 => writing to bits[7:4]
+ ui32Trim = SetupGetTrimForRcOscLfIBiasTrim( ui32Fcfg1Revision );
+ HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( 0x00000020 * 2 ) + 1 ) =
+ ( 0x80 | ( ui32Trim << 3 ));
+
+ // Update DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM and
+ // DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO in one write
+ // This can be simplified since the registers are packed together in the same
+ // order both in FCFG1 and in the HW register.
+ // This spans DDI_0_OSC_O_LFOSCCTL bits[23:18]
+ // Using MASK8 write + 4 => writing to bits[23:16]
+ ui32Trim = SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio( ui32Fcfg1Revision );
+ HWREGH( AUX_DDI0_OSC_BASE + DDI_O_MASK8B + ( DDI_0_OSC_O_LFOSCCTL * 2 ) + 4 ) =
+ ( 0xFC00 | ( ui32Trim << 2 ));
+
+ // Set trim the HPM_IBIAS_WAIT_CNT, LPM_IBIAS_WAIT_CNT and IDAC_STEP bit
+ // fields in the DDI0_OSC_O_RADCEXTCFG register in accordance to FCFG1 setting.
+ // Remaining register bit fields are set to their reset values of 0.
+ ui32Trim = SetupGetTrimForRadcExtCfg(ui32Fcfg1Revision);
+ DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_RADCEXTCFG, ui32Trim);
+
+}
+
+//*****************************************************************************
+//
+// SetupAfterColdResetWakeupFromShutDownCfg3
+//
+//*****************************************************************************
+void
+SetupAfterColdResetWakeupFromShutDownCfg3( uint32_t ccfg_ModeConfReg )
+{
+ uint32_t fcfg1OscConf;
+ uint32_t ui32Trim;
+ uint32_t currentHfClock;
+ uint32_t ccfgExtLfClk;
+
+ // Examine the XOSC_FREQ field to select 0x1=HPOSC, 0x2=48MHz XOSC, 0x3=24MHz XOSC
+ switch (( ccfg_ModeConfReg & CCFG_MODE_CONF_XOSC_FREQ_M ) >> CCFG_MODE_CONF_XOSC_FREQ_S ) {
+ case 2 :
+ // XOSC source is a 48 MHz crystal
+ // Do nothing (since this is the reset setting)
+ break;
+ case 1 :
+ // XOSC source is HPOSC (trim the HPOSC if this is a chip with HPOSC, otherwise skip trimming and default to 24 MHz XOSC)
+
+ fcfg1OscConf = HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF );
+
+ if (( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_OPTION ) == 0 ) {
+ // This is a HPOSC chip, apply HPOSC settings
+ // Set bit DDI_0_OSC_CTL0_HPOSC_MODE_EN (this is bit 14 in DDI_0_OSC_O_CTL0)
+ HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_HPOSC_MODE_EN;
+
+ // ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN = FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN (1 bit)
+ // ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO = FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO (4 bits)
+ // ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET = FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET (4 bits)
+ // ADI_2_REFSYS_HPOSCCTL0_FILTER_EN = FCFG1_OSC_CONF_HPOSC_FILTER_EN (1 bit)
+ // ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY = FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY (2 bits)
+ // ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP = FCFG1_OSC_CONF_HPOSC_SERIES_CAP (2 bits)
+ // ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS = FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS (1 bit)
+
+ HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL2 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL2 ) &
+ ~( ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_M | ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_M ) ) |
+ ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_S ) << ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_S ) |
+ ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_M ) >> FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_S ) << ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_S ) );
+ HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL1 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL1 ) & ~( ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_M ) ) |
+ ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_S ) << ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_S ) );
+ HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL0 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL0 ) &
+ ~( ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_M | ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_M | ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_M | ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_M )) |
+ ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_FILTER_EN_M ) >> FCFG1_OSC_CONF_HPOSC_FILTER_EN_S ) << ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_S ) |
+ ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_S ) << ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_S ) |
+ ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_SERIES_CAP_M ) >> FCFG1_OSC_CONF_HPOSC_SERIES_CAP_S ) << ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_S ) |
+ ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_M ) >> FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_S ) << ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_S ) );
+ break;
+ }
+ // Not a HPOSC chip - fall through to default
+ default :
+ // XOSC source is a 24 MHz crystal (default)
+ // Set bit DDI_0_OSC_CTL0_XTAL_IS_24M (this is bit 31 in DDI_0_OSC_O_CTL0)
+ HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_XTAL_IS_24M;
+ break;
+ }
+
+ // Set XOSC_HF in bypass mode if CCFG is configured for external TCXO
+ // Please note that it is up to the customer to make sure that the external clock source is up and running before XOSC_HF can be used.
+ if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO ) == 0 ) {
+ HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_XOSCHFCTL ) = DDI_0_OSC_XOSCHFCTL_BYPASS;
+ }
+
+ // Clear DDI_0_OSC_CTL0_CLK_LOSS_EN (ClockLossEventEnable()). This is bit 9 in DDI_0_OSC_O_CTL0.
+ // This is typically already 0 except on Lizard where it is set in ROM-boot
+ HWREG( AUX_DDI0_OSC_BASE + DDI_O_CLR + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_CLK_LOSS_EN;
+
+ // Setting DDI_0_OSC_CTL1_XOSC_HF_FAST_START according to value found in FCFG1
+ ui32Trim = SetupGetTrimForXoscHfFastStart();
+ HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_CTL1 * 2 )) = ( 0x30 | ui32Trim );
+
+ // setup the LF clock based upon CCFG:MODE_CONF:SCLK_LF_OPTION
+ switch (( ccfg_ModeConfReg & CCFG_MODE_CONF_SCLK_LF_OPTION_M ) >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) {
+ case 0 : // XOSC_HF_DLF (XOSCHF/1536) -> SCLK_LF (=31250 Hz)
+ OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_XOSC_HF );
+ SetupSetAonRtcSubSecInc( 0x8637BD ); // RTC_INCREMENT = 2^38 / frequency
+ break;
+ case 1 : // EXTERNAL signal -> SCLK_LF (frequency=2^38/CCFG_EXT_LF_CLK_RTC_INCREMENT)
+ // Set SCLK_LF to use the same source as SCLK_HF
+ // Can be simplified a bit since possible return values for HF matches LF settings
+ currentHfClock = OSCClockSourceGet( OSC_SRC_CLK_HF );
+ OSCClockSourceSet( OSC_SRC_CLK_LF, currentHfClock );
+ while( OSCClockSourceGet( OSC_SRC_CLK_LF ) != currentHfClock ) {
+ // Wait until switched
+ }
+ ccfgExtLfClk = HWREG( CCFG_BASE + CCFG_O_EXT_LF_CLK );
+ SetupSetAonRtcSubSecInc(( ccfgExtLfClk & CCFG_EXT_LF_CLK_RTC_INCREMENT_M ) >> CCFG_EXT_LF_CLK_RTC_INCREMENT_S );
+ IOCPortConfigureSet(( ccfgExtLfClk & CCFG_EXT_LF_CLK_DIO_M ) >> CCFG_EXT_LF_CLK_DIO_S,
+ IOC_PORT_AON_CLK32K,
+ IOC_STD_INPUT | IOC_HYST_ENABLE ); // Route external clock to AON IOC w/hysteresis
+ // Set XOSC_LF in bypass mode to allow external 32 kHz clock
+ HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS;
+ // Fall through to set XOSC_LF as SCLK_LF source
+ case 2 : // XOSC_LF -> SLCK_LF (32768 Hz)
+ OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_XOSC_LF );
+ break;
+ default : // (=3) RCOSC_LF
+ OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_RCOSC_LF );
+ break;
+ }
+
+ // Update ADI_4_AUX_ADCREF1_VTRIM with value from FCFG1
+ HWREGB( AUX_ADI4_BASE + ADI_4_AUX_O_ADCREF1 ) =
+ ((( HWREG( FCFG1_BASE + FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT ) >>
+ FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_S ) <<
+ ADI_4_AUX_ADCREF1_VTRIM_S ) &
+ ADI_4_AUX_ADCREF1_VTRIM_M );
+
+ // Sync with AON
+ SysCtrlAonSync();
+}
+
+//*****************************************************************************
+//
+// SetupGetTrimForAnabypassValue1
+//
+//*****************************************************************************
+uint32_t
+SetupGetTrimForAnabypassValue1( uint32_t ccfg_ModeConfReg )
+{
+ uint32_t ui32Fcfg1Value ;
+ uint32_t ui32XoscHfRow ;
+ uint32_t ui32XoscHfCol ;
+ uint32_t ui32TrimValue ;
+
+ // Use device specific trim values located in factory configuration
+ // area for the XOSC_HF_COLUMN_Q12 and XOSC_HF_ROW_Q12 bit fields in
+ // the ANABYPASS_VALUE1 register. Value for the other bit fields
+ // are set to 0.
+
+ ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP);
+ ui32XoscHfRow = (( ui32Fcfg1Value &
+ FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_M ) >>
+ FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_S );
+ ui32XoscHfCol = (( ui32Fcfg1Value &
+ FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_M ) >>
+ FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_S );
+
+ if (( ccfg_ModeConfReg & CCFG_MODE_CONF_XOSC_CAP_MOD ) == 0 ) {
+ // XOSC_CAP_MOD = 0 means: CAP_ARRAY_DELTA is in use -> Apply compensation
+ // XOSC_CAPARRAY_DELTA is located in bit[15:8] of ccfg_ModeConfReg
+ // Note: HW_REV_DEPENDENT_IMPLEMENTATION. Field width is not given by
+ // a define and sign extension must therefore be hard coded.
+ // ( A small test program is created verifying the code lines below:
+ // Ref.: ..\test\small_standalone_test_programs\CapArrayDeltaAdjust_test.c)
+ int32_t i32CustomerDeltaAdjust =
+ (((int32_t)( ccfg_ModeConfReg << ( 32 - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S )))
+ >> ( 32 - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W ));
+
+ while ( i32CustomerDeltaAdjust < 0 ) {
+ ui32XoscHfCol >>= 1; // COL 1 step down
+ if ( ui32XoscHfCol == 0 ) { // if COL below minimum
+ ui32XoscHfCol = 0xFFFF; // Set COL to maximum
+ ui32XoscHfRow >>= 1; // ROW 1 step down
+ if ( ui32XoscHfRow == 0 ) { // if ROW below minimum
+ ui32XoscHfRow = 1; // Set both ROW and COL
+ ui32XoscHfCol = 1; // to minimum
+ }
+ }
+ i32CustomerDeltaAdjust++;
+ }
+ while ( i32CustomerDeltaAdjust > 0 ) {
+ ui32XoscHfCol = ( ui32XoscHfCol << 1 ) | 1; // COL 1 step up
+ if ( ui32XoscHfCol > 0xFFFF ) { // if COL above maximum
+ ui32XoscHfCol = 1; // Set COL to minimum
+ ui32XoscHfRow = ( ui32XoscHfRow << 1 ) | 1; // ROW 1 step up
+ if ( ui32XoscHfRow > 0xF ) { // if ROW above maximum
+ ui32XoscHfRow = 0xF; // Set both ROW and COL
+ ui32XoscHfCol = 0xFFFF; // to maximum
+ }
+ }
+ i32CustomerDeltaAdjust--;
+ }
+ }
+
+ ui32TrimValue = (( ui32XoscHfRow << DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_S ) |
+ ( ui32XoscHfCol << DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_S ) );
+
+ return (ui32TrimValue);
+}
+
+//*****************************************************************************
+//
+// SetupGetTrimForRcOscLfRtuneCtuneTrim
+//
+//*****************************************************************************
+uint32_t
+SetupGetTrimForRcOscLfRtuneCtuneTrim( void )
+{
+ uint32_t ui32TrimValue;
+
+ // Use device specific trim values located in factory configuration
+ // area
+ ui32TrimValue =
+ ((HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP) &
+ FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_M)>>
+ FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_S)<<
+ DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S;
+
+ ui32TrimValue |=
+ ((HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP) &
+ FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_M)>>
+ FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_S)<<
+ DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_S;
+
+ return(ui32TrimValue);
+}
+
+//*****************************************************************************
+//
+// SetupGetTrimForXoscHfIbiastherm
+//
+//*****************************************************************************
+uint32_t
+SetupGetTrimForXoscHfIbiastherm( void )
+{
+ uint32_t ui32TrimValue;
+
+ // Use device specific trim value located in factory configuration
+ // area
+ ui32TrimValue =
+ (HWREG(FCFG1_BASE + FCFG1_O_ANABYPASS_VALUE2) &
+ FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_M)>>
+ FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_S;
+
+ return(ui32TrimValue);
+}
+
+//*****************************************************************************
+//
+// SetupGetTrimForAmpcompTh2
+//
+//*****************************************************************************
+uint32_t
+SetupGetTrimForAmpcompTh2( void )
+{
+ uint32_t ui32TrimValue;
+ uint32_t ui32Fcfg1Value;
+
+ // Use device specific trim value located in factory configuration
+ // area. All defined register bit fields have corresponding trim
+ // value in the factory configuration area
+ ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_AMPCOMP_TH2);
+ ui32TrimValue = ((ui32Fcfg1Value &
+ FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_M)>>
+ FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_S)<<
+ DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_S;
+ ui32TrimValue |= (((ui32Fcfg1Value &
+ FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_M)>>
+ FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_S)<<
+ DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_S);
+ ui32TrimValue |= (((ui32Fcfg1Value &
+ FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_M)>>
+ FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_S)<<
+ DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_S);
+ ui32TrimValue |= (((ui32Fcfg1Value &
+ FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_M)>>
+ FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_S)<<
+ DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_S);
+
+ return(ui32TrimValue);
+}
+
+//*****************************************************************************
+//
+// SetupGetTrimForAmpcompTh1
+//
+//*****************************************************************************
+uint32_t
+SetupGetTrimForAmpcompTh1( void )
+{
+ uint32_t ui32TrimValue;
+ uint32_t ui32Fcfg1Value;
+
+ // Use device specific trim values located in factory configuration
+ // area. All defined register bit fields have a corresponding trim
+ // value in the factory configuration area
+ ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_AMPCOMP_TH1);
+ ui32TrimValue = (((ui32Fcfg1Value &
+ FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_M)>>
+ FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_S)<<
+ DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_S);
+ ui32TrimValue |= (((ui32Fcfg1Value &
+ FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_M)>>
+ FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_S)<<
+ DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_S);
+ ui32TrimValue |= (((ui32Fcfg1Value &
+ FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_M)>>
+ FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_S)<<
+ DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_S);
+ ui32TrimValue |= (((ui32Fcfg1Value &
+ FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_M)>>
+ FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_S)<<
+ DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_S);
+
+ return(ui32TrimValue);
+}
+
+//*****************************************************************************
+//
+// SetupGetTrimForAmpcompCtrl
+//
+//*****************************************************************************
+uint32_t
+SetupGetTrimForAmpcompCtrl( uint32_t ui32Fcfg1Revision )
+{
+ uint32_t ui32TrimValue ;
+ uint32_t ui32Fcfg1Value ;
+ uint32_t ibiasOffset ;
+ uint32_t ibiasInit ;
+ uint32_t modeConf1 ;
+ int32_t deltaAdjust ;
+
+ // Use device specific trim values located in factory configuration
+ // area. Register bit fields without trim values in the factory
+ // configuration area will be set to the value of 0.
+ ui32Fcfg1Value = HWREG( FCFG1_BASE + FCFG1_O_AMPCOMP_CTRL1 );
+
+ ibiasOffset = ( ui32Fcfg1Value &
+ FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_M ) >>
+ FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_S ;
+ ibiasInit = ( ui32Fcfg1Value &
+ FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_M ) >>
+ FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_S ;
+
+ if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M ) == 0 ) {
+ // Adjust with DELTA_IBIAS_OFFSET and DELTA_IBIAS_INIT from CCFG
+ modeConf1 = HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 );
+
+ // Both fields are signed 4-bit values. This is an assumption when doing the sign extension.
+ deltaAdjust =
+ (((int32_t)( modeConf1 << ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S )))
+ >> ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W ));
+ deltaAdjust += (int32_t)ibiasOffset;
+ if ( deltaAdjust < 0 ) {
+ deltaAdjust = 0;
+ }
+ if ( deltaAdjust > ( DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S )) {
+ deltaAdjust = ( DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S );
+ }
+ ibiasOffset = (uint32_t)deltaAdjust;
+
+ deltaAdjust =
+ (((int32_t)( modeConf1 << ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S )))
+ >> ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W ));
+ deltaAdjust += (int32_t)ibiasInit;
+ if ( deltaAdjust < 0 ) {
+ deltaAdjust = 0;
+ }
+ if ( deltaAdjust > ( DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S )) {
+ deltaAdjust = ( DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S );
+ }
+ ibiasInit = (uint32_t)deltaAdjust;
+ }
+ ui32TrimValue = ( ibiasOffset << DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S ) |
+ ( ibiasInit << DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S ) ;
+
+ ui32TrimValue |= (((ui32Fcfg1Value &
+ FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_M)>>
+ FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_S)<<
+ DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_S);
+ ui32TrimValue |= (((ui32Fcfg1Value &
+ FCFG1_AMPCOMP_CTRL1_CAP_STEP_M)>>
+ FCFG1_AMPCOMP_CTRL1_CAP_STEP_S)<<
+ DDI_0_OSC_AMPCOMPCTL_CAP_STEP_S);
+ ui32TrimValue |= (((ui32Fcfg1Value &
+ FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_M)>>
+ FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_S)<<
+ DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_S);
+
+ if ( ui32Fcfg1Revision >= 0x00000022 ) {
+ ui32TrimValue |= ((( ui32Fcfg1Value &
+ FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_M ) >>
+ FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_S ) <<
+ DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_S );
+ }
+
+ return(ui32TrimValue);
+}
+
+//*****************************************************************************
+//
+// SetupGetTrimForDblrLoopFilterResetVoltage
+//
+//*****************************************************************************
+uint32_t
+SetupGetTrimForDblrLoopFilterResetVoltage( uint32_t ui32Fcfg1Revision )
+{
+ uint32_t dblrLoopFilterResetVoltageValue = 0; // Reset value
+
+ if ( ui32Fcfg1Revision >= 0x00000020 ) {
+ dblrLoopFilterResetVoltageValue = ( HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 ) &
+ FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_M ) >>
+ FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_S;
+ }
+
+ return ( dblrLoopFilterResetVoltageValue );
+}
+
+//*****************************************************************************
+//
+// SetupGetTrimForAdcShModeEn
+//
+//*****************************************************************************
+uint32_t
+SetupGetTrimForAdcShModeEn( uint32_t ui32Fcfg1Revision )
+{
+ uint32_t getTrimForAdcShModeEnValue = 1; // Recommended default setting
+
+ if ( ui32Fcfg1Revision >= 0x00000022 ) {
+ getTrimForAdcShModeEnValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) &
+ FCFG1_OSC_CONF_ADC_SH_MODE_EN_M ) >>
+ FCFG1_OSC_CONF_ADC_SH_MODE_EN_S;
+ }
+
+ return ( getTrimForAdcShModeEnValue );
+}
+
+//*****************************************************************************
+//
+// SetupGetTrimForAdcShVbufEn
+//
+//*****************************************************************************
+uint32_t
+SetupGetTrimForAdcShVbufEn( uint32_t ui32Fcfg1Revision )
+{
+ uint32_t getTrimForAdcShVbufEnValue = 1; // Recommended default setting
+
+ if ( ui32Fcfg1Revision >= 0x00000022 ) {
+ getTrimForAdcShVbufEnValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) &
+ FCFG1_OSC_CONF_ADC_SH_VBUF_EN_M ) >>
+ FCFG1_OSC_CONF_ADC_SH_VBUF_EN_S;
+ }
+
+ return ( getTrimForAdcShVbufEnValue );
+}
+
+//*****************************************************************************
+//
+// SetupGetTrimForXoscHfCtl
+//
+//*****************************************************************************
+uint32_t
+SetupGetTrimForXoscHfCtl( uint32_t ui32Fcfg1Revision )
+{
+ uint32_t getTrimForXoschfCtlValue = 0; // Recommended default setting
+ uint32_t fcfg1Data;
+
+ if ( ui32Fcfg1Revision >= 0x00000020 ) {
+ fcfg1Data = HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 );
+ getTrimForXoschfCtlValue =
+ ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_M ) >>
+ FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_S ) <<
+ DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_S);
+
+ getTrimForXoschfCtlValue |=
+ ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_M ) >>
+ FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_S ) <<
+ DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_S);
+
+ getTrimForXoschfCtlValue |=
+ ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_M ) >>
+ FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_S ) <<
+ DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_S);
+ }
+
+ return ( getTrimForXoschfCtlValue );
+}
+
+//*****************************************************************************
+//
+// SetupGetTrimForXoscHfFastStart
+//
+//*****************************************************************************
+uint32_t
+SetupGetTrimForXoscHfFastStart( void )
+{
+ uint32_t ui32XoscHfFastStartValue ;
+
+ // Get value from FCFG1
+ ui32XoscHfFastStartValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) &
+ FCFG1_OSC_CONF_XOSC_HF_FAST_START_M ) >>
+ FCFG1_OSC_CONF_XOSC_HF_FAST_START_S;
+
+ return ( ui32XoscHfFastStartValue );
+}
+
+//*****************************************************************************
+//
+// SetupGetTrimForRadcExtCfg
+//
+//*****************************************************************************
+uint32_t
+SetupGetTrimForRadcExtCfg( uint32_t ui32Fcfg1Revision )
+{
+ uint32_t getTrimForRadcExtCfgValue = 0x403F8000; // Recommended default setting
+ uint32_t fcfg1Data;
+
+ if ( ui32Fcfg1Revision >= 0x00000020 ) {
+ fcfg1Data = HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 );
+ getTrimForRadcExtCfgValue =
+ ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_M ) >>
+ FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_S ) <<
+ DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_S);
+
+ getTrimForRadcExtCfgValue |=
+ ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_M ) >>
+ FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_S ) <<
+ DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_S);
+
+ getTrimForRadcExtCfgValue |=
+ ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_IDAC_STEP_M ) >>
+ FCFG1_MISC_OTP_DATA_1_IDAC_STEP_S ) <<
+ DDI_0_OSC_RADCEXTCFG_IDAC_STEP_S);
+ }
+
+ return ( getTrimForRadcExtCfgValue );
+}
+
+//*****************************************************************************
+//
+// SetupGetTrimForRcOscLfIBiasTrim
+//
+//*****************************************************************************
+uint32_t
+SetupGetTrimForRcOscLfIBiasTrim( uint32_t ui32Fcfg1Revision )
+{
+ uint32_t trimForRcOscLfIBiasTrimValue = 0; // Default value
+
+ if ( ui32Fcfg1Revision >= 0x00000022 ) {
+ trimForRcOscLfIBiasTrimValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) &
+ FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_M ) >>
+ FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_S ;
+ }
+
+ return ( trimForRcOscLfIBiasTrimValue );
+}
+
+//*****************************************************************************
+//
+// SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio
+//
+//*****************************************************************************
+uint32_t
+SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio( uint32_t ui32Fcfg1Revision )
+{
+ uint32_t trimForXoscLfRegulatorAndCmirrwrRatioValue = 0; // Default value for both fields
+
+ if ( ui32Fcfg1Revision >= 0x00000022 ) {
+ trimForXoscLfRegulatorAndCmirrwrRatioValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) &
+ ( FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_M |
+ FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_M )) >>
+ FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_S ;
+ }
+
+ return ( trimForXoscLfRegulatorAndCmirrwrRatioValue );
+}
+
+//*****************************************************************************
+//
+// SetupSetCacheModeAccordingToCcfgSetting
+//
+//*****************************************************************************
+void
+SetupSetCacheModeAccordingToCcfgSetting( void )
+{
+ // - Make sure to enable aggressive VIMS clock gating for power optimization
+ // Only for PG2 devices.
+ // - Enable cache prefetch enable as default setting
+ // (Slightly higher power consumption, but higher CPU performance)
+ // - IF ( CCFG_..._DIS_GPRAM == 1 )
+ // then: Enable cache (set cache mode = 1), even if set by ROM boot code
+ // (This is done because it's not set by boot code when running inside
+ // a debugger supporting the Halt In Boot (HIB) functionality).
+ // else: Set MODE_GPRAM if not already set (see inline comments as well)
+ uint32_t vimsCtlMode0 ;
+
+ while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) {
+ // Do nothing - wait for an eventual ongoing mode change to complete.
+ // (There should typically be no wait time here, but need to be sure)
+ }
+
+ // Note that Mode=0 is equal to MODE_GPRAM
+ vimsCtlMode0 = (( HWREG( VIMS_BASE + VIMS_O_CTL ) & ~VIMS_CTL_MODE_M ) | VIMS_CTL_DYN_CG_EN_M | VIMS_CTL_PREF_EN_M );
+
+
+ if ( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM ) {
+ // Enable cache (and hence disable GPRAM)
+ HWREG( VIMS_BASE + VIMS_O_CTL ) = ( vimsCtlMode0 | VIMS_CTL_MODE_CACHE );
+ } else if (( HWREG( VIMS_BASE + VIMS_O_STAT ) & VIMS_STAT_MODE_M ) != VIMS_STAT_MODE_GPRAM ) {
+ // GPRAM is enabled in CCFG but not selected
+ // Note: It is recommended to go via MODE_OFF when switching to MODE_GPRAM
+ HWREG( VIMS_BASE + VIMS_O_CTL ) = ( vimsCtlMode0 | VIMS_CTL_MODE_OFF );
+ while (( HWREG( VIMS_BASE + VIMS_O_STAT ) & VIMS_STAT_MODE_M ) != VIMS_STAT_MODE_OFF ) {
+ // Do nothing - wait for an eventual mode change to complete (This goes fast).
+ }
+ HWREG( VIMS_BASE + VIMS_O_CTL ) = vimsCtlMode0;
+ } else {
+ // Correct mode, but make sure PREF_EN and DYN_CG_EN always are set
+ HWREG( VIMS_BASE + VIMS_O_CTL ) = vimsCtlMode0;
+ }
+}
+
+//*****************************************************************************
+//
+// SetupSetAonRtcSubSecInc
+//
+//*****************************************************************************
+void
+SetupSetAonRtcSubSecInc( uint32_t subSecInc )
+{
+ // Loading a new RTCSUBSECINC value is done in 5 steps:
+ // 1. Write bit[15:0] of new SUBSECINC value to AUX_SYSIF_O_RTCSUBSECINC0
+ // 2. Write bit[23:16] of new SUBSECINC value to AUX_SYSIF_O_RTCSUBSECINC1
+ // 3. Set AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ
+ // 4. Wait for AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK
+ // 5. Clear AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ
+ HWREG( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINC0 ) = (( subSecInc ) & AUX_SYSIF_RTCSUBSECINC0_INC15_0_M );
+ HWREG( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINC1 ) = (( subSecInc >> 16 ) & AUX_SYSIF_RTCSUBSECINC1_INC23_16_M );
+
+ HWREG( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINCCTL ) = AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ;
+ while( ! ( HWREGBITW( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINCCTL, AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK_BITN )));
+ HWREG( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINCCTL ) = 0;
+}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/setup_rom.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/setup_rom.h
new file mode 100644
index 0000000..e06ba29
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/setup_rom.h
@@ -0,0 +1,469 @@
+/******************************************************************************
+* Filename: setup_rom.h
+* Revised: 2018-10-24 11:23:04 +0200 (Wed, 24 Oct 2018)
+* Revision: 52993
+*
+* Description: Prototypes and defines for the setup API.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup system_control_group
+//! @{
+//! \addtogroup setup_rom_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __SETUP_ROM_H__
+#define __SETUP_ROM_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+// Hardware headers
+#include "../inc/hw_types.h"
+// Driverlib headers
+// - None needed
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// This section renames all functions that are not "static inline", so that
+// calling these functions will default to implementation in flash. At the end
+// of this file a second renaming will change the defaults to implementation in
+// ROM for available functions.
+//
+// To force use of the implementation in flash, e.g. for debugging:
+// - Globally: Define DRIVERLIB_NOROM at project level
+// - Per function: Use prefix "NOROM_" when calling the function
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #define SetupAfterColdResetWakeupFromShutDownCfg1 NOROM_SetupAfterColdResetWakeupFromShutDownCfg1
+ #define SetupAfterColdResetWakeupFromShutDownCfg2 NOROM_SetupAfterColdResetWakeupFromShutDownCfg2
+ #define SetupAfterColdResetWakeupFromShutDownCfg3 NOROM_SetupAfterColdResetWakeupFromShutDownCfg3
+ #define SetupGetTrimForAdcShModeEn NOROM_SetupGetTrimForAdcShModeEn
+ #define SetupGetTrimForAdcShVbufEn NOROM_SetupGetTrimForAdcShVbufEn
+ #define SetupGetTrimForAmpcompCtrl NOROM_SetupGetTrimForAmpcompCtrl
+ #define SetupGetTrimForAmpcompTh1 NOROM_SetupGetTrimForAmpcompTh1
+ #define SetupGetTrimForAmpcompTh2 NOROM_SetupGetTrimForAmpcompTh2
+ #define SetupGetTrimForAnabypassValue1 NOROM_SetupGetTrimForAnabypassValue1
+ #define SetupGetTrimForDblrLoopFilterResetVoltage NOROM_SetupGetTrimForDblrLoopFilterResetVoltage
+ #define SetupGetTrimForRadcExtCfg NOROM_SetupGetTrimForRadcExtCfg
+ #define SetupGetTrimForRcOscLfIBiasTrim NOROM_SetupGetTrimForRcOscLfIBiasTrim
+ #define SetupGetTrimForRcOscLfRtuneCtuneTrim NOROM_SetupGetTrimForRcOscLfRtuneCtuneTrim
+ #define SetupGetTrimForXoscHfCtl NOROM_SetupGetTrimForXoscHfCtl
+ #define SetupGetTrimForXoscHfFastStart NOROM_SetupGetTrimForXoscHfFastStart
+ #define SetupGetTrimForXoscHfIbiastherm NOROM_SetupGetTrimForXoscHfIbiastherm
+ #define SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio NOROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio
+ #define SetupSetCacheModeAccordingToCcfgSetting NOROM_SetupSetCacheModeAccordingToCcfgSetting
+ #define SetupSetAonRtcSubSecInc NOROM_SetupSetAonRtcSubSecInc
+ #define SetupStepVddrTrimTo NOROM_SetupStepVddrTrimTo
+#endif
+
+//*****************************************************************************
+//
+//! \brief First part of configuration required after cold reset and when waking up from shutdown.
+//!
+//! Configures the following based on settings in CCFG (Customer Configuration area:
+//! - Boost mode for CC13xx devices
+//! - Minimal VDDR voltage threshold used during sleep mode
+//! - DCDC functionality:
+//! - Selects if DCDC or GLDO regulator will be used for VDDR in active mode
+//! - Selects if DCDC or GLDO regulator will be used for VDDR in sleep mode
+//!
+//! In addition the battery monitor low limit for internal regulator mode is set
+//! to a hard coded value.
+//!
+//! \param ccfg_ModeConfReg is the value of the CCFG_O_MODE_CONF_1 register
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void SetupAfterColdResetWakeupFromShutDownCfg1( uint32_t ccfg_ModeConfReg );
+
+//*****************************************************************************
+//
+//! \brief Second part of configuration required after cold reset and when waking up from shutdown.
+//!
+//! Configures and trims functionalites required for use of XOSC_HF.
+//! The configurations and trimmings are based on settings in FCFG1 (Factory
+//! Configuration area) and partly on \c ccfg_ModeConfReg.
+//!
+//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register
+//! \param ccfg_ModeConfReg is the value of the CCFG_O_MODE_CONF_1 register
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void SetupAfterColdResetWakeupFromShutDownCfg2( uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg );
+
+//*****************************************************************************
+//
+//! \brief Third part of configuration required after cold reset and when waking up from shutdown.
+//!
+//! Configures the following:
+//! - XOSC source selection based on \c ccfg_ModeConfReg. If HPOSC is selected on a
+//! HPOSC device the oscillator is configured based on settings in FCFG1 (Factory
+//! Configuration area).
+//! - Clock loss detection is disabled. Will be re-enabled by TIRTOS power driver.
+//! - Duration of the XOSC_HF fast startup mode based on FCFG1 setting.
+//! - SCLK_LF based on \c ccfg_ModeConfReg.
+//! - Output voltage of ADC fixed reference based on FCFG1 setting.
+//!
+//! \param ccfg_ModeConfReg is the value of the CCFG_O_MODE_CONF_1 register
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void SetupAfterColdResetWakeupFromShutDownCfg3( uint32_t ccfg_ModeConfReg );
+
+//*****************************************************************************
+//
+//! \brief Returns the trim value from FCFG1 to be used as ADC_SH_MODE_EN setting.
+//!
+//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register
+//!
+//! \return Returns the trim value from FCFG1.
+//
+//*****************************************************************************
+extern uint32_t SetupGetTrimForAdcShModeEn( uint32_t ui32Fcfg1Revision );
+
+//*****************************************************************************
+//
+//! \brief Returns the trim value from FCFG1 to be used as ADC_SH_VBUF_EN setting.
+//!
+//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register
+//!
+//! \return Returns the trim value from FCFG1.
+//
+//*****************************************************************************
+extern uint32_t SetupGetTrimForAdcShVbufEn( uint32_t ui32Fcfg1Revision );
+
+//*****************************************************************************
+//
+//! \brief Returns the trim value to be used for the AMPCOMP_CTRL register in OSC_DIG.
+//!
+//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register
+//!
+//! \return Returns the trim value.
+//
+//*****************************************************************************
+extern uint32_t SetupGetTrimForAmpcompCtrl( uint32_t ui32Fcfg1Revision );
+
+//*****************************************************************************
+//
+//! \brief Returns the trim value to be used for the AMPCOMP_TH1 register in OSC_DIG.
+//!
+//! \return Returns the trim value.
+//
+//*****************************************************************************
+extern uint32_t SetupGetTrimForAmpcompTh1( void );
+
+//*****************************************************************************
+//
+//! \brief Returns the trim value to be used for the AMPCOMP_TH2 register in OSC_DIG.
+//!
+//! \return Returns the trim value.
+//
+//*****************************************************************************
+extern uint32_t SetupGetTrimForAmpcompTh2( void );
+
+//*****************************************************************************
+//
+//! \brief Returns the trim value to be used for the ANABYPASS_VALUE1 register in OSC_DIG.
+//!
+//! \param ccfg_ModeConfReg is the value of the CCFG_O_MODE_CONF_1 register
+//!
+//! \return Returns the trim value.
+//
+//*****************************************************************************
+extern uint32_t SetupGetTrimForAnabypassValue1( uint32_t ccfg_ModeConfReg );
+
+//*****************************************************************************
+//
+//! \brief Returns the trim value from FCFG1 to be used as DBLR_LOOP_FILTER_RESET_VOLTAGE setting.
+//!
+//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register
+//!
+//! \return Returns the trim value from FCFG1.
+//
+//*****************************************************************************
+extern uint32_t SetupGetTrimForDblrLoopFilterResetVoltage( uint32_t ui32Fcfg1Revision );
+
+//*****************************************************************************
+//
+//! \brief Returns the trim value to be used for the RADCEXTCFG register in OSC_DIG.
+//!
+//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register
+//!
+//! \return Returns the trim value.
+//
+//*****************************************************************************
+extern uint32_t SetupGetTrimForRadcExtCfg( uint32_t ui32Fcfg1Revision );
+
+//*****************************************************************************
+//
+//! \brief Returns the FCFG1 OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM.
+//!
+//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register
+//!
+//! \return Returns the trim value from FCFG1.
+//
+//*****************************************************************************
+extern uint32_t SetupGetTrimForRcOscLfIBiasTrim( uint32_t ui32Fcfg1Revision );
+
+//*****************************************************************************
+//
+//! \brief Returns the trim value to be used for the RCOSCLF_RTUNE_TRIM and the
+//! RCOSCLF_CTUNE_TRIM bit fields in the XOSCLF_RCOSCLF_CTRL register in OSC_DIG.
+//!
+//! \return Returns the trim value.
+//
+//*****************************************************************************
+extern uint32_t SetupGetTrimForRcOscLfRtuneCtuneTrim( void );
+
+//*****************************************************************************
+//
+//! \brief Returns the trim value to be used for the XOSCHFCTL register in OSC_DIG.
+//!
+//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register
+//!
+//! \return Returns the trim value.
+//
+//*****************************************************************************
+extern uint32_t SetupGetTrimForXoscHfCtl( uint32_t ui32Fcfg1Revision );
+
+//*****************************************************************************
+//
+//! \brief Returns the trim value to be used as OSC_DIG:CTL1.XOSC_HF_FAST_START.
+//!
+//! \return Returns the trim value.
+//
+//*****************************************************************************
+extern uint32_t SetupGetTrimForXoscHfFastStart( void );
+
+//*****************************************************************************
+//
+//! \brief Returns the trim value to be used for the XOSC_HF_IBIASTHERM bit field in
+//! the ANABYPASS_VALUE2 register in OSC_DIG.
+//!
+//! \return Returns the trim value.
+//
+//*****************************************************************************
+extern uint32_t SetupGetTrimForXoscHfIbiastherm( void );
+
+//*****************************************************************************
+//
+//! \brief Returns XOSCLF_REGULATOR_TRIM and XOSCLF_CMIRRWR_RATIO as one packet
+//! spanning bits [5:0] in the returned value.
+//!
+//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register
+//!
+//! \return Returns XOSCLF_REGULATOR_TRIM and XOSCLF_CMIRRWR_RATIO as one packet.
+//
+//*****************************************************************************
+extern uint32_t SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio( uint32_t ui32Fcfg1Revision );
+
+//*****************************************************************************
+//
+//! \brief Sign extend the VDDR_TRIM setting (special format ranging from -10 to +21)
+//!
+//! \param ui32VddrTrimVal
+//!
+//! \return Returns Sign extended VDDR_TRIM setting.
+//
+//*****************************************************************************
+__STATIC_INLINE int32_t
+SetupSignExtendVddrTrimValue( uint32_t ui32VddrTrimVal )
+{
+ // The VDDR trim value is 5 bits representing the range from -10 to +21
+ // (where -10=0x16, -1=0x1F, 0=0x00, 1=0x01 and +21=0x15)
+ int32_t i32SignedVddrVal = ui32VddrTrimVal;
+ if ( i32SignedVddrVal > 0x15 ) {
+ i32SignedVddrVal -= 0x20;
+ }
+ return ( i32SignedVddrVal );
+}
+
+//*****************************************************************************
+//
+//! \brief Set correct VIMS_MODE according to CCFG setting (CACHE or GPRAM)
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void SetupSetCacheModeAccordingToCcfgSetting( void );
+
+//*****************************************************************************
+//
+//! \brief Doing the tricky stuff needed to enter new RTCSUBSECINC value
+//!
+//! \param subSecInc
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void SetupSetAonRtcSubSecInc( uint32_t subSecInc );
+
+//*****************************************************************************
+//
+//! \brief Set VDDR boost mode (by setting VDDR_TRIM to FCFG1..VDDR_TRIM_HH and
+//! setting VDDS_BOD to max)
+//!
+//! \param toCode specifies the target VDDR trim value.
+//! The input parameter \c toCode can be either the signed extended
+//! trim value or holding the trim code bits only.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void SetupStepVddrTrimTo( uint32_t toCode );
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// Redirect to implementation in ROM when available.
+//
+//*****************************************************************************
+#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
+ #include "../driverlib/rom.h"
+ #ifdef ROM_SetupAfterColdResetWakeupFromShutDownCfg1
+ #undef SetupAfterColdResetWakeupFromShutDownCfg1
+ #define SetupAfterColdResetWakeupFromShutDownCfg1 ROM_SetupAfterColdResetWakeupFromShutDownCfg1
+ #endif
+ #ifdef ROM_SetupAfterColdResetWakeupFromShutDownCfg2
+ #undef SetupAfterColdResetWakeupFromShutDownCfg2
+ #define SetupAfterColdResetWakeupFromShutDownCfg2 ROM_SetupAfterColdResetWakeupFromShutDownCfg2
+ #endif
+ #ifdef ROM_SetupAfterColdResetWakeupFromShutDownCfg3
+ #undef SetupAfterColdResetWakeupFromShutDownCfg3
+ #define SetupAfterColdResetWakeupFromShutDownCfg3 ROM_SetupAfterColdResetWakeupFromShutDownCfg3
+ #endif
+ #ifdef ROM_SetupGetTrimForAdcShModeEn
+ #undef SetupGetTrimForAdcShModeEn
+ #define SetupGetTrimForAdcShModeEn ROM_SetupGetTrimForAdcShModeEn
+ #endif
+ #ifdef ROM_SetupGetTrimForAdcShVbufEn
+ #undef SetupGetTrimForAdcShVbufEn
+ #define SetupGetTrimForAdcShVbufEn ROM_SetupGetTrimForAdcShVbufEn
+ #endif
+ #ifdef ROM_SetupGetTrimForAmpcompCtrl
+ #undef SetupGetTrimForAmpcompCtrl
+ #define SetupGetTrimForAmpcompCtrl ROM_SetupGetTrimForAmpcompCtrl
+ #endif
+ #ifdef ROM_SetupGetTrimForAmpcompTh1
+ #undef SetupGetTrimForAmpcompTh1
+ #define SetupGetTrimForAmpcompTh1 ROM_SetupGetTrimForAmpcompTh1
+ #endif
+ #ifdef ROM_SetupGetTrimForAmpcompTh2
+ #undef SetupGetTrimForAmpcompTh2
+ #define SetupGetTrimForAmpcompTh2 ROM_SetupGetTrimForAmpcompTh2
+ #endif
+ #ifdef ROM_SetupGetTrimForAnabypassValue1
+ #undef SetupGetTrimForAnabypassValue1
+ #define SetupGetTrimForAnabypassValue1 ROM_SetupGetTrimForAnabypassValue1
+ #endif
+ #ifdef ROM_SetupGetTrimForDblrLoopFilterResetVoltage
+ #undef SetupGetTrimForDblrLoopFilterResetVoltage
+ #define SetupGetTrimForDblrLoopFilterResetVoltage ROM_SetupGetTrimForDblrLoopFilterResetVoltage
+ #endif
+ #ifdef ROM_SetupGetTrimForRadcExtCfg
+ #undef SetupGetTrimForRadcExtCfg
+ #define SetupGetTrimForRadcExtCfg ROM_SetupGetTrimForRadcExtCfg
+ #endif
+ #ifdef ROM_SetupGetTrimForRcOscLfIBiasTrim
+ #undef SetupGetTrimForRcOscLfIBiasTrim
+ #define SetupGetTrimForRcOscLfIBiasTrim ROM_SetupGetTrimForRcOscLfIBiasTrim
+ #endif
+ #ifdef ROM_SetupGetTrimForRcOscLfRtuneCtuneTrim
+ #undef SetupGetTrimForRcOscLfRtuneCtuneTrim
+ #define SetupGetTrimForRcOscLfRtuneCtuneTrim ROM_SetupGetTrimForRcOscLfRtuneCtuneTrim
+ #endif
+ #ifdef ROM_SetupGetTrimForXoscHfCtl
+ #undef SetupGetTrimForXoscHfCtl
+ #define SetupGetTrimForXoscHfCtl ROM_SetupGetTrimForXoscHfCtl
+ #endif
+ #ifdef ROM_SetupGetTrimForXoscHfFastStart
+ #undef SetupGetTrimForXoscHfFastStart
+ #define SetupGetTrimForXoscHfFastStart ROM_SetupGetTrimForXoscHfFastStart
+ #endif
+ #ifdef ROM_SetupGetTrimForXoscHfIbiastherm
+ #undef SetupGetTrimForXoscHfIbiastherm
+ #define SetupGetTrimForXoscHfIbiastherm ROM_SetupGetTrimForXoscHfIbiastherm
+ #endif
+ #ifdef ROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio
+ #undef SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio
+ #define SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio ROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio
+ #endif
+ #ifdef ROM_SetupSetCacheModeAccordingToCcfgSetting
+ #undef SetupSetCacheModeAccordingToCcfgSetting
+ #define SetupSetCacheModeAccordingToCcfgSetting ROM_SetupSetCacheModeAccordingToCcfgSetting
+ #endif
+ #ifdef ROM_SetupSetAonRtcSubSecInc
+ #undef SetupSetAonRtcSubSecInc
+ #define SetupSetAonRtcSubSecInc ROM_SetupSetAonRtcSubSecInc
+ #endif
+ #ifdef ROM_SetupStepVddrTrimTo
+ #undef SetupStepVddrTrimTo
+ #define SetupStepVddrTrimTo ROM_SetupStepVddrTrimTo
+ #endif
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __SETUP_ROM_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/setup_rom_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/setup_rom_doc.h
new file mode 100644
index 0000000..072e4ee
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/setup_rom_doc.h
@@ -0,0 +1,44 @@
+/******************************************************************************
+* Filename: setup_rom_doc.h
+* Revised: 2017-06-05 12:13:49 +0200 (ma, 05 jun 2017)
+* Revision: 49096
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+//! \addtogroup setup_rom_api
+//! @{
+//!
+//! This module contains functions from the Setup API which are likely to be in ROM.
+//!
+//! \note Do not use functions from this module directly! This module is only to be used by
+//! SetupTrimDevice().
+//!
+//! @}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sha2.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sha2.c
new file mode 100644
index 0000000..814e737
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sha2.c
@@ -0,0 +1,272 @@
+/******************************************************************************
+* Filename: sha2.c
+* Revised: 2018-04-17 15:57:27 +0200 (Tue, 17 Apr 2018)
+* Revision: 51892
+*
+* Description: Driver for the SHA-2 functions of the crypto module
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "sha2.h"
+
+//*****************************************************************************
+//
+// Handle support for DriverLib in ROM:
+// This section will undo prototype renaming made in the header file
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #undef SHA2StartDMAOperation
+ #define SHA2StartDMAOperation NOROM_SHA2StartDMAOperation
+ #undef SHA2WaitForIRQFlags
+ #define SHA2WaitForIRQFlags NOROM_SHA2WaitForIRQFlags
+ #undef SHA2ComputeInitialHash
+ #define SHA2ComputeInitialHash NOROM_SHA2ComputeInitialHash
+ #undef SHA2ComputeIntermediateHash
+ #define SHA2ComputeIntermediateHash NOROM_SHA2ComputeIntermediateHash
+ #undef SHA2ComputeFinalHash
+ #define SHA2ComputeFinalHash NOROM_SHA2ComputeFinalHash
+ #undef SHA2ComputeHash
+ #define SHA2ComputeHash NOROM_SHA2ComputeHash
+#endif
+
+
+static uint32_t SHA2ExecuteHash(const uint8_t *message, uint8_t *resultDigest, uint32_t *intermediateDigest, uint32_t totalMsgLength, uint32_t messageLength, uint32_t hashAlgorithm, bool initialHash, bool finalHash);
+
+
+//*****************************************************************************
+//
+// Start a SHA-2 DMA operation.
+//
+//*****************************************************************************
+void SHA2StartDMAOperation(uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length)
+{
+
+ // Clear any outstanding events.
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = CRYPTO_IRQCLR_RESULT_AVAIL_M | CRYPTO_IRQEN_DMA_IN_DONE_M;
+
+ while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | CRYPTO_IRQSTAT_RESULT_AVAIL_M));
+
+ if (channel0Addr) {
+ // Configure the DMA controller - enable both DMA channels.
+ HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1;
+
+ // Base address of the payload data in ext. memory.
+ HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)channel0Addr;
+
+ // Payload data length in bytes, equal to the cipher text length.
+ HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = channel0Length;
+ }
+
+ if (channel1Addr) {
+ // Enable DMA channel 1.
+ HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1;
+
+ // Base address of the output data buffer.
+ HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = (uint32_t)channel1Addr;
+
+ // Output data length in bytes, equal to the cipher text length.
+ HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = channel1Length;
+ }
+}
+
+//*****************************************************************************
+//
+// Poll the IRQ status register and return.
+//
+//*****************************************************************************
+uint32_t SHA2WaitForIRQFlags(uint32_t irqFlags)
+{
+ uint32_t irqTrigger = 0;
+ // Wait for the DMA operation to complete. Add a delay to make sure we are
+ // not flooding the bus with requests too much.
+ do {
+ CPUdelay(1);
+ }
+ while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & irqFlags & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | CRYPTO_IRQSTAT_RESULT_AVAIL_M)));
+
+ // Save the IRQ trigger source
+ irqTrigger = HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT);
+
+ // Clear IRQ flags
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = irqFlags;
+
+ while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & irqFlags & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | CRYPTO_IRQSTAT_RESULT_AVAIL_M));
+
+ return irqTrigger;
+}
+
+//*****************************************************************************
+//
+// Start a new SHA-2 hash operation.
+//
+//*****************************************************************************
+uint32_t SHA2ComputeInitialHash(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t initialMessageLength)
+{
+ ASSERT(message);
+ ASSERT((hashAlgorithm == SHA2_MODE_SELECT_SHA224) ||
+ (hashAlgorithm == SHA2_MODE_SELECT_SHA256) ||
+ (hashAlgorithm == SHA2_MODE_SELECT_SHA384) ||
+ (hashAlgorithm == SHA2_MODE_SELECT_SHA512));
+ ASSERT(!(intermediateDigest == NULL) && !((uint32_t)intermediateDigest & 0x03));
+
+ return SHA2ExecuteHash(message, (uint8_t *)intermediateDigest, intermediateDigest, initialMessageLength, initialMessageLength, hashAlgorithm, true, false);
+}
+
+//*****************************************************************************
+//
+// Start an intermediate SHA-2 hash operation.
+//
+//*****************************************************************************
+uint32_t SHA2ComputeIntermediateHash(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t intermediateMessageLength)
+{
+ ASSERT(message);
+ ASSERT(!(intermediateDigest == NULL) && !((uint32_t)intermediateDigest & 0x03));
+ ASSERT((hashAlgorithm == SHA2_MODE_SELECT_SHA224) ||
+ (hashAlgorithm == SHA2_MODE_SELECT_SHA256) ||
+ (hashAlgorithm == SHA2_MODE_SELECT_SHA384) ||
+ (hashAlgorithm == SHA2_MODE_SELECT_SHA512));
+
+ return SHA2ExecuteHash(message, (uint8_t *)intermediateDigest, intermediateDigest, 0, intermediateMessageLength, hashAlgorithm, false, false);
+}
+
+//*****************************************************************************
+//
+// Start an intermediate SHA-2 hash operation and finalize it.
+//
+//*****************************************************************************
+uint32_t SHA2ComputeFinalHash(const uint8_t *message, uint8_t *resultDigest, uint32_t *intermediateDigest, uint32_t totalMsgLength, uint32_t messageLength, uint32_t hashAlgorithm)
+{
+ ASSERT(message);
+ ASSERT(totalMsgLength);
+ ASSERT(!(intermediateDigest == NULL) && !((uint32_t)intermediateDigest & 0x03));
+ ASSERT(resultDigest);
+ ASSERT((hashAlgorithm == SHA2_MODE_SELECT_SHA224) ||
+ (hashAlgorithm == SHA2_MODE_SELECT_SHA256) ||
+ (hashAlgorithm == SHA2_MODE_SELECT_SHA384) ||
+ (hashAlgorithm == SHA2_MODE_SELECT_SHA512));
+
+ return SHA2ExecuteHash(message, resultDigest, intermediateDigest, totalMsgLength, messageLength, hashAlgorithm, false, true);
+}
+
+//*****************************************************************************
+//
+// Start and finalize a new SHA-2 hash operation.
+//
+//*****************************************************************************
+uint32_t SHA2ComputeHash(const uint8_t *message, uint8_t *resultDigest, uint32_t totalMsgLength, uint32_t hashAlgorithm)
+{
+ ASSERT(message);
+ ASSERT(totalMsgLength);
+ ASSERT(resultDigest);
+ ASSERT((hashAlgorithm == SHA2_MODE_SELECT_SHA224) ||
+ (hashAlgorithm == SHA2_MODE_SELECT_SHA256) ||
+ (hashAlgorithm == SHA2_MODE_SELECT_SHA384) ||
+ (hashAlgorithm == SHA2_MODE_SELECT_SHA512));
+
+ return SHA2ExecuteHash(message, resultDigest, 0, totalMsgLength, totalMsgLength, hashAlgorithm, true, true);
+}
+
+//*****************************************************************************
+//
+// Start any SHA-2 hash operation.
+//
+//*****************************************************************************
+static uint32_t SHA2ExecuteHash(const uint8_t *message, uint8_t *resultDigest, uint32_t *intermediateDigest, uint32_t totalMsgLength, uint32_t messageLength, uint32_t hashAlgorithm, bool initialHash, bool finalHash)
+{
+ uint8_t digestLength = 0;
+ uint32_t dmaAlgorithmSelect = 0;
+
+ SHA2ClearDigestAvailableFlag();
+
+ switch (hashAlgorithm) {
+ case SHA2_MODE_SELECT_SHA224:
+ digestLength = SHA2_SHA224_DIGEST_LENGTH_BYTES;
+ dmaAlgorithmSelect = SHA2_ALGSEL_SHA256;
+ break;
+ case SHA2_MODE_SELECT_SHA256:
+ digestLength = SHA2_SHA256_DIGEST_LENGTH_BYTES;
+ dmaAlgorithmSelect = SHA2_ALGSEL_SHA256;
+ break;
+ case SHA2_MODE_SELECT_SHA384:
+ digestLength = SHA2_SHA384_DIGEST_LENGTH_BYTES;
+ dmaAlgorithmSelect = SHA2_ALGSEL_SHA512;
+ break;
+ case SHA2_MODE_SELECT_SHA512:
+ digestLength = SHA2_SHA512_DIGEST_LENGTH_BYTES;
+ dmaAlgorithmSelect = SHA2_ALGSEL_SHA512;
+ break;
+ default:
+ return SHA2_INVALID_ALGORITHM;
+ }
+
+ if (initialHash && finalHash) {
+ // The empty string is a perfectly valid message. It obviously has a length of 0. The DMA cannot
+ // handle running with a transfer length of 0. This workaround depends on the hash engine adding the
+ // trailing 1 bit and 0-padding bits after the DMAtransfer is complete and not in the DMA itself.
+ // totalMsgLength is purposefully not altered as it is appended to the end of the message during finalization
+ // and determines how many padding-bytes are added.
+ // Altering totalMsgLength would alter the final hash digest.
+ // Because totalMsgLength specifies that the message is of length 0, the content of the byte loaded
+ // through the DMA is irrelevant. It is overwritten internally in the hash engine.
+ messageLength = messageLength ? messageLength : 1;
+ }
+
+ // Setting the incorrect number of bits here leads to the calculation of the correct result
+ // but a failure to read them out.
+ // The tag bit is set to read out the digest via DMA rather than through the slave interface.
+ SHA2SelectAlgorithm(dmaAlgorithmSelect | (resultDigest ? SHA2_ALGSEL_TAG : 0));
+ SHA2IntClear(SHA2_DMA_IN_DONE | SHA2_RESULT_RDY);
+ SHA2IntEnable(SHA2_DMA_IN_DONE | SHA2_RESULT_RDY);
+
+ HWREG(CRYPTO_BASE + CRYPTO_O_HASHMODE) = hashAlgorithm | (initialHash ? CRYPTO_HASHMODE_NEW_HASH_M : 0);
+
+ // Only load the intermediate digest if requested.
+ if (intermediateDigest && !initialHash) {
+ SHA2SetDigest(intermediateDigest, digestLength);
+ }
+
+ // If this is the final hash, finalization is required. This means appending a 1 bit, padding the message until this section
+ // is 448 bytes long, and adding the 64 bit total length of the message in bits. Thankfully, this is all done in hardware.
+ if (finalHash) {
+ // This specific length must be specified in bits not bytes.
+ SHA2SetMessageLength(totalMsgLength * 8);
+ HWREG(CRYPTO_BASE + CRYPTO_O_HASHIOBUFCTRL) = CRYPTO_HASHIOBUFCTRL_PAD_DMA_MESSAGE_M;
+
+ }
+
+ // The cast is fine in this case. SHA2StartDMAOperation channel one serves as input and no one does
+ // hash operations in-place.
+ SHA2StartDMAOperation((uint8_t *)message, messageLength, resultDigest, digestLength);
+
+ return SHA2_SUCCESS;
+}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sha2.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sha2.h
new file mode 100644
index 0000000..4910222
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sha2.h
@@ -0,0 +1,802 @@
+/******************************************************************************
+* Filename: sha2.h
+* Revised: 2018-04-17 16:04:03 +0200 (Tue, 17 Apr 2018)
+* Revision: 51893
+*
+* Description: SHA-2 header file.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup peripheral_group
+//! @{
+//! \addtogroup sha2_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __SHA2_H__
+#define __SHA2_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stddef.h>
+#include "../inc/hw_types.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_ints.h"
+#include "../inc/hw_crypto.h"
+#include "../inc/hw_ccfg.h"
+#include "debug.h"
+#include "interrupt.h"
+#include "cpu.h"
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// This section renames all functions that are not "static inline", so that
+// calling these functions will default to implementation in flash. At the end
+// of this file a second renaming will change the defaults to implementation in
+// ROM for available functions.
+//
+// To force use of the implementation in flash, e.g. for debugging:
+// - Globally: Define DRIVERLIB_NOROM at project level
+// - Per function: Use prefix "NOROM_" when calling the function
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #define SHA2StartDMAOperation NOROM_SHA2StartDMAOperation
+ #define SHA2WaitForIRQFlags NOROM_SHA2WaitForIRQFlags
+ #define SHA2ComputeInitialHash NOROM_SHA2ComputeInitialHash
+ #define SHA2ComputeIntermediateHash NOROM_SHA2ComputeIntermediateHash
+ #define SHA2ComputeFinalHash NOROM_SHA2ComputeFinalHash
+ #define SHA2ComputeHash NOROM_SHA2ComputeHash
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to SHA2IntEnable, SHA2IntDisable, and SHA2IntClear
+// as the intFlags parameter, and returned from SHA2IntStatus.
+// Only SHA2_DMA_IN_DONE and SHA2_RESULT_RDY are routed to the NVIC. Check each
+// function to see if it supports other interrupt status flags.
+//
+//*****************************************************************************
+#define SHA2_DMA_IN_DONE (CRYPTO_IRQEN_DMA_IN_DONE_M)
+#define SHA2_RESULT_RDY (CRYPTO_IRQEN_RESULT_AVAIL_M)
+#define SHA2_DMA_BUS_ERR (CRYPTO_IRQCLR_DMA_BUS_ERR_M)
+
+
+//*****************************************************************************
+//
+// General constants
+//
+//*****************************************************************************
+
+// SHA-2 module return codes
+#define SHA2_SUCCESS 0
+#define SHA2_INVALID_ALGORITHM 1
+#define SHA2_DMA_BUSY 3
+#define SHA2_DMA_ERROR 4
+#define SHA2_DIGEST_NOT_READY 5
+#define SHA2_OLD_DIGEST_NOT_READ 6
+
+// SHA-2 output digest lengths in bytes.
+#define SHA2_SHA224_DIGEST_LENGTH_BYTES (224 / 8)
+#define SHA2_SHA256_DIGEST_LENGTH_BYTES (256 / 8)
+#define SHA2_SHA384_DIGEST_LENGTH_BYTES (384 / 8)
+#define SHA2_SHA512_DIGEST_LENGTH_BYTES (512 / 8)
+
+//Selectable SHA-2 modes. They determine the algorithm used and if initial
+//values will be set to the default constants or not
+#define SHA2_MODE_SELECT_SHA224 (CRYPTO_HASHMODE_SHA224_MODE_M)
+#define SHA2_MODE_SELECT_SHA256 (CRYPTO_HASHMODE_SHA256_MODE_M)
+#define SHA2_MODE_SELECT_SHA384 (CRYPTO_HASHMODE_SHA384_MODE_M)
+#define SHA2_MODE_SELECT_SHA512 (CRYPTO_HASHMODE_SHA512_MODE_M)
+#define SHA2_MODE_SELECT_NEW_HASH (CRYPTO_HASHMODE_NEW_HASH_M)
+
+// SHA-2 block lengths. When hashing block-wise, they define the size of each
+// block provided to the new and intermediate hash functions.
+#define SHA2_SHA224_BLOCK_SIZE_BYTES (512 / 8)
+#define SHA2_SHA256_BLOCK_SIZE_BYTES (512 / 8)
+#define SHA2_SHA384_BLOCK_SIZE_BYTES (1024 / 8)
+#define SHA2_SHA512_BLOCK_SIZE_BYTES (1024 / 8)
+
+// DMA status codes
+#define SHA2_DMA_CHANNEL0_ACTIVE (CRYPTO_DMASTAT_CH0_ACT_M)
+#define SHA2_DMA_CHANNEL1_ACTIVE (CRYPTO_DMASTAT_CH1_ACT_M)
+#define SHA2_DMA_PORT_ERROR (CRYPTO_DMASTAT_PORT_ERR_M)
+
+// Crypto module DMA operation types
+#define SHA2_ALGSEL_SHA256 0x04
+#define SHA2_ALGSEL_SHA512 0x08
+#define SHA2_ALGSEL_TAG (CRYPTO_ALGSEL_TAG_M)
+
+
+
+//*****************************************************************************
+//
+// API Functions and prototypes
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \brief Start a crypto DMA operation
+//!
+//! Enable the crypto DMA channels, configure the channel addresses,
+//! and set the length of the data transfer.
+//! Setting the length of the data transfer automatically starts the
+//! transfer. It is also used by the hardware module as a signal to
+//! begin the encryption, decryption, or MAC operation.
+//!
+//! \param [in] channel0Addr
+//! A pointer to the address channel 0 shall use.
+//!
+//! \param [in] channel0Length
+//! Length of the data in bytes to be read from or written to at
+//! \c channel0Addr. Set to 0 to not set up this channel.
+//!
+//! \param [out] channel1Addr
+//! A pointer to the address channel 1 shall use.
+//!
+//! \param [in] channel1Length
+//! Length of the data in bytes to be read from or written to at
+//! \c channel1Addr. Set to 0 to not set up this channel.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void SHA2StartDMAOperation(uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length);
+
+//*****************************************************************************
+//
+//! \brief Poll the interrupt status register and clear when done.
+//!
+//! This function polls until one of the bits in the \c irqFlags is
+//! asserted. Only \ref SHA2_DMA_IN_DONE and \ref SHA2_RESULT_RDY can actually
+//! trigger the interrupt line. That means that one of those should
+//! always be included in \c irqFlags and will always be returned together
+//! with any error codes.
+//!
+//! \param [in] irqFlags
+//! IRQ flags to poll and mask that the status register will be
+//! masked with. Consists of any bitwise OR of the flags
+//! below that includes at least one of
+//! \ref SHA2_DMA_IN_DONE or \ref SHA2_RESULT_RDY :
+//! - \ref SHA2_DMA_IN_DONE
+//! - \ref SHA2_RESULT_RDY
+//! - \ref SHA2_DMA_BUS_ERR
+//!
+//! \return Returns the IRQ status register masked with \c irqFlags. May be any
+//! bitwise OR of the following masks:
+//! - \ref SHA2_DMA_IN_DONE
+//! - \ref SHA2_RESULT_RDY
+//! - \ref SHA2_DMA_BUS_ERR
+//
+//*****************************************************************************
+extern uint32_t SHA2WaitForIRQFlags(uint32_t irqFlags);
+
+//*****************************************************************************
+//
+//! \brief Start a new SHA-2 hash operation.
+//!
+//! This function begins a new piecewise hash operation.
+//!
+//! Call this function when starting a new hash operation and the
+//! entire message is not yet available.
+//!
+//! Call SHA2ComputeIntermediateHash() or SHA2ComputeFinalHash()
+//! after this call.
+//!
+//! If the device shall go into standby in between calls to this
+//! function and either SHA2ComputeIntermediateHash() or
+//! SHA2ComputeFinalHash(), the intermediate digest must be saved in
+//! system RAM.
+//!
+//! \param [in] message
+//! Byte array containing the start of the message to hash.
+//! Must be exactly as long as the block length of the selected
+//! algorithm.
+//! - \ref SHA2_SHA224_BLOCK_SIZE_BYTES
+//! - \ref SHA2_SHA256_BLOCK_SIZE_BYTES
+//! - \ref SHA2_SHA384_BLOCK_SIZE_BYTES
+//! - \ref SHA2_SHA512_BLOCK_SIZE_BYTES
+//!
+//! \param [out] intermediateDigest
+//! Pointer to intermediate digest.
+//! - NULL The intermediate digest will be stored in the internal
+//! registers of the SHA module.
+//! - Not NULL Specifies the location the intermediate digest will
+//! be written to.
+//!
+//! Must be of a length equal to the digest length of the selected
+//! hash algorithm.
+//! Must be 32-bit aligned. \c intermediateDigest is copied into the
+//! registers through the AHB slave interface in
+//! SHA2ComputeIntermediateHash() and SHA2ComputeFinalHash().
+//! This can only be done word-by-word.
+//!
+//! \param [in] hashAlgorithm Selects the hash algorithm to use. One of:
+//! - \ref SHA2_MODE_SELECT_SHA224
+//! - \ref SHA2_MODE_SELECT_SHA256
+//! - \ref SHA2_MODE_SELECT_SHA384
+//! - \ref SHA2_MODE_SELECT_SHA512
+//!
+//! \param [in] initialMessageLength The length in bytes of the first
+//! section of the message to process. Must be a multiple of the
+//! block size.
+//!
+//! \return Returns a SHA-2 return code.
+//! - \ref SHA2_SUCCESS
+//! - \ref SHA2_INVALID_ALGORITHM
+//!
+//! \sa SHA2ComputeIntermediateHash()
+//! \sa SHA2ComputeFinalHash()
+//
+//*****************************************************************************
+extern uint32_t SHA2ComputeInitialHash(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t initialMessageLength);
+
+//*****************************************************************************
+//
+//! \brief Resume a SHA-2 hash operation but do not finalize it.
+//!
+//! This function resumes a previous hash operation.
+//!
+//! Call this function when continuing a hash operation and the
+//! message is not yet complete.
+//!
+//! Call this function again or SHA2ComputeFinalHash()
+//! after this call.
+//!
+//! If the device shall go into standby in between calls to this
+//! function and SHA2ComputeFinalHash(), the intermediate
+//! digest must be saved in system RAM.
+//!
+//! \param [in] message
+//! Byte array containing the start of the current block of the
+//! message to hash.
+//! Must be exactly as long as the block length of the selected
+//! algorithm.
+//! - \ref SHA2_SHA224_BLOCK_SIZE_BYTES
+//! - \ref SHA2_SHA256_BLOCK_SIZE_BYTES
+//! - \ref SHA2_SHA384_BLOCK_SIZE_BYTES
+//! - \ref SHA2_SHA512_BLOCK_SIZE_BYTES
+//!
+//! \param [in, out] intermediateDigest
+//! Pointer to intermediate digest.
+//! - NULL The intermediate digest will be sourced from the internal
+//! registers of the SHA module and stored there after the
+//! operation completes.
+//! - Not NULL Specifies the location the intermediate digest will
+//! be read from and written to.
+//!
+//! Must be of a length equal to the digest length of the selected
+//! hash algorithm.
+//! Must be 32-bit aligned. \c intermediateDigest is copied from and
+//! to the registers through the AHB slave interface.
+//! This can only be done word-by-word.
+//!
+//! \param [in] hashAlgorithm Selects the hash algorithm to use. One of:
+//! - \ref SHA2_MODE_SELECT_SHA224
+//! - \ref SHA2_MODE_SELECT_SHA256
+//! - \ref SHA2_MODE_SELECT_SHA384
+//! - \ref SHA2_MODE_SELECT_SHA512
+//!
+//! \param [in] intermediateMessageLength The length in bytes of this
+//! section of the message to process. Must be a multiple of the
+//! block size.
+//!
+//! \return Returns a SHA-2 return code.
+//! - \ref SHA2_SUCCESS
+//! - \ref SHA2_INVALID_ALGORITHM
+//!
+//! \sa SHA2ComputeInitialHash()
+//! \sa SHA2ComputeFinalHash()
+//
+//*****************************************************************************
+extern uint32_t SHA2ComputeIntermediateHash(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t intermediateMessageLength);
+
+//*****************************************************************************
+//
+//! \brief Resume a SHA-2 hash operation and finalize it.
+//!
+//! This function resumes a previous hash session.
+//!
+//! Call this function when continuing a hash operation and the
+//! message is complete.
+//!
+//! \param [in] message
+//! Byte array containing the final block of the message to hash.
+//! Any length <= the block size is acceptable.
+//! The DMA finalize the message as necessary.
+//! - \ref SHA2_SHA224_BLOCK_SIZE_BYTES
+//! - \ref SHA2_SHA256_BLOCK_SIZE_BYTES
+//! - \ref SHA2_SHA384_BLOCK_SIZE_BYTES
+//! - \ref SHA2_SHA512_BLOCK_SIZE_BYTES
+//!
+//! \param [out] resultDigest
+//! Byte array that the final digest will be written to. Must be of
+//! a length equal to the digest length of the selected hash algorithm.
+//!
+//! \param [in] intermediateDigest
+//! Pointer to intermediate digest.
+//! - NULL The intermediate digest will be sourced from the internal
+//! registers of the SHA module.
+//! - Not NULL Specifies the location the intermediate digest will
+//! be read from.
+//! Must be of a length equal to the digest length of the selected
+//! hash algorithm.
+//! Must be 32-bit aligned. \c intermediateDigest is copied from and
+//! to the registers through the AHB slave interface.
+//! This can only be done word-by-word.
+//!
+//! \param [in] totalMsgLength
+//! The length in bytes of the entire \c message including the sections
+//! passed to previous calls to SHA2ComputeInitialHash() and
+//! SHA2ComputeIntermediateHash().
+//!
+//! \param [in] messageLength The length in bytes of the last
+//! section of the message to process. Does not need to be
+//! a multiple of the block size.
+//!
+//! \param [in] hashAlgorithm Selects the hash algorithm to use. One of:
+//! - \ref SHA2_MODE_SELECT_SHA224
+//! - \ref SHA2_MODE_SELECT_SHA256
+//! - \ref SHA2_MODE_SELECT_SHA384
+//! - \ref SHA2_MODE_SELECT_SHA512
+//!
+//! \return Returns a SHA-2 return code.
+//! - \ref SHA2_SUCCESS
+//! - \ref SHA2_INVALID_ALGORITHM
+//!
+//! \sa SHA2ComputeInitialHash()
+//! \sa SHA2ComputeIntermediateHash()
+//
+//*****************************************************************************
+extern uint32_t SHA2ComputeFinalHash(const uint8_t *message, uint8_t *resultDigest, uint32_t *intermediateDigest, uint32_t totalMsgLength, uint32_t messageLength, uint32_t hashAlgorithm);
+
+//*****************************************************************************
+//
+//! \brief Start a SHA-2 hash operation and return the finalized digest.
+//!
+//! This function starts a hash operation and returns the finalized
+//! digest.
+//!
+//! Use this function if the entire message is available when starting
+//! the hash.
+//!
+//! \param [in] message
+//! Byte array containing the message that will be hashed.
+//! Any length <= the block size is acceptable.
+//! The DMA will finalize the message as necessary.
+//! - \ref SHA2_SHA224_BLOCK_SIZE_BYTES
+//! - \ref SHA2_SHA256_BLOCK_SIZE_BYTES
+//! - \ref SHA2_SHA384_BLOCK_SIZE_BYTES
+//! - \ref SHA2_SHA512_BLOCK_SIZE_BYTES
+//!
+//! \param [out] resultDigest
+//! Byte array that the final digest will be written to. Must be of a
+//! length equal to the digest length of the selected hash algorithm.
+//!
+//! \param [in] totalMsgLength
+//! The length in bytes of the entire \c message.
+//!
+//! \param [in] hashAlgorithm Selects the hash algorithm to use. One of:
+//! - \ref SHA2_MODE_SELECT_SHA224
+//! - \ref SHA2_MODE_SELECT_SHA256
+//! - \ref SHA2_MODE_SELECT_SHA384
+//! - \ref SHA2_MODE_SELECT_SHA512
+//!
+//! \return Returns a SHA-2 return code.
+//! - \ref SHA2_SUCCESS
+//! - \ref SHA2_INVALID_ALGORITHM
+//!
+//
+//*****************************************************************************
+extern uint32_t SHA2ComputeHash(const uint8_t *message, uint8_t *resultDigest, uint32_t totalMsgLength, uint32_t hashAlgorithm);
+
+//*****************************************************************************
+//
+//! \brief Configure the crypto DMA for a particular operation.
+//!
+//! \param algorithm
+//! Configures the crypto DMA for a particular operation.
+//! It also powers on the respective part of the system.
+//! \ref SHA2_ALGSEL_TAG may be combined with another flag. All other
+//! flags are mutually exclusive.
+//! - 0 : Reset the module and turn off all sub-modules.
+//! - \ref SHA2_ALGSEL_SHA256 Configure for a SHA224 or SHA256 operation.
+//! - \ref SHA2_ALGSEL_SHA512 Configure for a SHA384 or SHA512 operation.
+//! - \ref SHA2_ALGSEL_TAG Read out hash via DMA rather than the slave interface
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void SHA2SelectAlgorithm(uint32_t algorithm)
+{
+ ASSERT((algorithm == SHA2_ALGSEL_SHA256) ||
+ (algorithm == SHA2_ALGSEL_SHA512) ||
+ (algorithm == SHA2_ALGSEL_SHA256 | SHA2_ALGSEL_TAG) ||
+ (algorithm == SHA2_ALGSEL_SHA512 | SHA2_ALGSEL_TAG));
+
+ HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = algorithm;
+}
+
+
+
+//*****************************************************************************
+//
+//! \brief Specify the total length of the message.
+//!
+//! Despite specifying it here, the crypto DMA must still be
+//! set up with the correct data length.
+//!
+//! Call this function only when setting up the final hash operation to
+//! enable finalization.
+//!
+//! \param length Total message length in bits.
+//!
+//! \return None
+//!
+//! \sa SHA2StartDMAOperation()
+//
+//*****************************************************************************
+__STATIC_INLINE void SHA2SetMessageLength(uint32_t length)
+{
+ HWREG(CRYPTO_BASE + CRYPTO_O_HASHINLENL) = length;
+ // CRYPTO_O_HASHINLENH is automatically set to 0. No need for the extra write.
+}
+
+//*****************************************************************************
+//
+//! \brief Load an intermediate digest.
+//!
+//! \param [in] digestLength
+//! Length of the digest in bytes. Must be one of:
+//! - \ref SHA2_SHA224_DIGEST_LENGTH_BYTES
+//! - \ref SHA2_SHA256_DIGEST_LENGTH_BYTES
+//! - \ref SHA2_SHA384_DIGEST_LENGTH_BYTES
+//! - \ref SHA2_SHA512_DIGEST_LENGTH_BYTES
+//!
+//! \param [in] digest
+//! Pointer to an intermediate digest. Must be 32-bit aligned.
+//!
+//
+//*****************************************************************************
+__STATIC_INLINE void SHA2SetDigest(uint32_t *digest, uint8_t digestLength)
+{
+ // Check the arguments.
+ ASSERT(!(digest == NULL) && !((uint32_t)digest & 0x03));
+ ASSERT((digestLength == SHA2_SHA224_DIGEST_LENGTH_BYTES) ||
+ (digestLength == SHA2_SHA256_DIGEST_LENGTH_BYTES) ||
+ (digestLength == SHA2_SHA384_DIGEST_LENGTH_BYTES) ||
+ (digestLength == SHA2_SHA512_DIGEST_LENGTH_BYTES));
+
+ // Write digest
+ uint32_t i = 0;
+ for (i = 0; i < (digestLength / sizeof(uint32_t)); i++) {
+ HWREG(CRYPTO_BASE + CRYPTO_O_HASHDIGESTA + (i * sizeof(uint32_t))) = digest[i];
+ }
+
+}
+
+//*****************************************************************************
+//
+//! \brief Read the intermediate or final digest.
+//!
+//! \param [in] digestLength Length of the digest in bytes. Must be one of:
+//! - ref SHA2_SHA224_DIGEST_LENGTH_BYTES
+//! - ref SHA2_SHA256_DIGEST_LENGTH_BYTES
+//! - ref SHA2_SHA384_DIGEST_LENGTH_BYTES
+//! - ref SHA2_SHA512_DIGEST_LENGTH_BYTES
+//!
+//! \param [out] digest
+//! Pointer to an intermediate digest. Must be 32-bit aligned.
+//!
+//! \return Returns a status code.
+//! - \ref SHA2_OLD_DIGEST_NOT_READ
+//! - \ref SHA2_SUCCESS
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t SHA2GetDigest(uint32_t *digest, uint8_t digestLength)
+{
+ // Check the arguments.
+ ASSERT(!(digest == NULL) && !((uint32_t)digest & 0x03));
+ ASSERT((digestLength == SHA2_SHA224_DIGEST_LENGTH_BYTES) ||
+ (digestLength == SHA2_SHA256_DIGEST_LENGTH_BYTES) ||
+ (digestLength == SHA2_SHA384_DIGEST_LENGTH_BYTES) ||
+ (digestLength == SHA2_SHA512_DIGEST_LENGTH_BYTES));
+
+ if (HWREG(CRYPTO_BASE + CRYPTO_O_HASHIOBUFCTRL) & CRYPTO_HASHIOBUFCTRL_OUTPUT_FULL_M) {
+ return SHA2_OLD_DIGEST_NOT_READ;
+ }
+ else {
+ // Read digest
+ uint32_t i = 0;
+ for (i = 0; i < (digestLength / sizeof(uint32_t)); i++) {
+ digest[i] = HWREG(CRYPTO_BASE + CRYPTO_O_HASHDIGESTA + (i * sizeof(uint32_t)));
+ }
+ return SHA2_SUCCESS;
+ }
+}
+
+//*****************************************************************************
+//
+//! \brief Confirm digest was read.
+//
+//*****************************************************************************
+__STATIC_INLINE void SHA2ClearDigestAvailableFlag(void)
+{
+ HWREG(CRYPTO_BASE + CRYPTO_O_HASHIOBUFCTRL) = HWREG(CRYPTO_BASE + CRYPTO_O_HASHIOBUFCTRL);
+}
+
+//*****************************************************************************
+//
+//! \brief Enable individual crypto interrupt sources.
+//!
+//! This function enables the indicated crypto interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt.
+//! Disabled sources have no effect on the processor.
+//!
+//! \param intFlags is the bitwise OR of the interrupt sources to be enabled.
+//! - \ref SHA2_DMA_IN_DONE
+//! - \ref SHA2_RESULT_RDY
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void SHA2IntEnable(uint32_t intFlags)
+{
+ // Check the arguments.
+ ASSERT((intFlags & SHA2_DMA_IN_DONE) ||
+ (intFlags & SHA2_RESULT_RDY));
+
+ // Using level interrupt.
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL_M;
+
+ // Enable the specified interrupts.
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) |= intFlags;
+}
+
+//*****************************************************************************
+//
+//! \brief Disable individual crypto interrupt sources.
+//!
+//! This function disables the indicated crypto interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt.
+//! Disabled sources have no effect on the processor.
+//!
+//! \param intFlags is the bitwise OR of the interrupt sources to be enabled.
+//! - \ref SHA2_DMA_IN_DONE
+//! - \ref SHA2_RESULT_RDY
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void SHA2IntDisable(uint32_t intFlags)
+{
+ // Check the arguments.
+ ASSERT((intFlags & SHA2_DMA_IN_DONE) ||
+ (intFlags & SHA2_RESULT_RDY));
+
+ // Disable the specified interrupts.
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~intFlags;
+}
+
+//*****************************************************************************
+//
+//! \brief Get the current masked interrupt status.
+//!
+//! This function returns the masked interrupt status of the crypto module.
+//!
+//! \return Returns the status of the masked lines when enabled:
+//! - \ref SHA2_DMA_IN_DONE
+//! - \ref SHA2_RESULT_RDY
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t SHA2IntStatusMasked(void)
+{
+ uint32_t mask;
+
+ // Return the masked interrupt status
+ mask = HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN);
+ return(mask & HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT));
+}
+
+//*****************************************************************************
+//
+//! \brief Get the current raw interrupt status.
+//!
+//! This function returns the raw interrupt status of the crypto module.
+//! It returns both the status of the lines routed to the NVIC as well as the
+//! error flags.
+//!
+//! \return Returns the raw interrupt status:
+//! - \ref SHA2_DMA_IN_DONE
+//! - \ref SHA2_RESULT_RDY
+//! - \ref SHA2_DMA_BUS_ERR
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t SHA2IntStatusRaw(void)
+{
+ // Return either the raw interrupt status
+ return(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT));
+}
+
+//*****************************************************************************
+//
+//! \brief Clear crypto interrupt sources.
+//!
+//! The specified crypto interrupt sources are cleared, so that they no longer
+//! assert. This function must be called in the interrupt handler to keep the
+//! interrupt from being recognized again immediately upon exit.
+//!
+//! \note Due to write buffers and synchronizers in the system it may take several
+//! clock cycles from a register write clearing an event in the module until the
+//! event is actually cleared in the NVIC of the system CPU. It is recommended to
+//! clear the event source early in the interrupt service routine (ISR) to allow
+//! the event clear to propagate to the NVIC before returning from the ISR.
+//!
+//! \param intFlags is a bit mask of the interrupt sources to be cleared.
+//! - \ref SHA2_DMA_IN_DONE
+//! - \ref SHA2_RESULT_RDY
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void SHA2IntClear(uint32_t intFlags)
+{
+ // Check the arguments.
+ ASSERT((intFlags & SHA2_DMA_IN_DONE) ||
+ (intFlags & SHA2_RESULT_RDY));
+
+ // Clear the requested interrupt sources,
+ HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = intFlags;
+}
+
+//*****************************************************************************
+//
+//! \brief Register an interrupt handler for a crypto interrupt in the dynamic interrupt table.
+//!
+//! \note Only use this function if you want to use the dynamic vector table (in SRAM)!
+//!
+//! This function registers a function as the interrupt handler for a specific
+//! interrupt and enables the corresponding interrupt in the interrupt controller.
+//!
+//! Specific crypto interrupts must be enabled via \ref SHA2IntEnable(). It is the
+//! interrupt handler's responsibility to clear the interrupt source.
+//!
+//! \param handlerFxn is a pointer to the function to be called when the
+//! crypto interrupt occurs.
+//!
+//! \return None
+//!
+//! \sa \ref IntRegister() for important information about registering interrupt
+//! handlers.
+//
+//*****************************************************************************
+__STATIC_INLINE void SHA2IntRegister(void (*handlerFxn)(void))
+{
+ // Register the interrupt handler.
+ IntRegister(INT_CRYPTO_RESULT_AVAIL_IRQ, handlerFxn);
+
+ // Enable the crypto interrupt.
+ IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ);
+}
+
+//*****************************************************************************
+//
+//! \brief Unregister an interrupt handler for a crypto interrupt in the dynamic interrupt table.
+//!
+//! This function does the actual unregistering of the interrupt handler. It
+//! clears the handler called when a crypto interrupt occurs. This
+//! function also masks off the interrupt in the interrupt controller so that
+//! the interrupt handler no longer is called.
+//!
+//! \return None
+//!
+//! \sa \ref IntRegister() for important information about registering interrupt
+//! handlers.
+//
+//*****************************************************************************
+__STATIC_INLINE void SHA2IntUnregister(void)
+{
+ // Disable the interrupt.
+ IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ);
+
+ // Unregister the interrupt handler.
+ IntUnregister(INT_CRYPTO_RESULT_AVAIL_IRQ);
+}
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// Redirect to implementation in ROM when available.
+//
+//*****************************************************************************
+#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
+ #include "../driverlib/rom.h"
+ #ifdef ROM_SHA2StartDMAOperation
+ #undef SHA2StartDMAOperation
+ #define SHA2StartDMAOperation ROM_SHA2StartDMAOperation
+ #endif
+ #ifdef ROM_SHA2WaitForIRQFlags
+ #undef SHA2WaitForIRQFlags
+ #define SHA2WaitForIRQFlags ROM_SHA2WaitForIRQFlags
+ #endif
+ #ifdef ROM_SHA2ComputeInitialHash
+ #undef SHA2ComputeInitialHash
+ #define SHA2ComputeInitialHash ROM_SHA2ComputeInitialHash
+ #endif
+ #ifdef ROM_SHA2ComputeIntermediateHash
+ #undef SHA2ComputeIntermediateHash
+ #define SHA2ComputeIntermediateHash ROM_SHA2ComputeIntermediateHash
+ #endif
+ #ifdef ROM_SHA2ComputeFinalHash
+ #undef SHA2ComputeFinalHash
+ #define SHA2ComputeFinalHash ROM_SHA2ComputeFinalHash
+ #endif
+ #ifdef ROM_SHA2ComputeHash
+ #undef SHA2ComputeHash
+ #define SHA2ComputeHash ROM_SHA2ComputeHash
+ #endif
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __SHA2_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sha2_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sha2_doc.h
new file mode 100644
index 0000000..2ca7c75
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sha2_doc.h
@@ -0,0 +1,62 @@
+/******************************************************************************
+* Filename: sha2_doc.h
+* Revised: 2017-11-01 10:33:37 +0100 (Wed, 01 Nov 2017)
+* Revision: 50125
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+//! \addtogroup sha2_api
+//! @{
+//! \section sec_sha2 Introduction
+//!
+//! The SHA-2 (Secure Hash Algorithm) API provides access to the SHA-2
+//! functionality of the crypto core. The AES accelerator and keystore are
+//! also contained within the crypto core. Hence, only one of SHA-2 and AES
+//! may be used at the same time.
+//! This module offers hardware acceleration for the SHA-2 family of hash
+//! algorithms. The following output digest sizes are supported:
+//! - 224 bits
+//! - 256 bits
+//! - 384 bits
+//! - 512 bits
+//!
+//! Messages are hashed in one go or in multiple steps. Stepwise hashing
+//! consists of an initial hash, multiple intermediate hashes, and a
+//! finalization hash.
+//!
+//! The crypto core does not have retention and all configuration settings
+//! are lost when going into standby or shutdown. If you wish to continue
+//! a hash operation after going into standby or shutdown, you must load
+//! the intermediate hash into system RAM before entering standby or shutdown
+//! and load the intermediate hash back into the crypto module after resuming
+//! operation.
+//!
+//! @}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/smph.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/smph.c
new file mode 100644
index 0000000..e6f47e6
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/smph.c
@@ -0,0 +1,101 @@
+/******************************************************************************
+* Filename: smph.c
+* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017)
+* Revision: 48852
+*
+* Description: Driver for the MCU Semaphore.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "smph.h"
+
+//*****************************************************************************
+//
+// Handle support for DriverLib in ROM:
+// This section will undo prototype renaming made in the header file
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #undef SMPHAcquire
+ #define SMPHAcquire NOROM_SMPHAcquire
+#endif
+
+//*****************************************************************************
+//
+// Acquire a semaphore
+//
+//*****************************************************************************
+void
+SMPHAcquire(uint32_t ui32Semaphore)
+{
+ // Check the arguments.
+ ASSERT((ui32Semaphore == SMPH_0) ||
+ (ui32Semaphore == SMPH_1) ||
+ (ui32Semaphore == SMPH_2) ||
+ (ui32Semaphore == SMPH_3) ||
+ (ui32Semaphore == SMPH_4) ||
+ (ui32Semaphore == SMPH_5) ||
+ (ui32Semaphore == SMPH_6) ||
+ (ui32Semaphore == SMPH_7) ||
+ (ui32Semaphore == SMPH_8) ||
+ (ui32Semaphore == SMPH_9) ||
+ (ui32Semaphore == SMPH_10) ||
+ (ui32Semaphore == SMPH_11) ||
+ (ui32Semaphore == SMPH_12) ||
+ (ui32Semaphore == SMPH_13) ||
+ (ui32Semaphore == SMPH_14) ||
+ (ui32Semaphore == SMPH_15) ||
+ (ui32Semaphore == SMPH_16) ||
+ (ui32Semaphore == SMPH_17) ||
+ (ui32Semaphore == SMPH_18) ||
+ (ui32Semaphore == SMPH_19) ||
+ (ui32Semaphore == SMPH_20) ||
+ (ui32Semaphore == SMPH_21) ||
+ (ui32Semaphore == SMPH_22) ||
+ (ui32Semaphore == SMPH_23) ||
+ (ui32Semaphore == SMPH_24) ||
+ (ui32Semaphore == SMPH_25) ||
+ (ui32Semaphore == SMPH_26) ||
+ (ui32Semaphore == SMPH_27) ||
+ (ui32Semaphore == SMPH_28) ||
+ (ui32Semaphore == SMPH_29) ||
+ (ui32Semaphore == SMPH_30) ||
+ (ui32Semaphore == SMPH_31));
+
+ // Wait for semaphore to be release such that it can be claimed
+ // Semaphore register reads 1 when lock was acquired otherwise 0
+ // (i.e. SMPH_CLAIMED).
+ while(HWREG(SMPH_BASE + SMPH_O_SMPH0 + 4 * ui32Semaphore) ==
+ SMPH_CLAIMED)
+ {
+ }
+}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/smph.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/smph.h
new file mode 100644
index 0000000..0ed7387
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/smph.h
@@ -0,0 +1,312 @@
+/******************************************************************************
+* Filename: smph.h
+* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016)
+* Revision: 47343
+*
+* Description: Defines and prototypes for the MCU Semaphore.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup peripheral_group
+//! @{
+//! \addtogroup mcusemaphore_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __SMPH_H__
+#define __SMPH_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "../inc/hw_types.h"
+#include "../inc/hw_smph.h"
+#include "../inc/hw_memmap.h"
+#include "debug.h"
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// This section renames all functions that are not "static inline", so that
+// calling these functions will default to implementation in flash. At the end
+// of this file a second renaming will change the defaults to implementation in
+// ROM for available functions.
+//
+// To force use of the implementation in flash, e.g. for debugging:
+// - Globally: Define DRIVERLIB_NOROM at project level
+// - Per function: Use prefix "NOROM_" when calling the function
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #define SMPHAcquire NOROM_SMPHAcquire
+#endif
+
+//*****************************************************************************
+//
+// General constants and defines
+//
+//*****************************************************************************
+#define SMPH_FREE 0x00000001 // MCU Semaphore has not been claimed
+#define SMPH_CLAIMED 0x00000000 // MCU Semaphore has been claimed
+
+//*****************************************************************************
+//
+// Values that can be passed to SMPHAcquire, SMPHTryAcquire and SMPHRelease
+// as the ui32Semaphore parameter.
+//
+//*****************************************************************************
+#define SMPH_0 0 // MCU Semaphore 0
+#define SMPH_1 1 // MCU Semaphore 1
+#define SMPH_2 2 // MCU Semaphore 2
+#define SMPH_3 3 // MCU Semaphore 3
+#define SMPH_4 4 // MCU Semaphore 4
+#define SMPH_5 5 // MCU Semaphore 5
+#define SMPH_6 6 // MCU Semaphore 6
+#define SMPH_7 7 // MCU Semaphore 7
+#define SMPH_8 8 // MCU Semaphore 8
+#define SMPH_9 9 // MCU Semaphore 9
+#define SMPH_10 10 // MCU Semaphore 10
+#define SMPH_11 11 // MCU Semaphore 11
+#define SMPH_12 12 // MCU Semaphore 12
+#define SMPH_13 13 // MCU Semaphore 13
+#define SMPH_14 14 // MCU Semaphore 14
+#define SMPH_15 15 // MCU Semaphore 15
+#define SMPH_16 16 // MCU Semaphore 16
+#define SMPH_17 17 // MCU Semaphore 17
+#define SMPH_18 18 // MCU Semaphore 18
+#define SMPH_19 19 // MCU Semaphore 19
+#define SMPH_20 20 // MCU Semaphore 20
+#define SMPH_21 21 // MCU Semaphore 21
+#define SMPH_22 22 // MCU Semaphore 22
+#define SMPH_23 23 // MCU Semaphore 23
+#define SMPH_24 24 // MCU Semaphore 24
+#define SMPH_25 25 // MCU Semaphore 25
+#define SMPH_26 26 // MCU Semaphore 26
+#define SMPH_27 27 // MCU Semaphore 27
+#define SMPH_28 28 // MCU Semaphore 28
+#define SMPH_29 29 // MCU Semaphore 29
+#define SMPH_30 30 // MCU Semaphore 30
+#define SMPH_31 31 // MCU Semaphore 31
+
+//*****************************************************************************
+//
+// API Functions and prototypes
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \brief Acquire a semaphore.
+//!
+//! This function acquires the given semaphore, blocking the call until
+//! the semaphore is available.
+//!
+//! \param ui32Semaphore is the semaphore number.
+//! - \ref SMPH_0
+//! - \ref SMPH_1
+//! - ...
+//! - \ref SMPH_31
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void SMPHAcquire(uint32_t ui32Semaphore);
+
+//*****************************************************************************
+//
+//! \brief Try to Acquire a semaphore.
+//!
+//! This function tries to acquire the given semaphore, if the semaphore
+//! could not be claimed the function returns false.
+//!
+//! \param ui32Semaphore is the semaphore number.
+//! - \ref SMPH_0
+//! - \ref SMPH_1
+//! - ...
+//! - \ref SMPH_31
+//!
+//! \return Returns if a semaphore was acquired
+//! - \c true : Semaphore acquired.
+//! - \c false : Semaphore \b not acquired.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+SMPHTryAcquire(uint32_t ui32Semaphore)
+{
+ uint32_t ui32SemaReg;
+
+ // Check the arguments.
+ ASSERT((ui32Semaphore == SMPH_0) ||
+ (ui32Semaphore == SMPH_1) ||
+ (ui32Semaphore == SMPH_2) ||
+ (ui32Semaphore == SMPH_3) ||
+ (ui32Semaphore == SMPH_4) ||
+ (ui32Semaphore == SMPH_5) ||
+ (ui32Semaphore == SMPH_6) ||
+ (ui32Semaphore == SMPH_7) ||
+ (ui32Semaphore == SMPH_8) ||
+ (ui32Semaphore == SMPH_9) ||
+ (ui32Semaphore == SMPH_10) ||
+ (ui32Semaphore == SMPH_11) ||
+ (ui32Semaphore == SMPH_12) ||
+ (ui32Semaphore == SMPH_13) ||
+ (ui32Semaphore == SMPH_14) ||
+ (ui32Semaphore == SMPH_15) ||
+ (ui32Semaphore == SMPH_16) ||
+ (ui32Semaphore == SMPH_17) ||
+ (ui32Semaphore == SMPH_18) ||
+ (ui32Semaphore == SMPH_19) ||
+ (ui32Semaphore == SMPH_20) ||
+ (ui32Semaphore == SMPH_21) ||
+ (ui32Semaphore == SMPH_22) ||
+ (ui32Semaphore == SMPH_23) ||
+ (ui32Semaphore == SMPH_24) ||
+ (ui32Semaphore == SMPH_25) ||
+ (ui32Semaphore == SMPH_26) ||
+ (ui32Semaphore == SMPH_27) ||
+ (ui32Semaphore == SMPH_28) ||
+ (ui32Semaphore == SMPH_29) ||
+ (ui32Semaphore == SMPH_30) ||
+ (ui32Semaphore == SMPH_31));
+
+ // Semaphore register reads 1 if lock was acquired
+ // (i.e. SMPH_FREE).
+ ui32SemaReg = HWREG(SMPH_BASE + SMPH_O_SMPH0 + 4 * ui32Semaphore);
+
+ return (ui32SemaReg == SMPH_FREE);
+}
+
+//*****************************************************************************
+//
+//! \brief Release a semaphore.
+//!
+//! This function releases the given semaphore.
+//!
+//! \note It is up to the application to provide the convention for clearing
+//! semaphore.
+//!
+//! \param ui32Semaphore is the semaphore number.
+//! - \ref SMPH_0
+//! - \ref SMPH_1
+//! - ...
+//! - \ref SMPH_31
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+SMPHRelease(uint32_t ui32Semaphore)
+{
+ // Check the arguments.
+ ASSERT((ui32Semaphore == SMPH_0) ||
+ (ui32Semaphore == SMPH_1) ||
+ (ui32Semaphore == SMPH_2) ||
+ (ui32Semaphore == SMPH_3) ||
+ (ui32Semaphore == SMPH_4) ||
+ (ui32Semaphore == SMPH_5) ||
+ (ui32Semaphore == SMPH_6) ||
+ (ui32Semaphore == SMPH_7) ||
+ (ui32Semaphore == SMPH_8) ||
+ (ui32Semaphore == SMPH_9) ||
+ (ui32Semaphore == SMPH_10) ||
+ (ui32Semaphore == SMPH_11) ||
+ (ui32Semaphore == SMPH_12) ||
+ (ui32Semaphore == SMPH_13) ||
+ (ui32Semaphore == SMPH_14) ||
+ (ui32Semaphore == SMPH_15) ||
+ (ui32Semaphore == SMPH_16) ||
+ (ui32Semaphore == SMPH_17) ||
+ (ui32Semaphore == SMPH_18) ||
+ (ui32Semaphore == SMPH_19) ||
+ (ui32Semaphore == SMPH_20) ||
+ (ui32Semaphore == SMPH_21) ||
+ (ui32Semaphore == SMPH_22) ||
+ (ui32Semaphore == SMPH_23) ||
+ (ui32Semaphore == SMPH_24) ||
+ (ui32Semaphore == SMPH_25) ||
+ (ui32Semaphore == SMPH_26) ||
+ (ui32Semaphore == SMPH_27) ||
+ (ui32Semaphore == SMPH_28) ||
+ (ui32Semaphore == SMPH_29) ||
+ (ui32Semaphore == SMPH_30) ||
+ (ui32Semaphore == SMPH_31));
+
+ // No check before release, it is up to the application to provide the
+ // conventions for who and when a semaphore can be released.
+ HWREG(SMPH_BASE + SMPH_O_SMPH0 + 4 * ui32Semaphore) = SMPH_FREE;
+}
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// Redirect to implementation in ROM when available.
+//
+//*****************************************************************************
+#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
+ #include "../driverlib/rom.h"
+ #ifdef ROM_SMPHAcquire
+ #undef SMPHAcquire
+ #define SMPHAcquire ROM_SMPHAcquire
+ #endif
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __SMPH_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/smph_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/smph_doc.h
new file mode 100644
index 0000000..3c6f4b3
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/smph_doc.h
@@ -0,0 +1,57 @@
+/******************************************************************************
+* Filename: smph_doc.h
+* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016)
+* Revision: 45971
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+//! \addtogroup mcusemaphore_api
+//! @{
+//! \section sec_mcusemaphore Introduction
+//!
+//! The MCU Semaphore offers 32 semaphores that each can be claimed and released in an atomic operation.
+//! One and only one semaphore can be handled during a transaction.
+//!
+//! Claiming a semaphore causes subsequent claims/reads to return '0' (i.e. "not available").
+//! How the semaphores are used and respected is decided by software.
+//!
+//! \section sec_mcusemaphore_api API
+//!
+//! The API functions can be grouped like this:
+//!
+//! Semaphore acquire:
+//! - \ref SMPHAcquire()
+//! - \ref SMPHTryAcquire()
+//!
+//! Semaphore release:
+//! - \ref SMPHRelease()
+//!
+//! @}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ssi.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ssi.c
new file mode 100644
index 0000000..eb66b6b
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ssi.c
@@ -0,0 +1,253 @@
+/******************************************************************************
+* Filename: ssi.c
+* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017)
+* Revision: 48852
+*
+* Description: Driver for Synchronous Serial Interface
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "ssi.h"
+
+//*****************************************************************************
+//
+// Handle support for DriverLib in ROM:
+// This section will undo prototype renaming made in the header file
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #undef SSIConfigSetExpClk
+ #define SSIConfigSetExpClk NOROM_SSIConfigSetExpClk
+ #undef SSIDataPut
+ #define SSIDataPut NOROM_SSIDataPut
+ #undef SSIDataPutNonBlocking
+ #define SSIDataPutNonBlocking NOROM_SSIDataPutNonBlocking
+ #undef SSIDataGet
+ #define SSIDataGet NOROM_SSIDataGet
+ #undef SSIDataGetNonBlocking
+ #define SSIDataGetNonBlocking NOROM_SSIDataGetNonBlocking
+ #undef SSIIntRegister
+ #define SSIIntRegister NOROM_SSIIntRegister
+ #undef SSIIntUnregister
+ #define SSIIntUnregister NOROM_SSIIntUnregister
+#endif
+
+//*****************************************************************************
+//
+// Configures the synchronous serial port
+//
+//*****************************************************************************
+void
+SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk,
+ uint32_t ui32Protocol, uint32_t ui32Mode,
+ uint32_t ui32BitRate, uint32_t ui32DataWidth)
+{
+ uint32_t ui32MaxBitRate;
+ uint32_t ui32RegVal;
+ uint32_t ui32PreDiv;
+ uint32_t ui32SCR;
+ uint32_t ui32SPH_SPO;
+
+ // Check the arguments.
+ ASSERT(SSIBaseValid(ui32Base));
+ ASSERT((ui32Protocol == SSI_FRF_MOTO_MODE_0) ||
+ (ui32Protocol == SSI_FRF_MOTO_MODE_1) ||
+ (ui32Protocol == SSI_FRF_MOTO_MODE_2) ||
+ (ui32Protocol == SSI_FRF_MOTO_MODE_3) ||
+ (ui32Protocol == SSI_FRF_TI) ||
+ (ui32Protocol == SSI_FRF_NMW));
+ ASSERT((ui32Mode == SSI_MODE_MASTER) ||
+ (ui32Mode == SSI_MODE_SLAVE) ||
+ (ui32Mode == SSI_MODE_SLAVE_OD));
+ ASSERT(((ui32Mode == SSI_MODE_MASTER) && (ui32BitRate <= (ui32SSIClk / 2))) ||
+ ((ui32Mode != SSI_MODE_MASTER) && (ui32BitRate <= (ui32SSIClk / 12))));
+ ASSERT((ui32SSIClk / ui32BitRate) <= (254 * 256));
+ ASSERT((ui32DataWidth >= 4) && (ui32DataWidth <= 16));
+
+ // Set the mode.
+ ui32RegVal = (ui32Mode == SSI_MODE_SLAVE_OD) ? SSI_CR1_SOD : 0;
+ ui32RegVal |= (ui32Mode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS;
+ HWREG(ui32Base + SSI_O_CR1) = ui32RegVal;
+
+ // Set the clock predivider.
+ ui32MaxBitRate = ui32SSIClk / ui32BitRate;
+ ui32PreDiv = 0;
+ do
+ {
+ ui32PreDiv += 2;
+ ui32SCR = (ui32MaxBitRate / ui32PreDiv) - 1;
+ }
+ while(ui32SCR > 255);
+ HWREG(ui32Base + SSI_O_CPSR) = ui32PreDiv;
+
+ // Set protocol and clock rate.
+ ui32SPH_SPO = (ui32Protocol & 3) << 6;
+ ui32Protocol &= SSI_CR0_FRF_M;
+ ui32RegVal = (ui32SCR << 8) | ui32SPH_SPO | ui32Protocol | (ui32DataWidth - 1);
+ HWREG(ui32Base + SSI_O_CR0) = ui32RegVal;
+}
+
+//*****************************************************************************
+//
+// Puts a data element into the SSI transmit FIFO
+//
+//*****************************************************************************
+int32_t
+SSIDataPutNonBlocking(uint32_t ui32Base, uint32_t ui32Data)
+{
+ // Check the arguments.
+ ASSERT(SSIBaseValid(ui32Base));
+ ASSERT((ui32Data & (0xfffffffe << (HWREG(ui32Base + SSI_O_CR0) &
+ SSI_CR0_DSS_M))) == 0);
+
+ // Check for space to write.
+ if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF)
+ {
+ HWREG(ui32Base + SSI_O_DR) = ui32Data;
+ return(1);
+ }
+ else
+ {
+ return(0);
+ }
+}
+
+//*****************************************************************************
+//
+// Puts a data element into the SSI transmit FIFO
+//
+//*****************************************************************************
+void
+SSIDataPut(uint32_t ui32Base, uint32_t ui32Data)
+{
+ // Check the arguments.
+ ASSERT(SSIBaseValid(ui32Base));
+ ASSERT((ui32Data & (0xfffffffe << (HWREG(ui32Base + SSI_O_CR0) &
+ SSI_CR0_DSS_M))) == 0);
+
+ // Wait until there is space.
+ while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF))
+ {
+ }
+
+ // Write the data to the SSI.
+ HWREG(ui32Base + SSI_O_DR) = ui32Data;
+}
+
+//*****************************************************************************
+//
+// Gets a data element from the SSI receive FIFO
+//
+//*****************************************************************************
+void
+SSIDataGet(uint32_t ui32Base, uint32_t *pui32Data)
+{
+ // Check the arguments.
+ ASSERT(SSIBaseValid(ui32Base));
+
+ // Wait until there is data to be read.
+ while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_RNE))
+ {
+ }
+
+ // Read data from SSI.
+ *pui32Data = HWREG(ui32Base + SSI_O_DR);
+}
+
+//*****************************************************************************
+//
+// Gets a data element from the SSI receive FIFO
+//
+//*****************************************************************************
+int32_t
+SSIDataGetNonBlocking(uint32_t ui32Base, uint32_t *pui32Data)
+{
+ // Check the arguments.
+ ASSERT(SSIBaseValid(ui32Base));
+
+ // Check for data to read.
+ if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_RNE)
+ {
+ *pui32Data = HWREG(ui32Base + SSI_O_DR);
+ return(1);
+ }
+ else
+ {
+ return(0);
+ }
+}
+
+//*****************************************************************************
+//
+// Registers an interrupt handler for the synchronous serial port
+//
+//*****************************************************************************
+void
+SSIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
+{
+ uint32_t ui32Int;
+
+ // Check the arguments.
+ ASSERT(SSIBaseValid(ui32Base));
+
+ // Determine the interrupt number based on the SSI port.
+ ui32Int = (ui32Base == SSI0_BASE) ? INT_SSI0_COMB : INT_SSI1_COMB;
+
+ // Register the interrupt handler.
+ IntRegister(ui32Int, pfnHandler);
+
+ // Enable the synchronous serial port interrupt.
+ IntEnable(ui32Int);
+}
+
+//*****************************************************************************
+//
+// Unregisters an interrupt handler for the synchronous serial port
+//
+//*****************************************************************************
+void
+SSIIntUnregister(uint32_t ui32Base)
+{
+ uint32_t ui32Int;
+
+ // Check the arguments.
+ ASSERT(SSIBaseValid(ui32Base));
+
+ // Determine the interrupt number based on the SSI port.
+ ui32Int = (ui32Base == SSI0_BASE) ? INT_SSI0_COMB : INT_SSI1_COMB;
+
+ // Disable the interrupt.
+ IntDisable(ui32Int);
+
+ // Unregister the interrupt handler.
+ IntUnregister(ui32Int);
+}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ssi.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ssi.h
new file mode 100644
index 0000000..21eacf8
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ssi.h
@@ -0,0 +1,700 @@
+/******************************************************************************
+* Filename: ssi.h
+* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017)
+* Revision: 49048
+*
+* Description: Defines and macros for the SSI.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup peripheral_group
+//! @{
+//! \addtogroup ssi_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __SSI_H__
+#define __SSI_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "../inc/hw_ints.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_types.h"
+#include "../inc/hw_ssi.h"
+#include "debug.h"
+#include "interrupt.h"
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// This section renames all functions that are not "static inline", so that
+// calling these functions will default to implementation in flash. At the end
+// of this file a second renaming will change the defaults to implementation in
+// ROM for available functions.
+//
+// To force use of the implementation in flash, e.g. for debugging:
+// - Globally: Define DRIVERLIB_NOROM at project level
+// - Per function: Use prefix "NOROM_" when calling the function
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #define SSIConfigSetExpClk NOROM_SSIConfigSetExpClk
+ #define SSIDataPut NOROM_SSIDataPut
+ #define SSIDataPutNonBlocking NOROM_SSIDataPutNonBlocking
+ #define SSIDataGet NOROM_SSIDataGet
+ #define SSIDataGetNonBlocking NOROM_SSIDataGetNonBlocking
+ #define SSIIntRegister NOROM_SSIIntRegister
+ #define SSIIntUnregister NOROM_SSIIntUnregister
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear
+// as the ui32IntFlags parameter, and returned by SSIIntStatus.
+//
+//*****************************************************************************
+#define SSI_TXFF 0x00000008 // TX FIFO half full or less
+#define SSI_RXFF 0x00000004 // RX FIFO half full or more
+#define SSI_RXTO 0x00000002 // RX timeout
+#define SSI_RXOR 0x00000001 // RX overrun
+
+//*****************************************************************************
+//
+// Values that are returned from SSIStatus
+//
+//*****************************************************************************
+#define SSI_RX_FULL 0x00000008 // Receive FIFO full
+#define SSI_RX_NOT_EMPTY 0x00000004 // Receive FIFO not empty
+#define SSI_TX_NOT_FULL 0x00000002 // Transmit FIFO not full
+#define SSI_TX_EMPTY 0x00000001 // Transmit FIFO empty
+#define SSI_STATUS_MASK 0x0000000F
+
+//*****************************************************************************
+//
+// Values that can be passed to SSIConfigSetExpClk.
+//
+//*****************************************************************************
+#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0
+#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1
+#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0
+#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1
+#define SSI_FRF_TI 0x00000010 // TI frame format
+#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format
+
+#define SSI_MODE_MASTER 0x00000000 // SSI master
+#define SSI_MODE_SLAVE 0x00000001 // SSI slave
+#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled
+
+//*****************************************************************************
+//
+// Values that can be passed to SSIDMAEnable() and SSIDMADisable().
+//
+//*****************************************************************************
+#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit
+#define SSI_DMA_RX 0x00000001 // Enable DMA for receive
+
+//*****************************************************************************
+//
+// API Functions and prototypes
+//
+//*****************************************************************************
+
+#ifdef DRIVERLIB_DEBUG
+//*****************************************************************************
+//
+//! \internal
+//!
+//! \brief Checks an SSI base address.
+//!
+//! This function determines if an SSI module base address is valid.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//!
+//! \return Returns \c true if the base address is valid and \c false
+//! otherwise.
+//
+//*****************************************************************************
+static bool
+SSIBaseValid(uint32_t ui32Base)
+{
+ return(ui32Base == SSI0_BASE || ui32Base == SSI1_BASE);
+}
+#endif
+
+//*****************************************************************************
+//
+//! \brief Configures the synchronous serial port.
+//!
+//! This function configures the synchronous serial port. It sets
+//! the SSI protocol, mode of operation, bit rate, and data width.
+//!
+//! The \c ui32Protocol parameter defines the data frame format. The Motorola
+//! frame formats imply the following polarity and phase configurations:
+//!
+//! <pre>
+//! Polarity Phase Mode
+//! 0 0 SSI_FRF_MOTO_MODE_0
+//! 0 1 SSI_FRF_MOTO_MODE_1
+//! 1 0 SSI_FRF_MOTO_MODE_2
+//! 1 1 SSI_FRF_MOTO_MODE_3
+//! </pre>
+//!
+//! The \c ui32Mode parameter defines the operating mode of the SSI module.
+//! The SSI module can operate as a master or slave; if a slave, the SSI can be
+//! configured to disable output on its serial output line.
+//!
+//! The \c ui32BitRate parameter defines the bit rate for the SSI. This bit
+//! rate must satisfy the following clock ratio criteria:
+//! - Master mode : FSSI >= 2 * bit rate
+//! - Slave mode : FSSI >= 12 * bit rate
+//!
+//! where FSSI is the frequency of the clock supplied to the SSI module.
+//!
+//! The \c ui32DataWidth parameter defines the width of the data transfers, and
+//! can be a value between 4 and 16, inclusive.
+//!
+//! \note The peripheral clock is not necessarily the same as the processor clock.
+//! The frequency of the peripheral clock is set by the system control.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//! \param ui32SSIClk is the rate of the clock supplied to the SSI module.
+//! \param ui32Protocol specifies the data transfer protocol.
+//! The parameter can be one of the following values:
+//! - \ref SSI_FRF_MOTO_MODE_0
+//! - \ref SSI_FRF_MOTO_MODE_1
+//! - \ref SSI_FRF_MOTO_MODE_2
+//! - \ref SSI_FRF_MOTO_MODE_3
+//! - \ref SSI_FRF_TI
+//! - \ref SSI_FRF_NMW.
+//! \param ui32Mode specifies the mode of operation.
+//! The parameter can be one of the following values:
+//! - \ref SSI_MODE_MASTER
+//! - \ref SSI_MODE_SLAVE
+//! - \ref SSI_MODE_SLAVE_OD
+//! \param ui32BitRate specifies the clock rate.
+//! \param ui32DataWidth specifies number of bits transferred per frame.
+//! Must be a value between 4 and 16, both included.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk,
+ uint32_t ui32Protocol, uint32_t ui32Mode,
+ uint32_t ui32BitRate, uint32_t ui32DataWidth);
+
+//*****************************************************************************
+//
+//! \brief Enables the synchronous serial port.
+//!
+//! This function enables operation of the synchronous serial port. The
+//! synchronous serial port must be configured before it is enabled.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+SSIEnable(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(SSIBaseValid(ui32Base));
+
+ // Read-modify-write the enable bit.
+ HWREG(ui32Base + SSI_O_CR1) |= SSI_CR1_SSE;
+}
+
+//*****************************************************************************
+//
+//! \brief Disables the synchronous serial port.
+//!
+//! This function disables operation of the synchronous serial port.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+SSIDisable(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(SSIBaseValid(ui32Base));
+
+ // Read-modify-write the enable bit.
+ HWREG(ui32Base + SSI_O_CR1) &= ~(SSI_CR1_SSE);
+}
+
+//*****************************************************************************
+//
+//! \brief Puts a data element into the SSI transmit FIFO.
+//!
+//! This function places the supplied data into the transmit FIFO of the
+//! specified SSI module.
+//!
+//! \note The upper 32 - N bits of the \c ui32Data are discarded by the
+//! hardware, where N is the data width as configured by \ref SSIConfigSetExpClk().
+//! For example, if the interface is configured for 8-bit data width, the upper
+//! 24 bits of \c ui32Data are discarded.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//! \param ui32Data is the data to be transmitted over the SSI interface.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void SSIDataPut(uint32_t ui32Base, uint32_t ui32Data);
+
+//*****************************************************************************
+//
+//! \brief Puts a data element into the SSI transmit FIFO.
+//!
+//! This function places the supplied data into the transmit FIFO of the
+//! specified SSI module. If there is no space in the FIFO, then this function
+//! returns a zero.
+//!
+//! \note The upper 32 - N bits of the \c ui32Data are discarded by the hardware,
+//! where N is the data width as configured by \ref SSIConfigSetExpClk(). For
+//! example, if the interface is configured for 8-bit data width, the upper 24
+//! bits of \c ui32Data are discarded.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//! \param ui32Data is the data to be transmitted over the SSI interface.
+//!
+//! \return Returns the number of elements written to the SSI transmit FIFO.
+//
+//*****************************************************************************
+extern int32_t SSIDataPutNonBlocking(uint32_t ui32Base, uint32_t ui32Data);
+
+//*****************************************************************************
+//
+//! \brief Gets a data element from the SSI receive FIFO.
+//!
+//! This function gets received data from the receive FIFO of the specified
+//! SSI module and places that data into the location specified by the
+//! \c pui32Data parameter.
+//!
+//! \note Only the lower N bits of the value written to \c pui32Data contain
+//! valid data, where N is the data width as configured by
+//! \ref SSIConfigSetExpClk(). For example, if the interface is configured for
+//! 8-bit data width, only the lower 8 bits of the value written to
+//! \c pui32Data contain valid data.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//! \param pui32Data is a pointer to a storage location for data that was
+//! received over the SSI interface.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void SSIDataGet(uint32_t ui32Base, uint32_t *pui32Data);
+
+//*****************************************************************************
+//
+//! \brief Gets a data element from the SSI receive FIFO.
+//!
+//! This function gets received data from the receive FIFO of the specified SSI
+//! module and places that data into the location specified by the \c ui32Data
+//! parameter. If there is no data in the FIFO, then this function returns a
+//! zero.
+//!
+//! \note Only the lower N bits of the value written to \c pui32Data contain
+//! valid data, where N is the data width as configured by
+//! \ref SSIConfigSetExpClk(). For example, if the interface is configured for
+//! 8-bit data width, only the lower 8 bits of the value written to \c pui32Data
+//! contain valid data.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//! \param pui32Data is a pointer to a storage location for data that was
+//! received over the SSI interface.
+//!
+//! \return Returns the number of elements read from the SSI receive FIFO.
+//
+//*****************************************************************************
+extern int32_t SSIDataGetNonBlocking(uint32_t ui32Base, uint32_t *pui32Data);
+
+//*****************************************************************************
+//
+//! \brief Determines whether the SSI transmitter is busy or not.
+//!
+//! Allows the caller to determine whether all transmitted bytes have cleared
+//! the transmitter hardware. If \c false is returned, then the transmit FIFO
+//! is empty and all bits of the last transmitted word have left the hardware
+//! shift register.
+//!
+//! \param ui32Base is the base address of the SSI port.
+//!
+//! \return Returns status of the SSI transmit buffer.
+//! - \c true : SSI is transmitting.
+//! - \c false : SSI transmissions are complete.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+SSIBusy(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(SSIBaseValid(ui32Base));
+
+ // Determine if the SSI is busy.
+ return((HWREG(ui32Base + SSI_O_SR) & SSI_SR_BSY) ? true : false);
+}
+
+//*****************************************************************************
+//
+//! \brief Get the status of the SSI data buffers.
+//!
+//! This function is used to poll the status of the internal FIFOs in the SSI
+//! module. The status of both TX and RX FIFO is returned.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//!
+//! \return Returns the current status of the internal SSI data buffers.
+//! The status is a bitwise OR'ed combination of:
+//! - \ref SSI_RX_FULL : Receive FIFO full.
+//! - \ref SSI_RX_NOT_EMPTY : Receive FIFO not empty.
+//! - \ref SSI_TX_NOT_FULL : Transmit FIFO not full.
+//! - \ref SSI_TX_EMPTY : Transmit FIFO empty.
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+SSIStatus(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(SSIBaseValid(ui32Base));
+
+ // Return the status
+ return (HWREG(ui32Base + SSI_O_SR) & SSI_STATUS_MASK);
+}
+
+//*****************************************************************************
+//
+//! \brief Registers an interrupt handler for the Synchronous Serial Interface in the dynamic interrupt table.
+//!
+//! \note Only use this function if you want to use the dynamic vector table (in SRAM)!
+//!
+//! This function registers a function as the interrupt handler for a specific
+//! interrupt and enables the corresponding interrupt in the interrupt controller.
+//!
+//! Specific SSI interrupts must be enabled via \ref SSIIntEnable(). If necessary,
+//! it is the interrupt handler's responsibility to clear the interrupt source
+//! via \ref SSIIntClear().
+//!
+//! \param ui32Base specifies the SSI module base address.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! synchronous serial port interrupt occurs.
+//!
+//! \return None
+//!
+//! \sa \ref IntRegister() for important information about registering interrupt
+//! handlers.
+//
+//*****************************************************************************
+extern void SSIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
+
+//*****************************************************************************
+//
+//! \brief Unregisters an interrupt handler for the Synchronous Serial Interface in the dynamic interrupt table.
+//!
+//! This function will clear the handler to be called when a SSI
+//! interrupt occurs. This will also mask off the interrupt in the interrupt
+//! controller so that the interrupt handler no longer is called.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//!
+//! \return None
+//!
+//! \sa \ref IntRegister() for important information about registering interrupt
+//! handlers.
+//
+//*****************************************************************************
+extern void SSIIntUnregister(uint32_t ui32Base);
+
+//*****************************************************************************
+//
+//! \brief Enables individual SSI interrupt sources.
+//!
+//! Enables the indicated SSI interrupt sources. Only the sources that are
+//! enabled can be reflected to the processor interrupt; disabled sources have
+//! no effect on the processor.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//! \param ui32IntFlags is a bit mask of the interrupt sources to be enabled.
+//! - \ref SSI_TXFF
+//! - \ref SSI_RXFF
+//! - \ref SSI_RXTO
+//! - \ref SSI_RXOR
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+SSIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ // Check the arguments.
+ ASSERT(SSIBaseValid(ui32Base));
+
+ // Enable the specified interrupts.
+ HWREG(ui32Base + SSI_O_IMSC) |= ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! \brief Disables individual SSI interrupt sources.
+//!
+//! Disables the indicated SSI interrupt sources.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//! \param ui32IntFlags is a bit mask of the interrupt sources to be disabled.
+//! - \ref SSI_TXFF
+//! - \ref SSI_RXFF
+//! - \ref SSI_RXTO
+//! - \ref SSI_RXOR
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+SSIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ // Check the arguments.
+ ASSERT(SSIBaseValid(ui32Base));
+
+ // Disable the specified interrupts.
+ HWREG(ui32Base + SSI_O_IMSC) &= ~(ui32IntFlags);
+}
+
+//*****************************************************************************
+//
+//! \brief Clears SSI interrupt sources.
+//!
+//! The specified SSI interrupt sources are cleared so that they no longer
+//! assert. This function must be called in the interrupt handler to keep the
+//! interrupts from being recognized again immediately upon exit.
+//!
+//! \note Due to write buffers and synchronizers in the system it may take several
+//! clock cycles from a register write clearing an event in a module and until the
+//! event is actually cleared in the NVIC of the system CPU. It is recommended to
+//! clear the event source early in the interrupt service routine (ISR) to allow
+//! the event clear to propagate to the NVIC before returning from the ISR.
+//! At the same time, an early event clear allows new events of the same type to be
+//! pended instead of ignored if the event is cleared later in the ISR.
+//! It is the responsibility of the programmer to make sure that enough time has passed
+//! before returning from the ISR to avoid false re-triggering of the cleared event.
+//! A simple, although not necessarily optimal, way of clearing an event before
+//! returning from the ISR is:
+//! -# Write to clear event (interrupt source). (buffered write)
+//! -# Dummy read from the event source module. (making sure the write has propagated)
+//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers)
+//!
+//! \param ui32Base specifies the SSI module base address.
+//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared.
+//! The parameter can consist of either or both of:
+//! - \ref SSI_RXTO : Timeout interrupt.
+//! - \ref SSI_RXOR : Overrun interrupt.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+SSIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ // Check the arguments.
+ ASSERT(SSIBaseValid(ui32Base));
+
+ // Clear the requested interrupt sources.
+ HWREG(ui32Base + SSI_O_ICR) = ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! \brief Gets the current interrupt status.
+//!
+//! This function returns the interrupt status for the SSI module. Either the
+//! raw interrupt status or the status of interrupts that are allowed to
+//! reflect to the processor can be returned.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//! \param bMasked selects either raw or masked interrupt.
+//! \c false : Raw interrupt status is required.
+//! \c true : Masked interrupt status is required.
+//!
+//! \return Returns the current interrupt status as an OR'ed combination of:
+//! - \ref SSI_TXFF
+//! - \ref SSI_RXFF
+//! - \ref SSI_RXTO
+//! - \ref SSI_RXOR
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+SSIIntStatus(uint32_t ui32Base, bool bMasked)
+{
+ // Check the arguments.
+ ASSERT(SSIBaseValid(ui32Base));
+
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ if(bMasked)
+ {
+ return(HWREG(ui32Base + SSI_O_MIS));
+ }
+ else
+ {
+ return(HWREG(ui32Base + SSI_O_RIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! \brief Enable SSI DMA operation.
+//!
+//! The specified SSI DMA features are enabled. The SSI can be
+//! configured to use DMA for transmit and/or receive data transfers.
+//!
+//! \note The uDMA controller must also be set up before DMA can be used
+//! with the SSI.
+//!
+//! \param ui32Base is the base address of the SSI port.
+//! \param ui32DMAFlags is a bit mask of the DMA features to enable.
+//! The parameter is the bitwise OR of any of the following values:
+//! - \ref SSI_DMA_RX : Enable DMA for receive.
+//! - \ref SSI_DMA_TX : Enable DMA for transmit.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+SSIDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags)
+{
+ // Check the arguments.
+ ASSERT(SSIBaseValid(ui32Base));
+
+ // Set the requested bits in the SSI DMA control register.
+ HWREG(ui32Base + SSI_O_DMACR) |= ui32DMAFlags;
+}
+
+//*****************************************************************************
+//
+//! \brief Disable SSI DMA operation.
+//!
+//! This function is used to disable SSI DMA features that were enabled
+//! by \ref SSIDMAEnable(). The specified SSI DMA features are disabled.
+//!
+//! \param ui32Base is the base address of the SSI port.
+//! \param ui32DMAFlags is a bit mask of the DMA features to disable.
+//! The parameter is the bitwise OR of any of the following values:
+//! - \ref SSI_DMA_RX : Disable DMA for receive.
+//! - \ref SSI_DMA_TX : Disable DMA for transmit.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+SSIDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags)
+{
+ // Check the arguments.
+ ASSERT(SSIBaseValid(ui32Base));
+
+ // Clear the requested bits in the SSI DMA control register.
+ HWREG(ui32Base + SSI_O_DMACR) &= ~ui32DMAFlags;
+}
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// Redirect to implementation in ROM when available.
+//
+//*****************************************************************************
+#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
+ #include "../driverlib/rom.h"
+ #ifdef ROM_SSIConfigSetExpClk
+ #undef SSIConfigSetExpClk
+ #define SSIConfigSetExpClk ROM_SSIConfigSetExpClk
+ #endif
+ #ifdef ROM_SSIDataPut
+ #undef SSIDataPut
+ #define SSIDataPut ROM_SSIDataPut
+ #endif
+ #ifdef ROM_SSIDataPutNonBlocking
+ #undef SSIDataPutNonBlocking
+ #define SSIDataPutNonBlocking ROM_SSIDataPutNonBlocking
+ #endif
+ #ifdef ROM_SSIDataGet
+ #undef SSIDataGet
+ #define SSIDataGet ROM_SSIDataGet
+ #endif
+ #ifdef ROM_SSIDataGetNonBlocking
+ #undef SSIDataGetNonBlocking
+ #define SSIDataGetNonBlocking ROM_SSIDataGetNonBlocking
+ #endif
+ #ifdef ROM_SSIIntRegister
+ #undef SSIIntRegister
+ #define SSIIntRegister ROM_SSIIntRegister
+ #endif
+ #ifdef ROM_SSIIntUnregister
+ #undef SSIIntUnregister
+ #define SSIIntUnregister ROM_SSIIntUnregister
+ #endif
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __SSI_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_chacha.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_chacha.c
new file mode 100644
index 0000000..781f48f
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_chacha.c
@@ -0,0 +1,121 @@
+/******************************************************************************
+* Filename: sw_chacha.c
+* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016)
+* Revision: 47308
+******************************************************************************/
+/*
+chacha-ref.c version 20080118
+D. J. Bernstein
+Public domain.
+*/
+
+#define ECRYPT_LITTLE_ENDIAN
+
+#include "sw_ecrypt-sync.h"
+
+#define ROTATE(v,c) (ROTL32(v,c))
+#define XOR(v,w) ((v) ^ (w))
+#define PLUS(v,w) (U32V((v) + (w)))
+#define PLUSONE(v) (PLUS((v),1))
+
+#define QUARTERROUND(a,b,c,d) \
+ x[a] = PLUS(x[a],x[b]); x[d] = ROTATE(XOR(x[d],x[a]),16); \
+ x[c] = PLUS(x[c],x[d]); x[b] = ROTATE(XOR(x[b],x[c]),12); \
+ x[a] = PLUS(x[a],x[b]); x[d] = ROTATE(XOR(x[d],x[a]), 8); \
+ x[c] = PLUS(x[c],x[d]); x[b] = ROTATE(XOR(x[b],x[c]), 7);
+
+static void salsa20_wordtobyte(u8 output[64],const u32 input[16])
+{
+ u32 x[16];
+ int i;
+
+ for (i = 0;i < 16;++i) x[i] = input[i];
+ for (i = 8;i > 0;i -= 2) {
+ QUARTERROUND( 0, 4, 8,12)
+ QUARTERROUND( 1, 5, 9,13)
+ QUARTERROUND( 2, 6,10,14)
+ QUARTERROUND( 3, 7,11,15)
+ QUARTERROUND( 0, 5,10,15)
+ QUARTERROUND( 1, 6,11,12)
+ QUARTERROUND( 2, 7, 8,13)
+ QUARTERROUND( 3, 4, 9,14)
+ }
+ for (i = 0;i < 16;++i) x[i] = PLUS(x[i],input[i]);
+ for (i = 0;i < 16;++i) U32TO8_LITTLE(output + 4 * i,x[i]);
+}
+
+void ECRYPT_init(void)
+{
+ return;
+}
+
+static const char sigma[16] = "expand 32-byte k";
+static const char tau[16] = "expand 16-byte k";
+
+void ECRYPT_keysetup(ECRYPT_ctx *x,const u8 *k,u32 kbits,u32 ivbits)
+{
+ const char *constants;
+
+ x->input[4] = U8TO32_LITTLE(k + 0);
+ x->input[5] = U8TO32_LITTLE(k + 4);
+ x->input[6] = U8TO32_LITTLE(k + 8);
+ x->input[7] = U8TO32_LITTLE(k + 12);
+ if (kbits == 256) { /* recommended */
+ k += 16;
+ constants = sigma;
+ } else { /* kbits == 128 */
+ constants = tau;
+ }
+ x->input[8] = U8TO32_LITTLE(k + 0);
+ x->input[9] = U8TO32_LITTLE(k + 4);
+ x->input[10] = U8TO32_LITTLE(k + 8);
+ x->input[11] = U8TO32_LITTLE(k + 12);
+ x->input[0] = U8TO32_LITTLE(constants + 0);
+ x->input[1] = U8TO32_LITTLE(constants + 4);
+ x->input[2] = U8TO32_LITTLE(constants + 8);
+ x->input[3] = U8TO32_LITTLE(constants + 12);
+}
+
+void ECRYPT_ivsetup(ECRYPT_ctx *x,const u8 *iv)
+{
+ x->input[12] = 0;
+ x->input[13] = 0;
+ x->input[14] = U8TO32_LITTLE(iv + 0);
+ x->input[15] = U8TO32_LITTLE(iv + 4);
+}
+
+void ECRYPT_encrypt_bytes(ECRYPT_ctx *x,const u8 *m,u8 *c,u32 bytes)
+{
+ u8 output[64];
+ int i;
+
+ if (!bytes) return;
+ for (;;) {
+ salsa20_wordtobyte(output,x->input);
+ x->input[12] = PLUSONE(x->input[12]);
+ if (!x->input[12]) {
+ x->input[13] = PLUSONE(x->input[13]);
+ /* stopping at 2^70 bytes per nonce is user's responsibility */
+ }
+ if (bytes <= 64) {
+ for (i = 0;i < bytes;++i) c[i] = m[i] ^ output[i];
+ return;
+ }
+ for (i = 0;i < 64;++i) c[i] = m[i] ^ output[i];
+ bytes -= 64;
+ c += 64;
+ m += 64;
+ }
+}
+
+void ECRYPT_decrypt_bytes(ECRYPT_ctx *x,const u8 *c,u8 *m,u32 bytes)
+{
+ ECRYPT_encrypt_bytes(x,c,m,bytes);
+}
+
+void ECRYPT_keystream_bytes(ECRYPT_ctx *x,u8 *stream,u32 bytes)
+{
+ u32 i;
+ for (i = 0;i < bytes;++i) stream[i] = 0;
+ ECRYPT_encrypt_bytes(x,stream,stream,bytes);
+}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-config.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-config.h
new file mode 100644
index 0000000..6ec233d
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-config.h
@@ -0,0 +1,279 @@
+/******************************************************************************
+* Filename: sw_ecrypt-config.h
+* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016)
+* Revision: 47308
+******************************************************************************/
+/* ecrypt-config.h */
+
+/* *** Normally, it should not be necessary to edit this file. *** */
+
+#ifndef ECRYPT_CONFIG
+#define ECRYPT_CONFIG
+
+/* ------------------------------------------------------------------------- */
+
+/* Guess the endianness of the target architecture. */
+
+/*
+ * The LITTLE endian machines:
+ */
+#if ( ! defined(ECRYPT_LITTLE_ENDIAN))
+#if defined(__ultrix) /* Older MIPS */
+#define ECRYPT_LITTLE_ENDIAN
+#elif defined(__alpha) /* Alpha */
+#define ECRYPT_LITTLE_ENDIAN
+#elif defined(i386) /* x86 (gcc) */
+#define ECRYPT_LITTLE_ENDIAN
+#elif defined(__i386) /* x86 (gcc) */
+#define ECRYPT_LITTLE_ENDIAN
+#elif defined(_M_IX86) /* x86 (MSC, Borland) */
+#define ECRYPT_LITTLE_ENDIAN
+#elif defined(_MSC_VER) /* x86 (surely MSC) */
+#define ECRYPT_LITTLE_ENDIAN
+#elif defined(__INTEL_COMPILER) /* x86 (surely Intel compiler icl.exe) */
+#define ECRYPT_LITTLE_ENDIAN
+
+/*
+ * The BIG endian machines:
+ */
+#elif defined(sun) /* Newer Sparc's */
+#define ECRYPT_BIG_ENDIAN
+#elif defined(__ppc__) /* PowerPC */
+#define ECRYPT_BIG_ENDIAN
+
+/*
+ * Finally machines with UNKNOWN endianness:
+ */
+#elif defined (_AIX) /* RS6000 */
+#define ECRYPT_UNKNOWN
+#elif defined(__hpux) /* HP-PA */
+#define ECRYPT_UNKNOWN
+#elif defined(__aux) /* 68K */
+#define ECRYPT_UNKNOWN
+#elif defined(__dgux) /* 88K (but P6 in latest boxes) */
+#define ECRYPT_UNKNOWN
+#elif defined(__sgi) /* Newer MIPS */
+#define ECRYPT_UNKNOWN
+#else /* Any other processor */
+#define ECRYPT_UNKNOWN
+#endif
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Find minimal-width types to store 8-bit, 16-bit, 32-bit, and 64-bit
+ * integers.
+ *
+ * Note: to enable 64-bit types on 32-bit compilers, it might be
+ * necessary to switch from ISO C90 mode to ISO C99 mode (e.g., gcc
+ * -std=c99).
+ */
+
+#include <limits.h>
+
+/* --- check char --- */
+
+#if (UCHAR_MAX / 0xFU > 0xFU)
+#ifndef I8T
+#define I8T char
+#define U8C(v) (v##U)
+
+#if (UCHAR_MAX == 0xFFU)
+#define ECRYPT_I8T_IS_BYTE
+#endif
+
+#endif
+
+#if (UCHAR_MAX / 0xFFU > 0xFFU)
+#ifndef I16T
+#define I16T char
+#define U16C(v) (v##U)
+#endif
+
+#if (UCHAR_MAX / 0xFFFFU > 0xFFFFU)
+#ifndef I32T
+#define I32T char
+#define U32C(v) (v##U)
+#endif
+
+#if (UCHAR_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU)
+#ifndef I64T
+#define I64T char
+#define U64C(v) (v##U)
+#define ECRYPT_NATIVE64
+#endif
+
+#endif
+#endif
+#endif
+#endif
+
+/* --- check short --- */
+
+#if (USHRT_MAX / 0xFU > 0xFU)
+#ifndef I8T
+#define I8T short
+#define U8C(v) (v##U)
+
+#if (USHRT_MAX == 0xFFU)
+#define ECRYPT_I8T_IS_BYTE
+#endif
+
+#endif
+
+#if (USHRT_MAX / 0xFFU > 0xFFU)
+#ifndef I16T
+#define I16T short
+#define U16C(v) (v##U)
+#endif
+
+#if (USHRT_MAX / 0xFFFFU > 0xFFFFU)
+#ifndef I32T
+#define I32T short
+#define U32C(v) (v##U)
+#endif
+
+#if (USHRT_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU)
+#ifndef I64T
+#define I64T short
+#define U64C(v) (v##U)
+#define ECRYPT_NATIVE64
+#endif
+
+#endif
+#endif
+#endif
+#endif
+
+/* --- check int --- */
+
+#if (UINT_MAX / 0xFU > 0xFU)
+#ifndef I8T
+#define I8T int
+#define U8C(v) (v##U)
+
+#if (ULONG_MAX == 0xFFU)
+#define ECRYPT_I8T_IS_BYTE
+#endif
+
+#endif
+
+#if (UINT_MAX / 0xFFU > 0xFFU)
+#ifndef I16T
+#define I16T int
+#define U16C(v) (v##U)
+#endif
+
+#if (UINT_MAX / 0xFFFFU > 0xFFFFU)
+#ifndef I32T
+#define I32T int
+#define U32C(v) (v##U)
+#endif
+
+#if (UINT_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU)
+#ifndef I64T
+#define I64T int
+#define U64C(v) (v##U)
+#define ECRYPT_NATIVE64
+#endif
+
+#endif
+#endif
+#endif
+#endif
+
+/* --- check long --- */
+
+#if (ULONG_MAX / 0xFUL > 0xFUL)
+#ifndef I8T
+#define I8T long
+#define U8C(v) (v##UL)
+
+#if (ULONG_MAX == 0xFFUL)
+#define ECRYPT_I8T_IS_BYTE
+#endif
+
+#endif
+
+#if (ULONG_MAX / 0xFFUL > 0xFFUL)
+#ifndef I16T
+#define I16T long
+#define U16C(v) (v##UL)
+#endif
+
+#if (ULONG_MAX / 0xFFFFUL > 0xFFFFUL)
+#ifndef I32T
+#define I32T long
+#define U32C(v) (v##UL)
+#endif
+
+#if (ULONG_MAX / 0xFFFFFFFFUL > 0xFFFFFFFFUL)
+#ifndef I64T
+#define I64T long
+#define U64C(v) (v##UL)
+#define ECRYPT_NATIVE64
+#endif
+
+#endif
+#endif
+#endif
+#endif
+
+/* --- check long long --- */
+
+#ifdef ULLONG_MAX
+
+#if (ULLONG_MAX / 0xFULL > 0xFULL)
+#ifndef I8T
+#define I8T long long
+#define U8C(v) (v##ULL)
+
+#if (ULLONG_MAX == 0xFFULL)
+#define ECRYPT_I8T_IS_BYTE
+#endif
+
+#endif
+
+#if (ULLONG_MAX / 0xFFULL > 0xFFULL)
+#ifndef I16T
+#define I16T long long
+#define U16C(v) (v##ULL)
+#endif
+
+#if (ULLONG_MAX / 0xFFFFULL > 0xFFFFULL)
+#ifndef I32T
+#define I32T long long
+#define U32C(v) (v##ULL)
+#endif
+
+#if (ULLONG_MAX / 0xFFFFFFFFULL > 0xFFFFFFFFULL)
+#ifndef I64T
+#define I64T long long
+#define U64C(v) (v##ULL)
+#endif
+
+#endif
+#endif
+#endif
+#endif
+
+#endif
+
+/* --- check __int64 --- */
+
+#ifdef _UI64_MAX
+
+#if (_UI64_MAX / 0xFFFFFFFFui64 > 0xFFFFFFFFui64)
+#ifndef I64T
+#define I64T __int64
+#define U64C(v) (v##ui64)
+#endif
+
+#endif
+
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+#endif
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-machine.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-machine.h
new file mode 100644
index 0000000..7194dcb
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-machine.h
@@ -0,0 +1,51 @@
+/******************************************************************************
+* Filename: sw_ecrypt-machine.h
+* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016)
+* Revision: 47308
+******************************************************************************/
+/* ecrypt-machine.h */
+
+/*
+ * This file is included by 'ecrypt-portable.h'. It allows to override
+ * the default macros for specific platforms. Please carefully check
+ * the machine code generated by your compiler (with optimisations
+ * turned on) before deciding to edit this file.
+ */
+
+/* ------------------------------------------------------------------------- */
+
+#if (defined(ECRYPT_DEFAULT_ROT) && !defined(ECRYPT_MACHINE_ROT))
+
+#define ECRYPT_MACHINE_ROT
+
+#if (defined(WIN32) && defined(_MSC_VER))
+
+#undef ROTL32
+#undef ROTR32
+#undef ROTL64
+#undef ROTR64
+
+#include <stdlib.h>
+
+#define ROTL32(v, n) _lrotl(v, n)
+#define ROTR32(v, n) _lrotr(v, n)
+#define ROTL64(v, n) _rotl64(v, n)
+#define ROTR64(v, n) _rotr64(v, n)
+
+#endif
+
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+#if (defined(ECRYPT_DEFAULT_SWAP) && !defined(ECRYPT_MACHINE_SWAP))
+
+#define ECRYPT_MACHINE_SWAP
+
+/*
+ * If you want to overwrite the default swap macros, put it here. And so on.
+ */
+
+#endif
+
+/* ------------------------------------------------------------------------- */
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-portable.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-portable.h
new file mode 100644
index 0000000..dd81b83
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-portable.h
@@ -0,0 +1,308 @@
+/******************************************************************************
+* Filename: sw_ecrypt-portable.h
+* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016)
+* Revision: 47308
+******************************************************************************/
+/* ecrypt-portable.h */
+
+/*
+ * WARNING: the conversions defined below are implemented as macros,
+ * and should be used carefully. They should NOT be used with
+ * parameters which perform some action. E.g., the following two lines
+ * are not equivalent:
+ *
+ * 1) ++x; y = ROTL32(x, n);
+ * 2) y = ROTL32(++x, n);
+ */
+
+/*
+ * *** Please do not edit this file. ***
+ *
+ * The default macros can be overridden for specific architectures by
+ * editing 'ecrypt-machine.h'.
+ */
+
+#ifndef ECRYPT_PORTABLE
+#define ECRYPT_PORTABLE
+
+#include "sw_ecrypt-config.h"
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * The following types are defined (if available):
+ *
+ * u8: unsigned integer type, at least 8 bits
+ * u16: unsigned integer type, at least 16 bits
+ * u32: unsigned integer type, at least 32 bits
+ * u64: unsigned integer type, at least 64 bits
+ *
+ * s8, s16, s32, s64 -> signed counterparts of u8, u16, u32, u64
+ *
+ * The selection of minimum-width integer types is taken care of by
+ * 'ecrypt-config.h'. Note: to enable 64-bit types on 32-bit
+ * compilers, it might be necessary to switch from ISO C90 mode to ISO
+ * C99 mode (e.g., gcc -std=c99).
+ */
+
+#ifdef I8T
+typedef signed I8T s8;
+typedef unsigned I8T u8;
+#endif
+
+#ifdef I16T
+typedef signed I16T s16;
+typedef unsigned I16T u16;
+#endif
+
+#ifdef I32T
+typedef signed I32T s32;
+typedef unsigned I32T u32;
+#endif
+
+#ifdef I64T
+typedef signed I64T s64;
+typedef unsigned I64T u64;
+#endif
+
+/*
+ * The following macros are used to obtain exact-width results.
+ */
+
+#define U8V(v) ((u8)(v) & U8C(0xFF))
+#define U16V(v) ((u16)(v) & U16C(0xFFFF))
+#define U32V(v) ((u32)(v) & U32C(0xFFFFFFFF))
+#define U64V(v) ((u64)(v) & U64C(0xFFFFFFFFFFFFFFFF))
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * The following macros return words with their bits rotated over n
+ * positions to the left/right.
+ */
+
+#define ECRYPT_DEFAULT_ROT
+
+#define ROTL8(v, n) \
+ (U8V((v) << (n)) | ((v) >> (8 - (n))))
+
+#define ROTL16(v, n) \
+ (U16V((v) << (n)) | ((v) >> (16 - (n))))
+
+#define ROTL32(v, n) \
+ (U32V((v) << (n)) | ((v) >> (32 - (n))))
+
+#define ROTL64(v, n) \
+ (U64V((v) << (n)) | ((v) >> (64 - (n))))
+
+#define ROTR8(v, n) ROTL8(v, 8 - (n))
+#define ROTR16(v, n) ROTL16(v, 16 - (n))
+#define ROTR32(v, n) ROTL32(v, 32 - (n))
+#define ROTR64(v, n) ROTL64(v, 64 - (n))
+
+#include "sw_ecrypt-machine.h"
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * The following macros return a word with bytes in reverse order.
+ */
+
+#define ECRYPT_DEFAULT_SWAP
+
+#define SWAP16(v) \
+ ROTL16(v, 8)
+
+#define SWAP32(v) \
+ ((ROTL32(v, 8) & U32C(0x00FF00FF)) | \
+ (ROTL32(v, 24) & U32C(0xFF00FF00)))
+
+#ifdef ECRYPT_NATIVE64
+#define SWAP64(v) \
+ ((ROTL64(v, 8) & U64C(0x000000FF000000FF)) | \
+ (ROTL64(v, 24) & U64C(0x0000FF000000FF00)) | \
+ (ROTL64(v, 40) & U64C(0x00FF000000FF0000)) | \
+ (ROTL64(v, 56) & U64C(0xFF000000FF000000)))
+#else
+#define SWAP64(v) \
+ (((u64)SWAP32(U32V(v)) << 32) | (u64)SWAP32(U32V(v >> 32)))
+#endif
+
+#include "sw_ecrypt-machine.h"
+
+#define ECRYPT_DEFAULT_WTOW
+
+#ifdef ECRYPT_LITTLE_ENDIAN
+#define U16TO16_LITTLE(v) (v)
+#define U32TO32_LITTLE(v) (v)
+#define U64TO64_LITTLE(v) (v)
+
+#define U16TO16_BIG(v) SWAP16(v)
+#define U32TO32_BIG(v) SWAP32(v)
+#define U64TO64_BIG(v) SWAP64(v)
+#endif
+
+#ifdef ECRYPT_BIG_ENDIAN
+#define U16TO16_LITTLE(v) SWAP16(v)
+#define U32TO32_LITTLE(v) SWAP32(v)
+#define U64TO64_LITTLE(v) SWAP64(v)
+
+#define U16TO16_BIG(v) (v)
+#define U32TO32_BIG(v) (v)
+#define U64TO64_BIG(v) (v)
+#endif
+
+#include "sw_ecrypt-machine.h"
+
+/*
+ * The following macros load words from an array of bytes with
+ * different types of endianness, and vice versa.
+ */
+
+#define ECRYPT_DEFAULT_BTOW
+
+#if (!defined(ECRYPT_UNKNOWN) && defined(ECRYPT_I8T_IS_BYTE))
+
+#define U8TO16_LITTLE(p) U16TO16_LITTLE(((u16*)(p))[0])
+#define U8TO32_LITTLE(p) U32TO32_LITTLE(((u32*)(p))[0])
+#define U8TO64_LITTLE(p) U64TO64_LITTLE(((u64*)(p))[0])
+
+#define U8TO16_BIG(p) U16TO16_BIG(((u16*)(p))[0])
+#define U8TO32_BIG(p) U32TO32_BIG(((u32*)(p))[0])
+#define U8TO64_BIG(p) U64TO64_BIG(((u64*)(p))[0])
+
+#define U16TO8_LITTLE(p, v) (((u16*)(p))[0] = U16TO16_LITTLE(v))
+#define U32TO8_LITTLE(p, v) (((u32*)(p))[0] = U32TO32_LITTLE(v))
+#define U64TO8_LITTLE(p, v) (((u64*)(p))[0] = U64TO64_LITTLE(v))
+
+#define U16TO8_BIG(p, v) (((u16*)(p))[0] = U16TO16_BIG(v))
+#define U32TO8_BIG(p, v) (((u32*)(p))[0] = U32TO32_BIG(v))
+#define U64TO8_BIG(p, v) (((u64*)(p))[0] = U64TO64_BIG(v))
+
+#else
+
+#define U8TO16_LITTLE(p) \
+ (((u16)((p)[0]) ) | \
+ ((u16)((p)[1]) << 8))
+
+#define U8TO32_LITTLE(p) \
+ (((u32)((p)[0]) ) | \
+ ((u32)((p)[1]) << 8) | \
+ ((u32)((p)[2]) << 16) | \
+ ((u32)((p)[3]) << 24))
+
+#ifdef ECRYPT_NATIVE64
+#define U8TO64_LITTLE(p) \
+ (((u64)((p)[0]) ) | \
+ ((u64)((p)[1]) << 8) | \
+ ((u64)((p)[2]) << 16) | \
+ ((u64)((p)[3]) << 24) | \
+ ((u64)((p)[4]) << 32) | \
+ ((u64)((p)[5]) << 40) | \
+ ((u64)((p)[6]) << 48) | \
+ ((u64)((p)[7]) << 56))
+#else
+#define U8TO64_LITTLE(p) \
+ ((u64)U8TO32_LITTLE(p) | ((u64)U8TO32_LITTLE((p) + 4) << 32))
+#endif
+
+#define U8TO16_BIG(p) \
+ (((u16)((p)[0]) << 8) | \
+ ((u16)((p)[1]) ))
+
+#define U8TO32_BIG(p) \
+ (((u32)((p)[0]) << 24) | \
+ ((u32)((p)[1]) << 16) | \
+ ((u32)((p)[2]) << 8) | \
+ ((u32)((p)[3]) ))
+
+#ifdef ECRYPT_NATIVE64
+#define U8TO64_BIG(p) \
+ (((u64)((p)[0]) << 56) | \
+ ((u64)((p)[1]) << 48) | \
+ ((u64)((p)[2]) << 40) | \
+ ((u64)((p)[3]) << 32) | \
+ ((u64)((p)[4]) << 24) | \
+ ((u64)((p)[5]) << 16) | \
+ ((u64)((p)[6]) << 8) | \
+ ((u64)((p)[7]) ))
+#else
+#define U8TO64_BIG(p) \
+ (((u64)U8TO32_BIG(p) << 32) | (u64)U8TO32_BIG((p) + 4))
+#endif
+
+#define U16TO8_LITTLE(p, v) \
+ do { \
+ (p)[0] = U8V((v) ); \
+ (p)[1] = U8V((v) >> 8); \
+ } while (0)
+
+#define U32TO8_LITTLE(p, v) \
+ do { \
+ (p)[0] = U8V((v) ); \
+ (p)[1] = U8V((v) >> 8); \
+ (p)[2] = U8V((v) >> 16); \
+ (p)[3] = U8V((v) >> 24); \
+ } while (0)
+
+#ifdef ECRYPT_NATIVE64
+#define U64TO8_LITTLE(p, v) \
+ do { \
+ (p)[0] = U8V((v) ); \
+ (p)[1] = U8V((v) >> 8); \
+ (p)[2] = U8V((v) >> 16); \
+ (p)[3] = U8V((v) >> 24); \
+ (p)[4] = U8V((v) >> 32); \
+ (p)[5] = U8V((v) >> 40); \
+ (p)[6] = U8V((v) >> 48); \
+ (p)[7] = U8V((v) >> 56); \
+ } while (0)
+#else
+#define U64TO8_LITTLE(p, v) \
+ do { \
+ U32TO8_LITTLE((p), U32V((v) )); \
+ U32TO8_LITTLE((p) + 4, U32V((v) >> 32)); \
+ } while (0)
+#endif
+
+#define U16TO8_BIG(p, v) \
+ do { \
+ (p)[0] = U8V((v) ); \
+ (p)[1] = U8V((v) >> 8); \
+ } while (0)
+
+#define U32TO8_BIG(p, v) \
+ do { \
+ (p)[0] = U8V((v) >> 24); \
+ (p)[1] = U8V((v) >> 16); \
+ (p)[2] = U8V((v) >> 8); \
+ (p)[3] = U8V((v) ); \
+ } while (0)
+
+#ifdef ECRYPT_NATIVE64
+#define U64TO8_BIG(p, v) \
+ do { \
+ (p)[0] = U8V((v) >> 56); \
+ (p)[1] = U8V((v) >> 48); \
+ (p)[2] = U8V((v) >> 40); \
+ (p)[3] = U8V((v) >> 32); \
+ (p)[4] = U8V((v) >> 24); \
+ (p)[5] = U8V((v) >> 16); \
+ (p)[6] = U8V((v) >> 8); \
+ (p)[7] = U8V((v) ); \
+ } while (0)
+#else
+#define U64TO8_BIG(p, v) \
+ do { \
+ U32TO8_BIG((p), U32V((v) >> 32)); \
+ U32TO8_BIG((p) + 4, U32V((v) )); \
+ } while (0)
+#endif
+
+#endif
+
+#include "sw_ecrypt-machine.h"
+
+/* ------------------------------------------------------------------------- */
+
+#endif
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-sync.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-sync.h
new file mode 100644
index 0000000..436d108
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-sync.h
@@ -0,0 +1,284 @@
+/******************************************************************************
+* Filename: sw_ecrypt-sync.h
+* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016)
+* Revision: 47308
+******************************************************************************/
+/* ecrypt-sync.h */
+
+/*
+ * Header file for synchronous stream ciphers without authentication
+ * mechanism.
+ *
+ * *** Please only edit parts marked with "[edit]". ***
+ */
+
+#ifndef ECRYPT_SYNC
+#define ECRYPT_SYNC
+
+#include "sw_ecrypt-portable.h"
+
+/* ------------------------------------------------------------------------- */
+
+/* Cipher parameters */
+
+/*
+ * The name of your cipher.
+ */
+#define ECRYPT_NAME "ChaCha8"
+#define ECRYPT_PROFILE "_____"
+
+/*
+ * Specify which key and IV sizes are supported by your cipher. A user
+ * should be able to enumerate the supported sizes by running the
+ * following code:
+ *
+ * for (i = 0; ECRYPT_KEYSIZE(i) <= ECRYPT_MAXKEYSIZE; ++i)
+ * {
+ * keysize = ECRYPT_KEYSIZE(i);
+ *
+ * ...
+ * }
+ *
+ * All sizes are in bits.
+ */
+
+#define ECRYPT_MAXKEYSIZE 256 /* [edit] */
+#define ECRYPT_KEYSIZE(i) (128 + (i)*128) /* [edit] */
+
+#define ECRYPT_MAXIVSIZE 64 /* [edit] */
+#define ECRYPT_IVSIZE(i) (64 + (i)*64) /* [edit] */
+
+/* ------------------------------------------------------------------------- */
+
+/* Data structures */
+
+/*
+ * ECRYPT_ctx is the structure containing the representation of the
+ * internal state of your cipher.
+ */
+
+typedef struct
+{
+ u32 input[16]; /* could be compressed */
+ /*
+ * [edit]
+ *
+ * Put here all state variable needed during the encryption process.
+ */
+} ECRYPT_ctx;
+
+/* ------------------------------------------------------------------------- */
+
+/* Mandatory functions */
+
+/*
+ * Key and message independent initialization. This function will be
+ * called once when the program starts (e.g., to build expanded S-box
+ * tables).
+ */
+void ECRYPT_init(void);
+
+/*
+ * Key setup. It is the user's responsibility to select the values of
+ * keysize and ivsize from the set of supported values specified
+ * above.
+ */
+void ECRYPT_keysetup(
+ ECRYPT_ctx* ctx,
+ const u8* key,
+ u32 keysize, /* Key size in bits. */
+ u32 ivsize); /* IV size in bits. */
+
+/*
+ * IV setup. After having called ECRYPT_keysetup(), the user is
+ * allowed to call ECRYPT_ivsetup() different times in order to
+ * encrypt/decrypt different messages with the same key but different
+ * IV's.
+ */
+void ECRYPT_ivsetup(
+ ECRYPT_ctx* ctx,
+ const u8* iv);
+
+/*
+ * Encryption/decryption of arbitrary length messages.
+ *
+ * For efficiency reasons, the API provides two types of
+ * encrypt/decrypt functions. The ECRYPT_encrypt_bytes() function
+ * (declared here) encrypts byte strings of arbitrary length, while
+ * the ECRYPT_encrypt_blocks() function (defined later) only accepts
+ * lengths which are multiples of ECRYPT_BLOCKLENGTH.
+ *
+ * The user is allowed to make multiple calls to
+ * ECRYPT_encrypt_blocks() to incrementally encrypt a long message,
+ * but he is NOT allowed to make additional encryption calls once he
+ * has called ECRYPT_encrypt_bytes() (unless he starts a new message
+ * of course). For example, this sequence of calls is acceptable:
+ *
+ * ECRYPT_keysetup();
+ *
+ * ECRYPT_ivsetup();
+ * ECRYPT_encrypt_blocks();
+ * ECRYPT_encrypt_blocks();
+ * ECRYPT_encrypt_bytes();
+ *
+ * ECRYPT_ivsetup();
+ * ECRYPT_encrypt_blocks();
+ * ECRYPT_encrypt_blocks();
+ *
+ * ECRYPT_ivsetup();
+ * ECRYPT_encrypt_bytes();
+ *
+ * The following sequence is not:
+ *
+ * ECRYPT_keysetup();
+ * ECRYPT_ivsetup();
+ * ECRYPT_encrypt_blocks();
+ * ECRYPT_encrypt_bytes();
+ * ECRYPT_encrypt_blocks();
+ */
+
+void ECRYPT_encrypt_bytes(
+ ECRYPT_ctx* ctx,
+ const u8* plaintext,
+ u8* ciphertext,
+ u32 msglen); /* Message length in bytes. */
+
+void ECRYPT_decrypt_bytes(
+ ECRYPT_ctx* ctx,
+ const u8* ciphertext,
+ u8* plaintext,
+ u32 msglen); /* Message length in bytes. */
+
+/* ------------------------------------------------------------------------- */
+
+/* Optional features */
+
+/*
+ * For testing purposes it can sometimes be useful to have a function
+ * which immediately generates keystream without having to provide it
+ * with a zero plaintext. If your cipher cannot provide this function
+ * (e.g., because it is not strictly a synchronous cipher), please
+ * reset the ECRYPT_GENERATES_KEYSTREAM flag.
+ */
+
+#define ECRYPT_GENERATES_KEYSTREAM
+#ifdef ECRYPT_GENERATES_KEYSTREAM
+
+void ECRYPT_keystream_bytes(
+ ECRYPT_ctx* ctx,
+ u8* keystream,
+ u32 length); /* Length of keystream in bytes. */
+
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+/* Optional optimizations */
+
+/*
+ * By default, the functions in this section are implemented using
+ * calls to functions declared above. However, you might want to
+ * implement them differently for performance reasons.
+ */
+
+/*
+ * All-in-one encryption/decryption of (short) packets.
+ *
+ * The default definitions of these functions can be found in
+ * "ecrypt-sync.c". If you want to implement them differently, please
+ * undef the ECRYPT_USES_DEFAULT_ALL_IN_ONE flag.
+ */
+#define ECRYPT_USES_DEFAULT_ALL_IN_ONE /* [edit] */
+
+void ECRYPT_encrypt_packet(
+ ECRYPT_ctx* ctx,
+ const u8* iv,
+ const u8* plaintext,
+ u8* ciphertext,
+ u32 msglen);
+
+void ECRYPT_decrypt_packet(
+ ECRYPT_ctx* ctx,
+ const u8* iv,
+ const u8* ciphertext,
+ u8* plaintext,
+ u32 msglen);
+
+/*
+ * Encryption/decryption of blocks.
+ *
+ * By default, these functions are defined as macros. If you want to
+ * provide a different implementation, please undef the
+ * ECRYPT_USES_DEFAULT_BLOCK_MACROS flag and implement the functions
+ * declared below.
+ */
+
+#define ECRYPT_BLOCKLENGTH 64 /* [edit] */
+
+#define ECRYPT_USES_DEFAULT_BLOCK_MACROS /* [edit] */
+#ifdef ECRYPT_USES_DEFAULT_BLOCK_MACROS
+
+#define ECRYPT_encrypt_blocks(ctx, plaintext, ciphertext, blocks) \
+ ECRYPT_encrypt_bytes(ctx, plaintext, ciphertext, \
+ (blocks) * ECRYPT_BLOCKLENGTH)
+
+#define ECRYPT_decrypt_blocks(ctx, ciphertext, plaintext, blocks) \
+ ECRYPT_decrypt_bytes(ctx, ciphertext, plaintext, \
+ (blocks) * ECRYPT_BLOCKLENGTH)
+
+#ifdef ECRYPT_GENERATES_KEYSTREAM
+
+#define ECRYPT_keystream_blocks(ctx, keystream, blocks) \
+ ECRYPT_keystream_bytes(ctx, keystream, \
+ (blocks) * ECRYPT_BLOCKLENGTH)
+
+#endif
+
+#else
+
+void ECRYPT_encrypt_blocks(
+ ECRYPT_ctx* ctx,
+ const u8* plaintext,
+ u8* ciphertext,
+ u32 blocks); /* Message length in blocks. */
+
+void ECRYPT_decrypt_blocks(
+ ECRYPT_ctx* ctx,
+ const u8* ciphertext,
+ u8* plaintext,
+ u32 blocks); /* Message length in blocks. */
+
+#ifdef ECRYPT_GENERATES_KEYSTREAM
+
+void ECRYPT_keystream_blocks(
+ ECRYPT_ctx* ctx,
+ const u8* keystream,
+ u32 blocks); /* Keystream length in blocks. */
+
+#endif
+
+#endif
+
+/*
+ * If your cipher can be implemented in different ways, you can use
+ * the ECRYPT_VARIANT parameter to allow the user to choose between
+ * them at compile time (e.g., gcc -DECRYPT_VARIANT=3 ...). Please
+ * only use this possibility if you really think it could make a
+ * significant difference and keep the number of variants
+ * (ECRYPT_MAXVARIANT) as small as possible (definitely not more than
+ * 10). Note also that all variants should have exactly the same
+ * external interface (i.e., the same ECRYPT_BLOCKLENGTH, etc.).
+ */
+#define ECRYPT_MAXVARIANT 1 /* [edit] */
+
+#ifndef ECRYPT_VARIANT
+#define ECRYPT_VARIANT 1
+#endif
+
+#if (ECRYPT_VARIANT > ECRYPT_MAXVARIANT)
+#error this variant does not exist
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+#endif
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_poly1305-donna-32.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_poly1305-donna-32.h
new file mode 100644
index 0000000..b25d40a
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_poly1305-donna-32.h
@@ -0,0 +1,223 @@
+/******************************************************************************
+* Filename: sw_poly1305-donna-32.h
+* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016)
+* Revision: 47308
+******************************************************************************/
+/*
+ poly1305 implementation using 32 bit * 32 bit = 64 bit multiplication and 64 bit addition
+*/
+
+#if defined(_MSC_VER)
+ #define POLY1305_NOINLINE __declspec(noinline)
+#elif defined(__GNUC__)
+ #define POLY1305_NOINLINE __attribute__((noinline))
+#else
+ #define POLY1305_NOINLINE
+#endif
+
+#define poly1305_block_size 16
+
+/* 17 + sizeof(size_t) + 14*sizeof(unsigned long) */
+typedef struct {
+ unsigned long r[5];
+ unsigned long h[5];
+ unsigned long pad[4];
+ size_t leftover;
+ unsigned char buffer[poly1305_block_size];
+ unsigned char final;
+} poly1305_state_internal_t;
+
+/* interpret four 8 bit unsigned integers as a 32 bit unsigned integer in little endian */
+static unsigned long
+U8TO32(const unsigned char *p) {
+ return
+ (((unsigned long)(p[0] & 0xff) ) |
+ ((unsigned long)(p[1] & 0xff) << 8) |
+ ((unsigned long)(p[2] & 0xff) << 16) |
+ ((unsigned long)(p[3] & 0xff) << 24));
+}
+
+/* store a 32 bit unsigned integer as four 8 bit unsigned integers in little endian */
+static void
+U32TO8(unsigned char *p, unsigned long v) {
+ p[0] = (v ) & 0xff;
+ p[1] = (v >> 8) & 0xff;
+ p[2] = (v >> 16) & 0xff;
+ p[3] = (v >> 24) & 0xff;
+}
+
+void
+poly1305_init(poly1305_context *ctx, const unsigned char key[32]) {
+ poly1305_state_internal_t *st = (poly1305_state_internal_t *)ctx;
+
+ /* r &= 0xffffffc0ffffffc0ffffffc0fffffff */
+ st->r[0] = (U8TO32(&key[ 0]) ) & 0x3ffffff;
+ st->r[1] = (U8TO32(&key[ 3]) >> 2) & 0x3ffff03;
+ st->r[2] = (U8TO32(&key[ 6]) >> 4) & 0x3ffc0ff;
+ st->r[3] = (U8TO32(&key[ 9]) >> 6) & 0x3f03fff;
+ st->r[4] = (U8TO32(&key[12]) >> 8) & 0x00fffff;
+
+ /* h = 0 */
+ st->h[0] = 0;
+ st->h[1] = 0;
+ st->h[2] = 0;
+ st->h[3] = 0;
+ st->h[4] = 0;
+
+ /* save pad for later */
+ st->pad[0] = U8TO32(&key[16]);
+ st->pad[1] = U8TO32(&key[20]);
+ st->pad[2] = U8TO32(&key[24]);
+ st->pad[3] = U8TO32(&key[28]);
+
+ st->leftover = 0;
+ st->final = 0;
+}
+
+static void
+poly1305_blocks(poly1305_state_internal_t *st, const unsigned char *m, size_t bytes) {
+ const unsigned long hibit = (st->final) ? 0 : (1UL << 24); /* 1 << 128 */
+ unsigned long r0,r1,r2,r3,r4;
+ unsigned long s1,s2,s3,s4;
+ unsigned long h0,h1,h2,h3,h4;
+ unsigned long long d0,d1,d2,d3,d4;
+ unsigned long c;
+
+ r0 = st->r[0];
+ r1 = st->r[1];
+ r2 = st->r[2];
+ r3 = st->r[3];
+ r4 = st->r[4];
+
+ s1 = r1 * 5;
+ s2 = r2 * 5;
+ s3 = r3 * 5;
+ s4 = r4 * 5;
+
+ h0 = st->h[0];
+ h1 = st->h[1];
+ h2 = st->h[2];
+ h3 = st->h[3];
+ h4 = st->h[4];
+
+ while (bytes >= poly1305_block_size) {
+ /* h += m[i] */
+ h0 += (U8TO32(m+ 0) ) & 0x3ffffff;
+ h1 += (U8TO32(m+ 3) >> 2) & 0x3ffffff;
+ h2 += (U8TO32(m+ 6) >> 4) & 0x3ffffff;
+ h3 += (U8TO32(m+ 9) >> 6) & 0x3ffffff;
+ h4 += (U8TO32(m+12) >> 8) | hibit;
+
+ /* h *= r */
+ d0 = ((unsigned long long)h0 * r0) + ((unsigned long long)h1 * s4) + ((unsigned long long)h2 * s3) + ((unsigned long long)h3 * s2) + ((unsigned long long)h4 * s1);
+ d1 = ((unsigned long long)h0 * r1) + ((unsigned long long)h1 * r0) + ((unsigned long long)h2 * s4) + ((unsigned long long)h3 * s3) + ((unsigned long long)h4 * s2);
+ d2 = ((unsigned long long)h0 * r2) + ((unsigned long long)h1 * r1) + ((unsigned long long)h2 * r0) + ((unsigned long long)h3 * s4) + ((unsigned long long)h4 * s3);
+ d3 = ((unsigned long long)h0 * r3) + ((unsigned long long)h1 * r2) + ((unsigned long long)h2 * r1) + ((unsigned long long)h3 * r0) + ((unsigned long long)h4 * s4);
+ d4 = ((unsigned long long)h0 * r4) + ((unsigned long long)h1 * r3) + ((unsigned long long)h2 * r2) + ((unsigned long long)h3 * r1) + ((unsigned long long)h4 * r0);
+
+ /* (partial) h %= p */
+ c = (unsigned long)(d0 >> 26); h0 = (unsigned long)d0 & 0x3ffffff;
+ d1 += c; c = (unsigned long)(d1 >> 26); h1 = (unsigned long)d1 & 0x3ffffff;
+ d2 += c; c = (unsigned long)(d2 >> 26); h2 = (unsigned long)d2 & 0x3ffffff;
+ d3 += c; c = (unsigned long)(d3 >> 26); h3 = (unsigned long)d3 & 0x3ffffff;
+ d4 += c; c = (unsigned long)(d4 >> 26); h4 = (unsigned long)d4 & 0x3ffffff;
+ h0 += c * 5; c = (h0 >> 26); h0 = h0 & 0x3ffffff;
+ h1 += c;
+
+ m += poly1305_block_size;
+ bytes -= poly1305_block_size;
+ }
+
+ st->h[0] = h0;
+ st->h[1] = h1;
+ st->h[2] = h2;
+ st->h[3] = h3;
+ st->h[4] = h4;
+}
+
+POLY1305_NOINLINE void
+poly1305_finish(poly1305_context *ctx, unsigned char mac[16]) {
+ poly1305_state_internal_t *st = (poly1305_state_internal_t *)ctx;
+ unsigned long h0,h1,h2,h3,h4,c;
+ unsigned long g0,g1,g2,g3,g4;
+ unsigned long long f;
+ unsigned long mask;
+
+ /* process the remaining block */
+ if (st->leftover) {
+ size_t i = st->leftover;
+ st->buffer[i++] = 1;
+ for (; i < poly1305_block_size; i++)
+ st->buffer[i] = 0;
+ st->final = 1;
+ poly1305_blocks(st, st->buffer, poly1305_block_size);
+ }
+
+ /* fully carry h */
+ h0 = st->h[0];
+ h1 = st->h[1];
+ h2 = st->h[2];
+ h3 = st->h[3];
+ h4 = st->h[4];
+
+ c = h1 >> 26; h1 = h1 & 0x3ffffff;
+ h2 += c; c = h2 >> 26; h2 = h2 & 0x3ffffff;
+ h3 += c; c = h3 >> 26; h3 = h3 & 0x3ffffff;
+ h4 += c; c = h4 >> 26; h4 = h4 & 0x3ffffff;
+ h0 += c * 5; c = h0 >> 26; h0 = h0 & 0x3ffffff;
+ h1 += c;
+
+ /* compute h + -p */
+ g0 = h0 + 5; c = g0 >> 26; g0 &= 0x3ffffff;
+ g1 = h1 + c; c = g1 >> 26; g1 &= 0x3ffffff;
+ g2 = h2 + c; c = g2 >> 26; g2 &= 0x3ffffff;
+ g3 = h3 + c; c = g3 >> 26; g3 &= 0x3ffffff;
+ g4 = h4 + c - (1UL << 26);
+
+ /* select h if h < p, or h + -p if h >= p */
+ mask = (g4 >> ((sizeof(unsigned long) * 8) - 1)) - 1;
+ g0 &= mask;
+ g1 &= mask;
+ g2 &= mask;
+ g3 &= mask;
+ g4 &= mask;
+ mask = ~mask;
+ h0 = (h0 & mask) | g0;
+ h1 = (h1 & mask) | g1;
+ h2 = (h2 & mask) | g2;
+ h3 = (h3 & mask) | g3;
+ h4 = (h4 & mask) | g4;
+
+ /* h = h % (2^128) */
+ h0 = ((h0 ) | (h1 << 26)) & 0xffffffff;
+ h1 = ((h1 >> 6) | (h2 << 20)) & 0xffffffff;
+ h2 = ((h2 >> 12) | (h3 << 14)) & 0xffffffff;
+ h3 = ((h3 >> 18) | (h4 << 8)) & 0xffffffff;
+
+ /* mac = (h + pad) % (2^128) */
+ f = (unsigned long long)h0 + st->pad[0] ; h0 = (unsigned long)f;
+ f = (unsigned long long)h1 + st->pad[1] + (f >> 32); h1 = (unsigned long)f;
+ f = (unsigned long long)h2 + st->pad[2] + (f >> 32); h2 = (unsigned long)f;
+ f = (unsigned long long)h3 + st->pad[3] + (f >> 32); h3 = (unsigned long)f;
+
+ U32TO8(mac + 0, h0);
+ U32TO8(mac + 4, h1);
+ U32TO8(mac + 8, h2);
+ U32TO8(mac + 12, h3);
+
+ /* zero out the state */
+ st->h[0] = 0;
+ st->h[1] = 0;
+ st->h[2] = 0;
+ st->h[3] = 0;
+ st->h[4] = 0;
+ st->r[0] = 0;
+ st->r[1] = 0;
+ st->r[2] = 0;
+ st->r[3] = 0;
+ st->r[4] = 0;
+ st->pad[0] = 0;
+ st->pad[1] = 0;
+ st->pad[2] = 0;
+ st->pad[3] = 0;
+}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_poly1305-donna.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_poly1305-donna.c
new file mode 100644
index 0000000..63234fe
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_poly1305-donna.c
@@ -0,0 +1,186 @@
+/******************************************************************************
+* Filename: sw_poly1305-donna.c
+* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016)
+* Revision: 47308
+******************************************************************************/
+
+#include "sw_poly1305-donna.h"
+
+#include "sw_poly1305-donna-32.h"
+
+void
+poly1305_update(poly1305_context *ctx, const unsigned char *m, size_t bytes) {
+ poly1305_state_internal_t *st = (poly1305_state_internal_t *)ctx;
+ size_t i;
+
+ /* handle leftover */
+ if (st->leftover) {
+ size_t want = (poly1305_block_size - st->leftover);
+ if (want > bytes)
+ want = bytes;
+ for (i = 0; i < want; i++)
+ st->buffer[st->leftover + i] = m[i];
+ bytes -= want;
+ m += want;
+ st->leftover += want;
+ if (st->leftover < poly1305_block_size)
+ return;
+ poly1305_blocks(st, st->buffer, poly1305_block_size);
+ st->leftover = 0;
+ }
+
+ /* process full blocks */
+ if (bytes >= poly1305_block_size) {
+ size_t want = (bytes & ~(poly1305_block_size - 1));
+ poly1305_blocks(st, m, want);
+ m += want;
+ bytes -= want;
+ }
+
+ /* store leftover */
+ if (bytes) {
+ for (i = 0; i < bytes; i++)
+ st->buffer[st->leftover + i] = m[i];
+ st->leftover += bytes;
+ }
+}
+
+void
+poly1305_auth(unsigned char mac[16], const unsigned char *m, size_t bytes, const unsigned char key[32]) {
+ poly1305_context ctx;
+ poly1305_init(&ctx, key);
+ poly1305_update(&ctx, m, bytes);
+ poly1305_finish(&ctx, mac);
+}
+
+int
+poly1305_verify(const unsigned char mac1[16], const unsigned char mac2[16]) {
+ size_t i;
+ unsigned int dif = 0;
+ for (i = 0; i < 16; i++)
+ dif |= (mac1[i] ^ mac2[i]);
+ dif = (dif - 1) >> ((sizeof(unsigned int) * 8) - 1);
+ return (dif & 1);
+}
+
+
+/* test a few basic operations */
+int
+poly1305_power_on_self_test(void) {
+ /* example from nacl */
+ static const unsigned char nacl_key[32] = {
+ 0xee,0xa6,0xa7,0x25,0x1c,0x1e,0x72,0x91,
+ 0x6d,0x11,0xc2,0xcb,0x21,0x4d,0x3c,0x25,
+ 0x25,0x39,0x12,0x1d,0x8e,0x23,0x4e,0x65,
+ 0x2d,0x65,0x1f,0xa4,0xc8,0xcf,0xf8,0x80
+ };
+
+ static const unsigned char nacl_msg[131] = {
+ 0x8e,0x99,0x3b,0x9f,0x48,0x68,0x12,0x73,
+ 0xc2,0x96,0x50,0xba,0x32,0xfc,0x76,0xce,
+ 0x48,0x33,0x2e,0xa7,0x16,0x4d,0x96,0xa4,
+ 0x47,0x6f,0xb8,0xc5,0x31,0xa1,0x18,0x6a,
+ 0xc0,0xdf,0xc1,0x7c,0x98,0xdc,0xe8,0x7b,
+ 0x4d,0xa7,0xf0,0x11,0xec,0x48,0xc9,0x72,
+ 0x71,0xd2,0xc2,0x0f,0x9b,0x92,0x8f,0xe2,
+ 0x27,0x0d,0x6f,0xb8,0x63,0xd5,0x17,0x38,
+ 0xb4,0x8e,0xee,0xe3,0x14,0xa7,0xcc,0x8a,
+ 0xb9,0x32,0x16,0x45,0x48,0xe5,0x26,0xae,
+ 0x90,0x22,0x43,0x68,0x51,0x7a,0xcf,0xea,
+ 0xbd,0x6b,0xb3,0x73,0x2b,0xc0,0xe9,0xda,
+ 0x99,0x83,0x2b,0x61,0xca,0x01,0xb6,0xde,
+ 0x56,0x24,0x4a,0x9e,0x88,0xd5,0xf9,0xb3,
+ 0x79,0x73,0xf6,0x22,0xa4,0x3d,0x14,0xa6,
+ 0x59,0x9b,0x1f,0x65,0x4c,0xb4,0x5a,0x74,
+ 0xe3,0x55,0xa5
+ };
+
+ static const unsigned char nacl_mac[16] = {
+ 0xf3,0xff,0xc7,0x70,0x3f,0x94,0x00,0xe5,
+ 0x2a,0x7d,0xfb,0x4b,0x3d,0x33,0x05,0xd9
+ };
+
+ /* generates a final value of (2^130 - 2) == 3 */
+ static const unsigned char wrap_key[32] = {
+ 0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+ };
+
+ static const unsigned char wrap_msg[16] = {
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff
+ };
+
+ static const unsigned char wrap_mac[16] = {
+ 0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+ };
+
+ /*
+ mac of the macs of messages of length 0 to 256, where the key and messages
+ have all their values set to the length
+ */
+ static const unsigned char total_key[32] = {
+ 0x01,0x02,0x03,0x04,0x05,0x06,0x07,
+ 0xff,0xfe,0xfd,0xfc,0xfb,0xfa,0xf9,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff
+ };
+
+ static const unsigned char total_mac[16] = {
+ 0x64,0xaf,0xe2,0xe8,0xd6,0xad,0x7b,0xbd,
+ 0xd2,0x87,0xf9,0x7c,0x44,0x62,0x3d,0x39
+ };
+
+ poly1305_context ctx;
+ poly1305_context total_ctx;
+ unsigned char all_key[32];
+ unsigned char all_msg[256];
+ unsigned char mac[16];
+ size_t i, j;
+ int result = 1;
+
+ for (i = 0; i < sizeof(mac); i++)
+ mac[i] = 0;
+ poly1305_auth(mac, nacl_msg, sizeof(nacl_msg), nacl_key);
+ result &= poly1305_verify(nacl_mac, mac);
+
+ for (i = 0; i < sizeof(mac); i++)
+ mac[i] = 0;
+ poly1305_init(&ctx, nacl_key);
+ poly1305_update(&ctx, nacl_msg + 0, 32);
+ poly1305_update(&ctx, nacl_msg + 32, 64);
+ poly1305_update(&ctx, nacl_msg + 96, 16);
+ poly1305_update(&ctx, nacl_msg + 112, 8);
+ poly1305_update(&ctx, nacl_msg + 120, 4);
+ poly1305_update(&ctx, nacl_msg + 124, 2);
+ poly1305_update(&ctx, nacl_msg + 126, 1);
+ poly1305_update(&ctx, nacl_msg + 127, 1);
+ poly1305_update(&ctx, nacl_msg + 128, 1);
+ poly1305_update(&ctx, nacl_msg + 129, 1);
+ poly1305_update(&ctx, nacl_msg + 130, 1);
+ poly1305_finish(&ctx, mac);
+ result &= poly1305_verify(nacl_mac, mac);
+
+ for (i = 0; i < sizeof(mac); i++)
+ mac[i] = 0;
+ poly1305_auth(mac, wrap_msg, sizeof(wrap_msg), wrap_key);
+ result &= poly1305_verify(wrap_mac, mac);
+
+ poly1305_init(&total_ctx, total_key);
+ for (i = 0; i < 256; i++) {
+ /* set key and message to 'i,i,i..' */
+ for (j = 0; j < sizeof(all_key); j++)
+ all_key[j] = i;
+ for (j = 0; j < i; j++)
+ all_msg[j] = i;
+ poly1305_auth(mac, all_msg, i, all_key);
+ poly1305_update(&total_ctx, mac, 16);
+ }
+ poly1305_finish(&total_ctx, mac);
+ result &= poly1305_verify(total_mac, mac);
+
+ return result;
+}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_poly1305-donna.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_poly1305-donna.h
new file mode 100644
index 0000000..2c91e4a
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_poly1305-donna.h
@@ -0,0 +1,25 @@
+/******************************************************************************
+* Filename: sw_poly1305-donna.h
+* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016)
+* Revision: 47308
+******************************************************************************/
+
+#ifndef POLY1305_DONNA_H
+#define POLY1305_DONNA_H
+
+#include <stddef.h>
+
+typedef struct {
+ size_t aligner;
+ unsigned char opaque[136];
+} poly1305_context;
+
+void poly1305_init(poly1305_context *ctx, const unsigned char key[32]);
+void poly1305_update(poly1305_context *ctx, const unsigned char *m, size_t bytes);
+void poly1305_finish(poly1305_context *ctx, unsigned char mac[16]);
+void poly1305_auth(unsigned char mac[16], const unsigned char *m, size_t bytes, const unsigned char key[32]);
+
+int poly1305_verify(const unsigned char mac1[16], const unsigned char mac2[16]);
+int poly1305_power_on_self_test(void);
+
+#endif /* POLY1305_DONNA_H */
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sys_ctrl.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sys_ctrl.c
new file mode 100644
index 0000000..1dd35f4
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sys_ctrl.c
@@ -0,0 +1,375 @@
+/******************************************************************************
+* Filename: sys_ctrl.c
+* Revised: 2018-06-26 15:19:11 +0200 (Tue, 26 Jun 2018)
+* Revision: 52220
+*
+* Description: Driver for the System Control.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+// Hardware headers
+#include "../inc/hw_types.h"
+#include "../inc/hw_ccfg.h"
+#include "../inc/hw_ioc.h"
+// Driverlib headers
+#include "aon_batmon.h"
+#include "flash.h"
+#include "gpio.h"
+#include "setup_rom.h"
+#include "sys_ctrl.h"
+
+
+//*****************************************************************************
+//
+// Handle support for DriverLib in ROM:
+// This section will undo prototype renaming made in the header file
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #undef SysCtrlIdle
+ #define SysCtrlIdle NOROM_SysCtrlIdle
+ #undef SysCtrlShutdownWithAbort
+ #define SysCtrlShutdownWithAbort NOROM_SysCtrlShutdownWithAbort
+ #undef SysCtrlShutdown
+ #define SysCtrlShutdown NOROM_SysCtrlShutdown
+ #undef SysCtrlStandby
+ #define SysCtrlStandby NOROM_SysCtrlStandby
+ #undef SysCtrlSetRechargeBeforePowerDown
+ #define SysCtrlSetRechargeBeforePowerDown NOROM_SysCtrlSetRechargeBeforePowerDown
+ #undef SysCtrlAdjustRechargeAfterPowerDown
+ #define SysCtrlAdjustRechargeAfterPowerDown NOROM_SysCtrlAdjustRechargeAfterPowerDown
+ #undef SysCtrl_DCDC_VoltageConditionalControl
+ #define SysCtrl_DCDC_VoltageConditionalControl NOROM_SysCtrl_DCDC_VoltageConditionalControl
+ #undef SysCtrlResetSourceGet
+ #define SysCtrlResetSourceGet NOROM_SysCtrlResetSourceGet
+#endif
+
+
+
+//*****************************************************************************
+//
+// Force the system in to idle mode
+//
+//*****************************************************************************
+void SysCtrlIdle(uint32_t vimsPdMode)
+{
+ // Configure the VIMS mode
+ HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS) = vimsPdMode;
+
+ // Always keep cache retention ON in IDLE
+ PRCMCacheRetentionEnable();
+
+ // Turn off the CPU power domain, will take effect when PRCMDeepSleep() executes
+ PRCMPowerDomainOff(PRCM_DOMAIN_CPU);
+
+ // Ensure any possible outstanding AON writes complete
+ SysCtrlAonSync();
+
+ // Invoke deep sleep to go to IDLE
+ PRCMDeepSleep();
+}
+
+//*****************************************************************************
+//
+// Try to enter shutdown but abort if wakeup event happened before shutdown
+//
+//*****************************************************************************
+void SysCtrlShutdownWithAbort(void)
+{
+ uint32_t wu_detect_vector = 0;
+ uint32_t io_num = 0;
+
+ // For all IO CFG registers check if wakeup detect is enabled
+ for(io_num = 0; io_num < 32; io_num++)
+ {
+ // Read MSB from WU_CFG bit field
+ if( HWREG(IOC_BASE + IOC_O_IOCFG0 + (io_num * 4) ) & (1 << (IOC_IOCFG0_WU_CFG_S + IOC_IOCFG0_WU_CFG_W - 1)) )
+ {
+ wu_detect_vector |= (1 << io_num);
+ }
+ }
+
+ // Wakeup events are detected when pads are in sleep mode
+ PowerCtrlPadSleepEnable();
+
+ // Make sure all potential events have propagated before checking event flags
+ SysCtrlAonUpdate();
+ SysCtrlAonUpdate();
+
+ // If no edge detect flags for wakeup enabled IOs are set then shut down the device
+ if( GPIO_getEventMultiDio(wu_detect_vector) == 0 )
+ {
+ SysCtrlShutdown();
+ }
+ else
+ {
+ PowerCtrlPadSleepDisable();
+ }
+}
+
+//*****************************************************************************
+//
+// Force the system into shutdown mode
+//
+//*****************************************************************************
+void SysCtrlShutdown(void)
+{
+ // Request shutdown mode
+ HWREG(AON_PMCTL_BASE + AON_PMCTL_O_SHUTDOWN) = AON_PMCTL_SHUTDOWN_EN;
+
+ // Make sure System CPU does not continue beyond this point.
+ // Shutdown happens when all shutdown conditions are met.
+ while(1);
+}
+
+//*****************************************************************************
+//
+// Force the system in to standby mode
+//
+//*****************************************************************************
+void SysCtrlStandby(bool retainCache, uint32_t vimsPdMode, uint32_t rechargeMode)
+{
+ uint32_t modeVIMS;
+
+ // Freeze the IOs on the boundary between MCU and AON
+ AONIOCFreezeEnable();
+
+ // Ensure any possible outstanding AON writes complete before turning off the power domains
+ SysCtrlAonSync();
+
+ // Request power off of domains in the MCU voltage domain
+ PRCMPowerDomainOff(PRCM_DOMAIN_RFCORE | PRCM_DOMAIN_SERIAL | PRCM_DOMAIN_PERIPH | PRCM_DOMAIN_CPU);
+
+ // Ensure that no clocks are forced on in any modes for Crypto, DMA and I2S
+ HWREG(PRCM_BASE + PRCM_O_SECDMACLKGR) &= (~PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN & ~PRCM_SECDMACLKGR_DMA_AM_CLK_EN);
+ HWREG(PRCM_BASE + PRCM_O_I2SCLKGR) &= ~PRCM_I2SCLKGR_AM_CLK_EN;
+
+ // Gate running deep sleep clocks for Crypto, DMA and I2S
+ PRCMPeripheralDeepSleepDisable(PRCM_PERIPH_CRYPTO);
+ PRCMPeripheralDeepSleepDisable(PRCM_PERIPH_UDMA);
+ PRCMPeripheralDeepSleepDisable(PRCM_PERIPH_I2S);
+
+ // Load the new clock settings
+ PRCMLoadSet();
+
+ // Configure the VIMS power domain mode
+ HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS) = vimsPdMode;
+
+ // Request uLDO during standby
+ PRCMMcuUldoConfigure(1);
+
+ // Check the regulator mode
+ if (HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) & AON_PMCTL_PWRCTL_EXT_REG_MODE)
+ {
+ // In external regulator mode the recharge functionality is disabled
+ HWREG(AON_PMCTL_BASE + AON_PMCTL_O_RECHARGECFG) = 0x00000000;
+ }
+ else
+ {
+ // In internal regulator mode the recharge functionality is set up with
+ // adaptive recharge mode and fixed parameter values
+ if(rechargeMode == SYSCTRL_PREFERRED_RECHARGE_MODE)
+ {
+ // Enable the Recharge Comparator
+ HWREG(AON_PMCTL_BASE + AON_PMCTL_O_RECHARGECFG) = AON_PMCTL_RECHARGECFG_MODE_COMPARATOR;
+ }
+ else
+ {
+ // Set requested recharge mode
+ HWREG(AON_PMCTL_BASE + AON_PMCTL_O_RECHARGECFG) = rechargeMode;
+ }
+ }
+
+ // Ensure all writes have taken effect
+ SysCtrlAonSync();
+
+ // Ensure UDMA, Crypto and I2C clocks are turned off
+ while (!PRCMLoadGet()) {;}
+
+ // Ensure power domains have been turned off.
+ // CPU power domain will power down when PRCMDeepSleep() executes.
+ while (PRCMPowerDomainStatus(PRCM_DOMAIN_RFCORE | PRCM_DOMAIN_SERIAL | PRCM_DOMAIN_PERIPH) != PRCM_DOMAIN_POWER_OFF) {;}
+
+ // Turn off cache retention if requested
+ if (retainCache == false) {
+
+ // Get the current VIMS mode
+ do {
+ modeVIMS = VIMSModeGet(VIMS_BASE);
+ } while (modeVIMS == VIMS_MODE_CHANGING);
+
+ // If in a cache mode, turn VIMS off
+ if (modeVIMS == VIMS_MODE_ENABLED) {
+ VIMSModeSet(VIMS_BASE, VIMS_MODE_OFF);
+ }
+
+ // Disable retention of cache RAM
+ PRCMCacheRetentionDisable();
+ }
+
+ // Invoke deep sleep to go to STANDBY
+ PRCMDeepSleep();
+}
+
+//*****************************************************************************
+//
+// SysCtrlSetRechargeBeforePowerDown( xoscPowerMode )
+//
+//*****************************************************************************
+void
+SysCtrlSetRechargeBeforePowerDown( uint32_t xoscPowerMode )
+{
+ uint32_t ccfg_ModeConfReg ;
+
+ // read the MODE_CONF register in CCFG
+ ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF );
+ // Do temperature compensation if enabled
+ if (( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC ) == 0 ) {
+ int32_t vddrSleepDelta ;
+ int32_t curTemp ;
+ int32_t tcDelta ;
+ int32_t vddrSleepTrim ;
+
+ // Get VDDR_TRIM_SLEEP_DELTA + 1 (sign extended) ==> vddrSleepDelta = -7..+8
+ vddrSleepDelta = (((int32_t)( ccfg_ModeConfReg << ( 32 - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S )))
+ >> ( 32 - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W )) + 1 ;
+ curTemp = AONBatMonTemperatureGetDegC();
+ tcDelta = ( 62 - curTemp ) >> 3;
+ if ( tcDelta > 7 ) {
+ tcDelta = 7 ;
+ }
+ if ( tcDelta > vddrSleepDelta ) {
+ vddrSleepDelta = tcDelta ;
+ }
+ vddrSleepTrim = (( HWREG( FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_MISC_TRIM ) & FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_REFLEVEL_M ) >>
+ FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_REFLEVEL_S ) ;
+ vddrSleepTrim -= vddrSleepDelta ;
+ if ( vddrSleepTrim > 15 ) vddrSleepTrim = 15 ;
+ if ( vddrSleepTrim < 1 ) vddrSleepTrim = 1 ;
+ // Write adjusted value using MASKED write (MASK8)
+ HWREGB( ADI3_BASE + ADI_O_MASK4B + ( ADI_3_REFSYS_O_CTL_RECHARGE_CMP0 * 2 )) = (( ADI_3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL_M << 4 ) |
+ (( vddrSleepTrim << ADI_3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL_S ) & ADI_3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL_M ) );
+ // Make a dummy read in order to make sure the write above is done before going into standby
+ HWREGB( ADI3_BASE + ADI_3_REFSYS_O_CTL_RECHARGE_CMP0 );
+ }
+}
+
+
+//*****************************************************************************
+//
+// SysCtrlAdjustRechargeAfterPowerDown()
+//
+//*****************************************************************************
+void
+SysCtrlAdjustRechargeAfterPowerDown( uint32_t vddrRechargeMargin )
+{
+ // Nothing to be done but keeping this function for platform compatibility.
+}
+
+
+//*****************************************************************************
+//
+// SysCtrl_DCDC_VoltageConditionalControl()
+//
+//*****************************************************************************
+void
+SysCtrl_DCDC_VoltageConditionalControl( void )
+{
+ uint32_t batThreshold ; // Fractional format with 8 fractional bits.
+ uint32_t aonBatmonBat ; // Fractional format with 8 fractional bits.
+ uint32_t ccfg_ModeConfReg ; // Holds a copy of the CCFG_O_MODE_CONF register.
+ uint32_t aonPmctlPwrctl ; // Reflect whats read/written to the AON_PMCTL_O_PWRCTL register.
+
+ // We could potentially call this function before any battery voltage measurement
+ // is made/available. In that case we must make sure that we do not turn off the DCDC.
+ // This can be done by doing nothing as long as the battery voltage is 0 (Since the
+ // reset value of the battery voltage register is 0).
+ aonBatmonBat = HWREG( AON_BATMON_BASE + AON_BATMON_O_BAT );
+ if ( aonBatmonBat != 0 ) {
+ // Check if Voltage Conditional Control is enabled
+ // It is enabled if all the following are true:
+ // - DCDC in use (either in active or recharge mode), (in use if one of the corresponding CCFG bits are zero).
+ // - Alternative DCDC settings are enabled ( DIS_ALT_DCDC_SETTING == 0 )
+ // - Not in external regulator mode ( EXT_REG_MODE == 0 )
+ ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF );
+
+ if (((( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_RECHARGE_M ) == 0 ) ||
+ (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_ACTIVE_M ) == 0 ) ) &&
+ (( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ) & AON_PMCTL_PWRCTL_EXT_REG_MODE ) == 0 ) &&
+ (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING ) == 0 ) )
+ {
+ aonPmctlPwrctl = HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL );
+ batThreshold = (((( HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ) &
+ CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M ) >>
+ CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S ) + 28 ) << 4 );
+
+ if ( aonPmctlPwrctl & ( AON_PMCTL_PWRCTL_DCDC_EN_M | AON_PMCTL_PWRCTL_DCDC_ACTIVE_M )) {
+ // DCDC is ON, check if it should be switched off
+ if ( aonBatmonBat < batThreshold ) {
+ aonPmctlPwrctl &= ~( AON_PMCTL_PWRCTL_DCDC_EN_M | AON_PMCTL_PWRCTL_DCDC_ACTIVE_M );
+
+ HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ) = aonPmctlPwrctl;
+ }
+ } else {
+ // DCDC is OFF, check if it should be switched on
+ if ( aonBatmonBat > batThreshold ) {
+ if (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_RECHARGE_M ) == 0 ) aonPmctlPwrctl |= AON_PMCTL_PWRCTL_DCDC_EN_M ;
+ if (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_ACTIVE_M ) == 0 ) aonPmctlPwrctl |= AON_PMCTL_PWRCTL_DCDC_ACTIVE_M ;
+
+ HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ) = aonPmctlPwrctl;
+ }
+ }
+ }
+ }
+}
+
+
+//*****************************************************************************
+//
+// SysCtrlResetSourceGet()
+//
+//*****************************************************************************
+uint32_t
+SysCtrlResetSourceGet( void )
+{
+ uint32_t aonPmctlResetCtl = HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL );
+
+ if ( aonPmctlResetCtl & AON_PMCTL_RESETCTL_WU_FROM_SD_M ) {
+ if ( aonPmctlResetCtl & AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD_M ) {
+ return ( RSTSRC_WAKEUP_FROM_SHUTDOWN );
+ } else {
+ return ( RSTSRC_WAKEUP_FROM_TCK_NOISE );
+ }
+ } else {
+ return (( aonPmctlResetCtl & AON_PMCTL_RESETCTL_RESET_SRC_M ) >> AON_PMCTL_RESETCTL_RESET_SRC_S );
+ }
+}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sys_ctrl.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sys_ctrl.h
new file mode 100644
index 0000000..6dbe831
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sys_ctrl.h
@@ -0,0 +1,577 @@
+/******************************************************************************
+* Filename: sys_ctrl.h
+* Revised: 2018-09-17 14:58:51 +0200 (Mon, 17 Sep 2018)
+* Revision: 52634
+*
+* Description: Defines and prototypes for the System Controller.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup system_control_group
+//! @{
+//! \addtogroup sysctrl_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __SYSCTRL_H__
+#define __SYSCTRL_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "../inc/hw_types.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_ints.h"
+#include "../inc/hw_sysctl.h"
+#include "../inc/hw_prcm.h"
+#include "../inc/hw_nvic.h"
+#include "../inc/hw_aon_ioc.h"
+#include "../inc/hw_ddi_0_osc.h"
+#include "../inc/hw_rfc_pwr.h"
+#include "../inc/hw_prcm.h"
+#include "../inc/hw_adi_3_refsys.h"
+#include "../inc/hw_aon_pmctl.h"
+#include "../inc/hw_aon_rtc.h"
+#include "../inc/hw_fcfg1.h"
+#include "interrupt.h"
+#include "debug.h"
+#include "pwr_ctrl.h"
+#include "osc.h"
+#include "prcm.h"
+#include "adi.h"
+#include "ddi.h"
+#include "cpu.h"
+#include "vims.h"
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// This section renames all functions that are not "static inline", so that
+// calling these functions will default to implementation in flash. At the end
+// of this file a second renaming will change the defaults to implementation in
+// ROM for available functions.
+//
+// To force use of the implementation in flash, e.g. for debugging:
+// - Globally: Define DRIVERLIB_NOROM at project level
+// - Per function: Use prefix "NOROM_" when calling the function
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #define SysCtrlIdle NOROM_SysCtrlIdle
+ #define SysCtrlShutdownWithAbort NOROM_SysCtrlShutdownWithAbort
+ #define SysCtrlShutdown NOROM_SysCtrlShutdown
+ #define SysCtrlStandby NOROM_SysCtrlStandby
+ #define SysCtrlSetRechargeBeforePowerDown NOROM_SysCtrlSetRechargeBeforePowerDown
+ #define SysCtrlAdjustRechargeAfterPowerDown NOROM_SysCtrlAdjustRechargeAfterPowerDown
+ #define SysCtrl_DCDC_VoltageConditionalControl NOROM_SysCtrl_DCDC_VoltageConditionalControl
+ #define SysCtrlResetSourceGet NOROM_SysCtrlResetSourceGet
+#endif
+
+//*****************************************************************************
+//
+// Defines for the settings of the main XOSC
+//
+//*****************************************************************************
+#define SYSCTRL_SYSBUS_ON 0x00000001
+#define SYSCTRL_SYSBUS_OFF 0x00000000
+
+//*****************************************************************************
+//
+// Defines for the different power modes of the System CPU
+//
+//*****************************************************************************
+#define CPU_RUN 0x00000000
+#define CPU_SLEEP 0x00000001
+#define CPU_DEEP_SLEEP 0x00000002
+
+//*****************************************************************************
+//
+// Defines for SysCtrlSetRechargeBeforePowerDown
+//
+//*****************************************************************************
+#define XOSC_IN_HIGH_POWER_MODE 0 // When xosc_hf is in HIGH_POWER_XOSC
+#define XOSC_IN_LOW_POWER_MODE 1 // When xosc_hf is in LOW_POWER_XOSC
+
+//*****************************************************************************
+//
+// Defines for the vimsPdMode parameter of SysCtrlIdle and SysCtrlStandby
+//
+//*****************************************************************************
+#define VIMS_ON_CPU_ON_MODE 0 // VIMS power domain is only powered when CPU power domain is powered
+#define VIMS_ON_BUS_ON_MODE 1 // VIMS power domain is powered whenever the BUS power domain is powered
+#define VIMS_NO_PWR_UP_MODE 2 // VIMS power domain is not powered up at next wakeup.
+
+//*****************************************************************************
+//
+// Defines for the rechargeMode parameter of SysCtrlStandby
+//
+//*****************************************************************************
+#define SYSCTRL_PREFERRED_RECHARGE_MODE \
+ 0xFFFFFFFF // Preferred recharge mode
+
+//*****************************************************************************
+//
+// API Functions and prototypes
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \brief Force the system into idle mode.
+//!
+//! This function forces the system into IDLE mode by configuring the requested
+//! VIMS mode, enabling cache retention and powering off the CPU power domain.
+//!
+//! \param vimsPdMode selects the requested VIMS power domain mode
+//! The parameter must be one of the following:
+//! - \ref VIMS_ON_CPU_ON_MODE
+//! - \ref VIMS_ON_BUS_ON_MODE
+//! - \ref VIMS_NO_PWR_UP_MODE
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void SysCtrlIdle(uint32_t vimsPdMode);
+
+//*****************************************************************************
+//
+//! \brief Try to enter shutdown but abort if wakeup event happened before shutdown.
+//!
+//! This function puts the device in shutdown state if no wakeup events are
+//! detected before shutdown.
+//!
+//! Compared to the basic \ref SysCtrlShutdown() function this function makes sure
+//! that wakeup events that happen before actual shutdown are also detected. This
+//! function either enters shutdown with a guaranteed wakeup detection or returns
+//! to the caller function due to a pre-shutdown wakeup event.
+//!
+//! See \ref SysCtrlShutdown() for basic information about how to configure the device before
+//! shutdown and how to wakeup from shutdown.
+//!
+//! This function uses IO edge detection in addition to the mandatory wakeup configuration.
+//! Additional requirements to the application for this function are:
+//! - \b Before :
+//! - When the application configures an IO for wakeup (see \ref IOCIOShutdownSet())
+//! the application must also configure the same IO for edge detection
+//! (see \ref IOCIOIntSet()).
+//! - Edge detection must use the same polarity as the wakeup configuration.
+//! - Application must enable peripheral power domain (see \ref PRCMPowerDomainOn())
+//! and enable GPIO module in the peripheral power domain (see \ref PRCMPeripheralRunEnable()).
+//! - \b After :
+//! - An edge, with same polarity as a wakeup event, was detected on a wakeup
+//! enabled IO before shutdown, and the shutdown was aborted. The application must
+//! clear the event generated by the edge detect (see \ref GPIO_clearEventDio()) and
+//! decide what happens next.
+//!
+//! Useful functions related to shutdown:
+//! - \ref IOCIOShutdownSet() : Enables wakeup from shutdown.
+//! - \ref IOCIOIntSet() : Enables IO edge detection.
+//! - \ref PRCMPowerDomainOn() : Enables peripheral power domain.
+//! - \ref PRCMPeripheralRunEnable() : Enables GPIO module.
+//! - \ref SysCtrlResetSourceGet() : Detects wakeup from shutdown.
+//! - \ref PowerCtrlPadSleepDisable() : Unlatches outputs (disables pad sleep) after
+//! wakeup from shutdown.
+//! - \ref GPIO_clearEventDio() : Clears edge detects.
+//!
+//! It is recommended to disable interrupts before calling this function because:
+//! - Pads are in sleep mode while this function runs.
+//! - An interrupt routine might be terminated if it is triggered after the decision
+//! to enter shutdown.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void SysCtrlShutdownWithAbort(void);
+
+//*****************************************************************************
+//
+//! \brief Enable shutdown of the device.
+//!
+//! This function puts the device in shutdown state. The device automatically
+//! latches all outputs (pads in sleep) before it turns off all internal power
+//! supplies.
+//!
+//! JTAG must be disconnected and JTAG power domain must be off before device can
+//! enter shutdown. This function waits until the device satisfies all shutdown
+//! conditions before it enters shutdown.
+//!
+//! \note The application must unlatch the outputs when the device wakes up from shutdown.
+//! It is recommended that any outputs that need to be restored after a wakeup from
+//! shutdown are restored before outputs are unlatched in order to avoid glitches.
+//!
+//! See \ref PowerCtrlPadSleepDisable() for information about how to unlatch outputs
+//! (disable pad sleep) after wakeup from shutdown.
+//!
+//! \note Wakeup events are only detected after the device enters shutdown.
+//!
+//! See \ref IOCIOShutdownSet() for information about how to enable wakeup from shutdown.
+//!
+//! See \ref SysCtrlResetSourceGet() for information about how to detect wakeup
+//! from shutdown.
+//!
+//! It is recommended to disable interrupts before calling this function. Shutdown
+//! happens immediately when the device satisfies all shutdown conditions thus
+//! interrupt routines triggered after this function is called might be
+//! aborted.
+//!
+//! \return This function does \b not return.
+//
+//*****************************************************************************
+extern void SysCtrlShutdown(void);
+
+//*****************************************************************************
+//
+//! \brief Force the system into standby mode.
+//!
+//! This function forces all power domains (RFCORE, SERIAL, PERIPHERAL) off.
+//! The VIMS and CPU power domains are turned off by the HW when the
+//! \ref PRCMDeepSleep() function is called.
+//! The IOs are latched (frozen) before the power domains are turned off to
+//! avoid glitches.
+//! The VIMS retention (cache) and VIMS module are turned off if requested.
+//! The deep-sleep clock for the crypto and DMA modules are turned off,
+//! as they must be off in order to enter standby.
+//! This function assumes that the LF clock has already been switched to
+//! and that the LF clock qualifiers must have been disabled/bypassed.
+//!
+//! In internal regulator mode the adaptive recharge functionality is enabled
+//! with fixed parameter values.
+//! In external regulator mode the recharge functionality is disabled.
+//!
+//! \note This function is optimized to execute with TI-RTOS. There might be
+//! application specific prerequisites you would want to do before entering
+//! standby which deviate from this specific implementation.
+//!
+//! \param retainCache selects if VIMS cache shall be retained or not.
+//! - false : VIMS cache is not retained
+//! - true : VIMS cache is retained
+//! \param vimsPdMode selects the VIMS power domain mode.
+//! The parameter must be one of the following:
+//! - \ref VIMS_ON_CPU_ON_MODE
+//! - \ref VIMS_NO_PWR_UP_MODE
+//! \param rechargeMode specifies the requested recharge mode.
+//! The parameter must be one of the following:
+//! - \ref SYSCTRL_PREFERRED_RECHARGE_MODE : Preferred recharge mode specified by TI
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void SysCtrlStandby(bool retainCache, uint32_t vimsPdMode, uint32_t rechargeMode);
+
+//*****************************************************************************
+//
+//! \brief Get the CPU core clock frequency.
+//!
+//! Use this function to get the current clock frequency for the CPU.
+//!
+//! The CPU can run from 48 MHz and down to 750kHz. The frequency is defined
+//! by the combined division factor of the SYSBUS and the CPU clock divider.
+//!
+//! \return Returns the current CPU core clock frequency.
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+SysCtrlClockGet( void )
+{
+ // Return fixed clock speed
+ return( GET_MCU_CLOCK );
+}
+
+//*****************************************************************************
+//
+//! \brief Sync all accesses to the AON register interface.
+//!
+//! When this function returns, all writes to the AON register interface are
+//! guaranteed to have propagated to hardware. The function will return
+//! immediately if no AON writes are pending; otherwise, it will wait for the next
+//! AON clock before returning.
+//!
+//! \return None
+//!
+//! \sa \ref SysCtrlAonUpdate()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+SysCtrlAonSync(void)
+{
+ // Sync the AON interface
+ HWREG(AON_RTC_BASE + AON_RTC_O_SYNC);
+}
+
+//*****************************************************************************
+//
+//! \brief Update all interfaces to AON.
+//!
+//! When this function returns, at least 1 clock cycle has progressed on the
+//! AON domain, so that any outstanding updates to and from the AON interface
+//! is guaranteed to be in sync.
+//!
+//! \note This function should primarily be used after wakeup from sleep modes,
+//! as it will guarantee that all shadow registers on the AON interface are updated
+//! before reading any AON registers from the MCU domain. If a write has been
+//! done to the AON interface it is sufficient to call the \ref SysCtrlAonSync().
+//!
+//! \return None
+//!
+//! \sa \ref SysCtrlAonSync()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+SysCtrlAonUpdate(void)
+{
+ // Force a clock cycle on the AON interface to guarantee all registers are
+ // in sync.
+ HWREG(AON_RTC_BASE + AON_RTC_O_SYNC) = 1;
+ HWREG(AON_RTC_BASE + AON_RTC_O_SYNC);
+}
+
+//*****************************************************************************
+//
+//! \brief Set Recharge values before entering Power Down.
+//!
+//! This function shall be called just before entering Power Down.
+//! This function typically does nothing (default setting), but
+//! if temperature compensated recharge level are enabled (by setting
+//! CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC = 0)
+//! it adds temperature compensation to the recharge level.
+//!
+//! \param xoscPowerMode (typically running in XOSC_IN_HIGH_POWER_MODE all the time).
+//! - \ref XOSC_IN_HIGH_POWER_MODE : When xosc_hf is in HIGH_POWER_XOSC.
+//! - \ref XOSC_IN_LOW_POWER_MODE : When xosc_hf is in LOW_POWER_XOSC.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void SysCtrlSetRechargeBeforePowerDown( uint32_t xoscPowerMode );
+
+//*****************************************************************************
+//
+//! \brief Adjust Recharge calculations to be used next.
+//!
+//! Nothing to be done but keeping this function for platform compatibility.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void SysCtrlAdjustRechargeAfterPowerDown( uint32_t vddrRechargeMargin );
+
+//*****************************************************************************
+//
+//! \brief Turns DCDC on or off depending of what is considered to be optimal usage.
+//!
+//! This function controls the DCDC only if both the following CCFG settings are \c true:
+//! - DCDC is configured to be used.
+//! - Alternative DCDC settings are defined and enabled.
+//!
+//! The DCDC is configured in accordance to the CCFG settings when turned on.
+//!
+//! This function should be called periodically.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void SysCtrl_DCDC_VoltageConditionalControl( void );
+
+//*****************************************************************************
+// \name Return values from calling SysCtrlResetSourceGet()
+//@{
+//*****************************************************************************
+#define RSTSRC_PWR_ON (( AON_PMCTL_RESETCTL_RESET_SRC_PWR_ON ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S ))
+#define RSTSRC_PIN_RESET (( AON_PMCTL_RESETCTL_RESET_SRC_PIN_RESET ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S ))
+#define RSTSRC_VDDS_LOSS (( AON_PMCTL_RESETCTL_RESET_SRC_VDDS_LOSS ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S ))
+#define RSTSRC_VDDR_LOSS (( AON_PMCTL_RESETCTL_RESET_SRC_VDDR_LOSS ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S ))
+#define RSTSRC_CLK_LOSS (( AON_PMCTL_RESETCTL_RESET_SRC_CLK_LOSS ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S ))
+#define RSTSRC_SYSRESET (( AON_PMCTL_RESETCTL_RESET_SRC_SYSRESET ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S ))
+#define RSTSRC_WARMRESET (( AON_PMCTL_RESETCTL_RESET_SRC_WARMRESET ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S ))
+#define RSTSRC_WAKEUP_FROM_SHUTDOWN ((( AON_PMCTL_RESETCTL_RESET_SRC_M ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) + 1 )
+#define RSTSRC_WAKEUP_FROM_TCK_NOISE ((( AON_PMCTL_RESETCTL_RESET_SRC_M ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) + 2 )
+//@}
+
+//*****************************************************************************
+//
+//! \brief Returns the reset source (including "wakeup from shutdown").
+//!
+//! In case of \ref RSTSRC_WAKEUP_FROM_SHUTDOWN the application is
+//! responsible for unlatching the outputs (disable pad sleep).
+//! See \ref PowerCtrlPadSleepDisable() for more information.
+//!
+//! \return Returns the reset source.
+//! - \ref RSTSRC_PWR_ON
+//! - \ref RSTSRC_PIN_RESET
+//! - \ref RSTSRC_VDDS_LOSS
+//! - \ref RSTSRC_VDDR_LOSS
+//! - \ref RSTSRC_CLK_LOSS
+//! - \ref RSTSRC_SYSRESET
+//! - \ref RSTSRC_WARMRESET
+//! - \ref RSTSRC_WAKEUP_FROM_SHUTDOWN
+//! - \ref RSTSRC_WAKEUP_FROM_TCK_NOISE
+//
+//*****************************************************************************
+extern uint32_t SysCtrlResetSourceGet( void );
+
+//*****************************************************************************
+//
+//! \brief Perform a full system reset.
+//!
+//! \return The chip will reset and hence never return from this call.
+//
+//*****************************************************************************
+__STATIC_INLINE void
+SysCtrlSystemReset( void )
+{
+ // Disable CPU interrupts
+ CPUcpsid();
+ // Write reset register
+ HWREGBITW( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL, AON_PMCTL_RESETCTL_SYSRESET_BITN ) = 1;
+ // Finally, wait until the above write propagates
+ while ( 1 ) {
+ // Do nothing, just wait for the reset (and never return from here)
+ }
+}
+
+//*****************************************************************************
+//
+//! \brief Enables reset if OSC clock loss event is asserted.
+//!
+//! Clock loss circuit in analog domain must be enabled as well in order to
+//! actually enable for a clock loss reset to occur
+//! \ref OSCClockLossEventEnable().
+//!
+//! \note This function shall typically not be called because the clock loss
+//! reset functionality is controlled by the boot code (a factory configuration
+//! defines whether it is set or not).
+//!
+//! \return None
+//!
+//! \sa \ref SysCtrlClockLossResetDisable(), \ref OSCClockLossEventEnable()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+SysCtrlClockLossResetEnable(void)
+{
+ // Set clock loss enable bit in AON_SYSCTRL using bit banding
+ HWREGBITW(AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL, AON_PMCTL_RESETCTL_CLK_LOSS_EN_BITN) = 1;
+}
+
+//*****************************************************************************
+//
+//! \brief Disables reset due to OSC clock loss event.
+//!
+//! \note This function shall typically not be called because the clock loss
+//! reset functionality is controlled by the boot code (a factory configuration
+//! defines whether it is set or not).
+//!
+//! \return None
+//!
+//! \sa \ref SysCtrlClockLossResetEnable()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+SysCtrlClockLossResetDisable(void)
+{
+ // Clear clock loss enable bit in AON_SYSCTRL using bit banding
+ HWREGBITW(AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL, AON_PMCTL_RESETCTL_CLK_LOSS_EN_BITN) = 0;
+}
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// Redirect to implementation in ROM when available.
+//
+//*****************************************************************************
+#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
+ #include "../driverlib/rom.h"
+ #ifdef ROM_SysCtrlIdle
+ #undef SysCtrlIdle
+ #define SysCtrlIdle ROM_SysCtrlIdle
+ #endif
+ #ifdef ROM_SysCtrlShutdownWithAbort
+ #undef SysCtrlShutdownWithAbort
+ #define SysCtrlShutdownWithAbort ROM_SysCtrlShutdownWithAbort
+ #endif
+ #ifdef ROM_SysCtrlShutdown
+ #undef SysCtrlShutdown
+ #define SysCtrlShutdown ROM_SysCtrlShutdown
+ #endif
+ #ifdef ROM_SysCtrlStandby
+ #undef SysCtrlStandby
+ #define SysCtrlStandby ROM_SysCtrlStandby
+ #endif
+ #ifdef ROM_SysCtrlSetRechargeBeforePowerDown
+ #undef SysCtrlSetRechargeBeforePowerDown
+ #define SysCtrlSetRechargeBeforePowerDown ROM_SysCtrlSetRechargeBeforePowerDown
+ #endif
+ #ifdef ROM_SysCtrlAdjustRechargeAfterPowerDown
+ #undef SysCtrlAdjustRechargeAfterPowerDown
+ #define SysCtrlAdjustRechargeAfterPowerDown ROM_SysCtrlAdjustRechargeAfterPowerDown
+ #endif
+ #ifdef ROM_SysCtrl_DCDC_VoltageConditionalControl
+ #undef SysCtrl_DCDC_VoltageConditionalControl
+ #define SysCtrl_DCDC_VoltageConditionalControl ROM_SysCtrl_DCDC_VoltageConditionalControl
+ #endif
+ #ifdef ROM_SysCtrlResetSourceGet
+ #undef SysCtrlResetSourceGet
+ #define SysCtrlResetSourceGet ROM_SysCtrlResetSourceGet
+ #endif
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __SYSCTRL_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/systick.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/systick.c
new file mode 100644
index 0000000..6a64e2d
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/systick.c
@@ -0,0 +1,41 @@
+/******************************************************************************
+* Filename: systick.c
+* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016)
+* Revision: 47179
+*
+* Description: Driver for the SysTick timer in NVIC
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "systick.h"
+
+// See systick.h for implementation
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/systick.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/systick.h
new file mode 100644
index 0000000..a70702c
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/systick.h
@@ -0,0 +1,287 @@
+/******************************************************************************
+* Filename: systick.h
+* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017)
+* Revision: 49048
+*
+* Description: Prototypes for the SysTick driver.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup system_cpu_group
+//! @{
+//! \addtogroup systick_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __SYSTICK_H__
+#define __SYSTICK_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "../inc/hw_ints.h"
+#include "../inc/hw_nvic.h"
+#include "../inc/hw_types.h"
+#include "debug.h"
+#include "interrupt.h"
+
+//*****************************************************************************
+//
+// API Functions and Prototypes
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \brief Enables the SysTick counter.
+//!
+//! This will start the SysTick counter. If an interrupt handler has been
+//! registered, it will be called when the SysTick counter rolls over.
+//!
+//! \note Calling this function will cause the SysTick counter to (re)commence
+//! counting from its current value. The counter is not automatically reloaded
+//! with the period as specified in a previous call to \ref SysTickPeriodSet(). If
+//! an immediate reload is required, the NVIC_ST_CURRENT register must be
+//! written to force this. Any write to this register clears the SysTick
+//! counter to 0 and will cause a reload with the supplied period on the next
+//! clock.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+SysTickEnable(void)
+{
+ // Enable SysTick.
+ HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE;
+}
+
+//*****************************************************************************
+//
+//! \brief Disables the SysTick counter.
+//!
+//! This will stop the SysTick counter. If an interrupt handler has been
+//! registered, it will no longer be called until SysTick is restarted.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+SysTickDisable(void)
+{
+ // Disable SysTick.
+ HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE);
+}
+
+//*****************************************************************************
+//
+//! \brief Registers an interrupt handler for the SysTick interrupt in the dynamic interrupt table.
+//!
+//! \note Only use this function if you want to use the dynamic vector table (in SRAM)!
+//!
+//! This function registers a function as the interrupt handler for a specific
+//! interrupt and enables the corresponding interrupt in the interrupt controller.
+//!
+//! \param pfnHandler is a pointer to the function to be called when the
+//! SysTick interrupt occurs.
+//!
+//! \return None
+//!
+//! \sa \ref IntRegister() for important information about registering interrupt
+//! handlers.
+//
+//*****************************************************************************
+__STATIC_INLINE void
+SysTickIntRegister(void (*pfnHandler)(void))
+{
+ // Register the interrupt handler, returning an error if an error occurs.
+ IntRegister(INT_SYSTICK, pfnHandler);
+
+ // Enable the SysTick interrupt.
+ HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
+}
+
+//*****************************************************************************
+//
+//! \brief Unregisters the interrupt handler for the SysTick interrupt in the dynamic interrupt table.
+//!
+//! This function will clear the handler to be called when a SysTick interrupt
+//! occurs.
+//!
+//! \return None
+//!
+//! \sa \ref IntRegister() for important information about registering interrupt
+//! handlers.
+//
+//*****************************************************************************
+__STATIC_INLINE void
+SysTickIntUnregister(void)
+{
+ // Disable the SysTick interrupt.
+ HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
+
+ // Unregister the interrupt handler.
+ IntUnregister(INT_SYSTICK);
+}
+
+//*****************************************************************************
+//
+//! \brief Enables the SysTick interrupt.
+//!
+//! This function will enable the SysTick interrupt, allowing it to be
+//! reflected to the processor.
+//!
+//! \note The SysTick interrupt handler does not need to clear the SysTick
+//! interrupt source as this is done automatically by NVIC when the interrupt
+//! handler is called.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+SysTickIntEnable(void)
+{
+ // Enable the SysTick interrupt.
+ HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
+}
+
+//*****************************************************************************
+//
+//! \brief Disables the SysTick interrupt.
+//!
+//! This function will disable the SysTick interrupt, preventing it from being
+//! reflected to the processor.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+SysTickIntDisable(void)
+{
+ // Disable the SysTick interrupt.
+ HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
+}
+
+//*****************************************************************************
+//
+//! \brief Sets the period of the SysTick counter.
+//!
+//! This function sets the rate at which the SysTick counter wraps; this
+//! equals to the number of processor clocks between interrupts.
+//!
+//! \note Calling this function does not cause the SysTick counter to reload
+//! immediately. If an immediate reload is required, the NVIC_ST_CURRENT
+//! register must be written. Any write to this register clears the SysTick
+//! counter to 0 and will cause a reload with the \c ui32Period supplied here
+//! on the next clock after the SysTick is enabled.
+//!
+//! \param ui32Period is the number of clock ticks in each period of the
+//! SysTick counter; must be between 1 and 16,777,216 (0x1000000), both included.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+SysTickPeriodSet(uint32_t ui32Period)
+{
+ // Check the arguments.
+ ASSERT((ui32Period > 0) && (ui32Period <= 16777216));
+
+ // Set the period of the SysTick counter.
+ HWREG(NVIC_ST_RELOAD) = ui32Period - 1;
+}
+
+//*****************************************************************************
+//
+//! \brief Gets the period of the SysTick counter.
+//!
+//! This function returns the rate at which the SysTick counter wraps; this
+//! equals to the number of processor clocks between interrupts.
+//!
+//! \return Returns the period of the SysTick counter.
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+SysTickPeriodGet(void)
+{
+ // Return the period of the SysTick counter.
+ return(HWREG(NVIC_ST_RELOAD) + 1);
+}
+
+//*****************************************************************************
+//
+//! \brief Gets the current value of the SysTick counter.
+//!
+//! This function returns the current value of the SysTick counter; this will
+//! be a value between the (period - 1) and zero, both included.
+//!
+//! \return Returns the current value of the SysTick counter
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+SysTickValueGet(void)
+{
+ // Return the current value of the SysTick counter.
+ return(HWREG(NVIC_ST_CURRENT));
+}
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __SYSTICK_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/systick_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/systick_doc.h
new file mode 100644
index 0000000..47a37de
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/systick_doc.h
@@ -0,0 +1,68 @@
+/******************************************************************************
+* Filename: systick_doc.h
+* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016)
+* Revision: 45971
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+//! \addtogroup systick_api
+//! @{
+//! \section sec_systick Introduction
+//!
+//! The system CPU includes a system timer, SysTick, integrated in the NVIC which provides a simple, 24-bit,
+//! clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism.
+//! When enabled, the timer counts down on each clock from the reload value to 0, reloads (wraps) on
+//! the next clock edge, then decrements on subsequent clocks.
+//!
+//! The SysTick counter runs on the system clock. If this clock signal is stopped for low-power mode, the
+//! SysTick counter stops.
+//!
+//! When the processor is halted for debugging, the counter does not decrement.
+//!
+//! \section sec_systick_api API
+//!
+//! The API functions can be grouped like this:
+//!
+//! Configuration and status:
+//! - \ref SysTickPeriodSet()
+//! - \ref SysTickPeriodGet()
+//! - \ref SysTickValueGet()
+//!
+//! Enable and disable:
+//! - \ref SysTickEnable()
+//! - \ref SysTickDisable()
+//!
+//! Interrupt configuration:
+//! - \ref SysTickIntRegister()
+//! - \ref SysTickIntUnregister()
+//! - \ref SysTickIntEnable()
+//! - \ref SysTickIntDisable()
+//! @}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/timer.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/timer.c
new file mode 100644
index 0000000..5acc1a6
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/timer.c
@@ -0,0 +1,392 @@
+/******************************************************************************
+* Filename: timer.c
+* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017)
+* Revision: 48852
+*
+* Description: Driver for the General Purpose Timer
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "timer.h"
+
+//*****************************************************************************
+//
+// Handle support for DriverLib in ROM:
+// This section will undo prototype renaming made in the header file
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #undef TimerConfigure
+ #define TimerConfigure NOROM_TimerConfigure
+ #undef TimerLevelControl
+ #define TimerLevelControl NOROM_TimerLevelControl
+ #undef TimerStallControl
+ #define TimerStallControl NOROM_TimerStallControl
+ #undef TimerWaitOnTriggerControl
+ #define TimerWaitOnTriggerControl NOROM_TimerWaitOnTriggerControl
+ #undef TimerIntRegister
+ #define TimerIntRegister NOROM_TimerIntRegister
+ #undef TimerIntUnregister
+ #define TimerIntUnregister NOROM_TimerIntUnregister
+ #undef TimerMatchUpdateMode
+ #define TimerMatchUpdateMode NOROM_TimerMatchUpdateMode
+ #undef TimerIntervalLoadMode
+ #define TimerIntervalLoadMode NOROM_TimerIntervalLoadMode
+#endif
+
+//*****************************************************************************
+//
+//! \brief Gets the timer interrupt number.
+//!
+//! Given a timer base address, this function returns the corresponding
+//! interrupt number.
+//!
+//! \param ui32Base is the base address of the timer module.
+//!
+//! \return Returns a timer interrupt number, or -1 if \c ui32Base is invalid.
+//
+//*****************************************************************************
+static uint32_t
+TimerIntNumberGet(uint32_t ui32Base)
+{
+ uint32_t ui32Int;
+
+ // Loop through the table that maps timer base addresses to interrupt
+ // numbers.
+ switch(ui32Base)
+ {
+ case GPT0_BASE :
+ ui32Int = INT_GPT0A;
+ break;
+ case GPT1_BASE :
+ ui32Int = INT_GPT1A;
+ break;
+ case GPT2_BASE :
+ ui32Int = INT_GPT2A;
+ break;
+ case GPT3_BASE :
+ ui32Int = INT_GPT3A;
+ break;
+ default :
+ ui32Int = 0x0;
+ }
+
+ // Return the interrupt number or (-1) if not base address is not matched.
+ return (ui32Int);
+}
+
+//*****************************************************************************
+//
+// Configures the timer(s)
+//
+//*****************************************************************************
+void
+TimerConfigure(uint32_t ui32Base, uint32_t ui32Config)
+{
+ // Check the arguments.
+ ASSERT(TimerBaseValid(ui32Base));
+ ASSERT((ui32Config == TIMER_CFG_ONE_SHOT) ||
+ (ui32Config == TIMER_CFG_ONE_SHOT_UP) ||
+ (ui32Config == TIMER_CFG_PERIODIC) ||
+ (ui32Config == TIMER_CFG_PERIODIC_UP) ||
+ ((ui32Config & 0xFF000000) == TIMER_CFG_SPLIT_PAIR));
+ ASSERT(((ui32Config & 0xFF000000) != TIMER_CFG_SPLIT_PAIR) ||
+ ((((ui32Config & 0x000000FF) == TIMER_CFG_A_ONE_SHOT) ||
+ ((ui32Config & 0x000000FF) == TIMER_CFG_A_ONE_SHOT_UP) ||
+ ((ui32Config & 0x000000FF) == TIMER_CFG_A_PERIODIC) ||
+ ((ui32Config & 0x000000FF) == TIMER_CFG_A_PERIODIC_UP) ||
+ ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_COUNT) ||
+ ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_COUNT_UP) ||
+ ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_TIME) ||
+ ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_TIME_UP) ||
+ ((ui32Config & 0x000000FF) == TIMER_CFG_A_PWM)) &&
+ (((ui32Config & 0x0000FF00) == TIMER_CFG_B_ONE_SHOT) ||
+ ((ui32Config & 0x0000FF00) == TIMER_CFG_B_ONE_SHOT_UP) ||
+ ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PERIODIC) ||
+ ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PERIODIC_UP) ||
+ ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_COUNT) ||
+ ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_COUNT_UP) ||
+ ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_TIME) ||
+ ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_TIME_UP) ||
+ ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PWM))));
+
+ // Disable the timers.
+ HWREG(ui32Base + GPT_O_CTL) &= ~(GPT_CTL_TAEN | GPT_CTL_TBEN);
+
+ // Set the global timer configuration.
+ HWREG(ui32Base + GPT_O_CFG) = ui32Config >> 24;
+
+ // Set the configuration of the A and B timers. Note that the B timer
+ // configuration is ignored by the hardware in 32-bit modes.
+ HWREG(ui32Base + GPT_O_TAMR) = (ui32Config & 0xFF) | GPT_TAMR_TAPWMIE;
+ HWREG(ui32Base + GPT_O_TBMR) =
+ ((ui32Config >> 8) & 0xFF) | GPT_TBMR_TBPWMIE;
+}
+
+//*****************************************************************************
+//
+// Controls the output level
+//
+//*****************************************************************************
+void
+TimerLevelControl(uint32_t ui32Base, uint32_t ui32Timer, bool bInvert)
+{
+ // Check the arguments.
+ ASSERT(TimerBaseValid(ui32Base));
+ ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+ (ui32Timer == TIMER_BOTH));
+
+ // Set the output levels as requested.
+ ui32Timer &= GPT_CTL_TAPWML | GPT_CTL_TBPWML;
+ HWREG(ui32Base + GPT_O_CTL) = (bInvert ?
+ (HWREG(ui32Base + GPT_O_CTL) | ui32Timer) :
+ (HWREG(ui32Base + GPT_O_CTL) &
+ ~(ui32Timer)));
+}
+
+//*****************************************************************************
+//
+// Controls the stall handling
+//
+//*****************************************************************************
+void
+TimerStallControl(uint32_t ui32Base, uint32_t ui32Timer, bool bStall)
+{
+ // Check the arguments.
+ ASSERT(TimerBaseValid(ui32Base));
+ ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+ (ui32Timer == TIMER_BOTH));
+
+ // Set the stall mode.
+ ui32Timer &= GPT_CTL_TASTALL | GPT_CTL_TBSTALL;
+ HWREG(ui32Base + GPT_O_CTL) = (bStall ?
+ (HWREG(ui32Base + GPT_O_CTL) | ui32Timer) :
+ (HWREG(ui32Base + GPT_O_CTL) & ~(ui32Timer)));
+}
+
+//*****************************************************************************
+//
+// Controls the wait on trigger handling
+//
+//*****************************************************************************
+void
+TimerWaitOnTriggerControl(uint32_t ui32Base, uint32_t ui32Timer, bool bWait)
+{
+ // Check the arguments.
+ ASSERT(TimerBaseValid(ui32Base));
+ ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+ (ui32Timer == TIMER_BOTH));
+
+ // Set the wait on trigger mode for timer A.
+ if(ui32Timer & TIMER_A)
+ {
+ if(bWait)
+ {
+ HWREG(ui32Base + GPT_O_TAMR) |= GPT_TAMR_TAWOT;
+ }
+ else
+ {
+ HWREG(ui32Base + GPT_O_TAMR) &= ~(GPT_TAMR_TAWOT);
+ }
+ }
+
+ // Set the wait on trigger mode for timer B.
+ if(ui32Timer & TIMER_B)
+ {
+ if(bWait)
+ {
+ HWREG(ui32Base + GPT_O_TBMR) |= GPT_TBMR_TBWOT;
+ }
+ else
+ {
+ HWREG(ui32Base + GPT_O_TBMR) &= ~(GPT_TBMR_TBWOT);
+ }
+ }
+}
+
+//*****************************************************************************
+//
+// Registers an interrupt handler for the timer interrupt
+//
+//*****************************************************************************
+void
+TimerIntRegister(uint32_t ui32Base, uint32_t ui32Timer, void (*pfnHandler)(void))
+{
+ uint32_t ui32Int;
+
+ // Check the arguments.
+ ASSERT(TimerBaseValid(ui32Base));
+ ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+ (ui32Timer == TIMER_BOTH));
+
+ // Get the interrupt number for this timer module.
+ ui32Int = TimerIntNumberGet(ui32Base);
+
+ // Register an interrupt handler for timer A if requested.
+ if(ui32Timer & TIMER_A)
+ {
+ // Register the interrupt handler.
+ IntRegister(ui32Int, pfnHandler);
+
+ // Enable the interrupt.
+ IntEnable(ui32Int);
+ }
+
+ // Register an interrupt handler for timer B if requested.
+ if(ui32Timer & TIMER_B)
+ {
+ // Register the interrupt handler.
+ IntRegister(ui32Int + 1, pfnHandler);
+
+ // Enable the interrupt.
+ IntEnable(ui32Int + 1);
+ }
+}
+
+//*****************************************************************************
+//
+// Unregisters an interrupt handler for the timer interrupt
+//
+//*****************************************************************************
+void
+TimerIntUnregister(uint32_t ui32Base, uint32_t ui32Timer)
+{
+ uint32_t ui32Int;
+
+ // Check the arguments.
+ ASSERT(TimerBaseValid(ui32Base));
+ ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+ (ui32Timer == TIMER_BOTH));
+
+ // Get the interrupt number for this timer module.
+ ui32Int = TimerIntNumberGet(ui32Base);
+
+ // Unregister the interrupt handler for timer A if requested.
+ if(ui32Timer & TIMER_A)
+ {
+ // Disable the interrupt.
+ IntDisable(ui32Int);
+
+ // Unregister the interrupt handler.
+ IntUnregister(ui32Int);
+ }
+
+ // Unregister the interrupt handler for timer B if requested.
+ if(ui32Timer & TIMER_B)
+ {
+ // Disable the interrupt.
+ IntDisable(ui32Int + 1);
+
+ // Unregister the interrupt handler.
+ IntUnregister(ui32Int + 1);
+ }
+}
+
+//*****************************************************************************
+//
+// Sets the Match Register Update mode
+//
+//*****************************************************************************
+void
+TimerMatchUpdateMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode)
+{
+ // Check the arguments
+ ASSERT(TimerBaseValid(ui32Base));
+ ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || (ui32Timer == TIMER_BOTH));
+ ASSERT((ui32Mode == TIMER_MATCHUPDATE_NEXTCYCLE) || (ui32Mode == TIMER_MATCHUPDATE_TIMEOUT));
+
+ // Set mode for timer A
+ if(ui32Timer & TIMER_A)
+ {
+ if(ui32Mode == TIMER_MATCHUPDATE_NEXTCYCLE)
+ {
+ HWREG(ui32Base + GPT_O_TAMR) &= ~(GPT_TAMR_TAMRSU);
+ }
+ else
+ {
+ HWREG(ui32Base + GPT_O_TAMR) |= GPT_TAMR_TAMRSU;
+ }
+ }
+
+ // Set mode for timer B
+ if(ui32Timer & TIMER_B)
+ {
+ if(ui32Mode == TIMER_MATCHUPDATE_NEXTCYCLE)
+ {
+ HWREG(ui32Base + GPT_O_TBMR) &= ~(GPT_TBMR_TBMRSU);
+ }
+ else
+ {
+ HWREG(ui32Base + GPT_O_TBMR) |= GPT_TBMR_TBMRSU;
+ }
+ }
+}
+
+//*****************************************************************************
+//
+// Sets the Interval Load mode
+//
+//*****************************************************************************
+void
+TimerIntervalLoadMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode)
+{
+ // Check the arguments
+ ASSERT(TimerBaseValid(ui32Base));
+ ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || (ui32Timer == TIMER_BOTH));
+ ASSERT((ui32Mode == TIMER_INTERVALLOAD_NEXTCYCLE) || (ui32Mode == TIMER_INTERVALLOAD_TIMEOUT));
+
+ // Set mode for timer A
+ if(ui32Timer & TIMER_A)
+ {
+ if(ui32Mode == TIMER_INTERVALLOAD_NEXTCYCLE)
+ {
+ HWREG(ui32Base + GPT_O_TAMR) &= ~(GPT_TAMR_TAILD);
+ }
+ else
+ {
+ HWREG(ui32Base + GPT_O_TAMR) |= GPT_TAMR_TAILD;
+ }
+ }
+
+ // Set mode for timer B
+ if(ui32Timer & TIMER_B)
+ {
+ if(ui32Mode == TIMER_INTERVALLOAD_NEXTCYCLE)
+ {
+ HWREG(ui32Base + GPT_O_TBMR) &= ~(GPT_TBMR_TBILD);
+ }
+ else
+ {
+ HWREG(ui32Base + GPT_O_TBMR) |= GPT_TBMR_TBILD;
+ }
+ }
+}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/timer.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/timer.h
new file mode 100644
index 0000000..d34e6ce
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/timer.h
@@ -0,0 +1,1176 @@
+/******************************************************************************
+* Filename: timer.h
+* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017)
+* Revision: 49048
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//****************************************************************************
+//
+//! \addtogroup peripheral_group
+//! @{
+//! \addtogroup timer_api
+//! @{
+//
+//****************************************************************************
+
+#ifndef __GPT_H__
+#define __GPT_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "../inc/hw_ints.h"
+#include "../inc/hw_types.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_gpt.h"
+#include "interrupt.h"
+#include "debug.h"
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// This section renames all functions that are not "static inline", so that
+// calling these functions will default to implementation in flash. At the end
+// of this file a second renaming will change the defaults to implementation in
+// ROM for available functions.
+//
+// To force use of the implementation in flash, e.g. for debugging:
+// - Globally: Define DRIVERLIB_NOROM at project level
+// - Per function: Use prefix "NOROM_" when calling the function
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #define TimerConfigure NOROM_TimerConfigure
+ #define TimerLevelControl NOROM_TimerLevelControl
+ #define TimerStallControl NOROM_TimerStallControl
+ #define TimerWaitOnTriggerControl NOROM_TimerWaitOnTriggerControl
+ #define TimerIntRegister NOROM_TimerIntRegister
+ #define TimerIntUnregister NOROM_TimerIntUnregister
+ #define TimerMatchUpdateMode NOROM_TimerMatchUpdateMode
+ #define TimerIntervalLoadMode NOROM_TimerIntervalLoadMode
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to TimerConfigure as the ui32Config parameter.
+//
+//*****************************************************************************
+#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer
+#define TIMER_CFG_ONE_SHOT_UP 0x00000031 // Full-width one-shot up-count timer
+#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer
+#define TIMER_CFG_PERIODIC_UP 0x00000032 // Full-width periodic up-count timer
+#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers
+#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer
+#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer
+#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer
+#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer
+#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter
+#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter
+#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer
+#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer
+#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output
+#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer
+#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer
+#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer
+#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer
+#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter
+#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter
+#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer
+#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer
+#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output
+
+//*****************************************************************************
+//
+// Values that can be passed to TimerIntEnable, TimerIntDisable, and
+// TimerIntClear as the ui32IntFlags parameter, and returned from
+// TimerIntStatus.
+//
+//*****************************************************************************
+#define TIMER_TIMB_DMA 0x00002000 // TimerB DMA Done interrupt
+#define TIMER_TIMB_MATCH 0x00000800 // TimerB match interrupt
+#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt
+#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt
+#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt
+#define TIMER_TIMA_DMA 0x00000020 // TimerA DMA Done interrupt
+#define TIMER_TIMA_MATCH 0x00000010 // TimerA match interrupt
+#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt
+#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt
+#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt
+
+//*****************************************************************************
+//
+// Values that can be passed to TimerControlEvent as the ui32Event parameter.
+//
+//*****************************************************************************
+#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges
+#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges
+#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges
+
+//*****************************************************************************
+//
+// Values that can be passed to most of the timer APIs as the ui32Timer
+// parameter.
+//
+//*****************************************************************************
+#define TIMER_A 0x000000FF // Timer A
+#define TIMER_B 0x0000FF00 // Timer B
+#define TIMER_BOTH 0x0000FFFF // Timer Both
+
+//*****************************************************************************
+//
+// Values that can be passed to GPTSynchronize as the ui32Timers parameter
+//
+//*****************************************************************************
+#define TIMER_0A_SYNC 0x00000001 // Synchronize Timer 0A
+#define TIMER_0B_SYNC 0x00000002 // Synchronize Timer 0B
+#define TIMER_1A_SYNC 0x00000004 // Synchronize Timer 1A
+#define TIMER_1B_SYNC 0x00000008 // Synchronize Timer 1B
+#define TIMER_2A_SYNC 0x00000010 // Synchronize Timer 2A
+#define TIMER_2B_SYNC 0x00000020 // Synchronize Timer 2B
+#define TIMER_3A_SYNC 0x00000040 // Synchronize Timer 3A
+#define TIMER_3B_SYNC 0x00000080 // Synchronize Timer 3B
+
+//*****************************************************************************
+//
+// Values that can be passed to TimerMatchUpdateMode
+//
+//*****************************************************************************
+#define TIMER_MATCHUPDATE_NEXTCYCLE 0x00000000 // Apply match register on next cycle
+#define TIMER_MATCHUPDATE_TIMEOUT 0x00000001 // Apply match register on next timeout
+
+//*****************************************************************************
+//
+// Values that can be passed to TimerIntervalLoad
+//
+//*****************************************************************************
+#define TIMER_INTERVALLOAD_NEXTCYCLE 0x00000000 // Load TxR register with the value in the TxILR register on the next clock cycle
+#define TIMER_INTERVALLOAD_TIMEOUT 0x00000001 // Load TxR register with the value in the TxILR register on next timeout
+
+//*****************************************************************************
+//
+// API Functions and prototypes
+//
+//*****************************************************************************
+
+#ifdef DRIVERLIB_DEBUG
+//*****************************************************************************
+//
+//! \internal
+//!
+//! \brief Checks a timer base address.
+//!
+//! This function determines if a timer module base address is valid.
+//!
+//! \param ui32Base is the base address of the timer module.
+//!
+//! \return Returns \c true if the base address is valid and \c false
+//! otherwise.
+//
+//*****************************************************************************
+static bool
+TimerBaseValid(uint32_t ui32Base)
+{
+ return((ui32Base == GPT0_BASE) || (ui32Base == GPT1_BASE) ||
+ (ui32Base == GPT2_BASE) || (ui32Base == GPT3_BASE));
+}
+#endif
+
+//*****************************************************************************
+//
+//! \brief Enables the timer(s).
+//!
+//! This function enables operation of the timer module. The timer must be
+//! configured before it is enabled.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s) to enable. Must be one of:
+//! - \ref TIMER_A
+//! - \ref TIMER_B
+//! - \ref TIMER_BOTH
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+TimerEnable(uint32_t ui32Base, uint32_t ui32Timer)
+{
+ // Check the arguments.
+ ASSERT(TimerBaseValid(ui32Base));
+ ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+ (ui32Timer == TIMER_BOTH));
+
+ // Enable the timer(s) module.
+ HWREG(ui32Base + GPT_O_CTL) |= ui32Timer & (GPT_CTL_TAEN | GPT_CTL_TBEN);
+}
+
+//*****************************************************************************
+//
+//! \brief Disables the timer(s).
+//!
+//! This function disables operation of the timer module.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s) to disable. Must be one of:
+//! - \ref TIMER_A
+//! - \ref TIMER_B
+//! - \ref TIMER_BOTH
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+TimerDisable(uint32_t ui32Base, uint32_t ui32Timer)
+{
+ // Check the arguments.
+ ASSERT(TimerBaseValid(ui32Base));
+ ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+ (ui32Timer == TIMER_BOTH));
+
+ // Disable the timer module.
+ HWREG(ui32Base + GPT_O_CTL) &= ~(ui32Timer &
+ (GPT_CTL_TAEN | GPT_CTL_TBEN));
+}
+
+//*****************************************************************************
+//
+//! \brief Configures the timer(s).
+//!
+//! This function configures the operating mode of the timer(s). The timer
+//! module is disabled before being configured and is left in the disabled
+//! state.
+//!
+//! The timers are comprised of two 16-bit timers that can
+//! operate independently or be concatenated to form a 32-bit timer.
+//!
+//! \note If the timers are used independently the length of timer can be
+//! extended to 24 bit by use of an 8 bit prescale register set using
+//! \ref TimerPrescaleSet().
+//!
+//! When configuring for full-width timer \c ui32Config is set
+//! as one of the following values:
+//! - \ref TIMER_CFG_ONE_SHOT : Full-width one-shot timer.
+//! - \ref TIMER_CFG_ONE_SHOT_UP : Full-width one-shot timer that counts up
+//! instead of down.
+//! - \ref TIMER_CFG_PERIODIC : Full-width periodic timer.
+//! - \ref TIMER_CFG_PERIODIC_UP : Full-width periodic timer that counts up
+//! instead of down.
+//!
+//! When configuring for a pair of half-width timers, each timer is separately
+//! configured. The timers are configured by setting \c ui32Config to
+//! the bitwise OR of one of each of the following three:
+//! - Use half-width timers:
+//! - \ref TIMER_CFG_SPLIT_PAIR
+//! - Timer A:
+//! - \ref TIMER_CFG_A_ONE_SHOT : Half-width one-shot timer
+//! - \ref TIMER_CFG_A_ONE_SHOT_UP : Half-width one-shot timer that counts up
+//! instead of down.
+//! - \ref TIMER_CFG_A_PERIODIC : Half-width periodic timer
+//! - \ref TIMER_CFG_A_PERIODIC_UP : Half-width periodic timer that counts up
+//! instead of down.
+//! - \ref TIMER_CFG_A_CAP_COUNT : Half-width edge count capture
+//! - \ref TIMER_CFG_A_CAP_COUNT_UP : Half-width edge count capture that counts
+//! up instead of down.
+//! - \ref TIMER_CFG_A_CAP_TIME : Half-width edge time capture
+//! - \ref TIMER_CFG_A_CAP_TIME_UP : Half-width edge time capture that counts up
+//! instead of down.
+//! - \ref TIMER_CFG_A_PWM : Half-width PWM output
+//! - Timer B:
+//! - Same as Timer A but using TIMER_CFG_B_* instead.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Config is the configuration for the timer.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void TimerConfigure(uint32_t ui32Base, uint32_t ui32Config);
+
+//*****************************************************************************
+//
+//! \brief Controls the output level.
+//!
+//! This function configures the PWM output level for the specified timer.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s) to adjust. Must be one of:
+//! - \ref TIMER_A
+//! - \ref TIMER_B
+//! - \ref TIMER_BOTH
+//! \param bInvert specifies the output level.
+//! - \c true : Timer's output is active low.
+//! - \c false : Timer's output is active high.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void TimerLevelControl(uint32_t ui32Base, uint32_t ui32Timer,
+ bool bInvert);
+
+//*****************************************************************************
+//
+//! \brief Controls the event type.
+//!
+//! This function configures the signal edge(s) that triggers the timer when
+//! in capture mode.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s) to be adjusted; must be one of:
+//! - \ref TIMER_A
+//! - \ref TIMER_B
+//! - \ref TIMER_BOTH
+//! \param ui32Event specifies the type of event; must be one of:
+//! - \ref TIMER_EVENT_POS_EDGE
+//! - \ref TIMER_EVENT_NEG_EDGE
+//! - \ref TIMER_EVENT_BOTH_EDGES
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+TimerEventControl(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Event)
+{
+ // Check the arguments.
+ ASSERT(TimerBaseValid(ui32Base));
+ ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+ (ui32Timer == TIMER_BOTH));
+
+ // Set the event type.
+ ui32Timer &= GPT_CTL_TAEVENT_M | GPT_CTL_TBEVENT_M;
+ HWREG(ui32Base + GPT_O_CTL) = ((HWREG(ui32Base + GPT_O_CTL) & ~ui32Timer) |
+ (ui32Event & ui32Timer));
+}
+
+//*****************************************************************************
+//
+//! \brief Controls the stall handling.
+//!
+//! This function controls the stall response for the specified timer. If the
+//! \e bStall parameter is \b true, then the timer stops counting if the
+//! processor enters debug mode; otherwise the timer keeps running while in
+//! debug mode.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s) to be adjusted; must be one of:
+//! - \ref TIMER_A
+//! - \ref TIMER_B
+//! - \ref TIMER_BOTH
+//! \param bStall specifies the response to a stall signal.
+//! - \c true : Timer stops counting if the processor enters debug mode.
+//! - \c false : Timer keeps running if the processor enters debug mode.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void TimerStallControl(uint32_t ui32Base, uint32_t ui32Timer,
+ bool bStall);
+
+//*****************************************************************************
+//
+//! \brief Controls the wait on trigger handling.
+//!
+//! This function controls whether or not a timer waits for a trigger input to
+//! start counting. When enabled, the previous timer in the trigger chain must
+//! count to its timeout in order for this timer to start counting. Refer to
+//! the part's data sheet for a description of the trigger chain.
+//!
+//! \note This function should not be used for Timer 0A or Wide Timer 0A.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s) to be adjusted; must be one of:
+//! - \ref TIMER_A
+//! - \ref TIMER_B
+//! - \ref TIMER_BOTH
+//! \param bWait specifies if the timer should wait for a trigger input.
+//! - \c true : Wait for trigger.
+//! - \c false : Do not wait for trigger.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void TimerWaitOnTriggerControl(uint32_t ui32Base, uint32_t ui32Timer,
+ bool bWait);
+
+//*****************************************************************************
+//
+//! \brief Set the timer prescale value.
+//!
+//! This function configures the value of the timer clock prescaler. The
+//! prescaler is only operational when in half-width mode and is used to extend
+//! the range of the half-width timer modes.
+//!
+//! When in one-shot or periodic down count modes, \b ui32Value defines the
+//! prescaler for the timer counter. When acting as a true prescaler, the
+//! prescaler counts down to 0 before the value in timer registers are incremented.
+//!
+//! In all other individual/split modes, \b ui32Value is a linear extension of
+//! the upper range of the timer counter, holding bits 23:16 in the 16-bit modes
+//! of the 16/32-bit timer.
+//!
+//! \note Because the prescaler counts down to 0 the timer division ratio equals
+//! \b ui32Value + 1. E.g. a prescale value of 15 divides the timer rate by 16.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s) to adjust; must be one of:
+//! - \ref TIMER_A
+//! - \ref TIMER_B
+//! - \ref TIMER_BOTH
+//! \param ui32Value is the timer prescale value which must be between 0 and 255
+//! (both included).
+//! - 0 : Timer division ratio = 1 (disable prescaling).
+//! - 1 : Timer division ratio = 2.
+//! - ...
+//! - 255 : Timer division ratio = 256.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+TimerPrescaleSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value)
+{
+ // Check the arguments.
+ ASSERT(TimerBaseValid(ui32Base));
+ ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+ (ui32Timer == TIMER_BOTH));
+ ASSERT(ui32Value < 256);
+
+ // Set the timer A prescaler if requested.
+ if(ui32Timer & TIMER_A)
+ {
+ HWREG(ui32Base + GPT_O_TAPR) = ui32Value;
+ }
+
+ // Set the timer B prescaler if requested.
+ if(ui32Timer & TIMER_B)
+ {
+ HWREG(ui32Base + GPT_O_TBPR) = ui32Value;
+ }
+}
+
+//*****************************************************************************
+//
+//! \brief Get the timer prescale value.
+//!
+//! This function gets the value of the timer clock prescaler. The
+//! prescaler is only operational when in half-width mode and is used to extend
+//! the range of the half-width timer modes.
+//!
+//! When in one-shot or periodic down count modes, \b ui32Value defines the
+//! prescaler for the timer counter. When acting as a true prescaler, the
+//! prescaler counts down to 0 before the value in timer registers are incremented.
+//!
+//! In all other individual/split modes, \b ui32Value is a linear extension of
+//! the upper range of the timer counter, holding bits 23:16 in the 16-bit modes
+//! of the 16/32-bit timer.
+//!
+//! \note Because the prescaler counts down to 0 the timer division ratio equals
+//! \b ui32Value + 1. E.g. a prescale value of 15 divides the timer rate by 16.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer; must be one of:
+//! - \ref TIMER_A
+//! - \ref TIMER_B
+//!
+//! \return Returns the value of the timer prescaler.
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+TimerPrescaleGet(uint32_t ui32Base, uint32_t ui32Timer)
+{
+ // Check the arguments.
+ ASSERT(TimerBaseValid(ui32Base));
+ ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+ (ui32Timer == TIMER_BOTH));
+
+ // Return the appropriate prescale value.
+ return((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAPR) :
+ HWREG(ui32Base + GPT_O_TBPR));
+}
+
+//*****************************************************************************
+//
+//! \brief Set the timer prescale match value.
+//!
+//! This function configures the value of the input clock prescaler match
+//! value. When in a half-width mode that uses the counter match and the
+//! prescaler, the prescale match effectively extends the range of the match.
+//! The prescaler provides the least significant bits when counting down in
+//! periodic and one-shot modes; in all other modes, the prescaler provides the
+//! most significant bits.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s) to adjust; must be one of:
+//! - \ref TIMER_A
+//! - \ref TIMER_B
+//! - \ref TIMER_BOTH
+//! \param ui32Value is the timer prescale match value which must be between 0
+//! and 255 (both included).
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+TimerPrescaleMatchSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value)
+{
+ // Check the arguments.
+ ASSERT(TimerBaseValid(ui32Base));
+ ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+ (ui32Timer == TIMER_BOTH));
+ ASSERT(ui32Value < 256);
+
+ // Set the timer A prescale match if requested.
+ if(ui32Timer & TIMER_A)
+ {
+ HWREG(ui32Base + GPT_O_TAPMR) = ui32Value;
+ }
+
+ // Set the timer B prescale match if requested.
+ if(ui32Timer & TIMER_B)
+ {
+ HWREG(ui32Base + GPT_O_TBPMR) = ui32Value;
+ }
+}
+
+//*****************************************************************************
+//
+//! \brief Get the timer prescale match value.
+//!
+//! This function gets the value of the input clock prescaler match value.
+//! When in a half-width mode that uses the counter match and prescaler, the
+//! prescale match effectively extends the range of the match. The prescaler
+//! provides the least significant bits when counting down in periodic and
+//! one-shot modes; in all other modes, the prescaler provides the most
+//! significant bits.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer; must be one of:
+//! - \ref TIMER_A
+//! - \ref TIMER_B
+//!
+//! \return Returns the value of the timer prescale match.
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+TimerPrescaleMatchGet(uint32_t ui32Base, uint32_t ui32Timer)
+{
+ // Check the arguments.
+ ASSERT(TimerBaseValid(ui32Base));
+ ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B));
+
+ // Return the appropriate prescale match value.
+ return((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAPMR) :
+ HWREG(ui32Base + GPT_O_TBPMR));
+}
+
+//*****************************************************************************
+//
+//! \brief Sets the timer load value.
+//!
+//! This function configures the timer load value; if the timer is running then
+//! the value is immediately loaded into the timer.
+//!
+//! \note This function can be used for both full- and half-width modes of
+//! 16/32-bit timers.
+//!
+//! \note Only \ref TIMER_A should be used when the timer is configured for
+//! full-width operation.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s) to adjust; must be one of:
+//! - \ref TIMER_A
+//! - \ref TIMER_B
+//! - \ref TIMER_BOTH
+//! \param ui32Value is the load value.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+TimerLoadSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value)
+{
+ // Check the arguments.
+ ASSERT(TimerBaseValid(ui32Base));
+ ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+ (ui32Timer == TIMER_BOTH));
+
+ // Set the timer A load value if requested.
+ if(ui32Timer & TIMER_A)
+ {
+ HWREG(ui32Base + GPT_O_TAILR) = ui32Value;
+ }
+
+ // Set the timer B load value if requested.
+ if(ui32Timer & TIMER_B)
+ {
+ HWREG(ui32Base + GPT_O_TBILR) = ui32Value;
+ }
+}
+
+//*****************************************************************************
+//
+//! \brief Gets the timer load value.
+//!
+//! This function gets the currently programmed interval load value for the
+//! specified timer.
+//!
+//! \note This function can be used for both full- and half-width modes of
+//! 16/32-bit timers.
+//!
+//! \note Only \ref TIMER_A should be used when the timer is configured for
+//! full-width operation.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer; must be one of:
+//! - \ref TIMER_A
+//! - \ref TIMER_B
+//!
+//! \return Returns the load value for the timer
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+TimerLoadGet(uint32_t ui32Base, uint32_t ui32Timer)
+{
+ // Check the arguments.
+ ASSERT(TimerBaseValid(ui32Base));
+ ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B));
+
+ // Return the appropriate load value.
+ return((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAILR) :
+ HWREG(ui32Base + GPT_O_TBILR));
+}
+
+//*****************************************************************************
+//
+//! \brief Gets the current timer value.
+//!
+//! This function reads the current value of the specified timer.
+//!
+//! \note This function can be used for both full- and half-width modes of
+//! 16/32-bit timers.
+//!
+//! \note Only \ref TIMER_A should be used when the timer is configured for
+//! full-width operation.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer; must be one of:
+//! - \ref TIMER_A
+//! - \ref TIMER_B
+//!
+//! \return Returns the current value of the timer.
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+TimerValueGet(uint32_t ui32Base, uint32_t ui32Timer)
+{
+ // Check the arguments.
+ ASSERT(TimerBaseValid(ui32Base));
+ ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B));
+
+ // Return the appropriate timer value.
+ return((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAR) :
+ HWREG(ui32Base + GPT_O_TBR));
+}
+
+//*****************************************************************************
+//
+//! \brief Sets the timer match value.
+//!
+//! This function configures the match value for a timer. This value is used
+//! in capture count mode to determine when to interrupt the processor and in
+//! PWM mode to determine the duty cycle of the output signal. Match interrupts
+//! can also be generated in periodic and one-shot modes when the value of the
+//! counter matches this register.
+//!
+//! \note This function can be used for both full- and half-width modes of
+//! 16/32-bit timers.
+//!
+//! \note Only \ref TIMER_A should be used when the timer is configured for
+//! full-width operation.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s) to adjust; must be one of:
+//! - \ref TIMER_A
+//! - \ref TIMER_B
+//! - \ref TIMER_BOTH
+//! \param ui32Value is the match value.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+TimerMatchSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value)
+{
+ // Check the arguments.
+ ASSERT(TimerBaseValid(ui32Base));
+ ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+ (ui32Timer == TIMER_BOTH));
+
+ // Set the timer A match value if requested.
+ if(ui32Timer & TIMER_A)
+ {
+ HWREG(ui32Base + GPT_O_TAMATCHR) = ui32Value;
+ }
+
+ // Set the timer B match value if requested.
+ if(ui32Timer & TIMER_B)
+ {
+ HWREG(ui32Base + GPT_O_TBMATCHR) = ui32Value;
+ }
+}
+
+//*****************************************************************************
+//
+//! \brief Gets the timer match value.
+//!
+//! This function gets the match value for the specified timer.
+//!
+//! \note This function can be used for both full- and half-width modes of
+//! 16/32-bit timers.
+//!
+//! \note Only \ref TIMER_A should be used when the timer is configured for
+//! full-width operation.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer; must be one of:
+//! - \ref TIMER_A
+//! - \ref TIMER_B
+//! - \ref TIMER_BOTH
+//!
+//! \return Returns the match value for the timer
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+TimerMatchGet(uint32_t ui32Base, uint32_t ui32Timer)
+{
+ // Check the arguments.
+ ASSERT(TimerBaseValid(ui32Base));
+ ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B));
+
+ // Return the appropriate match value.
+ return((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAMATCHR) :
+ HWREG(ui32Base + GPT_O_TBMATCHR));
+}
+
+//*****************************************************************************
+//
+//! \brief Registers an interrupt handler for the timer interrupt in the dynamic interrupt table.
+//!
+//! \note Only use this function if you want to use the dynamic vector table (in SRAM)!
+//!
+//! This function registers a function as the interrupt handler for a specific
+//! interrupt and enables the corresponding interrupt in the interrupt controller.
+//!
+//! Specific timer interrupts must be enabled via \ref TimerIntEnable(). It is the
+//! interrupt handler's responsibility to clear the interrupt source via
+//! \ref TimerIntClear().
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s); must be one of:
+//! - \ref TIMER_A
+//! - \ref TIMER_B
+//! - \ref TIMER_BOTH
+//! \param pfnHandler is a pointer to the function to be called when the timer
+//! interrupt occurs.
+//!
+//! \return None
+//!
+//! \sa \ref IntRegister() for important information about registering interrupt
+//! handlers.
+//
+//*****************************************************************************
+extern void TimerIntRegister(uint32_t ui32Base, uint32_t ui32Timer,
+ void (*pfnHandler)(void));
+
+//*****************************************************************************
+//
+//! \brief Unregisters an interrupt handler for the timer interrupt in the dynamic interrupt table.
+//!
+//! This function unregisters the handler to be called when a timer interrupt
+//! occurs. This function also masks off the interrupt in the interrupt
+//! controller so that the interrupt handler is no longer called.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s); must be one of:
+//! - \ref TIMER_A
+//! - \ref TIMER_B
+//! - \ref TIMER_BOTH
+//!
+//! \return None
+//!
+//! \sa \ref IntRegister() for important information about registering interrupt
+//! handlers.
+//
+//*****************************************************************************
+extern void TimerIntUnregister(uint32_t ui32Base, uint32_t ui32Timer);
+
+//*****************************************************************************
+//
+//! \brief Enables individual timer interrupt sources.
+//!
+//! This function enables the indicated timer interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled.
+//! The parameter must be the bitwise OR of any combination of
+//! the following:
+//! - \ref TIMER_CAPB_EVENT : Capture B event interrupt.
+//! - \ref TIMER_CAPB_MATCH : Capture B match interrupt.
+//! - \ref TIMER_TIMB_TIMEOUT : Timer B timeout interrupt.
+//! - \ref TIMER_CAPA_EVENT : Capture A event interrupt.
+//! - \ref TIMER_CAPA_MATCH : Capture A match interrupt.
+//! - \ref TIMER_TIMA_TIMEOUT : Timer A timeout interrupt.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+TimerIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ // Check the arguments.
+ ASSERT(TimerBaseValid(ui32Base));
+
+ // Enable the specified interrupts.
+ HWREG(ui32Base + GPT_O_IMR) |= ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! \brief Disables individual timer interrupt sources.
+//!
+//! This function disables the indicated timer interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled.
+//! The parameter must be the bitwise OR of any combination of
+//! the following:
+//! - \ref TIMER_CAPB_EVENT : Capture B event interrupt.
+//! - \ref TIMER_CAPB_MATCH : Capture B match interrupt.
+//! - \ref TIMER_TIMB_TIMEOUT : Timer B timeout interrupt.
+//! - \ref TIMER_CAPA_EVENT : Capture A event interrupt.
+//! - \ref TIMER_CAPA_MATCH : Capture A match interrupt.
+//! - \ref TIMER_TIMA_TIMEOUT : Timer A timeout interrupt.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+TimerIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ // Check the arguments.
+ ASSERT(TimerBaseValid(ui32Base));
+
+ // Disable the specified interrupts.
+ HWREG(ui32Base + GPT_O_IMR) &= ~(ui32IntFlags);
+}
+
+//*****************************************************************************
+//
+//! \brief Gets the current interrupt status.
+//!
+//! This function returns the interrupt status for the timer module. Either
+//! the raw interrupt status or the status of interrupts that are allowed to
+//! reflect to the processor can be returned.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param bMasked selects either raw or masked interrupt status:
+//! - \c true : Masked interrupt.
+//! - \c false : Raw interrupt.
+//!
+//! \return The current interrupt status, enumerated as a bit field of values:
+//! - \ref TIMER_CAPB_EVENT : Capture B event interrupt.
+//! - \ref TIMER_CAPB_MATCH : Capture B match interrupt.
+//! - \ref TIMER_TIMB_TIMEOUT : Timer B timeout interrupt.
+//! - \ref TIMER_CAPA_EVENT : Capture A event interrupt.
+//! - \ref TIMER_CAPA_MATCH : Capture A match interrupt.
+//! - \ref TIMER_TIMA_TIMEOUT : Timer A timeout interrupt.
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+TimerIntStatus(uint32_t ui32Base, bool bMasked)
+{
+ // Check the arguments.
+ ASSERT(TimerBaseValid(ui32Base));
+
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ return(bMasked ? HWREG(ui32Base + GPT_O_MIS) :
+ HWREG(ui32Base + GPT_O_RIS));
+}
+
+//*****************************************************************************
+//
+//! \brief Clears timer interrupt sources.
+//!
+//! The specified timer interrupt sources are cleared, so that they no longer
+//! assert. This function must be called in the interrupt handler to keep the
+//! interrupt from being triggered again immediately upon exit.
+//!
+//! \note Due to write buffers and synchronizers in the system it may take several
+//! clock cycles from a register write clearing an event in a module and until the
+//! event is actually cleared in the NVIC of the system CPU. It is recommended to
+//! clear the event source early in the interrupt service routine (ISR) to allow
+//! the event clear to propagate to the NVIC before returning from the ISR.
+//! At the same time, an early event clear allows new events of the same type to be
+//! pended instead of ignored if the event is cleared later in the ISR.
+//! It is the responsibility of the programmer to make sure that enough time has passed
+//! before returning from the ISR to avoid false re-triggering of the cleared event.
+//! A simple, although not necessarily optimal, way of clearing an event before
+//! returning from the ISR is:
+//! -# Write to clear event (interrupt source). (buffered write)
+//! -# Dummy read from the event source module. (making sure the write has propagated)
+//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers)
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared.
+//! The parameter must be the bitwise OR of any combination of
+//! the following:
+//! - \ref TIMER_CAPB_EVENT : Capture B event interrupt.
+//! - \ref TIMER_CAPB_MATCH : Capture B match interrupt.
+//! - \ref TIMER_TIMB_TIMEOUT : Timer B timeout interrupt.
+//! - \ref TIMER_CAPA_EVENT : Capture A event interrupt.
+//! - \ref TIMER_CAPA_MATCH : Capture A match interrupt.
+//! - \ref TIMER_TIMA_TIMEOUT : Timer A timeout interrupt.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+TimerIntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ // Check the arguments.
+ ASSERT(TimerBaseValid(ui32Base));
+
+ // Clear the requested interrupt sources.
+ HWREG(ui32Base + GPT_O_ICLR) = ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! \brief Synchronizes the counters in a set of timers.
+//!
+//! This function synchronizes the counters in a specified set of timers.
+//! When a timer is running in half-width mode, each half can be included or
+//! excluded in the synchronization event. When a timer is running in
+//! full-width mode, only the A timer can be synchronized (specifying the B
+//! timer has no effect).
+//!
+//! \param ui32Base is the base address of the timer module. This parameter must
+//! be the base address of Timer0 (in other words, \b GPT0_BASE).
+//! \param ui32Timers is the set of timers to synchronize.
+//! The parameter is the bitwise OR of any of the following:
+//! - \ref TIMER_0A_SYNC
+//! - \ref TIMER_0B_SYNC
+//! - \ref TIMER_1A_SYNC
+//! - \ref TIMER_1B_SYNC
+//! - \ref TIMER_2A_SYNC
+//! - \ref TIMER_2B_SYNC
+//! - \ref TIMER_3A_SYNC
+//! - \ref TIMER_3B_SYNC
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+TimerSynchronize(uint32_t ui32Base, uint32_t ui32Timers)
+{
+ // Check the arguments.
+ ASSERT(ui32Base == GPT0_BASE);
+
+ // Synchronize the specified timers.
+ HWREG(ui32Base + GPT_O_SYNC) = ui32Timers;
+}
+
+//*****************************************************************************
+//
+//! \brief Enables AND'ing of the CCP outputs from Timer A and Timer B.
+//!
+//! \param ui32Base is the base address of the timer module.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+TimerCcpCombineEnable(uint32_t ui32Base)
+{
+ // Check the arguments
+ ASSERT(TimerBaseValid(ui32Base));
+
+ // Set the bit
+ HWREG(ui32Base + GPT_O_ANDCCP) |= GPT_ANDCCP_CCP_AND_EN;
+}
+
+//*****************************************************************************
+//
+//! \brief Disables AND'ing of the CCP outputs from Timer A and Timer B.
+//!
+//! \param ui32Base is the base address of the timer module.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+TimerCcpCombineDisable(uint32_t ui32Base)
+{
+ // Check the arguments
+ ASSERT(TimerBaseValid(ui32Base));
+
+ // Clear the bit
+ HWREG(ui32Base + GPT_O_ANDCCP) &= ~(GPT_ANDCCP_CCP_AND_EN);
+}
+
+//*****************************************************************************
+//
+//! \brief Sets the Match Register Update mode.
+//!
+//! This function controls when the Match Register value and Prescale Register value
+//! are applied after writing these registers while a timer is enabled.
+//!
+//! \note If the timer is disabled when setting the update mode the Match Register
+//! and Prescale Register values are applied immediately when enabling the timer.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s) to configure; must be one of:
+//! - \ref TIMER_A
+//! - \ref TIMER_B
+//! - \ref TIMER_BOTH
+//! \param ui32Mode sets the mode:
+//! - \ref TIMER_MATCHUPDATE_NEXTCYCLE : Apply Match Register and Prescale Register on next clock
+//! cycle after writing any of these registers.
+//! - \ref TIMER_MATCHUPDATE_TIMEOUT : Apply Match Register and Prescale Register on next timeout
+//! after writing any of these registers.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void TimerMatchUpdateMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode);
+
+//*****************************************************************************
+//
+//! \brief Sets the Interval Load mode.
+//!
+//! This function controls when the Timer Register and Prescale Snap-shot (if used)
+//! are updated.
+//!
+//! Timer Register (TAR/TBR) is updated when Interval Load Register (TAILR/TBILR) is written
+//! and the Prescale Snap-shot (TAPS/TBPS) is updated when Prescale Register (TAPR/TBPR) is
+//! written depending on the mode of operation.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s) to configure; must be one of:
+//! - \ref TIMER_A
+//! - \ref TIMER_B
+//! - \ref TIMER_BOTH
+//! \param ui32Mode sets the mode:
+//! - \ref TIMER_INTERVALLOAD_NEXTCYCLE : Update Timer Register and Prescale Snap-shot on next clock
+//! cycle after writing Interval Load Register or Prescale Register, respectively.
+//! - \ref TIMER_INTERVALLOAD_TIMEOUT : Update Timer Register and Prescale Snap-shot on next timeout
+//! after writing Interval Load Register or Prescale Register, respectively.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void TimerIntervalLoadMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode);
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// Redirect to implementation in ROM when available.
+//
+//*****************************************************************************
+#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
+ #include "../driverlib/rom.h"
+ #ifdef ROM_TimerConfigure
+ #undef TimerConfigure
+ #define TimerConfigure ROM_TimerConfigure
+ #endif
+ #ifdef ROM_TimerLevelControl
+ #undef TimerLevelControl
+ #define TimerLevelControl ROM_TimerLevelControl
+ #endif
+ #ifdef ROM_TimerStallControl
+ #undef TimerStallControl
+ #define TimerStallControl ROM_TimerStallControl
+ #endif
+ #ifdef ROM_TimerWaitOnTriggerControl
+ #undef TimerWaitOnTriggerControl
+ #define TimerWaitOnTriggerControl ROM_TimerWaitOnTriggerControl
+ #endif
+ #ifdef ROM_TimerIntRegister
+ #undef TimerIntRegister
+ #define TimerIntRegister ROM_TimerIntRegister
+ #endif
+ #ifdef ROM_TimerIntUnregister
+ #undef TimerIntUnregister
+ #define TimerIntUnregister ROM_TimerIntUnregister
+ #endif
+ #ifdef ROM_TimerMatchUpdateMode
+ #undef TimerMatchUpdateMode
+ #define TimerMatchUpdateMode ROM_TimerMatchUpdateMode
+ #endif
+ #ifdef ROM_TimerIntervalLoadMode
+ #undef TimerIntervalLoadMode
+ #define TimerIntervalLoadMode ROM_TimerIntervalLoadMode
+ #endif
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __GPT_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/timer_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/timer_doc.h
new file mode 100644
index 0000000..f30779f
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/timer_doc.h
@@ -0,0 +1,121 @@
+/******************************************************************************
+* Filename: timer_doc.h
+* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016)
+* Revision: 45971
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+//! \addtogroup timer_api
+//! @{
+//! \section sec_timer Introduction
+//!
+//! The timer API provides a set of functions for using the general-purpose timer module.
+//!
+//! The timer module contains four timer blocks with the following functional options:
+//! - Operating modes:
+//! - 16-bit with 8-bit prescaler or 32-bit programmable one-shot timer.
+//! - 16-bit with 8-bit prescaler or 32-bit programmable periodic timer.
+//! - Two capture compare PWM pins (CCP) for each 32-bit timer.
+//! - 24-bit input-edge count or 24-bit time-capture modes.
+//! - 24-bit PWM mode with software-programmable output inversion of the PWM signal.
+//! - Count up or down.
+//! - Daisy chaining of timer modules allows a single timer to initiate multiple timing events.
+//! - Timer synchronization allows selected timers to start counting on the same clock cycle.
+//! - User-enabled stalling when the System CPU asserts a CPU Halt flag during debug.
+//! - Ability to determine the elapsed time between the assertion of the timer interrupt and
+//! entry into the interrupt service routine.
+//!
+//! Each timer block provides two half-width timers/counters that can be configured
+//! to operate independently as timers or event counters or to operate as a combined
+//! full-width timer.
+//! The timers provide 16-bit half-width timers and a 32-bit full-width timer.
+//! For the purposes of this API, the two
+//! half-width timers provided by a timer block are referred to as TimerA and
+//! TimerB, and the full-width timer is referred to as TimerA.
+//!
+//! When in half-width mode, the timer can also be configured for event capture or
+//! as a pulse width modulation (PWM) generator. When configured for event
+//! capture, the timer acts as a counter. It can be configured to count either the
+//! time between events or the events themselves. The type of event
+//! being counted can be configured as a positive edge, a negative edge, or both
+//! edges. When a timer is configured as a PWM generator, the input signal used to
+//! capture events becomes an output signal, and the timer drives an
+//! edge-aligned pulse onto that signal.
+//!
+//! Control is also provided over interrupt sources and events. Interrupts can be
+//! generated to indicate that an event has been captured, or that a certain number
+//! of events have been captured. Interrupts can also be generated when the timer
+//! has counted down to 0 or when the timer matches a certain value.
+//!
+//! Timer configuration is handled by \ref TimerConfigure(), which performs the high
+//! level setup of the timer module; that is, it is used to set up full- or
+//! half-width modes, and to select between PWM, capture, and timer operations.
+//!
+//! \section sec_timer_api API
+//!
+//! The API functions can be grouped like this:
+//!
+//! Functions to perform timer control:
+//! - \ref TimerConfigure()
+//! - \ref TimerEnable()
+//! - \ref TimerDisable()
+//! - \ref TimerLevelControl()
+//! - \ref TimerWaitOnTriggerControl()
+//! - \ref TimerEventControl()
+//! - \ref TimerStallControl()
+//! - \ref TimerIntervalLoadMode()
+//! - \ref TimerMatchUpdateMode()
+//! - \ref TimerCcpCombineDisable()
+//! - \ref TimerCcpCombineEnable()
+//!
+//! Functions to manage timer content:
+//! - \ref TimerLoadSet()
+//! - \ref TimerLoadGet()
+//! - \ref TimerPrescaleSet()
+//! - \ref TimerPrescaleGet()
+//! - \ref TimerMatchSet()
+//! - \ref TimerMatchGet()
+//! - \ref TimerPrescaleMatchSet()
+//! - \ref TimerPrescaleMatchGet()
+//! - \ref TimerValueGet()
+//! - \ref TimerSynchronize()
+//!
+//! Functions to manage the interrupt handler for the timer interrupt:
+//! - \ref TimerIntRegister()
+//! - \ref TimerIntUnregister()
+//!
+//! The individual interrupt sources within the timer module are managed with:
+//! - \ref TimerIntEnable()
+//! - \ref TimerIntDisable()
+//! - \ref TimerIntStatus()
+//! - \ref TimerIntClear()
+//!
+//! @}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/trng.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/trng.c
new file mode 100644
index 0000000..751c5cb
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/trng.c
@@ -0,0 +1,112 @@
+/******************************************************************************
+* Filename: trng.c
+* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017)
+* Revision: 48852
+*
+* Description: Driver for the TRNG module
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "trng.h"
+
+//*****************************************************************************
+//
+// Handle support for DriverLib in ROM:
+// This section will undo prototype renaming made in the header file
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #undef TRNGConfigure
+ #define TRNGConfigure NOROM_TRNGConfigure
+ #undef TRNGNumberGet
+ #define TRNGNumberGet NOROM_TRNGNumberGet
+#endif
+
+//*****************************************************************************
+//
+// Configure the true random number generator
+//
+//*****************************************************************************
+void
+TRNGConfigure(uint32_t ui32MinSamplesPerCycle,
+ uint32_t ui32MaxSamplesPerCycle,
+ uint32_t ui32ClocksPerSample)
+{
+ uint32_t ui32Val;
+
+ // Make sure the TRNG is disabled.
+ ui32Val = HWREG(TRNG_BASE + TRNG_O_CTL) & ~TRNG_CTL_TRNG_EN;
+ HWREG(TRNG_BASE + TRNG_O_CTL) = ui32Val;
+
+ // Configure the startup number of samples.
+ ui32Val &= ~TRNG_CTL_STARTUP_CYCLES_M;
+ ui32Val |= ((( ui32MaxSamplesPerCycle >> 8 ) << TRNG_CTL_STARTUP_CYCLES_S ) & TRNG_CTL_STARTUP_CYCLES_M );
+ HWREG(TRNG_BASE + TRNG_O_CTL) = ui32Val;
+
+ // Configure the minimum and maximum number of samples pr generated number
+ // and the number of clocks per sample.
+ HWREG(TRNG_BASE + TRNG_O_CFG0) = (
+ ((( ui32MaxSamplesPerCycle >> 8 ) << TRNG_CFG0_MAX_REFILL_CYCLES_S ) & TRNG_CFG0_MAX_REFILL_CYCLES_M ) |
+ ((( ui32ClocksPerSample ) << TRNG_CFG0_SMPL_DIV_S ) & TRNG_CFG0_SMPL_DIV_M ) |
+ ((( ui32MinSamplesPerCycle >> 6 ) << TRNG_CFG0_MIN_REFILL_CYCLES_S ) & TRNG_CFG0_MIN_REFILL_CYCLES_M ) );
+}
+
+//*****************************************************************************
+//
+// Get a random number from the generator
+//
+//*****************************************************************************
+uint32_t
+TRNGNumberGet(uint32_t ui32Word)
+{
+ uint32_t ui32RandomNumber;
+
+ // Check the arguments.
+ ASSERT((ui32Word == TRNG_HI_WORD) ||
+ (ui32Word == TRNG_LOW_WORD));
+
+ // Return the right requested part of the generated number.
+ if(ui32Word == TRNG_HI_WORD)
+ {
+ ui32RandomNumber = HWREG(TRNG_BASE + TRNG_O_OUT1);
+ }
+ else
+ {
+ ui32RandomNumber = HWREG(TRNG_BASE + TRNG_O_OUT0);
+ }
+
+ // Initiate generation of new number.
+ HWREG(TRNG_BASE + TRNG_O_IRQFLAGCLR) = 0x1;
+
+ // Return the random number.
+ return ui32RandomNumber;
+}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/trng.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/trng.h
new file mode 100644
index 0000000..2a2f047
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/trng.h
@@ -0,0 +1,451 @@
+/******************************************************************************
+* Filename: trng.h
+* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017)
+* Revision: 49048
+*
+* Description: Defines and prototypes for the true random number gen.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup peripheral_group
+//! @{
+//! \addtogroup trng_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __TRNG_H__
+#define __TRNG_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "../inc/hw_types.h"
+#include "../inc/hw_trng.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_ints.h"
+#include "debug.h"
+#include "interrupt.h"
+#include "cpu.h"
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// This section renames all functions that are not "static inline", so that
+// calling these functions will default to implementation in flash. At the end
+// of this file a second renaming will change the defaults to implementation in
+// ROM for available functions.
+//
+// To force use of the implementation in flash, e.g. for debugging:
+// - Globally: Define DRIVERLIB_NOROM at project level
+// - Per function: Use prefix "NOROM_" when calling the function
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #define TRNGConfigure NOROM_TRNGConfigure
+ #define TRNGNumberGet NOROM_TRNGNumberGet
+#endif
+
+//*****************************************************************************
+//
+//
+//
+//*****************************************************************************
+#define TRNG_NUMBER_READY 0x00000001 //
+#define TRNG_FRO_SHUTDOWN 0x00000002 //
+#define TRNG_NEED_CLOCK 0x80000000 //
+
+#define TRNG_HI_WORD 0x00000001
+#define TRNG_LOW_WORD 0x00000002
+
+//*****************************************************************************
+//
+// API Function and prototypes
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \brief Configure the true random number generator.
+//!
+//! Use this function to set the minimum and maximum number of samples required
+//! in each generation of a new random number.
+//!
+//! \param ui32MinSamplesPerCycle is the minimum number of samples per each
+//! generated random number. Constraints:
+//! - Value must be bigger than or equal to 2^6 and less than 2^14.
+//! - The 6 LSBs of the argument are truncated.
+//! - If the value is zero, the number of samples is fixed to the value determined
+//! by ui32MaxSamplesPerCycle. To ensure same entropy in all generated random
+//! numbers the value 0 should be used.
+//! \param ui32MaxSamplesPerCycle is the maximum number of samples per each
+//! generated random number. Constraints:
+//! - Value must be between 2^8 and 2^24 (both included).
+//! - The 8 LSBs of the argument are truncated.
+//! - Value 0 and 2^24 both give the highest possible value.
+//! \param ui32ClocksPerSample is the number of clock cycles for each time
+//! a new sample is generated from the FROs.
+//! - 0 : Every sample.
+//! - 1 : Every second sample.
+//! - ...
+//! - 15 : Every 16. sample.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void TRNGConfigure(uint32_t ui32MinSamplesPerCycle,
+ uint32_t ui32MaxSamplesPerCycle,
+ uint32_t ui32ClocksPerSample);
+
+//*****************************************************************************
+//
+//! \brief Enable the TRNG.
+//!
+//! Enable the TRNG to start preparing a random number.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+TRNGEnable(void)
+{
+ // Enable the TRNG.
+ HWREGBITW(TRNG_BASE + TRNG_O_CTL, TRNG_CTL_TRNG_EN_BITN) = 1;
+}
+
+//*****************************************************************************
+//
+//! \brief Disable the TRNG module.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+TRNGDisable(void)
+{
+ // Enable the TRNG
+ HWREGBITW(TRNG_BASE + TRNG_O_CTL, TRNG_CTL_TRNG_EN_BITN) = 0;
+}
+
+//*****************************************************************************
+//
+//! \brief Get a random number from the generator.
+//!
+//! Use this function to get either the high or low part of the 64 bit
+//! generated number.
+//!
+//! \note Data from this register is only valid if the TRNG has produced a
+//! number. Use \ref TRNGStatusGet() to poll the for status. After calling this
+//! function a new random number will be generated.
+//!
+//! \param ui32Word determines if whether to return the high or low 32 bits.
+//! - \ref TRNG_HI_WORD
+//! - \ref TRNG_LOW_WORD
+//!
+//! \return Return either the high or low part of the 64 bit generated random
+//! number.
+//
+//*****************************************************************************
+extern uint32_t TRNGNumberGet(uint32_t ui32Word);
+
+//*****************************************************************************
+//
+//! \brief Get the status of the TRNG.
+//!
+//! Use this function to retrieve the status of the TRNG.
+//!
+//! \return Returns the current status of the TRNG module.
+//! The returned status is a bitwise OR'ed combination of:
+//! - \ref TRNG_NUMBER_READY
+//! - \ref TRNG_FRO_SHUTDOWN
+//! - \ref TRNG_NEED_CLOCK
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+TRNGStatusGet(void)
+{
+ // Return the status.
+ return (HWREG(TRNG_BASE + TRNG_O_IRQFLAGSTAT));
+}
+
+//*****************************************************************************
+//
+//! \brief Reset the TRNG.
+//!
+//! Use this function to reset the TRNG module. Reset will be low for
+//! approximately 5 clock cycles.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+TRNGReset(void)
+{
+ // Reset the TRNG.
+ HWREG(TRNG_BASE + TRNG_O_SWRESET) = 1;
+}
+
+//*****************************************************************************
+//
+//! \brief Enables individual TRNG interrupt sources.
+//!
+//! This function enables the indicated TRNG interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled.
+//! The parameter is the bitwise OR of any of the following:
+//! - \ref TRNG_NUMBER_READY
+//! - \ref TRNG_FRO_SHUTDOWN
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+TRNGIntEnable(uint32_t ui32IntFlags)
+{
+ // Check the arguments.
+ ASSERT((ui32IntFlags & TRNG_NUMBER_READY) ||
+ (ui32IntFlags & TRNG_FRO_SHUTDOWN));
+
+ // Enable the specified interrupts.
+ HWREG(TRNG_BASE + TRNG_O_IRQFLAGMASK) |= ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! \brief Disables individual TRNG interrupt sources.
+//!
+//! This function disables the indicated TRNG interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled.
+//! The parameter is the bitwise OR of any of the following:
+//! - \ref TRNG_NUMBER_READY
+//! - \ref TRNG_FRO_SHUTDOWN
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+TRNGIntDisable(uint32_t ui32IntFlags)
+{
+ // Check the arguments.
+ ASSERT((ui32IntFlags & TRNG_NUMBER_READY) ||
+ (ui32IntFlags & TRNG_FRO_SHUTDOWN));
+
+ // Disable the specified interrupts.
+ HWREG(TRNG_BASE + TRNG_O_IRQFLAGMASK) &= ~ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! \brief Gets the current interrupt status of the TRNG module.
+//!
+//! This function returns the interrupt status for the specified TRNG. Either
+//! the raw interrupt status or the status of interrupts that are allowed to
+//! reflect to the processor can be returned.
+//!
+//! \param bMasked selects either raw or masked interrupt status.
+//! - \c true : Masked interrupt.
+//! - \c false : Raw interrupt.
+//!
+//! \return Returns the current interrupt status, enumerated as:
+//! - \ref TRNG_NUMBER_READY
+//! - \ref TRNG_FRO_SHUTDOWN
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+TRNGIntStatus(bool bMasked)
+{
+ uint32_t ui32Mask;
+
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ if(bMasked)
+ {
+ ui32Mask = HWREG(TRNG_BASE + TRNG_O_IRQFLAGMASK);
+ return(ui32Mask & HWREG(TRNG_BASE + TRNG_O_IRQFLAGSTAT));
+ }
+ else
+ {
+ return(HWREG(TRNG_BASE + TRNG_O_IRQFLAGSTAT) & 0x00000003);
+ }
+}
+
+//*****************************************************************************
+//
+//! \brief Clears TRNG interrupt sources.
+//!
+//! The specified TRNG interrupt sources are cleared, so that they no longer
+//! assert. This function must be called in the interrupt handler to keep the
+//! interrupt from being recognized again immediately upon exit.
+//!
+//! \note Due to write buffers and synchronizers in the system it may take several
+//! clock cycles from a register write clearing an event in a module and until the
+//! event is actually cleared in the NVIC of the system CPU. It is recommended to
+//! clear the event source early in the interrupt service routine (ISR) to allow
+//! the event clear to propagate to the NVIC before returning from the ISR.
+//! At the same time, an early event clear allows new events of the same type to be
+//! pended instead of ignored if the event is cleared later in the ISR.
+//! It is the responsibility of the programmer to make sure that enough time has passed
+//! before returning from the ISR to avoid false re-triggering of the cleared event.
+//! A simple, although not necessarily optimal, way of clearing an event before
+//! returning from the ISR is:
+//! -# Write to clear event (interrupt source). (buffered write)
+//! -# Dummy read from the event source module. (making sure the write has propagated)
+//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers)
+//!
+//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared.
+//! The parameter is the bitwise OR of any of the following:
+//! - \ref TRNG_NUMBER_READY
+//! - \ref TRNG_FRO_SHUTDOWN
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+TRNGIntClear(uint32_t ui32IntFlags)
+{
+ // Check the arguments.
+ ASSERT((ui32IntFlags & TRNG_NUMBER_READY) ||
+ (ui32IntFlags & TRNG_FRO_SHUTDOWN));
+
+ // Clear the requested interrupt sources.
+ HWREG(TRNG_BASE + TRNG_O_IRQFLAGCLR) = ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! \brief Registers an interrupt handler for a TRNG interrupt in the dynamic interrupt table.
+//!
+//! \note Only use this function if you want to use the dynamic vector table (in SRAM)!
+//!
+//! This function registers a function as the interrupt handler for a specific
+//! interrupt and enables the corresponding interrupt in the interrupt controller.
+//!
+//! Specific TRNG interrupts must be enabled via \ref TRNGIntEnable(). It is the interrupt
+//! handler's responsibility to clear the interrupt source.
+//!
+//! \param pfnHandler is a pointer to the function to be called when the
+//! TRNG interrupt occurs.
+//!
+//! \return None
+//!
+//! \sa \ref IntRegister() for important information about registering interrupt
+//! handlers.
+//
+//*****************************************************************************
+__STATIC_INLINE void
+TRNGIntRegister(void (*pfnHandler)(void))
+{
+ // Register the interrupt handler.
+ IntRegister(INT_TRNG_IRQ, pfnHandler);
+
+ // Enable the TRNG interrupt.
+ IntEnable(INT_TRNG_IRQ);
+}
+
+//*****************************************************************************
+//
+//! \brief Unregisters an interrupt handler for a TRNG interrupt in the dynamic interrupt table.
+//!
+//! This function does the actual unregistering of the interrupt handler. It
+//! clears the handler to be called when a Crypto interrupt occurs. This
+//! function also masks off the interrupt in the interrupt controller so that
+//! the interrupt handler no longer is called.
+//!
+//! \return None
+//!
+//! \sa \ref IntRegister() for important information about registering interrupt
+//! handlers.
+//
+//*****************************************************************************
+__STATIC_INLINE void
+TRNGIntUnregister(void)
+{
+ // Disable the interrupt.
+ IntDisable(INT_TRNG_IRQ);
+
+ // Unregister the interrupt handler.
+ IntUnregister(INT_TRNG_IRQ);
+}
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// Redirect to implementation in ROM when available.
+//
+//*****************************************************************************
+#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
+ #include "../driverlib/rom.h"
+ #ifdef ROM_TRNGConfigure
+ #undef TRNGConfigure
+ #define TRNGConfigure ROM_TRNGConfigure
+ #endif
+ #ifdef ROM_TRNGNumberGet
+ #undef TRNGNumberGet
+ #define TRNGNumberGet ROM_TRNGNumberGet
+ #endif
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __TRNG_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/uart.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/uart.c
new file mode 100644
index 0000000..d9f493b
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/uart.c
@@ -0,0 +1,304 @@
+/******************************************************************************
+* Filename: uart.c
+* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017)
+* Revision: 49096
+*
+* Description: Driver for the UART.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "uart.h"
+
+//*****************************************************************************
+//
+// Handle support for DriverLib in ROM:
+// This section will undo prototype renaming made in the header file
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #undef UARTFIFOLevelGet
+ #define UARTFIFOLevelGet NOROM_UARTFIFOLevelGet
+ #undef UARTConfigSetExpClk
+ #define UARTConfigSetExpClk NOROM_UARTConfigSetExpClk
+ #undef UARTConfigGetExpClk
+ #define UARTConfigGetExpClk NOROM_UARTConfigGetExpClk
+ #undef UARTDisable
+ #define UARTDisable NOROM_UARTDisable
+ #undef UARTCharGetNonBlocking
+ #define UARTCharGetNonBlocking NOROM_UARTCharGetNonBlocking
+ #undef UARTCharGet
+ #define UARTCharGet NOROM_UARTCharGet
+ #undef UARTCharPutNonBlocking
+ #define UARTCharPutNonBlocking NOROM_UARTCharPutNonBlocking
+ #undef UARTCharPut
+ #define UARTCharPut NOROM_UARTCharPut
+ #undef UARTIntRegister
+ #define UARTIntRegister NOROM_UARTIntRegister
+ #undef UARTIntUnregister
+ #define UARTIntUnregister NOROM_UARTIntUnregister
+#endif
+
+//*****************************************************************************
+//
+// Gets the FIFO level at which interrupts are generated
+//
+//*****************************************************************************
+void
+UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel,
+ uint32_t *pui32RxLevel)
+{
+ uint32_t ui32Temp;
+
+ // Check the arguments.
+ ASSERT(UARTBaseValid(ui32Base));
+
+ // Read the FIFO level register.
+ ui32Temp = HWREG(ui32Base + UART_O_IFLS);
+
+ // Extract the transmit and receive FIFO levels.
+ *pui32TxLevel = ui32Temp & UART_IFLS_TXSEL_M;
+ *pui32RxLevel = ui32Temp & UART_IFLS_RXSEL_M;
+}
+
+//*****************************************************************************
+//
+// Sets the configuration of a UART
+//
+//*****************************************************************************
+void
+UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk,
+ uint32_t ui32Baud, uint32_t ui32Config)
+{
+ uint32_t ui32Div;
+
+ // Check the arguments.
+ ASSERT(UARTBaseValid(ui32Base));
+ ASSERT(ui32Baud != 0);
+
+ // Stop the UART.
+ UARTDisable(ui32Base);
+
+ // Compute the fractional baud rate divider.
+ ui32Div = (((ui32UARTClk * 8) / ui32Baud) + 1) / 2;
+
+ // Set the baud rate.
+ HWREG(ui32Base + UART_O_IBRD) = ui32Div / 64;
+ HWREG(ui32Base + UART_O_FBRD) = ui32Div % 64;
+
+ // Set parity, data length, and number of stop bits.
+ HWREG(ui32Base + UART_O_LCRH) = ui32Config;
+}
+
+//*****************************************************************************
+//
+// Gets the current configuration of a UART
+//
+//*****************************************************************************
+void
+UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk,
+ uint32_t *pui32Baud, uint32_t *pui32Config)
+{
+ uint32_t ui32Int, ui32Frac;
+
+ // Check the arguments.
+ ASSERT(UARTBaseValid(ui32Base));
+
+ // Compute the baud rate.
+ ui32Int = HWREG(ui32Base + UART_O_IBRD);
+ ui32Frac = HWREG(ui32Base + UART_O_FBRD);
+ *pui32Baud = (ui32UARTClk * 4) / ((64 * ui32Int) + ui32Frac);
+
+ // Get the parity, data length, and number of stop bits.
+ *pui32Config = (HWREG(ui32Base + UART_O_LCRH) &
+ (UART_LCRH_SPS | UART_LCRH_WLEN_M | UART_LCRH_STP2 |
+ UART_LCRH_EPS | UART_LCRH_PEN));
+}
+
+//*****************************************************************************
+//
+// Disables transmitting and receiving
+//
+//*****************************************************************************
+void
+UARTDisable(uint32_t ui32Base)
+{
+
+ // Check the arguments.
+ ASSERT(UARTBaseValid(ui32Base));
+
+ // Wait for end of TX.
+ while(HWREG(ui32Base + UART_O_FR) & UART_FR_BUSY)
+ {
+ }
+
+ // Disable the FIFO.
+ HWREG(ui32Base + UART_O_LCRH) &= ~(UART_LCRH_FEN);
+
+ // Disable the UART.
+ HWREG(ui32Base + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE |
+ UART_CTL_RXE);
+}
+
+//*****************************************************************************
+//
+// Receives a character from the specified port
+//
+//*****************************************************************************
+int32_t
+UARTCharGetNonBlocking(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(UARTBaseValid(ui32Base));
+
+ // See if there are any characters in the receive FIFO.
+ if(!(HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE))
+ {
+ // Read and return the next character.
+ return(HWREG(ui32Base + UART_O_DR));
+ }
+ else
+ {
+ // There are no characters, so return a failure.
+ return(-1);
+ }
+}
+
+//*****************************************************************************
+//
+// Waits for a character from the specified port
+//
+//*****************************************************************************
+int32_t
+UARTCharGet(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(UARTBaseValid(ui32Base));
+
+ // Wait until a char is available.
+ while(HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE)
+ {
+ }
+
+ // Now get the character.
+ return(HWREG(ui32Base + UART_O_DR));
+}
+
+//*****************************************************************************
+//
+// Sends a character to the specified port
+//
+//*****************************************************************************
+bool
+UARTCharPutNonBlocking(uint32_t ui32Base, uint8_t ui8Data)
+{
+ // Check the arguments.
+ ASSERT(UARTBaseValid(ui32Base));
+
+ // See if there is space in the transmit FIFO.
+ if(!(HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF))
+ {
+ // Write this character to the transmit FIFO.
+ HWREG(ui32Base + UART_O_DR) = ui8Data;
+
+ // Success.
+ return(true);
+ }
+ else
+ {
+ // There is no space in the transmit FIFO, so return a failure.
+ return(false);
+ }
+}
+
+//*****************************************************************************
+//
+// Waits to send a character from the specified port
+//
+//*****************************************************************************
+void
+UARTCharPut(uint32_t ui32Base, uint8_t ui8Data)
+{
+ // Check the arguments.
+ ASSERT(UARTBaseValid(ui32Base));
+
+ // Wait until space is available.
+ while(HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF)
+ {
+ }
+
+ // Send the char.
+ HWREG(ui32Base + UART_O_DR) = ui8Data;
+}
+
+//*****************************************************************************
+//
+// Registers an interrupt handler for a UART interrupt
+//
+//*****************************************************************************
+void
+UARTIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
+{
+ // Check the arguments.
+ ASSERT(UARTBaseValid(ui32Base));
+
+ // Register and enable the interrupt handler.
+ // (Doing the '& 0xFFFF' to catch both buffered and unbufferd offsets)
+ if (( ui32Base & 0xFFFF ) == ( UART0_BASE & 0xFFFF )) {
+ IntRegister(INT_UART0_COMB, pfnHandler);
+ IntEnable(INT_UART0_COMB);
+ } else {
+ IntRegister(INT_UART1_COMB, pfnHandler);
+ IntEnable(INT_UART1_COMB);
+ }
+}
+
+//*****************************************************************************
+//
+// Unregisters an interrupt handler for a UART interrupt
+//
+//*****************************************************************************
+void
+UARTIntUnregister(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(UARTBaseValid(ui32Base));
+
+ // Disable and unregister the interrupt.
+ // (Doing the '& 0xFFFF' to catch both buffered and unbufferd offsets)
+ if (( ui32Base & 0xFFFF ) == ( UART0_BASE & 0xFFFF )) {
+ IntDisable(INT_UART0_COMB);
+ IntUnregister(INT_UART0_COMB);
+ } else {
+ IntDisable(INT_UART1_COMB);
+ IntUnregister(INT_UART1_COMB);
+ }
+}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/uart.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/uart.h
new file mode 100644
index 0000000..82ec130
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/uart.h
@@ -0,0 +1,1097 @@
+/******************************************************************************
+* Filename: uart.h
+* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017)
+* Revision: 49096
+*
+* Description: Defines and prototypes for the UART.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup peripheral_group
+//! @{
+//! \addtogroup uart_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __UART_H__
+#define __UART_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "../inc/hw_types.h"
+#include "../inc/hw_uart.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_ints.h"
+#include "interrupt.h"
+#include "debug.h"
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// This section renames all functions that are not "static inline", so that
+// calling these functions will default to implementation in flash. At the end
+// of this file a second renaming will change the defaults to implementation in
+// ROM for available functions.
+//
+// To force use of the implementation in flash, e.g. for debugging:
+// - Globally: Define DRIVERLIB_NOROM at project level
+// - Per function: Use prefix "NOROM_" when calling the function
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #define UARTFIFOLevelGet NOROM_UARTFIFOLevelGet
+ #define UARTConfigSetExpClk NOROM_UARTConfigSetExpClk
+ #define UARTConfigGetExpClk NOROM_UARTConfigGetExpClk
+ #define UARTDisable NOROM_UARTDisable
+ #define UARTCharGetNonBlocking NOROM_UARTCharGetNonBlocking
+ #define UARTCharGet NOROM_UARTCharGet
+ #define UARTCharPutNonBlocking NOROM_UARTCharPutNonBlocking
+ #define UARTCharPut NOROM_UARTCharPut
+ #define UARTIntRegister NOROM_UARTIntRegister
+ #define UARTIntUnregister NOROM_UARTIntUnregister
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear
+// as the ui32IntFlags parameter, and returned from UARTIntStatus.
+//
+//*****************************************************************************
+#define UART_INT_EOT ( UART_IMSC_EOTIM ) // End Of Transmission Interrupt Mask
+#define UART_INT_OE ( UART_IMSC_OEIM ) // Overrun Error Interrupt Mask
+#define UART_INT_BE ( UART_IMSC_BEIM ) // Break Error Interrupt Mask
+#define UART_INT_PE ( UART_IMSC_PEIM ) // Parity Error Interrupt Mask
+#define UART_INT_FE ( UART_IMSC_FEIM ) // Framing Error Interrupt Mask
+#define UART_INT_RT ( UART_IMSC_RTIM ) // Receive Timeout Interrupt Mask
+#define UART_INT_TX ( UART_IMSC_TXIM ) // Transmit Interrupt Mask
+#define UART_INT_RX ( UART_IMSC_RXIM ) // Receive Interrupt Mask
+#define UART_INT_CTS ( UART_IMSC_CTSMIM ) // CTS Modem Interrupt Mask
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTConfigSetExpClk as the ui32Config parameter
+// and returned by UARTConfigGetExpClk in the pui32Config parameter.
+// Additionally, the UART_CONFIG_PAR_* subset can be passed to
+// UARTParityModeSet as the ui32Parity parameter, and are returned by
+// UARTParityModeGet.
+//
+//*****************************************************************************
+#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length
+#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data
+#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data
+#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data
+#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data
+#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits
+#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit
+#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits
+#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity
+#define UART_CONFIG_PAR_NONE 0x00000000 // No parity
+#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity
+#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity
+#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one
+#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTFIFOLevelSet as the ui32TxLevel parameter
+// and returned by UARTFIFOLevelGet in the pui32TxLevel.
+//
+//*****************************************************************************
+#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full
+#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full
+#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full
+#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full
+#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTFIFOLevelSet as the ui32RxLevel parameter
+// and returned by UARTFIFOLevelGet in the pui32RxLevel.
+//
+//*****************************************************************************
+#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full
+#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full
+#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full
+#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full
+#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTDMAEnable() and UARTDMADisable().
+//
+//*****************************************************************************
+#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error
+#define UART_DMA_TX 0x00000002 // Enable DMA for transmit
+#define UART_DMA_RX 0x00000001 // Enable DMA for receive
+
+//*****************************************************************************
+//
+// Values returned from UARTRxErrorGet().
+//
+//*****************************************************************************
+#define UART_RXERROR_OVERRUN 0x00000008
+#define UART_RXERROR_BREAK 0x00000004
+#define UART_RXERROR_PARITY 0x00000002
+#define UART_RXERROR_FRAMING 0x00000001
+
+//*****************************************************************************
+//
+// Values returned from the UARTBusy().
+//
+//*****************************************************************************
+#define UART_BUSY 0x00000001
+#define UART_IDLE 0x00000000
+
+//*****************************************************************************
+//
+// API Functions and prototypes
+//
+//*****************************************************************************
+
+#ifdef DRIVERLIB_DEBUG
+//*****************************************************************************
+//
+//! \internal
+//!
+//! \brief Checks a UART base address.
+//!
+//! This function determines if a UART port base address is valid.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! \return Returns \c true if the base address is valid and \c false
+//! otherwise.
+//
+//*****************************************************************************
+static bool
+UARTBaseValid(uint32_t ui32Base)
+{
+ return(( ui32Base == UART0_BASE ) || ( ui32Base == UART0_NONBUF_BASE ) ||
+ ( ui32Base == UART1_BASE ) || ( ui32Base == UART1_NONBUF_BASE ) );
+}
+#endif
+
+//*****************************************************************************
+//
+//! \brief Sets the type of parity.
+//!
+//! This function sets the type of parity to use for transmitting and expect
+//! when receiving.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui32Parity specifies the type of parity to use. The last two allow
+//! direct control of the parity bit; it is always either one or zero based on
+//! the mode.
+//! - \ref UART_CONFIG_PAR_NONE
+//! - \ref UART_CONFIG_PAR_EVEN
+//! - \ref UART_CONFIG_PAR_ODD
+//! - \ref UART_CONFIG_PAR_ONE
+//! - \ref UART_CONFIG_PAR_ZERO
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+UARTParityModeSet(uint32_t ui32Base, uint32_t ui32Parity)
+{
+ // Check the arguments.
+ ASSERT(UARTBaseValid(ui32Base));
+ ASSERT((ui32Parity == UART_CONFIG_PAR_NONE) ||
+ (ui32Parity == UART_CONFIG_PAR_EVEN) ||
+ (ui32Parity == UART_CONFIG_PAR_ODD) ||
+ (ui32Parity == UART_CONFIG_PAR_ONE) ||
+ (ui32Parity == UART_CONFIG_PAR_ZERO));
+
+ // Set the parity mode.
+ HWREG(ui32Base + UART_O_LCRH) = ((HWREG(ui32Base + UART_O_LCRH) &
+ ~(UART_LCRH_SPS | UART_LCRH_EPS |
+ UART_LCRH_PEN)) | ui32Parity);
+}
+
+//*****************************************************************************
+//
+//! \brief Gets the type of parity currently being used.
+//!
+//! This function gets the type of parity used for transmitting data and
+//! expected when receiving data.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! \return Returns the current parity settings, specified as one of:
+//! - \ref UART_CONFIG_PAR_NONE
+//! - \ref UART_CONFIG_PAR_EVEN
+//! - \ref UART_CONFIG_PAR_ODD
+//! - \ref UART_CONFIG_PAR_ONE
+//! - \ref UART_CONFIG_PAR_ZERO
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+UARTParityModeGet(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(UARTBaseValid(ui32Base));
+
+ // Return the current parity setting
+ return(HWREG(ui32Base + UART_O_LCRH) &
+ (UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN));
+}
+
+//*****************************************************************************
+//
+//! \brief Sets the FIFO level at which interrupts are generated.
+//!
+//! This function sets the FIFO level at which transmit and receive interrupts
+//! are generated.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui32TxLevel is the transmit FIFO interrupt level, specified as one of:
+//! - \ref UART_FIFO_TX1_8
+//! - \ref UART_FIFO_TX2_8
+//! - \ref UART_FIFO_TX4_8
+//! - \ref UART_FIFO_TX6_8
+//! - \ref UART_FIFO_TX7_8
+//! \param ui32RxLevel is the receive FIFO interrupt level, specified as one of:
+//! - \ref UART_FIFO_RX1_8
+//! - \ref UART_FIFO_RX2_8
+//! - \ref UART_FIFO_RX4_8
+//! - \ref UART_FIFO_RX6_8
+//! - \ref UART_FIFO_RX7_8
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+UARTFIFOLevelSet(uint32_t ui32Base, uint32_t ui32TxLevel,
+ uint32_t ui32RxLevel)
+{
+ // Check the arguments.
+ ASSERT(UARTBaseValid(ui32Base));
+ ASSERT((ui32TxLevel == UART_FIFO_TX1_8) ||
+ (ui32TxLevel == UART_FIFO_TX2_8) ||
+ (ui32TxLevel == UART_FIFO_TX4_8) ||
+ (ui32TxLevel == UART_FIFO_TX6_8) ||
+ (ui32TxLevel == UART_FIFO_TX7_8));
+ ASSERT((ui32RxLevel == UART_FIFO_RX1_8) ||
+ (ui32RxLevel == UART_FIFO_RX2_8) ||
+ (ui32RxLevel == UART_FIFO_RX4_8) ||
+ (ui32RxLevel == UART_FIFO_RX6_8) ||
+ (ui32RxLevel == UART_FIFO_RX7_8));
+
+ // Set the FIFO interrupt levels.
+ HWREG(ui32Base + UART_O_IFLS) = ui32TxLevel | ui32RxLevel;
+}
+
+//*****************************************************************************
+//
+//! \brief Gets the FIFO level at which interrupts are generated.
+//!
+//! This function gets the FIFO level at which transmit and receive interrupts
+//! are generated.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param pui32TxLevel is a pointer to storage for the transmit FIFO level,
+//! returned as one of:
+//! - \ref UART_FIFO_TX1_8
+//! - \ref UART_FIFO_TX2_8
+//! - \ref UART_FIFO_TX4_8
+//! - \ref UART_FIFO_TX6_8
+//! - \ref UART_FIFO_TX7_8
+//! \param pui32RxLevel is a pointer to storage for the receive FIFO level,
+//! returned as one of:
+//! - \ref UART_FIFO_RX1_8
+//! - \ref UART_FIFO_RX2_8
+//! - \ref UART_FIFO_RX4_8
+//! - \ref UART_FIFO_RX6_8
+//! - \ref UART_FIFO_RX7_8
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel,
+ uint32_t *pui32RxLevel);
+
+//*****************************************************************************
+//
+//! \brief Sets the configuration of a UART.
+//!
+//! This function configures the UART for operation in the specified data
+//! format.
+//!
+//! \note The peripheral clock is not necessarily the same as the processor
+//! clock. The frequency of the peripheral clock is set by the system control.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui32UARTClk is the rate of the clock supplied to the UART module.
+//! \param ui32Baud is the desired baud rate.
+//! - Minimum baud rate: ui32Baud >= ceil(ui32UARTClk / 1,048,559.875)
+//! - Maximum baud rate: ui32Baud <= floor(ui32UARTClk / 15.875)
+//! \param ui32Config is the data format for the port.
+//! The parameter is the bitwise OR of three values:
+//! - Number of data bits
+//! - \ref UART_CONFIG_WLEN_8 : 8 data bits per byte.
+//! - \ref UART_CONFIG_WLEN_7 : 7 data bits per byte.
+//! - \ref UART_CONFIG_WLEN_6 : 6 data bits per byte.
+//! - \ref UART_CONFIG_WLEN_5 : 5 data bits per byte.
+//! - Number of stop bits
+//! - \ref UART_CONFIG_STOP_ONE : One stop bit.
+//! - \ref UART_CONFIG_STOP_TWO : Two stop bits.
+//! - Parity
+//! - \ref UART_CONFIG_PAR_NONE
+//! - \ref UART_CONFIG_PAR_EVEN
+//! - \ref UART_CONFIG_PAR_ODD
+//! - \ref UART_CONFIG_PAR_ONE
+//! - \ref UART_CONFIG_PAR_ZERO
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk,
+ uint32_t ui32Baud, uint32_t ui32Config);
+
+//*****************************************************************************
+//
+//! \brief Gets the current configuration of a UART.
+//!
+//! The baud rate and data format for the UART is determined, given an
+//! explicitly provided peripheral clock (hence the ExpClk suffix). The
+//! returned baud rate is the actual baud rate; it may not be the exact baud
+//! rate requested or an "official" baud rate. The data format returned in
+//! \c pui32Config is enumerated the same as the \c ui32Config parameter of
+//! \ref UARTConfigSetExpClk().
+//!
+//! \note The peripheral clock is not necessarily the same as the processor
+//! clock. The frequency of the peripheral clock is set by the system control.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui32UARTClk is the rate of the clock supplied to the UART module.
+//! \param pui32Baud is a pointer to storage for the baud rate.
+//! \param pui32Config is a pointer to storage for the data format.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk,
+ uint32_t *pui32Baud, uint32_t *pui32Config);
+
+//*****************************************************************************
+//
+//! \brief Enables transmitting and receiving.
+//!
+//! This function sets the UARTEN, TXE, and RXE bits, and enables the transmit
+//! and receive FIFOs.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+UARTEnable(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(UARTBaseValid(ui32Base));
+
+ // Enable the FIFO.
+ HWREG(ui32Base + UART_O_LCRH) |= UART_LCRH_FEN;
+
+ // Enable RX, TX, and the UART.
+ HWREG(ui32Base + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE |
+ UART_CTL_RXE);
+}
+
+//*****************************************************************************
+//
+//! \brief Disables transmitting and receiving.
+//!
+//! This function clears the UARTEN, TXE, and RXE bits, waits for the end of
+//! transmission of the current character, and flushes the transmit FIFO.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void UARTDisable(uint32_t ui32Base);
+
+//*****************************************************************************
+//
+//! \brief Enables the transmit and receive FIFOs.
+//!
+//! This functions enables the transmit and receive FIFOs in the UART.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+UARTFIFOEnable(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(UARTBaseValid(ui32Base));
+
+ // Enable the FIFO.
+ HWREG(ui32Base + UART_O_LCRH) |= UART_LCRH_FEN;
+}
+
+//*****************************************************************************
+//
+//! \brief Disables the transmit and receive FIFOs.
+//!
+//! This functions disables the transmit and receive FIFOs in the UART.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+UARTFIFODisable(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(UARTBaseValid(ui32Base));
+
+ // Disable the FIFO.
+ HWREG(ui32Base + UART_O_LCRH) &= ~(UART_LCRH_FEN);
+}
+
+//*****************************************************************************
+//
+//! \brief Determines if there are any characters in the receive FIFO.
+//!
+//! This function returns a flag indicating whether or not there is data
+//! available in the receive FIFO.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! \return Returns status of the receive FIFO.
+//! - \c true : There is data in the receive FIFO.
+//! - \c false : There is no data in the receive FIFO.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+UARTCharsAvail(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(UARTBaseValid(ui32Base));
+
+ // Return the availability of characters.
+ return((HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE) ? false : true);
+}
+
+//*****************************************************************************
+//
+//! \brief Determines if there is any space in the transmit FIFO.
+//!
+//! This function returns a flag indicating whether or not there is space
+//! available in the transmit FIFO.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! \return Returns status of the transmit FIFO.
+//! - \c true : There is space available in the transmit FIFO.
+//! - \c false : There is no space available in the transmit FIFO.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+UARTSpaceAvail(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(UARTBaseValid(ui32Base));
+
+ // Return the availability of space.
+ return((HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF) ? false : true);
+}
+
+//*****************************************************************************
+//
+//! \brief Receives a character from the specified port.
+//!
+//! This function gets a character from the receive FIFO for the specified
+//! port.
+//!
+//! \note The \ref UARTCharsAvail() function should be called before
+//! attempting to call this function.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! \return Returns the character read from the specified port, cast as an
+//! \c int32_t. A \c -1 is returned if there are no characters present in the
+//! receive FIFO.
+//!
+//! \sa \ref UARTCharsAvail()
+//
+//*****************************************************************************
+extern int32_t UARTCharGetNonBlocking(uint32_t ui32Base);
+
+//*****************************************************************************
+//
+//! \brief Waits for a character from the specified port.
+//!
+//! This function gets a character from the receive FIFO for the specified
+//! port. If there are no characters available, this function waits until a
+//! character is received before returning.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! \return Returns the character read from the specified port, cast as an
+//! \c int32_t.
+//
+//*****************************************************************************
+extern int32_t UARTCharGet(uint32_t ui32Base);
+
+//*****************************************************************************
+//
+//! \brief Sends a character to the specified port.
+//!
+//! This function writes the character \c ui8Data to the transmit FIFO for the
+//! specified port. This function does not block, so if there is no space
+//! available, then a \c false is returned, and the application must retry the
+//! function later.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui8Data is the character to be transmitted.
+//!
+//! \return Returns status of the character transmit.
+//! - \c true : The character was successfully placed in the transmit FIFO.
+//! - \c false : There was no space available in the transmit FIFO. Try again later.
+//
+//*****************************************************************************
+extern bool UARTCharPutNonBlocking(uint32_t ui32Base, uint8_t ui8Data);
+
+//*****************************************************************************
+//
+//! \brief Waits to send a character from the specified port.
+//!
+//! This function sends the character \c ui8Data to the transmit FIFO for the
+//! specified port. If there is no space available in the transmit FIFO, this
+//! function waits until there is space available before returning.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui8Data is the character to be transmitted.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void UARTCharPut(uint32_t ui32Base, uint8_t ui8Data);
+
+//*****************************************************************************
+//
+//! \brief Determines whether the UART transmitter is busy or not.
+//!
+//! Allows the caller to determine whether all transmitted bytes have cleared
+//! the transmitter hardware. If \c false is returned, the transmit FIFO is
+//! empty and all bits of the last transmitted character, including all stop
+//! bits, have left the hardware shift register.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! \return Returns status of UART transmitter.
+//! - \c true : UART is transmitting.
+//! - \c false : All transmissions are complete.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+UARTBusy(uint32_t ui32Base)
+{
+ // Check the argument.
+ ASSERT(UARTBaseValid(ui32Base));
+
+ // Determine if the UART is busy.
+ return((HWREG(ui32Base + UART_O_FR) & UART_FR_BUSY) ?
+ UART_BUSY : UART_IDLE);
+}
+
+//*****************************************************************************
+//
+//! \brief Causes a BREAK to be sent.
+//!
+//! \note For proper transmission of a break
+//! command, the break must be asserted for at least two complete frames.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param bBreakState controls the output level.
+//! - \c true : Asserts a break condition on the UART.
+//! - \c false : Removes the break condition.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+UARTBreakCtl(uint32_t ui32Base, bool bBreakState)
+{
+ // Check the arguments.
+ ASSERT(UARTBaseValid(ui32Base));
+
+ // Set the break condition as requested.
+ HWREG(ui32Base + UART_O_LCRH) =
+ (bBreakState ?
+ (HWREG(ui32Base + UART_O_LCRH) | UART_LCRH_BRK) :
+ (HWREG(ui32Base + UART_O_LCRH) & ~(UART_LCRH_BRK)));
+}
+
+//*****************************************************************************
+//
+//! \brief Registers an interrupt handler for a UART interrupt in the dynamic interrupt table.
+//!
+//! \note Only use this function if you want to use the dynamic vector table (in SRAM)!
+//!
+//! This function registers a function as the interrupt handler for a specific
+//! interrupt and enables the corresponding interrupt in the interrupt controller.
+//!
+//! Specific UART interrupts must be enabled via \ref UARTIntEnable(). It is the
+//! interrupt handler's responsibility to clear the interrupt source.
+//!
+//! \param ui32Base is the base address of the UART module.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! UART interrupt occurs.
+//!
+//! \return None
+//!
+//! \sa \ref IntRegister() for important information about registering interrupt
+//! handlers.
+//
+//*****************************************************************************
+extern void UARTIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
+
+//*****************************************************************************
+//
+//! \brief Unregisters an interrupt handler for a UART interrupt in the dynamic interrupt table.
+//!
+//! This function does the actual unregistering of the interrupt handler. It
+//! clears the handler to be called when a UART interrupt occurs. This
+//! function also masks off the interrupt in the interrupt controller so that
+//! the interrupt handler no longer is called.
+//!
+//! \param ui32Base is the base address of the UART module.
+//!
+//! \return None
+//!
+//! \sa \ref IntRegister() for important information about registering interrupt
+//! handlers.
+//
+//*****************************************************************************
+extern void UARTIntUnregister(uint32_t ui32Base);
+
+//*****************************************************************************
+//
+//! \brief Enables individual UART interrupt sources.
+//!
+//! This function enables the indicated UART interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled.
+//! The parameter is the bitwise OR of any of the following:
+//! - \ref UART_INT_EOT : End Of Transmission interrupt.
+//! - \ref UART_INT_OE : Overrun Error interrupt.
+//! - \ref UART_INT_BE : Break Error interrupt.
+//! - \ref UART_INT_PE : Parity Error interrupt.
+//! - \ref UART_INT_FE : Framing Error interrupt.
+//! - \ref UART_INT_RT : Receive Timeout interrupt.
+//! - \ref UART_INT_TX : Transmit interrupt.
+//! - \ref UART_INT_RX : Receive interrupt.
+//! - \ref UART_INT_CTS : CTS interrupt.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+UARTIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ // Check the arguments.
+ ASSERT(UARTBaseValid(ui32Base));
+
+ // Enable the specified interrupts.
+ HWREG(ui32Base + UART_O_IMSC) |= ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! \brief Disables individual UART interrupt sources.
+//!
+//! This function disables the indicated UART interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled.
+//! - \ref UART_INT_EOT : End Of Transmission interrupt.
+//! - \ref UART_INT_OE : Overrun Error interrupt.
+//! - \ref UART_INT_BE : Break Error interrupt.
+//! - \ref UART_INT_PE : Parity Error interrupt.
+//! - \ref UART_INT_FE : Framing Error interrupt.
+//! - \ref UART_INT_RT : Receive Timeout interrupt.
+//! - \ref UART_INT_TX : Transmit interrupt.
+//! - \ref UART_INT_RX : Receive interrupt.
+//! - \ref UART_INT_CTS : CTS interrupt.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+UARTIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ // Check the arguments.
+ ASSERT(UARTBaseValid(ui32Base));
+
+ // Disable the specified interrupts.
+ HWREG(ui32Base + UART_O_IMSC) &= ~(ui32IntFlags);
+}
+
+//*****************************************************************************
+//
+//! \brief Gets the current interrupt status.
+//!
+//! This function returns the interrupt status for the specified UART. Either
+//! the raw interrupt status or the status of interrupts that are allowed to
+//! reflect to the processor can be returned.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param bMasked selects either raw or masked interrupt.
+//! - \c true : Masked interrupt status is required.
+//! - \c false : Raw interrupt status is required.
+//!
+//! \return Returns the current interrupt status, enumerated as a bit field of:
+//! - \ref UART_INT_EOT : End Of Transmission interrupt.
+//! - \ref UART_INT_OE : Overrun Error interrupt.
+//! - \ref UART_INT_BE : Break Error interrupt.
+//! - \ref UART_INT_PE : Parity Error interrupt.
+//! - \ref UART_INT_FE : Framing Error interrupt.
+//! - \ref UART_INT_RT : Receive Timeout interrupt.
+//! - \ref UART_INT_TX : Transmit interrupt.
+//! - \ref UART_INT_RX : Receive interrupt.
+//! - \ref UART_INT_CTS : CTS interrupt.
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+UARTIntStatus(uint32_t ui32Base, bool bMasked)
+{
+ // Check the arguments.
+ ASSERT(UARTBaseValid(ui32Base));
+
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ if(bMasked)
+ {
+ return(HWREG(ui32Base + UART_O_MIS));
+ }
+ else
+ {
+ return(HWREG(ui32Base + UART_O_RIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! \brief Clears UART interrupt sources.
+//!
+//! The specified UART interrupt sources are cleared, so that they no longer
+//! assert. This function must be called in the interrupt handler to keep the
+//! interrupt from being recognized again immediately upon exit.
+//!
+//! \note Due to write buffers and synchronizers in the system it may take several
+//! clock cycles from a register write clearing an event in a module and until the
+//! event is actually cleared in the NVIC of the system CPU. It is recommended to
+//! clear the event source early in the interrupt service routine (ISR) to allow
+//! the event clear to propagate to the NVIC before returning from the ISR.
+//! At the same time, an early event clear allows new events of the same type to be
+//! pended instead of ignored if the event is cleared later in the ISR.
+//! It is the responsibility of the programmer to make sure that enough time has passed
+//! before returning from the ISR to avoid false re-triggering of the cleared event.
+//! A simple, although not necessarily optimal, way of clearing an event before
+//! returning from the ISR is:
+//! -# Write to clear event (interrupt source). (buffered write)
+//! -# Dummy read from the event source module. (making sure the write has propagated)
+//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers)
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared.
+//! - \ref UART_INT_EOT : End Of Transmission interrupt.
+//! - \ref UART_INT_OE : Overrun Error interrupt.
+//! - \ref UART_INT_BE : Break Error interrupt.
+//! - \ref UART_INT_PE : Parity Error interrupt.
+//! - \ref UART_INT_FE : Framing Error interrupt.
+//! - \ref UART_INT_RT : Receive Timeout interrupt.
+//! - \ref UART_INT_TX : Transmit interrupt.
+//! - \ref UART_INT_RX : Receive interrupt.
+//! - \ref UART_INT_CTS : CTS interrupt.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+UARTIntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ // Check the arguments
+ ASSERT(UARTBaseValid(ui32Base));
+
+ // Clear the requested interrupt sources
+ HWREG(ui32Base + UART_O_ICR) = ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! \brief Enable UART DMA operation.
+//!
+//! The specified UART DMA features are enabled. The UART can be
+//! configured to use DMA for transmit or receive, and to disable
+//! receive if an error occurs.
+//!
+//! \note The uDMA controller must also be set up before DMA can be used
+//! with the UART.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui32DMAFlags is a bit mask of the DMA features to enable.
+//! The parameter is the bitwise OR of any of the following values:
+//! - UART_DMA_RX : Enable DMA for receive.
+//! - UART_DMA_TX : Enable DMA for transmit.
+//! - UART_DMA_ERR_RXSTOP : Disable DMA receive on UART error.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+UARTDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags)
+{
+ // Check the arguments.
+ ASSERT(UARTBaseValid(ui32Base));
+
+ // Set the requested bits in the UART DMA control register.
+ HWREG(ui32Base + UART_O_DMACTL) |= ui32DMAFlags;
+}
+
+//*****************************************************************************
+//
+//! \brief Disable UART DMA operation.
+//!
+//! This function is used to disable UART DMA features that were enabled
+//! by \ref UARTDMAEnable(). The specified UART DMA features are disabled.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui32DMAFlags is a bit mask of the DMA features to disable.
+//! The parameter is the bitwise OR of any of the following values:
+//! - UART_DMA_RX : Enable DMA for receive.
+//! - UART_DMA_TX : Enable DMA for transmit.
+//! - UART_DMA_ERR_RXSTOP : Disable DMA receive on UART error.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+UARTDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags)
+{
+ // Check the arguments.
+ ASSERT(UARTBaseValid(ui32Base));
+
+ // Clear the requested bits in the UART DMA control register.
+ HWREG(ui32Base + UART_O_DMACTL) &= ~ui32DMAFlags;
+}
+
+//*****************************************************************************
+//
+//! \brief Gets current receiver errors.
+//!
+//! This function returns the current state of each of the 4 receiver error
+//! sources. The returned errors are equivalent to the four error bits
+//! returned via the previous call to \ref UARTCharGet() or \ref UARTCharGetNonBlocking()
+//! with the exception that the overrun error is set immediately the overrun
+//! occurs rather than when a character is next read.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! \return Returns a bitwise OR combination of the receiver error flags:
+//! - \ref UART_RXERROR_FRAMING
+//! - \ref UART_RXERROR_PARITY
+//! - \ref UART_RXERROR_BREAK
+//! - \ref UART_RXERROR_OVERRUN
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+UARTRxErrorGet(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(UARTBaseValid(ui32Base));
+
+ // Return the current value of the receive status register.
+ return(HWREG(ui32Base + UART_O_RSR) & 0x0000000F);
+}
+
+//*****************************************************************************
+//
+//! \brief Clears all reported receiver errors.
+//!
+//! This function is used to clear all receiver error conditions reported via
+//! \ref UARTRxErrorGet(). If using the overrun, framing error, parity error or
+//! break interrupts, this function must be called after clearing the interrupt
+//! to ensure that later errors of the same type trigger another interrupt.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+UARTRxErrorClear(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(UARTBaseValid(ui32Base));
+
+ // Any write to the Error Clear Register will clear all bits which are
+ // currently set.
+ HWREG(ui32Base + UART_O_ECR) = 0;
+}
+
+//*****************************************************************************
+//
+//! \brief Enables hardware flow control for both CTS and RTS
+//!
+//! Hardware flow control is disabled by default.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+UARTHwFlowControlEnable( uint32_t ui32Base )
+{
+ // Check the arguments.
+ ASSERT( UARTBaseValid( ui32Base ));
+
+ HWREG( ui32Base + UART_O_CTL ) |= ( UART_CTL_CTSEN | UART_CTL_RTSEN );
+}
+
+//*****************************************************************************
+//
+//! \brief Disables hardware flow control for both CTS and RTS
+//!
+//! Hardware flow control is disabled by default.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+UARTHwFlowControlDisable( uint32_t ui32Base )
+{
+ // Check the arguments.
+ ASSERT( UARTBaseValid( ui32Base ));
+
+ HWREG( ui32Base + UART_O_CTL ) &= ~( UART_CTL_CTSEN | UART_CTL_RTSEN );
+}
+
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// Redirect to implementation in ROM when available.
+//
+//*****************************************************************************
+#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
+ #include "../driverlib/rom.h"
+ #ifdef ROM_UARTFIFOLevelGet
+ #undef UARTFIFOLevelGet
+ #define UARTFIFOLevelGet ROM_UARTFIFOLevelGet
+ #endif
+ #ifdef ROM_UARTConfigSetExpClk
+ #undef UARTConfigSetExpClk
+ #define UARTConfigSetExpClk ROM_UARTConfigSetExpClk
+ #endif
+ #ifdef ROM_UARTConfigGetExpClk
+ #undef UARTConfigGetExpClk
+ #define UARTConfigGetExpClk ROM_UARTConfigGetExpClk
+ #endif
+ #ifdef ROM_UARTDisable
+ #undef UARTDisable
+ #define UARTDisable ROM_UARTDisable
+ #endif
+ #ifdef ROM_UARTCharGetNonBlocking
+ #undef UARTCharGetNonBlocking
+ #define UARTCharGetNonBlocking ROM_UARTCharGetNonBlocking
+ #endif
+ #ifdef ROM_UARTCharGet
+ #undef UARTCharGet
+ #define UARTCharGet ROM_UARTCharGet
+ #endif
+ #ifdef ROM_UARTCharPutNonBlocking
+ #undef UARTCharPutNonBlocking
+ #define UARTCharPutNonBlocking ROM_UARTCharPutNonBlocking
+ #endif
+ #ifdef ROM_UARTCharPut
+ #undef UARTCharPut
+ #define UARTCharPut ROM_UARTCharPut
+ #endif
+ #ifdef ROM_UARTIntRegister
+ #undef UARTIntRegister
+ #define UARTIntRegister ROM_UARTIntRegister
+ #endif
+ #ifdef ROM_UARTIntUnregister
+ #undef UARTIntUnregister
+ #define UARTIntUnregister ROM_UARTIntUnregister
+ #endif
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __UART_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/uart_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/uart_doc.h
new file mode 100644
index 0000000..e239428
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/uart_doc.h
@@ -0,0 +1,107 @@
+/******************************************************************************
+* Filename: uart_doc.h
+* Revised: 2018-02-09 15:45:36 +0100 (fr, 09 feb 2018)
+* Revision: 51470
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+/*!
+\addtogroup uart_api
+@{
+
+\section sec_uart_printf Use printf()
+
+DriverLib only supports writing a single character at a time to the UART buffer but it is
+possible to utilize the library function \c printf by overriding a few of the functions used by
+\c printf with a device specific definition. However, the implementation of \c printf is
+compiler specific and requires different functions to be overridden depending on the compiler.
+
+Using \c printf can increase code size significantly but some compilers provide a highly optimized
+and configurable implementation suitable for embedded systems which makes the code size increase
+acceptable for most applications. See the compiler's documentation for details about how to
+configure the \c printf library function.
+
+It is required that the application configures and enables the UART module before using \c printf
+function.
+
+\subsection sec_uart_printf_ccs Code Composer Studio
+
+In Code Composer Studio the functions \c fputc and \c fputs must be overridden.
+
+\code{.c}
+#include <stdio.h>
+#include <string.h>
+
+#define PRINTF_UART UART0_BASE
+
+// Override 'fputc' function in order to use printf() to output to UART
+int fputc(int _c, register FILE *_fp)
+{
+ UARTCharPut(PRINTF_UART, (uint8_t)_c);
+ return _c;
+}
+
+// Override 'fputs' function in order to use printf() to output to UART
+int fputs(const char *_ptr, register FILE *_fp)
+{
+ unsigned int i, len;
+
+ len = strlen(_ptr);
+
+ for(i=0 ; i<len ; i++)
+ {
+ UARTCharPut(PRINTF_UART, (uint8_t)_ptr[i]);
+ }
+
+ return len;
+}
+\endcode
+
+\subsection sec_uart_printf_iar IAR
+
+In IAR the function \c putchar must be overridden.
+
+\code{.c}
+#include <stdio.h>
+#include <string.h>
+
+#define PRINTF_UART UART0_BASE
+
+// Override 'putchar' function in order to use printf() to output to UART.
+int putchar(int data)
+{
+ UARTCharPut(PRINTF_UART, (uint8_t)data);
+ return data;
+}
+\endcode
+
+@}
+*/
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/udma.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/udma.c
new file mode 100644
index 0000000..32807e1
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/udma.c
@@ -0,0 +1,448 @@
+/******************************************************************************
+* Filename: udma.c
+* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017)
+* Revision: 48852
+*
+* Description: Driver for the uDMA controller
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "udma.h"
+
+//*****************************************************************************
+//
+// Handle support for DriverLib in ROM:
+// This section will undo prototype renaming made in the header file
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #undef uDMAChannelAttributeEnable
+ #define uDMAChannelAttributeEnable NOROM_uDMAChannelAttributeEnable
+ #undef uDMAChannelAttributeDisable
+ #define uDMAChannelAttributeDisable NOROM_uDMAChannelAttributeDisable
+ #undef uDMAChannelAttributeGet
+ #define uDMAChannelAttributeGet NOROM_uDMAChannelAttributeGet
+ #undef uDMAChannelControlSet
+ #define uDMAChannelControlSet NOROM_uDMAChannelControlSet
+ #undef uDMAChannelTransferSet
+ #define uDMAChannelTransferSet NOROM_uDMAChannelTransferSet
+ #undef uDMAChannelScatterGatherSet
+ #define uDMAChannelScatterGatherSet NOROM_uDMAChannelScatterGatherSet
+ #undef uDMAChannelSizeGet
+ #define uDMAChannelSizeGet NOROM_uDMAChannelSizeGet
+ #undef uDMAChannelModeGet
+ #define uDMAChannelModeGet NOROM_uDMAChannelModeGet
+#endif
+
+//*****************************************************************************
+//
+// Enables attributes of a uDMA channel
+//
+//*****************************************************************************
+void
+uDMAChannelAttributeEnable(uint32_t ui32Base, uint32_t ui32ChannelNum,
+ uint32_t ui32Attr)
+{
+ // Check the arguments.
+ ASSERT(uDMABaseValid(ui32Base));
+ ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS);
+ ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT |
+ UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0);
+
+ // Set the useburst bit for this channel if set in ui32Attr.
+ if(ui32Attr & UDMA_ATTR_USEBURST)
+ {
+ HWREG(ui32Base + UDMA_O_SETBURST) = 1 << ui32ChannelNum;
+ }
+
+ // Set the alternate control select bit for this channel,
+ // if set in ui32Attr.
+ if(ui32Attr & UDMA_ATTR_ALTSELECT)
+ {
+ HWREG(ui32Base + UDMA_O_SETCHNLPRIALT) = 1 << ui32ChannelNum;
+ }
+
+ // Set the high priority bit for this channel, if set in ui32Attr.
+ if(ui32Attr & UDMA_ATTR_HIGH_PRIORITY)
+ {
+ HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) = 1 << ui32ChannelNum;
+ }
+
+ // Set the request mask bit for this channel, if set in ui32Attr.
+ if(ui32Attr & UDMA_ATTR_REQMASK)
+ {
+ HWREG(ui32Base + UDMA_O_SETREQMASK) = 1 << ui32ChannelNum;
+ }
+}
+
+//*****************************************************************************
+//
+// Disables attributes of an uDMA channel
+//
+//*****************************************************************************
+void
+uDMAChannelAttributeDisable(uint32_t ui32Base, uint32_t ui32ChannelNum,
+ uint32_t ui32Attr)
+{
+ // Check the arguments.
+ ASSERT(uDMABaseValid(ui32Base));
+ ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS);
+ ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT |
+ UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0);
+
+ // Clear the useburst bit for this channel if set in ui32Attr.
+ if(ui32Attr & UDMA_ATTR_USEBURST)
+ {
+ HWREG(ui32Base + UDMA_O_CLEARBURST) = 1 << ui32ChannelNum;
+ }
+
+ // Clear the alternate control select bit for this channel, if set in
+ // ululAttr.
+ if(ui32Attr & UDMA_ATTR_ALTSELECT)
+ {
+ HWREG(ui32Base + UDMA_O_CLEARCHNLPRIALT) = 1 << ui32ChannelNum;
+ }
+
+ // Clear the high priority bit for this channel, if set in ui32Attr.
+ if(ui32Attr & UDMA_ATTR_HIGH_PRIORITY)
+ {
+ HWREG(ui32Base + UDMA_O_CLEARCHNLPRIORITY) = 1 << ui32ChannelNum;
+ }
+
+ // Clear the request mask bit for this channel, if set in ui32Attr.
+ if(ui32Attr & UDMA_ATTR_REQMASK)
+ {
+ HWREG(ui32Base + UDMA_O_CLEARREQMASK) = 1 << ui32ChannelNum;
+ }
+}
+
+//*****************************************************************************
+//
+// Gets the enabled attributes of a uDMA channel
+//
+//*****************************************************************************
+uint32_t
+uDMAChannelAttributeGet(uint32_t ui32Base, uint32_t ui32ChannelNum)
+{
+ uint32_t ui32Attr = 0;
+
+ // Check the arguments.
+ ASSERT(uDMABaseValid(ui32Base));
+ ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS);
+
+ // Check to see if useburst bit is set for this channel.
+ if(HWREG(ui32Base + UDMA_O_SETBURST) & (1 << ui32ChannelNum))
+ {
+ ui32Attr |= UDMA_ATTR_USEBURST;
+ }
+
+ // Check to see if the alternate control bit is set for this channel.
+ if(HWREG(ui32Base + UDMA_O_SETCHNLPRIALT) & (1 << ui32ChannelNum))
+ {
+ ui32Attr |= UDMA_ATTR_ALTSELECT;
+ }
+
+ // Check to see if the high priority bit is set for this channel.
+ if(HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) & (1 << ui32ChannelNum))
+ {
+ ui32Attr |= UDMA_ATTR_HIGH_PRIORITY;
+ }
+
+ // Check to see if the request mask bit is set for this channel.
+ if(HWREG(ui32Base + UDMA_O_SETREQMASK) & (1 << ui32ChannelNum))
+ {
+ ui32Attr |= UDMA_ATTR_REQMASK;
+ }
+
+ // Return the configuration flags.
+ return(ui32Attr);
+}
+
+//*****************************************************************************
+//
+// Sets the control parameters for a uDMA channel control structure
+//
+//*****************************************************************************
+void
+uDMAChannelControlSet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex,
+ uint32_t ui32Control)
+{
+ tDMAControlTable *pControlTable;
+
+ // Check the arguments.
+ ASSERT(uDMABaseValid(ui32Base));
+ ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2));
+ ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0);
+
+ // Get the base address of the control table.
+ pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL);
+
+ // Get the current control word value and mask off the fields to be
+ // changed, then OR in the new settings.
+ pControlTable[ui32ChannelStructIndex].ui32Control =
+ ((pControlTable[ui32ChannelStructIndex].ui32Control &
+ ~(UDMA_DST_INC_M |
+ UDMA_SRC_INC_M |
+ UDMA_SIZE_M |
+ UDMA_ARB_M |
+ UDMA_NEXT_USEBURST)) |
+ ui32Control);
+}
+
+//*****************************************************************************
+//
+// Sets the transfer parameters for a uDMA channel control structure
+//
+//*****************************************************************************
+void
+uDMAChannelTransferSet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex,
+ uint32_t ui32Mode, void *pvSrcAddr, void *pvDstAddr,
+ uint32_t ui32TransferSize)
+{
+ tDMAControlTable *pControlTable;
+ uint32_t ui32Control;
+ uint32_t ui32Inc;
+ uint32_t ui32BufferBytes;
+
+ // Check the arguments.
+ ASSERT(uDMABaseValid(ui32Base));
+ ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2));
+ ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0);
+ ASSERT(ui32Mode <= UDMA_MODE_PER_SCATTER_GATHER);
+ ASSERT((uint32_t)pvSrcAddr >= SRAM_BASE);
+ ASSERT((uint32_t)pvDstAddr >= SRAM_BASE);
+ ASSERT((ui32TransferSize != 0) && (ui32TransferSize <= UDMA_XFER_SIZE_MAX));
+
+ // Get the base address of the control table.
+ pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL);
+
+ // Get the current control word value and mask off the mode and size
+ // fields.
+ ui32Control = (pControlTable[ui32ChannelStructIndex].ui32Control &
+ ~(UDMA_XFER_SIZE_M | UDMA_MODE_M));
+
+ // Adjust the mode if the alt control structure is selected.
+ if(ui32ChannelStructIndex & UDMA_ALT_SELECT)
+ {
+ if((ui32Mode == UDMA_MODE_MEM_SCATTER_GATHER) ||
+ (ui32Mode == UDMA_MODE_PER_SCATTER_GATHER))
+ {
+ ui32Mode |= UDMA_MODE_ALT_SELECT;
+ }
+ }
+
+ // Set the transfer size and mode in the control word (but don't write the
+ // control word yet as it could kick off a transfer).
+ ui32Control |= ui32Mode | ((ui32TransferSize - 1) << UDMA_XFER_SIZE_S);
+
+ // Get the address increment value for the source, from the control word.
+ ui32Inc = (ui32Control & UDMA_SRC_INC_M);
+
+ // Compute the ending source address of the transfer. If the source
+ // increment is set to none, then the ending address is the same as the
+ // beginning.
+ if(ui32Inc != UDMA_SRC_INC_NONE)
+ {
+ ui32Inc = ui32Inc >> UDMA_SRC_INC_S;
+ ui32BufferBytes = ui32TransferSize << ui32Inc;
+ pvSrcAddr = (void *)((uint32_t)pvSrcAddr + ui32BufferBytes - (1 << ui32Inc));
+ }
+
+ // Load the source ending address into the control block.
+ pControlTable[ui32ChannelStructIndex].pvSrcEndAddr = pvSrcAddr;
+
+ // Get the address increment value for the destination, from the control
+ // word.
+ ui32Inc = ui32Control & UDMA_DST_INC_M;
+
+ // Compute the ending destination address of the transfer. If the
+ // destination increment is set to none, then the ending address is the
+ // same as the beginning.
+ if(ui32Inc != UDMA_DST_INC_NONE)
+ {
+ // There is a special case if this is setting up a scatter-gather
+ // transfer. The destination pointer needs to point to the end of
+ // the alternate structure for this channel instead of calculating
+ // the end of the buffer in the normal way.
+ if((ui32Mode == UDMA_MODE_MEM_SCATTER_GATHER) ||
+ (ui32Mode == UDMA_MODE_PER_SCATTER_GATHER))
+ {
+ pvDstAddr =
+ (void *)&pControlTable[ui32ChannelStructIndex |
+ UDMA_ALT_SELECT].ui32Spare;
+ }
+ // Not a scatter-gather transfer, calculate end pointer normally.
+ else
+ {
+ ui32Inc = ui32Inc >> UDMA_DST_INC_S;
+ ui32BufferBytes = ui32TransferSize << ui32Inc;
+ pvDstAddr = (void *)((uint32_t)pvDstAddr + ui32BufferBytes - 1);
+ }
+ }
+
+ // Load the destination ending address into the control block.
+ pControlTable[ui32ChannelStructIndex].pvDstEndAddr = pvDstAddr;
+
+ // Write the new control word value.
+ pControlTable[ui32ChannelStructIndex].ui32Control = ui32Control;
+}
+
+//*****************************************************************************
+//
+// Configures a uDMA channel for scatter-gather mode
+//
+//*****************************************************************************
+void
+uDMAChannelScatterGatherSet(uint32_t ui32Base, uint32_t ui32ChannelNum,
+ uint32_t ui32TaskCount, void *pvTaskList,
+ uint32_t ui32IsPeriphSG)
+{
+ tDMAControlTable *pControlTable;
+ tDMAControlTable *pTaskTable;
+
+ // Check the parameters.
+ ASSERT(uDMABaseValid(ui32Base));
+ ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS);
+ ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0);
+ ASSERT(pvTaskList != 0);
+ ASSERT(ui32TaskCount <= UDMA_XFER_SIZE_MAX);
+ ASSERT(ui32TaskCount != 0);
+
+ // Get the base address of the control table.
+ pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL);
+
+ // Get a handy pointer to the task list.
+ pTaskTable = (tDMAControlTable *)pvTaskList;
+
+ // Compute the ending address for the source pointer. This will be the
+ // last element of the last task in the task table.
+ pControlTable[ui32ChannelNum].pvSrcEndAddr =
+ &pTaskTable[ui32TaskCount - 1].ui32Spare;
+
+ // Compute the ending address for the destination pointer. This will be
+ // the end of the alternate structure for this channel.
+ pControlTable[ui32ChannelNum].pvDstEndAddr =
+ &pControlTable[ui32ChannelNum | UDMA_ALT_SELECT].ui32Spare;
+
+ // Compute the control word. Most configurable items are fixed for
+ // scatter-gather. Item and increment sizes are all 32-bit and arb
+ // size must be 4. The count is the number of items in the task list
+ // times 4 (4 words per task).
+ pControlTable[ui32ChannelNum].ui32Control =
+ (UDMA_DST_INC_32 | UDMA_SRC_INC_32 |
+ UDMA_SIZE_32 | UDMA_ARB_4 |
+ (((ui32TaskCount * 4) - 1) << UDMA_XFER_SIZE_S) |
+ (ui32IsPeriphSG ? UDMA_MODE_PER_SCATTER_GATHER :
+ UDMA_MODE_MEM_SCATTER_GATHER));
+
+ // Scatter-gather operations can leave the alt bit set. So if doing
+ // back to back scatter-gather transfers, the second attempt may not
+ // work correctly because the alt bit is set. Therefore, clear the
+ // alt bit here to ensure that it is always cleared before a new SG
+ // transfer is started.
+ HWREG(ui32Base + UDMA_O_CLEARCHNLPRIALT) = 1 << ui32ChannelNum;
+
+}
+
+//*****************************************************************************
+//
+// Gets the current transfer size for a uDMA channel control structure
+//
+//*****************************************************************************
+uint32_t
+uDMAChannelSizeGet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)
+{
+ tDMAControlTable *pControlTable;
+ uint32_t ui32Control;
+
+ // Check the arguments.
+ ASSERT(uDMABaseValid(ui32Base));
+ ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2));
+ ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0);
+
+ // Get the base address of the control table.
+ pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL);
+
+ // Get the current control word value and mask off all but the size field
+ // and the mode field.
+ ui32Control = (pControlTable[ui32ChannelStructIndex].ui32Control &
+ (UDMA_XFER_SIZE_M | UDMA_MODE_M));
+
+ // If the size field and mode field are 0 then the transfer is finished
+ // and there are no more items to transfer.
+ if(ui32Control == 0)
+ {
+ return(0);
+ }
+
+ // Otherwise, if either the size field or more field is non-zero, then
+ // not all the items have been transferred.
+ else
+ {
+ // Shift the size field and add one, then return to user.
+ return((ui32Control >> UDMA_XFER_SIZE_S) + 1);
+ }
+}
+
+//*****************************************************************************
+//
+// Gets the transfer mode for a uDMA channel control structure
+//
+//*****************************************************************************
+uint32_t
+uDMAChannelModeGet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)
+{
+ tDMAControlTable *pControlTable;
+ uint32_t ui32Control;
+
+ // Check the arguments.
+ ASSERT(uDMABaseValid(ui32Base));
+ ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2));
+ ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0);
+
+ // Get the base address of the control table.
+ pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL);
+
+ // Get the current control word value and mask off all but the mode field.
+ ui32Control = (pControlTable[ui32ChannelStructIndex].ui32Control &
+ UDMA_MODE_M);
+
+ // Check if scatter/gather mode, and if so, mask off the alt bit.
+ if(((ui32Control & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_MEM_SCATTER_GATHER) ||
+ ((ui32Control & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_PER_SCATTER_GATHER))
+ {
+ ui32Control &= ~UDMA_MODE_ALT_SELECT;
+ }
+
+ // Return the mode to the caller.
+ return(ui32Control);
+}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/udma.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/udma.h
new file mode 100644
index 0000000..510691b
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/udma.h
@@ -0,0 +1,1240 @@
+/******************************************************************************
+* Filename: udma.h
+* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017)
+* Revision: 49048
+*
+* Description: Defines and prototypes for the uDMA controller.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup peripheral_group
+//! @{
+//! \addtogroup udma_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __UDMA_H__
+#define __UDMA_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "../inc/hw_types.h"
+#include "../inc/hw_ints.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_udma.h"
+#include "debug.h"
+#include "interrupt.h"
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// This section renames all functions that are not "static inline", so that
+// calling these functions will default to implementation in flash. At the end
+// of this file a second renaming will change the defaults to implementation in
+// ROM for available functions.
+//
+// To force use of the implementation in flash, e.g. for debugging:
+// - Globally: Define DRIVERLIB_NOROM at project level
+// - Per function: Use prefix "NOROM_" when calling the function
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #define uDMAChannelAttributeEnable NOROM_uDMAChannelAttributeEnable
+ #define uDMAChannelAttributeDisable NOROM_uDMAChannelAttributeDisable
+ #define uDMAChannelAttributeGet NOROM_uDMAChannelAttributeGet
+ #define uDMAChannelControlSet NOROM_uDMAChannelControlSet
+ #define uDMAChannelTransferSet NOROM_uDMAChannelTransferSet
+ #define uDMAChannelScatterGatherSet NOROM_uDMAChannelScatterGatherSet
+ #define uDMAChannelSizeGet NOROM_uDMAChannelSizeGet
+ #define uDMAChannelModeGet NOROM_uDMAChannelModeGet
+#endif
+
+//*****************************************************************************
+//
+//! \brief A structure that defines an entry in the channel control table.
+//!
+//! These fields are used by the uDMA controller and normally it is not necessary for
+//! software to directly read or write fields in the table.
+//
+//*****************************************************************************
+typedef struct
+{
+ volatile void *pvSrcEndAddr; //!< The ending source address of the data transfer.
+ volatile void *pvDstEndAddr; //!< The ending destination address of the data transfer.
+ volatile uint32_t ui32Control; //!< The channel control mode.
+ volatile uint32_t ui32Spare; //!< An unused location.
+}
+tDMAControlTable;
+
+//*****************************************************************************
+//
+//! \brief A helper macro for building scatter-gather task table entries.
+//!
+//! This macro is intended to be used to help populate a table of uDMA tasks
+//! for a scatter-gather transfer. This macro will calculate the values for
+//! the fields of a task structure entry based on the input parameters.
+//!
+//! There are specific requirements for the values of each parameter. No
+//! checking is done so it is up to the caller to ensure that correct values
+//! are used for the parameters.
+//!
+//! This macro is intended to be used to initialize individual entries of
+//! a structure of tDMAControlTable type, like this:
+//!
+/*!
+\verbatim
+ tDMAControlTable MyTaskList[] =
+ {
+ uDMATaskStructEntry(Task1Count, UDMA_SIZE_8,
+ UDMA_SRC_INC_8, MySourceBuf,
+ UDMA_DST_INC_8, MyDestBuf,
+ UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER),
+ uDMATaskStructEntry(Task2Count, ... ),
+ }
+\endverbatim
+*/
+//! \param ui32TransferCount is the count of items to transfer for this task.
+//! It must be in the range 1-1024.
+//! \param ui32ItemSize is the bit size of the items to transfer for this task.
+//! It must be one of:
+//! - \ref UDMA_SIZE_8
+//! - \ref UDMA_SIZE_16
+//! - \ref UDMA_SIZE_32
+//! \param ui32SrcIncrement is the bit size increment for source data.
+//! It must be one of:
+//! - \ref UDMA_SRC_INC_8
+//! - \ref UDMA_SRC_INC_16
+//! - \ref UDMA_SRC_INC_32
+//! - \ref UDMA_SRC_INC_NONE
+//! \param pvSrcAddr is the starting address of the data to transfer.
+//! \param ui32DstIncrement is the bit size increment for destination data.
+//! It must be one of:
+//! - \ref UDMA_DST_INC_8
+//! - \ref UDMA_DST_INC_16
+//! - \ref UDMA_DST_INC_32
+//! - \ref UDMA_DST_INC_NONE
+//! \param pvDstAddr is the starting address of the destination data.
+//! \param ui32ArbSize is the arbitration size to use for the transfer task.
+//! This is used to select the arbitration size in powers of 2, from 1 to 1024.
+//! It must be one of:
+//! - \ref UDMA_ARB_1
+//! - \ref UDMA_ARB_2
+//! - \ref UDMA_ARB_4
+//! - ...
+//! - \ref UDMA_ARB_1024
+//! \param ui32Mode is the transfer mode for this task.
+//! Note that normally all tasks will be one of the scatter-gather modes while the
+//! last task is a task list will be AUTO or BASIC.
+//! It must be one of:
+//! - \ref UDMA_MODE_BASIC
+//! - \ref UDMA_MODE_AUTO
+//! - \ref UDMA_MODE_MEM_SCATTER_GATHER
+//! - \ref UDMA_MODE_PER_SCATTER_GATHER
+//!
+//! \return None (this is not a function)
+//
+//*****************************************************************************
+#define uDMATaskStructEntry(ui32TransferCount, \
+ ui32ItemSize, \
+ ui32SrcIncrement, \
+ pvSrcAddr, \
+ ui32DstIncrement, \
+ pvDstAddr, \
+ ui32ArbSize, \
+ ui32Mode) \
+ { \
+ (((ui32SrcIncrement) == UDMA_SRC_INC_NONE) ? (pvSrcAddr) : \
+ ((void *)(&((uint8_t *)(pvSrcAddr))[((ui32TransferCount) << \
+ ((ui32SrcIncrement) >> 26)) - 1]))), \
+ (((ui32DstIncrement) == UDMA_DST_INC_NONE) ? (pvDstAddr) : \
+ ((void *)(&((uint8_t *)(pvDstAddr))[((ui32TransferCount) << \
+ ((ui32DstIncrement) >> 30)) - 1]))), \
+ (ui32SrcIncrement) | (ui32DstIncrement) | (ui32ItemSize) | \
+ (ui32ArbSize) | (((ui32TransferCount) - 1) << 4) | \
+ ((((ui32Mode) == UDMA_MODE_MEM_SCATTER_GATHER) || \
+ ((ui32Mode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \
+ (ui32Mode) | UDMA_MODE_ALT_SELECT : (ui32Mode)), 0 \
+ }
+
+//*****************************************************************************
+//
+// The hardware configured number of uDMA channels.
+//
+//*****************************************************************************
+#define UDMA_NUM_CHANNELS 21
+
+//*****************************************************************************
+//
+// The level of priority for the uDMA channels
+//
+//*****************************************************************************
+#define UDMA_PRIORITY_LOW 0x00000000
+#define UDMA_PRIORITY_HIGH 0x00000001
+
+//*****************************************************************************
+//
+// Flags that can be passed to uDMAChannelAttributeEnable(),
+// uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet().
+//
+//*****************************************************************************
+#define UDMA_ATTR_USEBURST 0x00000001
+#define UDMA_ATTR_ALTSELECT 0x00000002
+#define UDMA_ATTR_HIGH_PRIORITY 0x00000004
+#define UDMA_ATTR_REQMASK 0x00000008
+#define UDMA_ATTR_ALL 0x0000000F
+
+//*****************************************************************************
+//
+// DMA control modes that can be passed to uDMAChannelModeSet() and returned
+// uDMAChannelModeGet().
+//
+//*****************************************************************************
+#define UDMA_MODE_STOP 0x00000000
+#define UDMA_MODE_BASIC 0x00000001
+#define UDMA_MODE_AUTO 0x00000002
+#define UDMA_MODE_PINGPONG 0x00000003
+#define UDMA_MODE_MEM_SCATTER_GATHER \
+ 0x00000004
+#define UDMA_MODE_PER_SCATTER_GATHER \
+ 0x00000006
+#define UDMA_MODE_M 0x00000007 // uDMA Transfer Mode
+#define UDMA_MODE_ALT_SELECT 0x00000001
+
+//*****************************************************************************
+//
+// Channel configuration values that can be passed to uDMAControlSet().
+//
+//*****************************************************************************
+#define UDMA_DST_INC_8 0x00000000
+#define UDMA_DST_INC_16 0x40000000
+#define UDMA_DST_INC_32 0x80000000
+#define UDMA_DST_INC_NONE 0xC0000000
+#define UDMA_DST_INC_M 0xC0000000 // Destination Address Increment
+#define UDMA_DST_INC_S 30
+#define UDMA_SRC_INC_8 0x00000000
+#define UDMA_SRC_INC_16 0x04000000
+#define UDMA_SRC_INC_32 0x08000000
+#define UDMA_SRC_INC_NONE 0x0c000000
+#define UDMA_SRC_INC_M 0x0C000000 // Source Address Increment
+#define UDMA_SRC_INC_S 26
+#define UDMA_SIZE_8 0x00000000
+#define UDMA_SIZE_16 0x11000000
+#define UDMA_SIZE_32 0x22000000
+#define UDMA_SIZE_M 0x33000000 // Data Size
+#define UDMA_SIZE_S 24
+#define UDMA_ARB_1 0x00000000
+#define UDMA_ARB_2 0x00004000
+#define UDMA_ARB_4 0x00008000
+#define UDMA_ARB_8 0x0000c000
+#define UDMA_ARB_16 0x00010000
+#define UDMA_ARB_32 0x00014000
+#define UDMA_ARB_64 0x00018000
+#define UDMA_ARB_128 0x0001c000
+#define UDMA_ARB_256 0x00020000
+#define UDMA_ARB_512 0x00024000
+#define UDMA_ARB_1024 0x00028000
+#define UDMA_ARB_M 0x0003C000 // Arbitration Size
+#define UDMA_ARB_S 14
+#define UDMA_NEXT_USEBURST 0x00000008
+#define UDMA_XFER_SIZE_MAX 1024
+#define UDMA_XFER_SIZE_M 0x00003FF0 // Transfer size
+#define UDMA_XFER_SIZE_S 4
+
+//*****************************************************************************
+//
+// Channel numbers to be passed to API functions that require a channel number
+// ID.
+//
+//*****************************************************************************
+#define UDMA_CHAN_SW_EVT0 0 // Software Event Channel 0
+#define UDMA_CHAN_UART0_RX 1 // UART0 RX Data
+#define UDMA_CHAN_UART0_TX 2 // UART0 RX Data
+#define UDMA_CHAN_SSI0_RX 3 // SSI0 RX Data
+#define UDMA_CHAN_SSI0_TX 4 // SSI0 RX Data
+#define UDMA_CHAN_AUX_ADC 7 // AUX ADC event
+#define UDMA_CHAN_AUX_SW 8 // AUX Software event
+#define UDMA_CHAN_TIMER0_A 9 // Timer0 A event
+#define UDMA_CHAN_TIMER0_B 10 // Timer0 B event
+#define UDMA_CHAN_TIMER1_A 11
+#define UDMA_CHAN_TIMER1_B 12
+#define UDMA_CHAN_AON_PROG2 13
+#define UDMA_CHAN_DMA_PROG 14
+#define UDMA_CHAN_AON_RTC 15
+#define UDMA_CHAN_SSI1_RX 16
+#define UDMA_CHAN_SSI1_TX 17
+#define UDMA_CHAN_SW_EVT1 18
+#define UDMA_CHAN_SW_EVT2 19
+#define UDMA_CHAN_SW_EVT3 20
+
+//*****************************************************************************
+//
+// Flags to be OR'd with the channel ID to indicate if the primary or alternate
+// control structure should be used.
+//
+//*****************************************************************************
+#define UDMA_PRI_SELECT 0x00000000
+#define UDMA_ALT_SELECT 0x00000020
+
+//*****************************************************************************
+//
+// API Functions and prototypes
+//
+//*****************************************************************************
+
+#ifdef DRIVERLIB_DEBUG
+//*****************************************************************************
+//
+//! \internal
+//!
+//! \brief Checks a uDMA base address.
+//!
+//! This function determines if a uDMA module base address is valid.
+//!
+//! \param ui32Base specifies the uDMA module base address.
+//!
+//! \return Returns \c true if the base address is valid and \c false
+//! otherwise.
+//
+//*****************************************************************************
+static bool
+uDMABaseValid(uint32_t ui32Base)
+{
+ return(ui32Base == UDMA0_BASE);
+}
+#endif
+
+//*****************************************************************************
+//
+//! \brief Enables the uDMA controller for use.
+//!
+//! This function enables the uDMA controller. The uDMA controller must be
+//! enabled before it can be configured and used.
+//!
+//! \param ui32Base is the base address of the uDMA port.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+uDMAEnable(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(uDMABaseValid(ui32Base));
+
+ // Set the master enable bit in the config register.
+ HWREG(ui32Base + UDMA_O_CFG) = UDMA_CFG_MASTERENABLE;
+}
+
+//*****************************************************************************
+//
+//! \brief Disables the uDMA controller for use.
+//!
+//! This function disables the uDMA controller. Once disabled, the uDMA
+//! controller will not operate until re-enabled with \ref uDMAEnable().
+//!
+//! \param ui32Base is the base address of the uDMA port.
+//!
+//! \return None.
+//
+//*****************************************************************************
+__STATIC_INLINE void
+uDMADisable(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(uDMABaseValid(ui32Base));
+
+ // Clear the master enable bit in the config register.
+ HWREG(ui32Base + UDMA_O_CFG) = 0;
+}
+
+//*****************************************************************************
+//
+//! \brief Gets the uDMA error status.
+//!
+//! This function returns the uDMA error status. It should be called from
+//! within the uDMA error interrupt handler to determine if a uDMA error
+//! occurred.
+//!
+//! \param ui32Base is the base address of the uDMA port.
+//!
+//! \return Returns non-zero if a uDMA error is pending.
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+uDMAErrorStatusGet(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(uDMABaseValid(ui32Base));
+
+ // Return the uDMA error status.
+ return(HWREG(ui32Base + UDMA_O_ERROR));
+}
+
+//*****************************************************************************
+//
+//! \brief Clears the uDMA error interrupt.
+//!
+//! This function clears a pending uDMA error interrupt. It should be called
+//! from within the uDMA error interrupt handler to clear the interrupt.
+//!
+//! \param ui32Base is the base address of the uDMA port.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+uDMAErrorStatusClear(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(uDMABaseValid(ui32Base));
+
+ // Clear the uDMA error interrupt.
+ HWREG(ui32Base + UDMA_O_ERROR) = UDMA_ERROR_STATUS;
+}
+
+//*****************************************************************************
+//
+//! \brief Enables a uDMA channel for operation.
+//!
+//! This function enables a specific uDMA channel for use. This function must
+//! be used to enable a channel before it can be used to perform a uDMA
+//! transfer.
+//!
+//! When a uDMA transfer is completed, the channel will be automatically
+//! disabled by the uDMA controller. Therefore, this function should be called
+//! prior to starting up any new transfer.
+//!
+//! \param ui32Base is the base address of the uDMA port.
+//! \param ui32ChannelNum is the channel number to enable.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+uDMAChannelEnable(uint32_t ui32Base, uint32_t ui32ChannelNum)
+{
+ // Check the arguments.
+ ASSERT(uDMABaseValid(ui32Base));
+ ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS);
+
+ // Set the bit for this channel in the enable set register.
+ HWREG(ui32Base + UDMA_O_SETCHANNELEN) = 1 << ui32ChannelNum;
+}
+
+//*****************************************************************************
+//
+//! \brief Disables a uDMA channel for operation.
+//!
+//! This function disables a specific uDMA channel. Once disabled, a channel
+//! will not respond to uDMA transfer requests until re-enabled via
+//! \ref uDMAChannelEnable().
+//!
+//! \param ui32Base is the base address of the uDMA port.
+//! \param ui32ChannelNum is the channel number to disable.
+//!
+//! \return None.
+//
+//*****************************************************************************
+__STATIC_INLINE void
+uDMAChannelDisable(uint32_t ui32Base, uint32_t ui32ChannelNum)
+{
+ // Check the arguments.
+ ASSERT(uDMABaseValid(ui32Base));
+ ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS);
+
+ // Set the bit for this channel in the enable clear register.
+ HWREG(ui32Base + UDMA_O_CLEARCHANNELEN) = 1 << ui32ChannelNum;
+}
+
+//*****************************************************************************
+//
+//! \brief Checks if a uDMA channel is enabled for operation.
+//!
+//! This function checks to see if a specific uDMA channel is enabled. This
+//! can be used to check the status of a transfer, since the channel will
+//! be automatically disabled at the end of a transfer.
+//!
+//! \param ui32Base is the base address of the uDMA port.
+//! \param ui32ChannelNum is the channel number to check.
+//!
+//! \return Returns status of uDMA channel.
+//! - \c true : Channel is enabled.
+//! - \c false : Disabled.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+uDMAChannelIsEnabled(uint32_t ui32Base, uint32_t ui32ChannelNum)
+{
+ // Check the arguments.
+ ASSERT(uDMABaseValid(ui32Base));
+ ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS);
+
+ // AND the specified channel bit with the enable register, and return the
+ // result.
+ return((HWREG(ui32Base + UDMA_O_SETCHANNELEN) & (1 << ui32ChannelNum)) ?
+ true : false);
+}
+
+//*****************************************************************************
+//
+//! \brief Sets the base address for the channel control table.
+//!
+//! This function sets the base address of the channel control table. This
+//! table resides in system memory and holds control information for each uDMA
+//! channel. The table must be aligned on a 1024 byte boundary. The base
+//! address must be set before any of the channel functions can be used.
+//! Setting the base address of the primary control table will automatically
+//! set the address for the alternate control table as the next memory
+//! location after the primary control table.
+//!
+//! The size of the channel control table depends on the number of uDMA
+//! channels, and which transfer modes are used. Refer to the introductory
+//! text and the microcontroller datasheet for more information about the
+//! channel control table.
+//!
+//! \note This register cannot be read when the controller is in the reset
+//! state.
+//!
+//! \param ui32Base is the base address of the uDMA port.
+//! \param pControlTable is a pointer to the 1024 byte aligned base address
+//! of the uDMA channel control table. The address must be an absolute address
+//! in system memory space.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+uDMAControlBaseSet(uint32_t ui32Base, void *pControlTable)
+{
+ // Check the arguments.
+ ASSERT(uDMABaseValid(ui32Base));
+ ASSERT(((uint32_t)pControlTable & ~0x3FF) ==
+ (uint32_t)pControlTable);
+ ASSERT((uint32_t)pControlTable >= SRAM_BASE);
+
+ // Program the base address into the register.
+ HWREG(ui32Base + UDMA_O_CTRL) = (uint32_t)pControlTable;
+}
+
+//*****************************************************************************
+//
+//! \brief Gets the base address for the channel control table.
+//!
+//! This function gets the base address of the channel control table. This
+//! table resides in system memory and holds control information for each uDMA
+//! channel.
+//!
+//! \param ui32Base is the base address of the uDMA port.
+//!
+//! \return Returns a pointer to the base address of the channel control table.
+//
+//*****************************************************************************
+__STATIC_INLINE void *
+uDMAControlBaseGet(uint32_t ui32Base)
+{
+ // Check the arguments.
+
+ ASSERT(uDMABaseValid(ui32Base));
+ // Read the current value of the control base register, and return it to
+ // the caller.
+ return((void *)HWREG(ui32Base + UDMA_O_CTRL));
+}
+
+//*****************************************************************************
+//
+//! \brief Gets the base address for the channel control table alternate structures.
+//!
+//! This function gets the base address of the second half of the channel
+//! control table that holds the alternate control structures for each channel.
+//!
+//! \param ui32Base is the base address of the uDMA port.
+//!
+//! \return Returns a pointer to the base address of the second half of the
+//! channel control table.
+//
+//*****************************************************************************
+__STATIC_INLINE void *
+uDMAControlAlternateBaseGet(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(uDMABaseValid(ui32Base));
+
+ // Read the current value of the control base register, and return it to
+ // the caller.
+ return((void *)HWREG(ui32Base + UDMA_O_ALTCTRL));
+}
+
+//*****************************************************************************
+//
+//! \brief Requests a uDMA channel to start a transfer.
+//!
+//! This function allows software to request a uDMA channel to begin a
+//! transfer. This could be used for performing a memory to memory transfer,
+//! or if for some reason a transfer needs to be initiated by software instead
+//! of the peripheral associated with that channel.
+//!
+//! \note If the channel is a software channel and interrupts are used, then
+//! the completion will be signaled on the uDMA dedicated interrupt. If a
+//! peripheral channel is used, then the completion will be signaled on the
+//! peripheral's interrupt.
+//!
+//! \param ui32Base is the base address of the uDMA port.
+//! \param ui32ChannelNum is the channel number on which to request a uDMA
+//! transfer.
+//!
+//! \return None.
+//
+//*****************************************************************************
+__STATIC_INLINE void
+uDMAChannelRequest(uint32_t ui32Base, uint32_t ui32ChannelNum)
+{
+ // Check the arguments.
+ ASSERT(uDMABaseValid(ui32Base));
+ ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS);
+
+ // Set the bit for this channel in the software uDMA request register.
+ HWREG(ui32Base + UDMA_O_SOFTREQ) = 1 << ui32ChannelNum;
+}
+
+//*****************************************************************************
+//
+//! \brief Enables attributes of a uDMA channel.
+//!
+//! This function is used to enable attributes of a uDMA channel.
+//!
+//! \param ui32Base is the base address of the uDMA port.
+//! \param ui32ChannelNum is the channel to configure.
+//! \param ui32Attr is a combination of attributes for the channel.
+//! The parameter is the bitwise OR of any of the following:
+//! - \ref UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst mode.
+//! - \ref UDMA_ATTR_ALTSELECT is used to select the alternate control structure
+//! for this channel (it is very unlikely that this flag should be used).
+//! - \ref UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority.
+//! - \ref UDMA_ATTR_REQMASK is used to mask the hardware request signal from the
+//! peripheral for this channel.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void uDMAChannelAttributeEnable(uint32_t ui32Base,
+ uint32_t ui32ChannelNum,
+ uint32_t ui32Attr);
+
+//*****************************************************************************
+//
+//! \brief Disables attributes of an uDMA channel.
+//!
+//! This function is used to disable attributes of a uDMA channel.
+//!
+//! \param ui32Base is the base address of the uDMA port.
+//! \param ui32ChannelNum is the channel to configure.
+//! \param ui32Attr is a combination of attributes for the channel.
+//! The parameter is the bitwise OR of any of the following:
+//! - \ref UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst mode.
+//! - \ref UDMA_ATTR_ALTSELECT is used to select the alternate control structure
+//! for this channel (it is very unlikely that this flag should be used).
+//! - \ref UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority.
+//! - \ref UDMA_ATTR_REQMASK is used to mask the hardware request signal from the
+//! peripheral for this channel.
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void uDMAChannelAttributeDisable(uint32_t ui32Base,
+ uint32_t ui32ChannelNum,
+ uint32_t ui32Attr);
+
+//*****************************************************************************
+//
+//! \brief Gets the enabled attributes of a uDMA channel.
+//!
+//! This function returns a combination of flags representing the attributes of
+//! the uDMA channel.
+//!
+//! \param ui32Base is the base address of the uDMA port.
+//! \param ui32ChannelNum is the channel to configure.
+//!
+//! \return Returns the bitwise OR of the attributes of the uDMA channel, which
+//! can be any of the following:
+//! - \ref UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst mode.
+//! - \ref UDMA_ATTR_ALTSELECT is used to select the alternate control structure
+//! for this channel (it is very unlikely that this flag should be used).
+//! - \ref UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority.
+//! - \ref UDMA_ATTR_REQMASK is used to mask the hardware request signal from the
+//! peripheral for this channel.
+//
+//*****************************************************************************
+extern uint32_t uDMAChannelAttributeGet(uint32_t ui32Base,
+ uint32_t ui32ChannelNum);
+
+//*****************************************************************************
+//
+//! \brief Sets the control parameters for a uDMA channel control structure.
+//!
+//! This function is used to set control parameters for a uDMA transfer. These
+//! are typically parameters that are not changed often.
+//!
+//! \note The address increment cannot be smaller than the data size.
+//!
+//! \param ui32Base is the base address of the uDMA port.
+//! \param ui32ChannelStructIndex is the bitwise OR of the uDMA channel number and:
+//! - \ref UDMA_PRI_SELECT : Use primary data structure.
+//! - \ref UDMA_ALT_SELECT : Use alternate data structure.
+//! \param ui32Control is the bitwise OR of five values:
+//! - Data size
+//! - \ref UDMA_SIZE_8 : 8 bits.
+//! - \ref UDMA_SIZE_16 : 16 bits.
+//! - \ref UDMA_SIZE_32 : 32 bits.
+//! - Source address increment
+//! - \ref UDMA_SRC_INC_8 : 8 bits.
+//! - \ref UDMA_SRC_INC_16 : 16 bits.
+//! - \ref UDMA_SRC_INC_32 : 32 bits.
+//! - \ref UDMA_SRC_INC_NONE : Non-incrementing.
+//! - Destination address increment
+//! - \ref UDMA_DST_INC_8 : 8 bits.
+//! - \ref UDMA_DST_INC_16 : 16 bits.
+//! - \ref UDMA_DST_INC_32 : 32 bits.
+//! - \ref UDMA_DST_INC_NONE : Non-incrementing.
+//! - Arbitration size. Determines how many items are transferred before
+//! the uDMA controller re-arbitrates for the bus. In power of 2.
+//! - \ref UDMA_ARB_1
+//! - \ref UDMA_ARB_2
+//! - \ref UDMA_ARB_4
+//! - \ref UDMA_ARB_8
+//! - ...
+//! - \ref UDMA_ARB_1024
+//! - Force the channel to only respond to burst requests at the tail end of a scatter-gather transfer.
+//! - \ref UDMA_NEXT_USEBURST
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void uDMAChannelControlSet(uint32_t ui32Base,
+ uint32_t ui32ChannelStructIndex,
+ uint32_t ui32Control);
+
+//*****************************************************************************
+//
+//! \brief Sets the transfer parameters for a uDMA channel control structure.
+//!
+//! This function is used to set the parameters for a uDMA transfer. These are
+//! typically parameters that are changed often. The function
+//! \ref uDMAChannelControlSet() MUST be called at least once for this channel prior
+//! to calling this function.
+//!
+//! The \c pvSrcAddr and \c pvDstAddr parameters are pointers to the first
+//! location of the data to be transferred. These addresses should be aligned
+//! according to the item size. The compiler will take care of this if the
+//! pointers are pointing to storage of the appropriate data type.
+//!
+//! The two scatter/gather modes, MEMORY and PERIPHERAL, are actually different
+//! depending on whether the primary or alternate control structure is
+//! selected. This function will look for the \ref UDMA_PRI_SELECT and
+//! \ref UDMA_ALT_SELECT flag along with the channel number and will set the
+//! scatter/gather mode as appropriate for the primary or alternate control
+//! structure.
+//!
+//! The channel must also be enabled using \ref uDMAChannelEnable() after calling
+//! this function. The transfer will not begin until the channel has been set
+//! up and enabled. Note that the channel is automatically disabled after the
+//! transfer is completed, meaning that \ref uDMAChannelEnable() must be called
+//! again after setting up the next transfer.
+//!
+//! \note Great care must be taken to not modify a channel control structure
+//! that is in use or else the results will be unpredictable, including the
+//! possibility of undesired data transfers to or from memory or peripherals.
+//! For BASIC and AUTO modes, it is safe to make changes when the channel is
+//! disabled, or the \ref uDMAChannelModeGet() returns \ref UDMA_MODE_STOP. For
+//! PINGPONG or one of the SCATTER_GATHER modes, it is safe to modify the
+//! primary or alternate control structure only when the other is being used.
+//! The \ref uDMAChannelModeGet() function will return \ref UDMA_MODE_STOP when a
+//! channel control structure is inactive and safe to modify.
+//!
+//! \param ui32Base is the base address of the uDMA port.
+//! \param ui32ChannelStructIndex is the bitwise OR of the uDMA channel number and:
+//! - \ref UDMA_PRI_SELECT : Use primary data structure.
+//! - \ref UDMA_ALT_SELECT : Use alternate data structure.
+//! \param ui32Mode is the type of uDMA transfer.
+//! The parameter should be one of the following values:
+//! - \ref UDMA_MODE_STOP : Stops the uDMA transfer. The controller sets the mode
+//! to this value at the end of a transfer.
+//! - \ref UDMA_MODE_BASIC : Perform a basic transfer based on request.
+//! - \ref UDMA_MODE_AUTO to perform a transfer that will always complete once
+//! started even if request is removed.
+//! - \ref UDMA_MODE_PINGPONG : Set up a transfer that switches between the
+//! primary and alternate control structures for the channel. This allows
+//! use of ping-pong buffering for uDMA transfers.
+//! - \ref UDMA_MODE_MEM_SCATTER_GATHER : Set up a memory scatter-gather transfer.
+//! - \ref UDMA_MODE_PER_SCATTER_GATHER : Set up a peripheral scatter-gather transfer.
+//! \param pvSrcAddr is the source address for the transfer.
+//! \param pvDstAddr is the destination address for the transfer.
+//! \param ui32TransferSize is the number of data items to transfer (\b NOT bytes).
+//!
+//! \return None
+//
+//*****************************************************************************
+extern void uDMAChannelTransferSet(uint32_t ui32Base,
+ uint32_t ui32ChannelStructIndex,
+ uint32_t ui32Mode, void *pvSrcAddr,
+ void *pvDstAddr, uint32_t ui32TransferSize);
+
+//*****************************************************************************
+//
+//! \brief Configures a uDMA channel for scatter-gather mode.
+//!
+//! This function is used to configure a channel for scatter-gather mode.
+//! The caller must have already set up a task list, and pass a pointer to
+//! the start of the task list as the \c pvTaskList parameter.
+//!
+//! The \c ui32TaskCount parameter is the count of tasks in the task list, not the
+//! size of the task list.
+//!
+//! The flag \c bIsPeriphSG should be used to indicate
+//! if the scatter-gather should be configured for a peripheral or memory
+//! scatter-gather operation.
+//!
+//! \param ui32Base is the base address of the uDMA port.
+//! \param ui32ChannelNum is the uDMA channel number.
+//! \param ui32TaskCount is the number of scatter-gather tasks to execute.
+//! \param pvTaskList is a pointer to the beginning of the scatter-gather
+//! task list.
+//! \param ui32IsPeriphSG is a flag to indicate it is a peripheral
+//! scatter-gather transfer (else it will be memory scatter-gather transfer)
+//!
+//! \return None
+//!
+//! \sa \ref uDMATaskStructEntry()
+//
+//*****************************************************************************
+extern void uDMAChannelScatterGatherSet(uint32_t ui32Base,
+ uint32_t ui32ChannelNum,
+ uint32_t ui32TaskCount,
+ void *pvTaskList,
+ uint32_t ui32IsPeriphSG);
+
+//*****************************************************************************
+//
+//! \brief Gets the current transfer size for a uDMA channel control structure.
+//!
+//! This function is used to get the uDMA transfer size for a channel. The
+//! transfer size is the number of items to transfer, where the size of an item
+//! might be 8, 16, or 32 bits. If a partial transfer has already occurred,
+//! then the number of remaining items will be returned. If the transfer is
+//! complete, then 0 will be returned.
+//!
+//! \param ui32Base is the base address of the uDMA port.
+//! \param ui32ChannelStructIndex is the bitwise OR of the uDMA channel number and:
+//! - \ref UDMA_PRI_SELECT
+//! - \ref UDMA_ALT_SELECT
+//!
+//! \return Returns the number of items remaining to transfer.
+//
+//*****************************************************************************
+extern uint32_t uDMAChannelSizeGet(uint32_t ui32Base,
+ uint32_t ui32ChannelStructIndex);
+
+//*****************************************************************************
+//
+//! \brief Gets the transfer mode for a uDMA channel control structure.
+//!
+//! This function is used to get the transfer mode for the uDMA channel. It
+//! can be used to query the status of a transfer on a channel. When the
+//! transfer is complete the mode will be \ref UDMA_MODE_STOP.
+//!
+//! \param ui32Base is the base address of the uDMA port.
+//! \param ui32ChannelStructIndex is the bitwise OR of the uDMA channel number and:
+//! - \ref UDMA_PRI_SELECT
+//! - \ref UDMA_ALT_SELECT
+//!
+//! \return Returns the transfer mode of the specified channel and control
+//! structure, which will be one of the following values:
+//! - \ref UDMA_MODE_STOP
+//! - \ref UDMA_MODE_BASIC
+//! - \ref UDMA_MODE_AUTO
+//! - \ref UDMA_MODE_PINGPONG
+//! - \ref UDMA_MODE_MEM_SCATTER_GATHER
+//! - \ref UDMA_MODE_PER_SCATTER_GATHER
+//
+//*****************************************************************************
+extern uint32_t uDMAChannelModeGet(uint32_t ui32Base,
+ uint32_t ui32ChannelStructIndex);
+
+//*****************************************************************************
+//
+//! \brief Registers an interrupt handler for the uDMA controller in the dynamic interrupt table.
+//!
+//! \note Only use this function if you want to use the dynamic vector table (in SRAM)!
+//!
+//! This function registers a function as the interrupt handler for a specific
+//! interrupt and enables the corresponding interrupt in the interrupt controller.
+//!
+//! \note The interrupt handler for uDMA is for transfer completion when the
+//! software channel is used, and for error interrupts. The interrupts for each
+//! peripheral channel are handled through the individual peripheral interrupt
+//! handlers.
+//!
+//! \param ui32Base is the base address of the uDMA module.
+//! \param ui32IntChannel specifies which uDMA interrupt is to be registered.
+//! - \c INT_DMA_DONE_COMB : Register an interrupt handler to process interrupts
+//! from the uDMA software channel.
+//! - \c INT_DMA_ERR : Register an interrupt handler to process uDMA error
+//! interrupts.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! interrupt is activated.
+//!
+//! \return None
+//!
+//! \sa \ref IntRegister() for important information about registering interrupt
+//! handlers.
+//
+//*****************************************************************************
+__STATIC_INLINE void
+uDMAIntRegister(uint32_t ui32Base, uint32_t ui32IntChannel,
+ void (*pfnHandler)(void))
+{
+ // Check the arguments.
+ ASSERT(uDMABaseValid(ui32Base));
+ ASSERT(pfnHandler);
+ ASSERT((ui32IntChannel == INT_DMA_DONE_COMB) || (ui32IntChannel == INT_DMA_ERR));
+
+ // Register the interrupt handler.
+ IntRegister(ui32IntChannel, pfnHandler);
+
+ // Enable the memory management fault.
+ IntEnable(ui32IntChannel);
+}
+
+//*****************************************************************************
+//
+//! \brief Unregisters an interrupt handler for the uDMA controller in the dynamic interrupt table.
+//!
+//! This function will disable and clear the handler to be called for the
+//! specified uDMA interrupt.
+//!
+//! \param ui32Base is the base address of the uDMA module.
+//! \param ui32IntChannel specifies which uDMA interrupt to unregister.
+//! - \c INT_DMA_DONE_COMB : Register an interrupt handler to process interrupts
+//! from the uDMA software channel.
+//! - \c INT_DMA_ERR : Register an interrupt handler to process uDMA error
+//! interrupts.
+//!
+//! \return None
+//!
+//! \sa \ref IntRegister() for important information about registering interrupt
+//! handlers.
+//
+//*****************************************************************************
+__STATIC_INLINE void
+uDMAIntUnregister(uint32_t ui32Base, uint32_t ui32IntChannel)
+{
+ // Check the arguments.
+ ASSERT(uDMABaseValid(ui32Base));
+ ASSERT((ui32IntChannel == INT_DMA_DONE_COMB) || (ui32IntChannel == INT_DMA_ERR));
+
+ // Disable the interrupt.
+ IntDisable(ui32IntChannel);
+
+ // Unregister the interrupt handler.
+ IntUnregister(ui32IntChannel);
+}
+
+//*****************************************************************************
+//
+//! \brief Clears uDMA interrupt done status.
+//!
+//! Clears bits in the uDMA interrupt status register according to which bits
+//! are set in \c ui32ChanMask. There is one bit for each channel. If a a bit
+//! is set in \c ui32ChanMask, then that corresponding channel's interrupt
+//! status will be cleared (if it was set).
+//!
+//! \param ui32Base is the base address of the uDMA port.
+//! \param ui32ChanMask is a 32-bit mask with one bit for each uDMA channel.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+uDMAIntClear(uint32_t ui32Base, uint32_t ui32ChanMask)
+{
+ // Check the arguments.
+ ASSERT(uDMABaseValid(ui32Base));
+
+ // Clear the requested bits in the uDMA interrupt status register.
+ HWREG(ui32Base + UDMA_O_REQDONE) = ui32ChanMask;
+}
+
+//*****************************************************************************
+//
+//! \brief Get the uDMA interrupt status.
+//!
+//! This function returns the interrupt status for the specified UDMA. This
+//! function does not differentiate between software or hardware activated
+//! interrupts.
+//!
+//! \param ui32Base is the base address of the uDMA port.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+uDMAIntStatus(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(uDMABaseValid(ui32Base));
+
+ // Return the uDMA interrupt status register.
+ return (HWREG(ui32Base + UDMA_O_REQDONE));
+}
+
+//*****************************************************************************
+//
+//! \brief Enable interrupt on software event driven uDMA transfers.
+//!
+//! \note The main purpose of this function is to prevent propagation of uDMA
+//! status signals to a peripheral, if a peripheral and a software event is
+//! sharing the uDMA channel. If it is desired to initiate a transfer by
+//! writing to a register inside the uDMA (this means a software driven
+//! channel), then the uDMA status signals propagation need to be blocked to
+//! the hardware peripherals.
+//!
+//! \param ui32Base is the base address of the uDMA port.
+//! \param ui32IntChannel identifies which uDMA interrupt to enable software
+//! interrupts for.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+uDMAIntSwEventEnable(uint32_t ui32Base, uint32_t ui32IntChannel)
+{
+ // Check the arguments.
+ ASSERT(uDMABaseValid(ui32Base));
+ ASSERT(ui32IntChannel < UDMA_NUM_CHANNELS);
+
+ // Enable the channel.
+ HWREGBITW(ui32Base + UDMA_O_DONEMASK, ui32IntChannel) = 1;
+}
+
+//*****************************************************************************
+//
+//! \brief Disable interrupt on software event driven uDMA transfers.
+//!
+//! This register disables the blocking of the uDMA status signals propagation
+//! to the hardware peripheral connected to the uDMA on the \c ui32IntChannel.
+//!
+//! \param ui32Base is the base address of the uDMA port.
+//! \param ui32IntChannel identifies which uDMA interrupt to disable software
+//! interrupts for.
+//!
+//! \return None
+//!
+//! \sa \ref uDMAIntSwEventEnable()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+uDMAIntSwEventDisable(uint32_t ui32Base, uint32_t ui32IntChannel)
+{
+ // Check the arguments.
+ ASSERT(uDMABaseValid(ui32Base));
+ ASSERT(ui32IntChannel < UDMA_NUM_CHANNELS);
+
+ // Disable the SW channel.
+ HWREGBITW(ui32Base + UDMA_O_DONEMASK, ui32IntChannel) = 0;
+}
+
+//*****************************************************************************
+//
+//! \brief Return the status of the uDMA module.
+//!
+//! \note This status register cannot be read when the controller is in the reset state.
+//!
+//! \param ui32Base is the base address of the uDMA port.
+//!
+//! \return Current status of the uDMA module.
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+uDMAGetStatus(uint32_t ui32Base)
+{
+ // Check the arguments.
+ ASSERT(uDMABaseValid(ui32Base));
+
+ // Read and return the status register.
+ return HWREG(ui32Base + UDMA_O_STATUS);
+}
+
+//*****************************************************************************
+//
+//! \brief Set the priority of a uDMA channel.
+//!
+//! \note Writing 0 to a bit has no effect on the priority. To reset a channel
+//! priority to the default value use \ref uDMAChannelPriorityClear().
+//!
+//! \param ui32Base is the base address of the uDMA port.
+//! \param ui32ChannelNum is uDMA channel to set the priority for.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+uDMAChannelPrioritySet(uint32_t ui32Base, uint32_t ui32ChannelNum)
+{
+ // Check the arguments.
+ ASSERT(uDMABaseValid(ui32Base));
+ ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS);
+
+ // Set the channel priority to high.
+ HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) = 1 << ui32ChannelNum;
+}
+
+//*****************************************************************************
+//
+//! \brief Get the priority of a uDMA channel.
+//!
+//! \param ui32Base is the base address of the uDMA port.
+//! \param ui32ChannelNum The uDMA channel to get the priority for.
+//!
+//! \return Returns one of:
+//! - \ref UDMA_PRIORITY_HIGH
+//! - \ref UDMA_PRIORITY_LOW
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+uDMAChannelPriorityGet(uint32_t ui32Base, uint32_t ui32ChannelNum)
+{
+ // Check the arguments.
+ ASSERT(uDMABaseValid(ui32Base));
+ ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS);
+
+ // Return the channel priority.
+ return(HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) & (1 << ui32ChannelNum) ?
+ UDMA_PRIORITY_HIGH : UDMA_PRIORITY_LOW);
+}
+
+//*****************************************************************************
+//
+//! \brief Clear the priority of a uDMA channel.
+//!
+//! \note Writing 0 to a bit has no effect on the priority. To set a channel
+//! priority to high use \ref uDMAChannelPrioritySet().
+//!
+//! \param ui32Base is the base address of the uDMA port.
+//! \param ui32ChannelNum The uDMA channel to clear the priority for.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+uDMAChannelPriorityClear(uint32_t ui32Base, uint32_t ui32ChannelNum)
+{
+ // Check the arguments.
+ ASSERT(uDMABaseValid(ui32Base));
+ ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS);
+
+ // Clear the channel priority.
+ HWREG(ui32Base + UDMA_O_CLEARCHNLPRIORITY) = 1 << ui32ChannelNum;
+}
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// Redirect to implementation in ROM when available.
+//
+//*****************************************************************************
+#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
+ #include "../driverlib/rom.h"
+ #ifdef ROM_uDMAChannelAttributeEnable
+ #undef uDMAChannelAttributeEnable
+ #define uDMAChannelAttributeEnable ROM_uDMAChannelAttributeEnable
+ #endif
+ #ifdef ROM_uDMAChannelAttributeDisable
+ #undef uDMAChannelAttributeDisable
+ #define uDMAChannelAttributeDisable ROM_uDMAChannelAttributeDisable
+ #endif
+ #ifdef ROM_uDMAChannelAttributeGet
+ #undef uDMAChannelAttributeGet
+ #define uDMAChannelAttributeGet ROM_uDMAChannelAttributeGet
+ #endif
+ #ifdef ROM_uDMAChannelControlSet
+ #undef uDMAChannelControlSet
+ #define uDMAChannelControlSet ROM_uDMAChannelControlSet
+ #endif
+ #ifdef ROM_uDMAChannelTransferSet
+ #undef uDMAChannelTransferSet
+ #define uDMAChannelTransferSet ROM_uDMAChannelTransferSet
+ #endif
+ #ifdef ROM_uDMAChannelScatterGatherSet
+ #undef uDMAChannelScatterGatherSet
+ #define uDMAChannelScatterGatherSet ROM_uDMAChannelScatterGatherSet
+ #endif
+ #ifdef ROM_uDMAChannelSizeGet
+ #undef uDMAChannelSizeGet
+ #define uDMAChannelSizeGet ROM_uDMAChannelSizeGet
+ #endif
+ #ifdef ROM_uDMAChannelModeGet
+ #undef uDMAChannelModeGet
+ #define uDMAChannelModeGet ROM_uDMAChannelModeGet
+ #endif
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __UDMA_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/vims.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/vims.c
new file mode 100644
index 0000000..a80d44e
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/vims.c
@@ -0,0 +1,176 @@
+/******************************************************************************
+* Filename: vims.c
+* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017)
+* Revision: 49096
+*
+* Description: Driver for the VIMS.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "vims.h"
+
+//*****************************************************************************
+//
+// Handle support for DriverLib in ROM:
+// This section will undo prototype renaming made in the header file
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #undef VIMSConfigure
+ #define VIMSConfigure NOROM_VIMSConfigure
+ #undef VIMSModeSet
+ #define VIMSModeSet NOROM_VIMSModeSet
+ #undef VIMSModeGet
+ #define VIMSModeGet NOROM_VIMSModeGet
+ #undef VIMSModeSafeSet
+ #define VIMSModeSafeSet NOROM_VIMSModeSafeSet
+#endif
+
+//*****************************************************************************
+//
+// Configures the VIMS.
+//
+//*****************************************************************************
+void
+VIMSConfigure(uint32_t ui32Base, bool bRoundRobin, bool bPrefetch)
+{
+ uint32_t ui32Reg;
+
+ // Check the arguments.
+ ASSERT(VIMSBaseValid(ui32Base));
+
+ ui32Reg = HWREG(ui32Base + VIMS_O_CTL);
+ ui32Reg &= ~(VIMS_CTL_PREF_EN | VIMS_CTL_ARB_CFG);
+ if(bRoundRobin)
+ {
+ ui32Reg |= VIMS_CTL_ARB_CFG;
+ }
+ if(bPrefetch)
+ {
+ ui32Reg |= VIMS_CTL_PREF_EN;
+ }
+
+ // Set the Arbitration and prefetch mode.
+ HWREG(ui32Base + VIMS_O_CTL) = ui32Reg;
+}
+
+//*****************************************************************************
+//
+// Set the operational mode of the VIMS
+//
+//*****************************************************************************
+void
+VIMSModeSet(uint32_t ui32Base, uint32_t ui32Mode)
+{
+ uint32_t ui32Reg;
+
+ // Check the arguments.
+ ASSERT(VIMSBaseValid(ui32Base));
+
+ ASSERT((ui32Mode == VIMS_MODE_DISABLED) ||
+ (ui32Mode == VIMS_MODE_ENABLED) ||
+ (ui32Mode == VIMS_MODE_OFF));
+
+ // Set the mode.
+ ui32Reg = HWREG(ui32Base + VIMS_O_CTL);
+ ui32Reg &= ~VIMS_CTL_MODE_M;
+ ui32Reg |= (ui32Mode & VIMS_CTL_MODE_M);
+
+ HWREG(ui32Base + VIMS_O_CTL) = ui32Reg;
+}
+
+//*****************************************************************************
+//
+// Get the current operational mode of the VIMS.
+//
+//*****************************************************************************
+uint32_t
+VIMSModeGet(uint32_t ui32Base)
+{
+ uint32_t ui32Reg;
+
+ // Check the arguments.
+ ASSERT(VIMSBaseValid(ui32Base));
+
+ ui32Reg = HWREG(ui32Base + VIMS_O_STAT);
+ if(ui32Reg & VIMS_STAT_MODE_CHANGING)
+ {
+ return (VIMS_MODE_CHANGING);
+ }
+ else
+ {
+ return (ui32Reg & VIMS_STAT_MODE_M);
+ }
+}
+
+//*****************************************************************************
+//
+// Safe setting of new VIMS mode
+// - Function might be blocking
+// - Can be called for any mode change (also if actually not changing mode)
+//
+//*****************************************************************************
+void
+VIMSModeSafeSet( uint32_t ui32Base, uint32_t ui32NewMode, bool blocking )
+{
+ uint32_t currentMode;
+
+ // Check the arguments.
+ ASSERT(VIMSBaseValid(ui32Base));
+ ASSERT((ui32NewMode == VIMS_MODE_DISABLED) ||
+ (ui32NewMode == VIMS_MODE_ENABLED) ||
+ (ui32NewMode == VIMS_MODE_OFF));
+
+ // Make sure that only the mode bits are set in the input parameter
+ // (done just for security since it is critical to the code flow)
+ ui32NewMode &= VIMS_CTL_MODE_M;
+
+ // Wait for any pending change to complete and get current VIMS mode
+ // (This is a blocking point but will typically only be a blocking point
+ // only if mode is changed multiple times with blocking=0)
+ do {
+ currentMode = VIMSModeGet( ui32Base );
+ } while ( currentMode == VIMS_MODE_CHANGING );
+
+ // First check that it actually is a mode change request
+ if ( ui32NewMode != currentMode ) {
+ // Set new mode
+ VIMSModeSet( ui32Base, ui32NewMode );
+
+ // Wait for final mode change to complete - if blocking is requested
+ if ( blocking ) {
+ while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) {
+ // Do nothing - wait for change to complete.
+ }
+ }
+ }
+}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/vims.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/vims.h
new file mode 100644
index 0000000..7a35af5
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/vims.h
@@ -0,0 +1,371 @@
+/******************************************************************************
+* Filename: vims.h
+* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016)
+* Revision: 47343
+*
+* Description: Defines and prototypes for the VIMS.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup system_control_group
+//! @{
+//! \addtogroup vims_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __VIMS_H__
+#define __VIMS_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "../inc/hw_types.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_vims.h"
+#include "debug.h"
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// This section renames all functions that are not "static inline", so that
+// calling these functions will default to implementation in flash. At the end
+// of this file a second renaming will change the defaults to implementation in
+// ROM for available functions.
+//
+// To force use of the implementation in flash, e.g. for debugging:
+// - Globally: Define DRIVERLIB_NOROM at project level
+// - Per function: Use prefix "NOROM_" when calling the function
+//
+//*****************************************************************************
+#if !defined(DOXYGEN)
+ #define VIMSConfigure NOROM_VIMSConfigure
+ #define VIMSModeSet NOROM_VIMSModeSet
+ #define VIMSModeGet NOROM_VIMSModeGet
+ #define VIMSModeSafeSet NOROM_VIMSModeSafeSet
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to VIMSModeSet() as the ui32IntFlags parameter,
+// and returned from VIMSModeGet().
+//
+//*****************************************************************************
+#define VIMS_MODE_CHANGING 0x4 // VIMS mode is changing now and VIMS_MODE
+ // can not be changed at moment.
+#define VIMS_MODE_DISABLED (VIMS_CTL_MODE_GPRAM) // Disabled mode (GPRAM enabled).
+#define VIMS_MODE_ENABLED (VIMS_CTL_MODE_CACHE) // Enabled mode, only USERCODE is cached.
+#define VIMS_MODE_OFF (VIMS_CTL_MODE_OFF) // VIMS Cache RAM is off
+
+//*****************************************************************************
+//
+// API Functions and prototypes
+//
+//*****************************************************************************
+
+#ifdef DRIVERLIB_DEBUG
+//*****************************************************************************
+//
+//! \brief Checks a VIMS base address.
+//!
+//! This function determines if the VIMS base address is valid.
+//!
+//! \param ui32Base is the base address of the VIMS.
+//!
+//! \return Returns \c true if the base address is valid and \c false
+//! otherwise.
+//
+//*****************************************************************************
+static bool
+VIMSBaseValid(uint32_t ui32Base)
+{
+ return(ui32Base == VIMS_BASE);
+}
+#endif
+
+//*****************************************************************************
+//
+//! \brief Configures the VIMS.
+//!
+//! This function sets general control settings of the VIMS system.
+//!
+//! \note The VIMS mode must be set using the \ref VIMSModeSet() call.
+//!
+//! \param ui32Base is the base address of the VIMS.
+//! \param bRoundRobin specifies the arbitration method.
+//! - \c true : Round Robin arbitration between the two available read/write interfaces
+//! (i.e. Icode/Dcode and Sysbus) is to be used.
+//! - \c false : Strict arbitration will be used, where Icode/Dcode
+//! is preferred over the Sysbus.
+//! \param bPrefetch specifies if prefetching is to be used.
+//! - \c true : Cache is to prefetch tag data for the following address.
+//! - \c false : No prefetch.
+//!
+//! \return None
+//!
+//! \sa \ref VIMSModeSet()
+//
+//*****************************************************************************
+extern void VIMSConfigure(uint32_t ui32Base, bool bRoundRobin,
+ bool bPrefetch);
+
+//*****************************************************************************
+//
+//! \brief Set the operational mode of the VIMS.
+//!
+//! This function sets the operational mode of the VIMS.
+//!
+//! Upon reset the VIMS will be in \ref VIMS_MODE_CHANGING mode.
+//! In this mode the VIMS will initialize the cache (GP) RAM (to all zeros).
+//! The GP RAM will not be operational (read/write will result in bus fault).
+//! The Cache will not be operational.
+//! Reads and writes to flash will be uncached.
+//! After a short delay (approx. 1029 clock cycles) the VIMS will
+//! automatically switch mode to \ref VIMS_MODE_DISABLED (GPRAM enabled).
+//!
+//! In \ref VIMS_MODE_DISABLED mode, the cache is disabled but the GP RAM is
+//! accessible:
+//! The GP RAM will be accessible.
+//! The Cache will not be operational.
+//! Reads from flash will be uncached.
+//! From this mode, the VIMS may be put in \ref VIMS_MODE_ENABLED (CACHE mode).
+//!
+//! In \ref VIMS_MODE_ENABLED mode, the cache is enabled for \b USERCODE space.
+//! The GP RAM will not be operational (read/write will result in bus fault).
+//! The Cache will be operational for SYSCODE space.
+//! Reads from flash in USERCODE space will be uncached.
+//!
+//! In \ref VIMS_MODE_OFF the cache RAM is off to conserve power.
+//!
+//! \note The VIMS must be invalidated when switching mode.
+//! This is done by setting VIMS_MODE_OFF before setting any new mode.
+//! This is automatically handled in \ref VIMSModeSafeSet()
+//!
+//! \note It is highly recommended that the VIMS is put in disabled mode before
+//! \b writing to flash, since the cache will not be updated nor invalidated
+//! by flash writes. The line buffers should also be disabled when updating the
+//! flash. Once \ref VIMSModeSet() is used to set the VIMS in
+//! \ref VIMS_MODE_CHANGING mode, the user should check using
+//! \ref VIMSModeGet() when the mode switches to \ref VIMS_MODE_DISABLED. Only when
+//! the mode has changed the cache has been completely invalidated.
+//!
+//! \note Access from System Bus is never cached. Only access through ICODE
+//! DCODE bus from the System CPU is cached.
+//!
+//! \param ui32Base is the base address of the VIMS.
+//! \param ui32Mode is the operational mode.
+//! - \ref VIMS_MODE_DISABLED (GPRAM enabled)
+//! - \ref VIMS_MODE_ENABLED (CACHE mode)
+//! - \ref VIMS_MODE_OFF
+//!
+//! \return None
+//!
+//! \sa \ref VIMSModeGet() and \ref VIMSModeSafeSet()
+//
+//*****************************************************************************
+extern void VIMSModeSet(uint32_t ui32Base, uint32_t ui32Mode);
+
+//*****************************************************************************
+//
+//! \brief Get the current operational mode of the VIMS.
+//!
+//! This function returns the operational mode of the VIMS.
+//!
+//! \param ui32Base is the base address of the VIMS.
+//!
+//! \return Returns one of:
+//! - \ref VIMS_MODE_CHANGING
+//! - \ref VIMS_MODE_DISABLED (GPRAM enabled)
+//! - \ref VIMS_MODE_ENABLED (CACHE mode)
+//! - \ref VIMS_MODE_OFF
+//!
+//! \sa \ref VIMSModeSet()
+//
+//*****************************************************************************
+extern uint32_t VIMSModeGet(uint32_t ui32Base);
+
+//*****************************************************************************
+//
+//! \brief Set the operational mode of the VIMS in a safe sequence.
+//!
+//! This function sets the operational mode of the VIMS in a safe sequence
+//!
+//! Upon reset the VIMS will be in \ref VIMS_MODE_CHANGING mode.
+//! In this mode the VIMS will initialize the cache (GP) RAM (to all zeros).
+//! The GP RAM will not be operational (read/write will result in bus fault).
+//! The Cache will not be operational (read/write to flash will be uncached).
+//! After a short delay (approx. 1029 clock cycles) the VIMS will
+//! automatically switch mode to \ref VIMS_MODE_DISABLED (GPRAM enabled).
+//!
+//! In \ref VIMS_MODE_DISABLED mode, the cache is disabled but the GP RAM is
+//! accessible:
+//! The GP RAM will be accessible.
+//! The Cache will not be operational.
+//! Reads from flash will be uncached.
+//! From this mode, the VIMS may be put in \ref VIMS_MODE_ENABLED (CACHE mode).
+//!
+//! In \ref VIMS_MODE_ENABLED mode, the cache is enabled for \b USERCODE space.
+//! The GP RAM will not be operational (read/write will result in bus fault).
+//! The Cache will be operational for SYSCODE space.
+//! Reads from flash in USERCODE space will be uncached.
+//!
+//! In \ref VIMS_MODE_OFF the cache RAM is off to conserve power.
+//!
+//! \note The VIMS must be invalidated when switching mode.
+//! This is done by setting VIMS_MODE_OFF before setting any new mode.
+//! This is automatically handled in this function.
+//!
+//! \note It is highly recommended that the VIMS is put in disabled mode before
+//! \b writing to flash, since the cache will not be updated nor invalidated
+//! by flash writes. The line buffers should also be disabled when updating the
+//! flash.
+//!
+//! \note Access from System Bus is never cached. Only access through ICODE
+//! DCODE bus from the System CPU is cached.
+//!
+//! \param ui32Base is the base address of the VIMS.
+//! \param ui32NewMode is the new operational mode:
+//! - \ref VIMS_MODE_DISABLED (GPRAM enabled)
+//! - \ref VIMS_MODE_ENABLED (CACHE mode)
+//! - \ref VIMS_MODE_OFF
+//! \param blocking shall be set to TRUE if further code execution shall be
+//! blocked (delayed) until mode change is completed.
+//!
+//! \return None
+//!
+//! \sa \ref VIMSModeSet() and \ref VIMSModeGet()
+//
+//*****************************************************************************
+extern void VIMSModeSafeSet( uint32_t ui32Base ,
+ uint32_t ui32NewMode ,
+ bool blocking );
+
+//*****************************************************************************
+//
+//! \brief Disable VIMS linebuffers.
+//!
+//! Linebuffers should only be disabled when attempting to update the flash, to
+//! ensure that the content of the buffers is not stale. As soon as flash is
+//! updated the linebuffers should be reenabled. Failing to enable
+//! will have a performance impact.
+//!
+//! \param ui32Base is the base address of the VIMS.
+//!
+//! \return None.
+//
+//*****************************************************************************
+__STATIC_INLINE void
+VIMSLineBufDisable(uint32_t ui32Base)
+{
+ // Disable line buffers
+ HWREG(ui32Base + VIMS_O_CTL) |= VIMS_CTL_IDCODE_LB_DIS_M |
+ VIMS_CTL_SYSBUS_LB_DIS_M;
+}
+
+//*****************************************************************************
+//
+//! \brief Enable VIMS linebuffers.
+//!
+//! Linebuffers should only be disabled when attempting to update the flash, to
+//! ensure that the content of the buffers is not stale. As soon as flash is
+//! updated the linebuffers should be reenabled. Failing to enable
+//! will have a performance impact.
+//!
+//! \param ui32Base is the base address of the VIMS.
+//!
+//! \return None.
+//
+//*****************************************************************************
+__STATIC_INLINE void
+VIMSLineBufEnable(uint32_t ui32Base)
+{
+ // Enable linebuffers
+ HWREG(ui32Base + VIMS_O_CTL) &= ~(VIMS_CTL_IDCODE_LB_DIS_M |
+ VIMS_CTL_SYSBUS_LB_DIS_M);
+}
+
+//*****************************************************************************
+//
+// Support for DriverLib in ROM:
+// Redirect to implementation in ROM when available.
+//
+//*****************************************************************************
+#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
+ #include "../driverlib/rom.h"
+ #ifdef ROM_VIMSConfigure
+ #undef VIMSConfigure
+ #define VIMSConfigure ROM_VIMSConfigure
+ #endif
+ #ifdef ROM_VIMSModeSet
+ #undef VIMSModeSet
+ #define VIMSModeSet ROM_VIMSModeSet
+ #endif
+ #ifdef ROM_VIMSModeGet
+ #undef VIMSModeGet
+ #define VIMSModeGet ROM_VIMSModeGet
+ #endif
+ #ifdef ROM_VIMSModeSafeSet
+ #undef VIMSModeSafeSet
+ #define VIMSModeSafeSet ROM_VIMSModeSafeSet
+ #endif
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __VIMS_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/watchdog.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/watchdog.c
new file mode 100644
index 0000000..3527cff
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/watchdog.c
@@ -0,0 +1,41 @@
+/******************************************************************************
+* Filename: wdt.c
+* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016)
+* Revision: 47179
+*
+* Description: Driver for the Watchdog Timer.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#include "watchdog.h"
+
+// See watchdog.h for implementation
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/watchdog.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/watchdog.h
new file mode 100644
index 0000000..3d8de36
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/watchdog.h
@@ -0,0 +1,520 @@
+/******************************************************************************
+* Filename: wdt.h
+* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017)
+* Revision: 49048
+*
+* Description: Defines and prototypes for the Watchdog Timer.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup peripheral_group
+//! @{
+//! \addtogroup wdt_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __WDT_H__
+#define __WDT_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "../inc/hw_types.h"
+#include "../inc/hw_ints.h"
+#include "../inc/hw_memmap.h"
+#include "../inc/hw_wdt.h"
+#include "debug.h"
+#include "interrupt.h"
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOCK register.
+//
+//*****************************************************************************
+#define WATCHDOG_LOCK_UNLOCKED 0x00000000 // Unlocked
+#define WATCHDOG_LOCK_LOCKED 0x00000001 // Locked
+#define WATCHDOG_LOCK_UNLOCK 0x1ACCE551 // Unlocks the Watchdog Timer
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and
+// WDT_MIS registers.
+//
+//*****************************************************************************
+#define WATCHDOG_INT_TIMEOUT 0x00000001 // Watchdog timer expired
+
+//*****************************************************************************
+//
+// The type of interrupt that can be generated by the watchdog.
+//
+//*****************************************************************************
+#define WATCHDOG_INT_TYPE_INT 0x00000000
+#define WATCHDOG_INT_TYPE_NMI 0x00000004
+
+//*****************************************************************************
+//
+// API Functions and prototypes
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \brief Determines if the watchdog timer is enabled.
+//!
+//! This function checks to see if the watchdog timer is enabled.
+//!
+//! \return Returns status of Watchdog Timer:
+//! - \c true : Watchdog timer is enabled.
+//! - \c false : Watchdog timer is disabled.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+WatchdogRunning(void)
+{
+ // See if the watchdog timer module is enabled, and return.
+ return((HWREG(WDT_BASE + WDT_O_CTL) & WDT_CTL_INTEN) ? true : false);
+}
+
+//*****************************************************************************
+//
+//! \brief Enables the watchdog timer.
+//!
+//! This function enables the watchdog timer counter and interrupt.
+//!
+//! Once enabled, the watchdog interrupt can only be disabled by a hardware reset.
+//!
+//! \note This function has no effect if the watchdog timer has been locked.
+//!
+//! \return None
+//!
+//! \sa \ref WatchdogLock(), \ref WatchdogUnlock()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+WatchdogEnable(void)
+{
+ // Enable the watchdog timer module.
+ HWREGBITW(WDT_BASE + WDT_O_CTL, WDT_CTL_INTEN_BITN) = 1;
+}
+
+//*****************************************************************************
+//
+//! \brief Enables the watchdog timer reset.
+//!
+//! This function enables the capability of the watchdog timer to issue a reset
+//! to the processor after a second timeout condition.
+//!
+//! \note This function has no effect if the watchdog timer has been locked.
+//!
+//! \return None
+//!
+//! \sa \ref WatchdogLock(), \ref WatchdogUnlock()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+WatchdogResetEnable(void)
+{
+ // Enable the watchdog reset.
+ HWREGBITW(WDT_BASE + WDT_O_CTL, WDT_CTL_RESEN_BITN) = 1;
+}
+
+//*****************************************************************************
+//
+//! \brief Disables the watchdog timer reset.
+//!
+//! This function disables the capability of the watchdog timer to issue a
+//! reset to the processor after a second timeout condition.
+//!
+//! \note This function has no effect if the watchdog timer has been locked.
+//!
+//! \return None
+//!
+//! \sa \ref WatchdogLock(), \ref WatchdogUnlock()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+WatchdogResetDisable(void)
+{
+ // Disable the watchdog reset.
+ HWREGBITW(WDT_BASE + WDT_O_CTL, WDT_CTL_RESEN_BITN) = 0;
+}
+
+//*****************************************************************************
+//
+//! \brief Enables the watchdog timer lock mechanism.
+//!
+//! This function locks out write access to the watchdog timer configuration
+//! registers.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+WatchdogLock(void)
+{
+ // Lock out watchdog register writes. Writing anything to the WDT_O_LOCK
+ // register causes the lock to go into effect.
+ HWREG(WDT_BASE + WDT_O_LOCK) = WATCHDOG_LOCK_LOCKED;
+}
+
+//*****************************************************************************
+//
+//! \brief Disables the watchdog timer lock mechanism.
+//!
+//! This function enables write access to the watchdog timer configuration
+//! registers.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+WatchdogUnlock(void)
+{
+ // Unlock watchdog register writes.
+ HWREG(WDT_BASE + WDT_O_LOCK) = WATCHDOG_LOCK_UNLOCK;
+}
+
+//*****************************************************************************
+//
+//! \brief Gets the state of the watchdog timer lock mechanism.
+//!
+//! This function returns the lock state of the watchdog timer registers.
+//!
+//! \return Returns state of lock mechanism.
+//! - \c true : Watchdog timer registers are locked.
+//! - \c false : Registers are not locked.
+//
+//*****************************************************************************
+__STATIC_INLINE bool
+WatchdogLockState(void)
+{
+ // Get the lock state.
+ return((HWREG(WDT_BASE + WDT_O_LOCK) == WATCHDOG_LOCK_LOCKED) ?
+ true : false);
+}
+
+//*****************************************************************************
+//
+//! \brief Sets the watchdog timer reload value.
+//!
+//! This function configures the value to load into the watchdog timer when the
+//! count reaches zero for the first time; if the watchdog timer is running
+//! when this function is called, then the value is immediately loaded into the
+//! watchdog timer counter. If the \c ui32LoadVal parameter is 0, then an
+//! interrupt is immediately generated.
+//!
+//! \note This function has no effect if the watchdog timer has been locked.
+//!
+//! \param ui32LoadVal is the load value for the watchdog timer.
+//!
+//! \return None
+//!
+//! \sa \ref WatchdogLock(), \ref WatchdogUnlock(), \ref WatchdogReloadGet()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+WatchdogReloadSet(uint32_t ui32LoadVal)
+{
+ // Set the load register.
+ HWREG(WDT_BASE + WDT_O_LOAD) = ui32LoadVal;
+}
+
+//*****************************************************************************
+//
+//! \brief Gets the watchdog timer reload value.
+//!
+//! This function gets the value that is loaded into the watchdog timer when
+//! the count reaches zero for the first time.
+//!
+//! \return None
+//!
+//! \sa \ref WatchdogReloadSet()
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+WatchdogReloadGet(void)
+{
+ // Get the load register.
+ return(HWREG(WDT_BASE + WDT_O_LOAD));
+}
+
+//*****************************************************************************
+//
+//! \brief Gets the current watchdog timer value.
+//!
+//! This function reads the current value of the watchdog timer.
+//!
+//! \return Returns the current value of the watchdog timer.
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+WatchdogValueGet(void)
+{
+ // Get the current watchdog timer register value.
+ return(HWREG(WDT_BASE + WDT_O_VALUE));
+}
+
+//*****************************************************************************
+//
+//! \brief Registers an interrupt handler for the watchdog timer interrupt in the dynamic interrupt table.
+//!
+//! \note Only use this function if you want to use the dynamic vector table (in SRAM)!
+//!
+//! This function registers a function as the interrupt handler for a specific
+//! interrupt and enables the corresponding interrupt in the interrupt controller.
+//!
+//! The watchdog timer interrupt must be enabled via \ref WatchdogIntEnable(). It is the
+//! interrupt handler's responsibility to clear the interrupt source via
+//! \ref WatchdogIntClear().
+//!
+//! \note This function registers the standard watchdog interrupt handler. To
+//! register the NMI watchdog handler, use \ref IntRegister() to register the
+//! handler for the \b INT_NMI_FAULT interrupt.
+//!
+//! \param pfnHandler is a pointer to the function to be called when the
+//! watchdog timer interrupt occurs.
+//!
+//! \return None
+//!
+//! \sa \ref IntRegister() for important information about registering interrupt
+//! handlers.
+//
+//*****************************************************************************
+__STATIC_INLINE void
+WatchdogIntRegister(void (*pfnHandler)(void))
+{
+ // Register the interrupt handler.
+ IntRegister(INT_WDT_IRQ, pfnHandler);
+
+ // Enable the watchdog timer interrupt.
+ IntEnable(INT_WDT_IRQ);
+}
+
+//*****************************************************************************
+//
+//! \brief Unregisters an interrupt handler for the watchdog timer interrupt in the dynamic interrupt table.
+//!
+//! This function does the actual unregistering of the interrupt handler. This
+//! function clears the handler to be called when a watchdog timer interrupt
+//! occurs. This function also masks off the interrupt in the interrupt
+//! controller so that the interrupt handler no longer is called.
+//!
+//! \note This function registers the standard watchdog interrupt handler. To
+//! register the NMI watchdog handler, use \ref IntRegister() to register the
+//! handler for the \b INT_NMI_FAULT interrupt.
+//!
+//! \return None
+//!
+//! \sa \ref IntRegister() for important information about registering interrupt
+//! handlers.
+//
+//*****************************************************************************
+__STATIC_INLINE void
+WatchdogIntUnregister(void)
+{
+ // Disable the interrupt.
+ IntDisable(INT_WDT_IRQ);
+
+ // Unregister the interrupt handler.
+ IntUnregister(INT_WDT_IRQ);
+}
+
+//*****************************************************************************
+//
+//! \brief Enables the watchdog timer.
+//!
+//! This function enables the watchdog timer interrupt by calling \ref WatchdogEnable().
+//!
+//! \return None
+//!
+//! \sa \ref WatchdogEnable()
+//
+//*****************************************************************************
+__STATIC_INLINE void
+WatchdogIntEnable(void)
+{
+ // Enable the Watchdog interrupt.
+ WatchdogEnable();
+}
+
+//*****************************************************************************
+//
+//! \brief Gets the current watchdog timer interrupt status.
+//!
+//! This function returns the interrupt status for the watchdog timer module.
+//!
+//! \return Returns the interrupt status.
+//! - 1 : Watchdog time-out has occurred.
+//! - 0 : Watchdog time-out has not occurred.
+//!
+//! \sa \ref WatchdogIntClear();
+//
+//*****************************************************************************
+__STATIC_INLINE uint32_t
+WatchdogIntStatus(void)
+{
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ return(HWREG(WDT_BASE + WDT_O_RIS));
+}
+
+//*****************************************************************************
+//
+//! \brief Clears the watchdog timer interrupt.
+//!
+//! The watchdog timer interrupt source is cleared, so that it no longer
+//! asserts.
+//!
+//! \note Due to write buffers and synchronizers in the system it may take several
+//! clock cycles from a register write clearing an event in a module and until the
+//! event is actually cleared in the NVIC of the system CPU. It is recommended to
+//! clear the event source early in the interrupt service routine (ISR) to allow
+//! the event clear to propagate to the NVIC before returning from the ISR.
+//! At the same time, an early event clear allows new events of the same type to be
+//! pended instead of ignored if the event is cleared later in the ISR.
+//! It is the responsibility of the programmer to make sure that enough time has passed
+//! before returning from the ISR to avoid false re-triggering of the cleared event.
+//! A simple, although not necessarily optimal, way of clearing an event before
+//! returning from the ISR is:
+//! -# Write to clear event (interrupt source). (buffered write)
+//! -# Dummy read from the event source module. (making sure the write has propagated)
+//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers)
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+WatchdogIntClear(void)
+{
+ // Clear the interrupt source.
+ HWREG(WDT_BASE + WDT_O_ICR) = WATCHDOG_INT_TIMEOUT;
+}
+
+//*****************************************************************************
+//
+//! \brief Sets the type of interrupt generated by the watchdog.
+//!
+//! This function sets the type of interrupt that is generated if the watchdog
+//! timer expires.
+//!
+//! When configured to generate an NMI, the watchdog interrupt must still be
+//! enabled with \ref WatchdogIntEnable(), and it must still be cleared inside the
+//! NMI handler with \ref WatchdogIntClear().
+//!
+//! \param ui32Type is the type of interrupt to generate.
+//! - \ref WATCHDOG_INT_TYPE_INT : Generate a standard interrupt (default).
+//! - \ref WATCHDOG_INT_TYPE_NMI : Generate a non-maskable interrupt (NMI).
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+WatchdogIntTypeSet(uint32_t ui32Type)
+{
+ // Check the arguments.
+ ASSERT((ui32Type == WATCHDOG_INT_TYPE_INT) ||
+ (ui32Type == WATCHDOG_INT_TYPE_NMI));
+
+ // Set the interrupt type.
+ HWREGBITW(WDT_BASE + WDT_O_CTL, WDT_CTL_INTTYPE_BITN) = (ui32Type == WATCHDOG_INT_TYPE_INT)? 0 : 1;
+}
+
+//*****************************************************************************
+//
+//! \brief Enables stalling of the watchdog timer during debug events.
+//!
+//! This function allows the watchdog timer to stop counting when the processor
+//! is stopped by the debugger. By doing so, the watchdog is prevented from
+//! expiring and resetting the system (if reset is enabled). The watchdog instead expires
+//! after the appropriate number of processor cycles have been executed while
+//! debugging (or at the appropriate time after the processor has been
+//! restarted).
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+WatchdogStallEnable(void)
+{
+ // Enable timer stalling.
+ HWREGBITW(WDT_BASE + WDT_O_TEST, WDT_TEST_STALL_BITN) = 1;
+}
+
+//*****************************************************************************
+//
+//! \brief Disables stalling of the watchdog timer during debug events.
+//!
+//! This function disables the debug mode stall of the watchdog timer. By
+//! doing so, the watchdog timer continues to count regardless of the processor
+//! debug state.
+//!
+//! \return None
+//
+//*****************************************************************************
+__STATIC_INLINE void
+WatchdogStallDisable(void)
+{
+ // Disable timer stalling.
+ HWREGBITW(WDT_BASE + WDT_O_TEST, WDT_TEST_STALL_BITN) = 0;
+}
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __WDT_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/watchdog_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/watchdog_doc.h
new file mode 100644
index 0000000..ef1f239
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/watchdog_doc.h
@@ -0,0 +1,121 @@
+/******************************************************************************
+* Filename: watchdog_doc.h
+* Revised: 2018-02-09 15:45:36 +0100 (Fri, 09 Feb 2018)
+* Revision: 51470
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+//! \addtogroup wdt_api
+//! @{
+//! \section sec_wdt Introduction
+//!
+//! The Watchdog Timer (WDT) allows the application to regain control if the system stalls due to
+//! unexpected software behavior. The WDT can generate a normal interrupt or a non-maskable interrupt
+//! on the first time-out and a system reset on the following time-out if the application fails to
+//! restart the WDT.
+//!
+//! WDT has the following features:
+//! - 32-bit down counter with a configurable load register.
+//! - Configurable interrupt generation logic with interrupt masking and optional NMI function.
+//! - Optional reset generation.
+//! - Register protection from runaway software (lock).
+//! - User-enabled stalling when the system CPU asserts the CPU Halt flag during debug.
+//!
+//! The WDT runs at system HF clock divided by 32; however, when in powerdown it runs at
+//! LF clock (32 kHz) - if the LF clock to the MCU domain is enabled.
+//!
+//! If application does not restart the WDT, using \ref WatchdogIntClear(), before a time-out:
+//! - At the first time-out the WDT asserts the interrupt, reloads the 32-bit counter with the load
+//! value, and resumes counting down from that value.
+//! - If the WDT counts down to zero again before the application clears the interrupt, and the
+//! reset signal has been enabled, the WDT asserts its reset signal to the system.
+//!
+//! \note By default, a "warm reset" triggers a pin reset and thus reboots the device.
+//!
+//! A reset caused by the WDT can be detected as a "warm reset" using \ref SysCtrlResetSourceGet().
+//! However, it is not possible to detect which of the warm reset sources that caused the reset.
+//!
+//! Typical use case:
+//! - Use \ref WatchdogIntTypeSet() to select either standard interrupt or non-maskable interrupt on
+//! first time-out.
+//! - The application must implement an interrupt handler for the selected interrupt type. If
+//! application uses the \e static vector table (see startup_<compiler>.c) the interrupt
+//! handlers for standard interrupt and non-maskable interrupt are named WatchdogIntHandler()
+//! and NmiSR() respectively. For more information about \e static and \e dynamic vector table,
+//! see \ref sec_interrupt_table.
+//! - Use \ref WatchdogResetEnable() to enable reset on second time-out.
+//! - Use \ref WatchdogReloadSet() to set (re)load value of the counter.
+//! - Use \ref WatchdogEnable() to start the WDT counter. The WDT counts down from the load value.
+//! - Use \ref WatchdogLock() to lock WDT configuration to prevent unintended re-configuration.
+//! - Application must use \ref WatchdogIntClear() to restart the counter before WDT times out.
+//! - If application does not restart the counter before it reaches zero (times out) the WDT asserts
+//! the selected type of interrupt, reloads the counter, and starts counting down again.
+//! - The interrupt handler triggered by the first time-out can be used to log debug information
+//! or try to enter a safe "pre-reset" state in order to have a more graceful reset when the WDT
+//! times out the second time.
+//! - It is \b not recommended that the WDT interrupt handler clears the WDT interrupt and thus
+//! reloads the WDT counter. This means that the WDT interrupt handler never returns.
+//! - If the application does not clear the WDT interrupt and the WDT times out when the interrupt
+//! is still asserted then WDT triggers a reset (if enabled).
+//!
+//! \section sec_wdt_api API
+//!
+//! The API functions can be grouped like this:
+//!
+//! Watchdog configuration:
+//! - \ref WatchdogIntTypeSet()
+//! - \ref WatchdogResetEnable()
+//! - \ref WatchdogResetDisable()
+//! - \ref WatchdogReloadSet()
+//! - \ref WatchdogEnable()
+//!
+//! Status:
+//! - \ref WatchdogRunning()
+//! - \ref WatchdogValueGet()
+//! - \ref WatchdogReloadGet()
+//! - \ref WatchdogIntStatus()
+//!
+//! Interrupt configuration:
+//! - \ref WatchdogIntEnable()
+//! - \ref WatchdogIntClear()
+//! - \ref WatchdogIntRegister()
+//! - \ref WatchdogIntUnregister()
+//!
+//! Register protection:
+//! - \ref WatchdogLock()
+//! - \ref WatchdogLockState()
+//! - \ref WatchdogUnlock()
+//!
+//! Stall configuration for debugging:
+//! - \ref WatchdogStallDisable()
+//! - \ref WatchdogStallEnable()
+//!
+//! @}
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/asmdefs.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/asmdefs.h
new file mode 100644
index 0000000..9e5a815
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/asmdefs.h
@@ -0,0 +1,151 @@
+/******************************************************************************
+* Filename: asmdefs.h
+* Revised: 2015-06-05 14:39:10 +0200 (Fri, 05 Jun 2015)
+* Revision: 43803
+*
+* Description: Macros to allow assembly code be portable among tool chains.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __ASMDEFS_H__
+#define __ASMDEFS_H__
+
+//*****************************************************************************
+//
+// The defines required for EW-ARM.
+//
+//*****************************************************************************
+#ifdef __IAR_SYSTEMS_ICC__
+
+//
+// Section headers.
+//
+#define __LIBRARY__ module
+#define __TEXT__ rseg CODE:CODE(2)
+#define __DATA__ rseg DATA:DATA(2)
+#define __BSS__ rseg DATA:DATA(2)
+#define __TEXT_NOROOT__ rseg CODE:CODE:NOROOT(2)
+
+//
+// Assembler mnemonics.
+//
+#define __ALIGN__ alignrom 2
+#define __END__ end
+#define __EXPORT__ export
+#define __IMPORT__ import
+#define __LABEL__
+#define __STR__ dcb
+#define __THUMB_LABEL__ thumb
+#define __WORD__ dcd
+#define __INLINE_DATA__ data
+
+#endif // __IAR_SYSTEMS_ICC__
+
+//*****************************************************************************
+//
+// The defines required for GCC.
+//
+//*****************************************************************************
+#if defined(__GNUC__)
+
+//
+// The assembly code preamble required to put the assembler into the correct
+// configuration.
+//
+ .syntax unified
+ .thumb
+
+//
+// Section headers.
+//
+#define __LIBRARY__ @
+#define __TEXT__ .text
+#define __DATA__ .data
+#define __BSS__ .bss
+#define __TEXT_NOROOT__ .text
+
+//
+// Assembler mnemonics.
+//
+#define __ALIGN__ .balign 4
+#define __END__ .end
+#define __EXPORT__ .globl
+#define __IMPORT__ .extern
+#define __LABEL__ :
+#define __STR__ .ascii
+#define __THUMB_LABEL__ .thumb_func
+#define __WORD__ .word
+#define __INLINE_DATA__
+
+#endif // __GNUC__
+
+//*****************************************************************************
+//
+// The defines required for RV-MDK.
+//
+//*****************************************************************************
+#if defined(__CC_ARM)
+
+//
+// The assembly code preamble required to put the assembler into the correct
+// configuration.
+//
+ thumb
+ require8
+ preserve8
+
+//
+// Section headers.
+//
+#define __LIBRARY__ ;
+#define __TEXT__ area ||.text||, code, readonly, align=2
+#define __DATA__ area ||.data||, data, align=2
+#define __BSS__ area ||.bss||, noinit, align=2
+#define __TEXT_NOROOT__ area ||.text||, code, readonly, align=2
+
+//
+// Assembler mnemonics.
+//
+#define __ALIGN__ align 4
+#define __END__ end
+#define __EXPORT__ export
+#define __IMPORT__ import
+#define __LABEL__
+#define __STR__ dcb
+#define __THUMB_LABEL__
+#define __WORD__ dcd
+#define __INLINE_DATA__
+
+#endif // __CC_ARM
+
+
+#endif // __ASMDEF_H__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_adi.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_adi.h
new file mode 100644
index 0000000..b14a5f6
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_adi.h
@@ -0,0 +1,1182 @@
+/******************************************************************************
+* Filename: hw_adi.h
+* Revised: 2015-01-13 16:59:55 +0100 (Tue, 13 Jan 2015)
+* Revision: 42365
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_ADI_H__
+#define __HW_ADI_H__
+
+//*****************************************************************************
+//
+// This file contains macros for controlling the ADI master and
+// accessing ADI slave registers via the ADI Master.
+// There are 3 categories of macros in this file:
+// - macros that provide an offset to a register
+// located within the DDI Master itself.
+// - macros that define bits or bitfields
+// within the DDI Master Registers.
+// - macros that provide an "instruction offset"
+// that are used when accessing a ADI Slave.
+//
+// The macros that that provide ADI Master register offsets and
+// define bits and bitfields for those registers are the typical
+// macros that appear in most hw_<module>.h header files. In
+// the following example ADI_O_SLAVECONF is a macro for a
+// register offset and ADI_SLAVECONF_WAITFORACK is a macro for
+// a bit in that register. This example code will set the WAITFORACK
+// bit in register ADI_O_SLAVECONF of the ADI Master. (Note: this
+// access the Master not the Slave).
+//
+// HWREG(ADI3_BASE + ADI_O_SLAVECONF) |= ADI_SLAVECONF_WAITFORACK;
+//
+// The "instruction offset" macros are used to pass an instruction to
+// the ADI Master when accessing ADI slave registers. These macros are
+// only used when accessing ADI Slave Registers. (Remember ADI
+// Master Registers are accessed normally).
+//
+// The instructions supported when accessing an ADI Slave Register follow:
+// - Direct Access to an ADI Slave register. I.e. read or
+// write the register.
+// - Set the specified bits in a ADI Slave register.
+// - Clear the specified bits in a ADI Slave register.
+// - Mask write of 4 bits to the a ADI Slave register.
+// - Mask write of 8 bits to the a ADI Slave register.
+// - Mask write of 16 bits to the a ADI Slave register.
+//
+// Note: only the "Direct Access" offset should be used when reading
+// a ADI Slave register. Only 4-bit reads are supported and 8 bits write are
+// supported natively. If accessing wider bitfields, the read/write operation
+// will be spread out over a number of transactions. This is hidden for the
+// user, but can potentially be very timeconsuming. Especially of running
+// on a slow clock.
+//
+// The generic format of using these macros for a read follows:
+// // Read low 8-bits in ADI_SLAVE_OFF
+// myushortvar = HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR);
+//
+// // Read high 8-bits in ADI_SLAVE_OFF (data[31:16])
+// myushortvar = HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR);
+//
+// Notes: In the above example:
+// - ADI_MASTER_BASE is the base address of the ADI Master defined
+// in the hw_memmap.h header file.
+// - ADI_SLAVE_OFF is the ADI Slave offset defined in the
+// hw_<adi_slave>.h header file (e.g. hw_adi_3_refsys_top.h for the refsys
+// module).
+// - ADI_O_DIR is the "instruction offset" macro defined in this
+// file that specifies the Direct Access instruction.
+//
+// Writes can use any of the "instruction macros".
+// The following examples do a "direct write" to an ADI Slave register
+// ADI_SLAVE_OFF using different size operands:
+//
+// // ---------- DIRECT WRITES ----------
+// // Write 32-bits aligned
+// HWREG(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR) = 0x12345678;
+//
+// // Write 16-bits aligned to high 16-bits then low 16-bits
+// // Add 2 to get to high 16-bits.
+// HWREGH(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 2) = 0xabcd;
+// HWREGH(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR) = 0xef01;
+//
+// // Write each byte at ADI_SLAVE_OFF, one at a time.
+// // Add 1,2,or 3 to get to bytes 1,2, or 3.
+// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR) = 0x33;
+// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 1) = 0x44;
+// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 2) = 0x55;
+// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 3) = 0x66;
+//
+// // ---------- SET/CLR ----------
+// The set and clear functions behave similarly to eachother. Each
+// can be performed on an 8-, 16-, or 32-bit operand.
+// Examples follow:
+// // Set all odd bits in a 32-bit words
+// HWREG(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_SET) = 0xaaaaaaaa;
+//
+// // Clear all bits in byte 2 (data[23:16]) using 32-bit operand
+// HWREG(DDI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_CLR) = 0x00ff0000;
+//
+// // Set even bits in byte 2 (data[23:16]) using 8-bit operand
+// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + 2 + ADI_O_CLR) = 0x55;
+//
+// // ---------- MASKED WRITES ----------
+// The mask writes are a bit different. They operate on nibbles,
+// bytes, and 16-bit elements. Two operands are required; a 'mask'
+// and 'data'; The operands are concatenated and written to the master.
+// e.g. the mask and data are combined as follows for a 16 bit masked
+// write:
+// (mask << 16) | data;
+// Examples follow:
+//
+// // Do an 4 bit masked write (Nibble) of 7 to data[3:0]).
+// // Byte write is needed.
+// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_MASK4B01) = 0xf7;
+//
+// // Do an 4 bit masked write of 4 to data[7:4]).
+// // Add 1 for next nibble
+// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + ADI_O_MASK4B01 + 1) = 0xf4;
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// The following are defines for the ADI master instruction offsets.
+//
+//*****************************************************************************
+#define ADI_O_DIR 0x00000000 // Offset for the direct access
+ // instruction
+#define ADI_O_SET 0x00000010 // Offset for 'Set' instruction.
+#define ADI_O_CLR 0x00000020 // Offset for 'Clear' instruction.
+#define ADI_O_MASK4B 0x00000040 // Offset for 4-bit masked access.
+ // Data bit[n] is written if mask
+ // bit[n] is set ('1').
+ // Bits 7:4 are mask. Bits 3:0 are data.
+ // Requires 'byte' write.
+#define ADI_O_MASK8B 0x00000060 // Offset for 8-bit masked access.
+ // Data bit[n] is written if mask
+ // bit[n] is set ('1'). Bits 15:8 are
+ // mask. Bits 7:0 are data. Requires
+ // 'short' write.
+#define ADI_O_MASK16B 0x00000080 // Offset for 16-bit masked access.
+ // Data bit[n] is written if mask
+ // bit[n] is set ('1'). Bits 31:16
+ // are mask. Bits 15:0 are data.
+ // Requires 'long' write.
+
+//*****************************************************************************
+//
+// The following are defines for the ADI register offsets.
+//
+//*****************************************************************************
+#define ADI_O_SLAVESTAT 0x00000030 // ADI Slave status register
+#define ADI_O_SLAVECONF 0x00000038 // ADI Master configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADI_O_SLAVESTAT register.
+//
+//*****************************************************************************
+#define ADI_SLAVESTAT_DI_REQ 0x00000002 // Read current value of DI_REQ
+ // signal. Writing 0 to this bit
+ // forces a sync with slave,
+ // ensuring that req will be 0. It
+ // is recommended to write 0 to
+ // this register before power down
+ // of the master.
+#define ADI_SLAVESTAT_DI_REQ_M 0x00000002
+#define ADI_SLAVESTAT_DI_REQ_S 1
+#define ADI_SLAVESTAT_DI_ACK 0x00000001 // Read current value of DI_ACK
+ // signal
+#define ADI_SLAVESTAT_DI_ACK_M 0x00000001
+#define ADI_SLAVESTAT_DI_ACK_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADI_O_SLAVECONF register.
+//
+//*****************************************************************************
+#define ADI_SLAVECONF_CONFLOCK 0x00000080 // This register is no longer
+ // accessible when this bit is set.
+ // (unless sticky_bit_overwrite is
+ // asserted on top module)
+#define ADI_SLAVECONF_CONFLOCK_M \
+ 0x00000080
+#define ADI_SLAVECONF_CONFLOCK_S 7
+#define ADI_SLAVECONF_WAITFORACK \
+ 0x00000004 // A transaction on the ADI
+ // interface does not end until ack
+ // has been received from the slave
+ // when this bit is set.
+
+#define ADI_SLAVECONF_WAITFORACK_M \
+ 0x00000004
+#define ADI_SLAVECONF_WAITFORACK_S 2
+#define ADI_SLAVECONF_ADICLKSPEED_M \
+ 0x00000003 // Sets the period of an ADI
+ // transactions. All transactions
+ // takes an even number of clock
+ // cycles,- ADI clock rising edge
+ // occurs in the middle of the
+ // period. Data and ctrl to slave
+ // is set up in beginning of cycle,
+ // and data from slave is read in
+ // after the transaction 00: An ADI
+ // transaction takes 2 master clock
+ // cyclkes 01: An ADI transaction
+ // takes 4 master clock cycles 10:
+ // And ADI Transaction takes 8
+ // master clock cycles 11: An ADI
+ // transaction takes 16 master
+ // clock cycles
+
+#define ADI_SLAVECONF_ADICLKSPEED_S 0
+
+//*****************************************************************************
+//
+// The following are defines pseudo-magic numbers that should go away.
+// New code should not use these registers and old code should be ported
+// to not use these.
+//
+//*****************************************************************************
+#define ADI_O_DIR03 0x00000000 // Direct access for adi byte
+ // offsets 0 to 3
+#define ADI_O_DIR47 0x00000004 // Direct access for adi byte
+ // offsets 4 to 7
+#define ADI_O_DIR811 0x00000008 // Direct access for adi byte
+ // offsets 8 to 11
+#define ADI_O_DIR1215 0x0000000C // Direct access for adi byte
+ // offsets 12 to 15
+#define ADI_O_SET03 0x00000010 // Set register for ADI byte
+ // offsets 0 to 3
+#define ADI_O_SET47 0x00000014 // Set register for ADI byte
+ // offsets 4 to 7
+#define ADI_O_SET811 0x00000018 // Set register for ADI byte
+ // offsets 8 to 11
+#define ADI_O_SET1215 0x0000001C // Set register for ADI byte
+ // offsets 12 to 15
+#define ADI_O_CLR03 0x00000020 // Clear register for ADI byte
+ // offsets 0 to 3
+#define ADI_O_CLR47 0x00000024 // Clear register for ADI byte
+ // offsets 4 to 7
+#define ADI_O_CLR811 0x00000028 // Clear register for ADI byte
+ // offsets 8 to 11
+#define ADI_O_CLR1215 0x0000002C // Clear register for ADI byte
+ // offsets 12 to 15
+#define ADI_O_SLAVESTAT 0x00000030 // ADI Slave status register
+#define ADI_O_SLAVECONF 0x00000038 // ADI Master configuration
+ // register
+#define ADI_O_MASK4B01 0x00000040 // Masked access (4m/4d) for ADI
+ // Registers at byte offsets 0 and
+ // 1
+#define ADI_O_MASK4B23 0x00000044 // Masked access (4m/4d) for ADI
+ // Registers at byte offsets 2 and
+ // 3
+#define ADI_O_MASK4B45 0x00000048 // Masked access (4m/4d) for ADI
+ // Registers at byte offsets 4 and
+ // 5
+#define ADI_O_MASK4B67 0x0000004C // Masked access (4m/4d) for ADI
+ // Registers at byte offsets 6 and
+ // 7
+#define ADI_O_MASK4B89 0x00000050 // Masked access (4m/4d) for ADI
+ // Registers at byte offsets 8 and
+ // 9
+#define ADI_O_MASK4B1011 0x00000054 // Masked access (4m/4d) for ADI
+ // Registers at byte offsets 10 and
+ // 11
+#define ADI_O_MASK4B1213 0x00000058 // Masked access (4m/4d) for ADI
+ // Registers at byte offsets 12 and
+ // 13
+#define ADI_O_MASK4B1415 0x0000005C // Masked access (4m/4d) for ADI
+ // Registers at byte offsets 14 and
+ // 15
+#define ADI_O_MASK8B01 0x00000060 // Masked access (8m/8d) for ADI
+ // Registers at byte offsets 0 and
+ // 1
+#define ADI_O_MASK8B23 0x00000064 // Masked access (8m/8d) for ADI
+ // Registers at byte offsets 2 and
+ // 3
+#define ADI_O_MASK8B45 0x00000068 // Masked access (8m/8d) for ADI
+ // Registers at byte offsets 4 and
+ // 5
+#define ADI_O_MASK8B67 0x0000006C // Masked access (8m/8d) for ADI
+ // Registers at byte offsets 6 and
+ // 7
+#define ADI_O_MASK8B89 0x00000070 // Masked access (8m/8d) for ADI
+ // Registers at byte offsets 8 and
+ // 9
+#define ADI_O_MASK8B1011 0x00000074 // Masked access (8m/8d) for ADI
+ // Registers at byte offsets 10 and
+ // 11
+#define ADI_O_MASK8B1213 0x00000078 // Masked access (8m/8d) for ADI
+ // Registers at byte offsets 12 and
+ // 13
+#define ADI_O_MASK8B1415 0x0000007C // Masked access (8m/8d) for ADI
+ // Registers at byte offsets 14 and
+ // 15
+#define ADI_O_MASK16B01 0x00000080 // Masked access (16m/16d) for ADI
+ // Registers at byte offsets 0 and
+ // 1
+#define ADI_O_MASK16B23 0x00000084 // Masked access (16m/16d) for ADI
+ // Registers at byte offsets 2 and
+ // 3
+#define ADI_O_MASK16B45 0x00000088 // Masked access (16m/16d) for ADI
+ // Registers at byte offsets 4 and
+ // 5
+#define ADI_O_MASK16B67 0x0000008C // Masked access (16m/16d) for ADI
+ // Registers at byte offsets 6 and
+ // 7
+#define ADI_O_MASK16B89 0x00000090 // Masked access (16m/16d) for ADI
+ // Registers at byte offsets 8 and
+ // 9
+#define ADI_O_MASK16B1011 0x00000094 // Masked access (16m/16d) for ADI
+ // Registers at byte offsets 10 and
+ // 11
+#define ADI_O_MASK16B1213 0x00000098 // Masked access (16m/16d) for ADI
+ // Registers at byte offsets 12 and
+ // 13
+#define ADI_O_MASK16B1415 0x0000009C // Masked access (16m/16d) for ADI
+ // Registers at byte offsets 14 and
+ // 15
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADI_O_DIR03 register.
+//
+//*****************************************************************************
+#define ADI_DIR03_B3_M 0xFF000000 // Direct access to ADI register 3
+#define ADI_DIR03_B3_S 24
+#define ADI_DIR03_B2_M 0x00FF0000 // Direct access to ADI register 2
+#define ADI_DIR03_B2_S 16
+#define ADI_DIR03_B1_M 0x0000FF00 // Direct access to ADI register 1
+#define ADI_DIR03_B1_S 8
+#define ADI_DIR03_B0_M 0x000000FF // Direct access to ADI register 0
+#define ADI_DIR03_B0_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADI_O_DIR47 register.
+//
+//*****************************************************************************
+#define ADI_DIR47_B3_M 0xFF000000 // Direct access to ADI register 7
+#define ADI_DIR47_B3_S 24
+#define ADI_DIR47_B2_M 0x00FF0000 // Direct access to ADI register 6
+#define ADI_DIR47_B2_S 16
+#define ADI_DIR47_B1_M 0x0000FF00 // Direct access to ADI register 5
+#define ADI_DIR47_B1_S 8
+#define ADI_DIR47_B0_M 0x000000FF // Direct access to ADI register 4
+#define ADI_DIR47_B0_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADI_O_DIR811 register.
+//
+//*****************************************************************************
+#define ADI_DIR811_B3_M 0xFF000000 // Direct access to ADI register
+ // 11
+#define ADI_DIR811_B3_S 24
+#define ADI_DIR811_B2_M 0x00FF0000 // Direct access to ADI register
+ // 10
+#define ADI_DIR811_B2_S 16
+#define ADI_DIR811_B1_M 0x0000FF00 // Direct access to ADI register 9
+#define ADI_DIR811_B1_S 8
+#define ADI_DIR811_B0_M 0x000000FF // Direct access to ADI register 8
+#define ADI_DIR811_B0_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADI_O_DIR1215 register.
+//
+//*****************************************************************************
+#define ADI_DIR1215_B3_M 0xFF000000 // Direct access to ADI register
+ // 15
+#define ADI_DIR1215_B3_S 24
+#define ADI_DIR1215_B2_M 0x00FF0000 // Direct access to ADI register
+ // 14
+#define ADI_DIR1215_B2_S 16
+#define ADI_DIR1215_B1_M 0x0000FF00 // Direct access to ADI register
+ // 13
+#define ADI_DIR1215_B1_S 8
+#define ADI_DIR1215_B0_M 0x000000FF // Direct access to ADI register
+ // 12
+#define ADI_DIR1215_B0_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADI_O_SET03 register.
+//
+//*****************************************************************************
+#define ADI_SET03_S3_M 0xFF000000 // A high bit value will set the
+ // corresponding bit in ADI
+ // register 3. Read returns 0.
+#define ADI_SET03_S3_S 24
+#define ADI_SET03_S2_M 0x00FF0000 // A high bit value will set the
+ // corresponding bit in ADI
+ // register 2. Read returns 0.
+#define ADI_SET03_S2_S 16
+#define ADI_SET03_S1_M 0x0000FF00 // A high bit value will set the
+ // corresponding bit in ADI
+ // register 1. Read returns 0.
+#define ADI_SET03_S1_S 8
+#define ADI_SET03_S0_M 0x000000FF // A high bit value will set the
+ // corresponding bit in ADI
+ // register 0. Read returns 0.
+#define ADI_SET03_S0_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADI_O_SET47 register.
+//
+//*****************************************************************************
+#define ADI_SET47_S3_M 0xFF000000 // A high bit value will set the
+ // corresponding bit in ADI
+ // register 7. Read returns 0.
+#define ADI_SET47_S3_S 24
+#define ADI_SET47_S2_M 0x00FF0000 // A high bit value will set the
+ // corresponding bit in ADI
+ // register 6. Read returns 0.
+#define ADI_SET47_S2_S 16
+#define ADI_SET47_S1_M 0x0000FF00 // A high bit value will set the
+ // corresponding bit in ADI
+ // register 5. Read returns 0.
+#define ADI_SET47_S1_S 8
+#define ADI_SET47_S0_M 0x000000FF // A high bit value will set the
+ // corresponding bit in ADI
+ // register 4. Read returns 0.
+#define ADI_SET47_S0_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADI_O_SET811 register.
+//
+//*****************************************************************************
+#define ADI_SET811_S3_M 0xFF000000 // A high bit value will set the
+ // corresponding bit in ADI
+ // register 11. Read returns 0.
+#define ADI_SET811_S3_S 24
+#define ADI_SET811_S2_M 0x00FF0000 // A high bit value will set the
+ // corresponding bit in ADI
+ // register 10. Read returns 0.
+#define ADI_SET811_S2_S 16
+#define ADI_SET811_S1_M 0x0000FF00 // A high bit value will set the
+ // corresponding bit in ADI
+ // register 9. Read returns 0.
+#define ADI_SET811_S1_S 8
+#define ADI_SET811_S0_M 0x000000FF // A high bit value will set the
+ // corresponding bit in ADI
+ // register 8. Read returns 0.
+#define ADI_SET811_S0_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADI_O_SET1215 register.
+//
+//*****************************************************************************
+#define ADI_SET1215_S3_M 0xFF000000 // A high bit value will set the
+ // corresponding bit in ADI
+ // register 15. Read returns 0.
+#define ADI_SET1215_S3_S 24
+#define ADI_SET1215_S2_M 0x00FF0000 // A high bit value will set the
+ // corresponding bit in ADI
+ // register 14. Read returns 0.
+#define ADI_SET1215_S2_S 16
+#define ADI_SET1215_S1_M 0x0000FF00 // A high bit value will set the
+ // corresponding bit in ADI
+ // register 13. Read returns 0.
+#define ADI_SET1215_S1_S 8
+#define ADI_SET1215_S0_M 0x000000FF // A high bit value will set the
+ // corresponding bit in ADI
+ // register 12. Read returns 0.
+#define ADI_SET1215_S0_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADI_O_CLR03 register.
+//
+//*****************************************************************************
+#define ADI_CLR03_S3_M 0xFF000000 // A high bit value will clear the
+ // corresponding bit in ADI
+ // register 3
+#define ADI_CLR03_S3_S 24
+#define ADI_CLR03_S2_M 0x00FF0000 // A high bit value will clear the
+ // corresponding bit in ADI
+ // register 2
+#define ADI_CLR03_S2_S 16
+#define ADI_CLR03_S1_M 0x0000FF00 // A high bit value will clear the
+ // corresponding bit in ADI
+ // register 1
+#define ADI_CLR03_S1_S 8
+#define ADI_CLR03_S0_M 0x000000FF // A high bit value will clear the
+ // corresponding bit in ADI
+ // register 0
+#define ADI_CLR03_S0_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADI_O_CLR47 register.
+//
+//*****************************************************************************
+#define ADI_CLR47_S3_M 0xFF000000 // A high bit value will clear the
+ // corresponding bit in ADI
+ // register 7
+#define ADI_CLR47_S3_S 24
+#define ADI_CLR47_S2_M 0x00FF0000 // A high bit value will clear the
+ // corresponding bit in ADI
+ // register 6
+#define ADI_CLR47_S2_S 16
+#define ADI_CLR47_S1_M 0x0000FF00 // A high bit value will clear the
+ // corresponding bit in ADI
+ // register 5
+#define ADI_CLR47_S1_S 8
+#define ADI_CLR47_S0_M 0x000000FF // A high bit value will clear the
+ // corresponding bit in ADI
+ // register 4
+#define ADI_CLR47_S0_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADI_O_CLR811 register.
+//
+//*****************************************************************************
+#define ADI_CLR811_S3_M 0xFF000000 // A high bit value will clear the
+ // corresponding bit in ADI
+ // register 11
+#define ADI_CLR811_S3_S 24
+#define ADI_CLR811_S2_M 0x00FF0000 // A high bit value will clear the
+ // corresponding bit in ADI
+ // register 10
+#define ADI_CLR811_S2_S 16
+#define ADI_CLR811_S1_M 0x0000FF00 // A high bit value will clear the
+ // corresponding bit in ADI
+ // register 9
+#define ADI_CLR811_S1_S 8
+#define ADI_CLR811_S0_M 0x000000FF // A high bit value will clear the
+ // corresponding bit in ADI
+ // register 8
+#define ADI_CLR811_S0_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADI_O_CLR1215 register.
+//
+//*****************************************************************************
+#define ADI_CLR1215_S3_M 0xFF000000 // A high bit value will clear the
+ // corresponding bit in ADI
+ // register 15
+#define ADI_CLR1215_S3_S 24
+#define ADI_CLR1215_S2_M 0x00FF0000 // A high bit value will clear the
+ // corresponding bit in ADI
+ // register 14
+#define ADI_CLR1215_S2_S 16
+#define ADI_CLR1215_S1_M 0x0000FF00 // A high bit value will clear the
+ // corresponding bit in ADI
+ // register 13
+#define ADI_CLR1215_S1_S 8
+#define ADI_CLR1215_S0_M 0x000000FF // A high bit value will clear the
+ // corresponding bit in ADI
+ // register 12
+#define ADI_CLR1215_S0_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADI_O_SLAVESTAT register.
+//
+//*****************************************************************************
+#define ADI_SLAVESTAT_DI_REQ 0x00000002 // Read current value of DI_REQ
+ // signal. Writing 0 to this bit
+ // forces a sync with slave,
+ // ensuring that req will be 0. It
+ // is recommended to write 0 to
+ // this register before power down
+ // of the master.
+#define ADI_SLAVESTAT_DI_REQ_M 0x00000002
+#define ADI_SLAVESTAT_DI_REQ_S 1
+#define ADI_SLAVESTAT_DI_ACK 0x00000001 // Read current value of DI_ACK
+ // signal
+#define ADI_SLAVESTAT_DI_ACK_M 0x00000001
+#define ADI_SLAVESTAT_DI_ACK_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADI_O_SLAVECONF register.
+//
+//*****************************************************************************
+#define ADI_SLAVECONF_CONFLOCK 0x00000080 // This register is no longer
+ // accessible when this bit is set.
+ // (unless sticky_bit_overwrite is
+ // asserted on top module)
+#define ADI_SLAVECONF_CONFLOCK_M \
+ 0x00000080
+#define ADI_SLAVECONF_CONFLOCK_S 7
+#define ADI_SLAVECONF_WAITFORACK \
+ 0x00000004 // A transaction on the ADI
+ // interface does not end until ack
+ // has been received from the slave
+ // when this bit is set.
+
+#define ADI_SLAVECONF_WAITFORACK_M \
+ 0x00000004
+#define ADI_SLAVECONF_WAITFORACK_S 2
+#define ADI_SLAVECONF_ADICLKSPEED_M \
+ 0x00000003 // Sets the period of an ADI
+ // transactions. All transactions
+ // takes an even number of clock
+ // cycles,- ADI clock rising edge
+ // occurs in the middle of the
+ // period. Data and ctrl to slave
+ // is set up in beginning of cycle,
+ // and data from slave is read in
+ // after the transaction 00: An ADI
+ // transaction takes 2 master clock
+ // cyclkes 01: An ADI transaction
+ // takes 4 master clock cycles 10:
+ // And ADI Transaction takes 8
+ // master clock cycles 11: An ADI
+ // transaction takes 16 master
+ // clock cycles
+
+#define ADI_SLAVECONF_ADICLKSPEED_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADI_O_MASK4B01 register.
+//
+//*****************************************************************************
+#define ADI_MASK4B01_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI
+ // register 1
+#define ADI_MASK4B01_M1H_S 28
+#define ADI_MASK4B01_D1H_M 0x0F000000 // Data for bits [7:4] in ADI
+ // register 1, - only bits selected
+ // by mask M1H will be affected by
+ // access
+#define ADI_MASK4B01_D1H_S 24
+#define ADI_MASK4B01_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI
+ // register 1
+#define ADI_MASK4B01_M1L_S 20
+#define ADI_MASK4B01_D1L_M 0x000F0000 // Data for bits [3:0] in ADI
+ // register 1, - only bits selected
+ // by mask M1L will be affected by
+ // access
+#define ADI_MASK4B01_D1L_S 16
+#define ADI_MASK4B01_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI
+ // register 0
+#define ADI_MASK4B01_M0H_S 12
+#define ADI_MASK4B01_D0H_M 0x00000F00 // Data for bits [7:4] in ADI
+ // register 0, - only bits selected
+ // by mask M0H will be affected by
+ // access
+#define ADI_MASK4B01_D0H_S 8
+#define ADI_MASK4B01_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI
+ // register 0
+#define ADI_MASK4B01_M0L_S 4
+#define ADI_MASK4B01_D0L_M 0x0000000F // Data for bits [3:0] in ADI
+ // register 0, - only bits selected
+ // by mask M0L will be affected by
+ // access
+#define ADI_MASK4B01_D0L_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADI_O_MASK4B23 register.
+//
+//*****************************************************************************
+#define ADI_MASK4B23_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI
+ // register 3
+#define ADI_MASK4B23_M1H_S 28
+#define ADI_MASK4B23_D1H_M 0x0F000000 // Data for bits [7:4] in ADI
+ // register 3, - only bits selected
+ // by mask M1H will be affected by
+ // access
+#define ADI_MASK4B23_D1H_S 24
+#define ADI_MASK4B23_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI
+ // register 3
+#define ADI_MASK4B23_M1L_S 20
+#define ADI_MASK4B23_D1L_M 0x000F0000 // Data for bits [3:0] in ADI
+ // register 3, - only bits selected
+ // by mask M1L will be affected by
+ // access
+#define ADI_MASK4B23_D1L_S 16
+#define ADI_MASK4B23_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI
+ // register 2
+#define ADI_MASK4B23_M0H_S 12
+#define ADI_MASK4B23_D0H_M 0x00000F00 // Data for bits [7:4] in ADI
+ // register 2, - only bits selected
+ // by mask M0H will be affected by
+ // access
+#define ADI_MASK4B23_D0H_S 8
+#define ADI_MASK4B23_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI
+ // register 2
+#define ADI_MASK4B23_M0L_S 4
+#define ADI_MASK4B23_D0L_M 0x0000000F // Data for bits [3:0] in ADI
+ // register 2, - only bits selected
+ // by mask M0L will be affected by
+ // access
+#define ADI_MASK4B23_D0L_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADI_O_MASK4B45 register.
+//
+//*****************************************************************************
+#define ADI_MASK4B45_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI
+ // register 5
+#define ADI_MASK4B45_M1H_S 28
+#define ADI_MASK4B45_D1H_M 0x0F000000 // Data for bits [7:4] in ADI
+ // register 5, - only bits selected
+ // by mask M1H will be affected by
+ // access
+#define ADI_MASK4B45_D1H_S 24
+#define ADI_MASK4B45_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI
+ // register 5
+#define ADI_MASK4B45_M1L_S 20
+#define ADI_MASK4B45_D1L_M 0x000F0000 // Data for bits [3:0] in ADI
+ // register 5, - only bits selected
+ // by mask M1L will be affected by
+ // access
+#define ADI_MASK4B45_D1L_S 16
+#define ADI_MASK4B45_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI
+ // register 4
+#define ADI_MASK4B45_M0H_S 12
+#define ADI_MASK4B45_D0H_M 0x00000F00 // Data for bits [7:4] in ADI
+ // register 4, - only bits selected
+ // by mask M0H will be affected by
+ // access
+#define ADI_MASK4B45_D0H_S 8
+#define ADI_MASK4B45_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI
+ // register 4
+#define ADI_MASK4B45_M0L_S 4
+#define ADI_MASK4B45_D0L_M 0x0000000F // Data for bits [3:0] in ADI
+ // register 4, - only bits selected
+ // by mask M0L will be affected by
+ // access
+#define ADI_MASK4B45_D0L_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADI_O_MASK4B67 register.
+//
+//*****************************************************************************
+#define ADI_MASK4B67_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI
+ // register 7
+#define ADI_MASK4B67_M1H_S 28
+#define ADI_MASK4B67_D1H_M 0x0F000000 // Data for bits [7:4] in ADI
+ // register 7, - only bits selected
+ // by mask M1H will be affected by
+ // access
+#define ADI_MASK4B67_D1H_S 24
+#define ADI_MASK4B67_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI
+ // register 7
+#define ADI_MASK4B67_M1L_S 20
+#define ADI_MASK4B67_D1L_M 0x000F0000 // Data for bits [3:0] in ADI
+ // register 7, - only bits selected
+ // by mask M1L will be affected by
+ // access
+#define ADI_MASK4B67_D1L_S 16
+#define ADI_MASK4B67_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI
+ // register 6
+#define ADI_MASK4B67_M0H_S 12
+#define ADI_MASK4B67_D0H_M 0x00000F00 // Data for bits [7:4] in ADI
+ // register 6, - only bits selected
+ // by mask M0H will be affected by
+ // access
+#define ADI_MASK4B67_D0H_S 8
+#define ADI_MASK4B67_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI
+ // register 6
+#define ADI_MASK4B67_M0L_S 4
+#define ADI_MASK4B67_D0L_M 0x0000000F // Data for bits [3:0] in ADI
+ // register 6, - only bits selected
+ // by mask M0L will be affected by
+ // access
+#define ADI_MASK4B67_D0L_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADI_O_MASK4B89 register.
+//
+//*****************************************************************************
+#define ADI_MASK4B89_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI
+ // register 9
+#define ADI_MASK4B89_M1H_S 28
+#define ADI_MASK4B89_D1H_M 0x0F000000 // Data for bits [7:4] in ADI
+ // register 9, - only bits selected
+ // by mask M1H will be affected by
+ // access
+#define ADI_MASK4B89_D1H_S 24
+#define ADI_MASK4B89_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI
+ // register 9
+#define ADI_MASK4B89_M1L_S 20
+#define ADI_MASK4B89_D1L_M 0x000F0000 // Data for bits [3:0] in ADI
+ // register 9, - only bits selected
+ // by mask M1L will be affected by
+ // access
+#define ADI_MASK4B89_D1L_S 16
+#define ADI_MASK4B89_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI
+ // register 8
+#define ADI_MASK4B89_M0H_S 12
+#define ADI_MASK4B89_D0H_M 0x00000F00 // Data for bits [7:4] in ADI
+ // register 8, - only bits selected
+ // by mask M0H will be affected by
+ // access
+#define ADI_MASK4B89_D0H_S 8
+#define ADI_MASK4B89_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI
+ // register 8
+#define ADI_MASK4B89_M0L_S 4
+#define ADI_MASK4B89_D0L_M 0x0000000F // Data for bits [3:0] in ADI
+ // register 8, - only bits selected
+ // by mask M0L will be affected by
+ // access
+#define ADI_MASK4B89_D0L_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADI_O_MASK4B1011 register.
+//
+//*****************************************************************************
+#define ADI_MASK4B1011_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI
+ // register 11
+#define ADI_MASK4B1011_M1H_S 28
+#define ADI_MASK4B1011_D1H_M 0x0F000000 // Data for bits [7:4] in ADI
+ // register 11, - only bits
+ // selected by mask M1H will be
+ // affected by access
+#define ADI_MASK4B1011_D1H_S 24
+#define ADI_MASK4B1011_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI
+ // register 11
+#define ADI_MASK4B1011_M1L_S 20
+#define ADI_MASK4B1011_D1L_M 0x000F0000 // Data for bits [3:0] in ADI
+ // register 11, - only bits
+ // selected by mask M1L will be
+ // affected by access
+#define ADI_MASK4B1011_D1L_S 16
+#define ADI_MASK4B1011_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI
+ // register 10
+#define ADI_MASK4B1011_M0H_S 12
+#define ADI_MASK4B1011_D0H_M 0x00000F00 // Data for bits [7:4] in ADI
+ // register 10, - only bits
+ // selected by mask M0H will be
+ // affected by access
+#define ADI_MASK4B1011_D0H_S 8
+#define ADI_MASK4B1011_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI
+ // register 10
+#define ADI_MASK4B1011_M0L_S 4
+#define ADI_MASK4B1011_D0L_M 0x0000000F // Data for bits [3:0] in ADI
+ // register 10, - only bits
+ // selected by mask M0L will be
+ // affected by access
+#define ADI_MASK4B1011_D0L_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADI_O_MASK4B1213 register.
+//
+//*****************************************************************************
+#define ADI_MASK4B1213_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI
+ // register 13
+#define ADI_MASK4B1213_M1H_S 28
+#define ADI_MASK4B1213_D1H_M 0x0F000000 // Data for bits [7:4] in ADI
+ // register 13, - only bits
+ // selected by mask M1H will be
+ // affected by access
+#define ADI_MASK4B1213_D1H_S 24
+#define ADI_MASK4B1213_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI
+ // register 13
+#define ADI_MASK4B1213_M1L_S 20
+#define ADI_MASK4B1213_D1L_M 0x000F0000 // Data for bits [3:0] in ADI
+ // register 13, - only bits
+ // selected by mask M1L will be
+ // affected by access
+#define ADI_MASK4B1213_D1L_S 16
+#define ADI_MASK4B1213_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI
+ // register 12
+#define ADI_MASK4B1213_M0H_S 12
+#define ADI_MASK4B1213_D0H_M 0x00000F00 // Data for bits [7:4] in ADI
+ // register 12, - only bits
+ // selected by mask M0H will be
+ // affected by access
+#define ADI_MASK4B1213_D0H_S 8
+#define ADI_MASK4B1213_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI
+ // register 12
+#define ADI_MASK4B1213_M0L_S 4
+#define ADI_MASK4B1213_D0L_M 0x0000000F // Data for bits [3:0] in ADI
+ // register 12, - only bits
+ // selected by mask M0L will be
+ // affected by access
+#define ADI_MASK4B1213_D0L_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADI_O_MASK4B1415 register.
+//
+//*****************************************************************************
+#define ADI_MASK4B1415_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI
+ // register 15
+#define ADI_MASK4B1415_M1H_S 28
+#define ADI_MASK4B1415_D1H_M 0x0F000000 // Data for bits [7:4] in ADI
+ // register 15, - only bits
+ // selected by mask M1H will be
+ // affected by access
+#define ADI_MASK4B1415_D1H_S 24
+#define ADI_MASK4B1415_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI
+ // register 15
+#define ADI_MASK4B1415_M1L_S 20
+#define ADI_MASK4B1415_D1L_M 0x000F0000 // Data for bits [3:0] in ADI
+ // register 15, - only bits
+ // selected by mask M1L will be
+ // affected by access
+#define ADI_MASK4B1415_D1L_S 16
+#define ADI_MASK4B1415_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI
+ // register 14
+#define ADI_MASK4B1415_M0H_S 12
+#define ADI_MASK4B1415_D0H_M 0x00000F00 // Data for bits [7:4] in ADI
+ // register 14, - only bits
+ // selected by mask M0H will be
+ // affected by access
+#define ADI_MASK4B1415_D0H_S 8
+#define ADI_MASK4B1415_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI
+ // register 14
+#define ADI_MASK4B1415_M0L_S 4
+#define ADI_MASK4B1415_D0L_M 0x0000000F // Data for bits [3:0] in ADI
+ // register 14, - only bits
+ // selected by mask M0L will be
+ // affected by access
+#define ADI_MASK4B1415_D0L_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADI_O_MASK8B01 register.
+//
+//*****************************************************************************
+#define ADI_MASK8B01_M1_M 0xFF000000 // Mask for ADI register 1
+#define ADI_MASK8B01_M1_S 24
+#define ADI_MASK8B01_D1_M 0x00FF0000 // Data for ADI register 1, - only
+ // bits selected by mask M1 will be
+ // affected by access
+#define ADI_MASK8B01_D1_S 16
+#define ADI_MASK8B01_M0_M 0x0000FF00 // Mask for ADI register 0
+#define ADI_MASK8B01_M0_S 8
+#define ADI_MASK8B01_D0_M 0x000000FF // Data for ADI register 0, - only
+ // bits selected by mask M0 will be
+ // affected by access
+#define ADI_MASK8B01_D0_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADI_O_MASK8B23 register.
+//
+//*****************************************************************************
+#define ADI_MASK8B23_M1_M 0xFF000000 // Mask for ADI register 3
+#define ADI_MASK8B23_M1_S 24
+#define ADI_MASK8B23_D1_M 0x00FF0000 // Data for ADI register 3, - only
+ // bits selected by mask M1 will be
+ // affected by access
+#define ADI_MASK8B23_D1_S 16
+#define ADI_MASK8B23_M0_M 0x0000FF00 // Mask for ADI register 2
+#define ADI_MASK8B23_M0_S 8
+#define ADI_MASK8B23_D0_M 0x000000FF // Data for ADI register 2, - only
+ // bits selected by mask M0 will be
+ // affected by access
+#define ADI_MASK8B23_D0_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADI_O_MASK8B45 register.
+//
+//*****************************************************************************
+#define ADI_MASK8B45_M1_M 0xFF000000 // Mask for ADI register 5
+#define ADI_MASK8B45_M1_S 24
+#define ADI_MASK8B45_D1_M 0x00FF0000 // Data for ADI register 5, - only
+ // bits selected by mask M1 will be
+ // affected by access
+#define ADI_MASK8B45_D1_S 16
+#define ADI_MASK8B45_M0_M 0x0000FF00 // Mask for ADI register 4
+#define ADI_MASK8B45_M0_S 8
+#define ADI_MASK8B45_D0_M 0x000000FF // Data for ADI register 4, - only
+ // bits selected by mask M0 will be
+ // affected by access
+#define ADI_MASK8B45_D0_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADI_O_MASK8B67 register.
+//
+//*****************************************************************************
+#define ADI_MASK8B67_M1_M 0xFF000000 // Mask for ADI register 7
+#define ADI_MASK8B67_M1_S 24
+#define ADI_MASK8B67_D1_M 0x00FF0000 // Data for ADI register 7, - only
+ // bits selected by mask M1 will be
+ // affected by access
+#define ADI_MASK8B67_D1_S 16
+#define ADI_MASK8B67_M0_M 0x0000FF00 // Mask for ADI register 6
+#define ADI_MASK8B67_M0_S 8
+#define ADI_MASK8B67_D0_M 0x000000FF // Data for ADI register 6, - only
+ // bits selected by mask M0 will be
+ // affected by access
+#define ADI_MASK8B67_D0_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADI_O_MASK8B89 register.
+//
+//*****************************************************************************
+#define ADI_MASK8B89_M1_M 0xFF000000 // Mask for ADI register 9
+#define ADI_MASK8B89_M1_S 24
+#define ADI_MASK8B89_D1_M 0x00FF0000 // Data for ADI register 9, - only
+ // bits selected by mask M1 will be
+ // affected by access
+#define ADI_MASK8B89_D1_S 16
+#define ADI_MASK8B89_M0_M 0x0000FF00 // Mask for ADI register 8
+#define ADI_MASK8B89_M0_S 8
+#define ADI_MASK8B89_D0_M 0x000000FF // Data for ADI register 8, - only
+ // bits selected by mask M0 will be
+ // affected by access
+#define ADI_MASK8B89_D0_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADI_O_MASK8B1011 register.
+//
+//*****************************************************************************
+#define ADI_MASK8B1011_M1_M 0xFF000000 // Mask for ADI register 11
+#define ADI_MASK8B1011_M1_S 24
+#define ADI_MASK8B1011_D1_M 0x00FF0000 // Data for ADI register 11, -
+ // only bits selected by mask M1
+ // will be affected by access
+#define ADI_MASK8B1011_D1_S 16
+#define ADI_MASK8B1011_M0_M 0x0000FF00 // Mask for ADI register 10
+#define ADI_MASK8B1011_M0_S 8
+#define ADI_MASK8B1011_D0_M 0x000000FF // Data for ADI register 10, -
+ // only bits selected by mask M0
+ // will be affected by access
+#define ADI_MASK8B1011_D0_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADI_O_MASK8B1213 register.
+//
+//*****************************************************************************
+#define ADI_MASK8B1213_M1_M 0xFF000000 // Mask for ADI register 13
+#define ADI_MASK8B1213_M1_S 24
+#define ADI_MASK8B1213_D1_M 0x00FF0000 // Data for ADI register 13, -
+ // only bits selected by mask M1
+ // will be affected by access
+#define ADI_MASK8B1213_D1_S 16
+#define ADI_MASK8B1213_M0_M 0x0000FF00 // Mask for ADI register 12
+#define ADI_MASK8B1213_M0_S 8
+#define ADI_MASK8B1213_D0_M 0x000000FF // Data for ADI register 12, -
+ // only bits selected by mask M0
+ // will be affected by access
+#define ADI_MASK8B1213_D0_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADI_O_MASK8B1415 register.
+//
+//*****************************************************************************
+#define ADI_MASK8B1415_M1_M 0xFF000000 // Mask for ADI register 15
+#define ADI_MASK8B1415_M1_S 24
+#define ADI_MASK8B1415_D1_M 0x00FF0000 // Data for ADI register 15, -
+ // only bits selected by mask M1
+ // will be affected by access
+#define ADI_MASK8B1415_D1_S 16
+#define ADI_MASK8B1415_M0_M 0x0000FF00 // Mask for ADI register 14
+#define ADI_MASK8B1415_M0_S 8
+#define ADI_MASK8B1415_D0_M 0x000000FF // Data for ADI register 14, -
+ // only bits selected by mask M0
+ // will be affected by access
+#define ADI_MASK8B1415_D0_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADI_O_MASK16B01 register.
+//
+//*****************************************************************************
+#define ADI_MASK16B01_M_M 0xFFFF0000 // Mask for ADI register 0 and 1
+#define ADI_MASK16B01_M_S 16
+#define ADI_MASK16B01_D_M 0x0000FFFF // Data for ADI register at
+ // offsets 0 and 1, - only bits
+ // selected by mask M will be
+ // affected by access
+#define ADI_MASK16B01_D_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADI_O_MASK16B23 register.
+//
+//*****************************************************************************
+#define ADI_MASK16B23_M_M 0xFFFF0000 // Mask for ADI register 2 and 3
+#define ADI_MASK16B23_M_S 16
+#define ADI_MASK16B23_D_M 0x0000FFFF // Data for ADI register at
+ // offsets 2 and 3, - only bits
+ // selected by mask M will be
+ // affected by access
+#define ADI_MASK16B23_D_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADI_O_MASK16B45 register.
+//
+//*****************************************************************************
+#define ADI_MASK16B45_M_M 0xFFFF0000 // Mask for ADI register 4 and 5
+#define ADI_MASK16B45_M_S 16
+#define ADI_MASK16B45_D_M 0x0000FFFF // Data for ADI register at
+ // offsets 4 and 5, - only bits
+ // selected by mask M will be
+ // affected by access
+#define ADI_MASK16B45_D_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADI_O_MASK16B67 register.
+//
+//*****************************************************************************
+#define ADI_MASK16B67_M_M 0xFFFF0000 // Mask for ADI register 6 and 7
+#define ADI_MASK16B67_M_S 16
+#define ADI_MASK16B67_D_M 0x0000FFFF // Data for ADI register at
+ // offsets 6 and 7, - only bits
+ // selected by mask M will be
+ // affected by access
+#define ADI_MASK16B67_D_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADI_O_MASK16B89 register.
+//
+//*****************************************************************************
+#define ADI_MASK16B89_M_M 0xFFFF0000 // Mask for ADI register 8 and 9
+#define ADI_MASK16B89_M_S 16
+#define ADI_MASK16B89_D_M 0x0000FFFF // Data for ADI register at
+ // offsets 8 and 9, - only bits
+ // selected by mask M will be
+ // affected by access
+#define ADI_MASK16B89_D_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADI_O_MASK16B1011 register.
+//
+//*****************************************************************************
+#define ADI_MASK16B1011_M_M 0xFFFF0000 // Mask for ADI register 10 and 11
+#define ADI_MASK16B1011_M_S 16
+#define ADI_MASK16B1011_D_M 0x0000FFFF // Data for ADI register at
+ // offsets 10 and 11, - only bits
+ // selected by mask M will be
+ // affected by access
+#define ADI_MASK16B1011_D_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADI_O_MASK16B1213 register.
+//
+//*****************************************************************************
+#define ADI_MASK16B1213_M_M 0xFFFF0000 // Mask for ADI register 12 and 13
+#define ADI_MASK16B1213_M_S 16
+#define ADI_MASK16B1213_D_M 0x0000FFFF // Data for ADI register at
+ // offsets 12 and 13, - only bits
+ // selected by mask M will be
+ // affected by access
+#define ADI_MASK16B1213_D_S 0
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADI_O_MASK16B1415 register.
+//
+//*****************************************************************************
+#define ADI_MASK16B1415_M_M 0xFFFF0000 // Mask for ADI register 14 and 15
+#define ADI_MASK16B1415_M_S 16
+#define ADI_MASK16B1415_D_M 0x0000FFFF // Data for ADI register at
+ // offsets 14 and 15, - only bits
+ // selected by mask M will be
+ // affected by access
+#define ADI_MASK16B1415_D_S 0
+
+#endif // __HW_ADI_H__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_2_refsys.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_2_refsys.h
new file mode 100644
index 0000000..68d37bd
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_2_refsys.h
@@ -0,0 +1,362 @@
+/******************************************************************************
+* Filename: hw_adi_2_refsys_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_ADI_2_REFSYS_H__
+#define __HW_ADI_2_REFSYS_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// ADI_2_REFSYS component
+//
+//*****************************************************************************
+// Internal
+#define ADI_2_REFSYS_O_REFSYSCTL0 0x00000000
+
+// Internal
+#define ADI_2_REFSYS_O_SOCLDOCTL0 0x00000002
+
+// Internal
+#define ADI_2_REFSYS_O_SOCLDOCTL1 0x00000003
+
+// Internal
+#define ADI_2_REFSYS_O_SOCLDOCTL2 0x00000004
+
+// Internal
+#define ADI_2_REFSYS_O_SOCLDOCTL3 0x00000005
+
+// Internal
+#define ADI_2_REFSYS_O_SOCLDOCTL4 0x00000006
+
+// Internal
+#define ADI_2_REFSYS_O_SOCLDOCTL5 0x00000007
+
+// Internal
+#define ADI_2_REFSYS_O_HPOSCCTL0 0x0000000A
+
+// Internal
+#define ADI_2_REFSYS_O_HPOSCCTL1 0x0000000B
+
+// Internal
+#define ADI_2_REFSYS_O_HPOSCCTL2 0x0000000C
+
+//*****************************************************************************
+//
+// Register: ADI_2_REFSYS_O_REFSYSCTL0
+//
+//*****************************************************************************
+// Field: [4:0] TRIM_IREF
+//
+// Internal. Only to be used through TI provided API.
+#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_W 5
+#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_M 0x0000001F
+#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_S 0
+
+//*****************************************************************************
+//
+// Register: ADI_2_REFSYS_O_SOCLDOCTL0
+//
+//*****************************************************************************
+// Field: [7:4] VTRIM_UDIG
+//
+// Internal. Only to be used through TI provided API.
+#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_W 4
+#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_M 0x000000F0
+#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_S 4
+
+// Field: [3:0] VTRIM_BOD
+//
+// Internal. Only to be used through TI provided API.
+#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_W 4
+#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_M 0x0000000F
+#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_S 0
+
+//*****************************************************************************
+//
+// Register: ADI_2_REFSYS_O_SOCLDOCTL1
+//
+//*****************************************************************************
+// Field: [7:4] VTRIM_COARSE
+//
+// Internal. Only to be used through TI provided API.
+#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_W 4
+#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_M 0x000000F0
+#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_S 4
+
+// Field: [3:0] VTRIM_DIG
+//
+// Internal. Only to be used through TI provided API.
+#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_W 4
+#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_M 0x0000000F
+#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_S 0
+
+//*****************************************************************************
+//
+// Register: ADI_2_REFSYS_O_SOCLDOCTL2
+//
+//*****************************************************************************
+// Field: [2:0] VTRIM_DELTA
+//
+// Internal. Only to be used through TI provided API.
+#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_W 3
+#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_M 0x00000007
+#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_S 0
+
+//*****************************************************************************
+//
+// Register: ADI_2_REFSYS_O_SOCLDOCTL3
+//
+//*****************************************************************************
+// Field: [7:6] ITRIM_DIGLDO_LOAD
+//
+// Internal. Only to be used through TI provided API.
+#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_W 2
+#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_M 0x000000C0
+#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_S 6
+
+// Field: [5:3] ITRIM_DIGLDO
+//
+// Internal. Only to be used through TI provided API.
+// ENUMs:
+// BIAS_120P Internal. Only to be used through TI provided API.
+// BIAS_100P Internal. Only to be used through TI provided API.
+// BIAS_80P Internal. Only to be used through TI provided API.
+// BIAS_60P Internal. Only to be used through TI provided API.
+#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_W 3
+#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_M 0x00000038
+#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_S 3
+#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_120P 0x00000038
+#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_100P 0x00000028
+#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_80P 0x00000018
+#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_60P 0x00000000
+
+// Field: [2:0] ITRIM_UDIGLDO
+//
+// Internal. Only to be used through TI provided API.
+#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_W 3
+#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_M 0x00000007
+#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_S 0
+
+//*****************************************************************************
+//
+// Register: ADI_2_REFSYS_O_SOCLDOCTL4
+//
+//*****************************************************************************
+// Field: [6:5] UDIG_ITEST_EN
+//
+// Internal. Only to be used through TI provided API.
+#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_W 2
+#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_M 0x00000060
+#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_S 5
+
+// Field: [4:2] DIG_ITEST_EN
+//
+// Internal. Only to be used through TI provided API.
+#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_W 3
+#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_M 0x0000001C
+#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_S 2
+
+// Field: [1] BIAS_DIS
+//
+// Internal. Only to be used through TI provided API.
+#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS 0x00000002
+#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS_M 0x00000002
+#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS_S 1
+
+// Field: [0] UDIG_LDO_EN
+//
+// Internal. Only to be used through TI provided API.
+// ENUMs:
+// EN Internal. Only to be used through TI provided API.
+// DIS Internal. Only to be used through TI provided API.
+#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN 0x00000001
+#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_M 0x00000001
+#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_S 0
+#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_EN 0x00000001
+#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_DIS 0x00000000
+
+//*****************************************************************************
+//
+// Register: ADI_2_REFSYS_O_SOCLDOCTL5
+//
+//*****************************************************************************
+// Field: [3] IMON_ITEST_EN
+//
+// Internal. Only to be used through TI provided API.
+#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN 0x00000008
+#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN_M 0x00000008
+#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN_S 3
+
+// Field: [2:0] TESTSEL
+//
+// Internal. Only to be used through TI provided API.
+// ENUMs:
+// VDD_AON Internal. Only to be used through TI provided API.
+// VREF_AMP Internal. Only to be used through TI provided API.
+// ITEST Internal. Only to be used through TI provided API.
+// NC Internal. Only to be used through TI provided API.
+#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_W 3
+#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_M 0x00000007
+#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_S 0
+#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_VDD_AON 0x00000004
+#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_VREF_AMP 0x00000002
+#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_ITEST 0x00000001
+#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_NC 0x00000000
+
+//*****************************************************************************
+//
+// Register: ADI_2_REFSYS_O_HPOSCCTL0
+//
+//*****************************************************************************
+// Field: [7] FILTER_EN
+//
+// Internal. Only to be used through TI provided API.
+#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN 0x00000080
+#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_M 0x00000080
+#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_S 7
+
+// Field: [6:5] BIAS_RECHARGE_DLY
+//
+// Internal. Only to be used through TI provided API.
+// ENUMs:
+// MIN_DLY_X8 Internal. Only to be used through TI provided API.
+// MIN_DLY_X4 Internal. Only to be used through TI provided API.
+// MIN_DLY_X2 Internal. Only to be used through TI provided API.
+// MIN_DLY_X1 Internal. Only to be used through TI provided API.
+#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_W 2
+#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_M 0x00000060
+#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_S 5
+#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X8 0x00000060
+#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X4 0x00000040
+#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X2 0x00000020
+#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X1 0x00000000
+
+// Field: [4:3] TUNE_CAP
+//
+// Internal. Only to be used through TI provided API.
+// ENUMs:
+// SHIFT_M108 Internal. Only to be used through TI provided API.
+// SHIFT_M70 Internal. Only to be used through TI provided API.
+// SHIFT_M35 Internal. Only to be used through TI provided API.
+// SHIFT_0 Internal. Only to be used through TI provided API.
+#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_W 2
+#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_M 0x00000018
+#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_S 3
+#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M108 0x00000018
+#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M70 0x00000010
+#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M35 0x00000008
+#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_0 0x00000000
+
+// Field: [2:1] SERIES_CAP
+//
+// Internal. Only to be used through TI provided API.
+#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_W 2
+#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_M 0x00000006
+#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_S 1
+
+// Field: [0] DIV3_BYPASS
+//
+// Internal. Only to be used through TI provided API.
+// ENUMs:
+// HPOSC_2520MHZ Internal. Only to be used through TI provided API.
+// HPOSC_840MHZ Internal. Only to be used through TI provided API.
+#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS 0x00000001
+#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_M 0x00000001
+#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_S 0
+#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_HPOSC_2520MHZ 0x00000001
+#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_HPOSC_840MHZ 0x00000000
+
+//*****************************************************************************
+//
+// Register: ADI_2_REFSYS_O_HPOSCCTL1
+//
+//*****************************************************************************
+// Field: [5] BIAS_DIS
+//
+// Internal. Only to be used through TI provided API.
+#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS 0x00000020
+#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS_M 0x00000020
+#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS_S 5
+
+// Field: [4] PWRDET_EN
+//
+// Internal. Only to be used through TI provided API.
+#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN 0x00000010
+#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN_M 0x00000010
+#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN_S 4
+
+// Field: [3:0] BIAS_RES_SET
+//
+// Internal. Only to be used through TI provided API.
+#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_W 4
+#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_M 0x0000000F
+#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_S 0
+
+//*****************************************************************************
+//
+// Register: ADI_2_REFSYS_O_HPOSCCTL2
+//
+//*****************************************************************************
+// Field: [7] BIAS_HOLD_MODE_EN
+//
+// Internal. Only to be used through TI provided API.
+#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN 0x00000080
+#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_M 0x00000080
+#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_S 7
+
+// Field: [6] TESTMUX_EN
+//
+// Internal. Only to be used through TI provided API.
+#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN 0x00000040
+#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN_M 0x00000040
+#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN_S 6
+
+// Field: [5:4] ATEST_SEL
+//
+// Internal. Only to be used through TI provided API.
+#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_W 2
+#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_M 0x00000030
+#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_S 4
+
+// Field: [3:0] CURRMIRR_RATIO
+//
+// Internal. Only to be used through TI provided API.
+#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_W 4
+#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_M 0x0000000F
+#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_S 0
+
+
+#endif // __ADI_2_REFSYS__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_3_refsys.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_3_refsys.h
new file mode 100644
index 0000000..2315d8d
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_3_refsys.h
@@ -0,0 +1,685 @@
+/******************************************************************************
+* Filename: hw_adi_3_refsys_h
+* Revised: 2018-09-27 10:33:21 +0200 (Thu, 27 Sep 2018)
+* Revision: 52772
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_ADI_3_REFSYS_H__
+#define __HW_ADI_3_REFSYS_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// ADI_3_REFSYS component
+//
+//*****************************************************************************
+// Internal
+#define ADI_3_REFSYS_O_ATESTCTL1 0x00000001
+
+// Internal
+#define ADI_3_REFSYS_O_REFSYSCTL0 0x00000002
+
+// Internal
+#define ADI_3_REFSYS_O_REFSYSCTL1 0x00000003
+
+// Internal
+#define ADI_3_REFSYS_O_REFSYSCTL2 0x00000004
+
+// Internal
+#define ADI_3_REFSYS_O_REFSYSCTL3 0x00000005
+
+// DCDC Control 0
+#define ADI_3_REFSYS_O_DCDCCTL0 0x00000006
+
+// DCDC Control 1
+#define ADI_3_REFSYS_O_DCDCCTL1 0x00000007
+
+// DCDC Control 2
+#define ADI_3_REFSYS_O_DCDCCTL2 0x00000008
+
+// Internal
+#define ADI_3_REFSYS_O_DCDCCTL3 0x00000009
+
+// Internal
+#define ADI_3_REFSYS_O_DCDCCTL4 0x0000000A
+
+// Internal
+#define ADI_3_REFSYS_O_DCDCCTL5 0x0000000B
+
+// RECHARGE_CONTROL_1
+#define ADI_3_REFSYS_O_AUX_DEBUG 0x0000000C
+
+// Recharge Comparator Control Byte 0
+#define ADI_3_REFSYS_O_CTL_RECHARGE_CMP0 0x0000000D
+
+// Recharge Comparator Control Byte 1
+#define ADI_3_REFSYS_O_CTL_RECHARGE_CMP1 0x0000000E
+
+//*****************************************************************************
+//
+// Register: ADI_3_REFSYS_O_ATESTCTL1
+//
+//*****************************************************************************
+// Field: [4:3] ATEST0_CTL
+//
+// Internal. Only to be used through TI provided API.
+// ENUMs:
+// ICELL_A0 Internal. Only to be used through TI provided API.
+// IREF_A0 Internal. Only to be used through TI provided API.
+// NC Internal. Only to be used through TI provided API.
+#define ADI_3_REFSYS_ATESTCTL1_ATEST0_CTL_W 2
+#define ADI_3_REFSYS_ATESTCTL1_ATEST0_CTL_M 0x00000018
+#define ADI_3_REFSYS_ATESTCTL1_ATEST0_CTL_S 3
+#define ADI_3_REFSYS_ATESTCTL1_ATEST0_CTL_ICELL_A0 0x00000010
+#define ADI_3_REFSYS_ATESTCTL1_ATEST0_CTL_IREF_A0 0x00000008
+#define ADI_3_REFSYS_ATESTCTL1_ATEST0_CTL_NC 0x00000000
+
+// Field: [2:0] ATEST1_CTL
+//
+// Internal. Only to be used through TI provided API.
+// ENUMs:
+// VREFM_A1 Internal. Only to be used through TI provided API.
+// VPP_DIV5_A1 Internal. Only to be used through TI provided API.
+// VREAD_DIV2_A1 Internal. Only to be used through TI provided API.
+// NC Internal. Only to be used through TI provided API.
+#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_W 3
+#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_M 0x00000007
+#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_S 0
+#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_VREFM_A1 0x00000004
+#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_VPP_DIV5_A1 0x00000002
+#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_VREAD_DIV2_A1 0x00000001
+#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_NC 0x00000000
+
+//*****************************************************************************
+//
+// Register: ADI_3_REFSYS_O_REFSYSCTL0
+//
+//*****************************************************************************
+// Field: [7:0] TESTCTL
+//
+// Internal. Only to be used through TI provided API.
+// ENUMs:
+// BMCOMPOUT Internal. Only to be used through TI provided API.
+// VTEMP Internal. Only to be used through TI provided API.
+// VREF0P8V Internal. Only to be used through TI provided API.
+// VBGUNBUFF Internal. Only to be used through TI provided API.
+// VBG Internal. Only to be used through TI provided API.
+// IREF4U Internal. Only to be used through TI provided API.
+// IVREF4U Internal. Only to be used through TI provided API.
+// IPTAT2U Internal. Only to be used through TI provided API.
+// NC Internal. Only to be used through TI provided API.
+#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_W 8
+#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_M 0x000000FF
+#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_S 0
+#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_BMCOMPOUT 0x00000080
+#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VTEMP 0x00000040
+#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VREF0P8V 0x00000020
+#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VBGUNBUFF 0x00000010
+#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VBG 0x00000008
+#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IREF4U 0x00000004
+#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IVREF4U 0x00000002
+#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IPTAT2U 0x00000001
+#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_NC 0x00000000
+
+//*****************************************************************************
+//
+// Register: ADI_3_REFSYS_O_REFSYSCTL1
+//
+//*****************************************************************************
+// Field: [7:3] TRIM_VDDS_BOD
+//
+// Internal. Only to be used through TI provided API.
+// ENUMs:
+// POS_27 Internal. Only to be used through TI provided API.
+// POS_26 Internal. Only to be used through TI provided API.
+// POS_25 Internal. Only to be used through TI provided API.
+// POS_24 Internal. Only to be used through TI provided API.
+// POS_31 Internal. Only to be used through TI provided API.
+// POS_30 Internal. Only to be used through TI provided API.
+// POS_29 Internal. Only to be used through TI provided API.
+// POS_28 Internal. Only to be used through TI provided API.
+// POS_19 Internal. Only to be used through TI provided API.
+// POS_18 Internal. Only to be used through TI provided API.
+// POS_17 Internal. Only to be used through TI provided API.
+// POS_16 Internal. Only to be used through TI provided API.
+// POS_23 Internal. Only to be used through TI provided API.
+// POS_22 Internal. Only to be used through TI provided API.
+// POS_21 Internal. Only to be used through TI provided API.
+// POS_20 Internal. Only to be used through TI provided API.
+// POS_11 Internal. Only to be used through TI provided API.
+// POS_10 Internal. Only to be used through TI provided API.
+// POS_9 Internal. Only to be used through TI provided API.
+// POS_8 Internal. Only to be used through TI provided API.
+// POS_15 Internal. Only to be used through TI provided API.
+// POS_14 Internal. Only to be used through TI provided API.
+// POS_13 Internal. Only to be used through TI provided API.
+// POS_12 Internal. Only to be used through TI provided API.
+// POS_3 Internal. Only to be used through TI provided API.
+// POS_2 Internal. Only to be used through TI provided API.
+// POS_1 Internal. Only to be used through TI provided API.
+// POS_0 Internal. Only to be used through TI provided API.
+// POS_7 Internal. Only to be used through TI provided API.
+// POS_6 Internal. Only to be used through TI provided API.
+// POS_5 Internal. Only to be used through TI provided API.
+// POS_4 Internal. Only to be used through TI provided API.
+#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_W 5
+#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_M 0x000000F8
+#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_S 3
+#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_27 0x000000F8
+#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_26 0x000000F0
+#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_25 0x000000E8
+#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_24 0x000000E0
+#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_31 0x000000D8
+#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_30 0x000000D0
+#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_29 0x000000C8
+#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_28 0x000000C0
+#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_19 0x000000B8
+#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_18 0x000000B0
+#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_17 0x000000A8
+#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_16 0x000000A0
+#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_23 0x00000098
+#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_22 0x00000090
+#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_21 0x00000088
+#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_20 0x00000080
+#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_11 0x00000078
+#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_10 0x00000070
+#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_9 0x00000068
+#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_8 0x00000060
+#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_15 0x00000058
+#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_14 0x00000050
+#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_13 0x00000048
+#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_12 0x00000040
+#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_3 0x00000038
+#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_2 0x00000030
+#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_1 0x00000028
+#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_0 0x00000020
+#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_7 0x00000018
+#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_6 0x00000010
+#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_5 0x00000008
+#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_4 0x00000000
+
+// Field: [2] BATMON_COMP_TEST_EN
+//
+// Internal. Only to be used through TI provided API.
+// ENUMs:
+// EN Internal. Only to be used through TI provided API.
+// DIS Internal. Only to be used through TI provided API.
+#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN 0x00000004
+#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_M 0x00000004
+#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_S 2
+#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_EN 0x00000004
+#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_DIS 0x00000000
+
+// Field: [1:0] TESTCTL
+//
+// Internal. Only to be used through TI provided API.
+// ENUMs:
+// IPTAT1U Internal. Only to be used through TI provided API.
+// BMCOMPIN Internal. Only to be used through TI provided API.
+// NC Internal. Only to be used through TI provided API.
+#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_W 2
+#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_M 0x00000003
+#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_S 0
+#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_IPTAT1U 0x00000002
+#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_BMCOMPIN 0x00000001
+#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_NC 0x00000000
+
+//*****************************************************************************
+//
+// Register: ADI_3_REFSYS_O_REFSYSCTL2
+//
+//*****************************************************************************
+// Field: [7:4] TRIM_VREF
+//
+// Internal. Only to be used through TI provided API.
+#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_W 4
+#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_M 0x000000F0
+#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_S 4
+
+// Field: [3] BOD_EXTERNAL_REG_MODE
+//
+// Internal. Only to be used through TI provided API.
+#define ADI_3_REFSYS_REFSYSCTL2_BOD_EXTERNAL_REG_MODE 0x00000008
+#define ADI_3_REFSYS_REFSYSCTL2_BOD_EXTERNAL_REG_MODE_M 0x00000008
+#define ADI_3_REFSYS_REFSYSCTL2_BOD_EXTERNAL_REG_MODE_S 3
+
+// Field: [1:0] TRIM_TSENSE
+//
+// Internal. Only to be used through TI provided API.
+#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_W 2
+#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_M 0x00000003
+#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_S 0
+
+//*****************************************************************************
+//
+// Register: ADI_3_REFSYS_O_REFSYSCTL3
+//
+//*****************************************************************************
+// Field: [7] BOD_BG_TRIM_EN
+//
+// Internal. Only to be used through TI provided API.
+#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN 0x00000080
+#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN_M 0x00000080
+#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN_S 7
+
+// Field: [6] VTEMP_EN
+//
+// Internal. Only to be used through TI provided API.
+// ENUMs:
+// EN Internal. Only to be used through TI provided API.
+// DIS Internal. Only to be used through TI provided API.
+#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN 0x00000040
+#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_M 0x00000040
+#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_S 6
+#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_EN 0x00000040
+#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_DIS 0x00000000
+
+// Field: [5:0] TRIM_VBG
+//
+// Internal. Only to be used through TI provided API.
+#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_W 6
+#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_M 0x0000003F
+#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_S 0
+
+//*****************************************************************************
+//
+// Register: ADI_3_REFSYS_O_DCDCCTL0
+//
+//*****************************************************************************
+// Field: [7:5] GLDO_ISRC
+//
+// Set charge and re-charge current level.
+// 2's complement encoding.
+//
+// 0x0: Default 11mA.
+// 0x3: Max 15mA.
+// 0x4: Max 5mA
+#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_W 3
+#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_M 0x000000E0
+#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_S 5
+
+// Field: [4:0] VDDR_TRIM
+//
+// Set the VDDR voltage.
+// Proprietary encoding.
+//
+// Increase voltage to max: 0x00, 0x01, 0x02 ... 0x15.
+// Decrease voltage to min: 0x00, 0x1F, 0x1E, 0x1D ... 0x16.
+// Step size = 16mV
+//
+// 0x00: Default, about 1.63V.
+// 0x05: Typical voltage after trim voltage 1.71V.
+// 0x15: Max voltage 1.96V.
+// 0x16: Min voltage 1.47V.
+#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_W 5
+#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M 0x0000001F
+#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S 0
+
+//*****************************************************************************
+//
+// Register: ADI_3_REFSYS_O_DCDCCTL1
+//
+//*****************************************************************************
+// Field: [7:6] IPTAT_TRIM
+//
+// Trim GLDO bias current.
+// Proprietary encoding.
+//
+// 0x0: Default
+// 0x1: Increase GLDO bias by 1.3x.
+// 0x2: Increase GLDO bias by 1.6x.
+// 0x3: Decrease GLDO bias by 0.7x.
+#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_W 2
+#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_M 0x000000C0
+#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_S 6
+
+// Field: [5] VDDR_OK_HYST
+//
+// Increase the hysteresis for when VDDR is considered ok.
+//
+// 0: Hysteresis = 60mV
+// 1: Hysteresis = 70mV
+#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST 0x00000020
+#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST_M 0x00000020
+#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST_S 5
+
+// Field: [4:0] VDDR_TRIM_SLEEP
+//
+// Set the min VDDR voltage threshold during sleep mode.
+// Proprietary encoding.
+//
+// Increase voltage to max: 0x00, 0x01, 0x02 ... 0x15.
+// Decrease voltage to min: 0x00, 0x1F, 0x1E, 0x1D ... 0x16.
+// Step size = 16mV
+//
+// 0x00: Default, about 1.63V.
+// 0x19: Typical voltage after trim voltage 1.52V.
+// 0x15: Max voltage 1.96V.
+// 0x16: Min voltage 1.47V.
+#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_W 5
+#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_M 0x0000001F
+#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_S 0
+
+//*****************************************************************************
+//
+// Register: ADI_3_REFSYS_O_DCDCCTL2
+//
+//*****************************************************************************
+// Field: [6] TURNON_EA_SW
+//
+// Turn on erroramp switch
+//
+// 0: Erroramp Off (Default)
+// 1: Erroramp On. Turns on GLDO error amp switch.
+#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW 0x00000040
+#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW_M 0x00000040
+#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW_S 6
+
+// Field: [5] TEST_VDDR
+//
+// Connect VDDR to ATEST bus
+//
+// 0: Not connected.
+// 1: Connected
+//
+// Set TESTSEL = 0x0 first before setting this bit.
+#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR 0x00000020
+#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR_M 0x00000020
+#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR_S 5
+
+// Field: [4] BIAS_DIS
+//
+// Disable dummy bias current.
+//
+// 0: Dummy bias current on (Default)
+// 1: Dummy bias current off
+#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS 0x00000010
+#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS_M 0x00000010
+#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS_S 4
+
+// Field: [3:0] TESTSEL
+//
+// Select signal for test bus, one hot.
+// ENUMs:
+// VDDROK VDDR_OK connected to test bus.
+// IB1U 1uA bias current connected to test bus.
+// PASSGATE Pass transistor gate voltage connected to test
+// bus.
+// ERRAMP_OUT Error amp output voltage connected to test bus.
+// NC No signal connected to test bus.
+#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_W 4
+#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_M 0x0000000F
+#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_S 0
+#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_VDDROK 0x00000008
+#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_IB1U 0x00000004
+#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_PASSGATE 0x00000002
+#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_ERRAMP_OUT 0x00000001
+#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_NC 0x00000000
+
+//*****************************************************************************
+//
+// Register: ADI_3_REFSYS_O_DCDCCTL3
+//
+//*****************************************************************************
+// Field: [1:0] VDDR_BOOST_COMP
+//
+// Internal. Only to be used through TI provided API.
+// ENUMs:
+// BOOST_P1 Internal. Only to be used through TI provided API.
+// BOOST Internal. Only to be used through TI provided API.
+// BOOST_N1 Internal. Only to be used through TI provided API.
+// DEFAULT Internal. Only to be used through TI provided API.
+#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_W 2
+#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_M 0x00000003
+#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_S 0
+#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_BOOST_P1 0x00000003
+#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_BOOST 0x00000002
+#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_BOOST_N1 0x00000001
+#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_DEFAULT 0x00000000
+
+//*****************************************************************************
+//
+// Register: ADI_3_REFSYS_O_DCDCCTL4
+//
+//*****************************************************************************
+// Field: [7:6] DEADTIME_TRIM
+//
+// Internal. Only to be used through TI provided API.
+#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_W 2
+#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_M 0x000000C0
+#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_S 6
+
+// Field: [5:3] LOW_EN_SEL
+//
+// Internal. Only to be used through TI provided API.
+#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_W 3
+#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_M 0x00000038
+#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_S 3
+
+// Field: [2:0] HIGH_EN_SEL
+//
+// Internal. Only to be used through TI provided API.
+#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_W 3
+#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_M 0x00000007
+#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_S 0
+
+//*****************************************************************************
+//
+// Register: ADI_3_REFSYS_O_DCDCCTL5
+//
+//*****************************************************************************
+// Field: [5] TESTN
+//
+// Internal. Only to be used through TI provided API.
+#define ADI_3_REFSYS_DCDCCTL5_TESTN 0x00000020
+#define ADI_3_REFSYS_DCDCCTL5_TESTN_M 0x00000020
+#define ADI_3_REFSYS_DCDCCTL5_TESTN_S 5
+
+// Field: [4] TESTP
+//
+// Internal. Only to be used through TI provided API.
+#define ADI_3_REFSYS_DCDCCTL5_TESTP 0x00000010
+#define ADI_3_REFSYS_DCDCCTL5_TESTP_M 0x00000010
+#define ADI_3_REFSYS_DCDCCTL5_TESTP_S 4
+
+// Field: [3] DITHER_EN
+//
+// Internal. Only to be used through TI provided API.
+// ENUMs:
+// EN Internal. Only to be used through TI provided API.
+// DIS Internal. Only to be used through TI provided API.
+#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN 0x00000008
+#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_M 0x00000008
+#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_S 3
+#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_EN 0x00000008
+#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_DIS 0x00000000
+
+// Field: [2:0] IPEAK
+//
+// Internal. Only to be used through TI provided API.
+#define ADI_3_REFSYS_DCDCCTL5_IPEAK_W 3
+#define ADI_3_REFSYS_DCDCCTL5_IPEAK_M 0x00000007
+#define ADI_3_REFSYS_DCDCCTL5_IPEAK_S 0
+
+//*****************************************************************************
+//
+// Register: ADI_3_REFSYS_O_AUX_DEBUG
+//
+//*****************************************************************************
+// Field: [6] LPM_BIAS_BACKUP_EN
+//
+// Activate the backup circuit in case the main circuit does not work
+#define ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN 0x00000040
+#define ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN_M 0x00000040
+#define ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN_S 6
+
+// Field: [5] DAC_DBG_OFFSET_COMP
+//
+// Offset compensation signal (Debug Mode)
+#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_OFFSET_COMP 0x00000020
+#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_OFFSET_COMP_M 0x00000020
+#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_OFFSET_COMP_S 5
+
+// Field: [4] DAC_DBG_HOLD
+//
+// S-H Cap hold signal (Debug Mode)
+#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_HOLD 0x00000010
+#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_HOLD_M 0x00000010
+#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_HOLD_S 4
+
+// Field: [3] DAC_DBG_PRECHARGE
+//
+// PRE-CHARGE signal (Debug Mode)
+#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_PRECHARGE 0x00000008
+#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_PRECHARGE_M 0x00000008
+#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_PRECHARGE_S 3
+
+// Field: [2] DAC_DBG_CAP_SAMPLE
+//
+// Cap-array sample signal (Debug Mode)
+#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_CAP_SAMPLE 0x00000004
+#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_CAP_SAMPLE_M 0x00000004
+#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_CAP_SAMPLE_S 2
+
+// Field: [1] DAC_DBG_SAMPLE
+//
+// S-H Cap sample signal (Debug Mode)
+#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_SAMPLE 0x00000002
+#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_SAMPLE_M 0x00000002
+#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_SAMPLE_S 1
+
+// Field: [0] DAC_DBG_EN
+//
+// Enable Debug Mode
+#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_EN 0x00000001
+#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_EN_M 0x00000001
+#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_EN_S 0
+
+//*****************************************************************************
+//
+// Register: ADI_3_REFSYS_O_CTL_RECHARGE_CMP0
+//
+//*****************************************************************************
+// Field: [4] COMP_CLK_DISABLE
+//
+// Enable/Disable the 32 kHz clock (SCLK_LF) to the recharge comparator
+// ENUMs:
+// DIS Disable the clock
+// EN Enable the clock
+#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_COMP_CLK_DISABLE 0x00000010
+#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_COMP_CLK_DISABLE_M 0x00000010
+#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_COMP_CLK_DISABLE_S 4
+#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_COMP_CLK_DISABLE_DIS 0x00000010
+#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_COMP_CLK_DISABLE_EN 0x00000000
+
+// Field: [3:0] TRIM_RECHARGE_COMP_REFLEVEL
+//
+// Trim ref level of recharge.
+//
+// 0xF: 90% of VDDR level.
+// 0x0: 100% of VDDR level.
+//
+// Step size = 0.67% of VDDR level.
+#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL_W \
+ 4
+#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL_M \
+ 0x0000000F
+#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL_S \
+ 0
+
+//*****************************************************************************
+//
+// Register: ADI_3_REFSYS_O_CTL_RECHARGE_CMP1
+//
+//*****************************************************************************
+// Field: [7] RECHARGE_BLOCK_VTRIG_EN
+//
+// Enable/Disable ATEST input to VDDR input of recharge comparator. Used for
+// trimming the recharge voltage reference level
+// ENUMs:
+// EN Enable. VDDR input is connected to ATEST network
+// DIS Disable. VDDR input is connected to VDDR itself
+#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_VTRIG_EN 0x00000080
+#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_VTRIG_EN_M \
+ 0x00000080
+#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_VTRIG_EN_S \
+ 7
+#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_VTRIG_EN_EN \
+ 0x00000080
+#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_VTRIG_EN_DIS \
+ 0x00000000
+
+// Field: [6] RECHARGE_BLOCK_ATEST_EN
+//
+// Enable/Disable test inputs/outputs to recharge comparator block
+// ENUMs:
+// EN Enable
+// DIS Disable
+#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_ATEST_EN 0x00000040
+#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_ATEST_EN_M \
+ 0x00000040
+#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_ATEST_EN_S \
+ 6
+#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_ATEST_EN_EN \
+ 0x00000040
+#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_ATEST_EN_DIS \
+ 0x00000000
+
+// Field: [5] FORCE_SAMPLE_VDDR
+//
+// Force Sample of VDDR on cap divider
+// ENUMs:
+// EN Enable
+// DIS Disable
+#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_FORCE_SAMPLE_VDDR 0x00000020
+#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_FORCE_SAMPLE_VDDR_M 0x00000020
+#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_FORCE_SAMPLE_VDDR_S 5
+#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_FORCE_SAMPLE_VDDR_EN 0x00000020
+#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_FORCE_SAMPLE_VDDR_DIS 0x00000000
+
+// Field: [4:0] TRIM_RECHARGE_COMP_OFFSET
+//
+// Trim offset of Recharge comparator.
+//
+// 0x00: Maximum degeneration on input side (VDDR side).
+// 0x1F: Maximum degeneration on reference side from cap divider.
+// 0x10: Nominal code.
+#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_TRIM_RECHARGE_COMP_OFFSET_W \
+ 5
+#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_TRIM_RECHARGE_COMP_OFFSET_M \
+ 0x0000001F
+#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_TRIM_RECHARGE_COMP_OFFSET_S \
+ 0
+
+
+#endif // __ADI_3_REFSYS__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_4_aux.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_4_aux.h
new file mode 100644
index 0000000..45fdfc3
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_4_aux.h
@@ -0,0 +1,513 @@
+/******************************************************************************
+* Filename: hw_adi_4_aux_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_ADI_4_AUX_H__
+#define __HW_ADI_4_AUX_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// ADI_4_AUX component
+//
+//*****************************************************************************
+// Internal
+#define ADI_4_AUX_O_MUX0 0x00000000
+
+// Internal
+#define ADI_4_AUX_O_MUX1 0x00000001
+
+// Internal
+#define ADI_4_AUX_O_MUX2 0x00000002
+
+// Internal
+#define ADI_4_AUX_O_MUX3 0x00000003
+
+// Current Source
+#define ADI_4_AUX_O_ISRC 0x00000004
+
+// Comparator
+#define ADI_4_AUX_O_COMP 0x00000005
+
+// Internal
+#define ADI_4_AUX_O_MUX4 0x00000007
+
+// ADC Control 0
+#define ADI_4_AUX_O_ADC0 0x00000008
+
+// ADC Control 1
+#define ADI_4_AUX_O_ADC1 0x00000009
+
+// ADC Reference 0
+#define ADI_4_AUX_O_ADCREF0 0x0000000A
+
+// ADC Reference 1
+#define ADI_4_AUX_O_ADCREF1 0x0000000B
+
+// Internal
+#define ADI_4_AUX_O_LPMBIAS 0x0000000E
+
+//*****************************************************************************
+//
+// Register: ADI_4_AUX_O_MUX0
+//
+//*****************************************************************************
+// Field: [6] ADCCOMPB_IN
+//
+// Internal. Only to be used through TI provided API.
+// ENUMs:
+// VDDR_1P8V Internal. Only to be used through TI provided API.
+// NC Internal. Only to be used through TI provided API.
+#define ADI_4_AUX_MUX0_ADCCOMPB_IN 0x00000040
+#define ADI_4_AUX_MUX0_ADCCOMPB_IN_M 0x00000040
+#define ADI_4_AUX_MUX0_ADCCOMPB_IN_S 6
+#define ADI_4_AUX_MUX0_ADCCOMPB_IN_VDDR_1P8V 0x00000040
+#define ADI_4_AUX_MUX0_ADCCOMPB_IN_NC 0x00000000
+
+// Field: [3:0] COMPA_REF
+//
+// Internal. Only to be used through TI provided API.
+// ENUMs:
+// ADCVREFP Internal. Only to be used through TI provided API.
+// VDDS Internal. Only to be used through TI provided API.
+// VSS Internal. Only to be used through TI provided API.
+// DCOUPL Internal. Only to be used through TI provided API.
+// NC Internal. Only to be used through TI provided API.
+#define ADI_4_AUX_MUX0_COMPA_REF_W 4
+#define ADI_4_AUX_MUX0_COMPA_REF_M 0x0000000F
+#define ADI_4_AUX_MUX0_COMPA_REF_S 0
+#define ADI_4_AUX_MUX0_COMPA_REF_ADCVREFP 0x00000008
+#define ADI_4_AUX_MUX0_COMPA_REF_VDDS 0x00000004
+#define ADI_4_AUX_MUX0_COMPA_REF_VSS 0x00000002
+#define ADI_4_AUX_MUX0_COMPA_REF_DCOUPL 0x00000001
+#define ADI_4_AUX_MUX0_COMPA_REF_NC 0x00000000
+
+//*****************************************************************************
+//
+// Register: ADI_4_AUX_O_MUX1
+//
+//*****************************************************************************
+// Field: [7:0] COMPA_IN
+//
+// Internal. Only to be used through TI provided API.
+// ENUMs:
+// AUXIO19 Internal. Only to be used through TI provided API.
+// AUXIO20 Internal. Only to be used through TI provided API.
+// AUXIO21 Internal. Only to be used through TI provided API.
+// AUXIO22 Internal. Only to be used through TI provided API.
+// AUXIO23 Internal. Only to be used through TI provided API.
+// AUXIO24 Internal. Only to be used through TI provided API.
+// AUXIO25 Internal. Only to be used through TI provided API.
+// AUXIO26 Internal. Only to be used through TI provided API.
+// NC Internal. Only to be used through TI provided API.
+#define ADI_4_AUX_MUX1_COMPA_IN_W 8
+#define ADI_4_AUX_MUX1_COMPA_IN_M 0x000000FF
+#define ADI_4_AUX_MUX1_COMPA_IN_S 0
+#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO19 0x00000080
+#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO20 0x00000040
+#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO21 0x00000020
+#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO22 0x00000010
+#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO23 0x00000008
+#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO24 0x00000004
+#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO25 0x00000002
+#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO26 0x00000001
+#define ADI_4_AUX_MUX1_COMPA_IN_NC 0x00000000
+
+//*****************************************************************************
+//
+// Register: ADI_4_AUX_O_MUX2
+//
+//*****************************************************************************
+// Field: [7:3] ADCCOMPB_IN
+//
+// Internal. Only to be used through TI provided API.
+// ENUMs:
+// VDDS Internal. Only to be used through TI provided API.
+// VSS Internal. Only to be used through TI provided API.
+// DCOUPL Internal. Only to be used through TI provided API.
+// ATEST1 Internal. Only to be used through TI provided API.
+// ATEST0 Internal. Only to be used through TI provided API.
+// NC Internal. Only to be used through TI provided API.
+#define ADI_4_AUX_MUX2_ADCCOMPB_IN_W 5
+#define ADI_4_AUX_MUX2_ADCCOMPB_IN_M 0x000000F8
+#define ADI_4_AUX_MUX2_ADCCOMPB_IN_S 3
+#define ADI_4_AUX_MUX2_ADCCOMPB_IN_VDDS 0x00000080
+#define ADI_4_AUX_MUX2_ADCCOMPB_IN_VSS 0x00000040
+#define ADI_4_AUX_MUX2_ADCCOMPB_IN_DCOUPL 0x00000020
+#define ADI_4_AUX_MUX2_ADCCOMPB_IN_ATEST1 0x00000010
+#define ADI_4_AUX_MUX2_ADCCOMPB_IN_ATEST0 0x00000008
+#define ADI_4_AUX_MUX2_ADCCOMPB_IN_NC 0x00000000
+
+// Field: [2:0] DAC_VREF_SEL
+//
+// Internal. Only to be used through TI provided API.
+// ENUMs:
+// VDDS Internal. Only to be used through TI provided API.
+// ADCREF Internal. Only to be used through TI provided API.
+// DCOUPL Internal. Only to be used through TI provided API.
+// NC Internal. Only to be used through TI provided API.
+#define ADI_4_AUX_MUX2_DAC_VREF_SEL_W 3
+#define ADI_4_AUX_MUX2_DAC_VREF_SEL_M 0x00000007
+#define ADI_4_AUX_MUX2_DAC_VREF_SEL_S 0
+#define ADI_4_AUX_MUX2_DAC_VREF_SEL_VDDS 0x00000004
+#define ADI_4_AUX_MUX2_DAC_VREF_SEL_ADCREF 0x00000002
+#define ADI_4_AUX_MUX2_DAC_VREF_SEL_DCOUPL 0x00000001
+#define ADI_4_AUX_MUX2_DAC_VREF_SEL_NC 0x00000000
+
+//*****************************************************************************
+//
+// Register: ADI_4_AUX_O_MUX3
+//
+//*****************************************************************************
+// Field: [7:0] ADCCOMPB_IN
+//
+// Internal. Only to be used through TI provided API.
+// ENUMs:
+// AUXIO19 Internal. Only to be used through TI provided API.
+// AUXIO20 Internal. Only to be used through TI provided API.
+// AUXIO21 Internal. Only to be used through TI provided API.
+// AUXIO22 Internal. Only to be used through TI provided API.
+// AUXIO23 Internal. Only to be used through TI provided API.
+// AUXIO24 Internal. Only to be used through TI provided API.
+// AUXIO25 Internal. Only to be used through TI provided API.
+// AUXIO26 Internal. Only to be used through TI provided API.
+// NC Internal. Only to be used through TI provided API.
+#define ADI_4_AUX_MUX3_ADCCOMPB_IN_W 8
+#define ADI_4_AUX_MUX3_ADCCOMPB_IN_M 0x000000FF
+#define ADI_4_AUX_MUX3_ADCCOMPB_IN_S 0
+#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO19 0x00000080
+#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO20 0x00000040
+#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO21 0x00000020
+#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO22 0x00000010
+#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO23 0x00000008
+#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO24 0x00000004
+#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO25 0x00000002
+#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO26 0x00000001
+#define ADI_4_AUX_MUX3_ADCCOMPB_IN_NC 0x00000000
+
+//*****************************************************************************
+//
+// Register: ADI_4_AUX_O_ISRC
+//
+//*****************************************************************************
+// Field: [7:2] TRIM
+//
+// Adjust current from current source.
+//
+// Output currents may be combined to get desired total current.
+// ENUMs:
+// 11P75U 11.75 uA
+// 4P5U 4.5 uA
+// 2P0U 2.0 uA
+// 1P0U 1.0 uA
+// 0P5U 0.5 uA
+// 0P25U 0.25 uA
+// NC No current connected
+#define ADI_4_AUX_ISRC_TRIM_W 6
+#define ADI_4_AUX_ISRC_TRIM_M 0x000000FC
+#define ADI_4_AUX_ISRC_TRIM_S 2
+#define ADI_4_AUX_ISRC_TRIM_11P75U 0x00000080
+#define ADI_4_AUX_ISRC_TRIM_4P5U 0x00000040
+#define ADI_4_AUX_ISRC_TRIM_2P0U 0x00000020
+#define ADI_4_AUX_ISRC_TRIM_1P0U 0x00000010
+#define ADI_4_AUX_ISRC_TRIM_0P5U 0x00000008
+#define ADI_4_AUX_ISRC_TRIM_0P25U 0x00000004
+#define ADI_4_AUX_ISRC_TRIM_NC 0x00000000
+
+// Field: [0] EN
+//
+// Current source enable
+#define ADI_4_AUX_ISRC_EN 0x00000001
+#define ADI_4_AUX_ISRC_EN_M 0x00000001
+#define ADI_4_AUX_ISRC_EN_S 0
+
+//*****************************************************************************
+//
+// Register: ADI_4_AUX_O_COMP
+//
+//*****************************************************************************
+// Field: [7] COMPA_REF_RES_EN
+//
+// Enables 400kohm resistance from COMPA reference node to ground. Used with
+// COMPA_REF_CURR_EN to generate voltage reference for cap-sense.
+#define ADI_4_AUX_COMP_COMPA_REF_RES_EN 0x00000080
+#define ADI_4_AUX_COMP_COMPA_REF_RES_EN_M 0x00000080
+#define ADI_4_AUX_COMP_COMPA_REF_RES_EN_S 7
+
+// Field: [6] COMPA_REF_CURR_EN
+//
+// Enables 2uA IPTAT current from ISRC to COMPA reference node. Requires
+// ISRC.EN = 1. Used with COMPA_REF_RES_EN to generate voltage reference for
+// cap-sense.
+#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN 0x00000040
+#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN_M 0x00000040
+#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN_S 6
+
+// Field: [5:3] LPM_BIAS_WIDTH_TRIM
+//
+// Internal. Only to be used through TI provided API.
+#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_W 3
+#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_M 0x00000038
+#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_S 3
+
+// Field: [2] COMPB_EN
+//
+// COMPB enable
+#define ADI_4_AUX_COMP_COMPB_EN 0x00000004
+#define ADI_4_AUX_COMP_COMPB_EN_M 0x00000004
+#define ADI_4_AUX_COMP_COMPB_EN_S 2
+
+// Field: [0] COMPA_EN
+//
+// COMPA enable
+#define ADI_4_AUX_COMP_COMPA_EN 0x00000001
+#define ADI_4_AUX_COMP_COMPA_EN_M 0x00000001
+#define ADI_4_AUX_COMP_COMPA_EN_S 0
+
+//*****************************************************************************
+//
+// Register: ADI_4_AUX_O_MUX4
+//
+//*****************************************************************************
+// Field: [7:0] COMPA_REF
+//
+// Internal. Only to be used through TI provided API.
+// ENUMs:
+// AUXIO19 Internal. Only to be used through TI provided API.
+// AUXIO20 Internal. Only to be used through TI provided API.
+// AUXIO21 Internal. Only to be used through TI provided API.
+// AUXIO22 Internal. Only to be used through TI provided API.
+// AUXIO23 Internal. Only to be used through TI provided API.
+// AUXIO24 Internal. Only to be used through TI provided API.
+// AUXIO25 Internal. Only to be used through TI provided API.
+// AUXIO26 Internal. Only to be used through TI provided API.
+// NC Internal. Only to be used through TI provided API.
+#define ADI_4_AUX_MUX4_COMPA_REF_W 8
+#define ADI_4_AUX_MUX4_COMPA_REF_M 0x000000FF
+#define ADI_4_AUX_MUX4_COMPA_REF_S 0
+#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO19 0x00000080
+#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO20 0x00000040
+#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO21 0x00000020
+#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO22 0x00000010
+#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO23 0x00000008
+#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO24 0x00000004
+#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO25 0x00000002
+#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO26 0x00000001
+#define ADI_4_AUX_MUX4_COMPA_REF_NC 0x00000000
+
+//*****************************************************************************
+//
+// Register: ADI_4_AUX_O_ADC0
+//
+//*****************************************************************************
+// Field: [7] SMPL_MODE
+//
+// ADC Sampling mode:
+//
+// 0: Synchronous mode
+// 1: Asynchronous mode
+//
+// The ADC does a sample-and-hold before conversion. In synchronous mode the
+// sampling starts when the ADC clock detects a rising edge on the trigger
+// signal. Jitter/uncertainty will be inferred in the detection if the trigger
+// signal originates from a domain that is asynchronous to the ADC clock.
+// SMPL_CYCLE_EXP determines the the duration of sampling.
+// Conversion starts immediately after sampling ends.
+//
+// In asynchronous mode the sampling is continuous when enabled. Sampling ends
+// and conversion starts immediately with the rising edge of the trigger
+// signal. Sampling restarts when the conversion has finished.
+// Asynchronous mode is useful when it is important to avoid jitter in the
+// sampling instant of an externally driven signal
+#define ADI_4_AUX_ADC0_SMPL_MODE 0x00000080
+#define ADI_4_AUX_ADC0_SMPL_MODE_M 0x00000080
+#define ADI_4_AUX_ADC0_SMPL_MODE_S 7
+
+// Field: [6:3] SMPL_CYCLE_EXP
+//
+// Controls the sampling duration before conversion when the ADC is operated in
+// synchronous mode (SMPL_MODE = 0). The setting has no effect in asynchronous
+// mode. The sampling duration is given as 2^(SMPL_CYCLE_EXP + 1) / 6 us.
+// ENUMs:
+// 10P9_MS 65536x 6 MHz clock periods = 10.9ms
+// 5P46_MS 32768x 6 MHz clock periods = 5.46ms
+// 2P73_MS 16384x 6 MHz clock periods = 2.73ms
+// 1P37_MS 8192x 6 MHz clock periods = 1.37ms
+// 682_US 4096x 6 MHz clock periods = 682us
+// 341_US 2048x 6 MHz clock periods = 341us
+// 170_US 1024x 6 MHz clock periods = 170us
+// 85P3_US 512x 6 MHz clock periods = 85.3us
+// 42P6_US 256x 6 MHz clock periods = 42.6us
+// 21P3_US 128x 6 MHz clock periods = 21.3us
+// 10P6_US 64x 6 MHz clock periods = 10.6us
+// 5P3_US 32x 6 MHz clock periods = 5.3us
+// 2P7_US 16x 6 MHz clock periods = 2.7us
+#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_W 4
+#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_M 0x00000078
+#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_S 3
+#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_10P9_MS 0x00000078
+#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_5P46_MS 0x00000070
+#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_2P73_MS 0x00000068
+#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_1P37_MS 0x00000060
+#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_682_US 0x00000058
+#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_341_US 0x00000050
+#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_170_US 0x00000048
+#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_85P3_US 0x00000040
+#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_42P6_US 0x00000038
+#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_21P3_US 0x00000030
+#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_10P6_US 0x00000028
+#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_5P3_US 0x00000020
+#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_2P7_US 0x00000018
+
+// Field: [1] RESET_N
+//
+// Reset ADC digital subchip, active low. ADC must be reset every time it is
+// reconfigured.
+//
+// 0: Reset
+// 1: Normal operation
+#define ADI_4_AUX_ADC0_RESET_N 0x00000002
+#define ADI_4_AUX_ADC0_RESET_N_M 0x00000002
+#define ADI_4_AUX_ADC0_RESET_N_S 1
+
+// Field: [0] EN
+//
+// ADC Enable
+//
+// 0: Disable
+// 1: Enable
+#define ADI_4_AUX_ADC0_EN 0x00000001
+#define ADI_4_AUX_ADC0_EN_M 0x00000001
+#define ADI_4_AUX_ADC0_EN_S 0
+
+//*****************************************************************************
+//
+// Register: ADI_4_AUX_O_ADC1
+//
+//*****************************************************************************
+// Field: [0] SCALE_DIS
+//
+// Internal. Only to be used through TI provided API.
+#define ADI_4_AUX_ADC1_SCALE_DIS 0x00000001
+#define ADI_4_AUX_ADC1_SCALE_DIS_M 0x00000001
+#define ADI_4_AUX_ADC1_SCALE_DIS_S 0
+
+//*****************************************************************************
+//
+// Register: ADI_4_AUX_O_ADCREF0
+//
+//*****************************************************************************
+// Field: [6] REF_ON_IDLE
+//
+// Enable ADCREF in IDLE state.
+//
+// 0: Disabled in IDLE state
+// 1: Enabled in IDLE state
+//
+// Keep ADCREF enabled when ADC0.SMPL_MODE = 0.
+// Recommendation: Enable ADCREF always when ADC0.SMPL_CYCLE_EXP is less than
+// 0x6 (21.3us sampling time).
+#define ADI_4_AUX_ADCREF0_REF_ON_IDLE 0x00000040
+#define ADI_4_AUX_ADCREF0_REF_ON_IDLE_M 0x00000040
+#define ADI_4_AUX_ADCREF0_REF_ON_IDLE_S 6
+
+// Field: [5] IOMUX
+//
+// Internal. Only to be used through TI provided API.
+#define ADI_4_AUX_ADCREF0_IOMUX 0x00000020
+#define ADI_4_AUX_ADCREF0_IOMUX_M 0x00000020
+#define ADI_4_AUX_ADCREF0_IOMUX_S 5
+
+// Field: [4] EXT
+//
+// Internal. Only to be used through TI provided API.
+#define ADI_4_AUX_ADCREF0_EXT 0x00000010
+#define ADI_4_AUX_ADCREF0_EXT_M 0x00000010
+#define ADI_4_AUX_ADCREF0_EXT_S 4
+
+// Field: [3] SRC
+//
+// ADC reference source:
+//
+// 0: Fixed reference = 4.3V
+// 1: Relative reference = VDDS
+#define ADI_4_AUX_ADCREF0_SRC 0x00000008
+#define ADI_4_AUX_ADCREF0_SRC_M 0x00000008
+#define ADI_4_AUX_ADCREF0_SRC_S 3
+
+// Field: [0] EN
+//
+// ADC reference module enable:
+//
+// 0: ADC reference module powered down
+// 1: ADC reference module enabled
+#define ADI_4_AUX_ADCREF0_EN 0x00000001
+#define ADI_4_AUX_ADCREF0_EN_M 0x00000001
+#define ADI_4_AUX_ADCREF0_EN_S 0
+
+//*****************************************************************************
+//
+// Register: ADI_4_AUX_O_ADCREF1
+//
+//*****************************************************************************
+// Field: [5:0] VTRIM
+//
+// Trim output voltage of ADC fixed reference (64 steps, 2's complement).
+// Applies only for ADCREF0.SRC = 0.
+//
+// Examples:
+// 0x00 - nominal voltage 1.43V
+// 0x01 - nominal + 0.4% 1.435V
+// 0x3F - nominal - 0.4% 1.425V
+// 0x1F - maximum voltage 1.6V
+// 0x20 - minimum voltage 1.3V
+#define ADI_4_AUX_ADCREF1_VTRIM_W 6
+#define ADI_4_AUX_ADCREF1_VTRIM_M 0x0000003F
+#define ADI_4_AUX_ADCREF1_VTRIM_S 0
+
+//*****************************************************************************
+//
+// Register: ADI_4_AUX_O_LPMBIAS
+//
+//*****************************************************************************
+// Field: [5:0] LPM_TRIM_IOUT
+//
+// Internal. Only to be used through TI provided API.
+#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_W 6
+#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_M 0x0000003F
+#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_S 0
+
+
+#endif // __ADI_4_AUX__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_batmon.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_batmon.h
new file mode 100644
index 0000000..ded130e
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_batmon.h
@@ -0,0 +1,662 @@
+/******************************************************************************
+* Filename: hw_aon_batmon_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_AON_BATMON_H__
+#define __HW_AON_BATMON_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// AON_BATMON component
+//
+//*****************************************************************************
+// Internal
+#define AON_BATMON_O_CTL 0x00000000
+
+// Internal
+#define AON_BATMON_O_MEASCFG 0x00000004
+
+// Internal
+#define AON_BATMON_O_TEMPP0 0x0000000C
+
+// Internal
+#define AON_BATMON_O_TEMPP1 0x00000010
+
+// Internal
+#define AON_BATMON_O_TEMPP2 0x00000014
+
+// Internal
+#define AON_BATMON_O_BATMONP0 0x00000018
+
+// Internal
+#define AON_BATMON_O_BATMONP1 0x0000001C
+
+// Internal
+#define AON_BATMON_O_IOSTRP0 0x00000020
+
+// Internal
+#define AON_BATMON_O_FLASHPUMPP0 0x00000024
+
+// Last Measured Battery Voltage
+#define AON_BATMON_O_BAT 0x00000028
+
+// Battery Update
+#define AON_BATMON_O_BATUPD 0x0000002C
+
+// Temperature
+#define AON_BATMON_O_TEMP 0x00000030
+
+// Temperature Update
+#define AON_BATMON_O_TEMPUPD 0x00000034
+
+// Event Mask
+#define AON_BATMON_O_EVENTMASK 0x00000048
+
+// Event
+#define AON_BATMON_O_EVENT 0x0000004C
+
+// Battery Upper Limit
+#define AON_BATMON_O_BATTUL 0x00000050
+
+// Battery Lower Limit
+#define AON_BATMON_O_BATTLL 0x00000054
+
+// Temperature Upper Limit
+#define AON_BATMON_O_TEMPUL 0x00000058
+
+// Temperature Lower Limit
+#define AON_BATMON_O_TEMPLL 0x0000005C
+
+//*****************************************************************************
+//
+// Register: AON_BATMON_O_CTL
+//
+//*****************************************************************************
+// Field: [1] CALC_EN
+//
+// Internal. Only to be used through TI provided API.
+#define AON_BATMON_CTL_CALC_EN 0x00000002
+#define AON_BATMON_CTL_CALC_EN_BITN 1
+#define AON_BATMON_CTL_CALC_EN_M 0x00000002
+#define AON_BATMON_CTL_CALC_EN_S 1
+
+// Field: [0] MEAS_EN
+//
+// Internal. Only to be used through TI provided API.
+#define AON_BATMON_CTL_MEAS_EN 0x00000001
+#define AON_BATMON_CTL_MEAS_EN_BITN 0
+#define AON_BATMON_CTL_MEAS_EN_M 0x00000001
+#define AON_BATMON_CTL_MEAS_EN_S 0
+
+//*****************************************************************************
+//
+// Register: AON_BATMON_O_MEASCFG
+//
+//*****************************************************************************
+// Field: [1:0] PER
+//
+// Internal. Only to be used through TI provided API.
+// ENUMs:
+// 32CYC Internal. Only to be used through TI provided API.
+// 16CYC Internal. Only to be used through TI provided API.
+// 8CYC Internal. Only to be used through TI provided API.
+// CONT Internal. Only to be used through TI provided API.
+#define AON_BATMON_MEASCFG_PER_W 2
+#define AON_BATMON_MEASCFG_PER_M 0x00000003
+#define AON_BATMON_MEASCFG_PER_S 0
+#define AON_BATMON_MEASCFG_PER_32CYC 0x00000003
+#define AON_BATMON_MEASCFG_PER_16CYC 0x00000002
+#define AON_BATMON_MEASCFG_PER_8CYC 0x00000001
+#define AON_BATMON_MEASCFG_PER_CONT 0x00000000
+
+//*****************************************************************************
+//
+// Register: AON_BATMON_O_TEMPP0
+//
+//*****************************************************************************
+// Field: [7:0] CFG
+//
+// Internal. Only to be used through TI provided API.
+#define AON_BATMON_TEMPP0_CFG_W 8
+#define AON_BATMON_TEMPP0_CFG_M 0x000000FF
+#define AON_BATMON_TEMPP0_CFG_S 0
+
+//*****************************************************************************
+//
+// Register: AON_BATMON_O_TEMPP1
+//
+//*****************************************************************************
+// Field: [5:0] CFG
+//
+// Internal. Only to be used through TI provided API.
+#define AON_BATMON_TEMPP1_CFG_W 6
+#define AON_BATMON_TEMPP1_CFG_M 0x0000003F
+#define AON_BATMON_TEMPP1_CFG_S 0
+
+//*****************************************************************************
+//
+// Register: AON_BATMON_O_TEMPP2
+//
+//*****************************************************************************
+// Field: [4:0] CFG
+//
+// Internal. Only to be used through TI provided API.
+#define AON_BATMON_TEMPP2_CFG_W 5
+#define AON_BATMON_TEMPP2_CFG_M 0x0000001F
+#define AON_BATMON_TEMPP2_CFG_S 0
+
+//*****************************************************************************
+//
+// Register: AON_BATMON_O_BATMONP0
+//
+//*****************************************************************************
+// Field: [6:0] CFG
+//
+// Internal. Only to be used through TI provided API.
+#define AON_BATMON_BATMONP0_CFG_W 7
+#define AON_BATMON_BATMONP0_CFG_M 0x0000007F
+#define AON_BATMON_BATMONP0_CFG_S 0
+
+//*****************************************************************************
+//
+// Register: AON_BATMON_O_BATMONP1
+//
+//*****************************************************************************
+// Field: [5:0] CFG
+//
+// Internal. Only to be used through TI provided API.
+#define AON_BATMON_BATMONP1_CFG_W 6
+#define AON_BATMON_BATMONP1_CFG_M 0x0000003F
+#define AON_BATMON_BATMONP1_CFG_S 0
+
+//*****************************************************************************
+//
+// Register: AON_BATMON_O_IOSTRP0
+//
+//*****************************************************************************
+// Field: [5:4] CFG2
+//
+// Internal. Only to be used through TI provided API.
+#define AON_BATMON_IOSTRP0_CFG2_W 2
+#define AON_BATMON_IOSTRP0_CFG2_M 0x00000030
+#define AON_BATMON_IOSTRP0_CFG2_S 4
+
+// Field: [3:0] CFG1
+//
+// Internal. Only to be used through TI provided API.
+#define AON_BATMON_IOSTRP0_CFG1_W 4
+#define AON_BATMON_IOSTRP0_CFG1_M 0x0000000F
+#define AON_BATMON_IOSTRP0_CFG1_S 0
+
+//*****************************************************************************
+//
+// Register: AON_BATMON_O_FLASHPUMPP0
+//
+//*****************************************************************************
+// Field: [9] DIS_NOISE_FILTER
+//
+// Internal. Only to be used through TI provided API.
+#define AON_BATMON_FLASHPUMPP0_DIS_NOISE_FILTER 0x00000200
+#define AON_BATMON_FLASHPUMPP0_DIS_NOISE_FILTER_BITN 9
+#define AON_BATMON_FLASHPUMPP0_DIS_NOISE_FILTER_M 0x00000200
+#define AON_BATMON_FLASHPUMPP0_DIS_NOISE_FILTER_S 9
+
+// Field: [8] FALLB
+//
+// Internal. Only to be used through TI provided API.
+#define AON_BATMON_FLASHPUMPP0_FALLB 0x00000100
+#define AON_BATMON_FLASHPUMPP0_FALLB_BITN 8
+#define AON_BATMON_FLASHPUMPP0_FALLB_M 0x00000100
+#define AON_BATMON_FLASHPUMPP0_FALLB_S 8
+
+// Field: [7:6] HIGHLIM
+//
+// Internal. Only to be used through TI provided API.
+#define AON_BATMON_FLASHPUMPP0_HIGHLIM_W 2
+#define AON_BATMON_FLASHPUMPP0_HIGHLIM_M 0x000000C0
+#define AON_BATMON_FLASHPUMPP0_HIGHLIM_S 6
+
+// Field: [5] LOWLIM
+//
+// Internal. Only to be used through TI provided API.
+#define AON_BATMON_FLASHPUMPP0_LOWLIM 0x00000020
+#define AON_BATMON_FLASHPUMPP0_LOWLIM_BITN 5
+#define AON_BATMON_FLASHPUMPP0_LOWLIM_M 0x00000020
+#define AON_BATMON_FLASHPUMPP0_LOWLIM_S 5
+
+// Field: [4] OVR
+//
+// Internal. Only to be used through TI provided API.
+#define AON_BATMON_FLASHPUMPP0_OVR 0x00000010
+#define AON_BATMON_FLASHPUMPP0_OVR_BITN 4
+#define AON_BATMON_FLASHPUMPP0_OVR_M 0x00000010
+#define AON_BATMON_FLASHPUMPP0_OVR_S 4
+
+// Field: [3:0] CFG
+//
+// Internal. Only to be used through TI provided API.
+#define AON_BATMON_FLASHPUMPP0_CFG_W 4
+#define AON_BATMON_FLASHPUMPP0_CFG_M 0x0000000F
+#define AON_BATMON_FLASHPUMPP0_CFG_S 0
+
+//*****************************************************************************
+//
+// Register: AON_BATMON_O_BAT
+//
+//*****************************************************************************
+// Field: [10:8] INT
+//
+// Integer part:
+//
+// 0x0: 0V + fractional part
+// ...
+// 0x3: 3V + fractional part
+// 0x4: 4V + fractional part
+#define AON_BATMON_BAT_INT_W 3
+#define AON_BATMON_BAT_INT_M 0x00000700
+#define AON_BATMON_BAT_INT_S 8
+
+// Field: [7:0] FRAC
+//
+// Fractional part, standard binary fractional encoding.
+//
+// 0x00: .0V
+// ...
+// 0x20: 1/8 = .125V
+// 0x40: 1/4 = .25V
+// 0x80: 1/2 = .5V
+// ...
+// 0xA0: 1/2 + 1/8 = .625V
+// ...
+// 0xFF: Max
+#define AON_BATMON_BAT_FRAC_W 8
+#define AON_BATMON_BAT_FRAC_M 0x000000FF
+#define AON_BATMON_BAT_FRAC_S 0
+
+//*****************************************************************************
+//
+// Register: AON_BATMON_O_BATUPD
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+//
+// 0: No update since last clear
+// 1: New battery voltage is present.
+//
+// Write 1 to clear the status.
+#define AON_BATMON_BATUPD_STAT 0x00000001
+#define AON_BATMON_BATUPD_STAT_BITN 0
+#define AON_BATMON_BATUPD_STAT_M 0x00000001
+#define AON_BATMON_BATUPD_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: AON_BATMON_O_TEMP
+//
+//*****************************************************************************
+// Field: [16:8] INT
+//
+// Integer part (signed) of temperature value.
+// Total value = INTEGER + FRACTIONAL
+// 2's complement encoding
+//
+// 0x100: Min value
+// 0x1D8: -40C
+// 0x1FF: -1C
+// 0x00: 0C
+// 0x1B: 27C
+// 0x55: 85C
+// 0xFF: Max value
+#define AON_BATMON_TEMP_INT_W 9
+#define AON_BATMON_TEMP_INT_M 0x0001FF00
+#define AON_BATMON_TEMP_INT_S 8
+
+//*****************************************************************************
+//
+// Register: AON_BATMON_O_TEMPUPD
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+//
+// 0: No update since last clear
+// 1: New temperature is present.
+//
+// Write 1 to clear the status.
+#define AON_BATMON_TEMPUPD_STAT 0x00000001
+#define AON_BATMON_TEMPUPD_STAT_BITN 0
+#define AON_BATMON_TEMPUPD_STAT_M 0x00000001
+#define AON_BATMON_TEMPUPD_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: AON_BATMON_O_EVENTMASK
+//
+//*****************************************************************************
+// Field: [5] TEMP_UPDATE_MASK
+//
+// 1: EVENT.TEMP_UPDATE contributes to combined event from BATMON
+// 0: EVENT.TEMP_UPDATE does not contribute to combined event from BATMON
+#define AON_BATMON_EVENTMASK_TEMP_UPDATE_MASK 0x00000020
+#define AON_BATMON_EVENTMASK_TEMP_UPDATE_MASK_BITN 5
+#define AON_BATMON_EVENTMASK_TEMP_UPDATE_MASK_M 0x00000020
+#define AON_BATMON_EVENTMASK_TEMP_UPDATE_MASK_S 5
+
+// Field: [4] BATT_UPDATE_MASK
+//
+// 1: EVENT.BATT_UPDATE contributes to combined event from BATMON
+// 0: EVENT.BATT_UPDATE does not contribute to combined event from BATMON
+#define AON_BATMON_EVENTMASK_BATT_UPDATE_MASK 0x00000010
+#define AON_BATMON_EVENTMASK_BATT_UPDATE_MASK_BITN 4
+#define AON_BATMON_EVENTMASK_BATT_UPDATE_MASK_M 0x00000010
+#define AON_BATMON_EVENTMASK_BATT_UPDATE_MASK_S 4
+
+// Field: [3] TEMP_BELOW_LL_MASK
+//
+// 1: EVENT.TEMP_BELOW_LL contributes to combined event from BATMON
+// 0: EVENT.TEMP_BELOW_LL does not contribute to combined event from BATMON
+#define AON_BATMON_EVENTMASK_TEMP_BELOW_LL_MASK 0x00000008
+#define AON_BATMON_EVENTMASK_TEMP_BELOW_LL_MASK_BITN 3
+#define AON_BATMON_EVENTMASK_TEMP_BELOW_LL_MASK_M 0x00000008
+#define AON_BATMON_EVENTMASK_TEMP_BELOW_LL_MASK_S 3
+
+// Field: [2] TEMP_OVER_UL_MASK
+//
+// 1: EVENT.TEMP_OVER_UL contributes to combined event from BATMON
+// 0: EVENT.TEMP_OVER_UL does not contribute to combined event from BATMON
+#define AON_BATMON_EVENTMASK_TEMP_OVER_UL_MASK 0x00000004
+#define AON_BATMON_EVENTMASK_TEMP_OVER_UL_MASK_BITN 2
+#define AON_BATMON_EVENTMASK_TEMP_OVER_UL_MASK_M 0x00000004
+#define AON_BATMON_EVENTMASK_TEMP_OVER_UL_MASK_S 2
+
+// Field: [1] BATT_BELOW_LL_MASK
+//
+// 1: EVENT.BATT_BELOW_LL contributes to combined event from BATMON
+// 0: EVENT.BATT_BELOW_LL does not contribute to combined event from BATMON
+#define AON_BATMON_EVENTMASK_BATT_BELOW_LL_MASK 0x00000002
+#define AON_BATMON_EVENTMASK_BATT_BELOW_LL_MASK_BITN 1
+#define AON_BATMON_EVENTMASK_BATT_BELOW_LL_MASK_M 0x00000002
+#define AON_BATMON_EVENTMASK_BATT_BELOW_LL_MASK_S 1
+
+// Field: [0] BATT_OVER_UL_MASK
+//
+// 1: EVENT.BATT_OVER_UL contributes to combined event from BATMON
+// 0: EVENT.BATT_OVER_UL does not contribute to combined event from BATMON
+#define AON_BATMON_EVENTMASK_BATT_OVER_UL_MASK 0x00000001
+#define AON_BATMON_EVENTMASK_BATT_OVER_UL_MASK_BITN 0
+#define AON_BATMON_EVENTMASK_BATT_OVER_UL_MASK_M 0x00000001
+#define AON_BATMON_EVENTMASK_BATT_OVER_UL_MASK_S 0
+
+//*****************************************************************************
+//
+// Register: AON_BATMON_O_EVENT
+//
+//*****************************************************************************
+// Field: [5] TEMP_UPDATE
+//
+// Alias to TEMPUPD.STAT
+#define AON_BATMON_EVENT_TEMP_UPDATE 0x00000020
+#define AON_BATMON_EVENT_TEMP_UPDATE_BITN 5
+#define AON_BATMON_EVENT_TEMP_UPDATE_M 0x00000020
+#define AON_BATMON_EVENT_TEMP_UPDATE_S 5
+
+// Field: [4] BATT_UPDATE
+//
+// Alias to BATUPD.STAT
+#define AON_BATMON_EVENT_BATT_UPDATE 0x00000010
+#define AON_BATMON_EVENT_BATT_UPDATE_BITN 4
+#define AON_BATMON_EVENT_BATT_UPDATE_M 0x00000010
+#define AON_BATMON_EVENT_BATT_UPDATE_S 4
+
+// Field: [3] TEMP_BELOW_LL
+//
+// Read:
+// 1: Temperature level is below the lower limit set by TEMPLL.
+// 0: Temperature level is not below the lower limit set by TEMPLL.
+// Write:
+// 1: Clears the flag
+// 0: No change in the flag
+#define AON_BATMON_EVENT_TEMP_BELOW_LL 0x00000008
+#define AON_BATMON_EVENT_TEMP_BELOW_LL_BITN 3
+#define AON_BATMON_EVENT_TEMP_BELOW_LL_M 0x00000008
+#define AON_BATMON_EVENT_TEMP_BELOW_LL_S 3
+
+// Field: [2] TEMP_OVER_UL
+//
+// Read:
+// 1: Temperature level is above the upper limit set by TEMPUL.
+// 0: Temperature level is not above the upper limit set by TEMPUL.
+// Write:
+// 1: Clears the flag
+// 0: No change in the flag
+#define AON_BATMON_EVENT_TEMP_OVER_UL 0x00000004
+#define AON_BATMON_EVENT_TEMP_OVER_UL_BITN 2
+#define AON_BATMON_EVENT_TEMP_OVER_UL_M 0x00000004
+#define AON_BATMON_EVENT_TEMP_OVER_UL_S 2
+
+// Field: [1] BATT_BELOW_LL
+//
+// Read:
+// 1: Battery level is below the lower limit set by BATTLL.
+// 0: Battery level is not below the lower limit set by BATTLL.
+// Write:
+// 1: Clears the flag
+// 0: No change in the flag
+#define AON_BATMON_EVENT_BATT_BELOW_LL 0x00000002
+#define AON_BATMON_EVENT_BATT_BELOW_LL_BITN 1
+#define AON_BATMON_EVENT_BATT_BELOW_LL_M 0x00000002
+#define AON_BATMON_EVENT_BATT_BELOW_LL_S 1
+
+// Field: [0] BATT_OVER_UL
+//
+// Read:
+// 1: Battery level is above the upper limit set by BATTUL.
+// 0: Battery level is not above the upper limit set by BATTUL.
+// Write:
+// 1: Clears the flag
+// 0: No change in the flag
+#define AON_BATMON_EVENT_BATT_OVER_UL 0x00000001
+#define AON_BATMON_EVENT_BATT_OVER_UL_BITN 0
+#define AON_BATMON_EVENT_BATT_OVER_UL_M 0x00000001
+#define AON_BATMON_EVENT_BATT_OVER_UL_S 0
+
+//*****************************************************************************
+//
+// Register: AON_BATMON_O_BATTUL
+//
+//*****************************************************************************
+// Field: [10:8] INT
+//
+// Integer part:
+//
+// 0x0: 0V + fractional part
+// ...
+// 0x3: 3V + fractional part
+// 0x4: 4V + fractional part
+#define AON_BATMON_BATTUL_INT_W 3
+#define AON_BATMON_BATTUL_INT_M 0x00000700
+#define AON_BATMON_BATTUL_INT_S 8
+
+// Field: [7:0] FRAC
+//
+// Fractional part, standard binary fractional encoding.
+//
+// 0x00: .0V
+// ...
+// 0x20: 1/8 = .125V
+// 0x40: 1/4 = .25V
+// 0x80: 1/2 = .5V
+// ...
+// 0xA0: 1/2 + 1/8 = .625V
+// ...
+// 0xFF: Max
+#define AON_BATMON_BATTUL_FRAC_W 8
+#define AON_BATMON_BATTUL_FRAC_M 0x000000FF
+#define AON_BATMON_BATTUL_FRAC_S 0
+
+//*****************************************************************************
+//
+// Register: AON_BATMON_O_BATTLL
+//
+//*****************************************************************************
+// Field: [10:8] INT
+//
+// Integer part:
+//
+// 0x0: 0V + fractional part
+// ...
+// 0x3: 3V + fractional part
+// 0x4: 4V + fractional part
+#define AON_BATMON_BATTLL_INT_W 3
+#define AON_BATMON_BATTLL_INT_M 0x00000700
+#define AON_BATMON_BATTLL_INT_S 8
+
+// Field: [7:0] FRAC
+//
+// Fractional part, standard binary fractional encoding.
+//
+// 0x00: .0V
+// ...
+// 0x20: 1/8 = .125V
+// 0x40: 1/4 = .25V
+// 0x80: 1/2 = .5V
+// ...
+// 0xA0: 1/2 + 1/8 = .625V
+// ...
+// 0xFF: Max
+#define AON_BATMON_BATTLL_FRAC_W 8
+#define AON_BATMON_BATTLL_FRAC_M 0x000000FF
+#define AON_BATMON_BATTLL_FRAC_S 0
+
+//*****************************************************************************
+//
+// Register: AON_BATMON_O_TEMPUL
+//
+//*****************************************************************************
+// Field: [16:8] INT
+//
+// Integer part (signed) of temperature upper limit.
+// Total value = INTEGER + FRACTIONAL
+// 2's complement encoding
+//
+// 0x100: Min value
+// 0x1D8: -40C
+// 0x1FF: -1C
+// 0x00: 0C
+// 0x1B: 27C
+// 0x55: 85C
+// 0xFF: Max value
+#define AON_BATMON_TEMPUL_INT_W 9
+#define AON_BATMON_TEMPUL_INT_M 0x0001FF00
+#define AON_BATMON_TEMPUL_INT_S 8
+
+// Field: [7:6] FRAC
+//
+// Fractional part of temperature upper limit.
+// Total value = INTEGER + FRACTIONAL
+// The encoding is an extension of the 2's complement encoding.
+//
+// 00: 0.0C
+// 01: 0.25C
+// 10: 0.5C
+// 11: 0.75C
+//
+// For example:
+// 000000001,00 = ( 1+0,00) = 1,00
+// 000000000,11 = ( 0+0,75) = 0,75
+// 000000000,10 = ( 0+0,50) = 0,50
+// 000000000,01 = ( 0+0,25) = 0,25
+// 000000000,00 = ( 0+0,00) = 0,00
+// 111111111,11 = (-1+0,75) = -0,25
+// 111111111,10 = (-1+0,50) = -0,50
+// 111111111,01 = (-1+0,25) = -0,75
+// 111111111,00 = (-1+0,00) = -1,00
+// 111111110,11 = (-2+0,75) = -1,25
+#define AON_BATMON_TEMPUL_FRAC_W 2
+#define AON_BATMON_TEMPUL_FRAC_M 0x000000C0
+#define AON_BATMON_TEMPUL_FRAC_S 6
+
+//*****************************************************************************
+//
+// Register: AON_BATMON_O_TEMPLL
+//
+//*****************************************************************************
+// Field: [16:8] INT
+//
+// Integer part (signed) of temperature lower limit.
+// Total value = INTEGER + FRACTIONAL
+// 2's complement encoding
+//
+// 0x100: Min value
+// 0x1D8: -40C
+// 0x1FF: -1C
+// 0x00: 0C
+// 0x1B: 27C
+// 0x55: 85C
+// 0xFF: Max value
+#define AON_BATMON_TEMPLL_INT_W 9
+#define AON_BATMON_TEMPLL_INT_M 0x0001FF00
+#define AON_BATMON_TEMPLL_INT_S 8
+
+// Field: [7:6] FRAC
+//
+// Fractional part of temperature lower limit.
+// Total value = INTEGER + FRACTIONAL
+// The encoding is an extension of the 2's complement encoding.
+//
+// 00: 0.0C
+// 01: 0.25C
+// 10: 0.5C
+// 11: 0.75C
+//
+// For example:
+// 000000001,00 = ( 1+0,00) = 1,00
+// 000000000,11 = ( 0+0,75) = 0,75
+// 000000000,10 = ( 0+0,50) = 0,50
+// 000000000,01 = ( 0+0,25) = 0,25
+// 000000000,00 = ( 0+0,00) = 0,00
+// 111111111,11 = (-1+0,75) = -0,25
+// 111111111,10 = (-1+0,50) = -0,50
+// 111111111,01 = (-1+0,25) = -0,75
+// 111111111,00 = (-1+0,00) = -1,00
+// 111111110,11 = (-2+0,75) = -1,25
+#define AON_BATMON_TEMPLL_FRAC_W 2
+#define AON_BATMON_TEMPLL_FRAC_M 0x000000C0
+#define AON_BATMON_TEMPLL_FRAC_S 6
+
+
+#endif // __AON_BATMON__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_event.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_event.h
new file mode 100644
index 0000000..81c93f3
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_event.h
@@ -0,0 +1,1135 @@
+/******************************************************************************
+* Filename: hw_aon_event_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_AON_EVENT_H__
+#define __HW_AON_EVENT_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// AON_EVENT component
+//
+//*****************************************************************************
+// Wake-up Selector For MCU
+#define AON_EVENT_O_MCUWUSEL 0x00000000
+
+// Wake-up Selector For MCU
+#define AON_EVENT_O_MCUWUSEL1 0x00000004
+
+// Event Selector For MCU Event Fabric
+#define AON_EVENT_O_EVTOMCUSEL 0x00000008
+
+// RTC Capture Event Selector For AON_RTC
+#define AON_EVENT_O_RTCSEL 0x0000000C
+
+//*****************************************************************************
+//
+// Register: AON_EVENT_O_MCUWUSEL
+//
+//*****************************************************************************
+// Field: [29:24] WU3_EV
+//
+// MCU Wakeup Source #3
+//
+// AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up
+// the MCU domain from Power Off or Power Down.
+// Note:
+// ENUMs:
+// NONE No event, always low
+// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal
+// directly from AUX Comparator B (inverted) as
+// opposed to AUX_COMPB which is synchronized in
+// AUX
+// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal
+// directly from the AUX Comparator B as opposed
+// to AUX_COMPB which is synchronized in AUX
+// BATMON_VOLT BATMON voltage update event
+// BATMON_TEMP BATMON temperature update event
+// AUX_TIMER1_EV AUX Timer 1 Event
+// AUX_TIMER0_EV AUX Timer 0 Event
+// AUX_TDC_DONE TDC completed or timed out
+// AUX_ADC_DONE ADC conversion completed
+// AUX_COMPB Comparator B triggered
+// AUX_COMPA Comparator A triggered
+// AUX_SWEV2 AUX Software triggered event #2. Triggered by
+// AUX_EVCTL:SWEVSET.SWEV2
+// AUX_SWEV1 AUX Software triggered event #1. Triggered by
+// AUX_EVCTL:SWEVSET.SWEV1
+// AUX_SWEV0 AUX Software triggered event #0. Triggered by
+// AUX_EVCTL:SWEVSET.SWEV0
+// JTAG JTAG generated event
+// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line
+// toggles value every 32 kHz clock period)
+// RTC_COMB_DLY RTC combined delayed event
+// RTC_CH2_DLY RTC channel 2 - delayed event
+// RTC_CH1_DLY RTC channel 1 - delayed event
+// RTC_CH0_DLY RTC channel 0 - delayed event
+// RTC_CH2 RTC channel 2 event
+// RTC_CH1 RTC channel 1 event
+// RTC_CH0 RTC channel 0 event
+// PAD Edge detect on any PAD
+// BATMON_COMBINED Combined event from BATMON
+// BATMON_TEMP_LL BATMON event: Temperature level below lower limit
+// BATMON_TEMP_UL BATMON event: Temperature level above upper limit
+// BATMON_BATT_LL BATMON event: Battery level below lower limit
+// BATMON_BATT_UL BATMON event: Battery level above upper limit
+// AUX_TIMER2_EV3 Event 3 from AUX TImer2
+// AUX_TIMER2_EV2 Event 2 from AUX TImer2
+// AUX_TIMER2_EV1 Event 1 from AUX TImer2
+// AUX_TIMER2_EV0 Event 0 from AUX TImer2
+// IOEV_MCU_WU Edge detect IO event from the DIO(s) which have
+// enabled contribution to IOEV_MCU_WU in
+// [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN]
+#define AON_EVENT_MCUWUSEL_WU3_EV_W 6
+#define AON_EVENT_MCUWUSEL_WU3_EV_M 0x3F000000
+#define AON_EVENT_MCUWUSEL_WU3_EV_S 24
+#define AON_EVENT_MCUWUSEL_WU3_EV_NONE 0x3F000000
+#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB_ASYNC_N 0x38000000
+#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB_ASYNC 0x37000000
+#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_VOLT 0x36000000
+#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_TEMP 0x35000000
+#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER1_EV 0x34000000
+#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER0_EV 0x33000000
+#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TDC_DONE 0x32000000
+#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_ADC_DONE 0x31000000
+#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB 0x30000000
+#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPA 0x2F000000
+#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV2 0x2E000000
+#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV1 0x2D000000
+#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV0 0x2C000000
+#define AON_EVENT_MCUWUSEL_WU3_EV_JTAG 0x2B000000
+#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_UPD 0x2A000000
+#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_COMB_DLY 0x29000000
+#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH2_DLY 0x28000000
+#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH1_DLY 0x27000000
+#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH0_DLY 0x26000000
+#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH2 0x25000000
+#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH1 0x24000000
+#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH0 0x23000000
+#define AON_EVENT_MCUWUSEL_WU3_EV_PAD 0x20000000
+#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_COMBINED 0x09000000
+#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_TEMP_LL 0x08000000
+#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_TEMP_UL 0x07000000
+#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_BATT_LL 0x06000000
+#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_BATT_UL 0x05000000
+#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER2_EV3 0x04000000
+#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER2_EV2 0x03000000
+#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER2_EV1 0x02000000
+#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER2_EV0 0x01000000
+#define AON_EVENT_MCUWUSEL_WU3_EV_IOEV_MCU_WU 0x00000000
+
+// Field: [21:16] WU2_EV
+//
+// MCU Wakeup Source #2
+//
+// AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up
+// the MCU domain from Power Off or Power Down.
+// Note:
+// ENUMs:
+// NONE No event, always low
+// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal
+// directly from AUX Comparator B (inverted) as
+// opposed to AUX_COMPB which is synchronized in
+// AUX
+// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal
+// directly from the AUX Comparator B as opposed
+// to AUX_COMPB which is synchronized in AUX
+// BATMON_VOLT BATMON voltage update event
+// BATMON_TEMP BATMON temperature update event
+// AUX_TIMER1_EV AUX Timer 1 Event
+// AUX_TIMER0_EV AUX Timer 0 Event
+// AUX_TDC_DONE TDC completed or timed out
+// AUX_ADC_DONE ADC conversion completed
+// AUX_COMPB Comparator B triggered
+// AUX_COMPA Comparator A triggered
+// AUX_SWEV2 AUX Software triggered event #2. Triggered by
+// AUX_EVCTL:SWEVSET.SWEV2
+// AUX_SWEV1 AUX Software triggered event #1. Triggered by
+// AUX_EVCTL:SWEVSET.SWEV1
+// AUX_SWEV0 AUX Software triggered event #0. Triggered by
+// AUX_EVCTL:SWEVSET.SWEV0
+// JTAG JTAG generated event
+// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line
+// toggles value every 32 kHz clock period)
+// RTC_COMB_DLY RTC combined delayed event
+// RTC_CH2_DLY RTC channel 2 - delayed event
+// RTC_CH1_DLY RTC channel 1 - delayed event
+// RTC_CH0_DLY RTC channel 0 - delayed event
+// RTC_CH2 RTC channel 2 event
+// RTC_CH1 RTC channel 1 event
+// RTC_CH0 RTC channel 0 event
+// PAD Edge detect on any PAD
+// BATMON_COMBINED Combined event from BATMON
+// BATMON_TEMP_LL BATMON event: Temperature level below lower limit
+// BATMON_TEMP_UL BATMON event: Temperature level above upper limit
+// BATMON_BATT_LL BATMON event: Battery level below lower limit
+// BATMON_BATT_UL BATMON event: Battery level above upper limit
+// AUX_TIMER2_EV3 Event 3 from AUX TImer2
+// AUX_TIMER2_EV2 Event 2 from AUX TImer2
+// AUX_TIMER2_EV1 Event 1 from AUX TImer2
+// AUX_TIMER2_EV0 Event 0 from AUX TImer2
+// IOEV_MCU_WU Edge detect IO event from the DIO(s) which have
+// enabled contribution to IOEV_MCU_WU in
+// [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN]
+#define AON_EVENT_MCUWUSEL_WU2_EV_W 6
+#define AON_EVENT_MCUWUSEL_WU2_EV_M 0x003F0000
+#define AON_EVENT_MCUWUSEL_WU2_EV_S 16
+#define AON_EVENT_MCUWUSEL_WU2_EV_NONE 0x003F0000
+#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB_ASYNC_N 0x00380000
+#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB_ASYNC 0x00370000
+#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_VOLT 0x00360000
+#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_TEMP 0x00350000
+#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER1_EV 0x00340000
+#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER0_EV 0x00330000
+#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TDC_DONE 0x00320000
+#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_ADC_DONE 0x00310000
+#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB 0x00300000
+#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPA 0x002F0000
+#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV2 0x002E0000
+#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV1 0x002D0000
+#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV0 0x002C0000
+#define AON_EVENT_MCUWUSEL_WU2_EV_JTAG 0x002B0000
+#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_UPD 0x002A0000
+#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_COMB_DLY 0x00290000
+#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH2_DLY 0x00280000
+#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH1_DLY 0x00270000
+#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH0_DLY 0x00260000
+#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH2 0x00250000
+#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH1 0x00240000
+#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH0 0x00230000
+#define AON_EVENT_MCUWUSEL_WU2_EV_PAD 0x00200000
+#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_COMBINED 0x00090000
+#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_TEMP_LL 0x00080000
+#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_TEMP_UL 0x00070000
+#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_BATT_LL 0x00060000
+#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_BATT_UL 0x00050000
+#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER2_EV3 0x00040000
+#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER2_EV2 0x00030000
+#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER2_EV1 0x00020000
+#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER2_EV0 0x00010000
+#define AON_EVENT_MCUWUSEL_WU2_EV_IOEV_MCU_WU 0x00000000
+
+// Field: [13:8] WU1_EV
+//
+// MCU Wakeup Source #1
+//
+// AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up
+// the MCU domain from Power Off or Power Down.
+// Note:
+// ENUMs:
+// NONE No event, always low
+// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal
+// directly from AUX Comparator B (inverted) as
+// opposed to AUX_COMPB which is synchronized in
+// AUX
+// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal
+// directly from the AUX Comparator B as opposed
+// to AUX_COMPB which is synchronized in AUX
+// BATMON_VOLT BATMON voltage update event
+// BATMON_TEMP BATMON temperature update event
+// AUX_TIMER1_EV AUX Timer 1 Event
+// AUX_TIMER0_EV AUX Timer 0 Event
+// AUX_TDC_DONE TDC completed or timed out
+// AUX_ADC_DONE ADC conversion completed
+// AUX_COMPB Comparator B triggered
+// AUX_COMPA Comparator A triggered
+// AUX_SWEV2 AUX Software triggered event #2. Triggered by
+// AUX_EVCTL:SWEVSET.SWEV2
+// AUX_SWEV1 AUX Software triggered event #1. Triggered by
+// AUX_EVCTL:SWEVSET.SWEV1
+// AUX_SWEV0 AUX Software triggered event #0. Triggered by
+// AUX_EVCTL:SWEVSET.SWEV0
+// JTAG JTAG generated event
+// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line
+// toggles value every 32 kHz clock period)
+// RTC_COMB_DLY RTC combined delayed event
+// RTC_CH2_DLY RTC channel 2 - delayed event
+// RTC_CH1_DLY RTC channel 1 - delayed event
+// RTC_CH0_DLY RTC channel 0 - delayed event
+// RTC_CH2 RTC channel 2 event
+// RTC_CH1 RTC channel 1 event
+// RTC_CH0 RTC channel 0 event
+// PAD Edge detect on any PAD
+// BATMON_COMBINED Combined event from BATMON
+// BATMON_TEMP_LL BATMON event: Temperature level below lower limit
+// BATMON_TEMP_UL BATMON event: Temperature level above upper limit
+// BATMON_BATT_LL BATMON event: Battery level below lower limit
+// BATMON_BATT_UL BATMON event: Battery level above upper limit
+// AUX_TIMER2_EV3 Event 3 from AUX TImer2
+// AUX_TIMER2_EV2 Event 2 from AUX TImer2
+// AUX_TIMER2_EV1 Event 1 from AUX TImer2
+// AUX_TIMER2_EV0 Event 0 from AUX TImer2
+// IOEV_MCU_WU Edge detect IO event from the DIO(s) which have
+// enabled contribution to IOEV_MCU_WU in
+// [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN]
+#define AON_EVENT_MCUWUSEL_WU1_EV_W 6
+#define AON_EVENT_MCUWUSEL_WU1_EV_M 0x00003F00
+#define AON_EVENT_MCUWUSEL_WU1_EV_S 8
+#define AON_EVENT_MCUWUSEL_WU1_EV_NONE 0x00003F00
+#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB_ASYNC_N 0x00003800
+#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB_ASYNC 0x00003700
+#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_VOLT 0x00003600
+#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_TEMP 0x00003500
+#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER1_EV 0x00003400
+#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER0_EV 0x00003300
+#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TDC_DONE 0x00003200
+#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_ADC_DONE 0x00003100
+#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB 0x00003000
+#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPA 0x00002F00
+#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV2 0x00002E00
+#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV1 0x00002D00
+#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV0 0x00002C00
+#define AON_EVENT_MCUWUSEL_WU1_EV_JTAG 0x00002B00
+#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_UPD 0x00002A00
+#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_COMB_DLY 0x00002900
+#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH2_DLY 0x00002800
+#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH1_DLY 0x00002700
+#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH0_DLY 0x00002600
+#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH2 0x00002500
+#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH1 0x00002400
+#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH0 0x00002300
+#define AON_EVENT_MCUWUSEL_WU1_EV_PAD 0x00002000
+#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_COMBINED 0x00000900
+#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_TEMP_LL 0x00000800
+#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_TEMP_UL 0x00000700
+#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_BATT_LL 0x00000600
+#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_BATT_UL 0x00000500
+#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER2_EV3 0x00000400
+#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER2_EV2 0x00000300
+#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER2_EV1 0x00000200
+#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER2_EV0 0x00000100
+#define AON_EVENT_MCUWUSEL_WU1_EV_IOEV_MCU_WU 0x00000000
+
+// Field: [5:0] WU0_EV
+//
+// MCU Wakeup Source #0
+//
+// AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up
+// the MCU domain from Power Off or Power Down.
+// Note:
+// ENUMs:
+// NONE No event, always low
+// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal
+// directly from AUX Comparator B (inverted) as
+// opposed to AUX_COMPB which is synchronized in
+// AUX
+// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal
+// directly from the AUX Comparator B as opposed
+// to AUX_COMPB which is synchronized in AUX
+// BATMON_VOLT BATMON voltage update event
+// BATMON_TEMP BATMON temperature update event
+// AUX_TIMER1_EV AUX Timer 1 Event
+// AUX_TIMER0_EV AUX Timer 0 Event
+// AUX_TDC_DONE TDC completed or timed out
+// AUX_ADC_DONE ADC conversion completed
+// AUX_COMPB Comparator B triggered
+// AUX_COMPA Comparator A triggered
+// AUX_SWEV2 AUX Software triggered event #2. Triggered by
+// AUX_EVCTL:SWEVSET.SWEV2
+// AUX_SWEV1 AUX Software triggered event #1. Triggered by
+// AUX_EVCTL:SWEVSET.SWEV1
+// AUX_SWEV0 AUX Software triggered event #0. Triggered by
+// AUX_EVCTL:SWEVSET.SWEV0
+// JTAG JTAG generated event
+// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line
+// toggles value every 32 kHz clock period)
+// RTC_COMB_DLY RTC combined delayed event
+// RTC_CH2_DLY RTC channel 2 - delayed event
+// RTC_CH1_DLY RTC channel 1 - delayed event
+// RTC_CH0_DLY RTC channel 0 - delayed event
+// RTC_CH2 RTC channel 2 event
+// RTC_CH1 RTC channel 1 event
+// RTC_CH0 RTC channel 0 event
+// PAD Edge detect on any PAD
+// BATMON_COMBINED Combined event from BATMON
+// BATMON_TEMP_LL BATMON event: Temperature level below lower limit
+// BATMON_TEMP_UL BATMON event: Temperature level above upper limit
+// BATMON_BATT_LL BATMON event: Battery level below lower limit
+// BATMON_BATT_UL BATMON event: Battery level above upper limit
+// AUX_TIMER2_EV3 Event 3 from AUX TImer2
+// AUX_TIMER2_EV2 Event 2 from AUX TImer2
+// AUX_TIMER2_EV1 Event 1 from AUX TImer2
+// AUX_TIMER2_EV0 Event 0 from AUX TImer2
+// IOEV_MCU_WU Edge detect IO event from the DIO(s) which have
+// enabled contribution to IOEV_MCU_WU in
+// [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN]
+#define AON_EVENT_MCUWUSEL_WU0_EV_W 6
+#define AON_EVENT_MCUWUSEL_WU0_EV_M 0x0000003F
+#define AON_EVENT_MCUWUSEL_WU0_EV_S 0
+#define AON_EVENT_MCUWUSEL_WU0_EV_NONE 0x0000003F
+#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB_ASYNC_N 0x00000038
+#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB_ASYNC 0x00000037
+#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_VOLT 0x00000036
+#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_TEMP 0x00000035
+#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER1_EV 0x00000034
+#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER0_EV 0x00000033
+#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TDC_DONE 0x00000032
+#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_ADC_DONE 0x00000031
+#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB 0x00000030
+#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPA 0x0000002F
+#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV2 0x0000002E
+#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV1 0x0000002D
+#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV0 0x0000002C
+#define AON_EVENT_MCUWUSEL_WU0_EV_JTAG 0x0000002B
+#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_UPD 0x0000002A
+#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_COMB_DLY 0x00000029
+#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH2_DLY 0x00000028
+#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH1_DLY 0x00000027
+#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH0_DLY 0x00000026
+#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH2 0x00000025
+#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH1 0x00000024
+#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH0 0x00000023
+#define AON_EVENT_MCUWUSEL_WU0_EV_PAD 0x00000020
+#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_COMBINED 0x00000009
+#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_TEMP_LL 0x00000008
+#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_TEMP_UL 0x00000007
+#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_BATT_LL 0x00000006
+#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_BATT_UL 0x00000005
+#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER2_EV3 0x00000004
+#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER2_EV2 0x00000003
+#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER2_EV1 0x00000002
+#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER2_EV0 0x00000001
+#define AON_EVENT_MCUWUSEL_WU0_EV_IOEV_MCU_WU 0x00000000
+
+//*****************************************************************************
+//
+// Register: AON_EVENT_O_MCUWUSEL1
+//
+//*****************************************************************************
+// Field: [29:24] WU7_EV
+//
+// MCU Wakeup Source #7
+//
+// AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up
+// the MCU domain from Power Off or Power Down.
+// Note:
+// ENUMs:
+// NONE No event, always low
+// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal
+// directly from AUX Comparator B (inverted) as
+// opposed to AUX_COMPB which is synchronized in
+// AUX
+// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal
+// directly from the AUX Comparator B as opposed
+// to AUX_COMPB which is synchronized in AUX
+// BATMON_VOLT BATMON voltage update event
+// BATMON_TEMP BATMON temperature update event
+// AUX_TIMER1_EV AUX Timer 1 Event
+// AUX_TIMER0_EV AUX Timer 0 Event
+// AUX_TDC_DONE TDC completed or timed out
+// AUX_ADC_DONE ADC conversion completed
+// AUX_COMPB Comparator B triggered
+// AUX_COMPA Comparator A triggered
+// AUX_SWEV2 AUX Software triggered event #2. Triggered by
+// AUX_EVCTL:SWEVSET.SWEV2
+// AUX_SWEV1 AUX Software triggered event #1. Triggered by
+// AUX_EVCTL:SWEVSET.SWEV1
+// AUX_SWEV0 AUX Software triggered event #0. Triggered by
+// AUX_EVCTL:SWEVSET.SWEV0
+// JTAG JTAG generated event
+// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line
+// toggles value every 32 kHz clock period)
+// RTC_COMB_DLY RTC combined delayed event
+// RTC_CH2_DLY RTC channel 2 - delayed event
+// RTC_CH1_DLY RTC channel 1 - delayed event
+// RTC_CH0_DLY RTC channel 0 - delayed event
+// RTC_CH2 RTC channel 2 event
+// RTC_CH1 RTC channel 1 event
+// RTC_CH0 RTC channel 0 event
+// PAD Edge detect on any PAD
+// BATMON_COMBINED Combined event from BATMON
+// BATMON_TEMP_LL BATMON event: Temperature level below lower limit
+// BATMON_TEMP_UL BATMON event: Temperature level above upper limit
+// BATMON_BATT_LL BATMON event: Battery level below lower limit
+// BATMON_BATT_UL BATMON event: Battery level above upper limit
+// AUX_TIMER2_EV3 Event 3 from AUX TImer2
+// AUX_TIMER2_EV2 Event 2 from AUX TImer2
+// AUX_TIMER2_EV1 Event 1 from AUX TImer2
+// AUX_TIMER2_EV0 Event 0 from AUX TImer2
+// IOEV_MCU_WU Edge detect IO event from the DIO(s) which have
+// enabled contribution to IOEV_MCU_WU in
+// [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN]
+#define AON_EVENT_MCUWUSEL1_WU7_EV_W 6
+#define AON_EVENT_MCUWUSEL1_WU7_EV_M 0x3F000000
+#define AON_EVENT_MCUWUSEL1_WU7_EV_S 24
+#define AON_EVENT_MCUWUSEL1_WU7_EV_NONE 0x3F000000
+#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_COMPB_ASYNC_N 0x38000000
+#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_COMPB_ASYNC 0x37000000
+#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_VOLT 0x36000000
+#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_TEMP 0x35000000
+#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TIMER1_EV 0x34000000
+#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TIMER0_EV 0x33000000
+#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TDC_DONE 0x32000000
+#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_ADC_DONE 0x31000000
+#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_COMPB 0x30000000
+#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_COMPA 0x2F000000
+#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_SWEV2 0x2E000000
+#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_SWEV1 0x2D000000
+#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_SWEV0 0x2C000000
+#define AON_EVENT_MCUWUSEL1_WU7_EV_JTAG 0x2B000000
+#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_UPD 0x2A000000
+#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_COMB_DLY 0x29000000
+#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_CH2_DLY 0x28000000
+#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_CH1_DLY 0x27000000
+#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_CH0_DLY 0x26000000
+#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_CH2 0x25000000
+#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_CH1 0x24000000
+#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_CH0 0x23000000
+#define AON_EVENT_MCUWUSEL1_WU7_EV_PAD 0x20000000
+#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_COMBINED 0x09000000
+#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_TEMP_LL 0x08000000
+#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_TEMP_UL 0x07000000
+#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_BATT_LL 0x06000000
+#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_BATT_UL 0x05000000
+#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TIMER2_EV3 0x04000000
+#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TIMER2_EV2 0x03000000
+#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TIMER2_EV1 0x02000000
+#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TIMER2_EV0 0x01000000
+#define AON_EVENT_MCUWUSEL1_WU7_EV_IOEV_MCU_WU 0x00000000
+
+// Field: [21:16] WU6_EV
+//
+// MCU Wakeup Source #6
+//
+// AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up
+// the MCU domain from Power Off or Power Down.
+// Note:
+// ENUMs:
+// NONE No event, always low
+// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal
+// directly from AUX Comparator B (inverted) as
+// opposed to AUX_COMPB which is synchronized in
+// AUX
+// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal
+// directly from the AUX Comparator B as opposed
+// to AUX_COMPB which is synchronized in AUX
+// BATMON_VOLT BATMON voltage update event
+// BATMON_TEMP BATMON temperature update event
+// AUX_TIMER1_EV AUX Timer 1 Event
+// AUX_TIMER0_EV AUX Timer 0 Event
+// AUX_TDC_DONE TDC completed or timed out
+// AUX_ADC_DONE ADC conversion completed
+// AUX_COMPB Comparator B triggered
+// AUX_COMPA Comparator A triggered
+// AUX_SWEV2 AUX Software triggered event #2. Triggered by
+// AUX_EVCTL:SWEVSET.SWEV2
+// AUX_SWEV1 AUX Software triggered event #1. Triggered by
+// AUX_EVCTL:SWEVSET.SWEV1
+// AUX_SWEV0 AUX Software triggered event #0. Triggered by
+// AUX_EVCTL:SWEVSET.SWEV0
+// JTAG JTAG generated event
+// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line
+// toggles value every 32 kHz clock period)
+// RTC_COMB_DLY RTC combined delayed event
+// RTC_CH2_DLY RTC channel 2 - delayed event
+// RTC_CH1_DLY RTC channel 1 - delayed event
+// RTC_CH0_DLY RTC channel 0 - delayed event
+// RTC_CH2 RTC channel 2 event
+// RTC_CH1 RTC channel 1 event
+// RTC_CH0 RTC channel 0 event
+// PAD Edge detect on any PAD
+// BATMON_COMBINED Combined event from BATMON
+// BATMON_TEMP_LL BATMON event: Temperature level below lower limit
+// BATMON_TEMP_UL BATMON event: Temperature level above upper limit
+// BATMON_BATT_LL BATMON event: Battery level below lower limit
+// BATMON_BATT_UL BATMON event: Battery level above upper limit
+// AUX_TIMER2_EV3 Event 3 from AUX TImer2
+// AUX_TIMER2_EV2 Event 2 from AUX TImer2
+// AUX_TIMER2_EV1 Event 1 from AUX TImer2
+// AUX_TIMER2_EV0 Event 0 from AUX TImer2
+// IOEV_MCU_WU Edge detect IO event from the DIO(s) which have
+// enabled contribution to IOEV_MCU_WU in
+// [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN]
+#define AON_EVENT_MCUWUSEL1_WU6_EV_W 6
+#define AON_EVENT_MCUWUSEL1_WU6_EV_M 0x003F0000
+#define AON_EVENT_MCUWUSEL1_WU6_EV_S 16
+#define AON_EVENT_MCUWUSEL1_WU6_EV_NONE 0x003F0000
+#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_COMPB_ASYNC_N 0x00380000
+#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_COMPB_ASYNC 0x00370000
+#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_VOLT 0x00360000
+#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_TEMP 0x00350000
+#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TIMER1_EV 0x00340000
+#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TIMER0_EV 0x00330000
+#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TDC_DONE 0x00320000
+#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_ADC_DONE 0x00310000
+#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_COMPB 0x00300000
+#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_COMPA 0x002F0000
+#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_SWEV2 0x002E0000
+#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_SWEV1 0x002D0000
+#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_SWEV0 0x002C0000
+#define AON_EVENT_MCUWUSEL1_WU6_EV_JTAG 0x002B0000
+#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_UPD 0x002A0000
+#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_COMB_DLY 0x00290000
+#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_CH2_DLY 0x00280000
+#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_CH1_DLY 0x00270000
+#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_CH0_DLY 0x00260000
+#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_CH2 0x00250000
+#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_CH1 0x00240000
+#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_CH0 0x00230000
+#define AON_EVENT_MCUWUSEL1_WU6_EV_PAD 0x00200000
+#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_COMBINED 0x00090000
+#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_TEMP_LL 0x00080000
+#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_TEMP_UL 0x00070000
+#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_BATT_LL 0x00060000
+#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_BATT_UL 0x00050000
+#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TIMER2_EV3 0x00040000
+#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TIMER2_EV2 0x00030000
+#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TIMER2_EV1 0x00020000
+#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TIMER2_EV0 0x00010000
+#define AON_EVENT_MCUWUSEL1_WU6_EV_IOEV_MCU_WU 0x00000000
+
+// Field: [13:8] WU5_EV
+//
+// MCU Wakeup Source #5
+//
+// AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up
+// the MCU domain from Power Off or Power Down.
+// Note:
+// ENUMs:
+// NONE No event, always low
+// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal
+// directly from AUX Comparator B (inverted) as
+// opposed to AUX_COMPB which is synchronized in
+// AUX
+// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal
+// directly from the AUX Comparator B as opposed
+// to AUX_COMPB which is synchronized in AUX
+// BATMON_VOLT BATMON voltage update event
+// BATMON_TEMP BATMON temperature update event
+// AUX_TIMER1_EV AUX Timer 1 Event
+// AUX_TIMER0_EV AUX Timer 0 Event
+// AUX_TDC_DONE TDC completed or timed out
+// AUX_ADC_DONE ADC conversion completed
+// AUX_COMPB Comparator B triggered
+// AUX_COMPA Comparator A triggered
+// AUX_SWEV2 AUX Software triggered event #2. Triggered by
+// AUX_EVCTL:SWEVSET.SWEV2
+// AUX_SWEV1 AUX Software triggered event #1. Triggered by
+// AUX_EVCTL:SWEVSET.SWEV1
+// AUX_SWEV0 AUX Software triggered event #0. Triggered by
+// AUX_EVCTL:SWEVSET.SWEV0
+// JTAG JTAG generated event
+// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line
+// toggles value every 32 kHz clock period)
+// RTC_COMB_DLY RTC combined delayed event
+// RTC_CH2_DLY RTC channel 2 - delayed event
+// RTC_CH1_DLY RTC channel 1 - delayed event
+// RTC_CH0_DLY RTC channel 0 - delayed event
+// RTC_CH2 RTC channel 2 event
+// RTC_CH1 RTC channel 1 event
+// RTC_CH0 RTC channel 0 event
+// PAD Edge detect on any PAD
+// BATMON_COMBINED Combined event from BATMON
+// BATMON_TEMP_LL BATMON event: Temperature level below lower limit
+// BATMON_TEMP_UL BATMON event: Temperature level above upper limit
+// BATMON_BATT_LL BATMON event: Battery level below lower limit
+// BATMON_BATT_UL BATMON event: Battery level above upper limit
+// AUX_TIMER2_EV3 Event 3 from AUX TImer2
+// AUX_TIMER2_EV2 Event 2 from AUX TImer2
+// AUX_TIMER2_EV1 Event 1 from AUX TImer2
+// AUX_TIMER2_EV0 Event 0 from AUX TImer2
+// IOEV_MCU_WU Edge detect IO event from the DIO(s) which have
+// enabled contribution to IOEV_MCU_WU in
+// [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN]
+#define AON_EVENT_MCUWUSEL1_WU5_EV_W 6
+#define AON_EVENT_MCUWUSEL1_WU5_EV_M 0x00003F00
+#define AON_EVENT_MCUWUSEL1_WU5_EV_S 8
+#define AON_EVENT_MCUWUSEL1_WU5_EV_NONE 0x00003F00
+#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_COMPB_ASYNC_N 0x00003800
+#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_COMPB_ASYNC 0x00003700
+#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_VOLT 0x00003600
+#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_TEMP 0x00003500
+#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TIMER1_EV 0x00003400
+#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TIMER0_EV 0x00003300
+#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TDC_DONE 0x00003200
+#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_ADC_DONE 0x00003100
+#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_COMPB 0x00003000
+#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_COMPA 0x00002F00
+#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_SWEV2 0x00002E00
+#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_SWEV1 0x00002D00
+#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_SWEV0 0x00002C00
+#define AON_EVENT_MCUWUSEL1_WU5_EV_JTAG 0x00002B00
+#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_UPD 0x00002A00
+#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_COMB_DLY 0x00002900
+#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_CH2_DLY 0x00002800
+#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_CH1_DLY 0x00002700
+#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_CH0_DLY 0x00002600
+#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_CH2 0x00002500
+#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_CH1 0x00002400
+#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_CH0 0x00002300
+#define AON_EVENT_MCUWUSEL1_WU5_EV_PAD 0x00002000
+#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_COMBINED 0x00000900
+#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_TEMP_LL 0x00000800
+#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_TEMP_UL 0x00000700
+#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_BATT_LL 0x00000600
+#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_BATT_UL 0x00000500
+#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TIMER2_EV3 0x00000400
+#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TIMER2_EV2 0x00000300
+#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TIMER2_EV1 0x00000200
+#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TIMER2_EV0 0x00000100
+#define AON_EVENT_MCUWUSEL1_WU5_EV_IOEV_MCU_WU 0x00000000
+
+// Field: [5:0] WU4_EV
+//
+// MCU Wakeup Source #4
+//
+// AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up
+// the MCU domain from Power Off or Power Down.
+// Note:
+// ENUMs:
+// NONE No event, always low
+// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal
+// directly from AUX Comparator B (inverted) as
+// opposed to AUX_COMPB which is synchronized in
+// AUX
+// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal
+// directly from the AUX Comparator B as opposed
+// to AUX_COMPB which is synchronized in AUX
+// BATMON_VOLT BATMON voltage update event
+// BATMON_TEMP BATMON temperature update event
+// AUX_TIMER1_EV AUX Timer 1 Event
+// AUX_TIMER0_EV AUX Timer 0 Event
+// AUX_TDC_DONE TDC completed or timed out
+// AUX_ADC_DONE ADC conversion completed
+// AUX_COMPB Comparator B triggered
+// AUX_COMPA Comparator A triggered
+// AUX_SWEV2 AUX Software triggered event #2. Triggered by
+// AUX_EVCTL:SWEVSET.SWEV2
+// AUX_SWEV1 AUX Software triggered event #1. Triggered by
+// AUX_EVCTL:SWEVSET.SWEV1
+// AUX_SWEV0 AUX Software triggered event #0. Triggered by
+// AUX_EVCTL:SWEVSET.SWEV0
+// JTAG JTAG generated event
+// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line
+// toggles value every 32 kHz clock period)
+// RTC_COMB_DLY RTC combined delayed event
+// RTC_CH2_DLY RTC channel 2 - delayed event
+// RTC_CH1_DLY RTC channel 1 - delayed event
+// RTC_CH0_DLY RTC channel 0 - delayed event
+// RTC_CH2 RTC channel 2 event
+// RTC_CH1 RTC channel 1 event
+// RTC_CH0 RTC channel 0 event
+// PAD Edge detect on any PAD
+// BATMON_COMBINED Combined event from BATMON
+// BATMON_TEMP_LL BATMON event: Temperature level below lower limit
+// BATMON_TEMP_UL BATMON event: Temperature level above upper limit
+// BATMON_BATT_LL BATMON event: Battery level below lower limit
+// BATMON_BATT_UL BATMON event: Battery level above upper limit
+// AUX_TIMER2_EV3 Event 3 from AUX TImer2
+// AUX_TIMER2_EV2 Event 2 from AUX TImer2
+// AUX_TIMER2_EV1 Event 1 from AUX TImer2
+// AUX_TIMER2_EV0 Event 0 from AUX TImer2
+// IOEV_MCU_WU Edge detect IO event from the DIO(s) which have
+// enabled contribution to IOEV_MCU_WU in
+// [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN]
+#define AON_EVENT_MCUWUSEL1_WU4_EV_W 6
+#define AON_EVENT_MCUWUSEL1_WU4_EV_M 0x0000003F
+#define AON_EVENT_MCUWUSEL1_WU4_EV_S 0
+#define AON_EVENT_MCUWUSEL1_WU4_EV_NONE 0x0000003F
+#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_COMPB_ASYNC_N 0x00000038
+#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_COMPB_ASYNC 0x00000037
+#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_VOLT 0x00000036
+#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_TEMP 0x00000035
+#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TIMER1_EV 0x00000034
+#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TIMER0_EV 0x00000033
+#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TDC_DONE 0x00000032
+#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_ADC_DONE 0x00000031
+#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_COMPB 0x00000030
+#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_COMPA 0x0000002F
+#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_SWEV2 0x0000002E
+#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_SWEV1 0x0000002D
+#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_SWEV0 0x0000002C
+#define AON_EVENT_MCUWUSEL1_WU4_EV_JTAG 0x0000002B
+#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_UPD 0x0000002A
+#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_COMB_DLY 0x00000029
+#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_CH2_DLY 0x00000028
+#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_CH1_DLY 0x00000027
+#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_CH0_DLY 0x00000026
+#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_CH2 0x00000025
+#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_CH1 0x00000024
+#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_CH0 0x00000023
+#define AON_EVENT_MCUWUSEL1_WU4_EV_PAD 0x00000020
+#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_COMBINED 0x00000009
+#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_TEMP_LL 0x00000008
+#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_TEMP_UL 0x00000007
+#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_BATT_LL 0x00000006
+#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_BATT_UL 0x00000005
+#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TIMER2_EV3 0x00000004
+#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TIMER2_EV2 0x00000003
+#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TIMER2_EV1 0x00000002
+#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TIMER2_EV0 0x00000001
+#define AON_EVENT_MCUWUSEL1_WU4_EV_IOEV_MCU_WU 0x00000000
+
+//*****************************************************************************
+//
+// Register: AON_EVENT_O_EVTOMCUSEL
+//
+//*****************************************************************************
+// Field: [21:16] AON_PROG2_EV
+//
+// Event selector for AON_PROG2 event.
+//
+// AON Event Source id# selecting event routed to EVENT as AON_PROG2 event.
+// ENUMs:
+// NONE No event, always low
+// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal
+// directly from AUX Comparator B (inverted) as
+// opposed to AUX_COMPB which is synchronized in
+// AUX
+// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal
+// directly from the AUX Comparator B as opposed
+// to AUX_COMPB which is synchronized in AUX
+// BATMON_VOLT BATMON voltage update event
+// BATMON_TEMP BATMON temperature update event
+// AUX_TIMER1_EV AUX Timer 1 Event
+// AUX_TIMER0_EV AUX Timer 0 Event
+// AUX_TDC_DONE TDC completed or timed out
+// AUX_ADC_DONE ADC conversion completed
+// AUX_COMPB Comparator B triggered
+// AUX_COMPA Comparator A triggered
+// AUX_SWEV2 AUX Software triggered event #2. Triggered by
+// AUX_EVCTL:SWEVSET.SWEV2
+// AUX_SWEV1 AUX Software triggered event #1. Triggered by
+// AUX_EVCTL:SWEVSET.SWEV1
+// AUX_SWEV0 AUX Software triggered event #0. Triggered by
+// AUX_EVCTL:SWEVSET.SWEV0
+// JTAG JTAG generated event
+// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line
+// toggles value every 32 kHz clock period)
+// RTC_COMB_DLY RTC combined delayed event
+// RTC_CH2_DLY RTC channel 2 - delayed event
+// RTC_CH1_DLY RTC channel 1 - delayed event
+// RTC_CH0_DLY RTC channel 0 - delayed event
+// RTC_CH2 RTC channel 2 event
+// RTC_CH1 RTC channel 1 event
+// RTC_CH0 RTC channel 0 event
+// PAD Edge detect on any PAD
+// BATMON_COMBINED Combined event from BATMON
+// BATMON_TEMP_LL BATMON event: Temperature level below lower limit
+// BATMON_TEMP_UL BATMON event: Temperature level above upper limit
+// BATMON_BATT_LL BATMON event: Battery level below lower limit
+// BATMON_BATT_UL BATMON event: Battery level above upper limit
+// AUX_TIMER2_EV3 Event 3 from AUX TImer2
+// AUX_TIMER2_EV2 Event 2 from AUX TImer2
+// AUX_TIMER2_EV1 Event 1 from AUX TImer2
+// AUX_TIMER2_EV0 Event 0 from AUX TImer2
+// IOEV_AON_PROG2 Edge detect IO event from the DIO(s) which have
+// enabled contribution to IOEV_AON_PROG2 in
+// [MCU_IOC:IOCFGx.IOEV_AON_PROG2_EN]
+#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_W 6
+#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M 0x003F0000
+#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S 16
+#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_NONE 0x003F0000
+#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB_ASYNC_N 0x00380000
+#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB_ASYNC 0x00370000
+#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_VOLT 0x00360000
+#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_TEMP 0x00350000
+#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER1_EV 0x00340000
+#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER0_EV 0x00330000
+#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TDC_DONE 0x00320000
+#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_ADC_DONE 0x00310000
+#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB 0x00300000
+#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPA 0x002F0000
+#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV2 0x002E0000
+#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV1 0x002D0000
+#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV0 0x002C0000
+#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_JTAG 0x002B0000
+#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_UPD 0x002A0000
+#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_COMB_DLY 0x00290000
+#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH2_DLY 0x00280000
+#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH1_DLY 0x00270000
+#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH0_DLY 0x00260000
+#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH2 0x00250000
+#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH1 0x00240000
+#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH0 0x00230000
+#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD 0x00200000
+#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_COMBINED 0x00090000
+#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_TEMP_LL 0x00080000
+#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_TEMP_UL 0x00070000
+#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_BATT_LL 0x00060000
+#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_BATT_UL 0x00050000
+#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER2_EV3 0x00040000
+#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER2_EV2 0x00030000
+#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER2_EV1 0x00020000
+#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER2_EV0 0x00010000
+#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_IOEV_AON_PROG2 0x00000000
+
+// Field: [13:8] AON_PROG1_EV
+//
+// Event selector for AON_PROG1 event.
+//
+// AON Event Source id# selecting event routed to EVENT as AON_PROG1 event.
+// ENUMs:
+// NONE
+// AUX_COMPB_ASYNC_N
+// AUX_COMPB_ASYNC
+// BATMON_VOLT
+// BATMON_TEMP
+// AUX_TIMER1_EV
+// AUX_TIMER0_EV
+// AUX_TDC_DONE
+// AUX_ADC_DONE
+// AUX_COMPB
+// AUX_COMPA
+// AUX_SWEV2
+// AUX_SWEV1
+// AUX_SWEV0
+// JTAG
+// RTC_UPD
+// RTC_COMB_DLY
+// RTC_CH2_DLY
+// RTC_CH1_DLY
+// RTC_CH0_DLY RTC channel 0 - delayed event
+// RTC_CH2 RTC channel 2 event
+// RTC_CH1 RTC channel 1 event
+// RTC_CH0 RTC channel 0 event
+// PAD Edge detect on any PAD
+// BATMON_COMBINED Combined event from BATMON
+// BATMON_TEMP_LL BATMON event: Temperature level below lower limit
+// BATMON_TEMP_UL BATMON event: Temperature level above upper limit
+// BATMON_BATT_LL BATMON event: Battery level below lower limit
+// BATMON_BATT_UL BATMON event: Battery level above upper limit
+// AUX_TIMER2_EV3 Event 3 from AUX TImer2
+// AUX_TIMER2_EV2 Event 2 from AUX TImer2
+// AUX_TIMER2_EV1 Event 1 from AUX TImer2
+// AUX_TIMER2_EV0 Event 0 from AUX TImer2
+// IOEV_AON_PROG1 Edge detect IO event from the DIO(s) which have
+// enabled contribution to IOEV_AON_PROG1 in
+// [MCU_IOC:IOCFGx.IOEV_AON_PROG1_EN]
+#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_W 6
+#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M 0x00003F00
+#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S 8
+#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_NONE 0x00003F00
+#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB_ASYNC_N 0x00003800
+#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB_ASYNC 0x00003700
+#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_VOLT 0x00003600
+#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_TEMP 0x00003500
+#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER1_EV 0x00003400
+#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER0_EV 0x00003300
+#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TDC_DONE 0x00003200
+#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_ADC_DONE 0x00003100
+#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB 0x00003000
+#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPA 0x00002F00
+#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV2 0x00002E00
+#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV1 0x00002D00
+#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV0 0x00002C00
+#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_JTAG 0x00002B00
+#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_UPD 0x00002A00
+#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_COMB_DLY 0x00002900
+#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH2_DLY 0x00002800
+#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH1_DLY 0x00002700
+#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH0_DLY 0x00002600
+#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH2 0x00002500
+#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH1 0x00002400
+#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH0 0x00002300
+#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD 0x00002000
+#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_COMBINED 0x00000900
+#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_TEMP_LL 0x00000800
+#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_TEMP_UL 0x00000700
+#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_BATT_LL 0x00000600
+#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_BATT_UL 0x00000500
+#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER2_EV3 0x00000400
+#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER2_EV2 0x00000300
+#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER2_EV1 0x00000200
+#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER2_EV0 0x00000100
+#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_IOEV_AON_PROG1 0x00000000
+
+// Field: [5:0] AON_PROG0_EV
+//
+// Event selector for AON_PROG0 event.
+//
+// AON Event Source id# selecting event routed to EVENT as AON_PROG0 event.
+// ENUMs:
+// NONE
+// AUX_COMPB_ASYNC_N
+// AUX_COMPB_ASYNC
+// BATMON_VOLT
+// BATMON_TEMP
+// AUX_TIMER1_EV
+// AUX_TIMER0_EV
+// AUX_TDC_DONE
+// AUX_ADC_DONE
+// AUX_COMPB
+// AUX_COMPA
+// AUX_SWEV2
+// AUX_SWEV1
+// AUX_SWEV0
+// JTAG
+// RTC_UPD
+// RTC_COMB_DLY
+// RTC_CH2_DLY
+// RTC_CH1_DLY
+// RTC_CH0_DLY
+// RTC_CH2
+// RTC_CH1
+// RTC_CH0
+// PAD
+// BATMON_COMBINED
+// BATMON_TEMP_LL
+// BATMON_TEMP_UL
+// BATMON_BATT_LL
+// BATMON_BATT_UL
+// AUX_TIMER2_EV3
+// AUX_TIMER2_EV2
+// AUX_TIMER2_EV1
+// AUX_TIMER2_EV0
+// IOEV_AON_PROG0 Edge detect IO event from the DIO(s) which have
+// enabled contribution to IOEV_AON_PROG0 in
+// [MCU_IOC:IOCFGx.IOEV_AON_PROG0_EN]
+#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_W 6
+#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M 0x0000003F
+#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S 0
+#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_NONE 0x0000003F
+#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB_ASYNC_N 0x00000038
+#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB_ASYNC 0x00000037
+#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_VOLT 0x00000036
+#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_TEMP 0x00000035
+#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER1_EV 0x00000034
+#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER0_EV 0x00000033
+#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TDC_DONE 0x00000032
+#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_ADC_DONE 0x00000031
+#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB 0x00000030
+#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPA 0x0000002F
+#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV2 0x0000002E
+#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV1 0x0000002D
+#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV0 0x0000002C
+#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_JTAG 0x0000002B
+#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_UPD 0x0000002A
+#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_COMB_DLY 0x00000029
+#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH2_DLY 0x00000028
+#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH1_DLY 0x00000027
+#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH0_DLY 0x00000026
+#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH2 0x00000025
+#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH1 0x00000024
+#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH0 0x00000023
+#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD 0x00000020
+#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_COMBINED 0x00000009
+#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_TEMP_LL 0x00000008
+#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_TEMP_UL 0x00000007
+#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_BATT_LL 0x00000006
+#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_BATT_UL 0x00000005
+#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER2_EV3 0x00000004
+#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER2_EV2 0x00000003
+#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER2_EV1 0x00000002
+#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER2_EV0 0x00000001
+#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_IOEV_AON_PROG0 0x00000000
+
+//*****************************************************************************
+//
+// Register: AON_EVENT_O_RTCSEL
+//
+//*****************************************************************************
+// Field: [5:0] RTC_CH1_CAPT_EV
+//
+// AON Event Source id# for RTCSEL event which is fed to AON_RTC. Please refer
+// to AON_RTC:CH1CAPT
+// ENUMs:
+// NONE
+// AUX_COMPB_ASYNC_N
+// AUX_COMPB_ASYNC
+// BATMON_VOLT
+// BATMON_TEMP
+// AUX_TIMER1_EV
+// AUX_TIMER0_EV
+// AUX_TDC_DONE
+// AUX_ADC_DONE
+// AUX_COMPB
+// AUX_COMPA
+// AUX_SWEV2
+// AUX_SWEV1
+// AUX_SWEV0
+// JTAG
+// RTC_UPD
+// RTC_COMB_DLY
+// RTC_CH2_DLY
+// RTC_CH1_DLY
+// RTC_CH0_DLY
+// RTC_CH2
+// RTC_CH1
+// RTC_CH0
+// PAD
+// BATMON_COMBINED
+// BATMON_TEMP_LL
+// BATMON_TEMP_UL
+// BATMON_BATT_LL
+// BATMON_BATT_UL
+// AUX_TIMER2_EV3
+// AUX_TIMER2_EV2
+// AUX_TIMER2_EV1
+// AUX_TIMER2_EV0
+// IOEV_RTC Edge detect IO event from the DIO(s) which have
+// enabled contribution to IOEV_RTC in
+// [MCU_IOC:IOCFGx.IOEV_RTC_EN]
+#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_W 6
+#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_M 0x0000003F
+#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_S 0
+#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_NONE 0x0000003F
+#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB_ASYNC_N 0x00000038
+#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB_ASYNC 0x00000037
+#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_VOLT 0x00000036
+#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_TEMP 0x00000035
+#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER1_EV 0x00000034
+#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER0_EV 0x00000033
+#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TDC_DONE 0x00000032
+#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_ADC_DONE 0x00000031
+#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB 0x00000030
+#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPA 0x0000002F
+#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV2 0x0000002E
+#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV1 0x0000002D
+#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV0 0x0000002C
+#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_JTAG 0x0000002B
+#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_UPD 0x0000002A
+#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_COMB_DLY 0x00000029
+#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH2_DLY 0x00000028
+#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH1_DLY 0x00000027
+#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH0_DLY 0x00000026
+#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH2 0x00000025
+#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH1 0x00000024
+#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH0 0x00000023
+#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD 0x00000020
+#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_COMBINED 0x00000009
+#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_TEMP_LL 0x00000008
+#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_TEMP_UL 0x00000007
+#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_BATT_LL 0x00000006
+#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_BATT_UL 0x00000005
+#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER2_EV3 0x00000004
+#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER2_EV2 0x00000003
+#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER2_EV1 0x00000002
+#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER2_EV0 0x00000001
+#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_IOEV_RTC 0x00000000
+
+
+#endif // __AON_EVENT__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_ioc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_ioc.h
new file mode 100644
index 0000000..d2e6d1f
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_ioc.h
@@ -0,0 +1,158 @@
+/******************************************************************************
+* Filename: hw_aon_ioc_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_AON_IOC_H__
+#define __HW_AON_IOC_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// AON_IOC component
+//
+//*****************************************************************************
+// Internal
+#define AON_IOC_O_IOSTRMIN 0x00000000
+
+// Internal
+#define AON_IOC_O_IOSTRMED 0x00000004
+
+// Internal
+#define AON_IOC_O_IOSTRMAX 0x00000008
+
+// IO Latch Control
+#define AON_IOC_O_IOCLATCH 0x0000000C
+
+// SCLK_LF External Output Control
+#define AON_IOC_O_CLK32KCTL 0x00000010
+
+// TCK IO Pin Control
+#define AON_IOC_O_TCKCTL 0x00000014
+
+//*****************************************************************************
+//
+// Register: AON_IOC_O_IOSTRMIN
+//
+//*****************************************************************************
+// Field: [2:0] GRAY_CODE
+//
+// Internal. Only to be used through TI provided API.
+#define AON_IOC_IOSTRMIN_GRAY_CODE_W 3
+#define AON_IOC_IOSTRMIN_GRAY_CODE_M 0x00000007
+#define AON_IOC_IOSTRMIN_GRAY_CODE_S 0
+
+//*****************************************************************************
+//
+// Register: AON_IOC_O_IOSTRMED
+//
+//*****************************************************************************
+// Field: [2:0] GRAY_CODE
+//
+// Internal. Only to be used through TI provided API.
+#define AON_IOC_IOSTRMED_GRAY_CODE_W 3
+#define AON_IOC_IOSTRMED_GRAY_CODE_M 0x00000007
+#define AON_IOC_IOSTRMED_GRAY_CODE_S 0
+
+//*****************************************************************************
+//
+// Register: AON_IOC_O_IOSTRMAX
+//
+//*****************************************************************************
+// Field: [2:0] GRAY_CODE
+//
+// Internal. Only to be used through TI provided API.
+#define AON_IOC_IOSTRMAX_GRAY_CODE_W 3
+#define AON_IOC_IOSTRMAX_GRAY_CODE_M 0x00000007
+#define AON_IOC_IOSTRMAX_GRAY_CODE_S 0
+
+//*****************************************************************************
+//
+// Register: AON_IOC_O_IOCLATCH
+//
+//*****************************************************************************
+// Field: [0] EN
+//
+// Controls latches between MCU IOC and AON_IOC.
+//
+// The latches are transparent by default.
+//
+// They must be closed prior to power off the domain(s) controlling the IOs in
+// order to preserve IO values on external pins.
+// ENUMs:
+// TRANSP Latches are transparent, meaning the value of the
+// IO is directly controlled by the GPIO or
+// peripheral value
+// STATIC Latches are static, meaning the current value on
+// the IO pin is frozen by latches and kept even
+// if GPIO module or a peripheral module is turned
+// off
+#define AON_IOC_IOCLATCH_EN 0x00000001
+#define AON_IOC_IOCLATCH_EN_BITN 0
+#define AON_IOC_IOCLATCH_EN_M 0x00000001
+#define AON_IOC_IOCLATCH_EN_S 0
+#define AON_IOC_IOCLATCH_EN_TRANSP 0x00000001
+#define AON_IOC_IOCLATCH_EN_STATIC 0x00000000
+
+//*****************************************************************************
+//
+// Register: AON_IOC_O_CLK32KCTL
+//
+//*****************************************************************************
+// Field: [0] OE_N
+//
+// 0: Output enable active. SCLK_LF output on IO pin that has PORT_ID (for
+// example IOC:IOCFG0.PORT_ID) set to AON_CLK32K.
+// 1: Output enable not active
+#define AON_IOC_CLK32KCTL_OE_N 0x00000001
+#define AON_IOC_CLK32KCTL_OE_N_BITN 0
+#define AON_IOC_CLK32KCTL_OE_N_M 0x00000001
+#define AON_IOC_CLK32KCTL_OE_N_S 0
+
+//*****************************************************************************
+//
+// Register: AON_IOC_O_TCKCTL
+//
+//*****************************************************************************
+// Field: [0] EN
+//
+// 0: Input driver for TCK disabled.
+// 1: Input driver for TCK enabled.
+#define AON_IOC_TCKCTL_EN 0x00000001
+#define AON_IOC_TCKCTL_EN_BITN 0
+#define AON_IOC_TCKCTL_EN_M 0x00000001
+#define AON_IOC_TCKCTL_EN_S 0
+
+
+#endif // __AON_IOC__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_pmctl.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_pmctl.h
new file mode 100644
index 0000000..e971217
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_pmctl.h
@@ -0,0 +1,625 @@
+/******************************************************************************
+* Filename: hw_aon_pmctl_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_AON_PMCTL_H__
+#define __HW_AON_PMCTL_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// AON_PMCTL component
+//
+//*****************************************************************************
+// AUX SCE Clock Management
+#define AON_PMCTL_O_AUXSCECLK 0x00000004
+
+// RAM Configuration
+#define AON_PMCTL_O_RAMCFG 0x00000008
+
+// Power Management Control
+#define AON_PMCTL_O_PWRCTL 0x00000010
+
+// AON Power and Reset Status
+#define AON_PMCTL_O_PWRSTAT 0x00000014
+
+// Shutdown Control
+#define AON_PMCTL_O_SHUTDOWN 0x00000018
+
+// Recharge Controller Configuration
+#define AON_PMCTL_O_RECHARGECFG 0x0000001C
+
+// Recharge Controller Status
+#define AON_PMCTL_O_RECHARGESTAT 0x00000020
+
+// Oscillator Configuration
+#define AON_PMCTL_O_OSCCFG 0x00000024
+
+// Reset Management
+#define AON_PMCTL_O_RESETCTL 0x00000028
+
+// Sleep Control
+#define AON_PMCTL_O_SLEEPCTL 0x0000002C
+
+// JTAG Configuration
+#define AON_PMCTL_O_JTAGCFG 0x00000034
+
+// JTAG USERCODE
+#define AON_PMCTL_O_JTAGUSERCODE 0x0000003C
+
+//*****************************************************************************
+//
+// Register: AON_PMCTL_O_AUXSCECLK
+//
+//*****************************************************************************
+// Field: [8] PD_SRC
+//
+// Selects the clock source for the AUX domain when AUX is in powerdown mode.
+// Note: Switching the clock source is guaranteed to be glitch-free
+// ENUMs:
+// SCLK_LF LF clock (SCLK_LF )
+// NO_CLOCK No clock
+#define AON_PMCTL_AUXSCECLK_PD_SRC 0x00000100
+#define AON_PMCTL_AUXSCECLK_PD_SRC_BITN 8
+#define AON_PMCTL_AUXSCECLK_PD_SRC_M 0x00000100
+#define AON_PMCTL_AUXSCECLK_PD_SRC_S 8
+#define AON_PMCTL_AUXSCECLK_PD_SRC_SCLK_LF 0x00000100
+#define AON_PMCTL_AUXSCECLK_PD_SRC_NO_CLOCK 0x00000000
+
+// Field: [0] SRC
+//
+// Selects the clock source for the AUX domain when AUX is in active mode.
+// Note: Switching the clock source is guaranteed to be glitch-free
+// ENUMs:
+// SCLK_MF MF Clock (SCLK_MF)
+// SCLK_HFDIV2 HF Clock divided by 2 (SCLK_HFDIV2)
+#define AON_PMCTL_AUXSCECLK_SRC 0x00000001
+#define AON_PMCTL_AUXSCECLK_SRC_BITN 0
+#define AON_PMCTL_AUXSCECLK_SRC_M 0x00000001
+#define AON_PMCTL_AUXSCECLK_SRC_S 0
+#define AON_PMCTL_AUXSCECLK_SRC_SCLK_MF 0x00000001
+#define AON_PMCTL_AUXSCECLK_SRC_SCLK_HFDIV2 0x00000000
+
+//*****************************************************************************
+//
+// Register: AON_PMCTL_O_RAMCFG
+//
+//*****************************************************************************
+// Field: [17] AUX_SRAM_PWR_OFF
+//
+// Internal. Only to be used through TI provided API.
+#define AON_PMCTL_RAMCFG_AUX_SRAM_PWR_OFF 0x00020000
+#define AON_PMCTL_RAMCFG_AUX_SRAM_PWR_OFF_BITN 17
+#define AON_PMCTL_RAMCFG_AUX_SRAM_PWR_OFF_M 0x00020000
+#define AON_PMCTL_RAMCFG_AUX_SRAM_PWR_OFF_S 17
+
+// Field: [16] AUX_SRAM_RET_EN
+//
+// Internal. Only to be used through TI provided API.
+#define AON_PMCTL_RAMCFG_AUX_SRAM_RET_EN 0x00010000
+#define AON_PMCTL_RAMCFG_AUX_SRAM_RET_EN_BITN 16
+#define AON_PMCTL_RAMCFG_AUX_SRAM_RET_EN_M 0x00010000
+#define AON_PMCTL_RAMCFG_AUX_SRAM_RET_EN_S 16
+
+// Field: [3:0] BUS_SRAM_RET_EN
+//
+// MCU SRAM is partitioned into 5 banks . This register controls which of the
+// banks that has retention during MCU Bus domain power off
+// ENUMs:
+// RET_FULL Retention on for all banks SRAM:BANK0, SRAM:BANK1
+// ,SRAM:BANK2, SRAM:BANK3 and SRAM:BANK4
+// RET_LEVEL3 Retention on for SRAM:BANK0, SRAM:BANK1
+// ,SRAM:BANK2 and SRAM:BANK3
+// RET_LEVEL2 Retention on for SRAM:BANK0, SRAM:BANK1 and
+// SRAM:BANK2
+// RET_LEVEL1 Retention on for SRAM:BANK0 and SRAM:BANK1
+// RET_NONE Retention is disabled
+#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_W 4
+#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_M 0x0000000F
+#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_S 0
+#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_FULL 0x0000000F
+#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL3 0x00000007
+#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL2 0x00000003
+#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL1 0x00000001
+#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Register: AON_PMCTL_O_PWRCTL
+//
+//*****************************************************************************
+// Field: [2] DCDC_ACTIVE
+//
+// Select to use DCDC regulator for VDDR in active mode
+//
+// 0: Use GLDO for regulation of VDDR in active mode.
+// 1: Use DCDC for regulation of VDDR in active mode.
+//
+// DCDC_EN must also be set for DCDC to be used as regulator for VDDR in active
+// mode
+#define AON_PMCTL_PWRCTL_DCDC_ACTIVE 0x00000004
+#define AON_PMCTL_PWRCTL_DCDC_ACTIVE_BITN 2
+#define AON_PMCTL_PWRCTL_DCDC_ACTIVE_M 0x00000004
+#define AON_PMCTL_PWRCTL_DCDC_ACTIVE_S 2
+
+// Field: [1] EXT_REG_MODE
+//
+// Status of source for VDDRsupply:
+//
+// 0: DCDC or GLDO are generating VDDR
+// 1: DCDC and GLDO are bypassed and an external regulator supplies VDDR
+#define AON_PMCTL_PWRCTL_EXT_REG_MODE 0x00000002
+#define AON_PMCTL_PWRCTL_EXT_REG_MODE_BITN 1
+#define AON_PMCTL_PWRCTL_EXT_REG_MODE_M 0x00000002
+#define AON_PMCTL_PWRCTL_EXT_REG_MODE_S 1
+
+// Field: [0] DCDC_EN
+//
+// Select to use DCDC regulator during recharge of VDDR
+//
+// 0: Use GLDO for recharge of VDDR
+// 1: Use DCDC for recharge of VDDR
+//
+// Note: This bitfield should be set to the same as DCDC_ACTIVE
+#define AON_PMCTL_PWRCTL_DCDC_EN 0x00000001
+#define AON_PMCTL_PWRCTL_DCDC_EN_BITN 0
+#define AON_PMCTL_PWRCTL_DCDC_EN_M 0x00000001
+#define AON_PMCTL_PWRCTL_DCDC_EN_S 0
+
+//*****************************************************************************
+//
+// Register: AON_PMCTL_O_PWRSTAT
+//
+//*****************************************************************************
+// Field: [2] JTAG_PD_ON
+//
+// Indicates JTAG power state:
+//
+// 0: JTAG is powered off
+// 1: JTAG is powered on
+#define AON_PMCTL_PWRSTAT_JTAG_PD_ON 0x00000004
+#define AON_PMCTL_PWRSTAT_JTAG_PD_ON_BITN 2
+#define AON_PMCTL_PWRSTAT_JTAG_PD_ON_M 0x00000004
+#define AON_PMCTL_PWRSTAT_JTAG_PD_ON_S 2
+
+// Field: [1] AUX_BUS_RESET_DONE
+//
+// Indicates Reset Done from AUX Bus:
+//
+// 0: AUX Bus is being reset
+// 1: AUX Bus reset is released
+#define AON_PMCTL_PWRSTAT_AUX_BUS_RESET_DONE 0x00000002
+#define AON_PMCTL_PWRSTAT_AUX_BUS_RESET_DONE_BITN 1
+#define AON_PMCTL_PWRSTAT_AUX_BUS_RESET_DONE_M 0x00000002
+#define AON_PMCTL_PWRSTAT_AUX_BUS_RESET_DONE_S 1
+
+// Field: [0] AUX_RESET_DONE
+//
+// Indicates Reset Done from AUX:
+//
+// 0: AUX is being reset
+// 1: AUX reset is released
+#define AON_PMCTL_PWRSTAT_AUX_RESET_DONE 0x00000001
+#define AON_PMCTL_PWRSTAT_AUX_RESET_DONE_BITN 0
+#define AON_PMCTL_PWRSTAT_AUX_RESET_DONE_M 0x00000001
+#define AON_PMCTL_PWRSTAT_AUX_RESET_DONE_S 0
+
+//*****************************************************************************
+//
+// Register: AON_PMCTL_O_SHUTDOWN
+//
+//*****************************************************************************
+// Field: [0] EN
+//
+// Shutdown control.
+//
+// 0: Do not write 0 to this bit.
+// 1: Immediately start the process to enter shutdown mode
+#define AON_PMCTL_SHUTDOWN_EN 0x00000001
+#define AON_PMCTL_SHUTDOWN_EN_BITN 0
+#define AON_PMCTL_SHUTDOWN_EN_M 0x00000001
+#define AON_PMCTL_SHUTDOWN_EN_S 0
+
+//*****************************************************************************
+//
+// Register: AON_PMCTL_O_RECHARGECFG
+//
+//*****************************************************************************
+// Field: [31:30] MODE
+//
+// Selects recharge algorithm for VDDR when the system is running on the uLDO
+// ENUMs:
+// COMPARATOR External recharge comparator.
+// Note that the clock to
+// the recharge comparator must be enabled,
+//
+// [ANATOP_MMAP:ADI_3_REFSYS:CTL_RECHARGE_CMP0:COMP_CLK_DISABLE],
+// before selecting this recharge algorithm.
+// ADAPTIVE Adaptive timer
+// STATIC Static timer
+// OFF Recharge disabled
+#define AON_PMCTL_RECHARGECFG_MODE_W 2
+#define AON_PMCTL_RECHARGECFG_MODE_M 0xC0000000
+#define AON_PMCTL_RECHARGECFG_MODE_S 30
+#define AON_PMCTL_RECHARGECFG_MODE_COMPARATOR 0xC0000000
+#define AON_PMCTL_RECHARGECFG_MODE_ADAPTIVE 0x80000000
+#define AON_PMCTL_RECHARGECFG_MODE_STATIC 0x40000000
+#define AON_PMCTL_RECHARGECFG_MODE_OFF 0x00000000
+
+// Field: [23:20] C2
+//
+// Internal. Only to be used through TI provided API.
+#define AON_PMCTL_RECHARGECFG_C2_W 4
+#define AON_PMCTL_RECHARGECFG_C2_M 0x00F00000
+#define AON_PMCTL_RECHARGECFG_C2_S 20
+
+// Field: [19:16] C1
+//
+// Internal. Only to be used through TI provided API.
+#define AON_PMCTL_RECHARGECFG_C1_W 4
+#define AON_PMCTL_RECHARGECFG_C1_M 0x000F0000
+#define AON_PMCTL_RECHARGECFG_C1_S 16
+
+// Field: [15:11] MAX_PER_M
+//
+// Internal. Only to be used through TI provided API.
+#define AON_PMCTL_RECHARGECFG_MAX_PER_M_W 5
+#define AON_PMCTL_RECHARGECFG_MAX_PER_M_M 0x0000F800
+#define AON_PMCTL_RECHARGECFG_MAX_PER_M_S 11
+
+// Field: [10:8] MAX_PER_E
+//
+// Internal. Only to be used through TI provided API.
+#define AON_PMCTL_RECHARGECFG_MAX_PER_E_W 3
+#define AON_PMCTL_RECHARGECFG_MAX_PER_E_M 0x00000700
+#define AON_PMCTL_RECHARGECFG_MAX_PER_E_S 8
+
+// Field: [7:3] PER_M
+//
+// Internal. Only to be used through TI provided API.
+#define AON_PMCTL_RECHARGECFG_PER_M_W 5
+#define AON_PMCTL_RECHARGECFG_PER_M_M 0x000000F8
+#define AON_PMCTL_RECHARGECFG_PER_M_S 3
+
+// Field: [2:0] PER_E
+//
+// Internal. Only to be used through TI provided API.
+#define AON_PMCTL_RECHARGECFG_PER_E_W 3
+#define AON_PMCTL_RECHARGECFG_PER_E_M 0x00000007
+#define AON_PMCTL_RECHARGECFG_PER_E_S 0
+
+//*****************************************************************************
+//
+// Register: AON_PMCTL_O_RECHARGESTAT
+//
+//*****************************************************************************
+// Field: [19:16] VDDR_SMPLS
+//
+// The last 4 VDDR samples.
+//
+// For each bit:
+// 0: VDDR was below VDDR_OK threshold when recharge started
+// 1: VDDR was above VDDR_OK threshold when recharge started
+//
+// The register is updated prior to every recharge period with a shift left,
+// and bit 0 is updated with the last VDDR sample.
+#define AON_PMCTL_RECHARGESTAT_VDDR_SMPLS_W 4
+#define AON_PMCTL_RECHARGESTAT_VDDR_SMPLS_M 0x000F0000
+#define AON_PMCTL_RECHARGESTAT_VDDR_SMPLS_S 16
+
+// Field: [15:0] MAX_USED_PER
+//
+// Shows the maximum number of 32kHz periods that have separated two recharge
+// cycles and VDDR still was above VDDR_OK threshold when the latter recharge
+// started. This register can be used as an indication of the leakage current
+// during standby.
+//
+// This bitfield is cleared to 0 when writing this register.
+#define AON_PMCTL_RECHARGESTAT_MAX_USED_PER_W 16
+#define AON_PMCTL_RECHARGESTAT_MAX_USED_PER_M 0x0000FFFF
+#define AON_PMCTL_RECHARGESTAT_MAX_USED_PER_S 0
+
+//*****************************************************************************
+//
+// Register: AON_PMCTL_O_OSCCFG
+//
+//*****************************************************************************
+// Field: [7:3] PER_M
+//
+// Internal. Only to be used through TI provided API.
+#define AON_PMCTL_OSCCFG_PER_M_W 5
+#define AON_PMCTL_OSCCFG_PER_M_M 0x000000F8
+#define AON_PMCTL_OSCCFG_PER_M_S 3
+
+// Field: [2:0] PER_E
+//
+// Internal. Only to be used through TI provided API.
+#define AON_PMCTL_OSCCFG_PER_E_W 3
+#define AON_PMCTL_OSCCFG_PER_E_M 0x00000007
+#define AON_PMCTL_OSCCFG_PER_E_S 0
+
+//*****************************************************************************
+//
+// Register: AON_PMCTL_O_RESETCTL
+//
+//*****************************************************************************
+// Field: [31] SYSRESET
+//
+// Cold reset register. Writing 1 to this bitfield will reset the entire chip
+// and cause boot code to run again.
+//
+// 0: No effect
+// 1: Generate system reset. Appears as SYSRESET in RESET_SRC
+#define AON_PMCTL_RESETCTL_SYSRESET 0x80000000
+#define AON_PMCTL_RESETCTL_SYSRESET_BITN 31
+#define AON_PMCTL_RESETCTL_SYSRESET_M 0x80000000
+#define AON_PMCTL_RESETCTL_SYSRESET_S 31
+
+// Field: [25] BOOT_DET_1_CLR
+//
+// Internal. Only to be used through TI provided API.
+#define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR 0x02000000
+#define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_BITN 25
+#define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_M 0x02000000
+#define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_S 25
+
+// Field: [24] BOOT_DET_0_CLR
+//
+// Internal. Only to be used through TI provided API.
+#define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR 0x01000000
+#define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_BITN 24
+#define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_M 0x01000000
+#define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_S 24
+
+// Field: [17] BOOT_DET_1_SET
+//
+// Internal. Only to be used through TI provided API.
+#define AON_PMCTL_RESETCTL_BOOT_DET_1_SET 0x00020000
+#define AON_PMCTL_RESETCTL_BOOT_DET_1_SET_BITN 17
+#define AON_PMCTL_RESETCTL_BOOT_DET_1_SET_M 0x00020000
+#define AON_PMCTL_RESETCTL_BOOT_DET_1_SET_S 17
+
+// Field: [16] BOOT_DET_0_SET
+//
+// Internal. Only to be used through TI provided API.
+#define AON_PMCTL_RESETCTL_BOOT_DET_0_SET 0x00010000
+#define AON_PMCTL_RESETCTL_BOOT_DET_0_SET_BITN 16
+#define AON_PMCTL_RESETCTL_BOOT_DET_0_SET_M 0x00010000
+#define AON_PMCTL_RESETCTL_BOOT_DET_0_SET_S 16
+
+// Field: [15] WU_FROM_SD
+//
+// A Wakeup from SHUTDOWN on an IO event has occurred, or a wakeup from
+// SHUTDOWN has occurred as a result of the debugger being attached.. (TCK pin
+// being forced low)
+//
+// Please refer to IOC:IOCFGn.WU_CFG for configuring the IO's as wakeup
+// sources.
+//
+// 0: Wakeup occurred from cold reset or brown out as seen in RESET_SRC
+// 1: A wakeup has occurred from SHUTDOWN
+//
+// Note: This flag will be cleared when SLEEPCTL.IO_PAD_SLEEP_DIS is asserted.
+#define AON_PMCTL_RESETCTL_WU_FROM_SD 0x00008000
+#define AON_PMCTL_RESETCTL_WU_FROM_SD_BITN 15
+#define AON_PMCTL_RESETCTL_WU_FROM_SD_M 0x00008000
+#define AON_PMCTL_RESETCTL_WU_FROM_SD_S 15
+
+// Field: [14] GPIO_WU_FROM_SD
+//
+// A wakeup from SHUTDOWN on an IO event has occurred
+//
+// Please refer to IOC:IOCFGn.WU_CFG for configuring the IO's as wakeup
+// sources.
+//
+// 0: The wakeup did not occur from SHUTDOWN on an IO event
+// 1: A wakeup from SHUTDOWN occurred from an IO event
+//
+// The case where WU_FROM_SD is asserted but this bitfield is not asserted will
+// only occur in a debug session. The boot code will not proceed with wakeup
+// from SHUTDOWN procedure until this bitfield is asserted as well.
+//
+// Note: This flag will be cleared when SLEEPCTL.IO_PAD_SLEEP_DIS is asserted.
+#define AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD 0x00004000
+#define AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD_BITN 14
+#define AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD_M 0x00004000
+#define AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD_S 14
+
+// Field: [13] BOOT_DET_1
+//
+// Internal. Only to be used through TI provided API.
+#define AON_PMCTL_RESETCTL_BOOT_DET_1 0x00002000
+#define AON_PMCTL_RESETCTL_BOOT_DET_1_BITN 13
+#define AON_PMCTL_RESETCTL_BOOT_DET_1_M 0x00002000
+#define AON_PMCTL_RESETCTL_BOOT_DET_1_S 13
+
+// Field: [12] BOOT_DET_0
+//
+// Internal. Only to be used through TI provided API.
+#define AON_PMCTL_RESETCTL_BOOT_DET_0 0x00001000
+#define AON_PMCTL_RESETCTL_BOOT_DET_0_BITN 12
+#define AON_PMCTL_RESETCTL_BOOT_DET_0_M 0x00001000
+#define AON_PMCTL_RESETCTL_BOOT_DET_0_S 12
+
+// Field: [8] VDDS_LOSS_EN
+//
+// Controls reset generation in case VDDS is lost
+//
+// 0: Brown out detect of VDDS is ignored, unless VDDS_LOSS_EN_OVR=1
+// 1: Brown out detect of VDDS generates system reset
+#define AON_PMCTL_RESETCTL_VDDS_LOSS_EN 0x00000100
+#define AON_PMCTL_RESETCTL_VDDS_LOSS_EN_BITN 8
+#define AON_PMCTL_RESETCTL_VDDS_LOSS_EN_M 0x00000100
+#define AON_PMCTL_RESETCTL_VDDS_LOSS_EN_S 8
+
+// Field: [7] VDDR_LOSS_EN
+//
+// Controls reset generation in case VDDR is lost
+//
+// 0: Brown out detect of VDDR is ignored, unless VDDR_LOSS_EN_OVR=1
+// 1: Brown out detect of VDDR generates system reset
+#define AON_PMCTL_RESETCTL_VDDR_LOSS_EN 0x00000080
+#define AON_PMCTL_RESETCTL_VDDR_LOSS_EN_BITN 7
+#define AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M 0x00000080
+#define AON_PMCTL_RESETCTL_VDDR_LOSS_EN_S 7
+
+// Field: [6] VDD_LOSS_EN
+//
+// Controls reset generation in case VDD is lost
+//
+// 0: Brown out detect of VDD is ignored, unless VDD_LOSS_EN_OVR=1
+// 1: Brown out detect of VDD generates system reset
+#define AON_PMCTL_RESETCTL_VDD_LOSS_EN 0x00000040
+#define AON_PMCTL_RESETCTL_VDD_LOSS_EN_BITN 6
+#define AON_PMCTL_RESETCTL_VDD_LOSS_EN_M 0x00000040
+#define AON_PMCTL_RESETCTL_VDD_LOSS_EN_S 6
+
+// Field: [5] CLK_LOSS_EN
+//
+// Controls reset generation in case SCLK_LF, SCLK_MF or SCLK_HF is lost when
+// clock loss detection is enabled by [ANATOP_MMAP:DDI_0_OSC:CTL0.CLK_LOSS_EN]
+//
+// 0: Clock loss is ignored
+// 1: Clock loss generates system reset
+//
+// Note: Clock loss reset generation must be disabled when changing clock
+// source for SCLK_LF. Failure to do so may result in a spurious system
+// reset. Clock loss reset generation is controlled by
+// [ANATOP_MMAP:DDI_0_OSC:CTL0.CLK_LOSS_EN]
+#define AON_PMCTL_RESETCTL_CLK_LOSS_EN 0x00000020
+#define AON_PMCTL_RESETCTL_CLK_LOSS_EN_BITN 5
+#define AON_PMCTL_RESETCTL_CLK_LOSS_EN_M 0x00000020
+#define AON_PMCTL_RESETCTL_CLK_LOSS_EN_S 5
+
+// Field: [4] MCU_WARM_RESET
+//
+// Internal. Only to be used through TI provided API.
+#define AON_PMCTL_RESETCTL_MCU_WARM_RESET 0x00000010
+#define AON_PMCTL_RESETCTL_MCU_WARM_RESET_BITN 4
+#define AON_PMCTL_RESETCTL_MCU_WARM_RESET_M 0x00000010
+#define AON_PMCTL_RESETCTL_MCU_WARM_RESET_S 4
+
+// Field: [3:1] RESET_SRC
+//
+// Shows the root cause of the last system reset. More than the reported reset
+// source can have been active during the last system reset but only the root
+// cause is reported.
+//
+// The capture feature is not rearmed until all off the possible reset sources
+// have been released and the result has been copied to AON_PMCTL. During the
+// copy and rearm process it is one 2MHz period in which and eventual new
+// system reset will be reported as Power on reset regardless of the root
+// cause.
+// ENUMs:
+// WARMRESET Software reset via PRCM warm reset request
+// SYSRESET Software reset via SYSRESET or hardware power
+// management timeout detection.
+//
+// Note: The hardware power
+// management timeout circuit is always enabled.
+// CLK_LOSS SCLK_LF, SCLK_MF or SCLK_HF clock loss detect
+// VDDR_LOSS Brown out detect on VDDR
+// VDDS_LOSS Brown out detect on VDDS
+// PIN_RESET Reset pin
+// PWR_ON Power on reset
+#define AON_PMCTL_RESETCTL_RESET_SRC_W 3
+#define AON_PMCTL_RESETCTL_RESET_SRC_M 0x0000000E
+#define AON_PMCTL_RESETCTL_RESET_SRC_S 1
+#define AON_PMCTL_RESETCTL_RESET_SRC_WARMRESET 0x0000000E
+#define AON_PMCTL_RESETCTL_RESET_SRC_SYSRESET 0x0000000C
+#define AON_PMCTL_RESETCTL_RESET_SRC_CLK_LOSS 0x0000000A
+#define AON_PMCTL_RESETCTL_RESET_SRC_VDDR_LOSS 0x00000008
+#define AON_PMCTL_RESETCTL_RESET_SRC_VDDS_LOSS 0x00000004
+#define AON_PMCTL_RESETCTL_RESET_SRC_PIN_RESET 0x00000002
+#define AON_PMCTL_RESETCTL_RESET_SRC_PWR_ON 0x00000000
+
+//*****************************************************************************
+//
+// Register: AON_PMCTL_O_SLEEPCTL
+//
+//*****************************************************************************
+// Field: [0] IO_PAD_SLEEP_DIS
+//
+// Controls the I/O pad sleep mode. The boot code will set this bitfield
+// automatically unless waking up from a SHUTDOWN ( RESETCTL.WU_FROM_SD is
+// set).
+//
+// 0: I/O pad sleep mode is enabled, meaning all outputs and pad configurations
+// are latched. Inputs are transparent if pad is configured as input before
+// IO_PAD_SLEEP_DIS is set to 1
+// 1: I/O pad sleep mode is disabled
+//
+// Application software must reconfigure the state for all IO's before setting
+// this bitfield upon waking up from a SHUTDOWN to avoid glitches on pins.
+#define AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS 0x00000001
+#define AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_BITN 0
+#define AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_M 0x00000001
+#define AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_S 0
+
+//*****************************************************************************
+//
+// Register: AON_PMCTL_O_JTAGCFG
+//
+//*****************************************************************************
+// Field: [8] JTAG_PD_FORCE_ON
+//
+// Controls JTAG Power domain power state:
+//
+// 0: Controlled exclusively by debug subsystem. (JTAG Power domain will be
+// powered off unless a debugger is attached)
+// 1: JTAG Power Domain is forced on, independent of debug subsystem.
+//
+// Note: The reset value causes JTAG Power domain to be powered on by default.
+// Software must clear this bit to turn off the JTAG Power domain
+#define AON_PMCTL_JTAGCFG_JTAG_PD_FORCE_ON 0x00000100
+#define AON_PMCTL_JTAGCFG_JTAG_PD_FORCE_ON_BITN 8
+#define AON_PMCTL_JTAGCFG_JTAG_PD_FORCE_ON_M 0x00000100
+#define AON_PMCTL_JTAGCFG_JTAG_PD_FORCE_ON_S 8
+
+//*****************************************************************************
+//
+// Register: AON_PMCTL_O_JTAGUSERCODE
+//
+//*****************************************************************************
+// Field: [31:0] USER_CODE
+//
+// 32-bit JTAG USERCODE register feeding main JTAG TAP
+// Note: This field can be locked by LOCKCFG.LOCK
+#define AON_PMCTL_JTAGUSERCODE_USER_CODE_W 32
+#define AON_PMCTL_JTAGUSERCODE_USER_CODE_M 0xFFFFFFFF
+#define AON_PMCTL_JTAGUSERCODE_USER_CODE_S 0
+
+
+#endif // __AON_PMCTL__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_rtc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_rtc.h
new file mode 100644
index 0000000..1718015
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_rtc.h
@@ -0,0 +1,546 @@
+/******************************************************************************
+* Filename: hw_aon_rtc_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_AON_RTC_H__
+#define __HW_AON_RTC_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// AON_RTC component
+//
+//*****************************************************************************
+// Control
+#define AON_RTC_O_CTL 0x00000000
+
+// Event Flags, RTC Status
+#define AON_RTC_O_EVFLAGS 0x00000004
+
+// Second Counter Value, Integer Part
+#define AON_RTC_O_SEC 0x00000008
+
+// Second Counter Value, Fractional Part
+#define AON_RTC_O_SUBSEC 0x0000000C
+
+// Subseconds Increment
+#define AON_RTC_O_SUBSECINC 0x00000010
+
+// Channel Configuration
+#define AON_RTC_O_CHCTL 0x00000014
+
+// Channel 0 Compare Value
+#define AON_RTC_O_CH0CMP 0x00000018
+
+// Channel 1 Compare Value
+#define AON_RTC_O_CH1CMP 0x0000001C
+
+// Channel 2 Compare Value
+#define AON_RTC_O_CH2CMP 0x00000020
+
+// Channel 2 Compare Value Auto-increment
+#define AON_RTC_O_CH2CMPINC 0x00000024
+
+// Channel 1 Capture Value
+#define AON_RTC_O_CH1CAPT 0x00000028
+
+// AON Synchronization
+#define AON_RTC_O_SYNC 0x0000002C
+
+// Current Counter Value
+#define AON_RTC_O_TIME 0x00000030
+
+// Synchronization to SCLK_LF
+#define AON_RTC_O_SYNCLF 0x00000034
+
+//*****************************************************************************
+//
+// Register: AON_RTC_O_CTL
+//
+//*****************************************************************************
+// Field: [18:16] COMB_EV_MASK
+//
+// Eventmask selecting which delayed events that form the combined event.
+// ENUMs:
+// CH2 Use Channel 2 delayed event in combined event
+// CH1 Use Channel 1 delayed event in combined event
+// CH0 Use Channel 0 delayed event in combined event
+// NONE No event is selected for combined event.
+#define AON_RTC_CTL_COMB_EV_MASK_W 3
+#define AON_RTC_CTL_COMB_EV_MASK_M 0x00070000
+#define AON_RTC_CTL_COMB_EV_MASK_S 16
+#define AON_RTC_CTL_COMB_EV_MASK_CH2 0x00040000
+#define AON_RTC_CTL_COMB_EV_MASK_CH1 0x00020000
+#define AON_RTC_CTL_COMB_EV_MASK_CH0 0x00010000
+#define AON_RTC_CTL_COMB_EV_MASK_NONE 0x00000000
+
+// Field: [11:8] EV_DELAY
+//
+// Number of SCLK_LF clock cycles waited before generating delayed events.
+// (Common setting for all RTC cannels) the delayed event is delayed
+// ENUMs:
+// D144 Delay by 144 clock cycles
+// D128 Delay by 128 clock cycles
+// D112 Delay by 112 clock cycles
+// D96 Delay by 96 clock cycles
+// D80 Delay by 80 clock cycles
+// D64 Delay by 64 clock cycles
+// D48 Delay by 48 clock cycles
+// D32 Delay by 32 clock cycles
+// D16 Delay by 16 clock cycles
+// D8 Delay by 8 clock cycles
+// D4 Delay by 4 clock cycles
+// D2 Delay by 2 clock cycles
+// D1 Delay by 1 clock cycles
+// D0 No delay on delayed event
+#define AON_RTC_CTL_EV_DELAY_W 4
+#define AON_RTC_CTL_EV_DELAY_M 0x00000F00
+#define AON_RTC_CTL_EV_DELAY_S 8
+#define AON_RTC_CTL_EV_DELAY_D144 0x00000D00
+#define AON_RTC_CTL_EV_DELAY_D128 0x00000C00
+#define AON_RTC_CTL_EV_DELAY_D112 0x00000B00
+#define AON_RTC_CTL_EV_DELAY_D96 0x00000A00
+#define AON_RTC_CTL_EV_DELAY_D80 0x00000900
+#define AON_RTC_CTL_EV_DELAY_D64 0x00000800
+#define AON_RTC_CTL_EV_DELAY_D48 0x00000700
+#define AON_RTC_CTL_EV_DELAY_D32 0x00000600
+#define AON_RTC_CTL_EV_DELAY_D16 0x00000500
+#define AON_RTC_CTL_EV_DELAY_D8 0x00000400
+#define AON_RTC_CTL_EV_DELAY_D4 0x00000300
+#define AON_RTC_CTL_EV_DELAY_D2 0x00000200
+#define AON_RTC_CTL_EV_DELAY_D1 0x00000100
+#define AON_RTC_CTL_EV_DELAY_D0 0x00000000
+
+// Field: [7] RESET
+//
+// RTC Counter reset.
+//
+// Writing 1 to this bit will reset the RTC counter.
+//
+// This bit is cleared when reset takes effect
+#define AON_RTC_CTL_RESET 0x00000080
+#define AON_RTC_CTL_RESET_BITN 7
+#define AON_RTC_CTL_RESET_M 0x00000080
+#define AON_RTC_CTL_RESET_S 7
+
+// Field: [2] RTC_4KHZ_EN
+//
+// RTC_4KHZ is a 4 KHz reference output, tapped from SUBSEC.VALUE bit 19
+// which is used by AUX timer.
+//
+// 0: RTC_4KHZ signal is forced to 0
+// 1: RTC_4KHZ is enabled ( provied that RTC is enabled EN)
+#define AON_RTC_CTL_RTC_4KHZ_EN 0x00000004
+#define AON_RTC_CTL_RTC_4KHZ_EN_BITN 2
+#define AON_RTC_CTL_RTC_4KHZ_EN_M 0x00000004
+#define AON_RTC_CTL_RTC_4KHZ_EN_S 2
+
+// Field: [1] RTC_UPD_EN
+//
+// RTC_UPD is a 16 KHz signal used to sync up the radio timer. The 16 Khz is
+// SCLK_LF divided by 2
+//
+// 0: RTC_UPD signal is forced to 0
+// 1: RTC_UPD signal is toggling @16 kHz
+#define AON_RTC_CTL_RTC_UPD_EN 0x00000002
+#define AON_RTC_CTL_RTC_UPD_EN_BITN 1
+#define AON_RTC_CTL_RTC_UPD_EN_M 0x00000002
+#define AON_RTC_CTL_RTC_UPD_EN_S 1
+
+// Field: [0] EN
+//
+// Enable RTC counter
+//
+// 0: Halted (frozen)
+// 1: Running
+#define AON_RTC_CTL_EN 0x00000001
+#define AON_RTC_CTL_EN_BITN 0
+#define AON_RTC_CTL_EN_M 0x00000001
+#define AON_RTC_CTL_EN_S 0
+
+//*****************************************************************************
+//
+// Register: AON_RTC_O_EVFLAGS
+//
+//*****************************************************************************
+// Field: [16] CH2
+//
+// Channel 2 event flag, set when CHCTL.CH2_EN = 1 and the RTC value matches or
+// passes the CH2CMP value.
+//
+// An event will be scheduled to occur as soon as possible when writing to
+// CH2CMP provided that the channel is enabled and the new value matches any
+// time between next RTC value and 1 second in the past
+//
+// Writing 1 clears this flag.
+//
+// AUX_SCE can read the flag through AUX_EVCTL:EVSTAT2.AON_RTC_CH2 and clear it
+// using AUX_SYSIF:RTCEVCLR.RTC_CH2_EV_CLR.
+#define AON_RTC_EVFLAGS_CH2 0x00010000
+#define AON_RTC_EVFLAGS_CH2_BITN 16
+#define AON_RTC_EVFLAGS_CH2_M 0x00010000
+#define AON_RTC_EVFLAGS_CH2_S 16
+
+// Field: [8] CH1
+//
+// Channel 1 event flag, set when CHCTL.CH1_EN = 1 and one of the following:
+// - CHCTL.CH1_CAPT_EN = 0 and the RTC value matches or passes the CH1CMP
+// value.
+// - CHCTL.CH1_CAPT_EN = 1 and capture occurs.
+//
+// An event will be scheduled to occur as soon as possible when writing to
+// CH1CMP provided that the channel is enabled, in compare mode and the new
+// value matches any time between next RTC value and 1 second in the past.
+//
+// Writing 1 clears this flag.
+#define AON_RTC_EVFLAGS_CH1 0x00000100
+#define AON_RTC_EVFLAGS_CH1_BITN 8
+#define AON_RTC_EVFLAGS_CH1_M 0x00000100
+#define AON_RTC_EVFLAGS_CH1_S 8
+
+// Field: [0] CH0
+//
+// Channel 0 event flag, set when CHCTL.CH0_EN = 1 and the RTC value matches or
+// passes the CH0CMP value.
+//
+// An event will be scheduled to occur as soon as possible when writing to
+// CH0CMP provided that the channels is enabled and the new value matches any
+// time between next RTC value and 1 second in the past.
+//
+// Writing 1 clears this flag.
+#define AON_RTC_EVFLAGS_CH0 0x00000001
+#define AON_RTC_EVFLAGS_CH0_BITN 0
+#define AON_RTC_EVFLAGS_CH0_M 0x00000001
+#define AON_RTC_EVFLAGS_CH0_S 0
+
+//*****************************************************************************
+//
+// Register: AON_RTC_O_SEC
+//
+//*****************************************************************************
+// Field: [31:0] VALUE
+//
+// Unsigned integer representing Real Time Clock in seconds.
+//
+// When reading this register the content of SUBSEC.VALUE is simultaneously
+// latched. A consistent reading of the combined Real Time Clock can be
+// obtained by first reading this register, then reading SUBSEC register.
+#define AON_RTC_SEC_VALUE_W 32
+#define AON_RTC_SEC_VALUE_M 0xFFFFFFFF
+#define AON_RTC_SEC_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AON_RTC_O_SUBSEC
+//
+//*****************************************************************************
+// Field: [31:0] VALUE
+//
+// Unsigned integer representing Real Time Clock in fractions of a second
+// (VALUE/2^32 seconds) at the time when SEC register was read.
+//
+// Examples :
+// - 0x0000_0000 = 0.0 sec
+// - 0x4000_0000 = 0.25 sec
+// - 0x8000_0000 = 0.5 sec
+// - 0xC000_0000 = 0.75 sec
+#define AON_RTC_SUBSEC_VALUE_W 32
+#define AON_RTC_SUBSEC_VALUE_M 0xFFFFFFFF
+#define AON_RTC_SUBSEC_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AON_RTC_O_SUBSECINC
+//
+//*****************************************************************************
+// Field: [23:0] VALUEINC
+//
+// This value compensates for a SCLK_LF clock which has an offset from 32768
+// Hz.
+//
+// The compensation value can be found as 2^38 / freq, where freq is SCLK_LF
+// clock frequency in Hertz
+//
+// This value is added to SUBSEC.VALUE on every cycle, and carry of this is
+// added to SEC.VALUE. To perform the addition, bits [23:6] are aligned with
+// SUBSEC.VALUE bits [17:0]. The remaining bits [5:0] are accumulated in a
+// hidden 6-bit register that generates a carry into the above mentioned
+// addition on overflow.
+// The default value corresponds to incrementing by precisely 1/32768 of a
+// second.
+//
+// NOTE: This register is read only. Modification of the register value must be
+// done using registers AUX_SYSIF:RTCSUBSECINC0 , AUX_SYSIF:RTCSUBSECINC1 and
+// AUX_SYSIF:RTCSUBSECINCCTL
+#define AON_RTC_SUBSECINC_VALUEINC_W 24
+#define AON_RTC_SUBSECINC_VALUEINC_M 0x00FFFFFF
+#define AON_RTC_SUBSECINC_VALUEINC_S 0
+
+//*****************************************************************************
+//
+// Register: AON_RTC_O_CHCTL
+//
+//*****************************************************************************
+// Field: [18] CH2_CONT_EN
+//
+// Set to enable continuous operation of Channel 2
+#define AON_RTC_CHCTL_CH2_CONT_EN 0x00040000
+#define AON_RTC_CHCTL_CH2_CONT_EN_BITN 18
+#define AON_RTC_CHCTL_CH2_CONT_EN_M 0x00040000
+#define AON_RTC_CHCTL_CH2_CONT_EN_S 18
+
+// Field: [16] CH2_EN
+//
+// RTC Channel 2 Enable
+//
+// 0: Disable RTC Channel 2
+// 1: Enable RTC Channel 2
+#define AON_RTC_CHCTL_CH2_EN 0x00010000
+#define AON_RTC_CHCTL_CH2_EN_BITN 16
+#define AON_RTC_CHCTL_CH2_EN_M 0x00010000
+#define AON_RTC_CHCTL_CH2_EN_S 16
+
+// Field: [9] CH1_CAPT_EN
+//
+// Set Channel 1 mode
+//
+// 0: Compare mode (default)
+// 1: Capture mode
+#define AON_RTC_CHCTL_CH1_CAPT_EN 0x00000200
+#define AON_RTC_CHCTL_CH1_CAPT_EN_BITN 9
+#define AON_RTC_CHCTL_CH1_CAPT_EN_M 0x00000200
+#define AON_RTC_CHCTL_CH1_CAPT_EN_S 9
+
+// Field: [8] CH1_EN
+//
+// RTC Channel 1 Enable
+//
+// 0: Disable RTC Channel 1
+// 1: Enable RTC Channel 1
+#define AON_RTC_CHCTL_CH1_EN 0x00000100
+#define AON_RTC_CHCTL_CH1_EN_BITN 8
+#define AON_RTC_CHCTL_CH1_EN_M 0x00000100
+#define AON_RTC_CHCTL_CH1_EN_S 8
+
+// Field: [0] CH0_EN
+//
+// RTC Channel 0 Enable
+//
+// 0: Disable RTC Channel 0
+// 1: Enable RTC Channel 0
+#define AON_RTC_CHCTL_CH0_EN 0x00000001
+#define AON_RTC_CHCTL_CH0_EN_BITN 0
+#define AON_RTC_CHCTL_CH0_EN_M 0x00000001
+#define AON_RTC_CHCTL_CH0_EN_S 0
+
+//*****************************************************************************
+//
+// Register: AON_RTC_O_CH0CMP
+//
+//*****************************************************************************
+// Field: [31:0] VALUE
+//
+// RTC Channel 0 compare value.
+//
+// Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of
+// the compare value.
+//
+// The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE
+// (31:16) values of the Real Time Clock register. A Cannel 0 event is
+// generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or
+// exciting the compare value.
+//
+// Writing to this register can trigger an immediate*) event in case the new
+// compare value matches a Real Time Clock value from 1 second in the past up
+// till current Real Time Clock value.
+//
+// Example:
+// To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000
+//
+// *) It can take up to one SCLK_LF clock cycles before event occurs due to
+// synchronization.
+#define AON_RTC_CH0CMP_VALUE_W 32
+#define AON_RTC_CH0CMP_VALUE_M 0xFFFFFFFF
+#define AON_RTC_CH0CMP_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AON_RTC_O_CH1CMP
+//
+//*****************************************************************************
+// Field: [31:0] VALUE
+//
+// RTC Channel 1 compare value.
+//
+// Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of
+// the compare value.
+//
+// The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE
+// (31:16) values of the Real Time Clock register. A Cannel 0 event is
+// generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or
+// exciting the compare value.
+//
+// Writing to this register can trigger an immediate*) event in case the new
+// compare value matches a Real Time Clock value from 1 second in the past up
+// till current Real Time Clock value.
+//
+// Example:
+// To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000
+//
+// *) It can take up to one SCLK_LF clock cycles before event occurs due to
+// synchronization.
+#define AON_RTC_CH1CMP_VALUE_W 32
+#define AON_RTC_CH1CMP_VALUE_M 0xFFFFFFFF
+#define AON_RTC_CH1CMP_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AON_RTC_O_CH2CMP
+//
+//*****************************************************************************
+// Field: [31:0] VALUE
+//
+// RTC Channel 2 compare value.
+//
+// Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of
+// the compare value.
+//
+// The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE
+// (31:16) values of the Real Time Clock register. A Cannel 0 event is
+// generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or
+// exciting the compare value.
+//
+// Writing to this register can trigger an immediate*) event in case the new
+// compare value matches a Real Time Clock value from 1 second in the past up
+// till current Real Time Clock value.
+//
+// Example:
+// To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000
+//
+// *) It can take up to one SCLK_LF clock cycles before event occurs due to
+// synchronization.
+#define AON_RTC_CH2CMP_VALUE_W 32
+#define AON_RTC_CH2CMP_VALUE_M 0xFFFFFFFF
+#define AON_RTC_CH2CMP_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AON_RTC_O_CH2CMPINC
+//
+//*****************************************************************************
+// Field: [31:0] VALUE
+//
+// If CHCTL.CH2_CONT_EN is set, this value is added to CH2CMP.VALUE on every
+// channel 2 compare event.
+#define AON_RTC_CH2CMPINC_VALUE_W 32
+#define AON_RTC_CH2CMPINC_VALUE_M 0xFFFFFFFF
+#define AON_RTC_CH2CMPINC_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AON_RTC_O_CH1CAPT
+//
+//*****************************************************************************
+// Field: [31:16] SEC
+//
+// Value of SEC.VALUE bits 15:0 at capture time.
+#define AON_RTC_CH1CAPT_SEC_W 16
+#define AON_RTC_CH1CAPT_SEC_M 0xFFFF0000
+#define AON_RTC_CH1CAPT_SEC_S 16
+
+// Field: [15:0] SUBSEC
+//
+// Value of SUBSEC.VALUE bits 31:16 at capture time.
+#define AON_RTC_CH1CAPT_SUBSEC_W 16
+#define AON_RTC_CH1CAPT_SUBSEC_M 0x0000FFFF
+#define AON_RTC_CH1CAPT_SUBSEC_S 0
+
+//*****************************************************************************
+//
+// Register: AON_RTC_O_SYNC
+//
+//*****************************************************************************
+// Field: [0] WBUSY
+//
+// This register will always return 0,- however it will not return the value
+// until there are no outstanding write requests between MCU and AON
+//
+// Note: Writing to this register prior to reading will force a wait until next
+// SCLK_MF edge. This is recommended for syncing read registers from AON when
+// waking up from sleep
+// Failure to do so may result in reading AON values from prior to going to
+// sleep
+#define AON_RTC_SYNC_WBUSY 0x00000001
+#define AON_RTC_SYNC_WBUSY_BITN 0
+#define AON_RTC_SYNC_WBUSY_M 0x00000001
+#define AON_RTC_SYNC_WBUSY_S 0
+
+//*****************************************************************************
+//
+// Register: AON_RTC_O_TIME
+//
+//*****************************************************************************
+// Field: [31:16] SEC_L
+//
+// Returns the lower halfword of SEC register.
+#define AON_RTC_TIME_SEC_L_W 16
+#define AON_RTC_TIME_SEC_L_M 0xFFFF0000
+#define AON_RTC_TIME_SEC_L_S 16
+
+// Field: [15:0] SUBSEC_H
+//
+// Returns the upper halfword of SUBSEC register.
+#define AON_RTC_TIME_SUBSEC_H_W 16
+#define AON_RTC_TIME_SUBSEC_H_M 0x0000FFFF
+#define AON_RTC_TIME_SUBSEC_H_S 0
+
+//*****************************************************************************
+//
+// Register: AON_RTC_O_SYNCLF
+//
+//*****************************************************************************
+// Field: [0] PHASE
+//
+// This bit will always return the SCLK_LF phase. The return will delayed until
+// a positive or negative edge of SCLK_LF is seen.
+// 0: Falling edge of SCLK_LF
+// 1: Rising edge of SCLK_LF
+#define AON_RTC_SYNCLF_PHASE 0x00000001
+#define AON_RTC_SYNCLF_PHASE_BITN 0
+#define AON_RTC_SYNCLF_PHASE_M 0x00000001
+#define AON_RTC_SYNCLF_PHASE_S 0
+
+
+#endif // __AON_RTC__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_aiodio.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_aiodio.h
new file mode 100644
index 0000000..a66a0d5
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_aiodio.h
@@ -0,0 +1,1030 @@
+/******************************************************************************
+* Filename: hw_aux_aiodio_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_AUX_AIODIO_H__
+#define __HW_AUX_AIODIO_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// AUX_AIODIO component
+//
+//*****************************************************************************
+// Input Output Mode
+#define AUX_AIODIO_O_IOMODE 0x00000000
+
+// General Purpose Input Output Digital Input Enable
+#define AUX_AIODIO_O_GPIODIE 0x00000004
+
+// Input Output Peripheral Output Enable
+#define AUX_AIODIO_O_IOPOE 0x00000008
+
+// General Purpose Input Output Data Out
+#define AUX_AIODIO_O_GPIODOUT 0x0000000C
+
+// General Purpose Input Output Data In
+#define AUX_AIODIO_O_GPIODIN 0x00000010
+
+// General Purpose Input Output Data Out Set
+#define AUX_AIODIO_O_GPIODOUTSET 0x00000014
+
+// General Purpose Input Output Data Out Clear
+#define AUX_AIODIO_O_GPIODOUTCLR 0x00000018
+
+// General Purpose Input Output Data Out Toggle
+#define AUX_AIODIO_O_GPIODOUTTGL 0x0000001C
+
+// Input Output 0 Peripheral Select
+#define AUX_AIODIO_O_IO0PSEL 0x00000020
+
+// Input Output 1 Peripheral Select
+#define AUX_AIODIO_O_IO1PSEL 0x00000024
+
+// Input Output 2 Peripheral Select
+#define AUX_AIODIO_O_IO2PSEL 0x00000028
+
+// Input Output 3 Peripheral Select
+#define AUX_AIODIO_O_IO3PSEL 0x0000002C
+
+// Input Output 4 Peripheral Select
+#define AUX_AIODIO_O_IO4PSEL 0x00000030
+
+// Input Output 5 Peripheral Select
+#define AUX_AIODIO_O_IO5PSEL 0x00000034
+
+// Input Output 6 Peripheral Select
+#define AUX_AIODIO_O_IO6PSEL 0x00000038
+
+// Input Output 7 Peripheral Select
+#define AUX_AIODIO_O_IO7PSEL 0x0000003C
+
+// Input Output Mode Low
+#define AUX_AIODIO_O_IOMODEL 0x00000040
+
+// Input Output Mode High
+#define AUX_AIODIO_O_IOMODEH 0x00000044
+
+//*****************************************************************************
+//
+// Register: AUX_AIODIO_O_IOMODE
+//
+//*****************************************************************************
+// Field: [15:14] IO7
+//
+// Selects mode for AUXIO[8i+7].
+// ENUMs:
+// OPEN_SOURCE Open-Source Mode:
+//
+// When IOPOE bit 7 is 0:
+// - If GPIODOUT bit 7 is 0:
+// AUXIO[8i+7] is tri-stated or pulled. This
+// depends on IOC:IOCFGn.PULL_CTL.
+// - If GPIODOUT bit 7 is 1:
+// AUXIO[8i+7] is driven high.
+//
+// When IOPOE bit 7 is 1:
+// - If signal selected by
+// IO7PSEL.SRC is 0: AUXIO[8i+7] is tri-stated or
+// pulled. This depends on IOC:IOCFGn.PULL_CTL.
+// - If signal selected by
+// IO7PSEL.SRC is 1: AUXIO[8i+7] is driven high.
+// OPEN_DRAIN Open-Drain Mode:
+//
+// When IOPOE bit 7 is 0:
+// - If GPIODOUT bit 7 is 0:
+// AUXIO[8i+7] is driven low.
+// - If GPIODOUT bit 7 is 1:
+// AUXIO[8i+7] is tri-stated or pulled. This
+// depends on IOC:IOCFGn.PULL_CTL.
+//
+// When IOPOE bit 7 is 1:
+// - If signal selected by
+// IO7PSEL.SRC is 0: AUXIO[8i+7] is driven low.
+// - If signal selected by
+// IO7PSEL.SRC is 1: AUXIO[8i+7] is tri-stated or
+// pulled. This depends on IOC:IOCFGn.PULL_CTL.
+// IN Input Mode:
+//
+// When GPIODIE bit 7 is 0:
+// AUXIO[8i+7] is enabled for analog signal
+// transfer.
+//
+// When GPIODIE bit 7 is 1:
+// AUXIO[8i+7] is enabled for digital input.
+// OUT Output Mode:
+//
+// When IOPOE bit 7 is 0:
+// GPIODOUT bit 7 drives AUXIO[8i+7].
+//
+// When IOPOE bit 7 is 1:
+// The signal selected by IO7PSEL.SRC drives
+// AUXIO[8i+7].
+#define AUX_AIODIO_IOMODE_IO7_W 2
+#define AUX_AIODIO_IOMODE_IO7_M 0x0000C000
+#define AUX_AIODIO_IOMODE_IO7_S 14
+#define AUX_AIODIO_IOMODE_IO7_OPEN_SOURCE 0x0000C000
+#define AUX_AIODIO_IOMODE_IO7_OPEN_DRAIN 0x00008000
+#define AUX_AIODIO_IOMODE_IO7_IN 0x00004000
+#define AUX_AIODIO_IOMODE_IO7_OUT 0x00000000
+
+// Field: [13:12] IO6
+//
+// Selects mode for AUXIO[8i+6].
+// ENUMs:
+// OPEN_SOURCE Open-Source Mode:
+//
+// When IOPOE bit 6 is 0:
+// - If GPIODOUT bit 6 is 0:
+// AUXIO[8i+6] is tri-stated or pulled. This
+// depends on IOC:IOCFGn.PULL_CTL.
+// - If GPIODOUT bit 6 is 1:
+// AUXIO[8i+6] is driven high.
+//
+// When IOPOE bit 6 is 1:
+// - If signal selected by
+// IO6PSEL.SRC is 0: AUXIO[8i+6] is tri-stated or
+// pulled. This depends on IOC:IOCFGn.PULL_CTL.
+// - If signal selected by
+// IO6PSEL.SRC is 1: AUXIO[8i+6] is driven high.
+// OPEN_DRAIN Open-Drain Mode:
+//
+// When IOPOE bit 6 is 0:
+// - If GPIODOUT bit 6 is 0:
+// AUXIO[8i+6] is driven low.
+// - If GPIODOUT bit 6 is 1:
+// AUXIO[8i+6] is tri-stated or pulled. This
+// depends on IOC:IOCFGn.PULL_CTL.
+//
+// When IOPOE bit 6 is 1:
+// - If signal selected by
+// IO6PSEL.SRC is 0: AUXIO[8i+6] is driven low.
+// - If signal selected by
+// IO6PSEL.SRC is 1: AUXIO[8i+6] is tri-stated or
+// pulled. This depends on IOC:IOCFGn.PULL_CTL.
+// IN Input Mode:
+//
+// When GPIODIE bit 6 is 0:
+// AUXIO[8i+6] is enabled for analog signal
+// transfer.
+//
+// When GPIODIE bit 6 is 1:
+// AUXIO[8i+6] is enabled for digital input.
+// OUT Output Mode:
+//
+// When IOPOE bit 6 is 0:
+// GPIODOUT bit 6 drives AUXIO[8i+6].
+//
+// When IOPOE bit 6 is 1:
+// The signal selected by IO6PSEL.SRC drives
+// AUXIO[8i+6].
+#define AUX_AIODIO_IOMODE_IO6_W 2
+#define AUX_AIODIO_IOMODE_IO6_M 0x00003000
+#define AUX_AIODIO_IOMODE_IO6_S 12
+#define AUX_AIODIO_IOMODE_IO6_OPEN_SOURCE 0x00003000
+#define AUX_AIODIO_IOMODE_IO6_OPEN_DRAIN 0x00002000
+#define AUX_AIODIO_IOMODE_IO6_IN 0x00001000
+#define AUX_AIODIO_IOMODE_IO6_OUT 0x00000000
+
+// Field: [11:10] IO5
+//
+// Selects mode for AUXIO[8i+5].
+// ENUMs:
+// OPEN_SOURCE Open-Source Mode:
+//
+// When IOPOE bit 5 is 0:
+// - If GPIODOUT bit 5 is 0:
+// AUXIO[8i+5] is tri-stated or pulled. This
+// depends on IOC:IOCFGn.PULL_CTL.
+// - If GPIODOUT bit 5 is 1:
+// AUXIO[8i+5] is driven high.
+//
+// When IOPOE bit 5 is 1:
+// - If signal selected by
+// IO5PSEL.SRC is 0: AUXIO[8i+5] is tri-stated or
+// pulled. This depends on IOC:IOCFGn.PULL_CTL.
+// - If signal selected by
+// IO5PSEL.SRC is 1: AUXIO[8i+5] is driven high.
+// OPEN_DRAIN Open-Drain Mode:
+//
+// When IOPOE bit 5 is 0:
+// - If GPIODOUT bit 5 is 0:
+// AUXIO[8i+5] is driven low.
+// - If GPIODOUT bit 5 is 1:
+// AUXIO[8i+5] is tri-stated or pulled. This
+// depends on IOC:IOCFGn.PULL_CTL.
+//
+// When IOPOE bit 5 is 1:
+// - If signal selected by
+// IO5PSEL.SRC is 0: AUXIO[8i+5] is driven low.
+// - If signal selected by
+// IO5PSEL.SRC is 1: AUXIO[8i+5] is tri-stated or
+// pulled. This depends on IOC:IOCFGn.PULL_CTL.
+// IN Input Mode:
+//
+// When GPIODIE bit 5 is 0:
+// AUXIO[8i+5] is enabled for analog signal
+// transfer.
+//
+// When GPIODIE bit 5 is 1:
+// AUXIO[8i+5] is enabled for digital input.
+// OUT Output Mode:
+//
+// When IOPOE bit 5 is 0:
+// GPIODOUT bit 5 drives AUXIO[8i+5].
+//
+// When IOPOE bit 5 is 1:
+// The signal selected by IO5PSEL.SRC drives
+// AUXIO[8i+5].
+#define AUX_AIODIO_IOMODE_IO5_W 2
+#define AUX_AIODIO_IOMODE_IO5_M 0x00000C00
+#define AUX_AIODIO_IOMODE_IO5_S 10
+#define AUX_AIODIO_IOMODE_IO5_OPEN_SOURCE 0x00000C00
+#define AUX_AIODIO_IOMODE_IO5_OPEN_DRAIN 0x00000800
+#define AUX_AIODIO_IOMODE_IO5_IN 0x00000400
+#define AUX_AIODIO_IOMODE_IO5_OUT 0x00000000
+
+// Field: [9:8] IO4
+//
+// Selects mode for AUXIO[8i+4].
+// ENUMs:
+// OPEN_SOURCE Open-Source Mode:
+//
+// When IOPOE bit 4 is 0:
+// - If GPIODOUT bit 4 is 0:
+// AUXIO[8i+4] is tri-stated or pulled. This
+// depends on IOC:IOCFGn.PULL_CTL.
+// - If GPIODOUT bit 4 is 1:
+// AUXIO[8i+4] is driven high.
+//
+// When IOPOE bit 4 is 1:
+// - If signal selected by
+// IO4PSEL.SRC is 0: AUXIO[8i+4] is tri-stated or
+// pulled. This depends on IOC:IOCFGn.PULL_CTL.
+// - If signal selected by
+// IO4PSEL.SRC is 1: AUXIO[8i+4] is driven high.
+// OPEN_DRAIN Open-Drain Mode:
+//
+// When IOPOE bit 4 is 0:
+// - If GPIODOUT bit 4 is 0:
+// AUXIO[8i+4] is driven low.
+// - If GPIODOUT bit 4 is 1:
+// AUXIO[8i+4] is tri-stated or pulled. This
+// depends on IOC:IOCFGn.PULL_CTL.
+//
+// When IOPOE bit 4 is 1:
+// - If signal selected by
+// IO4PSEL.SRC is 0: AUXIO[8i+4] is driven low.
+// - If signal selected by
+// IO4PSEL.SRC is 1: AUXIO[8i+4] is tri-stated or
+// pulled. This depends on IOC:IOCFGn.PULL_CTL.
+// IN Input Mode:
+//
+// When GPIODIE bit 4 is 0:
+// AUXIO[8i+4] is enabled for analog signal
+// transfer.
+//
+// When GPIODIE bit 4 is 1:
+// AUXIO[8i+4] is enabled for digital input.
+// OUT Output Mode:
+//
+// When IOPOE bit 4 is 0:
+// GPIODOUT bit 4 drives AUXIO[8i+4].
+//
+// When IOPOE bit 4 is 1:
+// The signal selected by IO4PSEL.SRC drives
+// AUXIO[8i+4].
+#define AUX_AIODIO_IOMODE_IO4_W 2
+#define AUX_AIODIO_IOMODE_IO4_M 0x00000300
+#define AUX_AIODIO_IOMODE_IO4_S 8
+#define AUX_AIODIO_IOMODE_IO4_OPEN_SOURCE 0x00000300
+#define AUX_AIODIO_IOMODE_IO4_OPEN_DRAIN 0x00000200
+#define AUX_AIODIO_IOMODE_IO4_IN 0x00000100
+#define AUX_AIODIO_IOMODE_IO4_OUT 0x00000000
+
+// Field: [7:6] IO3
+//
+// Selects mode for AUXIO[8i+3].
+// ENUMs:
+// OPEN_SOURCE Open-Source Mode:
+//
+// When IOPOE bit 3 is 0:
+// - If GPIODOUT bit 3 is 0:
+// AUXIO[8i+3] is tri-stated or pulled. This
+// depends on IOC:IOCFGn.PULL_CTL.
+// - If GPIODOUT bit 3 is 1:
+// AUXIO[8i+3] is driven high.
+//
+// When IOPOE bit 3 is 1:
+// - If signal selected by
+// IO3PSEL.SRC is 0: AUXIO[8i+3] is tri-stated or
+// pulled. This depends on IOC:IOCFGn.PULL_CTL.
+// - If signal selected by
+// IO3PSEL.SRC is 1: AUXIO[8i+3] is driven high.
+// OPEN_DRAIN Open-Drain Mode:
+//
+// When IOPOE bit 3 is 0:
+// - If GPIODOUT bit 3 is 0:
+// AUXIO[8i+3] is driven low.
+// - If GPIODOUT bit 3 is 1:
+// AUXIO[8i+3] is tri-stated or pulled. This
+// depends on IOC:IOCFGn.PULL_CTL.
+//
+// When IOPOE bit 3 is 1:
+// - If signal selected by
+// IO3PSEL.SRC is 0: AUXIO[8i+3] is driven low.
+// - If signal selected by
+// IO3PSEL.SRC is 1: AUXIO[8i+3] is tri-stated or
+// pulled. This depends on IOC:IOCFGn.PULL_CTL.
+// IN Input Mode:
+//
+// When GPIODIE bit 3 is 0:
+// AUXIO[8i+3] is enabled for analog signal
+// transfer.
+//
+// When GPIODIE bit 3 is 1:
+// AUXIO[8i+3] is enabled for digital input.
+// OUT Output Mode:
+//
+// When IOPOE bit 3 is 0:
+// GPIODOUT bit 3 drives AUXIO[8i+3].
+//
+// When IOPOE bit 3 is 1:
+// The signal selected by IO3PSEL.SRC drives
+// AUXIO[8i+3].
+#define AUX_AIODIO_IOMODE_IO3_W 2
+#define AUX_AIODIO_IOMODE_IO3_M 0x000000C0
+#define AUX_AIODIO_IOMODE_IO3_S 6
+#define AUX_AIODIO_IOMODE_IO3_OPEN_SOURCE 0x000000C0
+#define AUX_AIODIO_IOMODE_IO3_OPEN_DRAIN 0x00000080
+#define AUX_AIODIO_IOMODE_IO3_IN 0x00000040
+#define AUX_AIODIO_IOMODE_IO3_OUT 0x00000000
+
+// Field: [5:4] IO2
+//
+// Select mode for AUXIO[8i+2].
+// ENUMs:
+// OPEN_SOURCE Open-Source Mode:
+//
+// When IOPOE bit 2 is 0:
+// - If GPIODOUT bit 2 is 0:
+// AUXIO[8i+2] is tri-stated or pulled. This
+// depends on IOC:IOCFGn.PULL_CTL.
+// - If GPIODOUT bit 2 is 1:
+// AUXIO[8i+2] is driven high.
+//
+// When IOPOE bit 2 is 1:
+// - If signal selected by
+// IO2PSEL.SRC is 0: AUXIO[8i+2] is tri-stated or
+// pulled. This depends on IOC:IOCFGn.PULL_CTL.
+// - If signal selected by
+// IO2PSEL.SRC is 1: AUXIO[8i+2] is driven high.
+// OPEN_DRAIN Open-Drain Mode:
+//
+// When IOPOE bit 2 is 0:
+// - If GPIODOUT bit 2 is 0:
+// AUXIO[8i+2] is driven low.
+// - If GPIODOUT bit 2 is 1:
+// AUXIO[8i+2] is tri-stated or pulled. This
+// depends on IOC:IOCFGn.PULL_CTL.
+//
+// When IOPOE bit 2 is 1:
+// - If signal selected by
+// IO2PSEL.SRC is 0: AUXIO[8i+2] is driven low.
+// - If signal selected by
+// IO2PSEL.SRC is 1: AUXIO[8i+2] is tri-stated or
+// pulled. This depends on IOC:IOCFGn.PULL_CTL.
+// IN Input Mode:
+//
+// When GPIODIE bit 2 is 0:
+// AUXIO[8i+2] is enabled for analog signal
+// transfer.
+//
+// When GPIODIE bit 2 is 1:
+// AUXIO[8i+2] is enabled for digital input.
+// OUT Output Mode:
+//
+// When IOPOE bit 2 is 0:
+// GPIODOUT bit 2 drives AUXIO[8i+2].
+//
+// When IOPOE bit 2 is 1:
+// The signal selected by IO2PSEL.SRC drives
+// AUXIO[8i+2].
+#define AUX_AIODIO_IOMODE_IO2_W 2
+#define AUX_AIODIO_IOMODE_IO2_M 0x00000030
+#define AUX_AIODIO_IOMODE_IO2_S 4
+#define AUX_AIODIO_IOMODE_IO2_OPEN_SOURCE 0x00000030
+#define AUX_AIODIO_IOMODE_IO2_OPEN_DRAIN 0x00000020
+#define AUX_AIODIO_IOMODE_IO2_IN 0x00000010
+#define AUX_AIODIO_IOMODE_IO2_OUT 0x00000000
+
+// Field: [3:2] IO1
+//
+// Select mode for AUXIO[8i+1].
+// ENUMs:
+// OPEN_SOURCE Open-Source Mode:
+//
+// When IOPOE bit 1 is 0:
+// - If GPIODOUT bit 1 is 0:
+// AUXIO[8i+1] is tri-stated or pulled. This
+// depends on IOC:IOCFGn.PULL_CTL.
+// - If GPIODOUT bit 1 is 1:
+// AUXIO[8i+1] is driven high.
+//
+// When IOPOE bit 1 is 1:
+// - If signal selected by
+// IO1PSEL.SRC is 0: AUXIO[8i+1] is tri-stated or
+// pulled. This depends on IOC:IOCFGn.PULL_CTL.
+// - If signal selected by
+// IO1PSEL.SRC is 1: AUXIO[8i+1] is driven high.
+// OPEN_DRAIN Open-Drain Mode:
+//
+// When IOPOE bit 1 is 0:
+// - If GPIODOUT bit 1 is 0:
+// AUXIO[8i+1] is driven low.
+// - If GPIODOUT bit 1 is 1:
+// AUXIO[8i+1] is tri-stated or pulled. This
+// depends on IOC:IOCFGn.PULL_CTL.
+//
+// When IOPOE bit 1 is 1:
+// - If signal selected by
+// IO1PSEL.SRC is 0: AUXIO[8i+1] is driven low.
+// - If signal selected by
+// IO1PSEL.SRC is 1: AUXIO[8i+1] is tri-stated or
+// pulled. This depends on IOC:IOCFGn.PULL_CTL.
+// IN Input Mode:
+//
+// When GPIODIE bit 1 is 0:
+// AUXIO[8i+1] is enabled for analog signal
+// transfer.
+//
+// When GPIODIE bit 1 is 1:
+// AUXIO[8i+1] is enabled for digital input.
+// OUT Output Mode:
+//
+// When IOPOE bit 1 is 0:
+// GPIODOUT bit 1 drives AUXIO[8i+1].
+//
+// When IOPOE bit 1 is 1:
+// The signal selected by IO1PSEL.SRC drives
+// AUXIO[8i+1].
+#define AUX_AIODIO_IOMODE_IO1_W 2
+#define AUX_AIODIO_IOMODE_IO1_M 0x0000000C
+#define AUX_AIODIO_IOMODE_IO1_S 2
+#define AUX_AIODIO_IOMODE_IO1_OPEN_SOURCE 0x0000000C
+#define AUX_AIODIO_IOMODE_IO1_OPEN_DRAIN 0x00000008
+#define AUX_AIODIO_IOMODE_IO1_IN 0x00000004
+#define AUX_AIODIO_IOMODE_IO1_OUT 0x00000000
+
+// Field: [1:0] IO0
+//
+// Select mode for AUXIO[8i+0].
+// ENUMs:
+// OPEN_SOURCE Open-Source Mode:
+//
+// When IOPOE bit 0 is 0:
+// - If GPIODOUT bit 0 is 0:
+// AUXIO[8i+0] is tri-stated or pulled. This
+// depends on IOC:IOCFGn.PULL_CTL.
+// - If GPIODOUT bit 0 is 1:
+// AUXIO[8i+0] is driven high.
+//
+// When IOPOE bit 0 is 1:
+// - If signal selected by
+// IO0PSEL.SRC is 0: AUXIO[8i+0] is tri-stated or
+// pulled. This depends on IOC:IOCFGn.PULL_CTL.
+// - If signal selected by
+// IO0PSEL.SRC is 1: AUXIO[8i+0] is driven high.
+// OPEN_DRAIN Open-Drain Mode:
+//
+// When IOPOE bit 0 is 0:
+// - If GPIODOUT bit 0 is 0:
+// AUXIO[8i+0] is driven low.
+// - If GPIODOUT bit 0 is 1:
+// AUXIO[8i+0] is tri-stated or pulled. This
+// depends on IOC:IOCFGn.PULL_CTL.
+//
+// When IOPOE bit 0 is 1:
+// - If signal selected by
+// IO0PSEL.SRC is 0: AUXIO[8i+0] is driven low.
+// - If signal selected by
+// IO0PSEL.SRC is 1: AUXIO[8i+0] is tri-stated or
+// pulled. This depends on IOC:IOCFGn.PULL_CTL.
+// IN Input Mode:
+//
+// When GPIODIE bit 0 is 0:
+// AUXIO[8i+0] is enabled for analog signal
+// transfer.
+//
+// When GPIODIE bit 0 is 1:
+// AUXIO[8i+0] is enabled for digital input.
+// OUT Output Mode:
+//
+// When IOPOE bit 0 is 0:
+// GPIODOUT bit 0 drives AUXIO[8i+0].
+//
+// When IOPOE bit 0 is 1:
+// The signal selected by IO0PSEL.SRC drives
+// AUXIO[8i+0].
+#define AUX_AIODIO_IOMODE_IO0_W 2
+#define AUX_AIODIO_IOMODE_IO0_M 0x00000003
+#define AUX_AIODIO_IOMODE_IO0_S 0
+#define AUX_AIODIO_IOMODE_IO0_OPEN_SOURCE 0x00000003
+#define AUX_AIODIO_IOMODE_IO0_OPEN_DRAIN 0x00000002
+#define AUX_AIODIO_IOMODE_IO0_IN 0x00000001
+#define AUX_AIODIO_IOMODE_IO0_OUT 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_AIODIO_O_GPIODIE
+//
+//*****************************************************************************
+// Field: [7:0] IO7_0
+//
+// Write 1 to bit index n in this bit vector to enable digital input buffer for
+// AUXIO[8i+n].
+// Write 0 to bit index n in this bit vector to disable digital input buffer
+// for AUXIO[8i+n].
+//
+// You must enable the digital input buffer for AUXIO[8i+n] to read the pin
+// value in GPIODIN.
+// You must disable the digital input buffer for analog input or pins that
+// float to avoid current leakage.
+#define AUX_AIODIO_GPIODIE_IO7_0_W 8
+#define AUX_AIODIO_GPIODIE_IO7_0_M 0x000000FF
+#define AUX_AIODIO_GPIODIE_IO7_0_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_AIODIO_O_IOPOE
+//
+//*****************************************************************************
+// Field: [7:0] IO7_0
+//
+// Write 1 to bit index n in this bit vector to configure AUXIO[8i+n] to be
+// driven from source given in [IOnPSEL.*].
+// Write 0 to bit index n in this bit vector to configure AUXIO[8i+n] to be
+// driven from bit n in GPIODOUT.
+#define AUX_AIODIO_IOPOE_IO7_0_W 8
+#define AUX_AIODIO_IOPOE_IO7_0_M 0x000000FF
+#define AUX_AIODIO_IOPOE_IO7_0_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_AIODIO_O_GPIODOUT
+//
+//*****************************************************************************
+// Field: [7:0] IO7_0
+//
+// Write 1 to bit index n in this bit vector to set AUXIO[8i+n].
+// Write 0 to bit index n in this bit vector to clear AUXIO[8i+n].
+//
+// You must clear bit n in IOPOE to connect bit n in this bit vector to
+// AUXIO[8i+n].
+#define AUX_AIODIO_GPIODOUT_IO7_0_W 8
+#define AUX_AIODIO_GPIODOUT_IO7_0_M 0x000000FF
+#define AUX_AIODIO_GPIODOUT_IO7_0_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_AIODIO_O_GPIODIN
+//
+//*****************************************************************************
+// Field: [7:0] IO7_0
+//
+// Bit n in this bit vector contains the value for AUXIO[8i+n] when GPIODIE bit
+// n is set. Otherwise, bit n is read as 0.
+#define AUX_AIODIO_GPIODIN_IO7_0_W 8
+#define AUX_AIODIO_GPIODIN_IO7_0_M 0x000000FF
+#define AUX_AIODIO_GPIODIN_IO7_0_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_AIODIO_O_GPIODOUTSET
+//
+//*****************************************************************************
+// Field: [7:0] IO7_0
+//
+// Write 1 to bit index n in this bit vector to set GPIODOUT bit n.
+//
+// Read value is 0.
+#define AUX_AIODIO_GPIODOUTSET_IO7_0_W 8
+#define AUX_AIODIO_GPIODOUTSET_IO7_0_M 0x000000FF
+#define AUX_AIODIO_GPIODOUTSET_IO7_0_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_AIODIO_O_GPIODOUTCLR
+//
+//*****************************************************************************
+// Field: [7:0] IO7_0
+//
+// Write 1 to bit index n in this bit vector to clear GPIODOUT bit n.
+//
+// Read value is 0.
+#define AUX_AIODIO_GPIODOUTCLR_IO7_0_W 8
+#define AUX_AIODIO_GPIODOUTCLR_IO7_0_M 0x000000FF
+#define AUX_AIODIO_GPIODOUTCLR_IO7_0_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_AIODIO_O_GPIODOUTTGL
+//
+//*****************************************************************************
+// Field: [7:0] IO7_0
+//
+// Write 1 to bit index n in this bit vector to toggle GPIODOUT bit n.
+//
+// Read value is 0.
+#define AUX_AIODIO_GPIODOUTTGL_IO7_0_W 8
+#define AUX_AIODIO_GPIODOUTTGL_IO7_0_M 0x000000FF
+#define AUX_AIODIO_GPIODOUTTGL_IO7_0_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_AIODIO_O_IO0PSEL
+//
+//*****************************************************************************
+// Field: [2:0] SRC
+//
+// Select a peripheral signal that connects to AUXIO[8i+0] when IOPOE bit 0 is
+// set.
+// ENUMs:
+// AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE.
+// AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3.
+// AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2.
+// AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1.
+// AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0.
+// AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI.
+// AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK.
+// AUX_EV_OBS Peripheral output mux selects event selected by
+// AUX_EVCTL:EVOBSCFG
+#define AUX_AIODIO_IO0PSEL_SRC_W 3
+#define AUX_AIODIO_IO0PSEL_SRC_M 0x00000007
+#define AUX_AIODIO_IO0PSEL_SRC_S 0
+#define AUX_AIODIO_IO0PSEL_SRC_AUX_TIMER2_PULSE 0x00000007
+#define AUX_AIODIO_IO0PSEL_SRC_AUX_TIMER2_EV3 0x00000006
+#define AUX_AIODIO_IO0PSEL_SRC_AUX_TIMER2_EV2 0x00000005
+#define AUX_AIODIO_IO0PSEL_SRC_AUX_TIMER2_EV1 0x00000004
+#define AUX_AIODIO_IO0PSEL_SRC_AUX_TIMER2_EV0 0x00000003
+#define AUX_AIODIO_IO0PSEL_SRC_AUX_SPIM_MOSI 0x00000002
+#define AUX_AIODIO_IO0PSEL_SRC_AUX_SPIM_SCLK 0x00000001
+#define AUX_AIODIO_IO0PSEL_SRC_AUX_EV_OBS 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_AIODIO_O_IO1PSEL
+//
+//*****************************************************************************
+// Field: [2:0] SRC
+//
+// Select a peripheral signal that connects to AUXIO[8i+1] when IOPOE bit 1 is
+// set.
+// ENUMs:
+// AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE.
+// AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3.
+// AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2.
+// AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1.
+// AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0.
+// AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI.
+// AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK.
+// AUX_EV_OBS Peripheral output mux selects event selected by
+// AUX_EVCTL:EVOBSCFG
+#define AUX_AIODIO_IO1PSEL_SRC_W 3
+#define AUX_AIODIO_IO1PSEL_SRC_M 0x00000007
+#define AUX_AIODIO_IO1PSEL_SRC_S 0
+#define AUX_AIODIO_IO1PSEL_SRC_AUX_TIMER2_PULSE 0x00000007
+#define AUX_AIODIO_IO1PSEL_SRC_AUX_TIMER2_EV3 0x00000006
+#define AUX_AIODIO_IO1PSEL_SRC_AUX_TIMER2_EV2 0x00000005
+#define AUX_AIODIO_IO1PSEL_SRC_AUX_TIMER2_EV1 0x00000004
+#define AUX_AIODIO_IO1PSEL_SRC_AUX_TIMER2_EV0 0x00000003
+#define AUX_AIODIO_IO1PSEL_SRC_AUX_SPIM_MOSI 0x00000002
+#define AUX_AIODIO_IO1PSEL_SRC_AUX_SPIM_SCLK 0x00000001
+#define AUX_AIODIO_IO1PSEL_SRC_AUX_EV_OBS 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_AIODIO_O_IO2PSEL
+//
+//*****************************************************************************
+// Field: [2:0] SRC
+//
+// Select a peripheral signal that connects to AUXIO[8i+2] when IOPOE bit 2 is
+// set.
+// ENUMs:
+// AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE.
+// AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3.
+// AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2.
+// AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1.
+// AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0.
+// AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI.
+// AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK.
+// AUX_EV_OBS Peripheral output mux selects event selected by
+// AUX_EVCTL:EVOBSCFG
+#define AUX_AIODIO_IO2PSEL_SRC_W 3
+#define AUX_AIODIO_IO2PSEL_SRC_M 0x00000007
+#define AUX_AIODIO_IO2PSEL_SRC_S 0
+#define AUX_AIODIO_IO2PSEL_SRC_AUX_TIMER2_PULSE 0x00000007
+#define AUX_AIODIO_IO2PSEL_SRC_AUX_TIMER2_EV3 0x00000006
+#define AUX_AIODIO_IO2PSEL_SRC_AUX_TIMER2_EV2 0x00000005
+#define AUX_AIODIO_IO2PSEL_SRC_AUX_TIMER2_EV1 0x00000004
+#define AUX_AIODIO_IO2PSEL_SRC_AUX_TIMER2_EV0 0x00000003
+#define AUX_AIODIO_IO2PSEL_SRC_AUX_SPIM_MOSI 0x00000002
+#define AUX_AIODIO_IO2PSEL_SRC_AUX_SPIM_SCLK 0x00000001
+#define AUX_AIODIO_IO2PSEL_SRC_AUX_EV_OBS 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_AIODIO_O_IO3PSEL
+//
+//*****************************************************************************
+// Field: [2:0] SRC
+//
+// Select a peripheral signal that connects to AUXIO[8i+3] when IOPOE bit 3 is
+// set.
+// ENUMs:
+// AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE.
+// AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3.
+// AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2.
+// AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1.
+// AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0.
+// AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI.
+// AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK.
+// AUX_EV_OBS Peripheral output mux selects event selected by
+// AUX_EVCTL:EVOBSCFG
+#define AUX_AIODIO_IO3PSEL_SRC_W 3
+#define AUX_AIODIO_IO3PSEL_SRC_M 0x00000007
+#define AUX_AIODIO_IO3PSEL_SRC_S 0
+#define AUX_AIODIO_IO3PSEL_SRC_AUX_TIMER2_PULSE 0x00000007
+#define AUX_AIODIO_IO3PSEL_SRC_AUX_TIMER2_EV3 0x00000006
+#define AUX_AIODIO_IO3PSEL_SRC_AUX_TIMER2_EV2 0x00000005
+#define AUX_AIODIO_IO3PSEL_SRC_AUX_TIMER2_EV1 0x00000004
+#define AUX_AIODIO_IO3PSEL_SRC_AUX_TIMER2_EV0 0x00000003
+#define AUX_AIODIO_IO3PSEL_SRC_AUX_SPIM_MOSI 0x00000002
+#define AUX_AIODIO_IO3PSEL_SRC_AUX_SPIM_SCLK 0x00000001
+#define AUX_AIODIO_IO3PSEL_SRC_AUX_EV_OBS 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_AIODIO_O_IO4PSEL
+//
+//*****************************************************************************
+// Field: [2:0] SRC
+//
+// Select a peripheral signal that connects to AUXIO[8i+4] when IOPOE bit 4 is
+// set.
+// ENUMs:
+// AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE.
+// AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3.
+// AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2.
+// AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1.
+// AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0.
+// AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI.
+// AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK.
+// AUX_EV_OBS Peripheral output mux selects event selected by
+// AUX_EVCTL:EVOBSCFG
+#define AUX_AIODIO_IO4PSEL_SRC_W 3
+#define AUX_AIODIO_IO4PSEL_SRC_M 0x00000007
+#define AUX_AIODIO_IO4PSEL_SRC_S 0
+#define AUX_AIODIO_IO4PSEL_SRC_AUX_TIMER2_PULSE 0x00000007
+#define AUX_AIODIO_IO4PSEL_SRC_AUX_TIMER2_EV3 0x00000006
+#define AUX_AIODIO_IO4PSEL_SRC_AUX_TIMER2_EV2 0x00000005
+#define AUX_AIODIO_IO4PSEL_SRC_AUX_TIMER2_EV1 0x00000004
+#define AUX_AIODIO_IO4PSEL_SRC_AUX_TIMER2_EV0 0x00000003
+#define AUX_AIODIO_IO4PSEL_SRC_AUX_SPIM_MOSI 0x00000002
+#define AUX_AIODIO_IO4PSEL_SRC_AUX_SPIM_SCLK 0x00000001
+#define AUX_AIODIO_IO4PSEL_SRC_AUX_EV_OBS 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_AIODIO_O_IO5PSEL
+//
+//*****************************************************************************
+// Field: [2:0] SRC
+//
+// Select a peripheral signal that connects to AUXIO[8i+5] when IOPOE bit 5 is
+// set.
+// ENUMs:
+// AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE.
+// AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3.
+// AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2.
+// AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1.
+// AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0.
+// AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI.
+// AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK.
+// AUX_EV_OBS Peripheral output mux selects event selected by
+// AUX_EVCTL:EVOBSCFG
+#define AUX_AIODIO_IO5PSEL_SRC_W 3
+#define AUX_AIODIO_IO5PSEL_SRC_M 0x00000007
+#define AUX_AIODIO_IO5PSEL_SRC_S 0
+#define AUX_AIODIO_IO5PSEL_SRC_AUX_TIMER2_PULSE 0x00000007
+#define AUX_AIODIO_IO5PSEL_SRC_AUX_TIMER2_EV3 0x00000006
+#define AUX_AIODIO_IO5PSEL_SRC_AUX_TIMER2_EV2 0x00000005
+#define AUX_AIODIO_IO5PSEL_SRC_AUX_TIMER2_EV1 0x00000004
+#define AUX_AIODIO_IO5PSEL_SRC_AUX_TIMER2_EV0 0x00000003
+#define AUX_AIODIO_IO5PSEL_SRC_AUX_SPIM_MOSI 0x00000002
+#define AUX_AIODIO_IO5PSEL_SRC_AUX_SPIM_SCLK 0x00000001
+#define AUX_AIODIO_IO5PSEL_SRC_AUX_EV_OBS 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_AIODIO_O_IO6PSEL
+//
+//*****************************************************************************
+// Field: [2:0] SRC
+//
+// Select a peripheral signal that connects to AUXIO[8i+6] when IOPOE bit 6 is
+// set.
+// ENUMs:
+// AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE.
+// AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3.
+// AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2.
+// AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1.
+// AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0.
+// AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI.
+// AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK.
+// AUX_EV_OBS Peripheral output mux selects event selected by
+// AUX_EVCTL:EVOBSCFG
+#define AUX_AIODIO_IO6PSEL_SRC_W 3
+#define AUX_AIODIO_IO6PSEL_SRC_M 0x00000007
+#define AUX_AIODIO_IO6PSEL_SRC_S 0
+#define AUX_AIODIO_IO6PSEL_SRC_AUX_TIMER2_PULSE 0x00000007
+#define AUX_AIODIO_IO6PSEL_SRC_AUX_TIMER2_EV3 0x00000006
+#define AUX_AIODIO_IO6PSEL_SRC_AUX_TIMER2_EV2 0x00000005
+#define AUX_AIODIO_IO6PSEL_SRC_AUX_TIMER2_EV1 0x00000004
+#define AUX_AIODIO_IO6PSEL_SRC_AUX_TIMER2_EV0 0x00000003
+#define AUX_AIODIO_IO6PSEL_SRC_AUX_SPIM_MOSI 0x00000002
+#define AUX_AIODIO_IO6PSEL_SRC_AUX_SPIM_SCLK 0x00000001
+#define AUX_AIODIO_IO6PSEL_SRC_AUX_EV_OBS 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_AIODIO_O_IO7PSEL
+//
+//*****************************************************************************
+// Field: [2:0] SRC
+//
+// Select a peripheral signal that connects to AUXIO[8i+7] when IOPOE bit 7 is
+// set.
+// ENUMs:
+// AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE.
+// AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3.
+// AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2.
+// AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1.
+// AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version
+// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0.
+// AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI.
+// AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK.
+// AUX_EV_OBS Peripheral output mux selects event selected by
+// AUX_EVCTL:EVOBSCFG
+#define AUX_AIODIO_IO7PSEL_SRC_W 3
+#define AUX_AIODIO_IO7PSEL_SRC_M 0x00000007
+#define AUX_AIODIO_IO7PSEL_SRC_S 0
+#define AUX_AIODIO_IO7PSEL_SRC_AUX_TIMER2_PULSE 0x00000007
+#define AUX_AIODIO_IO7PSEL_SRC_AUX_TIMER2_EV3 0x00000006
+#define AUX_AIODIO_IO7PSEL_SRC_AUX_TIMER2_EV2 0x00000005
+#define AUX_AIODIO_IO7PSEL_SRC_AUX_TIMER2_EV1 0x00000004
+#define AUX_AIODIO_IO7PSEL_SRC_AUX_TIMER2_EV0 0x00000003
+#define AUX_AIODIO_IO7PSEL_SRC_AUX_SPIM_MOSI 0x00000002
+#define AUX_AIODIO_IO7PSEL_SRC_AUX_SPIM_SCLK 0x00000001
+#define AUX_AIODIO_IO7PSEL_SRC_AUX_EV_OBS 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_AIODIO_O_IOMODEL
+//
+//*****************************************************************************
+// Field: [7:6] IO3
+//
+// See IOMODE.IO3.
+#define AUX_AIODIO_IOMODEL_IO3_W 2
+#define AUX_AIODIO_IOMODEL_IO3_M 0x000000C0
+#define AUX_AIODIO_IOMODEL_IO3_S 6
+
+// Field: [5:4] IO2
+//
+// See IOMODE.IO2.
+#define AUX_AIODIO_IOMODEL_IO2_W 2
+#define AUX_AIODIO_IOMODEL_IO2_M 0x00000030
+#define AUX_AIODIO_IOMODEL_IO2_S 4
+
+// Field: [3:2] IO1
+//
+// See IOMODE.IO1.
+#define AUX_AIODIO_IOMODEL_IO1_W 2
+#define AUX_AIODIO_IOMODEL_IO1_M 0x0000000C
+#define AUX_AIODIO_IOMODEL_IO1_S 2
+
+// Field: [1:0] IO0
+//
+// See IOMODE.IO0.
+#define AUX_AIODIO_IOMODEL_IO0_W 2
+#define AUX_AIODIO_IOMODEL_IO0_M 0x00000003
+#define AUX_AIODIO_IOMODEL_IO0_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_AIODIO_O_IOMODEH
+//
+//*****************************************************************************
+// Field: [7:6] IO7
+//
+// See IOMODE.IO7.
+#define AUX_AIODIO_IOMODEH_IO7_W 2
+#define AUX_AIODIO_IOMODEH_IO7_M 0x000000C0
+#define AUX_AIODIO_IOMODEH_IO7_S 6
+
+// Field: [5:4] IO6
+//
+// See IOMODE.IO6.
+#define AUX_AIODIO_IOMODEH_IO6_W 2
+#define AUX_AIODIO_IOMODEH_IO6_M 0x00000030
+#define AUX_AIODIO_IOMODEH_IO6_S 4
+
+// Field: [3:2] IO5
+//
+// See IOMODE.IO5.
+#define AUX_AIODIO_IOMODEH_IO5_W 2
+#define AUX_AIODIO_IOMODEH_IO5_M 0x0000000C
+#define AUX_AIODIO_IOMODEH_IO5_S 2
+
+// Field: [1:0] IO4
+//
+// See IOMODE.IO4.
+#define AUX_AIODIO_IOMODEH_IO4_W 2
+#define AUX_AIODIO_IOMODEH_IO4_M 0x00000003
+#define AUX_AIODIO_IOMODEH_IO4_S 0
+
+
+#endif // __AUX_AIODIO__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_anaif.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_anaif.h
new file mode 100644
index 0000000..8b08db3
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_anaif.h
@@ -0,0 +1,633 @@
+/******************************************************************************
+* Filename: hw_aux_anaif_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_AUX_ANAIF_H__
+#define __HW_AUX_ANAIF_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// AUX_ANAIF component
+//
+//*****************************************************************************
+// ADC Control
+#define AUX_ANAIF_O_ADCCTL 0x00000010
+
+// ADC FIFO Status
+#define AUX_ANAIF_O_ADCFIFOSTAT 0x00000014
+
+// ADC FIFO
+#define AUX_ANAIF_O_ADCFIFO 0x00000018
+
+// ADC Trigger
+#define AUX_ANAIF_O_ADCTRIG 0x0000001C
+
+// Current Source Control
+#define AUX_ANAIF_O_ISRCCTL 0x00000020
+
+// DAC Control
+#define AUX_ANAIF_O_DACCTL 0x00000030
+
+// Low Power Mode Bias Control
+#define AUX_ANAIF_O_LPMBIASCTL 0x00000034
+
+// DAC Sample Control
+#define AUX_ANAIF_O_DACSMPLCTL 0x00000038
+
+// DAC Sample Configuration 0
+#define AUX_ANAIF_O_DACSMPLCFG0 0x0000003C
+
+// DAC Sample Configuration 1
+#define AUX_ANAIF_O_DACSMPLCFG1 0x00000040
+
+// DAC Value
+#define AUX_ANAIF_O_DACVALUE 0x00000044
+
+// DAC Status
+#define AUX_ANAIF_O_DACSTAT 0x00000048
+
+//*****************************************************************************
+//
+// Register: AUX_ANAIF_O_ADCCTL
+//
+//*****************************************************************************
+// Field: [14] START_POL
+//
+// Select active polarity for START_SRC event.
+// ENUMs:
+// FALL Set ADC trigger on falling edge of event source.
+// RISE Set ADC trigger on rising edge of event source.
+#define AUX_ANAIF_ADCCTL_START_POL 0x00004000
+#define AUX_ANAIF_ADCCTL_START_POL_BITN 14
+#define AUX_ANAIF_ADCCTL_START_POL_M 0x00004000
+#define AUX_ANAIF_ADCCTL_START_POL_S 14
+#define AUX_ANAIF_ADCCTL_START_POL_FALL 0x00004000
+#define AUX_ANAIF_ADCCTL_START_POL_RISE 0x00000000
+
+// Field: [13:8] START_SRC
+//
+// Select ADC trigger event source from the asynchronous AUX event bus.
+//
+// Set START_SRC to NO_EVENT if you want to trigger the ADC manually through
+// ADCTRIG.START.
+//
+// If you write a non-enumerated value the behavior is identical to NO_EVENT.
+// The written value is returned when read.
+// ENUMs:
+// NO_EVENT No event.
+// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE
+// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N
+// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE
+// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV
+// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV
+// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE
+// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3
+// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2
+// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1
+// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0
+// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB
+// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA
+// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV
+// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF
+// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE
+// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE
+// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN
+// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF
+// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD
+// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD
+// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ
+// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY
+// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2
+// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV
+// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31
+// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30
+// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29
+// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28
+// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27
+// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26
+// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25
+// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24
+// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23
+// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22
+// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21
+// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20
+// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19
+// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18
+// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17
+// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16
+// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15
+// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14
+// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13
+// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12
+// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11
+// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10
+// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9
+// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8
+// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7
+// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6
+// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5
+// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4
+// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3
+// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2
+// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1
+// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0
+#define AUX_ANAIF_ADCCTL_START_SRC_W 6
+#define AUX_ANAIF_ADCCTL_START_SRC_M 0x00003F00
+#define AUX_ANAIF_ADCCTL_START_SRC_S 8
+#define AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT 0x00003F00
+#define AUX_ANAIF_ADCCTL_START_SRC_AUX_SMPH_AUTOTAKE_DONE 0x00003D00
+#define AUX_ANAIF_ADCCTL_START_SRC_AUX_ISRC_RESET_N 0x00003800
+#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TDC_DONE 0x00003700
+#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER0_EV 0x00003600
+#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER1_EV 0x00003500
+#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER2_PULSE 0x00003400
+#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER2_EV3 0x00003300
+#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER2_EV2 0x00003200
+#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER2_EV1 0x00003100
+#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER2_EV0 0x00003000
+#define AUX_ANAIF_ADCCTL_START_SRC_AUX_COMPB 0x00002F00
+#define AUX_ANAIF_ADCCTL_START_SRC_AUX_COMPA 0x00002E00
+#define AUX_ANAIF_ADCCTL_START_SRC_MCU_EV 0x00002B00
+#define AUX_ANAIF_ADCCTL_START_SRC_ACLK_REF 0x00002A00
+#define AUX_ANAIF_ADCCTL_START_SRC_VDDR_RECHARGE 0x00002900
+#define AUX_ANAIF_ADCCTL_START_SRC_MCU_ACTIVE 0x00002800
+#define AUX_ANAIF_ADCCTL_START_SRC_PWR_DWN 0x00002700
+#define AUX_ANAIF_ADCCTL_START_SRC_SCLK_LF 0x00002600
+#define AUX_ANAIF_ADCCTL_START_SRC_AON_BATMON_TEMP_UPD 0x00002500
+#define AUX_ANAIF_ADCCTL_START_SRC_AON_BATMON_BAT_UPD 0x00002400
+#define AUX_ANAIF_ADCCTL_START_SRC_AON_RTC_4KHZ 0x00002300
+#define AUX_ANAIF_ADCCTL_START_SRC_AON_RTC_CH2_DLY 0x00002200
+#define AUX_ANAIF_ADCCTL_START_SRC_AON_RTC_CH2 0x00002100
+#define AUX_ANAIF_ADCCTL_START_SRC_MANUAL_EV 0x00002000
+#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO31 0x00001F00
+#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO30 0x00001E00
+#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO29 0x00001D00
+#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO28 0x00001C00
+#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO27 0x00001B00
+#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO26 0x00001A00
+#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO25 0x00001900
+#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO24 0x00001800
+#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO23 0x00001700
+#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO22 0x00001600
+#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO21 0x00001500
+#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO20 0x00001400
+#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO19 0x00001300
+#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO18 0x00001200
+#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO17 0x00001100
+#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO16 0x00001000
+#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO15 0x00000F00
+#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO14 0x00000E00
+#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO13 0x00000D00
+#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO12 0x00000C00
+#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO11 0x00000B00
+#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO10 0x00000A00
+#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO9 0x00000900
+#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO8 0x00000800
+#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO7 0x00000700
+#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO6 0x00000600
+#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO5 0x00000500
+#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO4 0x00000400
+#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO3 0x00000300
+#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO2 0x00000200
+#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO1 0x00000100
+#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO0 0x00000000
+
+// Field: [1:0] CMD
+//
+// ADC interface command.
+//
+// Non-enumerated values are not supported. The written value is returned when
+// read.
+// ENUMs:
+// FLUSH Flush ADC FIFO.
+//
+// You must set CMD to EN or
+// DIS after flush.
+//
+// System CPU must wait two
+// clock cycles before it sets CMD to EN or DIS.
+// EN Enable ADC interface.
+// DIS Disable ADC interface.
+#define AUX_ANAIF_ADCCTL_CMD_W 2
+#define AUX_ANAIF_ADCCTL_CMD_M 0x00000003
+#define AUX_ANAIF_ADCCTL_CMD_S 0
+#define AUX_ANAIF_ADCCTL_CMD_FLUSH 0x00000003
+#define AUX_ANAIF_ADCCTL_CMD_EN 0x00000001
+#define AUX_ANAIF_ADCCTL_CMD_DIS 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_ANAIF_O_ADCFIFOSTAT
+//
+//*****************************************************************************
+// Field: [4] OVERFLOW
+//
+// FIFO overflow flag.
+//
+// 0: FIFO has not overflowed.
+// 1: FIFO has overflowed, this flag is sticky until you flush the FIFO.
+//
+// When the flag is set, the ADC FIFO write pointer is static. It is not
+// possible to add more samples to the ADC FIFO. Flush FIFO to clear the flag.
+#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW 0x00000010
+#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_BITN 4
+#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_M 0x00000010
+#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_S 4
+
+// Field: [3] UNDERFLOW
+//
+// FIFO underflow flag.
+//
+// 0: FIFO has not underflowed.
+// 1: FIFO has underflowed, this flag is sticky until you flush the FIFO.
+//
+// When the flag is set, the ADC FIFO read pointer is static. Read returns the
+// previous sample that was read. Flush FIFO to clear the flag.
+#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW 0x00000008
+#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_BITN 3
+#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_M 0x00000008
+#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_S 3
+
+// Field: [2] FULL
+//
+// FIFO full flag.
+//
+// 0: FIFO is not full, there is less than 4 samples in the FIFO.
+// 1: FIFO is full, there are 4 samples in the FIFO.
+//
+// When the flag is set, it is not possible to add more samples to the ADC
+// FIFO. An attempt to add samples sets the OVERFLOW flag.
+#define AUX_ANAIF_ADCFIFOSTAT_FULL 0x00000004
+#define AUX_ANAIF_ADCFIFOSTAT_FULL_BITN 2
+#define AUX_ANAIF_ADCFIFOSTAT_FULL_M 0x00000004
+#define AUX_ANAIF_ADCFIFOSTAT_FULL_S 2
+
+// Field: [1] ALMOST_FULL
+//
+// FIFO almost full flag.
+//
+// 0: There are less than 3 samples in the FIFO, or the FIFO is full. The FULL
+// flag is also asserted in the latter case.
+// 1: There are 3 samples in the FIFO, there is room for one more sample.
+#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL 0x00000002
+#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_BITN 1
+#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_M 0x00000002
+#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_S 1
+
+// Field: [0] EMPTY
+//
+// FIFO empty flag.
+//
+// 0: FIFO contains one or more samples.
+// 1: FIFO is empty.
+//
+// When the flag is set, read returns the previous sample that was read and
+// sets the UNDERFLOW flag.
+#define AUX_ANAIF_ADCFIFOSTAT_EMPTY 0x00000001
+#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_BITN 0
+#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_M 0x00000001
+#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_ANAIF_O_ADCFIFO
+//
+//*****************************************************************************
+// Field: [11:0] DATA
+//
+// FIFO data.
+//
+// Read:
+// Get oldest ADC sample from FIFO.
+//
+// Write:
+// Write dummy sample to FIFO. This is useful for code development when you do
+// not have real ADC samples.
+#define AUX_ANAIF_ADCFIFO_DATA_W 12
+#define AUX_ANAIF_ADCFIFO_DATA_M 0x00000FFF
+#define AUX_ANAIF_ADCFIFO_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_ANAIF_O_ADCTRIG
+//
+//*****************************************************************************
+// Field: [0] START
+//
+// Manual ADC trigger.
+//
+// 0: No effect.
+// 1: Single ADC trigger.
+//
+// To manually trigger the ADC, you must set ADCCTL.START_SRC to NO_EVENT to
+// avoid conflict with event-driven ADC trigger.
+#define AUX_ANAIF_ADCTRIG_START 0x00000001
+#define AUX_ANAIF_ADCTRIG_START_BITN 0
+#define AUX_ANAIF_ADCTRIG_START_M 0x00000001
+#define AUX_ANAIF_ADCTRIG_START_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_ANAIF_O_ISRCCTL
+//
+//*****************************************************************************
+// Field: [0] RESET_N
+//
+// ISRC reset control.
+//
+// 0: ISRC drives 0 uA.
+// 1: ISRC drives current ADI_4_AUX:ISRC.TRIM to COMPA_IN.
+#define AUX_ANAIF_ISRCCTL_RESET_N 0x00000001
+#define AUX_ANAIF_ISRCCTL_RESET_N_BITN 0
+#define AUX_ANAIF_ISRCCTL_RESET_N_M 0x00000001
+#define AUX_ANAIF_ISRCCTL_RESET_N_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_ANAIF_O_DACCTL
+//
+//*****************************************************************************
+// Field: [5] DAC_EN
+//
+// DAC module enable.
+//
+// 0: Disable DAC.
+// 1: Enable DAC.
+//
+// The Sensor Controller must not use the DAC when AUX_SYSIF:OPMODEREQ.REQ
+// equals PDA.
+//
+// The System CPU must not use the DAC when AUX_SYSIF:OPMODEREQ.REQ equals PDA
+// in Standby TI-RTOS power mode. The System CPU must set
+// AUX_SYSIF:PEROPRATE.ANAIF_DAC_OP_RATE to BUS_RATE to use the DAC in Active
+// and Idle TI-RTOS power modes.
+#define AUX_ANAIF_DACCTL_DAC_EN 0x00000020
+#define AUX_ANAIF_DACCTL_DAC_EN_BITN 5
+#define AUX_ANAIF_DACCTL_DAC_EN_M 0x00000020
+#define AUX_ANAIF_DACCTL_DAC_EN_S 5
+
+// Field: [4] DAC_BUFFER_EN
+//
+// DAC buffer enable.
+//
+// DAC buffer reduces the time required to produce the programmed voltage at
+// the expense of increased current consumption.
+//
+// 0: Disable DAC buffer.
+// 1: Enable DAC buffer.
+//
+// Enable buffer when DAC_VOUT_SEL equals COMPA_IN.
+//
+// Do not enable the buffer when AUX_SYSIF:OPMODEREQ.REQ equals PDA or PDLP.
+#define AUX_ANAIF_DACCTL_DAC_BUFFER_EN 0x00000010
+#define AUX_ANAIF_DACCTL_DAC_BUFFER_EN_BITN 4
+#define AUX_ANAIF_DACCTL_DAC_BUFFER_EN_M 0x00000010
+#define AUX_ANAIF_DACCTL_DAC_BUFFER_EN_S 4
+
+// Field: [3] DAC_PRECHARGE_EN
+//
+// DAC precharge enable.
+//
+// Only enable precharge when ADI_4_AUX:MUX2.DAC_VREF_SEL equals DCOUPL and
+// VDDS is higher than 2.65 V.
+//
+// DAC output voltage range:
+//
+// 0: 0 V to 1.28 V.
+// 1: 1.28 V to 2.56 V.
+//
+// Otherwise, see ADI_4_AUX:MUX2.DAC_VREF_SEL for DAC output voltage range.
+//
+// Enable precharge 1 us before you enable the DAC and the buffer.
+#define AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN 0x00000008
+#define AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN_BITN 3
+#define AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN_M 0x00000008
+#define AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN_S 3
+
+// Field: [2:0] DAC_VOUT_SEL
+//
+// DAC output connection.
+//
+// An analog node must only have one driver. Other drivers for the following
+// analog nodes are configured in [ANATOP_MMAP::ADI_4_AUX:*].
+// ENUMs:
+// COMPA_IN Connect to COMPA_IN analog node.
+//
+// Required setting to drive
+// external load selected in
+// ADI_4_AUX:MUX1.COMPA_IN.
+// COMPA_REF Connect to COMPA_REF analog node.
+//
+// It is not possible to
+// drive external loads connected to COMPA_REF I/O
+// mux with this setting.
+// COMPB_REF Connect to COMPB_REF analog node.
+//
+// Required setting to use
+// Comparator B.
+// NC Connect to nothing
+//
+// It is recommended to use
+// NC as intermediate step when you change
+// DAC_VOUT_SEL.
+#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_W 3
+#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_M 0x00000007
+#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_S 0
+#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_COMPA_IN 0x00000004
+#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_COMPA_REF 0x00000002
+#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_COMPB_REF 0x00000001
+#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_NC 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_ANAIF_O_LPMBIASCTL
+//
+//*****************************************************************************
+// Field: [0] EN
+//
+// Module enable.
+//
+// 0: Disable low power mode bias module.
+// 1: Enable low power mode bias module.
+//
+// Set EN to 1 15 us before you enable the DAC or Comparator A.
+#define AUX_ANAIF_LPMBIASCTL_EN 0x00000001
+#define AUX_ANAIF_LPMBIASCTL_EN_BITN 0
+#define AUX_ANAIF_LPMBIASCTL_EN_M 0x00000001
+#define AUX_ANAIF_LPMBIASCTL_EN_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_ANAIF_O_DACSMPLCTL
+//
+//*****************************************************************************
+// Field: [0] EN
+//
+// DAC sample clock enable.
+//
+// 0: Disable sample clock. The sample clock stops low and DACSTAT becomes 0
+// when the current sample clock period completes.
+// 1: Enable DAC sample clock. DACSTAT must be 0 before you enable sample
+// clock.
+#define AUX_ANAIF_DACSMPLCTL_EN 0x00000001
+#define AUX_ANAIF_DACSMPLCTL_EN_BITN 0
+#define AUX_ANAIF_DACSMPLCTL_EN_M 0x00000001
+#define AUX_ANAIF_DACSMPLCTL_EN_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_ANAIF_O_DACSMPLCFG0
+//
+//*****************************************************************************
+// Field: [5:0] CLKDIV
+//
+// Clock division.
+//
+// AUX_SYSIF:PEROPRATE.ANAIF_DAC_OP_RATE divided by (CLKDIV + 1) determines the
+// sample clock base frequency.
+//
+// 0: Divide by 1.
+// 1: Divide by 2.
+// ...
+// 63: Divide by 64.
+#define AUX_ANAIF_DACSMPLCFG0_CLKDIV_W 6
+#define AUX_ANAIF_DACSMPLCFG0_CLKDIV_M 0x0000003F
+#define AUX_ANAIF_DACSMPLCFG0_CLKDIV_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_ANAIF_O_DACSMPLCFG1
+//
+//*****************************************************************************
+// Field: [14] H_PER
+//
+// High time.
+//
+// The sample clock period is high for this many base periods.
+//
+// 0: 2 periods
+// 1: 4 periods
+#define AUX_ANAIF_DACSMPLCFG1_H_PER 0x00004000
+#define AUX_ANAIF_DACSMPLCFG1_H_PER_BITN 14
+#define AUX_ANAIF_DACSMPLCFG1_H_PER_M 0x00004000
+#define AUX_ANAIF_DACSMPLCFG1_H_PER_S 14
+
+// Field: [13:12] L_PER
+//
+// Low time.
+//
+// The sample clock period is low for this many base periods.
+//
+// 0: 1 period
+// 1: 2 periods
+// 2: 3 periods
+// 3: 4 periods
+#define AUX_ANAIF_DACSMPLCFG1_L_PER_W 2
+#define AUX_ANAIF_DACSMPLCFG1_L_PER_M 0x00003000
+#define AUX_ANAIF_DACSMPLCFG1_L_PER_S 12
+
+// Field: [11:8] SETUP_CNT
+//
+// Setup count.
+//
+// Number of active sample clock periods during the setup phase.
+//
+// 0: 1 sample clock period
+// 1: 2 sample clock periods
+// ...
+// 15 : 16 sample clock periods
+#define AUX_ANAIF_DACSMPLCFG1_SETUP_CNT_W 4
+#define AUX_ANAIF_DACSMPLCFG1_SETUP_CNT_M 0x00000F00
+#define AUX_ANAIF_DACSMPLCFG1_SETUP_CNT_S 8
+
+// Field: [7:0] HOLD_INTERVAL
+//
+// Hold interval.
+//
+// Number of inactive sample clock periods between each active sample clock
+// period during hold phase. The sample clock is low when inactive.
+//
+// The range is 0 to 255.
+#define AUX_ANAIF_DACSMPLCFG1_HOLD_INTERVAL_W 8
+#define AUX_ANAIF_DACSMPLCFG1_HOLD_INTERVAL_M 0x000000FF
+#define AUX_ANAIF_DACSMPLCFG1_HOLD_INTERVAL_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_ANAIF_O_DACVALUE
+//
+//*****************************************************************************
+// Field: [7:0] VALUE
+//
+// DAC value.
+//
+// Digital data word for the DAC.
+//
+// Only change VALUE when DACCTL.DAC_EN is 0. Then wait 1 us before you enable
+// the DAC.
+#define AUX_ANAIF_DACVALUE_VALUE_W 8
+#define AUX_ANAIF_DACVALUE_VALUE_M 0x000000FF
+#define AUX_ANAIF_DACVALUE_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_ANAIF_O_DACSTAT
+//
+//*****************************************************************************
+// Field: [1] SETUP_ACTIVE
+//
+// DAC setup phase status.
+//
+// 0: Sample clock is disabled or setup phase is complete.
+// 1: Setup phase in progress.
+#define AUX_ANAIF_DACSTAT_SETUP_ACTIVE 0x00000002
+#define AUX_ANAIF_DACSTAT_SETUP_ACTIVE_BITN 1
+#define AUX_ANAIF_DACSTAT_SETUP_ACTIVE_M 0x00000002
+#define AUX_ANAIF_DACSTAT_SETUP_ACTIVE_S 1
+
+// Field: [0] HOLD_ACTIVE
+//
+// DAC hold phase status.
+//
+// 0: Sample clock is disabled or DAC is not in hold phase.
+// 1: Hold phase in progress.
+#define AUX_ANAIF_DACSTAT_HOLD_ACTIVE 0x00000001
+#define AUX_ANAIF_DACSTAT_HOLD_ACTIVE_BITN 0
+#define AUX_ANAIF_DACSTAT_HOLD_ACTIVE_M 0x00000001
+#define AUX_ANAIF_DACSTAT_HOLD_ACTIVE_S 0
+
+
+#endif // __AUX_ANAIF__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_evctl.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_evctl.h
new file mode 100644
index 0000000..b92db64
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_evctl.h
@@ -0,0 +1,2355 @@
+/******************************************************************************
+* Filename: hw_aux_evctl_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_AUX_EVCTL_H__
+#define __HW_AUX_EVCTL_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// AUX_EVCTL component
+//
+//*****************************************************************************
+// Event Status 0
+#define AUX_EVCTL_O_EVSTAT0 0x00000000
+
+// Event Status 1
+#define AUX_EVCTL_O_EVSTAT1 0x00000004
+
+// Event Status 2
+#define AUX_EVCTL_O_EVSTAT2 0x00000008
+
+// Event Status 3
+#define AUX_EVCTL_O_EVSTAT3 0x0000000C
+
+// Sensor Controller Engine Wait Event Configuration 0
+#define AUX_EVCTL_O_SCEWEVCFG0 0x00000010
+
+// Sensor Controller Engine Wait Event Configuration 1
+#define AUX_EVCTL_O_SCEWEVCFG1 0x00000014
+
+// Direct Memory Access Control
+#define AUX_EVCTL_O_DMACTL 0x00000018
+
+// Software Event Set
+#define AUX_EVCTL_O_SWEVSET 0x00000020
+
+// Events To AON Flags
+#define AUX_EVCTL_O_EVTOAONFLAGS 0x00000024
+
+// Events To AON Polarity
+#define AUX_EVCTL_O_EVTOAONPOL 0x00000028
+
+// Events To AON Clear
+#define AUX_EVCTL_O_EVTOAONFLAGSCLR 0x0000002C
+
+// Events to MCU Flags
+#define AUX_EVCTL_O_EVTOMCUFLAGS 0x00000030
+
+// Event To MCU Polarity
+#define AUX_EVCTL_O_EVTOMCUPOL 0x00000034
+
+// Events To MCU Flags Clear
+#define AUX_EVCTL_O_EVTOMCUFLAGSCLR 0x00000038
+
+// Combined Event To MCU Mask
+#define AUX_EVCTL_O_COMBEVTOMCUMASK 0x0000003C
+
+// Event Observation Configuration
+#define AUX_EVCTL_O_EVOBSCFG 0x00000040
+
+// Programmable Delay
+#define AUX_EVCTL_O_PROGDLY 0x00000044
+
+// Manual
+#define AUX_EVCTL_O_MANUAL 0x00000048
+
+// Event Status 0 Low
+#define AUX_EVCTL_O_EVSTAT0L 0x0000004C
+
+// Event Status 0 High
+#define AUX_EVCTL_O_EVSTAT0H 0x00000050
+
+// Event Status 1 Low
+#define AUX_EVCTL_O_EVSTAT1L 0x00000054
+
+// Event Status 1 High
+#define AUX_EVCTL_O_EVSTAT1H 0x00000058
+
+// Event Status 2 Low
+#define AUX_EVCTL_O_EVSTAT2L 0x0000005C
+
+// Event Status 2 High
+#define AUX_EVCTL_O_EVSTAT2H 0x00000060
+
+// Event Status 3 Low
+#define AUX_EVCTL_O_EVSTAT3L 0x00000064
+
+// Event Status 3 High
+#define AUX_EVCTL_O_EVSTAT3H 0x00000068
+
+//*****************************************************************************
+//
+// Register: AUX_EVCTL_O_EVSTAT0
+//
+//*****************************************************************************
+// Field: [15] AUXIO15
+//
+// AUXIO15 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 7.
+#define AUX_EVCTL_EVSTAT0_AUXIO15 0x00008000
+#define AUX_EVCTL_EVSTAT0_AUXIO15_BITN 15
+#define AUX_EVCTL_EVSTAT0_AUXIO15_M 0x00008000
+#define AUX_EVCTL_EVSTAT0_AUXIO15_S 15
+
+// Field: [14] AUXIO14
+//
+// AUXIO14 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 6.
+#define AUX_EVCTL_EVSTAT0_AUXIO14 0x00004000
+#define AUX_EVCTL_EVSTAT0_AUXIO14_BITN 14
+#define AUX_EVCTL_EVSTAT0_AUXIO14_M 0x00004000
+#define AUX_EVCTL_EVSTAT0_AUXIO14_S 14
+
+// Field: [13] AUXIO13
+//
+// AUXIO13 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 5.
+#define AUX_EVCTL_EVSTAT0_AUXIO13 0x00002000
+#define AUX_EVCTL_EVSTAT0_AUXIO13_BITN 13
+#define AUX_EVCTL_EVSTAT0_AUXIO13_M 0x00002000
+#define AUX_EVCTL_EVSTAT0_AUXIO13_S 13
+
+// Field: [12] AUXIO12
+//
+// AUXIO12 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 4.
+#define AUX_EVCTL_EVSTAT0_AUXIO12 0x00001000
+#define AUX_EVCTL_EVSTAT0_AUXIO12_BITN 12
+#define AUX_EVCTL_EVSTAT0_AUXIO12_M 0x00001000
+#define AUX_EVCTL_EVSTAT0_AUXIO12_S 12
+
+// Field: [11] AUXIO11
+//
+// AUXIO11 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 3.
+#define AUX_EVCTL_EVSTAT0_AUXIO11 0x00000800
+#define AUX_EVCTL_EVSTAT0_AUXIO11_BITN 11
+#define AUX_EVCTL_EVSTAT0_AUXIO11_M 0x00000800
+#define AUX_EVCTL_EVSTAT0_AUXIO11_S 11
+
+// Field: [10] AUXIO10
+//
+// AUXIO10 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 2.
+#define AUX_EVCTL_EVSTAT0_AUXIO10 0x00000400
+#define AUX_EVCTL_EVSTAT0_AUXIO10_BITN 10
+#define AUX_EVCTL_EVSTAT0_AUXIO10_M 0x00000400
+#define AUX_EVCTL_EVSTAT0_AUXIO10_S 10
+
+// Field: [9] AUXIO9
+//
+// AUXIO9 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 1.
+#define AUX_EVCTL_EVSTAT0_AUXIO9 0x00000200
+#define AUX_EVCTL_EVSTAT0_AUXIO9_BITN 9
+#define AUX_EVCTL_EVSTAT0_AUXIO9_M 0x00000200
+#define AUX_EVCTL_EVSTAT0_AUXIO9_S 9
+
+// Field: [8] AUXIO8
+//
+// AUXIO8 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 0.
+#define AUX_EVCTL_EVSTAT0_AUXIO8 0x00000100
+#define AUX_EVCTL_EVSTAT0_AUXIO8_BITN 8
+#define AUX_EVCTL_EVSTAT0_AUXIO8_M 0x00000100
+#define AUX_EVCTL_EVSTAT0_AUXIO8_S 8
+
+// Field: [7] AUXIO7
+//
+// AUXIO7 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 7.
+#define AUX_EVCTL_EVSTAT0_AUXIO7 0x00000080
+#define AUX_EVCTL_EVSTAT0_AUXIO7_BITN 7
+#define AUX_EVCTL_EVSTAT0_AUXIO7_M 0x00000080
+#define AUX_EVCTL_EVSTAT0_AUXIO7_S 7
+
+// Field: [6] AUXIO6
+//
+// AUXIO6 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 6.
+#define AUX_EVCTL_EVSTAT0_AUXIO6 0x00000040
+#define AUX_EVCTL_EVSTAT0_AUXIO6_BITN 6
+#define AUX_EVCTL_EVSTAT0_AUXIO6_M 0x00000040
+#define AUX_EVCTL_EVSTAT0_AUXIO6_S 6
+
+// Field: [5] AUXIO5
+//
+// AUXIO5 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 5.
+#define AUX_EVCTL_EVSTAT0_AUXIO5 0x00000020
+#define AUX_EVCTL_EVSTAT0_AUXIO5_BITN 5
+#define AUX_EVCTL_EVSTAT0_AUXIO5_M 0x00000020
+#define AUX_EVCTL_EVSTAT0_AUXIO5_S 5
+
+// Field: [4] AUXIO4
+//
+// AUXIO4 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 4.
+#define AUX_EVCTL_EVSTAT0_AUXIO4 0x00000010
+#define AUX_EVCTL_EVSTAT0_AUXIO4_BITN 4
+#define AUX_EVCTL_EVSTAT0_AUXIO4_M 0x00000010
+#define AUX_EVCTL_EVSTAT0_AUXIO4_S 4
+
+// Field: [3] AUXIO3
+//
+// AUXIO3 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 3.
+#define AUX_EVCTL_EVSTAT0_AUXIO3 0x00000008
+#define AUX_EVCTL_EVSTAT0_AUXIO3_BITN 3
+#define AUX_EVCTL_EVSTAT0_AUXIO3_M 0x00000008
+#define AUX_EVCTL_EVSTAT0_AUXIO3_S 3
+
+// Field: [2] AUXIO2
+//
+// AUXIO2 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 2.
+#define AUX_EVCTL_EVSTAT0_AUXIO2 0x00000004
+#define AUX_EVCTL_EVSTAT0_AUXIO2_BITN 2
+#define AUX_EVCTL_EVSTAT0_AUXIO2_M 0x00000004
+#define AUX_EVCTL_EVSTAT0_AUXIO2_S 2
+
+// Field: [1] AUXIO1
+//
+// AUXIO1 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 1.
+#define AUX_EVCTL_EVSTAT0_AUXIO1 0x00000002
+#define AUX_EVCTL_EVSTAT0_AUXIO1_BITN 1
+#define AUX_EVCTL_EVSTAT0_AUXIO1_M 0x00000002
+#define AUX_EVCTL_EVSTAT0_AUXIO1_S 1
+
+// Field: [0] AUXIO0
+//
+// AUXIO0 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 0.
+#define AUX_EVCTL_EVSTAT0_AUXIO0 0x00000001
+#define AUX_EVCTL_EVSTAT0_AUXIO0_BITN 0
+#define AUX_EVCTL_EVSTAT0_AUXIO0_M 0x00000001
+#define AUX_EVCTL_EVSTAT0_AUXIO0_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_EVCTL_O_EVSTAT1
+//
+//*****************************************************************************
+// Field: [15] AUXIO31
+//
+// AUXIO31 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 7.
+#define AUX_EVCTL_EVSTAT1_AUXIO31 0x00008000
+#define AUX_EVCTL_EVSTAT1_AUXIO31_BITN 15
+#define AUX_EVCTL_EVSTAT1_AUXIO31_M 0x00008000
+#define AUX_EVCTL_EVSTAT1_AUXIO31_S 15
+
+// Field: [14] AUXIO30
+//
+// AUXIO30 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 6.
+#define AUX_EVCTL_EVSTAT1_AUXIO30 0x00004000
+#define AUX_EVCTL_EVSTAT1_AUXIO30_BITN 14
+#define AUX_EVCTL_EVSTAT1_AUXIO30_M 0x00004000
+#define AUX_EVCTL_EVSTAT1_AUXIO30_S 14
+
+// Field: [13] AUXIO29
+//
+// AUXIO29 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 5.
+#define AUX_EVCTL_EVSTAT1_AUXIO29 0x00002000
+#define AUX_EVCTL_EVSTAT1_AUXIO29_BITN 13
+#define AUX_EVCTL_EVSTAT1_AUXIO29_M 0x00002000
+#define AUX_EVCTL_EVSTAT1_AUXIO29_S 13
+
+// Field: [12] AUXIO28
+//
+// AUXIO28 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 4.
+#define AUX_EVCTL_EVSTAT1_AUXIO28 0x00001000
+#define AUX_EVCTL_EVSTAT1_AUXIO28_BITN 12
+#define AUX_EVCTL_EVSTAT1_AUXIO28_M 0x00001000
+#define AUX_EVCTL_EVSTAT1_AUXIO28_S 12
+
+// Field: [11] AUXIO27
+//
+// AUXIO27 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 3.
+#define AUX_EVCTL_EVSTAT1_AUXIO27 0x00000800
+#define AUX_EVCTL_EVSTAT1_AUXIO27_BITN 11
+#define AUX_EVCTL_EVSTAT1_AUXIO27_M 0x00000800
+#define AUX_EVCTL_EVSTAT1_AUXIO27_S 11
+
+// Field: [10] AUXIO26
+//
+// AUXIO26 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 2.
+#define AUX_EVCTL_EVSTAT1_AUXIO26 0x00000400
+#define AUX_EVCTL_EVSTAT1_AUXIO26_BITN 10
+#define AUX_EVCTL_EVSTAT1_AUXIO26_M 0x00000400
+#define AUX_EVCTL_EVSTAT1_AUXIO26_S 10
+
+// Field: [9] AUXIO25
+//
+// AUXIO25 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 1.
+#define AUX_EVCTL_EVSTAT1_AUXIO25 0x00000200
+#define AUX_EVCTL_EVSTAT1_AUXIO25_BITN 9
+#define AUX_EVCTL_EVSTAT1_AUXIO25_M 0x00000200
+#define AUX_EVCTL_EVSTAT1_AUXIO25_S 9
+
+// Field: [8] AUXIO24
+//
+// AUXIO24 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 0.
+#define AUX_EVCTL_EVSTAT1_AUXIO24 0x00000100
+#define AUX_EVCTL_EVSTAT1_AUXIO24_BITN 8
+#define AUX_EVCTL_EVSTAT1_AUXIO24_M 0x00000100
+#define AUX_EVCTL_EVSTAT1_AUXIO24_S 8
+
+// Field: [7] AUXIO23
+//
+// AUXIO23 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 7.
+#define AUX_EVCTL_EVSTAT1_AUXIO23 0x00000080
+#define AUX_EVCTL_EVSTAT1_AUXIO23_BITN 7
+#define AUX_EVCTL_EVSTAT1_AUXIO23_M 0x00000080
+#define AUX_EVCTL_EVSTAT1_AUXIO23_S 7
+
+// Field: [6] AUXIO22
+//
+// AUXIO22 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 6.
+#define AUX_EVCTL_EVSTAT1_AUXIO22 0x00000040
+#define AUX_EVCTL_EVSTAT1_AUXIO22_BITN 6
+#define AUX_EVCTL_EVSTAT1_AUXIO22_M 0x00000040
+#define AUX_EVCTL_EVSTAT1_AUXIO22_S 6
+
+// Field: [5] AUXIO21
+//
+// AUXIO21 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 5.
+#define AUX_EVCTL_EVSTAT1_AUXIO21 0x00000020
+#define AUX_EVCTL_EVSTAT1_AUXIO21_BITN 5
+#define AUX_EVCTL_EVSTAT1_AUXIO21_M 0x00000020
+#define AUX_EVCTL_EVSTAT1_AUXIO21_S 5
+
+// Field: [4] AUXIO20
+//
+// AUXIO20 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 4.
+#define AUX_EVCTL_EVSTAT1_AUXIO20 0x00000010
+#define AUX_EVCTL_EVSTAT1_AUXIO20_BITN 4
+#define AUX_EVCTL_EVSTAT1_AUXIO20_M 0x00000010
+#define AUX_EVCTL_EVSTAT1_AUXIO20_S 4
+
+// Field: [3] AUXIO19
+//
+// AUXIO19 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 3.
+#define AUX_EVCTL_EVSTAT1_AUXIO19 0x00000008
+#define AUX_EVCTL_EVSTAT1_AUXIO19_BITN 3
+#define AUX_EVCTL_EVSTAT1_AUXIO19_M 0x00000008
+#define AUX_EVCTL_EVSTAT1_AUXIO19_S 3
+
+// Field: [2] AUXIO18
+//
+// AUXIO18 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 2.
+#define AUX_EVCTL_EVSTAT1_AUXIO18 0x00000004
+#define AUX_EVCTL_EVSTAT1_AUXIO18_BITN 2
+#define AUX_EVCTL_EVSTAT1_AUXIO18_M 0x00000004
+#define AUX_EVCTL_EVSTAT1_AUXIO18_S 2
+
+// Field: [1] AUXIO17
+//
+// AUXIO17 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 1.
+#define AUX_EVCTL_EVSTAT1_AUXIO17 0x00000002
+#define AUX_EVCTL_EVSTAT1_AUXIO17_BITN 1
+#define AUX_EVCTL_EVSTAT1_AUXIO17_M 0x00000002
+#define AUX_EVCTL_EVSTAT1_AUXIO17_S 1
+
+// Field: [0] AUXIO16
+//
+// AUXIO16 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 0.
+#define AUX_EVCTL_EVSTAT1_AUXIO16 0x00000001
+#define AUX_EVCTL_EVSTAT1_AUXIO16_BITN 0
+#define AUX_EVCTL_EVSTAT1_AUXIO16_M 0x00000001
+#define AUX_EVCTL_EVSTAT1_AUXIO16_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_EVCTL_O_EVSTAT2
+//
+//*****************************************************************************
+// Field: [15] AUX_COMPB
+//
+// Comparator B output.
+// Configuration of AUX_SYSIF:EVSYNCRATE.AUX_COMPB_SYNC_RATE sets the
+// synchronization rate for this event.
+#define AUX_EVCTL_EVSTAT2_AUX_COMPB 0x00008000
+#define AUX_EVCTL_EVSTAT2_AUX_COMPB_BITN 15
+#define AUX_EVCTL_EVSTAT2_AUX_COMPB_M 0x00008000
+#define AUX_EVCTL_EVSTAT2_AUX_COMPB_S 15
+
+// Field: [14] AUX_COMPA
+//
+// Comparator A output.
+// Configuration of AUX_SYSIF:EVSYNCRATE.AUX_COMPA_SYNC_RATE sets the
+// synchronization rate for this event.
+#define AUX_EVCTL_EVSTAT2_AUX_COMPA 0x00004000
+#define AUX_EVCTL_EVSTAT2_AUX_COMPA_BITN 14
+#define AUX_EVCTL_EVSTAT2_AUX_COMPA_M 0x00004000
+#define AUX_EVCTL_EVSTAT2_AUX_COMPA_S 14
+
+// Field: [13] MCU_OBSMUX1
+//
+// Observation input 1 from IOC.
+// This event is configured by IOC:OBSAUXOUTPUT.SEL1.
+#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX1 0x00002000
+#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX1_BITN 13
+#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX1_M 0x00002000
+#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX1_S 13
+
+// Field: [12] MCU_OBSMUX0
+//
+// Observation input 0 from IOC.
+// This event is configured by IOC:OBSAUXOUTPUT.SEL0 and can be overridden by
+// IOC:OBSAUXOUTPUT.SEL_MISC.
+#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX0 0x00001000
+#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX0_BITN 12
+#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX0_M 0x00001000
+#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX0_S 12
+
+// Field: [11] MCU_EV
+//
+// Event from EVENT configured by EVENT:AUXSEL0.
+#define AUX_EVCTL_EVSTAT2_MCU_EV 0x00000800
+#define AUX_EVCTL_EVSTAT2_MCU_EV_BITN 11
+#define AUX_EVCTL_EVSTAT2_MCU_EV_M 0x00000800
+#define AUX_EVCTL_EVSTAT2_MCU_EV_S 11
+
+// Field: [10] ACLK_REF
+//
+// TDC reference clock.
+// It is configured by DDI_0_OSC:CTL0.ACLK_REF_SRC_SEL and enabled by
+// AUX_SYSIF:TDCREFCLKCTL.REQ.
+#define AUX_EVCTL_EVSTAT2_ACLK_REF 0x00000400
+#define AUX_EVCTL_EVSTAT2_ACLK_REF_BITN 10
+#define AUX_EVCTL_EVSTAT2_ACLK_REF_M 0x00000400
+#define AUX_EVCTL_EVSTAT2_ACLK_REF_S 10
+
+// Field: [9] VDDR_RECHARGE
+//
+// Event is high during VDDR recharge.
+#define AUX_EVCTL_EVSTAT2_VDDR_RECHARGE 0x00000200
+#define AUX_EVCTL_EVSTAT2_VDDR_RECHARGE_BITN 9
+#define AUX_EVCTL_EVSTAT2_VDDR_RECHARGE_M 0x00000200
+#define AUX_EVCTL_EVSTAT2_VDDR_RECHARGE_S 9
+
+// Field: [8] MCU_ACTIVE
+//
+// Event is high while system(MCU, AUX, or JTAG domains) is active or
+// transitions to active (GLDO or DCDC power supply state). Event is not high
+// during VDDR recharge.
+#define AUX_EVCTL_EVSTAT2_MCU_ACTIVE 0x00000100
+#define AUX_EVCTL_EVSTAT2_MCU_ACTIVE_BITN 8
+#define AUX_EVCTL_EVSTAT2_MCU_ACTIVE_M 0x00000100
+#define AUX_EVCTL_EVSTAT2_MCU_ACTIVE_S 8
+
+// Field: [7] PWR_DWN
+//
+// Event is high while system(MCU, AUX, or JTAG domains) is in powerdown (uLDO
+// power supply).
+#define AUX_EVCTL_EVSTAT2_PWR_DWN 0x00000080
+#define AUX_EVCTL_EVSTAT2_PWR_DWN_BITN 7
+#define AUX_EVCTL_EVSTAT2_PWR_DWN_M 0x00000080
+#define AUX_EVCTL_EVSTAT2_PWR_DWN_S 7
+
+// Field: [6] SCLK_LF
+//
+// SCLK_LF clock
+#define AUX_EVCTL_EVSTAT2_SCLK_LF 0x00000040
+#define AUX_EVCTL_EVSTAT2_SCLK_LF_BITN 6
+#define AUX_EVCTL_EVSTAT2_SCLK_LF_M 0x00000040
+#define AUX_EVCTL_EVSTAT2_SCLK_LF_S 6
+
+// Field: [5] AON_BATMON_TEMP_UPD
+//
+// Event is high for two SCLK_MF clock periods when there is an update of
+// AON_BATMON:TEMP.
+#define AUX_EVCTL_EVSTAT2_AON_BATMON_TEMP_UPD 0x00000020
+#define AUX_EVCTL_EVSTAT2_AON_BATMON_TEMP_UPD_BITN 5
+#define AUX_EVCTL_EVSTAT2_AON_BATMON_TEMP_UPD_M 0x00000020
+#define AUX_EVCTL_EVSTAT2_AON_BATMON_TEMP_UPD_S 5
+
+// Field: [4] AON_BATMON_BAT_UPD
+//
+// Event is high for two SCLK_MF clock periods when there is an update of
+// AON_BATMON:BAT.
+#define AUX_EVCTL_EVSTAT2_AON_BATMON_BAT_UPD 0x00000010
+#define AUX_EVCTL_EVSTAT2_AON_BATMON_BAT_UPD_BITN 4
+#define AUX_EVCTL_EVSTAT2_AON_BATMON_BAT_UPD_M 0x00000010
+#define AUX_EVCTL_EVSTAT2_AON_BATMON_BAT_UPD_S 4
+
+// Field: [3] AON_RTC_4KHZ
+//
+// AON_RTC:SUBSEC.VALUE bit 19.
+// AON_RTC:CTL.RTC_4KHZ_EN enables this event.
+#define AUX_EVCTL_EVSTAT2_AON_RTC_4KHZ 0x00000008
+#define AUX_EVCTL_EVSTAT2_AON_RTC_4KHZ_BITN 3
+#define AUX_EVCTL_EVSTAT2_AON_RTC_4KHZ_M 0x00000008
+#define AUX_EVCTL_EVSTAT2_AON_RTC_4KHZ_S 3
+
+// Field: [2] AON_RTC_CH2_DLY
+//
+// AON_RTC:EVFLAGS.CH2 delayed by AON_RTC:CTL.EV_DELAY configuration.
+#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_DLY 0x00000004
+#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_DLY_BITN 2
+#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_DLY_M 0x00000004
+#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_DLY_S 2
+
+// Field: [1] AON_RTC_CH2
+//
+// AON_RTC:EVFLAGS.CH2.
+#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2 0x00000002
+#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_BITN 1
+#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_M 0x00000002
+#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_S 1
+
+// Field: [0] MANUAL_EV
+//
+// Programmable event. See MANUAL for description.
+#define AUX_EVCTL_EVSTAT2_MANUAL_EV 0x00000001
+#define AUX_EVCTL_EVSTAT2_MANUAL_EV_BITN 0
+#define AUX_EVCTL_EVSTAT2_MANUAL_EV_M 0x00000001
+#define AUX_EVCTL_EVSTAT2_MANUAL_EV_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_EVCTL_O_EVSTAT3
+//
+//*****************************************************************************
+// Field: [15] AUX_TIMER2_CLKSWITCH_RDY
+//
+// AUX_SYSIF:TIMER2CLKSWITCH.RDY
+#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_CLKSWITCH_RDY 0x00008000
+#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_CLKSWITCH_RDY_BITN 15
+#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_CLKSWITCH_RDY_M 0x00008000
+#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_CLKSWITCH_RDY_S 15
+
+// Field: [14] AUX_DAC_HOLD_ACTIVE
+//
+// AUX_ANAIF:DACSTAT.HOLD_ACTIVE
+#define AUX_EVCTL_EVSTAT3_AUX_DAC_HOLD_ACTIVE 0x00004000
+#define AUX_EVCTL_EVSTAT3_AUX_DAC_HOLD_ACTIVE_BITN 14
+#define AUX_EVCTL_EVSTAT3_AUX_DAC_HOLD_ACTIVE_M 0x00004000
+#define AUX_EVCTL_EVSTAT3_AUX_DAC_HOLD_ACTIVE_S 14
+
+// Field: [13] AUX_SMPH_AUTOTAKE_DONE
+//
+// See AUX_SMPH:AUTOTAKE.SMPH_ID for description.
+#define AUX_EVCTL_EVSTAT3_AUX_SMPH_AUTOTAKE_DONE 0x00002000
+#define AUX_EVCTL_EVSTAT3_AUX_SMPH_AUTOTAKE_DONE_BITN 13
+#define AUX_EVCTL_EVSTAT3_AUX_SMPH_AUTOTAKE_DONE_M 0x00002000
+#define AUX_EVCTL_EVSTAT3_AUX_SMPH_AUTOTAKE_DONE_S 13
+
+// Field: [12] AUX_ADC_FIFO_NOT_EMPTY
+//
+// AUX_ANAIF:ADCFIFOSTAT.EMPTY negated
+#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_NOT_EMPTY 0x00001000
+#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_NOT_EMPTY_BITN 12
+#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_NOT_EMPTY_M 0x00001000
+#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_NOT_EMPTY_S 12
+
+// Field: [11] AUX_ADC_FIFO_ALMOST_FULL
+//
+// AUX_ANAIF:ADCFIFOSTAT.ALMOST_FULL
+#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_ALMOST_FULL 0x00000800
+#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_ALMOST_FULL_BITN 11
+#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_ALMOST_FULL_M 0x00000800
+#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_ALMOST_FULL_S 11
+
+// Field: [10] AUX_ADC_IRQ
+//
+// The logical function for this event is configurable.
+//
+// When DMACTL.EN = 1 :
+// Event = UDMA0 Channel 7 done event OR
+// AUX_ANAIF:ADCFIFOSTAT.OVERFLOW OR AUX_ANAIF:ADCFIFOSTAT.UNDERFLOW
+//
+// When DMACTL.EN = 0 :
+// Event = (NOT AUX_ANAIF:ADCFIFOSTAT.EMPTY) OR
+// AUX_ANAIF:ADCFIFOSTAT.OVERFLOW OR AUX_ANAIF:ADCFIFOSTAT.UNDERFLOW
+//
+// Bit 7 in UDMA0:DONEMASK must be 0.
+#define AUX_EVCTL_EVSTAT3_AUX_ADC_IRQ 0x00000400
+#define AUX_EVCTL_EVSTAT3_AUX_ADC_IRQ_BITN 10
+#define AUX_EVCTL_EVSTAT3_AUX_ADC_IRQ_M 0x00000400
+#define AUX_EVCTL_EVSTAT3_AUX_ADC_IRQ_S 10
+
+// Field: [9] AUX_ADC_DONE
+//
+// AUX_ANAIF ADC conversion done event.
+// Event is synchronized at AUX bus rate.
+#define AUX_EVCTL_EVSTAT3_AUX_ADC_DONE 0x00000200
+#define AUX_EVCTL_EVSTAT3_AUX_ADC_DONE_BITN 9
+#define AUX_EVCTL_EVSTAT3_AUX_ADC_DONE_M 0x00000200
+#define AUX_EVCTL_EVSTAT3_AUX_ADC_DONE_S 9
+
+// Field: [8] AUX_ISRC_RESET_N
+//
+// AUX_ANAIF:ISRCCTL.RESET_N
+#define AUX_EVCTL_EVSTAT3_AUX_ISRC_RESET_N 0x00000100
+#define AUX_EVCTL_EVSTAT3_AUX_ISRC_RESET_N_BITN 8
+#define AUX_EVCTL_EVSTAT3_AUX_ISRC_RESET_N_M 0x00000100
+#define AUX_EVCTL_EVSTAT3_AUX_ISRC_RESET_N_S 8
+
+// Field: [7] AUX_TDC_DONE
+//
+// AUX_TDC:STAT.DONE
+#define AUX_EVCTL_EVSTAT3_AUX_TDC_DONE 0x00000080
+#define AUX_EVCTL_EVSTAT3_AUX_TDC_DONE_BITN 7
+#define AUX_EVCTL_EVSTAT3_AUX_TDC_DONE_M 0x00000080
+#define AUX_EVCTL_EVSTAT3_AUX_TDC_DONE_S 7
+
+// Field: [6] AUX_TIMER0_EV
+//
+// AUX_TIMER0_EV event, see AUX_TIMER01:T0TARGET for description.
+#define AUX_EVCTL_EVSTAT3_AUX_TIMER0_EV 0x00000040
+#define AUX_EVCTL_EVSTAT3_AUX_TIMER0_EV_BITN 6
+#define AUX_EVCTL_EVSTAT3_AUX_TIMER0_EV_M 0x00000040
+#define AUX_EVCTL_EVSTAT3_AUX_TIMER0_EV_S 6
+
+// Field: [5] AUX_TIMER1_EV
+//
+// AUX_TIMER1_EV event, see AUX_TIMER01:T1TARGET for description.
+#define AUX_EVCTL_EVSTAT3_AUX_TIMER1_EV 0x00000020
+#define AUX_EVCTL_EVSTAT3_AUX_TIMER1_EV_BITN 5
+#define AUX_EVCTL_EVSTAT3_AUX_TIMER1_EV_M 0x00000020
+#define AUX_EVCTL_EVSTAT3_AUX_TIMER1_EV_S 5
+
+// Field: [4] AUX_TIMER2_PULSE
+//
+// AUX_TIMER2 pulse event.
+// Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the
+// synchronization rate for this event.
+#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_PULSE 0x00000010
+#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_PULSE_BITN 4
+#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_PULSE_M 0x00000010
+#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_PULSE_S 4
+
+// Field: [3] AUX_TIMER2_EV3
+//
+// AUX_TIMER2 event output 3.
+// Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the
+// synchronization rate for this event.
+#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV3 0x00000008
+#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV3_BITN 3
+#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV3_M 0x00000008
+#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV3_S 3
+
+// Field: [2] AUX_TIMER2_EV2
+//
+// AUX_TIMER2 event output 2.
+// Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the
+// synchronization rate for this event.
+#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV2 0x00000004
+#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV2_BITN 2
+#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV2_M 0x00000004
+#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV2_S 2
+
+// Field: [1] AUX_TIMER2_EV1
+//
+// AUX_TIMER2 event output 1.
+// Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the
+// synchronization rate for this event.
+#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV1 0x00000002
+#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV1_BITN 1
+#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV1_M 0x00000002
+#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV1_S 1
+
+// Field: [0] AUX_TIMER2_EV0
+//
+// AUX_TIMER2 event output 0.
+// Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the
+// synchronization rate for this event.
+#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV0 0x00000001
+#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV0_BITN 0
+#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV0_M 0x00000001
+#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV0_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_EVCTL_O_SCEWEVCFG0
+//
+//*****************************************************************************
+// Field: [6] COMB_EV_EN
+//
+// Event combination control:
+//
+// 0: Disable event combination.
+// 1: Enable event combination.
+#define AUX_EVCTL_SCEWEVCFG0_COMB_EV_EN 0x00000040
+#define AUX_EVCTL_SCEWEVCFG0_COMB_EV_EN_BITN 6
+#define AUX_EVCTL_SCEWEVCFG0_COMB_EV_EN_M 0x00000040
+#define AUX_EVCTL_SCEWEVCFG0_COMB_EV_EN_S 6
+
+// Field: [5:0] EV0_SEL
+//
+// Select the event source from the synchronous event bus to be used in event
+// equation.
+// ENUMs:
+// AUX_TIMER2_CLKSWITCH_RDY EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY
+// AUX_DAC_HOLD_ACTIVE EVSTAT3.AUX_DAC_HOLD_ACTIVE
+// AUX_SMPH_AUTOTAKE_DONE EVSTAT3.AUX_SMPH_AUTOTAKE_DONE
+// AUX_ADC_FIFO_NOT_EMPTY EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY
+// AUX_ADC_FIFO_ALMOST_FULL EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL
+// AUX_ADC_IRQ EVSTAT3.AUX_ADC_IRQ
+// AUX_ADC_DONE EVSTAT3.AUX_ADC_DONE
+// AUX_ISRC_RESET_N EVSTAT3.AUX_ISRC_RESET_N
+// AUX_TDC_DONE EVSTAT3.AUX_TDC_DONE
+// AUX_TIMER0_EV EVSTAT3.AUX_TIMER0_EV
+// AUX_TIMER1_EV EVSTAT3.AUX_TIMER1_EV
+// AUX_TIMER2_PULSE EVSTAT3.AUX_TIMER2_PULSE
+// AUX_TIMER2_EV3 EVSTAT3.AUX_TIMER2_EV3
+// AUX_TIMER2_EV2 EVSTAT3.AUX_TIMER2_EV2
+// AUX_TIMER2_EV1 EVSTAT3.AUX_TIMER2_EV1
+// AUX_TIMER2_EV0 EVSTAT3.AUX_TIMER2_EV0
+// AUX_COMPB EVSTAT2.AUX_COMPB
+// AUX_COMPA EVSTAT2.AUX_COMPA
+// MCU_OBSMUX1 EVSTAT2.MCU_OBSMUX1
+// MCU_OBSMUX0 EVSTAT2.MCU_OBSMUX0
+// MCU_EV EVSTAT2.MCU_EV
+// ACLK_REF EVSTAT2.ACLK_REF
+// VDDR_RECHARGE EVSTAT2.VDDR_RECHARGE
+// MCU_ACTIVE EVSTAT2.MCU_ACTIVE
+// PWR_DWN EVSTAT2.PWR_DWN
+// SCLK_LF EVSTAT2.SCLK_LF
+// AON_BATMON_TEMP_UPD EVSTAT2.AON_BATMON_TEMP_UPD
+// AON_BATMON_BAT_UPD EVSTAT2.AON_BATMON_BAT_UPD
+// AON_RTC_4KHZ EVSTAT2.AON_RTC_4KHZ
+// AON_RTC_CH2_DLY EVSTAT2.AON_RTC_CH2_DLY
+// AON_RTC_CH2 EVSTAT2.AON_RTC_CH2
+// AUX_PROG_DLY_IDLE Programmable delay event as described in PROGDLY
+// AUXIO31 EVSTAT1.AUXIO31
+// AUXIO30 EVSTAT1.AUXIO30
+// AUXIO29 EVSTAT1.AUXIO29
+// AUXIO28 EVSTAT1.AUXIO28
+// AUXIO27 EVSTAT1.AUXIO27
+// AUXIO26 EVSTAT1.AUXIO26
+// AUXIO25 EVSTAT1.AUXIO25
+// AUXIO24 EVSTAT1.AUXIO24
+// AUXIO23 EVSTAT1.AUXIO23
+// AUXIO22 EVSTAT1.AUXIO22
+// AUXIO21 EVSTAT1.AUXIO21
+// AUXIO20 EVSTAT1.AUXIO20
+// AUXIO19 EVSTAT1.AUXIO19
+// AUXIO18 EVSTAT1.AUXIO18
+// AUXIO17 EVSTAT1.AUXIO17
+// AUXIO16 EVSTAT1.AUXIO16
+// AUXIO15 EVSTAT0.AUXIO15
+// AUXIO14 EVSTAT0.AUXIO14
+// AUXIO13 EVSTAT0.AUXIO13
+// AUXIO12 EVSTAT0.AUXIO12
+// AUXIO11 EVSTAT0.AUXIO11
+// AUXIO10 EVSTAT0.AUXIO10
+// AUXIO9 EVSTAT0.AUXIO9
+// AUXIO8 EVSTAT0.AUXIO8
+// AUXIO7 EVSTAT0.AUXIO7
+// AUXIO6 EVSTAT0.AUXIO6
+// AUXIO5 EVSTAT0.AUXIO5
+// AUXIO4 EVSTAT0.AUXIO4
+// AUXIO3 EVSTAT0.AUXIO3
+// AUXIO2 EVSTAT0.AUXIO2
+// AUXIO1 EVSTAT0.AUXIO1
+// AUXIO0 EVSTAT0.AUXIO0
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_W 6
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_M 0x0000003F
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_S 0
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER2_CLKSWITCH_RDY 0x0000003F
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_DAC_HOLD_ACTIVE 0x0000003E
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_SMPH_AUTOTAKE_DONE 0x0000003D
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_ADC_IRQ 0x0000003A
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_ADC_DONE 0x00000039
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_ISRC_RESET_N 0x00000038
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TDC_DONE 0x00000037
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER0_EV 0x00000036
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER1_EV 0x00000035
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER2_PULSE 0x00000034
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER2_EV3 0x00000033
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER2_EV2 0x00000032
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER2_EV1 0x00000031
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER2_EV0 0x00000030
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_COMPB 0x0000002F
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_COMPA 0x0000002E
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_MCU_OBSMUX1 0x0000002D
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_MCU_OBSMUX0 0x0000002C
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_MCU_EV 0x0000002B
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_ACLK_REF 0x0000002A
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_VDDR_RECHARGE 0x00000029
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_MCU_ACTIVE 0x00000028
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_PWR_DWN 0x00000027
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_SCLK_LF 0x00000026
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AON_BATMON_TEMP_UPD 0x00000025
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AON_BATMON_BAT_UPD 0x00000024
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AON_RTC_4KHZ 0x00000023
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AON_RTC_CH2_DLY 0x00000022
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AON_RTC_CH2 0x00000021
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_PROG_DLY_IDLE 0x00000020
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO31 0x0000001F
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO30 0x0000001E
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO29 0x0000001D
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO28 0x0000001C
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO27 0x0000001B
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO26 0x0000001A
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO25 0x00000019
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO24 0x00000018
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO23 0x00000017
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO22 0x00000016
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO21 0x00000015
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO20 0x00000014
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO19 0x00000013
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO18 0x00000012
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO17 0x00000011
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO16 0x00000010
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO15 0x0000000F
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO14 0x0000000E
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO13 0x0000000D
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO12 0x0000000C
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO11 0x0000000B
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO10 0x0000000A
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO9 0x00000009
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO8 0x00000008
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO7 0x00000007
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO6 0x00000006
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO5 0x00000005
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO4 0x00000004
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO3 0x00000003
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO2 0x00000002
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO1 0x00000001
+#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO0 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_EVCTL_O_SCEWEVCFG1
+//
+//*****************************************************************************
+// Field: [7] EV0_POL
+//
+// Polarity of SCEWEVCFG0.EV0_SEL event.
+//
+// When SCEWEVCFG0.COMB_EV_EN is 0:
+//
+// 0: Non-inverted.
+// 1: Non-inverted.
+//
+// When SCEWEVCFG0.COMB_EV_EN is 1.
+//
+// 0: Non-inverted.
+// 1: Inverted.
+#define AUX_EVCTL_SCEWEVCFG1_EV0_POL 0x00000080
+#define AUX_EVCTL_SCEWEVCFG1_EV0_POL_BITN 7
+#define AUX_EVCTL_SCEWEVCFG1_EV0_POL_M 0x00000080
+#define AUX_EVCTL_SCEWEVCFG1_EV0_POL_S 7
+
+// Field: [6] EV1_POL
+//
+// Polarity of EV1_SEL event.
+//
+// When SCEWEVCFG0.COMB_EV_EN is 0:
+//
+// 0: Non-inverted.
+// 1: Non-inverted.
+//
+// When SCEWEVCFG0.COMB_EV_EN is 1.
+//
+// 0: Non-inverted.
+// 1: Inverted.
+#define AUX_EVCTL_SCEWEVCFG1_EV1_POL 0x00000040
+#define AUX_EVCTL_SCEWEVCFG1_EV1_POL_BITN 6
+#define AUX_EVCTL_SCEWEVCFG1_EV1_POL_M 0x00000040
+#define AUX_EVCTL_SCEWEVCFG1_EV1_POL_S 6
+
+// Field: [5:0] EV1_SEL
+//
+// Select the event source from the synchronous event bus to be used in event
+// equation.
+// ENUMs:
+// AUX_TIMER2_CLKSWITCH_RDY EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY
+// AUX_DAC_HOLD_ACTIVE EVSTAT3.AUX_DAC_HOLD_ACTIVE
+// AUX_SMPH_AUTOTAKE_DONE EVSTAT3.AUX_SMPH_AUTOTAKE_DONE
+// AUX_ADC_FIFO_NOT_EMPTY EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY
+// AUX_ADC_FIFO_ALMOST_FULL EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL
+// AUX_ADC_IRQ EVSTAT3.AUX_ADC_IRQ
+// AUX_ADC_DONE EVSTAT3.AUX_ADC_DONE
+// AUX_ISRC_RESET_N EVSTAT3.AUX_ISRC_RESET_N
+// AUX_TDC_DONE EVSTAT3.AUX_TDC_DONE
+// AUX_TIMER0_EV EVSTAT3.AUX_TIMER0_EV
+// AUX_TIMER1_EV EVSTAT3.AUX_TIMER1_EV
+// AUX_TIMER2_PULSE EVSTAT3.AUX_TIMER2_PULSE
+// AUX_TIMER2_EV3 EVSTAT3.AUX_TIMER2_EV3
+// AUX_TIMER2_EV2 EVSTAT3.AUX_TIMER2_EV2
+// AUX_TIMER2_EV1 EVSTAT3.AUX_TIMER2_EV1
+// AUX_TIMER2_EV0 EVSTAT3.AUX_TIMER2_EV0
+// AUX_COMPB EVSTAT2.AUX_COMPB
+// AUX_COMPA EVSTAT2.AUX_COMPA
+// MCU_OBSMUX1 EVSTAT2.MCU_OBSMUX1
+// MCU_OBSMUX0 EVSTAT2.MCU_OBSMUX0
+// MCU_EV EVSTAT2.MCU_EV
+// ACLK_REF EVSTAT2.ACLK_REF
+// VDDR_RECHARGE EVSTAT2.VDDR_RECHARGE
+// MCU_ACTIVE EVSTAT2.MCU_ACTIVE
+// PWR_DWN EVSTAT2.PWR_DWN
+// SCLK_LF EVSTAT2.SCLK_LF
+// AON_BATMON_TEMP_UPD EVSTAT2.AON_BATMON_TEMP_UPD
+// AON_BATMON_BAT_UPD EVSTAT2.AON_BATMON_BAT_UPD
+// AON_RTC_4KHZ EVSTAT2.AON_RTC_4KHZ
+// AON_RTC_CH2_DLY EVSTAT2.AON_RTC_CH2_DLY
+// AON_RTC_CH2 EVSTAT2.AON_RTC_CH2
+// AUX_PROG_DLY_IDLE Programmable delay event as described in PROGDLY
+// AUXIO31 EVSTAT1.AUXIO31
+// AUXIO30 EVSTAT1.AUXIO30
+// AUXIO29 EVSTAT1.AUXIO29
+// AUXIO28 EVSTAT1.AUXIO28
+// AUXIO27 EVSTAT1.AUXIO27
+// AUXIO26 EVSTAT1.AUXIO26
+// AUXIO25 EVSTAT1.AUXIO25
+// AUXIO24 EVSTAT1.AUXIO24
+// AUXIO23 EVSTAT1.AUXIO23
+// AUXIO22 EVSTAT1.AUXIO22
+// AUXIO21 EVSTAT1.AUXIO21
+// AUXIO20 EVSTAT1.AUXIO20
+// AUXIO19 EVSTAT1.AUXIO19
+// AUXIO18 EVSTAT1.AUXIO18
+// AUXIO17 EVSTAT1.AUXIO17
+// AUXIO16 EVSTAT1.AUXIO16
+// AUXIO15 EVSTAT0.AUXIO15
+// AUXIO14 EVSTAT0.AUXIO14
+// AUXIO13 EVSTAT0.AUXIO13
+// AUXIO12 EVSTAT0.AUXIO12
+// AUXIO11 EVSTAT0.AUXIO11
+// AUXIO10 EVSTAT0.AUXIO10
+// AUXIO9 EVSTAT0.AUXIO9
+// AUXIO8 EVSTAT0.AUXIO8
+// AUXIO7 EVSTAT0.AUXIO7
+// AUXIO6 EVSTAT0.AUXIO6
+// AUXIO5 EVSTAT0.AUXIO5
+// AUXIO4 EVSTAT0.AUXIO4
+// AUXIO3 EVSTAT0.AUXIO3
+// AUXIO2 EVSTAT0.AUXIO2
+// AUXIO1 EVSTAT0.AUXIO1
+// AUXIO0 EVSTAT0.AUXIO0
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_W 6
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_M 0x0000003F
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_S 0
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER2_CLKSWITCH_RDY 0x0000003F
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_DAC_HOLD_ACTIVE 0x0000003E
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_SMPH_AUTOTAKE_DONE 0x0000003D
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_ADC_IRQ 0x0000003A
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_ADC_DONE 0x00000039
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_ISRC_RESET_N 0x00000038
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TDC_DONE 0x00000037
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER0_EV 0x00000036
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER1_EV 0x00000035
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER2_PULSE 0x00000034
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER2_EV3 0x00000033
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER2_EV2 0x00000032
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER2_EV1 0x00000031
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER2_EV0 0x00000030
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_COMPB 0x0000002F
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_COMPA 0x0000002E
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_MCU_OBSMUX1 0x0000002D
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_MCU_OBSMUX0 0x0000002C
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_MCU_EV 0x0000002B
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_ACLK_REF 0x0000002A
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_VDDR_RECHARGE 0x00000029
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_MCU_ACTIVE 0x00000028
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_PWR_DWN 0x00000027
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_SCLK_LF 0x00000026
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AON_BATMON_TEMP_UPD 0x00000025
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AON_BATMON_BAT_UPD 0x00000024
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AON_RTC_4KHZ 0x00000023
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AON_RTC_CH2_DLY 0x00000022
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AON_RTC_CH2 0x00000021
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_PROG_DLY_IDLE 0x00000020
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO31 0x0000001F
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO30 0x0000001E
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO29 0x0000001D
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO28 0x0000001C
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO27 0x0000001B
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO26 0x0000001A
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO25 0x00000019
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO24 0x00000018
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO23 0x00000017
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO22 0x00000016
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO21 0x00000015
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO20 0x00000014
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO19 0x00000013
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO18 0x00000012
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO17 0x00000011
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO16 0x00000010
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO15 0x0000000F
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO14 0x0000000E
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO13 0x0000000D
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO12 0x0000000C
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO11 0x0000000B
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO10 0x0000000A
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO9 0x00000009
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO8 0x00000008
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO7 0x00000007
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO6 0x00000006
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO5 0x00000005
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO4 0x00000004
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO3 0x00000003
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO2 0x00000002
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO1 0x00000001
+#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO0 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_EVCTL_O_DMACTL
+//
+//*****************************************************************************
+// Field: [2] REQ_MODE
+//
+// UDMA0 Request mode
+// ENUMs:
+// SINGLE Single requests are generated on UDMA0 channel 7
+// when the condition configured in SEL is met.
+// BURST Burst requests are generated on UDMA0 channel 7
+// when the condition configured in SEL is met.
+#define AUX_EVCTL_DMACTL_REQ_MODE 0x00000004
+#define AUX_EVCTL_DMACTL_REQ_MODE_BITN 2
+#define AUX_EVCTL_DMACTL_REQ_MODE_M 0x00000004
+#define AUX_EVCTL_DMACTL_REQ_MODE_S 2
+#define AUX_EVCTL_DMACTL_REQ_MODE_SINGLE 0x00000004
+#define AUX_EVCTL_DMACTL_REQ_MODE_BURST 0x00000000
+
+// Field: [1] EN
+//
+// uDMA ADC interface enable.
+//
+// 0: Disable UDMA0 interface to ADC.
+// 1: Enable UDMA0 interface to ADC.
+#define AUX_EVCTL_DMACTL_EN 0x00000002
+#define AUX_EVCTL_DMACTL_EN_BITN 1
+#define AUX_EVCTL_DMACTL_EN_M 0x00000002
+#define AUX_EVCTL_DMACTL_EN_S 1
+
+// Field: [0] SEL
+//
+// Select FIFO watermark level required to trigger a UDMA0 transfer of ADC FIFO
+// data.
+// ENUMs:
+// AUX_ADC_FIFO_ALMOST_FULL UDMA0 trigger event will be generated when the ADC
+// FIFO is almost full (3/4 full).
+// AUX_ADC_FIFO_NOT_EMPTY UDMA0 trigger event will be generated when there
+// are samples in the ADC FIFO.
+#define AUX_EVCTL_DMACTL_SEL 0x00000001
+#define AUX_EVCTL_DMACTL_SEL_BITN 0
+#define AUX_EVCTL_DMACTL_SEL_M 0x00000001
+#define AUX_EVCTL_DMACTL_SEL_S 0
+#define AUX_EVCTL_DMACTL_SEL_AUX_ADC_FIFO_ALMOST_FULL 0x00000001
+#define AUX_EVCTL_DMACTL_SEL_AUX_ADC_FIFO_NOT_EMPTY 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_EVCTL_O_SWEVSET
+//
+//*****************************************************************************
+// Field: [2] SWEV2
+//
+// Software event flag 2.
+//
+// 0: No effect.
+// 1: Set software event flag 2.
+#define AUX_EVCTL_SWEVSET_SWEV2 0x00000004
+#define AUX_EVCTL_SWEVSET_SWEV2_BITN 2
+#define AUX_EVCTL_SWEVSET_SWEV2_M 0x00000004
+#define AUX_EVCTL_SWEVSET_SWEV2_S 2
+
+// Field: [1] SWEV1
+//
+// Software event flag 1.
+//
+// 0: No effect.
+// 1: Set software event flag 1.
+#define AUX_EVCTL_SWEVSET_SWEV1 0x00000002
+#define AUX_EVCTL_SWEVSET_SWEV1_BITN 1
+#define AUX_EVCTL_SWEVSET_SWEV1_M 0x00000002
+#define AUX_EVCTL_SWEVSET_SWEV1_S 1
+
+// Field: [0] SWEV0
+//
+// Software event flag 0.
+//
+// 0: No effect.
+// 1: Set software event flag 0.
+#define AUX_EVCTL_SWEVSET_SWEV0 0x00000001
+#define AUX_EVCTL_SWEVSET_SWEV0_BITN 0
+#define AUX_EVCTL_SWEVSET_SWEV0_M 0x00000001
+#define AUX_EVCTL_SWEVSET_SWEV0_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_EVCTL_O_EVTOAONFLAGS
+//
+//*****************************************************************************
+// Field: [8] AUX_TIMER1_EV
+//
+// This event flag is set when level selected by EVTOAONPOL.AUX_TIMER1_EV
+// occurs on EVSTAT3.AUX_TIMER1_EV.
+#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER1_EV 0x00000100
+#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER1_EV_BITN 8
+#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER1_EV_M 0x00000100
+#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER1_EV_S 8
+
+// Field: [7] AUX_TIMER0_EV
+//
+// This event flag is set when level selected by EVTOAONPOL.AUX_TIMER0_EV
+// occurs on EVSTAT3.AUX_TIMER0_EV.
+#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER0_EV 0x00000080
+#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER0_EV_BITN 7
+#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER0_EV_M 0x00000080
+#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER0_EV_S 7
+
+// Field: [6] AUX_TDC_DONE
+//
+// This event flag is set when level selected by EVTOAONPOL.AUX_TDC_DONE occurs
+// on EVSTAT3.AUX_TDC_DONE.
+#define AUX_EVCTL_EVTOAONFLAGS_AUX_TDC_DONE 0x00000040
+#define AUX_EVCTL_EVTOAONFLAGS_AUX_TDC_DONE_BITN 6
+#define AUX_EVCTL_EVTOAONFLAGS_AUX_TDC_DONE_M 0x00000040
+#define AUX_EVCTL_EVTOAONFLAGS_AUX_TDC_DONE_S 6
+
+// Field: [5] AUX_ADC_DONE
+//
+// This event flag is set when level selected by EVTOAONPOL.AUX_ADC_DONE occurs
+// on EVSTAT3.AUX_ADC_DONE.
+#define AUX_EVCTL_EVTOAONFLAGS_AUX_ADC_DONE 0x00000020
+#define AUX_EVCTL_EVTOAONFLAGS_AUX_ADC_DONE_BITN 5
+#define AUX_EVCTL_EVTOAONFLAGS_AUX_ADC_DONE_M 0x00000020
+#define AUX_EVCTL_EVTOAONFLAGS_AUX_ADC_DONE_S 5
+
+// Field: [4] AUX_COMPB
+//
+// This event flag is set when edge selected by EVTOAONPOL.AUX_COMPB occurs on
+// EVSTAT2.AUX_COMPB.
+#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB 0x00000010
+#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_BITN 4
+#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_M 0x00000010
+#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_S 4
+
+// Field: [3] AUX_COMPA
+//
+// This event flag is set when edge selected by EVTOAONPOL.AUX_COMPA occurs on
+// EVSTAT2.AUX_COMPA.
+#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA 0x00000008
+#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_BITN 3
+#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_M 0x00000008
+#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_S 3
+
+// Field: [2] SWEV2
+//
+// This event flag is set when software writes a 1 to SWEVSET.SWEV2.
+#define AUX_EVCTL_EVTOAONFLAGS_SWEV2 0x00000004
+#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_BITN 2
+#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_M 0x00000004
+#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_S 2
+
+// Field: [1] SWEV1
+//
+// This event flag is set when software writes a 1 to SWEVSET.SWEV1.
+#define AUX_EVCTL_EVTOAONFLAGS_SWEV1 0x00000002
+#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_BITN 1
+#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_M 0x00000002
+#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_S 1
+
+// Field: [0] SWEV0
+//
+// This event flag is set when software writes a 1 to SWEVSET.SWEV0.
+#define AUX_EVCTL_EVTOAONFLAGS_SWEV0 0x00000001
+#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_BITN 0
+#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_M 0x00000001
+#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_EVCTL_O_EVTOAONPOL
+//
+//*****************************************************************************
+// Field: [8] AUX_TIMER1_EV
+//
+// Select the level of EVSTAT3.AUX_TIMER1_EV that sets
+// EVTOAONFLAGS.AUX_TIMER1_EV.
+// ENUMs:
+// LOW Low level
+// HIGH High level
+#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER1_EV 0x00000100
+#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER1_EV_BITN 8
+#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER1_EV_M 0x00000100
+#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER1_EV_S 8
+#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER1_EV_LOW 0x00000100
+#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER1_EV_HIGH 0x00000000
+
+// Field: [7] AUX_TIMER0_EV
+//
+// Select the level of EVSTAT3.AUX_TIMER0_EV that sets
+// EVTOAONFLAGS.AUX_TIMER0_EV.
+// ENUMs:
+// LOW Low level
+// HIGH High level
+#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER0_EV 0x00000080
+#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER0_EV_BITN 7
+#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER0_EV_M 0x00000080
+#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER0_EV_S 7
+#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER0_EV_LOW 0x00000080
+#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER0_EV_HIGH 0x00000000
+
+// Field: [6] AUX_TDC_DONE
+//
+// Select level of EVSTAT3.AUX_TDC_DONE that sets EVTOAONFLAGS.AUX_TDC_DONE.
+// ENUMs:
+// LOW Low level
+// HIGH High level
+#define AUX_EVCTL_EVTOAONPOL_AUX_TDC_DONE 0x00000040
+#define AUX_EVCTL_EVTOAONPOL_AUX_TDC_DONE_BITN 6
+#define AUX_EVCTL_EVTOAONPOL_AUX_TDC_DONE_M 0x00000040
+#define AUX_EVCTL_EVTOAONPOL_AUX_TDC_DONE_S 6
+#define AUX_EVCTL_EVTOAONPOL_AUX_TDC_DONE_LOW 0x00000040
+#define AUX_EVCTL_EVTOAONPOL_AUX_TDC_DONE_HIGH 0x00000000
+
+// Field: [5] AUX_ADC_DONE
+//
+// Select the level of EVSTAT3.AUX_ADC_DONE that sets
+// EVTOAONFLAGS.AUX_ADC_DONE.
+// ENUMs:
+// LOW Low level
+// HIGH High level
+#define AUX_EVCTL_EVTOAONPOL_AUX_ADC_DONE 0x00000020
+#define AUX_EVCTL_EVTOAONPOL_AUX_ADC_DONE_BITN 5
+#define AUX_EVCTL_EVTOAONPOL_AUX_ADC_DONE_M 0x00000020
+#define AUX_EVCTL_EVTOAONPOL_AUX_ADC_DONE_S 5
+#define AUX_EVCTL_EVTOAONPOL_AUX_ADC_DONE_LOW 0x00000020
+#define AUX_EVCTL_EVTOAONPOL_AUX_ADC_DONE_HIGH 0x00000000
+
+// Field: [4] AUX_COMPB
+//
+// Select the edge of EVSTAT2.AUX_COMPB that sets EVTOAONFLAGS.AUX_COMPB.
+// ENUMs:
+// FALL Falling edge
+// RISE Rising edge
+#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB 0x00000010
+#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_BITN 4
+#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_M 0x00000010
+#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_S 4
+#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_FALL 0x00000010
+#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_RISE 0x00000000
+
+// Field: [3] AUX_COMPA
+//
+// Select the edge of EVSTAT2.AUX_COMPA that sets EVTOAONFLAGS.AUX_COMPA.
+// ENUMs:
+// FALL Falling edge
+// RISE Rising edge
+#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA 0x00000008
+#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_BITN 3
+#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_M 0x00000008
+#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_S 3
+#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_FALL 0x00000008
+#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_RISE 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_EVCTL_O_EVTOAONFLAGSCLR
+//
+//*****************************************************************************
+// Field: [8] AUX_TIMER1_EV
+//
+// Write 1 to clear EVTOAONFLAGS.AUX_TIMER1_EV.
+//
+// Read value is 0.
+#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER1_EV 0x00000100
+#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER1_EV_BITN 8
+#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER1_EV_M 0x00000100
+#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER1_EV_S 8
+
+// Field: [7] AUX_TIMER0_EV
+//
+// Write 1 to clear EVTOAONFLAGS.AUX_TIMER0_EV.
+//
+// Read value is 0.
+#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER0_EV 0x00000080
+#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER0_EV_BITN 7
+#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER0_EV_M 0x00000080
+#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER0_EV_S 7
+
+// Field: [6] AUX_TDC_DONE
+//
+// Write 1 to clear EVTOAONFLAGS.AUX_TDC_DONE.
+//
+// Read value is 0.
+#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TDC_DONE 0x00000040
+#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TDC_DONE_BITN 6
+#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TDC_DONE_M 0x00000040
+#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TDC_DONE_S 6
+
+// Field: [5] AUX_ADC_DONE
+//
+// Write 1 to clear EVTOAONFLAGS.AUX_ADC_DONE.
+//
+// Read value is 0.
+#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_ADC_DONE 0x00000020
+#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_ADC_DONE_BITN 5
+#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_ADC_DONE_M 0x00000020
+#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_ADC_DONE_S 5
+
+// Field: [4] AUX_COMPB
+//
+// Write 1 to clear EVTOAONFLAGS.AUX_COMPB.
+//
+// Read value is 0.
+#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB 0x00000010
+#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_BITN 4
+#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_M 0x00000010
+#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_S 4
+
+// Field: [3] AUX_COMPA
+//
+// Write 1 to clear EVTOAONFLAGS.AUX_COMPA.
+//
+// Read value is 0.
+#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA 0x00000008
+#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_BITN 3
+#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_M 0x00000008
+#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_S 3
+
+// Field: [2] SWEV2
+//
+// Write 1 to clear EVTOAONFLAGS.SWEV2.
+//
+// Read value is 0.
+#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2 0x00000004
+#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_BITN 2
+#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_M 0x00000004
+#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_S 2
+
+// Field: [1] SWEV1
+//
+// Write 1 to clear EVTOAONFLAGS.SWEV1.
+//
+// Read value is 0.
+#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1 0x00000002
+#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_BITN 1
+#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_M 0x00000002
+#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_S 1
+
+// Field: [0] SWEV0
+//
+// Write 1 to clear EVTOAONFLAGS.SWEV0.
+//
+// Read value is 0.
+#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0 0x00000001
+#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_BITN 0
+#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_M 0x00000001
+#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_EVCTL_O_EVTOMCUFLAGS
+//
+//*****************************************************************************
+// Field: [15] AUX_TIMER2_PULSE
+//
+// This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_PULSE
+// occurs on EVSTAT3.AUX_TIMER2_PULSE.
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_PULSE 0x00008000
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_PULSE_BITN 15
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_PULSE_M 0x00008000
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_PULSE_S 15
+
+// Field: [14] AUX_TIMER2_EV3
+//
+// This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV3
+// occurs on EVSTAT3.AUX_TIMER2_EV3.
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV3 0x00004000
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV3_BITN 14
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV3_M 0x00004000
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV3_S 14
+
+// Field: [13] AUX_TIMER2_EV2
+//
+// This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV2
+// occurs on EVSTAT3.AUX_TIMER2_EV2.
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV2 0x00002000
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV2_BITN 13
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV2_M 0x00002000
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV2_S 13
+
+// Field: [12] AUX_TIMER2_EV1
+//
+// This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV1
+// occurs on EVSTAT3.AUX_TIMER2_EV1.
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV1 0x00001000
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV1_BITN 12
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV1_M 0x00001000
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV1_S 12
+
+// Field: [11] AUX_TIMER2_EV0
+//
+// This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV0
+// occurs on EVSTAT3.AUX_TIMER2_EV0.
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV0 0x00000800
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV0_BITN 11
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV0_M 0x00000800
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV0_S 11
+
+// Field: [10] AUX_ADC_IRQ
+//
+// This event flag is set when level selected by EVTOMCUPOL.AUX_ADC_IRQ occurs
+// on EVSTAT3.AUX_ADC_IRQ.
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_IRQ 0x00000400
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_IRQ_BITN 10
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_IRQ_M 0x00000400
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_IRQ_S 10
+
+// Field: [9] MCU_OBSMUX0
+//
+// This event flag is set when level selected by EVTOMCUPOL.MCU_OBSMUX0 occurs
+// on EVSTAT2.MCU_OBSMUX0.
+#define AUX_EVCTL_EVTOMCUFLAGS_MCU_OBSMUX0 0x00000200
+#define AUX_EVCTL_EVTOMCUFLAGS_MCU_OBSMUX0_BITN 9
+#define AUX_EVCTL_EVTOMCUFLAGS_MCU_OBSMUX0_M 0x00000200
+#define AUX_EVCTL_EVTOMCUFLAGS_MCU_OBSMUX0_S 9
+
+// Field: [8] AUX_ADC_FIFO_ALMOST_FULL
+//
+// This event flag is set when level selected by
+// EVTOMCUPOL.AUX_ADC_FIFO_ALMOST_FULL occurs on
+// EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL.
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_FIFO_ALMOST_FULL 0x00000100
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_FIFO_ALMOST_FULL_BITN 8
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_FIFO_ALMOST_FULL_M 0x00000100
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_FIFO_ALMOST_FULL_S 8
+
+// Field: [7] AUX_ADC_DONE
+//
+// This event flag is set when level selected by EVTOMCUPOL.AUX_ADC_DONE occurs
+// on EVSTAT3.AUX_ADC_DONE.
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_DONE 0x00000080
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_DONE_BITN 7
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_DONE_M 0x00000080
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_DONE_S 7
+
+// Field: [6] AUX_SMPH_AUTOTAKE_DONE
+//
+// This event flag is set when level selected by
+// EVTOMCUPOL.AUX_SMPH_AUTOTAKE_DONE occurs on EVSTAT3.AUX_SMPH_AUTOTAKE_DONE.
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_SMPH_AUTOTAKE_DONE 0x00000040
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_SMPH_AUTOTAKE_DONE_BITN 6
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_SMPH_AUTOTAKE_DONE_M 0x00000040
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_SMPH_AUTOTAKE_DONE_S 6
+
+// Field: [5] AUX_TIMER1_EV
+//
+// This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER1_EV
+// occurs on EVSTAT3.AUX_TIMER1_EV.
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER1_EV 0x00000020
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER1_EV_BITN 5
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER1_EV_M 0x00000020
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER1_EV_S 5
+
+// Field: [4] AUX_TIMER0_EV
+//
+// This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER0_EV
+// occurs on EVSTAT3.AUX_TIMER0_EV.
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER0_EV 0x00000010
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER0_EV_BITN 4
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER0_EV_M 0x00000010
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER0_EV_S 4
+
+// Field: [3] AUX_TDC_DONE
+//
+// This event flag is set when level selected by EVTOMCUPOL.AUX_TDC_DONE occurs
+// on EVSTAT3.AUX_TDC_DONE.
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TDC_DONE 0x00000008
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TDC_DONE_BITN 3
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TDC_DONE_M 0x00000008
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TDC_DONE_S 3
+
+// Field: [2] AUX_COMPB
+//
+// This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPB occurs on
+// EVSTAT2.AUX_COMPB.
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB 0x00000004
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_BITN 2
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_M 0x00000004
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_S 2
+
+// Field: [1] AUX_COMPA
+//
+// This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPA occurs on
+// EVSTAT2.AUX_COMPA.
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA 0x00000002
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_BITN 1
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_M 0x00000002
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_S 1
+
+// Field: [0] AUX_WU_EV
+//
+// This event flag is set when level selected by EVTOMCUPOL.AUX_WU_EV occurs on
+// reduction-OR of the AUX_SYSIF:WUFLAGS register.
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_WU_EV 0x00000001
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_WU_EV_BITN 0
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_WU_EV_M 0x00000001
+#define AUX_EVCTL_EVTOMCUFLAGS_AUX_WU_EV_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_EVCTL_O_EVTOMCUPOL
+//
+//*****************************************************************************
+// Field: [15] AUX_TIMER2_PULSE
+//
+// Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_PULSE.
+// ENUMs:
+// LOW Low level
+// HIGH High level
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_PULSE 0x00008000
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_PULSE_BITN 15
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_PULSE_M 0x00008000
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_PULSE_S 15
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_PULSE_LOW 0x00008000
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_PULSE_HIGH 0x00000000
+
+// Field: [14] AUX_TIMER2_EV3
+//
+// Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV3.
+// ENUMs:
+// LOW Low level
+// HIGH High level
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV3 0x00004000
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV3_BITN 14
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV3_M 0x00004000
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV3_S 14
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV3_LOW 0x00004000
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV3_HIGH 0x00000000
+
+// Field: [13] AUX_TIMER2_EV2
+//
+// Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV2.
+// ENUMs:
+// LOW Low level
+// HIGH High level
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV2 0x00002000
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV2_BITN 13
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV2_M 0x00002000
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV2_S 13
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV2_LOW 0x00002000
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV2_HIGH 0x00000000
+
+// Field: [12] AUX_TIMER2_EV1
+//
+// Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV1.
+// ENUMs:
+// LOW Low level
+// HIGH High level
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV1 0x00001000
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV1_BITN 12
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV1_M 0x00001000
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV1_S 12
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV1_LOW 0x00001000
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV1_HIGH 0x00000000
+
+// Field: [11] AUX_TIMER2_EV0
+//
+// Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV0.
+// ENUMs:
+// LOW Low level
+// HIGH High level
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV0 0x00000800
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV0_BITN 11
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV0_M 0x00000800
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV0_S 11
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV0_LOW 0x00000800
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV0_HIGH 0x00000000
+
+// Field: [10] AUX_ADC_IRQ
+//
+// Select the event source level that sets EVTOMCUFLAGS.AUX_ADC_IRQ.
+// ENUMs:
+// LOW Low level
+// HIGH High level
+#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_IRQ 0x00000400
+#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_IRQ_BITN 10
+#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_IRQ_M 0x00000400
+#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_IRQ_S 10
+#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_IRQ_LOW 0x00000400
+#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_IRQ_HIGH 0x00000000
+
+// Field: [9] MCU_OBSMUX0
+//
+// Select the event source level that sets EVTOMCUFLAGS.MCU_OBSMUX0.
+// ENUMs:
+// LOW Low level
+// HIGH High level
+#define AUX_EVCTL_EVTOMCUPOL_MCU_OBSMUX0 0x00000200
+#define AUX_EVCTL_EVTOMCUPOL_MCU_OBSMUX0_BITN 9
+#define AUX_EVCTL_EVTOMCUPOL_MCU_OBSMUX0_M 0x00000200
+#define AUX_EVCTL_EVTOMCUPOL_MCU_OBSMUX0_S 9
+#define AUX_EVCTL_EVTOMCUPOL_MCU_OBSMUX0_LOW 0x00000200
+#define AUX_EVCTL_EVTOMCUPOL_MCU_OBSMUX0_HIGH 0x00000000
+
+// Field: [8] AUX_ADC_FIFO_ALMOST_FULL
+//
+// Select the event source level that sets
+// EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL.
+// ENUMs:
+// LOW Low level
+// HIGH High level
+#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_FIFO_ALMOST_FULL 0x00000100
+#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_FIFO_ALMOST_FULL_BITN 8
+#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_FIFO_ALMOST_FULL_M 0x00000100
+#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_FIFO_ALMOST_FULL_S 8
+#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_FIFO_ALMOST_FULL_LOW 0x00000100
+#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_FIFO_ALMOST_FULL_HIGH 0x00000000
+
+// Field: [7] AUX_ADC_DONE
+//
+// Select the event source level that sets EVTOMCUFLAGS.AUX_ADC_DONE.
+// ENUMs:
+// LOW Low level
+// HIGH High level
+#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_DONE 0x00000080
+#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_DONE_BITN 7
+#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_DONE_M 0x00000080
+#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_DONE_S 7
+#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_DONE_LOW 0x00000080
+#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_DONE_HIGH 0x00000000
+
+// Field: [6] AUX_SMPH_AUTOTAKE_DONE
+//
+// Select the event source level that sets EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE.
+// ENUMs:
+// LOW Low level
+// HIGH High level
+#define AUX_EVCTL_EVTOMCUPOL_AUX_SMPH_AUTOTAKE_DONE 0x00000040
+#define AUX_EVCTL_EVTOMCUPOL_AUX_SMPH_AUTOTAKE_DONE_BITN 6
+#define AUX_EVCTL_EVTOMCUPOL_AUX_SMPH_AUTOTAKE_DONE_M 0x00000040
+#define AUX_EVCTL_EVTOMCUPOL_AUX_SMPH_AUTOTAKE_DONE_S 6
+#define AUX_EVCTL_EVTOMCUPOL_AUX_SMPH_AUTOTAKE_DONE_LOW 0x00000040
+#define AUX_EVCTL_EVTOMCUPOL_AUX_SMPH_AUTOTAKE_DONE_HIGH 0x00000000
+
+// Field: [5] AUX_TIMER1_EV
+//
+// Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER1_EV.
+// ENUMs:
+// LOW Low level
+// HIGH High level
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER1_EV 0x00000020
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER1_EV_BITN 5
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER1_EV_M 0x00000020
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER1_EV_S 5
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER1_EV_LOW 0x00000020
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER1_EV_HIGH 0x00000000
+
+// Field: [4] AUX_TIMER0_EV
+//
+// Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER0_EV.
+// ENUMs:
+// LOW Low level
+// HIGH High level
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER0_EV 0x00000010
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER0_EV_BITN 4
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER0_EV_M 0x00000010
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER0_EV_S 4
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER0_EV_LOW 0x00000010
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER0_EV_HIGH 0x00000000
+
+// Field: [3] AUX_TDC_DONE
+//
+// Select the event source level that sets EVTOMCUFLAGS.AUX_TDC_DONE.
+// ENUMs:
+// LOW Low level
+// HIGH High level
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TDC_DONE 0x00000008
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TDC_DONE_BITN 3
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TDC_DONE_M 0x00000008
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TDC_DONE_S 3
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TDC_DONE_LOW 0x00000008
+#define AUX_EVCTL_EVTOMCUPOL_AUX_TDC_DONE_HIGH 0x00000000
+
+// Field: [2] AUX_COMPB
+//
+// Select the event source edge that sets EVTOMCUFLAGS.AUX_COMPB.
+// ENUMs:
+// FALL Falling edge
+// RISE Rising edge
+#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB 0x00000004
+#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_BITN 2
+#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_M 0x00000004
+#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_S 2
+#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_FALL 0x00000004
+#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_RISE 0x00000000
+
+// Field: [1] AUX_COMPA
+//
+// Select the event source edge that sets EVTOMCUFLAGS.AUX_COMPA.
+// ENUMs:
+// FALL Falling edge
+// RISE Rising edge
+#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA 0x00000002
+#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_BITN 1
+#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_M 0x00000002
+#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_S 1
+#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_FALL 0x00000002
+#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_RISE 0x00000000
+
+// Field: [0] AUX_WU_EV
+//
+// Select the event source level that sets EVTOMCUFLAGS.AUX_WU_EV.
+// ENUMs:
+// LOW Low level
+// HIGH High level
+#define AUX_EVCTL_EVTOMCUPOL_AUX_WU_EV 0x00000001
+#define AUX_EVCTL_EVTOMCUPOL_AUX_WU_EV_BITN 0
+#define AUX_EVCTL_EVTOMCUPOL_AUX_WU_EV_M 0x00000001
+#define AUX_EVCTL_EVTOMCUPOL_AUX_WU_EV_S 0
+#define AUX_EVCTL_EVTOMCUPOL_AUX_WU_EV_LOW 0x00000001
+#define AUX_EVCTL_EVTOMCUPOL_AUX_WU_EV_HIGH 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_EVCTL_O_EVTOMCUFLAGSCLR
+//
+//*****************************************************************************
+// Field: [15] AUX_TIMER2_PULSE
+//
+// Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_PULSE.
+//
+// Read value is 0.
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_PULSE 0x00008000
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_PULSE_BITN 15
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_PULSE_M 0x00008000
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_PULSE_S 15
+
+// Field: [14] AUX_TIMER2_EV3
+//
+// Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV3.
+//
+// Read value is 0.
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV3 0x00004000
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV3_BITN 14
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV3_M 0x00004000
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV3_S 14
+
+// Field: [13] AUX_TIMER2_EV2
+//
+// Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV2.
+//
+// Read value is 0.
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV2 0x00002000
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV2_BITN 13
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV2_M 0x00002000
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV2_S 13
+
+// Field: [12] AUX_TIMER2_EV1
+//
+// Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV1.
+//
+// Read value is 0.
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV1 0x00001000
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV1_BITN 12
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV1_M 0x00001000
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV1_S 12
+
+// Field: [11] AUX_TIMER2_EV0
+//
+// Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV0.
+//
+// Read value is 0.
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV0 0x00000800
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV0_BITN 11
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV0_M 0x00000800
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV0_S 11
+
+// Field: [10] AUX_ADC_IRQ
+//
+// Write 1 to clear EVTOMCUFLAGS.AUX_ADC_IRQ.
+//
+// Read value is 0.
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_IRQ 0x00000400
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_IRQ_BITN 10
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_IRQ_M 0x00000400
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_IRQ_S 10
+
+// Field: [9] MCU_OBSMUX0
+//
+// Write 1 to clear EVTOMCUFLAGS.MCU_OBSMUX0.
+//
+// Read value is 0.
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_MCU_OBSMUX0 0x00000200
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_MCU_OBSMUX0_BITN 9
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_MCU_OBSMUX0_M 0x00000200
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_MCU_OBSMUX0_S 9
+
+// Field: [8] AUX_ADC_FIFO_ALMOST_FULL
+//
+// Write 1 to clear EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL.
+//
+// Read value is 0.
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_FIFO_ALMOST_FULL 0x00000100
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_FIFO_ALMOST_FULL_BITN 8
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_FIFO_ALMOST_FULL_M 0x00000100
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_FIFO_ALMOST_FULL_S 8
+
+// Field: [7] AUX_ADC_DONE
+//
+// Write 1 to clear EVTOMCUFLAGS.AUX_ADC_DONE.
+//
+// Read value is 0.
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_DONE 0x00000080
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_DONE_BITN 7
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_DONE_M 0x00000080
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_DONE_S 7
+
+// Field: [6] AUX_SMPH_AUTOTAKE_DONE
+//
+// Write 1 to clear EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE.
+//
+// Read value is 0.
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_SMPH_AUTOTAKE_DONE 0x00000040
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_SMPH_AUTOTAKE_DONE_BITN 6
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_SMPH_AUTOTAKE_DONE_M 0x00000040
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_SMPH_AUTOTAKE_DONE_S 6
+
+// Field: [5] AUX_TIMER1_EV
+//
+// Write 1 to clear EVTOMCUFLAGS.AUX_TIMER1_EV.
+//
+// Read value is 0.
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER1_EV 0x00000020
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER1_EV_BITN 5
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER1_EV_M 0x00000020
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER1_EV_S 5
+
+// Field: [4] AUX_TIMER0_EV
+//
+// Write 1 to clear EVTOMCUFLAGS.AUX_TIMER0_EV.
+//
+// Read value is 0.
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER0_EV 0x00000010
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER0_EV_BITN 4
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER0_EV_M 0x00000010
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER0_EV_S 4
+
+// Field: [3] AUX_TDC_DONE
+//
+// Write 1 to clear EVTOMCUFLAGS.AUX_TDC_DONE.
+//
+// Read value is 0.
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TDC_DONE 0x00000008
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TDC_DONE_BITN 3
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TDC_DONE_M 0x00000008
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TDC_DONE_S 3
+
+// Field: [2] AUX_COMPB
+//
+// Write 1 to clear EVTOMCUFLAGS.AUX_COMPB.
+//
+// Read value is 0.
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB 0x00000004
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_BITN 2
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_M 0x00000004
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_S 2
+
+// Field: [1] AUX_COMPA
+//
+// Write 1 to clear EVTOMCUFLAGS.AUX_COMPA.
+//
+// Read value is 0.
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA 0x00000002
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_BITN 1
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_M 0x00000002
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_S 1
+
+// Field: [0] AUX_WU_EV
+//
+// Write 1 to clear EVTOMCUFLAGS.AUX_WU_EV.
+//
+// Read value is 0.
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_WU_EV 0x00000001
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_WU_EV_BITN 0
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_WU_EV_M 0x00000001
+#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_WU_EV_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_EVCTL_O_COMBEVTOMCUMASK
+//
+//*****************************************************************************
+// Field: [15] AUX_TIMER2_PULSE
+//
+// EVTOMCUFLAGS.AUX_TIMER2_PULSE contribution to the AUX_COMB event.
+//
+// 0: Exclude.
+// 1: Include.
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_PULSE 0x00008000
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_PULSE_BITN 15
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_PULSE_M 0x00008000
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_PULSE_S 15
+
+// Field: [14] AUX_TIMER2_EV3
+//
+// EVTOMCUFLAGS.AUX_TIMER2_EV3 contribution to the AUX_COMB event.
+//
+// 0: Exclude.
+// 1: Include.
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV3 0x00004000
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV3_BITN 14
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV3_M 0x00004000
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV3_S 14
+
+// Field: [13] AUX_TIMER2_EV2
+//
+// EVTOMCUFLAGS.AUX_TIMER2_EV2 contribution to the AUX_COMB event.
+//
+// 0: Exclude.
+// 1: Include.
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV2 0x00002000
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV2_BITN 13
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV2_M 0x00002000
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV2_S 13
+
+// Field: [12] AUX_TIMER2_EV1
+//
+// EVTOMCUFLAGS.AUX_TIMER2_EV1 contribution to the AUX_COMB event.
+//
+// 0: Exclude.
+// 1: Include.
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV1 0x00001000
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV1_BITN 12
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV1_M 0x00001000
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV1_S 12
+
+// Field: [11] AUX_TIMER2_EV0
+//
+// EVTOMCUFLAGS.AUX_TIMER2_EV0 contribution to the AUX_COMB event.
+//
+// 0: Exclude.
+// 1: Include.
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV0 0x00000800
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV0_BITN 11
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV0_M 0x00000800
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV0_S 11
+
+// Field: [10] AUX_ADC_IRQ
+//
+// EVTOMCUFLAGS.AUX_ADC_IRQ contribution to the AUX_COMB event.
+//
+// 0: Exclude.
+// 1: Include.
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_IRQ 0x00000400
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_IRQ_BITN 10
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_IRQ_M 0x00000400
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_IRQ_S 10
+
+// Field: [9] MCU_OBSMUX0
+//
+// EVTOMCUFLAGS.MCU_OBSMUX0 contribution to the AUX_COMB event.
+//
+// 0: Exclude.
+// 1: Include.
+#define AUX_EVCTL_COMBEVTOMCUMASK_MCU_OBSMUX0 0x00000200
+#define AUX_EVCTL_COMBEVTOMCUMASK_MCU_OBSMUX0_BITN 9
+#define AUX_EVCTL_COMBEVTOMCUMASK_MCU_OBSMUX0_M 0x00000200
+#define AUX_EVCTL_COMBEVTOMCUMASK_MCU_OBSMUX0_S 9
+
+// Field: [8] AUX_ADC_FIFO_ALMOST_FULL
+//
+// EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL contribution to the AUX_COMB event.
+//
+// 0: Exclude.
+// 1: Include.
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_FIFO_ALMOST_FULL 0x00000100
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_FIFO_ALMOST_FULL_BITN 8
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_FIFO_ALMOST_FULL_M 0x00000100
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_FIFO_ALMOST_FULL_S 8
+
+// Field: [7] AUX_ADC_DONE
+//
+// EVTOMCUFLAGS.AUX_ADC_DONE contribution to the AUX_COMB event.
+//
+// 0: Exclude.
+// 1: Include.
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_DONE 0x00000080
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_DONE_BITN 7
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_DONE_M 0x00000080
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_DONE_S 7
+
+// Field: [6] AUX_SMPH_AUTOTAKE_DONE
+//
+// EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE contribution to the AUX_COMB event.
+//
+// 0: Exclude.
+// 1: Include.
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_SMPH_AUTOTAKE_DONE 0x00000040
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_SMPH_AUTOTAKE_DONE_BITN 6
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_SMPH_AUTOTAKE_DONE_M 0x00000040
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_SMPH_AUTOTAKE_DONE_S 6
+
+// Field: [5] AUX_TIMER1_EV
+//
+// EVTOMCUFLAGS.AUX_TIMER1_EV contribution to the AUX_COMB event.
+//
+// 0: Exclude.
+// 1: Include.
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER1_EV 0x00000020
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER1_EV_BITN 5
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER1_EV_M 0x00000020
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER1_EV_S 5
+
+// Field: [4] AUX_TIMER0_EV
+//
+// EVTOMCUFLAGS.AUX_TIMER0_EV contribution to the AUX_COMB event.
+//
+// 0: Exclude.
+// 1: Include.
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER0_EV 0x00000010
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER0_EV_BITN 4
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER0_EV_M 0x00000010
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER0_EV_S 4
+
+// Field: [3] AUX_TDC_DONE
+//
+// EVTOMCUFLAGS.AUX_TDC_DONE contribution to the AUX_COMB event.
+//
+// 0: Exclude.
+// 1: Include.
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TDC_DONE 0x00000008
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TDC_DONE_BITN 3
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TDC_DONE_M 0x00000008
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TDC_DONE_S 3
+
+// Field: [2] AUX_COMPB
+//
+// EVTOMCUFLAGS.AUX_COMPB contribution to the AUX_COMB event.
+//
+// 0: Exclude
+// 1: Include.
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB 0x00000004
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_BITN 2
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_M 0x00000004
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_S 2
+
+// Field: [1] AUX_COMPA
+//
+// EVTOMCUFLAGS.AUX_COMPA contribution to the AUX_COMB event.
+//
+// 0: Exclude.
+// 1: Include.
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA 0x00000002
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_BITN 1
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_M 0x00000002
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_S 1
+
+// Field: [0] AUX_WU_EV
+//
+// EVTOMCUFLAGS.AUX_WU_EV contribution to the AUX_COMB event.
+//
+// 0: Exclude.
+// 1: Include.
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_WU_EV 0x00000001
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_WU_EV_BITN 0
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_WU_EV_M 0x00000001
+#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_WU_EV_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_EVCTL_O_EVOBSCFG
+//
+//*****************************************************************************
+// Field: [5:0] EVOBS_SEL
+//
+// Select which event from the asynchronous event bus that represents
+// AUX_EV_OBS in AUX_AIODIOn.
+// ENUMs:
+// AUX_TIMER2_CLKSW_RDY EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY
+// AUX_DAC_HOLD_ACTIVE EVSTAT3.AUX_DAC_HOLD_ACTIVE
+// AUX_SMPH_AUTOTAKE_DONE EVSTAT3.AUX_SMPH_AUTOTAKE_DONE
+// AUX_ADC_FIFO_NOT_EMPTY EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY
+// AUX_ADC_FIFO_ALMOST_FULL EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL
+// AUX_ADC_IRQ EVSTAT3.AUX_ADC_IRQ
+// AUX_ADC_DONE EVSTAT3.AUX_ADC_DONE
+// AUX_ISRC_RESET_N EVSTAT3.AUX_ISRC_RESET_N
+// AUX_TDC_DONE EVSTAT3.AUX_TDC_DONE
+// AUX_TIMER0_EV EVSTAT3.AUX_TIMER0_EV
+// AUX_TIMER1_EV EVSTAT3.AUX_TIMER1_EV
+// AUX_TIMER2_PULSE EVSTAT3.AUX_TIMER2_PULSE
+// AUX_TIMER2_EV3 EVSTAT3.AUX_TIMER2_EV3
+// AUX_TIMER2_EV2 EVSTAT3.AUX_TIMER2_EV2
+// AUX_TIMER2_EV1 EVSTAT3.AUX_TIMER2_EV1
+// AUX_TIMER2_EV0 EVSTAT3.AUX_TIMER2_EV0
+// AUX_COMPB EVSTAT2.AUX_COMPB
+// AUX_COMPA EVSTAT2.AUX_COMPA
+// MCU_OBSMUX1 EVSTAT2.MCU_OBSMUX1
+// MCU_OBSMUX0 EVSTAT2.MCU_OBSMUX0
+// MCU_EV EVSTAT2.MCU_EV
+// ACLK_REF EVSTAT2.ACLK_REF
+// VDDR_RECHARGE EVSTAT2.VDDR_RECHARGE
+// MCU_ACTIVE EVSTAT2.MCU_ACTIVE
+// PWR_DWN EVSTAT2.PWR_DWN
+// SCLK_LF EVSTAT2.SCLK_LF
+// AON_BATMON_TEMP_UPD EVSTAT2.AON_BATMON_TEMP_UPD
+// AON_BATMON_BAT_UPD EVSTAT2.AON_BATMON_BAT_UPD
+// AON_RTC_4KHZ EVSTAT2.AON_RTC_4KHZ
+// AON_RTC_CH2_DLY EVSTAT2.AON_RTC_CH2_DLY
+// AON_RTC_CH2 EVSTAT2.AON_RTC_CH2
+// MANUAL_EV EVSTAT2.MANUAL_EV
+// AUXIO31 EVSTAT1.AUXIO31
+// AUXIO30 EVSTAT1.AUXIO30
+// AUXIO29 EVSTAT1.AUXIO29
+// AUXIO28 EVSTAT1.AUXIO28
+// AUXIO27 EVSTAT1.AUXIO27
+// AUXIO26 EVSTAT1.AUXIO26
+// AUXIO25 EVSTAT1.AUXIO25
+// AUXIO24 EVSTAT1.AUXIO24
+// AUXIO23 EVSTAT1.AUXIO23
+// AUXIO22 EVSTAT1.AUXIO22
+// AUXIO21 EVSTAT1.AUXIO21
+// AUXIO20 EVSTAT1.AUXIO20
+// AUXIO19 EVSTAT1.AUXIO19
+// AUXIO18 EVSTAT1.AUXIO18
+// AUXIO17 EVSTAT1.AUXIO17
+// AUXIO16 EVSTAT1.AUXIO16
+// AUXIO15 EVSTAT0.AUXIO15
+// AUXIO14 EVSTAT0.AUXIO14
+// AUXIO13 EVSTAT0.AUXIO13
+// AUXIO12 EVSTAT0.AUXIO12
+// AUXIO11 EVSTAT0.AUXIO11
+// AUXIO10 EVSTAT0.AUXIO10
+// AUXIO9 EVSTAT0.AUXIO9
+// AUXIO8 EVSTAT0.AUXIO8
+// AUXIO7 EVSTAT0.AUXIO7
+// AUXIO6 EVSTAT0.AUXIO6
+// AUXIO5 EVSTAT0.AUXIO5
+// AUXIO4 EVSTAT0.AUXIO4
+// AUXIO3 EVSTAT0.AUXIO3
+// AUXIO2 EVSTAT0.AUXIO2
+// AUXIO1 EVSTAT0.AUXIO1
+// AUXIO0 EVSTAT0.AUXIO0
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_W 6
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_M 0x0000003F
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_S 0
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER2_CLKSW_RDY 0x0000003F
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_DAC_HOLD_ACTIVE 0x0000003E
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_SMPH_AUTOTAKE_DONE 0x0000003D
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_ADC_IRQ 0x0000003A
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_ADC_DONE 0x00000039
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_ISRC_RESET_N 0x00000038
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TDC_DONE 0x00000037
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER0_EV 0x00000036
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER1_EV 0x00000035
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER2_PULSE 0x00000034
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER2_EV3 0x00000033
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER2_EV2 0x00000032
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER2_EV1 0x00000031
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER2_EV0 0x00000030
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_COMPB 0x0000002F
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_COMPA 0x0000002E
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_MCU_OBSMUX1 0x0000002D
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_MCU_OBSMUX0 0x0000002C
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_MCU_EV 0x0000002B
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_ACLK_REF 0x0000002A
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_VDDR_RECHARGE 0x00000029
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_MCU_ACTIVE 0x00000028
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_PWR_DWN 0x00000027
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_SCLK_LF 0x00000026
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AON_BATMON_TEMP_UPD 0x00000025
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AON_BATMON_BAT_UPD 0x00000024
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AON_RTC_4KHZ 0x00000023
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AON_RTC_CH2_DLY 0x00000022
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AON_RTC_CH2 0x00000021
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_MANUAL_EV 0x00000020
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO31 0x0000001F
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO30 0x0000001E
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO29 0x0000001D
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO28 0x0000001C
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO27 0x0000001B
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO26 0x0000001A
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO25 0x00000019
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO24 0x00000018
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO23 0x00000017
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO22 0x00000016
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO21 0x00000015
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO20 0x00000014
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO19 0x00000013
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO18 0x00000012
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO17 0x00000011
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO16 0x00000010
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO15 0x0000000F
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO14 0x0000000E
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO13 0x0000000D
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO12 0x0000000C
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO11 0x0000000B
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO10 0x0000000A
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO9 0x00000009
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO8 0x00000008
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO7 0x00000007
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO6 0x00000006
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO5 0x00000005
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO4 0x00000004
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO3 0x00000003
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO2 0x00000002
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO1 0x00000001
+#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO0 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_EVCTL_O_PROGDLY
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// VALUE decrements to 0 at a rate of 1 MHz.
+//
+// The event AUX_PROG_DLY_IDLE is high when VALUE is 0, otherwise it is low.
+//
+// Only use the programmable delay counter and the AUX_PROG_DLY_IDLE event when
+// AUX_SYSIF:OPMODEACK.ACK equals A or LP.
+//
+// Decrementation of VALUE halts when either is true:
+// - AUX_SCE:CTL.DBG_FREEZE_EN is set and system CPU is halted in debug mode.
+// - AUX_SYSIF:TIMERHALT.PROGDLY is set.
+#define AUX_EVCTL_PROGDLY_VALUE_W 16
+#define AUX_EVCTL_PROGDLY_VALUE_M 0x0000FFFF
+#define AUX_EVCTL_PROGDLY_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_EVCTL_O_MANUAL
+//
+//*****************************************************************************
+// Field: [0] EV
+//
+// This bit field sets the value of EVSTAT2.MANUAL_EV.
+#define AUX_EVCTL_MANUAL_EV 0x00000001
+#define AUX_EVCTL_MANUAL_EV_BITN 0
+#define AUX_EVCTL_MANUAL_EV_M 0x00000001
+#define AUX_EVCTL_MANUAL_EV_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_EVCTL_O_EVSTAT0L
+//
+//*****************************************************************************
+// Field: [7:0] ALIAS_EV
+//
+// Alias of EVSTAT0 event 7 down to 0.
+#define AUX_EVCTL_EVSTAT0L_ALIAS_EV_W 8
+#define AUX_EVCTL_EVSTAT0L_ALIAS_EV_M 0x000000FF
+#define AUX_EVCTL_EVSTAT0L_ALIAS_EV_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_EVCTL_O_EVSTAT0H
+//
+//*****************************************************************************
+// Field: [7:0] ALIAS_EV
+//
+// Alias of EVSTAT0 event 15 down to 8.
+#define AUX_EVCTL_EVSTAT0H_ALIAS_EV_W 8
+#define AUX_EVCTL_EVSTAT0H_ALIAS_EV_M 0x000000FF
+#define AUX_EVCTL_EVSTAT0H_ALIAS_EV_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_EVCTL_O_EVSTAT1L
+//
+//*****************************************************************************
+// Field: [7:0] ALIAS_EV
+//
+// Alias of EVSTAT1 event 7 down to 0.
+#define AUX_EVCTL_EVSTAT1L_ALIAS_EV_W 8
+#define AUX_EVCTL_EVSTAT1L_ALIAS_EV_M 0x000000FF
+#define AUX_EVCTL_EVSTAT1L_ALIAS_EV_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_EVCTL_O_EVSTAT1H
+//
+//*****************************************************************************
+// Field: [7:0] ALIAS_EV
+//
+// Alias of EVSTAT1 event 15 down to 8.
+#define AUX_EVCTL_EVSTAT1H_ALIAS_EV_W 8
+#define AUX_EVCTL_EVSTAT1H_ALIAS_EV_M 0x000000FF
+#define AUX_EVCTL_EVSTAT1H_ALIAS_EV_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_EVCTL_O_EVSTAT2L
+//
+//*****************************************************************************
+// Field: [7:0] ALIAS_EV
+//
+// Alias of EVSTAT2 event 7 down to 0.
+#define AUX_EVCTL_EVSTAT2L_ALIAS_EV_W 8
+#define AUX_EVCTL_EVSTAT2L_ALIAS_EV_M 0x000000FF
+#define AUX_EVCTL_EVSTAT2L_ALIAS_EV_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_EVCTL_O_EVSTAT2H
+//
+//*****************************************************************************
+// Field: [7:0] ALIAS_EV
+//
+// Alias of EVSTAT2 event 15 down to 8.
+#define AUX_EVCTL_EVSTAT2H_ALIAS_EV_W 8
+#define AUX_EVCTL_EVSTAT2H_ALIAS_EV_M 0x000000FF
+#define AUX_EVCTL_EVSTAT2H_ALIAS_EV_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_EVCTL_O_EVSTAT3L
+//
+//*****************************************************************************
+// Field: [7:0] ALIAS_EV
+//
+// Alias of EVSTAT3 event 7 down to 0.
+#define AUX_EVCTL_EVSTAT3L_ALIAS_EV_W 8
+#define AUX_EVCTL_EVSTAT3L_ALIAS_EV_M 0x000000FF
+#define AUX_EVCTL_EVSTAT3L_ALIAS_EV_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_EVCTL_O_EVSTAT3H
+//
+//*****************************************************************************
+// Field: [7:0] ALIAS_EV
+//
+// Alias of EVSTAT3 event 15 down to 8.
+#define AUX_EVCTL_EVSTAT3H_ALIAS_EV_W 8
+#define AUX_EVCTL_EVSTAT3H_ALIAS_EV_M 0x000000FF
+#define AUX_EVCTL_EVSTAT3H_ALIAS_EV_S 0
+
+
+#endif // __AUX_EVCTL__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_mac.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_mac.h
new file mode 100644
index 0000000..83dea0b
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_mac.h
@@ -0,0 +1,748 @@
+/******************************************************************************
+* Filename: hw_aux_mac_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_AUX_MAC_H__
+#define __HW_AUX_MAC_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// AUX_MAC component
+//
+//*****************************************************************************
+// Signed Operand 0
+#define AUX_MAC_O_OP0S 0x00000000
+
+// Unsigned Operand 0
+#define AUX_MAC_O_OP0U 0x00000004
+
+// Signed Operand 1 and Multiply
+#define AUX_MAC_O_OP1SMUL 0x00000008
+
+// Unsigned Operand 1 and Multiply
+#define AUX_MAC_O_OP1UMUL 0x0000000C
+
+// Signed Operand 1 and Multiply-Accumulate
+#define AUX_MAC_O_OP1SMAC 0x00000010
+
+// Unsigned Operand 1 and Multiply-Accumulate
+#define AUX_MAC_O_OP1UMAC 0x00000014
+
+// Signed Operand 1 and 16-bit Addition
+#define AUX_MAC_O_OP1SADD16 0x00000018
+
+// Unsigned Operand 1 and 16-bit Addition
+#define AUX_MAC_O_OP1UADD16 0x0000001C
+
+// Signed Operand 1 and 32-bit Addition
+#define AUX_MAC_O_OP1SADD32 0x00000020
+
+// Unsigned Operand 1 and 32-bit Addition
+#define AUX_MAC_O_OP1UADD32 0x00000024
+
+// Count Leading Zero
+#define AUX_MAC_O_CLZ 0x00000028
+
+// Count Leading Sign
+#define AUX_MAC_O_CLS 0x0000002C
+
+// Accumulator Shift
+#define AUX_MAC_O_ACCSHIFT 0x00000030
+
+// Accumulator Reset
+#define AUX_MAC_O_ACCRESET 0x00000034
+
+// Accumulator Bits 15:0
+#define AUX_MAC_O_ACC15_0 0x00000038
+
+// Accumulator Bits 16:1
+#define AUX_MAC_O_ACC16_1 0x0000003C
+
+// Accumulator Bits 17:2
+#define AUX_MAC_O_ACC17_2 0x00000040
+
+// Accumulator Bits 18:3
+#define AUX_MAC_O_ACC18_3 0x00000044
+
+// Accumulator Bits 19:4
+#define AUX_MAC_O_ACC19_4 0x00000048
+
+// Accumulator Bits 20:5
+#define AUX_MAC_O_ACC20_5 0x0000004C
+
+// Accumulator Bits 21:6
+#define AUX_MAC_O_ACC21_6 0x00000050
+
+// Accumulator Bits 22:7
+#define AUX_MAC_O_ACC22_7 0x00000054
+
+// Accumulator Bits 23:8
+#define AUX_MAC_O_ACC23_8 0x00000058
+
+// Accumulator Bits 24:9
+#define AUX_MAC_O_ACC24_9 0x0000005C
+
+// Accumulator Bits 25:10
+#define AUX_MAC_O_ACC25_10 0x00000060
+
+// Accumulator Bits 26:11
+#define AUX_MAC_O_ACC26_11 0x00000064
+
+// Accumulator Bits 27:12
+#define AUX_MAC_O_ACC27_12 0x00000068
+
+// Accumulator Bits 28:13
+#define AUX_MAC_O_ACC28_13 0x0000006C
+
+// Accumulator Bits 29:14
+#define AUX_MAC_O_ACC29_14 0x00000070
+
+// Accumulator Bits 30:15
+#define AUX_MAC_O_ACC30_15 0x00000074
+
+// Accumulator Bits 31:16
+#define AUX_MAC_O_ACC31_16 0x00000078
+
+// Accumulator Bits 32:17
+#define AUX_MAC_O_ACC32_17 0x0000007C
+
+// Accumulator Bits 33:18
+#define AUX_MAC_O_ACC33_18 0x00000080
+
+// Accumulator Bits 34:19
+#define AUX_MAC_O_ACC34_19 0x00000084
+
+// Accumulator Bits 35:20
+#define AUX_MAC_O_ACC35_20 0x00000088
+
+// Accumulator Bits 36:21
+#define AUX_MAC_O_ACC36_21 0x0000008C
+
+// Accumulator Bits 37:22
+#define AUX_MAC_O_ACC37_22 0x00000090
+
+// Accumulator Bits 38:23
+#define AUX_MAC_O_ACC38_23 0x00000094
+
+// Accumulator Bits 39:24
+#define AUX_MAC_O_ACC39_24 0x00000098
+
+// Accumulator Bits 39:32
+#define AUX_MAC_O_ACC39_32 0x0000009C
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_OP0S
+//
+//*****************************************************************************
+// Field: [15:0] OP0_VALUE
+//
+// Signed operand 0.
+//
+// Operand for multiply, multiply-and-accumulate, or 32-bit add operations.
+#define AUX_MAC_OP0S_OP0_VALUE_W 16
+#define AUX_MAC_OP0S_OP0_VALUE_M 0x0000FFFF
+#define AUX_MAC_OP0S_OP0_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_OP0U
+//
+//*****************************************************************************
+// Field: [15:0] OP0_VALUE
+//
+// Unsigned operand 0.
+//
+// Operand for multiply, multiply-and-accumulate, or 32-bit add operations.
+#define AUX_MAC_OP0U_OP0_VALUE_W 16
+#define AUX_MAC_OP0U_OP0_VALUE_M 0x0000FFFF
+#define AUX_MAC_OP0U_OP0_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_OP1SMUL
+//
+//*****************************************************************************
+// Field: [15:0] OP1_VALUE
+//
+// Signed operand 1 and multiplication trigger.
+//
+// Write OP1_VALUE to set signed operand 1 and trigger the following operation:
+//
+// When operand 0 was written to OP0S.OP0_VALUE: ACC = OP1_VALUE *
+// OP0S.OP0_VALUE.
+// When operand 0 was written to OP0U.OP0_VALUE: ACC = OP1_VALUE *
+// OP0U.OP0_VALUE.
+#define AUX_MAC_OP1SMUL_OP1_VALUE_W 16
+#define AUX_MAC_OP1SMUL_OP1_VALUE_M 0x0000FFFF
+#define AUX_MAC_OP1SMUL_OP1_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_OP1UMUL
+//
+//*****************************************************************************
+// Field: [15:0] OP1_VALUE
+//
+// Unsigned operand 1 and multiplication trigger.
+//
+// Write OP1_VALUE to set unsigned operand 1 and trigger the following
+// operation:
+//
+// When operand 0 was written to OP0S.OP0_VALUE: ACC = OP1_VALUE *
+// OP0S.OP0_VALUE.
+// When operand 0 was written to OP0U.OP0_VALUE: ACC = OP1_VALUE *
+// OP0U.OP0_VALUE.
+#define AUX_MAC_OP1UMUL_OP1_VALUE_W 16
+#define AUX_MAC_OP1UMUL_OP1_VALUE_M 0x0000FFFF
+#define AUX_MAC_OP1UMUL_OP1_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_OP1SMAC
+//
+//*****************************************************************************
+// Field: [15:0] OP1_VALUE
+//
+// Signed operand 1 and multiply-accumulation trigger.
+//
+// Write OP1_VALUE to set signed operand 1 and trigger the following operation:
+//
+// When operand 0 was written to OP0S.OP0_VALUE: ACC = ACC + ( OP1_VALUE *
+// OP0S.OP0_VALUE ).
+// When operand 0 was written to OP0U.OP0_VALUE: ACC = ACC + ( OP1_VALUE *
+// OP0U.OP0_VALUE ).
+#define AUX_MAC_OP1SMAC_OP1_VALUE_W 16
+#define AUX_MAC_OP1SMAC_OP1_VALUE_M 0x0000FFFF
+#define AUX_MAC_OP1SMAC_OP1_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_OP1UMAC
+//
+//*****************************************************************************
+// Field: [15:0] OP1_VALUE
+//
+// Unsigned operand 1 and multiply-accumulation trigger.
+//
+// Write OP1_VALUE to set unsigned operand 1 and trigger the following
+// operation:
+//
+// When operand 0 was written to OP0S.OP0_VALUE: ACC = ACC + ( OP1_VALUE *
+// OP0S.OP0_VALUE ).
+// When operand 0 was written to OP0U.OP0_VALUE: ACC = ACC + ( OP1_VALUE *
+// OP0U.OP0_VALUE ).
+#define AUX_MAC_OP1UMAC_OP1_VALUE_W 16
+#define AUX_MAC_OP1UMAC_OP1_VALUE_M 0x0000FFFF
+#define AUX_MAC_OP1UMAC_OP1_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_OP1SADD16
+//
+//*****************************************************************************
+// Field: [15:0] OP1_VALUE
+//
+// Signed operand 1 and 16-bit addition trigger.
+//
+// Write OP1_VALUE to set signed operand 1 and trigger the following operation:
+//
+// ACC = ACC + OP1_VALUE.
+#define AUX_MAC_OP1SADD16_OP1_VALUE_W 16
+#define AUX_MAC_OP1SADD16_OP1_VALUE_M 0x0000FFFF
+#define AUX_MAC_OP1SADD16_OP1_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_OP1UADD16
+//
+//*****************************************************************************
+// Field: [15:0] OP1_VALUE
+//
+// Unsigned operand 1 and 16-bit addition trigger.
+//
+// Write OP1_VALUE to set unsigned operand 1 and trigger the following
+// operation:
+//
+// ACC = ACC + OP1_VALUE.
+#define AUX_MAC_OP1UADD16_OP1_VALUE_W 16
+#define AUX_MAC_OP1UADD16_OP1_VALUE_M 0x0000FFFF
+#define AUX_MAC_OP1UADD16_OP1_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_OP1SADD32
+//
+//*****************************************************************************
+// Field: [15:0] OP1_VALUE
+//
+// Upper half of signed 32-bit operand and addition trigger.
+//
+// Write OP1_VALUE to set upper half of signed 32-bit operand and trigger the
+// following operation:
+//
+// When lower half of 32-bit operand was written to OP0S.OP0_VALUE: ACC = ACC +
+// (( OP1_VALUE << 16) | OP0S.OP0_VALUE ).
+// When lower half of 32-bit operand was written to OP0U.OP0_VALUE: ACC = ACC +
+// (( OP1_VALUE << 16) | OP0U.OP0_VALUE ).
+#define AUX_MAC_OP1SADD32_OP1_VALUE_W 16
+#define AUX_MAC_OP1SADD32_OP1_VALUE_M 0x0000FFFF
+#define AUX_MAC_OP1SADD32_OP1_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_OP1UADD32
+//
+//*****************************************************************************
+// Field: [15:0] OP1_VALUE
+//
+// Upper half of unsigned 32-bit operand and addition trigger.
+//
+// Write OP1_VALUE to set upper half of unsigned 32-bit operand and trigger the
+// following operation:
+//
+// When lower half of 32-bit operand was written to OP0S.OP0_VALUE: ACC = ACC +
+// (( OP1_VALUE << 16) | OP0S.OP0_VALUE ).
+// When lower half of 32-bit operand was written to OP0U.OP0_VALUE: ACC = ACC +
+// (( OP1_VALUE << 16) | OP0U.OP0_VALUE ).
+#define AUX_MAC_OP1UADD32_OP1_VALUE_W 16
+#define AUX_MAC_OP1UADD32_OP1_VALUE_M 0x0000FFFF
+#define AUX_MAC_OP1UADD32_OP1_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_CLZ
+//
+//*****************************************************************************
+// Field: [5:0] VALUE
+//
+// Number of leading zero bits in the accumulator:
+//
+// 0x00: 0 leading zeros.
+// 0x01: 1 leading zero.
+// ...
+// 0x28: 40 leading zeros (accumulator value is 0).
+#define AUX_MAC_CLZ_VALUE_W 6
+#define AUX_MAC_CLZ_VALUE_M 0x0000003F
+#define AUX_MAC_CLZ_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_CLS
+//
+//*****************************************************************************
+// Field: [5:0] VALUE
+//
+// Number of leading sign bits in the accumulator.
+//
+// When MSB of accumulator is 0, VALUE is number of leading zeros, MSB
+// included.
+// When MSB of accumulator is 1, VALUE is number of leading ones, MSB included.
+//
+// VALUE range is 1 thru 40.
+#define AUX_MAC_CLS_VALUE_W 6
+#define AUX_MAC_CLS_VALUE_M 0x0000003F
+#define AUX_MAC_CLS_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_ACCSHIFT
+//
+//*****************************************************************************
+// Field: [2] LSL1
+//
+// Logic shift left by 1 bit.
+//
+// Write 1 to shift the accumulator one bit to the left, 0 inserted at bit 0.
+#define AUX_MAC_ACCSHIFT_LSL1 0x00000004
+#define AUX_MAC_ACCSHIFT_LSL1_BITN 2
+#define AUX_MAC_ACCSHIFT_LSL1_M 0x00000004
+#define AUX_MAC_ACCSHIFT_LSL1_S 2
+
+// Field: [1] LSR1
+//
+// Logic shift right by 1 bit.
+//
+// Write 1 to shift the accumulator one bit to the right, 0 inserted at bit 39.
+#define AUX_MAC_ACCSHIFT_LSR1 0x00000002
+#define AUX_MAC_ACCSHIFT_LSR1_BITN 1
+#define AUX_MAC_ACCSHIFT_LSR1_M 0x00000002
+#define AUX_MAC_ACCSHIFT_LSR1_S 1
+
+// Field: [0] ASR1
+//
+// Arithmetic shift right by 1 bit.
+//
+// Write 1 to shift the accumulator one bit to the right, previous sign bit
+// inserted at bit 39.
+#define AUX_MAC_ACCSHIFT_ASR1 0x00000001
+#define AUX_MAC_ACCSHIFT_ASR1_BITN 0
+#define AUX_MAC_ACCSHIFT_ASR1_M 0x00000001
+#define AUX_MAC_ACCSHIFT_ASR1_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_ACCRESET
+//
+//*****************************************************************************
+// Field: [15:0] TRG
+//
+// Write any value to this register to trigger a reset of all bits in the
+// accumulator.
+#define AUX_MAC_ACCRESET_TRG_W 16
+#define AUX_MAC_ACCRESET_TRG_M 0x0000FFFF
+#define AUX_MAC_ACCRESET_TRG_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_ACC15_0
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Value of the accumulator, bits 15:0.
+//
+// Write VALUE to initialize bits 15:0 of accumulator.
+#define AUX_MAC_ACC15_0_VALUE_W 16
+#define AUX_MAC_ACC15_0_VALUE_M 0x0000FFFF
+#define AUX_MAC_ACC15_0_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_ACC16_1
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Value of the accumulator, bits 16:1.
+#define AUX_MAC_ACC16_1_VALUE_W 16
+#define AUX_MAC_ACC16_1_VALUE_M 0x0000FFFF
+#define AUX_MAC_ACC16_1_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_ACC17_2
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Value of the accumulator, bits 17:2.
+#define AUX_MAC_ACC17_2_VALUE_W 16
+#define AUX_MAC_ACC17_2_VALUE_M 0x0000FFFF
+#define AUX_MAC_ACC17_2_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_ACC18_3
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Value of the accumulator, bits 18:3.
+#define AUX_MAC_ACC18_3_VALUE_W 16
+#define AUX_MAC_ACC18_3_VALUE_M 0x0000FFFF
+#define AUX_MAC_ACC18_3_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_ACC19_4
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Value of the accumulator, bits 19:4.
+#define AUX_MAC_ACC19_4_VALUE_W 16
+#define AUX_MAC_ACC19_4_VALUE_M 0x0000FFFF
+#define AUX_MAC_ACC19_4_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_ACC20_5
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Value of the accumulator, bits 20:5.
+#define AUX_MAC_ACC20_5_VALUE_W 16
+#define AUX_MAC_ACC20_5_VALUE_M 0x0000FFFF
+#define AUX_MAC_ACC20_5_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_ACC21_6
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Value of the accumulator, bits 21:6.
+#define AUX_MAC_ACC21_6_VALUE_W 16
+#define AUX_MAC_ACC21_6_VALUE_M 0x0000FFFF
+#define AUX_MAC_ACC21_6_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_ACC22_7
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Value of the accumulator, bits 22:7.
+#define AUX_MAC_ACC22_7_VALUE_W 16
+#define AUX_MAC_ACC22_7_VALUE_M 0x0000FFFF
+#define AUX_MAC_ACC22_7_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_ACC23_8
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Value of the accumulator, bits 23:8.
+#define AUX_MAC_ACC23_8_VALUE_W 16
+#define AUX_MAC_ACC23_8_VALUE_M 0x0000FFFF
+#define AUX_MAC_ACC23_8_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_ACC24_9
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Value of the accumulator, bits 24:9.
+#define AUX_MAC_ACC24_9_VALUE_W 16
+#define AUX_MAC_ACC24_9_VALUE_M 0x0000FFFF
+#define AUX_MAC_ACC24_9_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_ACC25_10
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Value of the accumulator, bits 25:10.
+#define AUX_MAC_ACC25_10_VALUE_W 16
+#define AUX_MAC_ACC25_10_VALUE_M 0x0000FFFF
+#define AUX_MAC_ACC25_10_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_ACC26_11
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Value of the accumulator, bits 26:11.
+#define AUX_MAC_ACC26_11_VALUE_W 16
+#define AUX_MAC_ACC26_11_VALUE_M 0x0000FFFF
+#define AUX_MAC_ACC26_11_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_ACC27_12
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Value of the accumulator, bits 27:12.
+#define AUX_MAC_ACC27_12_VALUE_W 16
+#define AUX_MAC_ACC27_12_VALUE_M 0x0000FFFF
+#define AUX_MAC_ACC27_12_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_ACC28_13
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Value of the accumulator, bits 28:13.
+#define AUX_MAC_ACC28_13_VALUE_W 16
+#define AUX_MAC_ACC28_13_VALUE_M 0x0000FFFF
+#define AUX_MAC_ACC28_13_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_ACC29_14
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Value of the accumulator, bits 29:14.
+#define AUX_MAC_ACC29_14_VALUE_W 16
+#define AUX_MAC_ACC29_14_VALUE_M 0x0000FFFF
+#define AUX_MAC_ACC29_14_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_ACC30_15
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Value of the accumulator, bits 30:15.
+#define AUX_MAC_ACC30_15_VALUE_W 16
+#define AUX_MAC_ACC30_15_VALUE_M 0x0000FFFF
+#define AUX_MAC_ACC30_15_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_ACC31_16
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Value of the accumulator, bits 31:16.
+//
+// Write VALUE to initialize bits 31:16 of accumulator.
+#define AUX_MAC_ACC31_16_VALUE_W 16
+#define AUX_MAC_ACC31_16_VALUE_M 0x0000FFFF
+#define AUX_MAC_ACC31_16_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_ACC32_17
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Value of the accumulator, bits 32:17.
+#define AUX_MAC_ACC32_17_VALUE_W 16
+#define AUX_MAC_ACC32_17_VALUE_M 0x0000FFFF
+#define AUX_MAC_ACC32_17_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_ACC33_18
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Value of the accumulator, bits 33:18.
+#define AUX_MAC_ACC33_18_VALUE_W 16
+#define AUX_MAC_ACC33_18_VALUE_M 0x0000FFFF
+#define AUX_MAC_ACC33_18_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_ACC34_19
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Value of the accumulator, bits 34:19.
+#define AUX_MAC_ACC34_19_VALUE_W 16
+#define AUX_MAC_ACC34_19_VALUE_M 0x0000FFFF
+#define AUX_MAC_ACC34_19_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_ACC35_20
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Value of the accumulator, bits 35:20.
+#define AUX_MAC_ACC35_20_VALUE_W 16
+#define AUX_MAC_ACC35_20_VALUE_M 0x0000FFFF
+#define AUX_MAC_ACC35_20_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_ACC36_21
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Value of the accumulator, bits 36:21.
+#define AUX_MAC_ACC36_21_VALUE_W 16
+#define AUX_MAC_ACC36_21_VALUE_M 0x0000FFFF
+#define AUX_MAC_ACC36_21_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_ACC37_22
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Value of the accumulator, bits 37:22.
+#define AUX_MAC_ACC37_22_VALUE_W 16
+#define AUX_MAC_ACC37_22_VALUE_M 0x0000FFFF
+#define AUX_MAC_ACC37_22_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_ACC38_23
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Value of the accumulator, bits 38:23.
+#define AUX_MAC_ACC38_23_VALUE_W 16
+#define AUX_MAC_ACC38_23_VALUE_M 0x0000FFFF
+#define AUX_MAC_ACC38_23_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_ACC39_24
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Value of the accumulator, bits 39:24.
+#define AUX_MAC_ACC39_24_VALUE_W 16
+#define AUX_MAC_ACC39_24_VALUE_M 0x0000FFFF
+#define AUX_MAC_ACC39_24_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_MAC_O_ACC39_32
+//
+//*****************************************************************************
+// Field: [7:0] VALUE
+//
+// Value of the accumulator, bits 39:32.
+//
+// Write VALUE to initialize bits 39:32 of accumulator.
+#define AUX_MAC_ACC39_32_VALUE_W 8
+#define AUX_MAC_ACC39_32_VALUE_M 0x000000FF
+#define AUX_MAC_ACC39_32_VALUE_S 0
+
+
+#endif // __AUX_MAC__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_ram.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_ram.h
new file mode 100644
index 0000000..6a20b91
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_ram.h
@@ -0,0 +1,48 @@
+/******************************************************************************
+* Filename: hw_aux_ram_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_AUX_RAM_H__
+#define __HW_AUX_RAM_H__
+
+
+#define AUX_RAM_O_BANK0 0x00000000
+#define AUX_RAM_BANK0_BYTE_SIZE 4096
+
+#define AUX_RAM_TOT_BYTE_SIZE 4096
+
+
+
+#endif // __HW_AUX_RAM__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_sce.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_sce.h
new file mode 100644
index 0000000..39f1758
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_sce.h
@@ -0,0 +1,398 @@
+/******************************************************************************
+* Filename: hw_aux_sce_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_AUX_SCE_H__
+#define __HW_AUX_SCE_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// AUX_SCE component
+//
+//*****************************************************************************
+// Internal
+#define AUX_SCE_O_CTL 0x00000000
+
+// Internal
+#define AUX_SCE_O_FETCHSTAT 0x00000004
+
+// Internal
+#define AUX_SCE_O_CPUSTAT 0x00000008
+
+// Internal
+#define AUX_SCE_O_WUSTAT 0x0000000C
+
+// Internal
+#define AUX_SCE_O_REG1_0 0x00000010
+
+// Internal
+#define AUX_SCE_O_REG3_2 0x00000014
+
+// Internal
+#define AUX_SCE_O_REG5_4 0x00000018
+
+// Internal
+#define AUX_SCE_O_REG7_6 0x0000001C
+
+// Internal
+#define AUX_SCE_O_LOOPADDR 0x00000020
+
+// Internal
+#define AUX_SCE_O_LOOPCNT 0x00000024
+
+//*****************************************************************************
+//
+// Register: AUX_SCE_O_CTL
+//
+//*****************************************************************************
+// Field: [31:24] FORCE_EV_LOW
+//
+// Internal. Only to be used through TI provided API.
+#define AUX_SCE_CTL_FORCE_EV_LOW_W 8
+#define AUX_SCE_CTL_FORCE_EV_LOW_M 0xFF000000
+#define AUX_SCE_CTL_FORCE_EV_LOW_S 24
+
+// Field: [23:16] FORCE_EV_HIGH
+//
+// Internal. Only to be used through TI provided API.
+#define AUX_SCE_CTL_FORCE_EV_HIGH_W 8
+#define AUX_SCE_CTL_FORCE_EV_HIGH_M 0x00FF0000
+#define AUX_SCE_CTL_FORCE_EV_HIGH_S 16
+
+// Field: [15:8] RESET_VECTOR
+//
+// Internal. Only to be used through TI provided API.
+#define AUX_SCE_CTL_RESET_VECTOR_W 8
+#define AUX_SCE_CTL_RESET_VECTOR_M 0x0000FF00
+#define AUX_SCE_CTL_RESET_VECTOR_S 8
+
+// Field: [6] DBG_FREEZE_EN
+//
+// Internal. Only to be used through TI provided API.
+#define AUX_SCE_CTL_DBG_FREEZE_EN 0x00000040
+#define AUX_SCE_CTL_DBG_FREEZE_EN_BITN 6
+#define AUX_SCE_CTL_DBG_FREEZE_EN_M 0x00000040
+#define AUX_SCE_CTL_DBG_FREEZE_EN_S 6
+
+// Field: [5] FORCE_WU_LOW
+//
+// Internal. Only to be used through TI provided API.
+#define AUX_SCE_CTL_FORCE_WU_LOW 0x00000020
+#define AUX_SCE_CTL_FORCE_WU_LOW_BITN 5
+#define AUX_SCE_CTL_FORCE_WU_LOW_M 0x00000020
+#define AUX_SCE_CTL_FORCE_WU_LOW_S 5
+
+// Field: [4] FORCE_WU_HIGH
+//
+// Internal. Only to be used through TI provided API.
+#define AUX_SCE_CTL_FORCE_WU_HIGH 0x00000010
+#define AUX_SCE_CTL_FORCE_WU_HIGH_BITN 4
+#define AUX_SCE_CTL_FORCE_WU_HIGH_M 0x00000010
+#define AUX_SCE_CTL_FORCE_WU_HIGH_S 4
+
+// Field: [3] RESTART
+//
+// Internal. Only to be used through TI provided API.
+#define AUX_SCE_CTL_RESTART 0x00000008
+#define AUX_SCE_CTL_RESTART_BITN 3
+#define AUX_SCE_CTL_RESTART_M 0x00000008
+#define AUX_SCE_CTL_RESTART_S 3
+
+// Field: [2] SINGLE_STEP
+//
+// Internal. Only to be used through TI provided API.
+#define AUX_SCE_CTL_SINGLE_STEP 0x00000004
+#define AUX_SCE_CTL_SINGLE_STEP_BITN 2
+#define AUX_SCE_CTL_SINGLE_STEP_M 0x00000004
+#define AUX_SCE_CTL_SINGLE_STEP_S 2
+
+// Field: [1] SUSPEND
+//
+// Internal. Only to be used through TI provided API.
+#define AUX_SCE_CTL_SUSPEND 0x00000002
+#define AUX_SCE_CTL_SUSPEND_BITN 1
+#define AUX_SCE_CTL_SUSPEND_M 0x00000002
+#define AUX_SCE_CTL_SUSPEND_S 1
+
+// Field: [0] CLK_EN
+//
+// Internal. Only to be used through TI provided API.
+#define AUX_SCE_CTL_CLK_EN 0x00000001
+#define AUX_SCE_CTL_CLK_EN_BITN 0
+#define AUX_SCE_CTL_CLK_EN_M 0x00000001
+#define AUX_SCE_CTL_CLK_EN_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SCE_O_FETCHSTAT
+//
+//*****************************************************************************
+// Field: [31:16] OPCODE
+//
+// Internal. Only to be used through TI provided API.
+#define AUX_SCE_FETCHSTAT_OPCODE_W 16
+#define AUX_SCE_FETCHSTAT_OPCODE_M 0xFFFF0000
+#define AUX_SCE_FETCHSTAT_OPCODE_S 16
+
+// Field: [15:0] PC
+//
+// Internal. Only to be used through TI provided API.
+#define AUX_SCE_FETCHSTAT_PC_W 16
+#define AUX_SCE_FETCHSTAT_PC_M 0x0000FFFF
+#define AUX_SCE_FETCHSTAT_PC_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SCE_O_CPUSTAT
+//
+//*****************************************************************************
+// Field: [11] BUS_ERROR
+//
+// Internal. Only to be used through TI provided API.
+#define AUX_SCE_CPUSTAT_BUS_ERROR 0x00000800
+#define AUX_SCE_CPUSTAT_BUS_ERROR_BITN 11
+#define AUX_SCE_CPUSTAT_BUS_ERROR_M 0x00000800
+#define AUX_SCE_CPUSTAT_BUS_ERROR_S 11
+
+// Field: [10] SLEEP
+//
+// Internal. Only to be used through TI provided API.
+#define AUX_SCE_CPUSTAT_SLEEP 0x00000400
+#define AUX_SCE_CPUSTAT_SLEEP_BITN 10
+#define AUX_SCE_CPUSTAT_SLEEP_M 0x00000400
+#define AUX_SCE_CPUSTAT_SLEEP_S 10
+
+// Field: [9] WEV
+//
+// Internal. Only to be used through TI provided API.
+#define AUX_SCE_CPUSTAT_WEV 0x00000200
+#define AUX_SCE_CPUSTAT_WEV_BITN 9
+#define AUX_SCE_CPUSTAT_WEV_M 0x00000200
+#define AUX_SCE_CPUSTAT_WEV_S 9
+
+// Field: [8] HALTED
+//
+// Internal. Only to be used through TI provided API.
+#define AUX_SCE_CPUSTAT_HALTED 0x00000100
+#define AUX_SCE_CPUSTAT_HALTED_BITN 8
+#define AUX_SCE_CPUSTAT_HALTED_M 0x00000100
+#define AUX_SCE_CPUSTAT_HALTED_S 8
+
+// Field: [3] V_FLAG
+//
+// Internal. Only to be used through TI provided API.
+#define AUX_SCE_CPUSTAT_V_FLAG 0x00000008
+#define AUX_SCE_CPUSTAT_V_FLAG_BITN 3
+#define AUX_SCE_CPUSTAT_V_FLAG_M 0x00000008
+#define AUX_SCE_CPUSTAT_V_FLAG_S 3
+
+// Field: [2] C_FLAG
+//
+// Internal. Only to be used through TI provided API.
+#define AUX_SCE_CPUSTAT_C_FLAG 0x00000004
+#define AUX_SCE_CPUSTAT_C_FLAG_BITN 2
+#define AUX_SCE_CPUSTAT_C_FLAG_M 0x00000004
+#define AUX_SCE_CPUSTAT_C_FLAG_S 2
+
+// Field: [1] N_FLAG
+//
+// Internal. Only to be used through TI provided API.
+#define AUX_SCE_CPUSTAT_N_FLAG 0x00000002
+#define AUX_SCE_CPUSTAT_N_FLAG_BITN 1
+#define AUX_SCE_CPUSTAT_N_FLAG_M 0x00000002
+#define AUX_SCE_CPUSTAT_N_FLAG_S 1
+
+// Field: [0] Z_FLAG
+//
+// Internal. Only to be used through TI provided API.
+#define AUX_SCE_CPUSTAT_Z_FLAG 0x00000001
+#define AUX_SCE_CPUSTAT_Z_FLAG_BITN 0
+#define AUX_SCE_CPUSTAT_Z_FLAG_M 0x00000001
+#define AUX_SCE_CPUSTAT_Z_FLAG_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SCE_O_WUSTAT
+//
+//*****************************************************************************
+// Field: [18:16] EXC_VECTOR
+//
+// Internal. Only to be used through TI provided API.
+#define AUX_SCE_WUSTAT_EXC_VECTOR_W 3
+#define AUX_SCE_WUSTAT_EXC_VECTOR_M 0x00070000
+#define AUX_SCE_WUSTAT_EXC_VECTOR_S 16
+
+// Field: [8] WU_SIGNAL
+//
+// Internal. Only to be used through TI provided API.
+#define AUX_SCE_WUSTAT_WU_SIGNAL 0x00000100
+#define AUX_SCE_WUSTAT_WU_SIGNAL_BITN 8
+#define AUX_SCE_WUSTAT_WU_SIGNAL_M 0x00000100
+#define AUX_SCE_WUSTAT_WU_SIGNAL_S 8
+
+// Field: [7:0] EV_SIGNALS
+//
+// Internal. Only to be used through TI provided API.
+// ENUMs:
+// SCEWEV_PROG Internal. Only to be used through TI provided API.
+// AUX_ADC_FIFO_NOT_EMPTY Internal. Only to be used through TI provided API.
+// AUX_TIMER1_EV_OR_IDLE Internal. Only to be used through TI provided API.
+// AUX_TIMER0_EV_OR_IDLE Internal. Only to be used through TI provided API.
+// AUX_TDC_DONE Internal. Only to be used through TI provided API.
+// AUX_COMPB Internal. Only to be used through TI provided API.
+// AUX_COMPA Internal. Only to be used through TI provided API.
+// AUX_PROG_DLY_IDLE Internal. Only to be used through TI provided API.
+#define AUX_SCE_WUSTAT_EV_SIGNALS_W 8
+#define AUX_SCE_WUSTAT_EV_SIGNALS_M 0x000000FF
+#define AUX_SCE_WUSTAT_EV_SIGNALS_S 0
+#define AUX_SCE_WUSTAT_EV_SIGNALS_SCEWEV_PROG 0x00000080
+#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_ADC_FIFO_NOT_EMPTY 0x00000040
+#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_TIMER1_EV_OR_IDLE 0x00000020
+#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_TIMER0_EV_OR_IDLE 0x00000010
+#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_TDC_DONE 0x00000008
+#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_COMPB 0x00000004
+#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_COMPA 0x00000002
+#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_PROG_DLY_IDLE 0x00000001
+
+//*****************************************************************************
+//
+// Register: AUX_SCE_O_REG1_0
+//
+//*****************************************************************************
+// Field: [31:16] REG1
+//
+// Internal. Only to be used through TI provided API.
+#define AUX_SCE_REG1_0_REG1_W 16
+#define AUX_SCE_REG1_0_REG1_M 0xFFFF0000
+#define AUX_SCE_REG1_0_REG1_S 16
+
+// Field: [15:0] REG0
+//
+// Internal. Only to be used through TI provided API.
+#define AUX_SCE_REG1_0_REG0_W 16
+#define AUX_SCE_REG1_0_REG0_M 0x0000FFFF
+#define AUX_SCE_REG1_0_REG0_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SCE_O_REG3_2
+//
+//*****************************************************************************
+// Field: [31:16] REG3
+//
+// Internal. Only to be used through TI provided API.
+#define AUX_SCE_REG3_2_REG3_W 16
+#define AUX_SCE_REG3_2_REG3_M 0xFFFF0000
+#define AUX_SCE_REG3_2_REG3_S 16
+
+// Field: [15:0] REG2
+//
+// Internal. Only to be used through TI provided API.
+#define AUX_SCE_REG3_2_REG2_W 16
+#define AUX_SCE_REG3_2_REG2_M 0x0000FFFF
+#define AUX_SCE_REG3_2_REG2_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SCE_O_REG5_4
+//
+//*****************************************************************************
+// Field: [31:16] REG5
+//
+// Internal. Only to be used through TI provided API.
+#define AUX_SCE_REG5_4_REG5_W 16
+#define AUX_SCE_REG5_4_REG5_M 0xFFFF0000
+#define AUX_SCE_REG5_4_REG5_S 16
+
+// Field: [15:0] REG4
+//
+// Internal. Only to be used through TI provided API.
+#define AUX_SCE_REG5_4_REG4_W 16
+#define AUX_SCE_REG5_4_REG4_M 0x0000FFFF
+#define AUX_SCE_REG5_4_REG4_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SCE_O_REG7_6
+//
+//*****************************************************************************
+// Field: [31:16] REG7
+//
+// Internal. Only to be used through TI provided API.
+#define AUX_SCE_REG7_6_REG7_W 16
+#define AUX_SCE_REG7_6_REG7_M 0xFFFF0000
+#define AUX_SCE_REG7_6_REG7_S 16
+
+// Field: [15:0] REG6
+//
+// Internal. Only to be used through TI provided API.
+#define AUX_SCE_REG7_6_REG6_W 16
+#define AUX_SCE_REG7_6_REG6_M 0x0000FFFF
+#define AUX_SCE_REG7_6_REG6_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SCE_O_LOOPADDR
+//
+//*****************************************************************************
+// Field: [31:16] STOP
+//
+// Internal. Only to be used through TI provided API.
+#define AUX_SCE_LOOPADDR_STOP_W 16
+#define AUX_SCE_LOOPADDR_STOP_M 0xFFFF0000
+#define AUX_SCE_LOOPADDR_STOP_S 16
+
+// Field: [15:0] START
+//
+// Internal. Only to be used through TI provided API.
+#define AUX_SCE_LOOPADDR_START_W 16
+#define AUX_SCE_LOOPADDR_START_M 0x0000FFFF
+#define AUX_SCE_LOOPADDR_START_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SCE_O_LOOPCNT
+//
+//*****************************************************************************
+// Field: [7:0] ITER_LEFT
+//
+// Internal. Only to be used through TI provided API.
+#define AUX_SCE_LOOPCNT_ITER_LEFT_W 8
+#define AUX_SCE_LOOPCNT_ITER_LEFT_M 0x000000FF
+#define AUX_SCE_LOOPCNT_ITER_LEFT_S 0
+
+
+#endif // __AUX_SCE__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_smph.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_smph.h
new file mode 100644
index 0000000..0bee0c5
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_smph.h
@@ -0,0 +1,282 @@
+/******************************************************************************
+* Filename: hw_aux_smph_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_AUX_SMPH_H__
+#define __HW_AUX_SMPH_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// AUX_SMPH component
+//
+//*****************************************************************************
+// Semaphore 0
+#define AUX_SMPH_O_SMPH0 0x00000000
+
+// Semaphore 1
+#define AUX_SMPH_O_SMPH1 0x00000004
+
+// Semaphore 2
+#define AUX_SMPH_O_SMPH2 0x00000008
+
+// Semaphore 3
+#define AUX_SMPH_O_SMPH3 0x0000000C
+
+// Semaphore 4
+#define AUX_SMPH_O_SMPH4 0x00000010
+
+// Semaphore 5
+#define AUX_SMPH_O_SMPH5 0x00000014
+
+// Semaphore 6
+#define AUX_SMPH_O_SMPH6 0x00000018
+
+// Semaphore 7
+#define AUX_SMPH_O_SMPH7 0x0000001C
+
+// Auto Take
+#define AUX_SMPH_O_AUTOTAKE 0x00000020
+
+//*****************************************************************************
+//
+// Register: AUX_SMPH_O_SMPH0
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Request or release of semaphore.
+//
+// Request by read:
+//
+// 0: Semaphore not available.
+// 1: Semaphore granted.
+//
+// Release by write:
+//
+// 0: Do not use.
+// 1: Release semaphore.
+#define AUX_SMPH_SMPH0_STAT 0x00000001
+#define AUX_SMPH_SMPH0_STAT_BITN 0
+#define AUX_SMPH_SMPH0_STAT_M 0x00000001
+#define AUX_SMPH_SMPH0_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SMPH_O_SMPH1
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Request or release of semaphore.
+//
+// Request by read:
+//
+// 0: Semaphore not available.
+// 1: Semaphore granted.
+//
+// Release by write:
+//
+// 0: Do not use.
+// 1: Release semaphore.
+#define AUX_SMPH_SMPH1_STAT 0x00000001
+#define AUX_SMPH_SMPH1_STAT_BITN 0
+#define AUX_SMPH_SMPH1_STAT_M 0x00000001
+#define AUX_SMPH_SMPH1_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SMPH_O_SMPH2
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Request or release of semaphore.
+//
+// Request by read:
+//
+// 0: Semaphore not available.
+// 1: Semaphore granted.
+//
+// Release by write:
+//
+// 0: Do not use.
+// 1: Release semaphore.
+#define AUX_SMPH_SMPH2_STAT 0x00000001
+#define AUX_SMPH_SMPH2_STAT_BITN 0
+#define AUX_SMPH_SMPH2_STAT_M 0x00000001
+#define AUX_SMPH_SMPH2_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SMPH_O_SMPH3
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Request or release of semaphore.
+//
+// Request by read:
+//
+// 0: Semaphore not available.
+// 1: Semaphore granted.
+//
+// Release by write:
+//
+// 0: Do not use.
+// 1: Release semaphore.
+#define AUX_SMPH_SMPH3_STAT 0x00000001
+#define AUX_SMPH_SMPH3_STAT_BITN 0
+#define AUX_SMPH_SMPH3_STAT_M 0x00000001
+#define AUX_SMPH_SMPH3_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SMPH_O_SMPH4
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Request or release of semaphore.
+//
+// Request by read:
+//
+// 0: Semaphore not available.
+// 1: Semaphore granted.
+//
+// Release by write:
+//
+// 0: Do not use.
+// 1: Release semaphore.
+#define AUX_SMPH_SMPH4_STAT 0x00000001
+#define AUX_SMPH_SMPH4_STAT_BITN 0
+#define AUX_SMPH_SMPH4_STAT_M 0x00000001
+#define AUX_SMPH_SMPH4_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SMPH_O_SMPH5
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Request or release of semaphore.
+//
+// Request by read:
+//
+// 0: Semaphore not available.
+// 1: Semaphore granted.
+//
+// Release by write:
+//
+// 0: Do not use.
+// 1: Release semaphore.
+#define AUX_SMPH_SMPH5_STAT 0x00000001
+#define AUX_SMPH_SMPH5_STAT_BITN 0
+#define AUX_SMPH_SMPH5_STAT_M 0x00000001
+#define AUX_SMPH_SMPH5_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SMPH_O_SMPH6
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Request or release of semaphore.
+//
+// Request by read:
+//
+// 0: Semaphore not available.
+// 1: Semaphore granted.
+//
+// Release by write:
+//
+// 0: Do not use.
+// 1: Release semaphore.
+#define AUX_SMPH_SMPH6_STAT 0x00000001
+#define AUX_SMPH_SMPH6_STAT_BITN 0
+#define AUX_SMPH_SMPH6_STAT_M 0x00000001
+#define AUX_SMPH_SMPH6_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SMPH_O_SMPH7
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Request or release of semaphore.
+//
+// Request by read:
+//
+// 0: Semaphore not available.
+// 1: Semaphore granted.
+//
+// Release by write:
+//
+// 0: Do not use.
+// 1: Release semaphore.
+#define AUX_SMPH_SMPH7_STAT 0x00000001
+#define AUX_SMPH_SMPH7_STAT_BITN 0
+#define AUX_SMPH_SMPH7_STAT_M 0x00000001
+#define AUX_SMPH_SMPH7_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SMPH_O_AUTOTAKE
+//
+//*****************************************************************************
+// Field: [2:0] SMPH_ID
+//
+// Write the semaphore ID,0x0-0x7, to SMPH_ID to request this semaphore until
+// it is granted.
+//
+// When semaphore SMPH_ID is granted, event
+// AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE becomes 1.
+//
+// The event becomes 0 when software releases the semaphore or writes a new
+// value to SMPH_ID.
+//
+// To avoid corrupted semaphores:
+// - Usage of this functionality must be restricted to one CPU core.
+// - Software must wait until AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE is 1
+// before it writes a new value to SMPH_ID.
+#define AUX_SMPH_AUTOTAKE_SMPH_ID_W 3
+#define AUX_SMPH_AUTOTAKE_SMPH_ID_M 0x00000007
+#define AUX_SMPH_AUTOTAKE_SMPH_ID_S 0
+
+
+#endif // __AUX_SMPH__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_spim.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_spim.h
new file mode 100644
index 0000000..c2f354d
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_spim.h
@@ -0,0 +1,239 @@
+/******************************************************************************
+* Filename: hw_aux_spim_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_AUX_SPIM_H__
+#define __HW_AUX_SPIM_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// AUX_SPIM component
+//
+//*****************************************************************************
+// SPI Master Configuration
+#define AUX_SPIM_O_SPIMCFG 0x00000000
+
+// MISO Configuration
+#define AUX_SPIM_O_MISOCFG 0x00000004
+
+// MOSI Control
+#define AUX_SPIM_O_MOSICTL 0x00000008
+
+// Transmit 8 Bit
+#define AUX_SPIM_O_TX8 0x0000000C
+
+// Transmit 16 Bit
+#define AUX_SPIM_O_TX16 0x00000010
+
+// Receive 8 Bit
+#define AUX_SPIM_O_RX8 0x00000014
+
+// Receive 16 Bit
+#define AUX_SPIM_O_RX16 0x00000018
+
+// SCLK Idle
+#define AUX_SPIM_O_SCLKIDLE 0x0000001C
+
+// Data Idle
+#define AUX_SPIM_O_DATAIDLE 0x00000020
+
+//*****************************************************************************
+//
+// Register: AUX_SPIM_O_SPIMCFG
+//
+//*****************************************************************************
+// Field: [7:2] DIV
+//
+// SCLK divider.
+//
+// Peripheral clock frequency division gives the SCLK clock frequency. The
+// division factor equals (2 * (DIV+1)):
+//
+// 0x00: Divide by 2.
+// 0x01: Divide by 4.
+// 0x02: Divide by 6.
+// ...
+// 0x3F: Divide by 128.
+#define AUX_SPIM_SPIMCFG_DIV_W 6
+#define AUX_SPIM_SPIMCFG_DIV_M 0x000000FC
+#define AUX_SPIM_SPIMCFG_DIV_S 2
+
+// Field: [1] PHA
+//
+// Phase of the MOSI and MISO data signals.
+//
+// 0: Sample MISO at leading (odd) edges and shift MOSI at trailing (even)
+// edges of SCLK.
+// 1: Sample MISO at trailing (even) edges and shift MOSI at leading (odd)
+// edges of SCLK.
+#define AUX_SPIM_SPIMCFG_PHA 0x00000002
+#define AUX_SPIM_SPIMCFG_PHA_BITN 1
+#define AUX_SPIM_SPIMCFG_PHA_M 0x00000002
+#define AUX_SPIM_SPIMCFG_PHA_S 1
+
+// Field: [0] POL
+//
+// Polarity of the SCLK signal.
+//
+// 0: SCLK is low when idle, first clock edge rises.
+// 1: SCLK is high when idle, first clock edge falls.
+#define AUX_SPIM_SPIMCFG_POL 0x00000001
+#define AUX_SPIM_SPIMCFG_POL_BITN 0
+#define AUX_SPIM_SPIMCFG_POL_M 0x00000001
+#define AUX_SPIM_SPIMCFG_POL_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SPIM_O_MISOCFG
+//
+//*****************************************************************************
+// Field: [4:0] AUXIO
+//
+// AUXIO to MISO mux.
+//
+// Select the AUXIO pin that connects to MISO.
+#define AUX_SPIM_MISOCFG_AUXIO_W 5
+#define AUX_SPIM_MISOCFG_AUXIO_M 0x0000001F
+#define AUX_SPIM_MISOCFG_AUXIO_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SPIM_O_MOSICTL
+//
+//*****************************************************************************
+// Field: [0] VALUE
+//
+// MOSI level control.
+//
+// 0: Set MOSI low.
+// 1: Set MOSI high.
+#define AUX_SPIM_MOSICTL_VALUE 0x00000001
+#define AUX_SPIM_MOSICTL_VALUE_BITN 0
+#define AUX_SPIM_MOSICTL_VALUE_M 0x00000001
+#define AUX_SPIM_MOSICTL_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SPIM_O_TX8
+//
+//*****************************************************************************
+// Field: [7:0] DATA
+//
+// 8 bit data transfer.
+//
+// Write DATA to start transfer, MSB first. When transfer completes, MOSI stays
+// at the value of LSB.
+#define AUX_SPIM_TX8_DATA_W 8
+#define AUX_SPIM_TX8_DATA_M 0x000000FF
+#define AUX_SPIM_TX8_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SPIM_O_TX16
+//
+//*****************************************************************************
+// Field: [15:0] DATA
+//
+// 16 bit data transfer.
+//
+// Write DATA to start transfer, MSB first. When transfer completes, MOSI stays
+// at the value of LSB.
+#define AUX_SPIM_TX16_DATA_W 16
+#define AUX_SPIM_TX16_DATA_M 0x0000FFFF
+#define AUX_SPIM_TX16_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SPIM_O_RX8
+//
+//*****************************************************************************
+// Field: [7:0] DATA
+//
+// Latest 8 bits received on MISO.
+#define AUX_SPIM_RX8_DATA_W 8
+#define AUX_SPIM_RX8_DATA_M 0x000000FF
+#define AUX_SPIM_RX8_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SPIM_O_RX16
+//
+//*****************************************************************************
+// Field: [15:0] DATA
+//
+// Latest 16 bits received on MISO.
+#define AUX_SPIM_RX16_DATA_W 16
+#define AUX_SPIM_RX16_DATA_M 0x0000FFFF
+#define AUX_SPIM_RX16_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SPIM_O_SCLKIDLE
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Wait for SCLK idle.
+//
+// Read operation stalls until SCLK is idle with no remaining clock edges. Read
+// then returns 1.
+//
+// AUX_SCE can use this to control CS deassertion.
+#define AUX_SPIM_SCLKIDLE_STAT 0x00000001
+#define AUX_SPIM_SCLKIDLE_STAT_BITN 0
+#define AUX_SPIM_SCLKIDLE_STAT_M 0x00000001
+#define AUX_SPIM_SCLKIDLE_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SPIM_O_DATAIDLE
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Wait for data idle.
+//
+// Read operation stalls until the SCLK period associated with LSB transmission
+// completes. Read then returns 1.
+//
+// AUX_SCE can use this to control CS deassertion.
+#define AUX_SPIM_DATAIDLE_STAT 0x00000001
+#define AUX_SPIM_DATAIDLE_STAT_BITN 0
+#define AUX_SPIM_DATAIDLE_STAT_M 0x00000001
+#define AUX_SPIM_DATAIDLE_STAT_S 0
+
+
+#endif // __AUX_SPIM__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_sysif.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_sysif.h
new file mode 100644
index 0000000..a3de3f9
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_sysif.h
@@ -0,0 +1,2088 @@
+/******************************************************************************
+* Filename: hw_aux_sysif_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_AUX_SYSIF_H__
+#define __HW_AUX_SYSIF_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// AUX_SYSIF component
+//
+//*****************************************************************************
+// Operational Mode Request
+#define AUX_SYSIF_O_OPMODEREQ 0x00000000
+
+// Operational Mode Acknowledgement
+#define AUX_SYSIF_O_OPMODEACK 0x00000004
+
+// Programmable Wakeup 0 Configuration
+#define AUX_SYSIF_O_PROGWU0CFG 0x00000008
+
+// Programmable Wakeup 1 Configuration
+#define AUX_SYSIF_O_PROGWU1CFG 0x0000000C
+
+// Programmable Wakeup 2 Configuration
+#define AUX_SYSIF_O_PROGWU2CFG 0x00000010
+
+// Programmable Wakeup 3 Configuration
+#define AUX_SYSIF_O_PROGWU3CFG 0x00000014
+
+// Software Wakeup Triggers
+#define AUX_SYSIF_O_SWWUTRIG 0x00000018
+
+// Wakeup Flags
+#define AUX_SYSIF_O_WUFLAGS 0x0000001C
+
+// Wakeup Flags Clear
+#define AUX_SYSIF_O_WUFLAGSCLR 0x00000020
+
+// Wakeup Gate
+#define AUX_SYSIF_O_WUGATE 0x00000024
+
+// Vector Configuration 0
+#define AUX_SYSIF_O_VECCFG0 0x00000028
+
+// Vector Configuration 1
+#define AUX_SYSIF_O_VECCFG1 0x0000002C
+
+// Vector Configuration 2
+#define AUX_SYSIF_O_VECCFG2 0x00000030
+
+// Vector Configuration 3
+#define AUX_SYSIF_O_VECCFG3 0x00000034
+
+// Vector Configuration 4
+#define AUX_SYSIF_O_VECCFG4 0x00000038
+
+// Vector Configuration 5
+#define AUX_SYSIF_O_VECCFG5 0x0000003C
+
+// Vector Configuration 6
+#define AUX_SYSIF_O_VECCFG6 0x00000040
+
+// Vector Configuration 7
+#define AUX_SYSIF_O_VECCFG7 0x00000044
+
+// Event Synchronization Rate
+#define AUX_SYSIF_O_EVSYNCRATE 0x00000048
+
+// Peripheral Operational Rate
+#define AUX_SYSIF_O_PEROPRATE 0x0000004C
+
+// ADC Clock Control
+#define AUX_SYSIF_O_ADCCLKCTL 0x00000050
+
+// TDC Counter Clock Control
+#define AUX_SYSIF_O_TDCCLKCTL 0x00000054
+
+// TDC Reference Clock Control
+#define AUX_SYSIF_O_TDCREFCLKCTL 0x00000058
+
+// AUX_TIMER2 Clock Control
+#define AUX_SYSIF_O_TIMER2CLKCTL 0x0000005C
+
+// AUX_TIMER2 Clock Status
+#define AUX_SYSIF_O_TIMER2CLKSTAT 0x00000060
+
+// AUX_TIMER2 Clock Switch
+#define AUX_SYSIF_O_TIMER2CLKSWITCH 0x00000064
+
+// AUX_TIMER2 Debug Control
+#define AUX_SYSIF_O_TIMER2DBGCTL 0x00000068
+
+// Clock Shift Detection
+#define AUX_SYSIF_O_CLKSHIFTDET 0x00000070
+
+// VDDR Recharge Trigger
+#define AUX_SYSIF_O_RECHARGETRIG 0x00000074
+
+// VDDR Recharge Detection
+#define AUX_SYSIF_O_RECHARGEDET 0x00000078
+
+// Real Time Counter Sub Second Increment 0
+#define AUX_SYSIF_O_RTCSUBSECINC0 0x0000007C
+
+// Real Time Counter Sub Second Increment 1
+#define AUX_SYSIF_O_RTCSUBSECINC1 0x00000080
+
+// Real Time Counter Sub Second Increment Control
+#define AUX_SYSIF_O_RTCSUBSECINCCTL 0x00000084
+
+// Real Time Counter Second
+#define AUX_SYSIF_O_RTCSEC 0x00000088
+
+// Real Time Counter Sub-Second
+#define AUX_SYSIF_O_RTCSUBSEC 0x0000008C
+
+// AON_RTC Event Clear
+#define AUX_SYSIF_O_RTCEVCLR 0x00000090
+
+// AON_BATMON Battery Voltage Value
+#define AUX_SYSIF_O_BATMONBAT 0x00000094
+
+// AON_BATMON Temperature Value
+#define AUX_SYSIF_O_BATMONTEMP 0x0000009C
+
+// Timer Halt
+#define AUX_SYSIF_O_TIMERHALT 0x000000A0
+
+// AUX_TIMER2 Bridge
+#define AUX_SYSIF_O_TIMER2BRIDGE 0x000000B0
+
+// Software Power Profiler
+#define AUX_SYSIF_O_SWPWRPROF 0x000000B4
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_OPMODEREQ
+//
+//*****************************************************************************
+// Field: [1:0] REQ
+//
+// AUX operational mode request.
+// ENUMs:
+// PDLP Powerdown operational mode with wakeup to lowpower
+// mode, characterized by:
+// - Powerdown system power
+// supply state (uLDO) request.
+// -
+// AON_PMCTL:AUXSCECLK.PD_SRC sets the SCE clock
+// frequency (SCE_RATE).
+// - An active wakeup flag
+// overrides the operational mode externally to
+// lowpower (LP) as long as the flag is set.
+// PDA Powerdown operational mode with wakeup to active
+// mode, characterized by:
+// - Powerdown system power
+// supply state (uLDO) request.
+// -
+// AON_PMCTL:AUXSCECLK.PD_SRC sets the SCE clock
+// frequency (SCE_RATE).
+// - An active wakeup flag
+// overrides the operational mode externally to
+// active (A) as long as the flag is set.
+// LP Lowpower operational mode, characterized by:
+// - Powerdown system power
+// supply state (uLDO) request.
+// - SCE clock frequency
+// (SCE_RATE) equals SCLK_MF.
+// - An active wakeup flag
+// does not change operational mode.
+// A Active operational mode, characterized by:
+// - Active system power
+// supply state (GLDO or DCDC) request.
+// - AON_PMCTL:AUXSCECLK.SRC
+// sets the SCE clock frequency (SCE_RATE).
+// - An active wakeup flag
+// does not change operational mode.
+#define AUX_SYSIF_OPMODEREQ_REQ_W 2
+#define AUX_SYSIF_OPMODEREQ_REQ_M 0x00000003
+#define AUX_SYSIF_OPMODEREQ_REQ_S 0
+#define AUX_SYSIF_OPMODEREQ_REQ_PDLP 0x00000003
+#define AUX_SYSIF_OPMODEREQ_REQ_PDA 0x00000002
+#define AUX_SYSIF_OPMODEREQ_REQ_LP 0x00000001
+#define AUX_SYSIF_OPMODEREQ_REQ_A 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_OPMODEACK
+//
+//*****************************************************************************
+// Field: [1:0] ACK
+//
+// AUX operational mode acknowledgement.
+// ENUMs:
+// PDLP Powerdown operational mode with wakeup to lowpower
+// mode is acknowledged.
+// PDA Powerdown operational mode with wakeup to active
+// mode is acknowledged.
+// LP Lowpower operational mode is acknowledged.
+// A Active operational mode is acknowledged.
+#define AUX_SYSIF_OPMODEACK_ACK_W 2
+#define AUX_SYSIF_OPMODEACK_ACK_M 0x00000003
+#define AUX_SYSIF_OPMODEACK_ACK_S 0
+#define AUX_SYSIF_OPMODEACK_ACK_PDLP 0x00000003
+#define AUX_SYSIF_OPMODEACK_ACK_PDA 0x00000002
+#define AUX_SYSIF_OPMODEACK_ACK_LP 0x00000001
+#define AUX_SYSIF_OPMODEACK_ACK_A 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_PROGWU0CFG
+//
+//*****************************************************************************
+// Field: [7] POL
+//
+// Polarity of WU_SRC.
+//
+// The procedure used to clear the wakeup flag decides level or edge
+// sensitivity, see WUFLAGSCLR.PROG_WU0.
+// ENUMs:
+// LOW The wakeup flag is set when WU_SRC is low or goes
+// low.
+// HIGH The wakeup flag is set when WU_SRC is high or goes
+// high.
+#define AUX_SYSIF_PROGWU0CFG_POL 0x00000080
+#define AUX_SYSIF_PROGWU0CFG_POL_BITN 7
+#define AUX_SYSIF_PROGWU0CFG_POL_M 0x00000080
+#define AUX_SYSIF_PROGWU0CFG_POL_S 7
+#define AUX_SYSIF_PROGWU0CFG_POL_LOW 0x00000080
+#define AUX_SYSIF_PROGWU0CFG_POL_HIGH 0x00000000
+
+// Field: [6] EN
+//
+// Programmable wakeup flag enable.
+//
+// 0: Disable wakeup flag.
+// 1: Enable wakeup flag.
+#define AUX_SYSIF_PROGWU0CFG_EN 0x00000040
+#define AUX_SYSIF_PROGWU0CFG_EN_BITN 6
+#define AUX_SYSIF_PROGWU0CFG_EN_M 0x00000040
+#define AUX_SYSIF_PROGWU0CFG_EN_S 6
+
+// Field: [5:0] WU_SRC
+//
+// Wakeup source from the asynchronous AUX event bus.
+//
+// Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU0 is 1.
+//
+// If you write a non-enumerated value the behavior is identical to NO_EVENT.
+// The written value is returned when read.
+// ENUMs:
+// NO_EVENT No event.
+// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE
+// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY
+// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL
+// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ
+// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE
+// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N
+// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE
+// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV
+// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV
+// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE
+// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3
+// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2
+// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1
+// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0
+// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB
+// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA
+// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1
+// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0
+// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV
+// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF
+// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE
+// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE
+// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN
+// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF
+// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD
+// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD
+// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ
+// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY
+// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2
+// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV
+// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31
+// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30
+// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29
+// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28
+// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27
+// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26
+// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25
+// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24
+// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23
+// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22
+// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21
+// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20
+// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19
+// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18
+// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17
+// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16
+// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15
+// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14
+// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13
+// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12
+// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11
+// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10
+// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9
+// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8
+// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7
+// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6
+// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5
+// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4
+// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3
+// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2
+// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1
+// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_W 6
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_M 0x0000003F
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_S 0
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_NO_EVENT 0x0000003F
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000003D
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_ADC_IRQ 0x0000003A
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_ADC_DONE 0x00000039
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_ISRC_RESET_N 0x00000038
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TDC_DONE 0x00000037
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER0_EV 0x00000036
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER1_EV 0x00000035
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER2_PULSE 0x00000034
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER2_EV3 0x00000033
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER2_EV2 0x00000032
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER2_EV1 0x00000031
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER2_EV0 0x00000030
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_COMPB 0x0000002F
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_COMPA 0x0000002E
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_MCU_OBSMUX1 0x0000002D
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_MCU_OBSMUX0 0x0000002C
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_MCU_EV 0x0000002B
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_ACLK_REF 0x0000002A
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_VDDR_RECHARGE 0x00000029
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_MCU_ACTIVE 0x00000028
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_PWR_DWN 0x00000027
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_SCLK_LF 0x00000026
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AON_BATMON_TEMP_UPD 0x00000025
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AON_BATMON_BAT_UPD 0x00000024
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AON_RTC_4KHZ 0x00000023
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AON_RTC_CH2_DLY 0x00000022
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AON_RTC_CH2 0x00000021
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_MANUAL_EV 0x00000020
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO31 0x0000001F
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO30 0x0000001E
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO29 0x0000001D
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO28 0x0000001C
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO27 0x0000001B
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO26 0x0000001A
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO25 0x00000019
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO24 0x00000018
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO23 0x00000017
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO22 0x00000016
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO21 0x00000015
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO20 0x00000014
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO19 0x00000013
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO18 0x00000012
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO17 0x00000011
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO16 0x00000010
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO15 0x0000000F
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO14 0x0000000E
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO13 0x0000000D
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO12 0x0000000C
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO11 0x0000000B
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO10 0x0000000A
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO9 0x00000009
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO8 0x00000008
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO7 0x00000007
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO6 0x00000006
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO5 0x00000005
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO4 0x00000004
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO3 0x00000003
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO2 0x00000002
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO1 0x00000001
+#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO0 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_PROGWU1CFG
+//
+//*****************************************************************************
+// Field: [7] POL
+//
+// Polarity of WU_SRC.
+//
+// The procedure used to clear the wakeup flag decides level or edge
+// sensitivity, see WUFLAGSCLR.PROG_WU1.
+// ENUMs:
+// LOW The wakeup flag is set when WU_SRC is low or goes
+// low.
+// HIGH The wakeup flag is set when WU_SRC is high or goes
+// high.
+#define AUX_SYSIF_PROGWU1CFG_POL 0x00000080
+#define AUX_SYSIF_PROGWU1CFG_POL_BITN 7
+#define AUX_SYSIF_PROGWU1CFG_POL_M 0x00000080
+#define AUX_SYSIF_PROGWU1CFG_POL_S 7
+#define AUX_SYSIF_PROGWU1CFG_POL_LOW 0x00000080
+#define AUX_SYSIF_PROGWU1CFG_POL_HIGH 0x00000000
+
+// Field: [6] EN
+//
+// Programmable wakeup flag enable.
+//
+// 0: Disable wakeup flag.
+// 1: Enable wakeup flag.
+#define AUX_SYSIF_PROGWU1CFG_EN 0x00000040
+#define AUX_SYSIF_PROGWU1CFG_EN_BITN 6
+#define AUX_SYSIF_PROGWU1CFG_EN_M 0x00000040
+#define AUX_SYSIF_PROGWU1CFG_EN_S 6
+
+// Field: [5:0] WU_SRC
+//
+// Wakeup source from the asynchronous AUX event bus.
+//
+// Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU1 is 1.
+//
+// If you write a non-enumerated value the behavior is identical to NO_EVENT.
+// The written value is returned when read.
+// ENUMs:
+// NO_EVENT No event.
+// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE
+// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY
+// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL
+// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ
+// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE
+// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N
+// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE
+// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV
+// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV
+// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE
+// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3
+// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2
+// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1
+// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0
+// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB
+// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA
+// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1
+// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0
+// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV
+// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF
+// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE
+// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE
+// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN
+// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF
+// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD
+// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD
+// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ
+// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY
+// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2
+// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV
+// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31
+// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30
+// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29
+// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28
+// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27
+// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26
+// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25
+// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24
+// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23
+// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22
+// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21
+// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20
+// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19
+// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18
+// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17
+// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16
+// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15
+// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14
+// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13
+// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12
+// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11
+// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10
+// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9
+// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8
+// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7
+// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6
+// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5
+// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4
+// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3
+// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2
+// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1
+// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_W 6
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_M 0x0000003F
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_S 0
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_NO_EVENT 0x0000003F
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000003D
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_ADC_IRQ 0x0000003A
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_ADC_DONE 0x00000039
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_ISRC_RESET_N 0x00000038
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TDC_DONE 0x00000037
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER0_EV 0x00000036
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER1_EV 0x00000035
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER2_PULSE 0x00000034
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER2_EV3 0x00000033
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER2_EV2 0x00000032
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER2_EV1 0x00000031
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER2_EV0 0x00000030
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_COMPB 0x0000002F
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_COMPA 0x0000002E
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_MCU_OBSMUX1 0x0000002D
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_MCU_OBSMUX0 0x0000002C
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_MCU_EV 0x0000002B
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_ACLK_REF 0x0000002A
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_VDDR_RECHARGE 0x00000029
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_MCU_ACTIVE 0x00000028
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_PWR_DWN 0x00000027
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_SCLK_LF 0x00000026
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AON_BATMON_TEMP_UPD 0x00000025
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AON_BATMON_BAT_UPD 0x00000024
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AON_RTC_4KHZ 0x00000023
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AON_RTC_CH2_DLY 0x00000022
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AON_RTC_CH2 0x00000021
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_MANUAL_EV 0x00000020
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO31 0x0000001F
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO30 0x0000001E
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO29 0x0000001D
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO28 0x0000001C
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO27 0x0000001B
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO26 0x0000001A
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO25 0x00000019
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO24 0x00000018
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO23 0x00000017
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO22 0x00000016
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO21 0x00000015
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO20 0x00000014
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO19 0x00000013
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO18 0x00000012
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO17 0x00000011
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO16 0x00000010
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO15 0x0000000F
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO14 0x0000000E
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO13 0x0000000D
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO12 0x0000000C
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO11 0x0000000B
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO10 0x0000000A
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO9 0x00000009
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO8 0x00000008
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO7 0x00000007
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO6 0x00000006
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO5 0x00000005
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO4 0x00000004
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO3 0x00000003
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO2 0x00000002
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO1 0x00000001
+#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO0 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_PROGWU2CFG
+//
+//*****************************************************************************
+// Field: [7] POL
+//
+// Polarity of WU_SRC.
+//
+// The procedure used to clear the wakeup flag decides level or edge
+// sensitivity, see WUFLAGSCLR.PROG_WU2.
+// ENUMs:
+// LOW The wakeup flag is set when WU_SRC is low or goes
+// low.
+// HIGH The wakeup flag is set when WU_SRC is high or goes
+// high.
+#define AUX_SYSIF_PROGWU2CFG_POL 0x00000080
+#define AUX_SYSIF_PROGWU2CFG_POL_BITN 7
+#define AUX_SYSIF_PROGWU2CFG_POL_M 0x00000080
+#define AUX_SYSIF_PROGWU2CFG_POL_S 7
+#define AUX_SYSIF_PROGWU2CFG_POL_LOW 0x00000080
+#define AUX_SYSIF_PROGWU2CFG_POL_HIGH 0x00000000
+
+// Field: [6] EN
+//
+// Programmable wakeup flag enable.
+//
+// 0: Disable wakeup flag.
+// 1: Enable wakeup flag.
+#define AUX_SYSIF_PROGWU2CFG_EN 0x00000040
+#define AUX_SYSIF_PROGWU2CFG_EN_BITN 6
+#define AUX_SYSIF_PROGWU2CFG_EN_M 0x00000040
+#define AUX_SYSIF_PROGWU2CFG_EN_S 6
+
+// Field: [5:0] WU_SRC
+//
+// Wakeup source from the asynchronous AUX event bus.
+//
+// Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU2 is 1.
+//
+// If you write a non-enumerated value the behavior is identical to NO_EVENT.
+// The written value is returned when read.
+// ENUMs:
+// NO_EVENT No event.
+// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE
+// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY
+// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL
+// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ
+// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE
+// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N
+// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE
+// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV
+// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV
+// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE
+// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3
+// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2
+// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1
+// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0
+// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB
+// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA
+// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1
+// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0
+// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV
+// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF
+// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE
+// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE
+// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN
+// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF
+// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD
+// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD
+// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ
+// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY
+// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2
+// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV
+// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31
+// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30
+// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29
+// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28
+// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27
+// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26
+// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25
+// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24
+// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23
+// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22
+// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21
+// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20
+// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19
+// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18
+// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17
+// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16
+// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15
+// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14
+// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13
+// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12
+// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11
+// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10
+// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9
+// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8
+// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7
+// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6
+// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5
+// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4
+// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3
+// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2
+// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1
+// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_W 6
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_M 0x0000003F
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_S 0
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_NO_EVENT 0x0000003F
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000003D
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_ADC_IRQ 0x0000003A
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_ADC_DONE 0x00000039
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_ISRC_RESET_N 0x00000038
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TDC_DONE 0x00000037
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER0_EV 0x00000036
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER1_EV 0x00000035
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER2_PULSE 0x00000034
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER2_EV3 0x00000033
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER2_EV2 0x00000032
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER2_EV1 0x00000031
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER2_EV0 0x00000030
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_COMPB 0x0000002F
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_COMPA 0x0000002E
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_MCU_OBSMUX1 0x0000002D
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_MCU_OBSMUX0 0x0000002C
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_MCU_EV 0x0000002B
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_ACLK_REF 0x0000002A
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_VDDR_RECHARGE 0x00000029
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_MCU_ACTIVE 0x00000028
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_PWR_DWN 0x00000027
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_SCLK_LF 0x00000026
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AON_BATMON_TEMP_UPD 0x00000025
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AON_BATMON_BAT_UPD 0x00000024
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AON_RTC_4KHZ 0x00000023
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AON_RTC_CH2_DLY 0x00000022
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AON_RTC_CH2 0x00000021
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_MANUAL_EV 0x00000020
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO31 0x0000001F
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO30 0x0000001E
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO29 0x0000001D
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO28 0x0000001C
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO27 0x0000001B
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO26 0x0000001A
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO25 0x00000019
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO24 0x00000018
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO23 0x00000017
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO22 0x00000016
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO21 0x00000015
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO20 0x00000014
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO19 0x00000013
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO18 0x00000012
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO17 0x00000011
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO16 0x00000010
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO15 0x0000000F
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO14 0x0000000E
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO13 0x0000000D
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO12 0x0000000C
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO11 0x0000000B
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO10 0x0000000A
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO9 0x00000009
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO8 0x00000008
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO7 0x00000007
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO6 0x00000006
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO5 0x00000005
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO4 0x00000004
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO3 0x00000003
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO2 0x00000002
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO1 0x00000001
+#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO0 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_PROGWU3CFG
+//
+//*****************************************************************************
+// Field: [7] POL
+//
+// Polarity of WU_SRC.
+//
+// The procedure used to clear the wakeup flag decides level or edge
+// sensitivity, see WUFLAGSCLR.PROG_WU3.
+// ENUMs:
+// LOW The wakeup flag is set when WU_SRC is low or goes
+// low.
+// HIGH The wakeup flag is set when WU_SRC is high or goes
+// high.
+#define AUX_SYSIF_PROGWU3CFG_POL 0x00000080
+#define AUX_SYSIF_PROGWU3CFG_POL_BITN 7
+#define AUX_SYSIF_PROGWU3CFG_POL_M 0x00000080
+#define AUX_SYSIF_PROGWU3CFG_POL_S 7
+#define AUX_SYSIF_PROGWU3CFG_POL_LOW 0x00000080
+#define AUX_SYSIF_PROGWU3CFG_POL_HIGH 0x00000000
+
+// Field: [6] EN
+//
+// Programmable wakeup flag enable.
+//
+// 0: Disable wakeup flag.
+// 1: Enable wakeup flag.
+#define AUX_SYSIF_PROGWU3CFG_EN 0x00000040
+#define AUX_SYSIF_PROGWU3CFG_EN_BITN 6
+#define AUX_SYSIF_PROGWU3CFG_EN_M 0x00000040
+#define AUX_SYSIF_PROGWU3CFG_EN_S 6
+
+// Field: [5:0] WU_SRC
+//
+// Wakeup source from the asynchronous AUX event bus.
+//
+// Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU3 is 1.
+//
+// If you write a non-enumerated value the behavior is identical to NO_EVENT.
+// The written value is returned when read.
+// ENUMs:
+// NO_EVENT No event.
+// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE
+// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY
+// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL
+// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ
+// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE
+// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N
+// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE
+// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV
+// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV
+// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE
+// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3
+// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2
+// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1
+// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0
+// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB
+// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA
+// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1
+// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0
+// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV
+// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF
+// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE
+// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE
+// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN
+// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF
+// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD
+// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD
+// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ
+// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY
+// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2
+// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV
+// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31
+// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30
+// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29
+// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28
+// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27
+// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26
+// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25
+// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24
+// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23
+// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22
+// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21
+// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20
+// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19
+// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18
+// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17
+// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16
+// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15
+// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14
+// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13
+// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12
+// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11
+// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10
+// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9
+// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8
+// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7
+// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6
+// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5
+// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4
+// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3
+// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2
+// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1
+// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_W 6
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_M 0x0000003F
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_S 0
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_NO_EVENT 0x0000003F
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000003D
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_ADC_IRQ 0x0000003A
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_ADC_DONE 0x00000039
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_ISRC_RESET_N 0x00000038
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TDC_DONE 0x00000037
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER0_EV 0x00000036
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER1_EV 0x00000035
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER2_PULSE 0x00000034
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER2_EV3 0x00000033
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER2_EV2 0x00000032
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER2_EV1 0x00000031
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER2_EV0 0x00000030
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_COMPB 0x0000002F
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_COMPA 0x0000002E
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_MCU_OBSMUX1 0x0000002D
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_MCU_OBSMUX0 0x0000002C
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_MCU_EV 0x0000002B
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_ACLK_REF 0x0000002A
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_VDDR_RECHARGE 0x00000029
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_MCU_ACTIVE 0x00000028
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_PWR_DWN 0x00000027
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_SCLK_LF 0x00000026
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AON_BATMON_TEMP_UPD 0x00000025
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AON_BATMON_BAT_UPD 0x00000024
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AON_RTC_4KHZ 0x00000023
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AON_RTC_CH2_DLY 0x00000022
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AON_RTC_CH2 0x00000021
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_MANUAL_EV 0x00000020
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO31 0x0000001F
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO30 0x0000001E
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO29 0x0000001D
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO28 0x0000001C
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO27 0x0000001B
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO26 0x0000001A
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO25 0x00000019
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO24 0x00000018
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO23 0x00000017
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO22 0x00000016
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO21 0x00000015
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO20 0x00000014
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO19 0x00000013
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO18 0x00000012
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO17 0x00000011
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO16 0x00000010
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO15 0x0000000F
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO14 0x0000000E
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO13 0x0000000D
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO12 0x0000000C
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO11 0x0000000B
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO10 0x0000000A
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO9 0x00000009
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO8 0x00000008
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO7 0x00000007
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO6 0x00000006
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO5 0x00000005
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO4 0x00000004
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO3 0x00000003
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO2 0x00000002
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO1 0x00000001
+#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO0 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_SWWUTRIG
+//
+//*****************************************************************************
+// Field: [3] SW_WU3
+//
+// Software wakeup 3 trigger.
+//
+// 0: No effect.
+// 1: Set WUFLAGS.SW_WU3 and trigger AUX wakeup.
+#define AUX_SYSIF_SWWUTRIG_SW_WU3 0x00000008
+#define AUX_SYSIF_SWWUTRIG_SW_WU3_BITN 3
+#define AUX_SYSIF_SWWUTRIG_SW_WU3_M 0x00000008
+#define AUX_SYSIF_SWWUTRIG_SW_WU3_S 3
+
+// Field: [2] SW_WU2
+//
+// Software wakeup 2 trigger.
+//
+// 0: No effect.
+// 1: Set WUFLAGS.SW_WU2 and trigger AUX wakeup.
+#define AUX_SYSIF_SWWUTRIG_SW_WU2 0x00000004
+#define AUX_SYSIF_SWWUTRIG_SW_WU2_BITN 2
+#define AUX_SYSIF_SWWUTRIG_SW_WU2_M 0x00000004
+#define AUX_SYSIF_SWWUTRIG_SW_WU2_S 2
+
+// Field: [1] SW_WU1
+//
+// Software wakeup 1 trigger.
+//
+// 0: No effect.
+// 1: Set WUFLAGS.SW_WU1 and trigger AUX wakeup.
+#define AUX_SYSIF_SWWUTRIG_SW_WU1 0x00000002
+#define AUX_SYSIF_SWWUTRIG_SW_WU1_BITN 1
+#define AUX_SYSIF_SWWUTRIG_SW_WU1_M 0x00000002
+#define AUX_SYSIF_SWWUTRIG_SW_WU1_S 1
+
+// Field: [0] SW_WU0
+//
+// Software wakeup 0 trigger.
+//
+// 0: No effect.
+// 1: Set WUFLAGS.SW_WU0 and trigger AUX wakeup.
+#define AUX_SYSIF_SWWUTRIG_SW_WU0 0x00000001
+#define AUX_SYSIF_SWWUTRIG_SW_WU0_BITN 0
+#define AUX_SYSIF_SWWUTRIG_SW_WU0_M 0x00000001
+#define AUX_SYSIF_SWWUTRIG_SW_WU0_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_WUFLAGS
+//
+//*****************************************************************************
+// Field: [7] SW_WU3
+//
+// Software wakeup 3 flag.
+//
+// 0: Software wakeup 3 not triggered.
+// 1: Software wakeup 3 triggered.
+#define AUX_SYSIF_WUFLAGS_SW_WU3 0x00000080
+#define AUX_SYSIF_WUFLAGS_SW_WU3_BITN 7
+#define AUX_SYSIF_WUFLAGS_SW_WU3_M 0x00000080
+#define AUX_SYSIF_WUFLAGS_SW_WU3_S 7
+
+// Field: [6] SW_WU2
+//
+// Software wakeup 2 flag.
+//
+// 0: Software wakeup 2 not triggered.
+// 1: Software wakeup 2 triggered.
+#define AUX_SYSIF_WUFLAGS_SW_WU2 0x00000040
+#define AUX_SYSIF_WUFLAGS_SW_WU2_BITN 6
+#define AUX_SYSIF_WUFLAGS_SW_WU2_M 0x00000040
+#define AUX_SYSIF_WUFLAGS_SW_WU2_S 6
+
+// Field: [5] SW_WU1
+//
+// Software wakeup 1 flag.
+//
+// 0: Software wakeup 1 not triggered.
+// 1: Software wakeup 1 triggered.
+#define AUX_SYSIF_WUFLAGS_SW_WU1 0x00000020
+#define AUX_SYSIF_WUFLAGS_SW_WU1_BITN 5
+#define AUX_SYSIF_WUFLAGS_SW_WU1_M 0x00000020
+#define AUX_SYSIF_WUFLAGS_SW_WU1_S 5
+
+// Field: [4] SW_WU0
+//
+// Software wakeup 0 flag.
+//
+// 0: Software wakeup 0 not triggered.
+// 1: Software wakeup 0 triggered.
+#define AUX_SYSIF_WUFLAGS_SW_WU0 0x00000010
+#define AUX_SYSIF_WUFLAGS_SW_WU0_BITN 4
+#define AUX_SYSIF_WUFLAGS_SW_WU0_M 0x00000010
+#define AUX_SYSIF_WUFLAGS_SW_WU0_S 4
+
+// Field: [3] PROG_WU3
+//
+// Programmable wakeup 3.
+//
+// 0: Programmable wakeup 3 not triggered.
+// 1: Programmable wakeup 3 triggered.
+#define AUX_SYSIF_WUFLAGS_PROG_WU3 0x00000008
+#define AUX_SYSIF_WUFLAGS_PROG_WU3_BITN 3
+#define AUX_SYSIF_WUFLAGS_PROG_WU3_M 0x00000008
+#define AUX_SYSIF_WUFLAGS_PROG_WU3_S 3
+
+// Field: [2] PROG_WU2
+//
+// Programmable wakeup 2.
+//
+// 0: Programmable wakeup 2 not triggered.
+// 1: Programmable wakeup 2 triggered.
+#define AUX_SYSIF_WUFLAGS_PROG_WU2 0x00000004
+#define AUX_SYSIF_WUFLAGS_PROG_WU2_BITN 2
+#define AUX_SYSIF_WUFLAGS_PROG_WU2_M 0x00000004
+#define AUX_SYSIF_WUFLAGS_PROG_WU2_S 2
+
+// Field: [1] PROG_WU1
+//
+// Programmable wakeup 1.
+//
+// 0: Programmable wakeup 1 not triggered.
+// 1: Programmable wakeup 1 triggered.
+#define AUX_SYSIF_WUFLAGS_PROG_WU1 0x00000002
+#define AUX_SYSIF_WUFLAGS_PROG_WU1_BITN 1
+#define AUX_SYSIF_WUFLAGS_PROG_WU1_M 0x00000002
+#define AUX_SYSIF_WUFLAGS_PROG_WU1_S 1
+
+// Field: [0] PROG_WU0
+//
+// Programmable wakeup 0.
+//
+// 0: Programmable wakeup 0 not triggered.
+// 1: Programmable wakeup 0 triggered.
+#define AUX_SYSIF_WUFLAGS_PROG_WU0 0x00000001
+#define AUX_SYSIF_WUFLAGS_PROG_WU0_BITN 0
+#define AUX_SYSIF_WUFLAGS_PROG_WU0_M 0x00000001
+#define AUX_SYSIF_WUFLAGS_PROG_WU0_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_WUFLAGSCLR
+//
+//*****************************************************************************
+// Field: [7] SW_WU3
+//
+// Clear software wakeup flag 3.
+//
+// 0: No effect.
+// 1: Clear WUFLAGS.SW_WU3. Keep high until WUFLAGS.SW_WU3 is 0.
+#define AUX_SYSIF_WUFLAGSCLR_SW_WU3 0x00000080
+#define AUX_SYSIF_WUFLAGSCLR_SW_WU3_BITN 7
+#define AUX_SYSIF_WUFLAGSCLR_SW_WU3_M 0x00000080
+#define AUX_SYSIF_WUFLAGSCLR_SW_WU3_S 7
+
+// Field: [6] SW_WU2
+//
+// Clear software wakeup flag 2.
+//
+// 0: No effect.
+// 1: Clear WUFLAGS.SW_WU2. Keep high until WUFLAGS.SW_WU2 is 0.
+#define AUX_SYSIF_WUFLAGSCLR_SW_WU2 0x00000040
+#define AUX_SYSIF_WUFLAGSCLR_SW_WU2_BITN 6
+#define AUX_SYSIF_WUFLAGSCLR_SW_WU2_M 0x00000040
+#define AUX_SYSIF_WUFLAGSCLR_SW_WU2_S 6
+
+// Field: [5] SW_WU1
+//
+// Clear software wakeup flag 1.
+//
+// 0: No effect.
+// 1: Clear WUFLAGS.SW_WU1. Keep high until WUFLAGS.SW_WU1 is 0.
+#define AUX_SYSIF_WUFLAGSCLR_SW_WU1 0x00000020
+#define AUX_SYSIF_WUFLAGSCLR_SW_WU1_BITN 5
+#define AUX_SYSIF_WUFLAGSCLR_SW_WU1_M 0x00000020
+#define AUX_SYSIF_WUFLAGSCLR_SW_WU1_S 5
+
+// Field: [4] SW_WU0
+//
+// Clear software wakeup flag 0.
+//
+// 0: No effect.
+// 1: Clear WUFLAGS.SW_WU0. Keep high until WUFLAGS.SW_WU0 is 0.
+#define AUX_SYSIF_WUFLAGSCLR_SW_WU0 0x00000010
+#define AUX_SYSIF_WUFLAGSCLR_SW_WU0_BITN 4
+#define AUX_SYSIF_WUFLAGSCLR_SW_WU0_M 0x00000010
+#define AUX_SYSIF_WUFLAGSCLR_SW_WU0_S 4
+
+// Field: [3] PROG_WU3
+//
+// Programmable wakeup flag 3.
+//
+// 0: No effect.
+// 1: Clear WUFLAGS.PROG_WU3. Keep high until WUFLAGS.PROG_WU3 is 0.
+//
+// The wakeup flag becomes edge sensitive if you write PROG_WU3 to 0 when
+// PROGWU3CFG.EN is 1.
+// The wakeup flag becomes level sensitive if you write PROG_WU3 to 0 when
+// PROGWU3CFG.EN is 0, then set PROGWU3CFG.EN.
+#define AUX_SYSIF_WUFLAGSCLR_PROG_WU3 0x00000008
+#define AUX_SYSIF_WUFLAGSCLR_PROG_WU3_BITN 3
+#define AUX_SYSIF_WUFLAGSCLR_PROG_WU3_M 0x00000008
+#define AUX_SYSIF_WUFLAGSCLR_PROG_WU3_S 3
+
+// Field: [2] PROG_WU2
+//
+// Programmable wakeup flag 2.
+//
+// 0: No effect.
+// 1: Clear WUFLAGS.PROG_WU2. Keep high until WUFLAGS.PROG_WU2 is 0.
+//
+// The wakeup flag becomes edge sensitive if you write PROG_WU2 to 0 when
+// PROGWU2CFG.EN is 1.
+// The wakeup flag becomes level sensitive if you write PROG_WU2 to 0 when
+// PROGWU2CFG.EN is 0, then set PROGWU2CFG.EN.
+#define AUX_SYSIF_WUFLAGSCLR_PROG_WU2 0x00000004
+#define AUX_SYSIF_WUFLAGSCLR_PROG_WU2_BITN 2
+#define AUX_SYSIF_WUFLAGSCLR_PROG_WU2_M 0x00000004
+#define AUX_SYSIF_WUFLAGSCLR_PROG_WU2_S 2
+
+// Field: [1] PROG_WU1
+//
+// Programmable wakeup flag 1.
+//
+// 0: No effect.
+// 1: Clear WUFLAGS.PROG_WU1. Keep high until WUFLAGS.PROG_WU1 is 0.
+//
+// The wakeup flag becomes edge sensitive if you write PROG_WU1 to 0 when
+// PROGWU1CFG.EN is 1.
+// The wakeup flag becomes level sensitive if you write PROG_WU1 to 0 when
+// PROGWU1CFG.EN is 0, then set PROGWU1CFG.EN.
+#define AUX_SYSIF_WUFLAGSCLR_PROG_WU1 0x00000002
+#define AUX_SYSIF_WUFLAGSCLR_PROG_WU1_BITN 1
+#define AUX_SYSIF_WUFLAGSCLR_PROG_WU1_M 0x00000002
+#define AUX_SYSIF_WUFLAGSCLR_PROG_WU1_S 1
+
+// Field: [0] PROG_WU0
+//
+// Programmable wakeup flag 0.
+//
+// 0: No effect.
+// 1: Clear WUFLAGS.PROG_WU0. Keep high until WUFLAGS.PROG_WU0 is 0.
+//
+// The wakeup flag becomes edge sensitive if you write PROG_WU0 to 0 when
+// PROGWU0CFG.EN is 1.
+// The wakeup flag becomes level sensitive if you write PROG_WU0 to 0 when
+// PROGWU0CFG.EN is 0, then set PROGWU0CFG.EN.
+#define AUX_SYSIF_WUFLAGSCLR_PROG_WU0 0x00000001
+#define AUX_SYSIF_WUFLAGSCLR_PROG_WU0_BITN 0
+#define AUX_SYSIF_WUFLAGSCLR_PROG_WU0_M 0x00000001
+#define AUX_SYSIF_WUFLAGSCLR_PROG_WU0_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_WUGATE
+//
+//*****************************************************************************
+// Field: [0] EN
+//
+// Wakeup output enable.
+//
+// 0: Disable AUX wakeup output.
+// 1: Enable AUX wakeup output.
+#define AUX_SYSIF_WUGATE_EN 0x00000001
+#define AUX_SYSIF_WUGATE_EN_BITN 0
+#define AUX_SYSIF_WUGATE_EN_M 0x00000001
+#define AUX_SYSIF_WUGATE_EN_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_VECCFG0
+//
+//*****************************************************************************
+// Field: [3:0] VEC_EV
+//
+// Select trigger event for vector 0.
+//
+// Non-enumerated values are treated as NONE.
+// ENUMs:
+// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY
+// SW_WU3 WUFLAGS.SW_WU3
+// SW_WU2 WUFLAGS.SW_WU2
+// SW_WU1 WUFLAGS.SW_WU1
+// SW_WU0 WUFLAGS.SW_WU0
+// PROG_WU3 WUFLAGS.PROG_WU3
+// PROG_WU2 WUFLAGS.PROG_WU2
+// PROG_WU1 WUFLAGS.PROG_WU1
+// PROG_WU0 WUFLAGS.PROG_WU0
+// NONE Vector is disabled.
+#define AUX_SYSIF_VECCFG0_VEC_EV_W 4
+#define AUX_SYSIF_VECCFG0_VEC_EV_M 0x0000000F
+#define AUX_SYSIF_VECCFG0_VEC_EV_S 0
+#define AUX_SYSIF_VECCFG0_VEC_EV_AON_RTC_CH2_DLY 0x00000009
+#define AUX_SYSIF_VECCFG0_VEC_EV_SW_WU3 0x00000008
+#define AUX_SYSIF_VECCFG0_VEC_EV_SW_WU2 0x00000007
+#define AUX_SYSIF_VECCFG0_VEC_EV_SW_WU1 0x00000006
+#define AUX_SYSIF_VECCFG0_VEC_EV_SW_WU0 0x00000005
+#define AUX_SYSIF_VECCFG0_VEC_EV_PROG_WU3 0x00000004
+#define AUX_SYSIF_VECCFG0_VEC_EV_PROG_WU2 0x00000003
+#define AUX_SYSIF_VECCFG0_VEC_EV_PROG_WU1 0x00000002
+#define AUX_SYSIF_VECCFG0_VEC_EV_PROG_WU0 0x00000001
+#define AUX_SYSIF_VECCFG0_VEC_EV_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_VECCFG1
+//
+//*****************************************************************************
+// Field: [3:0] VEC_EV
+//
+// Select trigger event for vector 1.
+//
+// Non-enumerated values are treated as NONE.
+// ENUMs:
+// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY
+// SW_WU3 WUFLAGS.SW_WU3
+// SW_WU2 WUFLAGS.SW_WU2
+// SW_WU1 WUFLAGS.SW_WU1
+// SW_WU0 WUFLAGS.SW_WU0
+// PROG_WU3 WUFLAGS.PROG_WU3
+// PROG_WU2 WUFLAGS.PROG_WU2
+// PROG_WU1 WUFLAGS.PROG_WU1
+// PROG_WU0 WUFLAGS.PROG_WU0
+// NONE Vector is disabled.
+#define AUX_SYSIF_VECCFG1_VEC_EV_W 4
+#define AUX_SYSIF_VECCFG1_VEC_EV_M 0x0000000F
+#define AUX_SYSIF_VECCFG1_VEC_EV_S 0
+#define AUX_SYSIF_VECCFG1_VEC_EV_AON_RTC_CH2_DLY 0x00000009
+#define AUX_SYSIF_VECCFG1_VEC_EV_SW_WU3 0x00000008
+#define AUX_SYSIF_VECCFG1_VEC_EV_SW_WU2 0x00000007
+#define AUX_SYSIF_VECCFG1_VEC_EV_SW_WU1 0x00000006
+#define AUX_SYSIF_VECCFG1_VEC_EV_SW_WU0 0x00000005
+#define AUX_SYSIF_VECCFG1_VEC_EV_PROG_WU3 0x00000004
+#define AUX_SYSIF_VECCFG1_VEC_EV_PROG_WU2 0x00000003
+#define AUX_SYSIF_VECCFG1_VEC_EV_PROG_WU1 0x00000002
+#define AUX_SYSIF_VECCFG1_VEC_EV_PROG_WU0 0x00000001
+#define AUX_SYSIF_VECCFG1_VEC_EV_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_VECCFG2
+//
+//*****************************************************************************
+// Field: [3:0] VEC_EV
+//
+// Select trigger event for vector 2.
+//
+// Non-enumerated values are treated as NONE.
+// ENUMs:
+// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY
+// SW_WU3 WUFLAGS.SW_WU3
+// SW_WU2 WUFLAGS.SW_WU2
+// SW_WU1 WUFLAGS.SW_WU1
+// SW_WU0 WUFLAGS.SW_WU0
+// PROG_WU3 WUFLAGS.PROG_WU3
+// PROG_WU2 WUFLAGS.PROG_WU2
+// PROG_WU1 WUFLAGS.PROG_WU1
+// PROG_WU0 WUFLAGS.PROG_WU0
+// NONE Vector is disabled.
+#define AUX_SYSIF_VECCFG2_VEC_EV_W 4
+#define AUX_SYSIF_VECCFG2_VEC_EV_M 0x0000000F
+#define AUX_SYSIF_VECCFG2_VEC_EV_S 0
+#define AUX_SYSIF_VECCFG2_VEC_EV_AON_RTC_CH2_DLY 0x00000009
+#define AUX_SYSIF_VECCFG2_VEC_EV_SW_WU3 0x00000008
+#define AUX_SYSIF_VECCFG2_VEC_EV_SW_WU2 0x00000007
+#define AUX_SYSIF_VECCFG2_VEC_EV_SW_WU1 0x00000006
+#define AUX_SYSIF_VECCFG2_VEC_EV_SW_WU0 0x00000005
+#define AUX_SYSIF_VECCFG2_VEC_EV_PROG_WU3 0x00000004
+#define AUX_SYSIF_VECCFG2_VEC_EV_PROG_WU2 0x00000003
+#define AUX_SYSIF_VECCFG2_VEC_EV_PROG_WU1 0x00000002
+#define AUX_SYSIF_VECCFG2_VEC_EV_PROG_WU0 0x00000001
+#define AUX_SYSIF_VECCFG2_VEC_EV_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_VECCFG3
+//
+//*****************************************************************************
+// Field: [3:0] VEC_EV
+//
+// Select trigger event for vector 3.
+//
+// Non-enumerated values are treated as NONE.
+// ENUMs:
+// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY
+// SW_WU3 WUFLAGS.SW_WU3
+// SW_WU2 WUFLAGS.SW_WU2
+// SW_WU1 WUFLAGS.SW_WU1
+// SW_WU0 WUFLAGS.SW_WU0
+// PROG_WU3 WUFLAGS.PROG_WU3
+// PROG_WU2 WUFLAGS.PROG_WU2
+// PROG_WU1 WUFLAGS.PROG_WU1
+// PROG_WU0 WUFLAGS.PROG_WU0
+// NONE Vector is disabled.
+#define AUX_SYSIF_VECCFG3_VEC_EV_W 4
+#define AUX_SYSIF_VECCFG3_VEC_EV_M 0x0000000F
+#define AUX_SYSIF_VECCFG3_VEC_EV_S 0
+#define AUX_SYSIF_VECCFG3_VEC_EV_AON_RTC_CH2_DLY 0x00000009
+#define AUX_SYSIF_VECCFG3_VEC_EV_SW_WU3 0x00000008
+#define AUX_SYSIF_VECCFG3_VEC_EV_SW_WU2 0x00000007
+#define AUX_SYSIF_VECCFG3_VEC_EV_SW_WU1 0x00000006
+#define AUX_SYSIF_VECCFG3_VEC_EV_SW_WU0 0x00000005
+#define AUX_SYSIF_VECCFG3_VEC_EV_PROG_WU3 0x00000004
+#define AUX_SYSIF_VECCFG3_VEC_EV_PROG_WU2 0x00000003
+#define AUX_SYSIF_VECCFG3_VEC_EV_PROG_WU1 0x00000002
+#define AUX_SYSIF_VECCFG3_VEC_EV_PROG_WU0 0x00000001
+#define AUX_SYSIF_VECCFG3_VEC_EV_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_VECCFG4
+//
+//*****************************************************************************
+// Field: [3:0] VEC_EV
+//
+// Select trigger event for vector 4.
+//
+// Non-enumerated values are treated as NONE.
+// ENUMs:
+// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY
+// SW_WU3 WUFLAGS.SW_WU3
+// SW_WU2 WUFLAGS.SW_WU2
+// SW_WU1 WUFLAGS.SW_WU1
+// SW_WU0 WUFLAGS.SW_WU0
+// PROG_WU3 WUFLAGS.PROG_WU3
+// PROG_WU2 WUFLAGS.PROG_WU2
+// PROG_WU1 WUFLAGS.PROG_WU1
+// PROG_WU0 WUFLAGS.PROG_WU0
+// NONE Vector is disabled.
+#define AUX_SYSIF_VECCFG4_VEC_EV_W 4
+#define AUX_SYSIF_VECCFG4_VEC_EV_M 0x0000000F
+#define AUX_SYSIF_VECCFG4_VEC_EV_S 0
+#define AUX_SYSIF_VECCFG4_VEC_EV_AON_RTC_CH2_DLY 0x00000009
+#define AUX_SYSIF_VECCFG4_VEC_EV_SW_WU3 0x00000008
+#define AUX_SYSIF_VECCFG4_VEC_EV_SW_WU2 0x00000007
+#define AUX_SYSIF_VECCFG4_VEC_EV_SW_WU1 0x00000006
+#define AUX_SYSIF_VECCFG4_VEC_EV_SW_WU0 0x00000005
+#define AUX_SYSIF_VECCFG4_VEC_EV_PROG_WU3 0x00000004
+#define AUX_SYSIF_VECCFG4_VEC_EV_PROG_WU2 0x00000003
+#define AUX_SYSIF_VECCFG4_VEC_EV_PROG_WU1 0x00000002
+#define AUX_SYSIF_VECCFG4_VEC_EV_PROG_WU0 0x00000001
+#define AUX_SYSIF_VECCFG4_VEC_EV_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_VECCFG5
+//
+//*****************************************************************************
+// Field: [3:0] VEC_EV
+//
+// Select trigger event for vector 5.
+//
+// Non-enumerated values are treated as NONE.
+// ENUMs:
+// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY
+// SW_WU3 WUFLAGS.SW_WU3
+// SW_WU2 WUFLAGS.SW_WU2
+// SW_WU1 WUFLAGS.SW_WU1
+// SW_WU0 WUFLAGS.SW_WU0
+// PROG_WU3 WUFLAGS.PROG_WU3
+// PROG_WU2 WUFLAGS.PROG_WU2
+// PROG_WU1 WUFLAGS.PROG_WU1
+// PROG_WU0 WUFLAGS.PROG_WU0
+// NONE Vector is disabled.
+#define AUX_SYSIF_VECCFG5_VEC_EV_W 4
+#define AUX_SYSIF_VECCFG5_VEC_EV_M 0x0000000F
+#define AUX_SYSIF_VECCFG5_VEC_EV_S 0
+#define AUX_SYSIF_VECCFG5_VEC_EV_AON_RTC_CH2_DLY 0x00000009
+#define AUX_SYSIF_VECCFG5_VEC_EV_SW_WU3 0x00000008
+#define AUX_SYSIF_VECCFG5_VEC_EV_SW_WU2 0x00000007
+#define AUX_SYSIF_VECCFG5_VEC_EV_SW_WU1 0x00000006
+#define AUX_SYSIF_VECCFG5_VEC_EV_SW_WU0 0x00000005
+#define AUX_SYSIF_VECCFG5_VEC_EV_PROG_WU3 0x00000004
+#define AUX_SYSIF_VECCFG5_VEC_EV_PROG_WU2 0x00000003
+#define AUX_SYSIF_VECCFG5_VEC_EV_PROG_WU1 0x00000002
+#define AUX_SYSIF_VECCFG5_VEC_EV_PROG_WU0 0x00000001
+#define AUX_SYSIF_VECCFG5_VEC_EV_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_VECCFG6
+//
+//*****************************************************************************
+// Field: [3:0] VEC_EV
+//
+// Select trigger event for vector 6.
+//
+// Non-enumerated values are treated as NONE.
+// ENUMs:
+// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY
+// SW_WU3 WUFLAGS.SW_WU3
+// SW_WU2 WUFLAGS.SW_WU2
+// SW_WU1 WUFLAGS.SW_WU1
+// SW_WU0 WUFLAGS.SW_WU0
+// PROG_WU3 WUFLAGS.PROG_WU3
+// PROG_WU2 WUFLAGS.PROG_WU2
+// PROG_WU1 WUFLAGS.PROG_WU1
+// PROG_WU0 WUFLAGS.PROG_WU0
+// NONE Vector is disabled.
+#define AUX_SYSIF_VECCFG6_VEC_EV_W 4
+#define AUX_SYSIF_VECCFG6_VEC_EV_M 0x0000000F
+#define AUX_SYSIF_VECCFG6_VEC_EV_S 0
+#define AUX_SYSIF_VECCFG6_VEC_EV_AON_RTC_CH2_DLY 0x00000009
+#define AUX_SYSIF_VECCFG6_VEC_EV_SW_WU3 0x00000008
+#define AUX_SYSIF_VECCFG6_VEC_EV_SW_WU2 0x00000007
+#define AUX_SYSIF_VECCFG6_VEC_EV_SW_WU1 0x00000006
+#define AUX_SYSIF_VECCFG6_VEC_EV_SW_WU0 0x00000005
+#define AUX_SYSIF_VECCFG6_VEC_EV_PROG_WU3 0x00000004
+#define AUX_SYSIF_VECCFG6_VEC_EV_PROG_WU2 0x00000003
+#define AUX_SYSIF_VECCFG6_VEC_EV_PROG_WU1 0x00000002
+#define AUX_SYSIF_VECCFG6_VEC_EV_PROG_WU0 0x00000001
+#define AUX_SYSIF_VECCFG6_VEC_EV_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_VECCFG7
+//
+//*****************************************************************************
+// Field: [3:0] VEC_EV
+//
+// Select trigger event for vector 7.
+//
+// Non-enumerated values are treated as NONE.
+// ENUMs:
+// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY
+// SW_WU3 WUFLAGS.SW_WU3
+// SW_WU2 WUFLAGS.SW_WU2
+// SW_WU1 WUFLAGS.SW_WU1
+// SW_WU0 WUFLAGS.SW_WU0
+// PROG_WU3 WUFLAGS.PROG_WU3
+// PROG_WU2 WUFLAGS.PROG_WU2
+// PROG_WU1 WUFLAGS.PROG_WU1
+// PROG_WU0 WUFLAGS.PROG_WU0
+// NONE Vector is disabled.
+#define AUX_SYSIF_VECCFG7_VEC_EV_W 4
+#define AUX_SYSIF_VECCFG7_VEC_EV_M 0x0000000F
+#define AUX_SYSIF_VECCFG7_VEC_EV_S 0
+#define AUX_SYSIF_VECCFG7_VEC_EV_AON_RTC_CH2_DLY 0x00000009
+#define AUX_SYSIF_VECCFG7_VEC_EV_SW_WU3 0x00000008
+#define AUX_SYSIF_VECCFG7_VEC_EV_SW_WU2 0x00000007
+#define AUX_SYSIF_VECCFG7_VEC_EV_SW_WU1 0x00000006
+#define AUX_SYSIF_VECCFG7_VEC_EV_SW_WU0 0x00000005
+#define AUX_SYSIF_VECCFG7_VEC_EV_PROG_WU3 0x00000004
+#define AUX_SYSIF_VECCFG7_VEC_EV_PROG_WU2 0x00000003
+#define AUX_SYSIF_VECCFG7_VEC_EV_PROG_WU1 0x00000002
+#define AUX_SYSIF_VECCFG7_VEC_EV_PROG_WU0 0x00000001
+#define AUX_SYSIF_VECCFG7_VEC_EV_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_EVSYNCRATE
+//
+//*****************************************************************************
+// Field: [2] AUX_COMPA_SYNC_RATE
+//
+// Select synchronization rate for AUX_EVCTL:EVSTAT2.AUX_COMPA event.
+// ENUMs:
+// BUS_RATE AUX bus rate
+// SCE_RATE SCE rate
+#define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE 0x00000004
+#define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE_BITN 2
+#define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE_M 0x00000004
+#define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE_S 2
+#define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE_BUS_RATE 0x00000004
+#define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE_SCE_RATE 0x00000000
+
+// Field: [1] AUX_COMPB_SYNC_RATE
+//
+// Select synchronization rate for AUX_EVCTL:EVSTAT2.AUX_COMPB event.
+// ENUMs:
+// BUS_RATE AUX bus rate
+// SCE_RATE SCE rate
+#define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE 0x00000002
+#define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE_BITN 1
+#define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE_M 0x00000002
+#define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE_S 1
+#define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE_BUS_RATE 0x00000002
+#define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE_SCE_RATE 0x00000000
+
+// Field: [0] AUX_TIMER2_SYNC_RATE
+//
+// Select synchronization rate for:
+// - AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0
+// - AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1
+// - AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2
+// - AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3
+// - AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE
+// ENUMs:
+// BUS_RATE AUX bus rate
+// SCE_RATE SCE rate
+#define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE 0x00000001
+#define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE_BITN 0
+#define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE_M 0x00000001
+#define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE_S 0
+#define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE_BUS_RATE 0x00000001
+#define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE_SCE_RATE 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_PEROPRATE
+//
+//*****************************************************************************
+// Field: [3] ANAIF_DAC_OP_RATE
+//
+// Select operational rate for AUX_ANAIF DAC sample clock state machine.
+// ENUMs:
+// BUS_RATE AUX bus rate
+// SCE_RATE SCE rate
+#define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE 0x00000008
+#define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE_BITN 3
+#define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE_M 0x00000008
+#define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE_S 3
+#define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE_BUS_RATE 0x00000008
+#define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE_SCE_RATE 0x00000000
+
+// Field: [2] TIMER01_OP_RATE
+//
+// Select operational rate for AUX_TIMER01.
+// ENUMs:
+// BUS_RATE AUX bus rate
+// SCE_RATE SCE rate
+#define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE 0x00000004
+#define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE_BITN 2
+#define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE_M 0x00000004
+#define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE_S 2
+#define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE_BUS_RATE 0x00000004
+#define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE_SCE_RATE 0x00000000
+
+// Field: [1] SPIM_OP_RATE
+//
+// Select operational rate for AUX_SPIM.
+// ENUMs:
+// BUS_RATE AUX bus rate
+// SCE_RATE SCE rate
+#define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE 0x00000002
+#define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE_BITN 1
+#define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE_M 0x00000002
+#define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE_S 1
+#define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE_BUS_RATE 0x00000002
+#define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE_SCE_RATE 0x00000000
+
+// Field: [0] MAC_OP_RATE
+//
+// Select operational rate for AUX_MAC.
+// ENUMs:
+// BUS_RATE AUX bus rate
+// SCE_RATE SCE rate
+#define AUX_SYSIF_PEROPRATE_MAC_OP_RATE 0x00000001
+#define AUX_SYSIF_PEROPRATE_MAC_OP_RATE_BITN 0
+#define AUX_SYSIF_PEROPRATE_MAC_OP_RATE_M 0x00000001
+#define AUX_SYSIF_PEROPRATE_MAC_OP_RATE_S 0
+#define AUX_SYSIF_PEROPRATE_MAC_OP_RATE_BUS_RATE 0x00000001
+#define AUX_SYSIF_PEROPRATE_MAC_OP_RATE_SCE_RATE 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_ADCCLKCTL
+//
+//*****************************************************************************
+// Field: [1] ACK
+//
+// Clock acknowledgement.
+//
+// 0: ADC clock is disabled.
+// 1: ADC clock is enabled.
+#define AUX_SYSIF_ADCCLKCTL_ACK 0x00000002
+#define AUX_SYSIF_ADCCLKCTL_ACK_BITN 1
+#define AUX_SYSIF_ADCCLKCTL_ACK_M 0x00000002
+#define AUX_SYSIF_ADCCLKCTL_ACK_S 1
+
+// Field: [0] REQ
+//
+// ADC clock request.
+//
+// 0: Disable ADC clock.
+// 1: Enable ADC clock.
+//
+// Only modify REQ when equal to ACK.
+#define AUX_SYSIF_ADCCLKCTL_REQ 0x00000001
+#define AUX_SYSIF_ADCCLKCTL_REQ_BITN 0
+#define AUX_SYSIF_ADCCLKCTL_REQ_M 0x00000001
+#define AUX_SYSIF_ADCCLKCTL_REQ_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_TDCCLKCTL
+//
+//*****************************************************************************
+// Field: [1] ACK
+//
+// TDC counter clock acknowledgement.
+//
+// 0: TDC counter clock is disabled.
+// 1: TDC counter clock is enabled.
+#define AUX_SYSIF_TDCCLKCTL_ACK 0x00000002
+#define AUX_SYSIF_TDCCLKCTL_ACK_BITN 1
+#define AUX_SYSIF_TDCCLKCTL_ACK_M 0x00000002
+#define AUX_SYSIF_TDCCLKCTL_ACK_S 1
+
+// Field: [0] REQ
+//
+// TDC counter clock request.
+//
+// 0: Disable TDC counter clock.
+// 1: Enable TDC counter clock.
+//
+// Only modify REQ when equal to ACK.
+#define AUX_SYSIF_TDCCLKCTL_REQ 0x00000001
+#define AUX_SYSIF_TDCCLKCTL_REQ_BITN 0
+#define AUX_SYSIF_TDCCLKCTL_REQ_M 0x00000001
+#define AUX_SYSIF_TDCCLKCTL_REQ_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_TDCREFCLKCTL
+//
+//*****************************************************************************
+// Field: [1] ACK
+//
+// TDC reference clock acknowledgement.
+//
+// 0: TDC reference clock is disabled.
+// 1: TDC reference clock is enabled.
+#define AUX_SYSIF_TDCREFCLKCTL_ACK 0x00000002
+#define AUX_SYSIF_TDCREFCLKCTL_ACK_BITN 1
+#define AUX_SYSIF_TDCREFCLKCTL_ACK_M 0x00000002
+#define AUX_SYSIF_TDCREFCLKCTL_ACK_S 1
+
+// Field: [0] REQ
+//
+// TDC reference clock request.
+//
+// 0: Disable TDC reference clock.
+// 1: Enable TDC reference clock.
+//
+// Only modify REQ when equal to ACK.
+#define AUX_SYSIF_TDCREFCLKCTL_REQ 0x00000001
+#define AUX_SYSIF_TDCREFCLKCTL_REQ_BITN 0
+#define AUX_SYSIF_TDCREFCLKCTL_REQ_M 0x00000001
+#define AUX_SYSIF_TDCREFCLKCTL_REQ_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_TIMER2CLKCTL
+//
+//*****************************************************************************
+// Field: [2:0] SRC
+//
+// Select clock source for AUX_TIMER2.
+//
+// Update is only accepted if SRC equals TIMER2CLKSTAT.STAT or
+// TIMER2CLKSWITCH.RDY is 1.
+//
+// It is recommended to select NONE only when TIMER2BRIDGE.BUSY is 0.
+//
+// A non-enumerated value is ignored.
+// ENUMs:
+// SCLK_HFDIV2 SCLK_HF / 2
+// SCLK_MF SCLK_MF
+// SCLK_LF SCLK_LF
+// NONE no clock
+#define AUX_SYSIF_TIMER2CLKCTL_SRC_W 3
+#define AUX_SYSIF_TIMER2CLKCTL_SRC_M 0x00000007
+#define AUX_SYSIF_TIMER2CLKCTL_SRC_S 0
+#define AUX_SYSIF_TIMER2CLKCTL_SRC_SCLK_HFDIV2 0x00000004
+#define AUX_SYSIF_TIMER2CLKCTL_SRC_SCLK_MF 0x00000002
+#define AUX_SYSIF_TIMER2CLKCTL_SRC_SCLK_LF 0x00000001
+#define AUX_SYSIF_TIMER2CLKCTL_SRC_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_TIMER2CLKSTAT
+//
+//*****************************************************************************
+// Field: [2:0] STAT
+//
+// AUX_TIMER2 clock source status.
+// ENUMs:
+// SCLK_HFDIV2 SCLK_HF / 2
+// SCLK_MF SCLK_MF
+// SCLK_LF SCLK_LF
+// NONE No clock
+#define AUX_SYSIF_TIMER2CLKSTAT_STAT_W 3
+#define AUX_SYSIF_TIMER2CLKSTAT_STAT_M 0x00000007
+#define AUX_SYSIF_TIMER2CLKSTAT_STAT_S 0
+#define AUX_SYSIF_TIMER2CLKSTAT_STAT_SCLK_HFDIV2 0x00000004
+#define AUX_SYSIF_TIMER2CLKSTAT_STAT_SCLK_MF 0x00000002
+#define AUX_SYSIF_TIMER2CLKSTAT_STAT_SCLK_LF 0x00000001
+#define AUX_SYSIF_TIMER2CLKSTAT_STAT_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_TIMER2CLKSWITCH
+//
+//*****************************************************************************
+// Field: [0] RDY
+//
+// Status of clock switcher.
+//
+// 0: TIMER2CLKCTL.SRC is different from TIMER2CLKSTAT.STAT.
+// 1: TIMER2CLKCTL.SRC equals TIMER2CLKSTAT.STAT.
+//
+// RDY connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY.
+#define AUX_SYSIF_TIMER2CLKSWITCH_RDY 0x00000001
+#define AUX_SYSIF_TIMER2CLKSWITCH_RDY_BITN 0
+#define AUX_SYSIF_TIMER2CLKSWITCH_RDY_M 0x00000001
+#define AUX_SYSIF_TIMER2CLKSWITCH_RDY_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_TIMER2DBGCTL
+//
+//*****************************************************************************
+// Field: [0] DBG_FREEZE_EN
+//
+// Debug freeze enable.
+//
+// 0: AUX_TIMER2 does not halt when the system CPU halts in debug mode.
+// 1: Halt AUX_TIMER2 when the system CPU halts in debug mode.
+#define AUX_SYSIF_TIMER2DBGCTL_DBG_FREEZE_EN 0x00000001
+#define AUX_SYSIF_TIMER2DBGCTL_DBG_FREEZE_EN_BITN 0
+#define AUX_SYSIF_TIMER2DBGCTL_DBG_FREEZE_EN_M 0x00000001
+#define AUX_SYSIF_TIMER2DBGCTL_DBG_FREEZE_EN_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_CLKSHIFTDET
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Clock shift detection.
+//
+// Write:
+//
+// 0: Restart clock shift detection.
+// 1: Do not use.
+//
+// Read:
+//
+// 0: MCU domain did not enter or exit active state since you wrote 0 to STAT.
+// 1: MCU domain entered or exited active state since you wrote 0 to STAT.
+#define AUX_SYSIF_CLKSHIFTDET_STAT 0x00000001
+#define AUX_SYSIF_CLKSHIFTDET_STAT_BITN 0
+#define AUX_SYSIF_CLKSHIFTDET_STAT_M 0x00000001
+#define AUX_SYSIF_CLKSHIFTDET_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_RECHARGETRIG
+//
+//*****************************************************************************
+// Field: [0] TRIG
+//
+// Recharge trigger.
+//
+// 0: No effect.
+// 1: Request VDDR recharge.
+//
+// Request VDDR recharge only when AUX_EVCTL:EVSTAT2.PWR_DWN is 1.
+//
+// Follow this sequence when OPMODEREQ.REQ is LP:
+// - Set TRIG.
+// - Wait until AUX_EVCTL:EVSTAT2.VDDR_RECHARGE is 1.
+// - Clear TRIG.
+// - Wait until AUX_EVCTL:EVSTAT2.VDDR_RECHARGE is 0.
+//
+// Follow this sequence when OPMODEREQ.REQ is PDA or PDLP:
+// - Set TRIG.
+// - Clear TRIG.
+#define AUX_SYSIF_RECHARGETRIG_TRIG 0x00000001
+#define AUX_SYSIF_RECHARGETRIG_TRIG_BITN 0
+#define AUX_SYSIF_RECHARGETRIG_TRIG_M 0x00000001
+#define AUX_SYSIF_RECHARGETRIG_TRIG_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_RECHARGEDET
+//
+//*****************************************************************************
+// Field: [1] STAT
+//
+// VDDR recharge detector status.
+//
+// 0: No recharge of VDDR has occurred since EN was set.
+// 1: Recharge of VDDR has occurred since EN was set.
+#define AUX_SYSIF_RECHARGEDET_STAT 0x00000002
+#define AUX_SYSIF_RECHARGEDET_STAT_BITN 1
+#define AUX_SYSIF_RECHARGEDET_STAT_M 0x00000002
+#define AUX_SYSIF_RECHARGEDET_STAT_S 1
+
+// Field: [0] EN
+//
+// VDDR recharge detector enable.
+//
+// 0: Disable recharge detection. STAT becomes zero.
+// 1: Enable recharge detection.
+#define AUX_SYSIF_RECHARGEDET_EN 0x00000001
+#define AUX_SYSIF_RECHARGEDET_EN_BITN 0
+#define AUX_SYSIF_RECHARGEDET_EN_M 0x00000001
+#define AUX_SYSIF_RECHARGEDET_EN_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_RTCSUBSECINC0
+//
+//*****************************************************************************
+// Field: [15:0] INC15_0
+//
+// New value for bits 15:0 in AON_RTC:SUBSECINC.
+#define AUX_SYSIF_RTCSUBSECINC0_INC15_0_W 16
+#define AUX_SYSIF_RTCSUBSECINC0_INC15_0_M 0x0000FFFF
+#define AUX_SYSIF_RTCSUBSECINC0_INC15_0_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_RTCSUBSECINC1
+//
+//*****************************************************************************
+// Field: [7:0] INC23_16
+//
+// New value for bits 23:16 in AON_RTC:SUBSECINC.
+#define AUX_SYSIF_RTCSUBSECINC1_INC23_16_W 8
+#define AUX_SYSIF_RTCSUBSECINC1_INC23_16_M 0x000000FF
+#define AUX_SYSIF_RTCSUBSECINC1_INC23_16_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_RTCSUBSECINCCTL
+//
+//*****************************************************************************
+// Field: [1] UPD_ACK
+//
+// Update acknowledgement.
+//
+// 0: AON_RTC has not acknowledged UPD_REQ.
+// 1: AON_RTC has acknowledged UPD_REQ.
+#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK 0x00000002
+#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK_BITN 1
+#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK_M 0x00000002
+#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK_S 1
+
+// Field: [0] UPD_REQ
+//
+// Request AON_RTC to update AON_RTC:SUBSECINC.
+//
+// 0: Clear request to update.
+// 1: Set request to update.
+//
+// Only change UPD_REQ when it equals UPD_ACK. Clear UPD_REQ after UPD_ACK is
+// 1.
+#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ 0x00000001
+#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ_BITN 0
+#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ_M 0x00000001
+#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_RTCSEC
+//
+//*****************************************************************************
+// Field: [15:0] SEC
+//
+// Bits 15:0 in AON_RTC:SEC.VALUE.
+//
+// Follow this procedure to get the correct value:
+// - Do two dummy reads of SEC.
+// - Then read SEC until two consecutive reads are equal.
+#define AUX_SYSIF_RTCSEC_SEC_W 16
+#define AUX_SYSIF_RTCSEC_SEC_M 0x0000FFFF
+#define AUX_SYSIF_RTCSEC_SEC_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_RTCSUBSEC
+//
+//*****************************************************************************
+// Field: [15:0] SUBSEC
+//
+// Bits 31:16 in AON_RTC:SUBSEC.VALUE.
+//
+// Follow this procedure to get the correct value:
+// - Do two dummy reads SUBSEC.
+// - Then read SUBSEC until two consecutive reads are equal.
+#define AUX_SYSIF_RTCSUBSEC_SUBSEC_W 16
+#define AUX_SYSIF_RTCSUBSEC_SUBSEC_M 0x0000FFFF
+#define AUX_SYSIF_RTCSUBSEC_SUBSEC_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_RTCEVCLR
+//
+//*****************************************************************************
+// Field: [0] RTC_CH2_EV_CLR
+//
+// Clear events from AON_RTC channel 2.
+//
+// 0: No effect.
+// 1: Clear events from AON_RTC channel 2.
+//
+// Keep RTC_CH2_EV_CLR high until AUX_EVCTL:EVSTAT2.AON_RTC_CH2 and
+// AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY are 0.
+#define AUX_SYSIF_RTCEVCLR_RTC_CH2_EV_CLR 0x00000001
+#define AUX_SYSIF_RTCEVCLR_RTC_CH2_EV_CLR_BITN 0
+#define AUX_SYSIF_RTCEVCLR_RTC_CH2_EV_CLR_M 0x00000001
+#define AUX_SYSIF_RTCEVCLR_RTC_CH2_EV_CLR_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_BATMONBAT
+//
+//*****************************************************************************
+// Field: [10:8] INT
+//
+// See AON_BATMON:BAT.INT.
+//
+// Follow this procedure to get the correct value:
+// - Do two dummy reads of INT.
+// - Then read INT until two consecutive reads are equal.
+#define AUX_SYSIF_BATMONBAT_INT_W 3
+#define AUX_SYSIF_BATMONBAT_INT_M 0x00000700
+#define AUX_SYSIF_BATMONBAT_INT_S 8
+
+// Field: [7:0] FRAC
+//
+// See AON_BATMON:BAT.FRAC.
+//
+// Follow this procedure to get the correct value:
+// - Do two dummy reads of FRAC.
+// - Then read FRAC until two consecutive reads are equal.
+#define AUX_SYSIF_BATMONBAT_FRAC_W 8
+#define AUX_SYSIF_BATMONBAT_FRAC_M 0x000000FF
+#define AUX_SYSIF_BATMONBAT_FRAC_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_BATMONTEMP
+//
+//*****************************************************************************
+// Field: [15:11] SIGN
+//
+// Sign extension of INT.
+//
+// Follow this procedure to get the correct value:
+// - Do two dummy reads of SIGN.
+// - Then read SIGN until two consecutive reads are equal.
+#define AUX_SYSIF_BATMONTEMP_SIGN_W 5
+#define AUX_SYSIF_BATMONTEMP_SIGN_M 0x0000F800
+#define AUX_SYSIF_BATMONTEMP_SIGN_S 11
+
+// Field: [10:2] INT
+//
+// See AON_BATMON:TEMP.INT.
+//
+// Follow this procedure to get the correct value:
+// - Do two dummy reads of INT.
+// - Then read INT until two consecutive reads are equal.
+#define AUX_SYSIF_BATMONTEMP_INT_W 9
+#define AUX_SYSIF_BATMONTEMP_INT_M 0x000007FC
+#define AUX_SYSIF_BATMONTEMP_INT_S 2
+
+// Field: [1:0] FRAC
+//
+// See AON_BATMON:TEMP.FRAC.
+//
+// Follow this procedure to get the correct value:
+// - Do two dummy reads of FRAC.
+// - Then read FRAC until two consecutive reads are equal.
+#define AUX_SYSIF_BATMONTEMP_FRAC_W 2
+#define AUX_SYSIF_BATMONTEMP_FRAC_M 0x00000003
+#define AUX_SYSIF_BATMONTEMP_FRAC_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_TIMERHALT
+//
+//*****************************************************************************
+// Field: [3] PROGDLY
+//
+// Halt programmable delay.
+//
+// 0: AUX_EVCTL:PROGDLY.VALUE decrements as normal.
+// 1: Halt AUX_EVCTL:PROGDLY.VALUE decrementation.
+#define AUX_SYSIF_TIMERHALT_PROGDLY 0x00000008
+#define AUX_SYSIF_TIMERHALT_PROGDLY_BITN 3
+#define AUX_SYSIF_TIMERHALT_PROGDLY_M 0x00000008
+#define AUX_SYSIF_TIMERHALT_PROGDLY_S 3
+
+// Field: [2] AUX_TIMER2
+//
+// Halt AUX_TIMER2.
+//
+// 0: AUX_TIMER2 operates as normal.
+// 1: Halt AUX_TIMER2 operation.
+#define AUX_SYSIF_TIMERHALT_AUX_TIMER2 0x00000004
+#define AUX_SYSIF_TIMERHALT_AUX_TIMER2_BITN 2
+#define AUX_SYSIF_TIMERHALT_AUX_TIMER2_M 0x00000004
+#define AUX_SYSIF_TIMERHALT_AUX_TIMER2_S 2
+
+// Field: [1] AUX_TIMER1
+//
+// Halt AUX_TIMER01 Timer 1.
+//
+// 0: AUX_TIMER01 Timer 1 operates as normal.
+// 1: Halt AUX_TIMER01 Timer 1 operation.
+#define AUX_SYSIF_TIMERHALT_AUX_TIMER1 0x00000002
+#define AUX_SYSIF_TIMERHALT_AUX_TIMER1_BITN 1
+#define AUX_SYSIF_TIMERHALT_AUX_TIMER1_M 0x00000002
+#define AUX_SYSIF_TIMERHALT_AUX_TIMER1_S 1
+
+// Field: [0] AUX_TIMER0
+//
+// Halt AUX_TIMER01 Timer 0.
+//
+// 0: AUX_TIMER01 Timer 0 operates as normal.
+// 1: Halt AUX_TIMER01 Timer 0 operation.
+#define AUX_SYSIF_TIMERHALT_AUX_TIMER0 0x00000001
+#define AUX_SYSIF_TIMERHALT_AUX_TIMER0_BITN 0
+#define AUX_SYSIF_TIMERHALT_AUX_TIMER0_M 0x00000001
+#define AUX_SYSIF_TIMERHALT_AUX_TIMER0_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_TIMER2BRIDGE
+//
+//*****************************************************************************
+// Field: [0] BUSY
+//
+// Status of bus transactions to AUX_TIMER2.
+//
+// 0: No unfinished bus transactions.
+// 1: A bus transaction is ongoing.
+#define AUX_SYSIF_TIMER2BRIDGE_BUSY 0x00000001
+#define AUX_SYSIF_TIMER2BRIDGE_BUSY_BITN 0
+#define AUX_SYSIF_TIMER2BRIDGE_BUSY_M 0x00000001
+#define AUX_SYSIF_TIMER2BRIDGE_BUSY_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_SYSIF_O_SWPWRPROF
+//
+//*****************************************************************************
+// Field: [2:0] STAT
+//
+// Software status bits that can be read by the power profiler.
+#define AUX_SYSIF_SWPWRPROF_STAT_W 3
+#define AUX_SYSIF_SWPWRPROF_STAT_M 0x00000007
+#define AUX_SYSIF_SWPWRPROF_STAT_S 0
+
+
+#endif // __AUX_SYSIF__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_tdc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_tdc.h
new file mode 100644
index 0000000..002d740
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_tdc.h
@@ -0,0 +1,879 @@
+/******************************************************************************
+* Filename: hw_aux_tdc_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_AUX_TDC_H__
+#define __HW_AUX_TDC_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// AUX_TDC component
+//
+//*****************************************************************************
+// Control
+#define AUX_TDC_O_CTL 0x00000000
+
+// Status
+#define AUX_TDC_O_STAT 0x00000004
+
+// Result
+#define AUX_TDC_O_RESULT 0x00000008
+
+// Saturation Configuration
+#define AUX_TDC_O_SATCFG 0x0000000C
+
+// Trigger Source
+#define AUX_TDC_O_TRIGSRC 0x00000010
+
+// Trigger Counter
+#define AUX_TDC_O_TRIGCNT 0x00000014
+
+// Trigger Counter Load
+#define AUX_TDC_O_TRIGCNTLOAD 0x00000018
+
+// Trigger Counter Configuration
+#define AUX_TDC_O_TRIGCNTCFG 0x0000001C
+
+// Prescaler Control
+#define AUX_TDC_O_PRECTL 0x00000020
+
+// Prescaler Counter
+#define AUX_TDC_O_PRECNTR 0x00000024
+
+//*****************************************************************************
+//
+// Register: AUX_TDC_O_CTL
+//
+//*****************************************************************************
+// Field: [1:0] CMD
+//
+// TDC commands.
+// ENUMs:
+// ABORT Force TDC state machine back to IDLE state.
+//
+// Never write this command
+// while AUX_TDC:STAT.STATE equals CLR_CNT or
+// WAIT_CLR_CNT_DONE.
+// RUN Asynchronous counter start.
+//
+// The counter starts to
+// count when the start event is high. To achieve
+// precise edge-to-edge measurements you must
+// ensure that the start event is low for at least
+// 420 ns after you write this command.
+// RUN_SYNC_START Synchronous counter start.
+//
+// The counter looks for the
+// opposite edge of the selected start event
+// before it starts to count when the selected
+// edge occurs. This guarantees an edge-triggered
+// start and is recommended for frequency
+// measurements.
+// CLR_RESULT Clear STAT.SAT, STAT.DONE, and RESULT.VALUE.
+//
+// This is not needed as
+// prerequisite for a measurement. Reliable clear
+// is only guaranteed from IDLE state.
+#define AUX_TDC_CTL_CMD_W 2
+#define AUX_TDC_CTL_CMD_M 0x00000003
+#define AUX_TDC_CTL_CMD_S 0
+#define AUX_TDC_CTL_CMD_ABORT 0x00000003
+#define AUX_TDC_CTL_CMD_RUN 0x00000002
+#define AUX_TDC_CTL_CMD_RUN_SYNC_START 0x00000001
+#define AUX_TDC_CTL_CMD_CLR_RESULT 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_TDC_O_STAT
+//
+//*****************************************************************************
+// Field: [7] SAT
+//
+// TDC measurement saturation flag.
+//
+// 0: Conversion has not saturated.
+// 1: Conversion stopped due to saturation.
+//
+// This field is cleared when a new measurement is started or when CLR_RESULT
+// is written to CTL.CMD.
+#define AUX_TDC_STAT_SAT 0x00000080
+#define AUX_TDC_STAT_SAT_BITN 7
+#define AUX_TDC_STAT_SAT_M 0x00000080
+#define AUX_TDC_STAT_SAT_S 7
+
+// Field: [6] DONE
+//
+// TDC measurement complete flag.
+//
+// 0: TDC measurement has not yet completed.
+// 1: TDC measurement has completed.
+//
+// This field clears when a new TDC measurement starts or when you write
+// CLR_RESULT to CTL.CMD.
+#define AUX_TDC_STAT_DONE 0x00000040
+#define AUX_TDC_STAT_DONE_BITN 6
+#define AUX_TDC_STAT_DONE_M 0x00000040
+#define AUX_TDC_STAT_DONE_S 6
+
+// Field: [5:0] STATE
+//
+// TDC state machine status.
+// ENUMs:
+// FORCE_STOP Current state is TDC_FORCESTOP.
+// You wrote ABORT to
+// CTL.CMD to abort the TDC measurement.
+// START_FALL Current state is TDC_WAIT_STARTFALL.
+// The fast-counter circuit
+// waits for a falling edge on the start event.
+// WAIT_CLR_CNT_DONE Current state is TDC_STATE_WAIT_CLRCNT_DONE.
+// The state machine waits
+// for fast-counter circuit to finish reset.
+// POR Current state is TDC_STATE_POR.
+// This is the reset state.
+// GET_RESULT Current state is TDC_STATE_GETRESULTS.
+// The state machine copies
+// the counter value from the fast-counter
+// circuit.
+// WAIT_STOP_CNTDWN Current state is TDC_STATE_WAIT_STOPCNTDOWN.
+// The fast-counter circuit
+// looks for the stop condition. It will ignore a
+// number of stop events configured in
+// TRIGCNTLOAD.CNT.
+// WAIT_STOP Current state is TDC_STATE_WAIT_STOP.
+// The state machine waits
+// for the fast-counter circuit to stop.
+// CLR_CNT Current state is TDC_STATE_CLRCNT. The
+// fast-counter circuit is reset.
+// IDLE Current state is TDC_STATE_IDLE.
+// This is the default state
+// after reset and abortion. State will change
+// when you write CTL.CMD to either RUN_SYNC_START
+// or RUN.
+// WAIT_START_STOP_CNT_EN Current state is TDC_STATE_WAIT_STARTSTOPCNTEN.
+// The fast-counter circuit
+// looks for the start condition. The state
+// machine waits for the fast-counter to
+// increment.
+// WAIT_START Current state is TDC_STATE_WAIT_START.
+// The fast-counter circuit
+// looks for the start condition. The state
+// machine waits for the fast-counter to
+// increment.
+#define AUX_TDC_STAT_STATE_W 6
+#define AUX_TDC_STAT_STATE_M 0x0000003F
+#define AUX_TDC_STAT_STATE_S 0
+#define AUX_TDC_STAT_STATE_FORCE_STOP 0x0000002E
+#define AUX_TDC_STAT_STATE_START_FALL 0x0000001E
+#define AUX_TDC_STAT_STATE_WAIT_CLR_CNT_DONE 0x00000016
+#define AUX_TDC_STAT_STATE_POR 0x0000000F
+#define AUX_TDC_STAT_STATE_GET_RESULT 0x0000000E
+#define AUX_TDC_STAT_STATE_WAIT_STOP_CNTDWN 0x0000000C
+#define AUX_TDC_STAT_STATE_WAIT_STOP 0x00000008
+#define AUX_TDC_STAT_STATE_CLR_CNT 0x00000007
+#define AUX_TDC_STAT_STATE_IDLE 0x00000006
+#define AUX_TDC_STAT_STATE_WAIT_START_STOP_CNT_EN 0x00000004
+#define AUX_TDC_STAT_STATE_WAIT_START 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_TDC_O_RESULT
+//
+//*****************************************************************************
+// Field: [24:0] VALUE
+//
+// TDC conversion result.
+//
+// The result of the TDC conversion is given in number of clock edges of the
+// clock source selected in DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL. Both rising and
+// falling edges are counted.
+//
+// If TDC counter saturates, VALUE is slightly higher than SATCFG.LIMIT, as it
+// takes a non-zero time to stop the measurement. Hence, the maximum value of
+// this field becomes slightly higher than 2^24 if you configure SATCFG.LIMIT
+// to R24.
+#define AUX_TDC_RESULT_VALUE_W 25
+#define AUX_TDC_RESULT_VALUE_M 0x01FFFFFF
+#define AUX_TDC_RESULT_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_TDC_O_SATCFG
+//
+//*****************************************************************************
+// Field: [3:0] LIMIT
+//
+// Saturation limit.
+//
+// The flag STAT.SAT is set when the TDC counter saturates.
+//
+// Values not enumerated are not supported
+// ENUMs:
+// R24 Result bit 24: TDC conversion saturates and stops
+// when RESULT.VALUE[24] is set.
+// R23 Result bit 23: TDC conversion saturates and stops
+// when RESULT.VALUE[23] is set.
+// R22 Result bit 22: TDC conversion saturates and stops
+// when RESULT.VALUE[22] is set.
+// R21 Result bit 21: TDC conversion saturates and stops
+// when RESULT.VALUE[21] is set.
+// R20 Result bit 20: TDC conversion saturates and stops
+// when RESULT.VALUE[20] is set.
+// R19 Result bit 19: TDC conversion saturates and stops
+// when RESULT.VALUE[19] is set.
+// R18 Result bit 18: TDC conversion saturates and stops
+// when RESULT.VALUE[18] is set.
+// R17 Result bit 17: TDC conversion saturates and stops
+// when RESULT.VALUE[17] is set.
+// R16 Result bit 16: TDC conversion saturates and stops
+// when RESULT.VALUE[16] is set.
+// R15 Result bit 15: TDC conversion saturates and stops
+// when RESULT.VALUE[15] is set.
+// R14 Result bit 14: TDC conversion saturates and stops
+// when RESULT.VALUE[14] is set.
+// R13 Result bit 13: TDC conversion saturates and stops
+// when RESULT.VALUE[13] is set.
+// R12 Result bit 12: TDC conversion saturates and stops
+// when RESULT.VALUE[12] is set.
+#define AUX_TDC_SATCFG_LIMIT_W 4
+#define AUX_TDC_SATCFG_LIMIT_M 0x0000000F
+#define AUX_TDC_SATCFG_LIMIT_S 0
+#define AUX_TDC_SATCFG_LIMIT_R24 0x0000000F
+#define AUX_TDC_SATCFG_LIMIT_R23 0x0000000E
+#define AUX_TDC_SATCFG_LIMIT_R22 0x0000000D
+#define AUX_TDC_SATCFG_LIMIT_R21 0x0000000C
+#define AUX_TDC_SATCFG_LIMIT_R20 0x0000000B
+#define AUX_TDC_SATCFG_LIMIT_R19 0x0000000A
+#define AUX_TDC_SATCFG_LIMIT_R18 0x00000009
+#define AUX_TDC_SATCFG_LIMIT_R17 0x00000008
+#define AUX_TDC_SATCFG_LIMIT_R16 0x00000007
+#define AUX_TDC_SATCFG_LIMIT_R15 0x00000006
+#define AUX_TDC_SATCFG_LIMIT_R14 0x00000005
+#define AUX_TDC_SATCFG_LIMIT_R13 0x00000004
+#define AUX_TDC_SATCFG_LIMIT_R12 0x00000003
+
+//*****************************************************************************
+//
+// Register: AUX_TDC_O_TRIGSRC
+//
+//*****************************************************************************
+// Field: [14] STOP_POL
+//
+// Polarity of stop source.
+//
+// Change only while STAT.STATE is IDLE.
+// ENUMs:
+// LOW TDC conversion stops when low level is detected.
+// HIGH TDC conversion stops when high level is detected.
+#define AUX_TDC_TRIGSRC_STOP_POL 0x00004000
+#define AUX_TDC_TRIGSRC_STOP_POL_BITN 14
+#define AUX_TDC_TRIGSRC_STOP_POL_M 0x00004000
+#define AUX_TDC_TRIGSRC_STOP_POL_S 14
+#define AUX_TDC_TRIGSRC_STOP_POL_LOW 0x00004000
+#define AUX_TDC_TRIGSRC_STOP_POL_HIGH 0x00000000
+
+// Field: [13:8] STOP_SRC
+//
+// Select stop source from the asynchronous AUX event bus.
+//
+// Change only while STAT.STATE is IDLE.
+// ENUMs:
+// NO_EVENT No event.
+// AUX_TDC_PRE Select TDC Prescaler event which is generated by
+// configuration of PRECTL.
+// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE
+// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY
+// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL
+// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ
+// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE
+// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N
+// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE
+// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV
+// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV
+// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE
+// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3
+// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2
+// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1
+// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0
+// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB
+// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA
+// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1
+// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0
+// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV
+// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF
+// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE
+// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE
+// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN
+// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF
+// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD
+// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD
+// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ
+// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY
+// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2
+// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV
+// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31
+// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30
+// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29
+// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28
+// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27
+// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26
+// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25
+// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24
+// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23
+// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22
+// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21
+// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20
+// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19
+// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18
+// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17
+// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16
+// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15
+// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14
+// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13
+// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12
+// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11
+// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10
+// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9
+// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8
+// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7
+// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6
+// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5
+// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4
+// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3
+// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2
+// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1
+// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0
+#define AUX_TDC_TRIGSRC_STOP_SRC_W 6
+#define AUX_TDC_TRIGSRC_STOP_SRC_M 0x00003F00
+#define AUX_TDC_TRIGSRC_STOP_SRC_S 8
+#define AUX_TDC_TRIGSRC_STOP_SRC_NO_EVENT 0x00003F00
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TDC_PRE 0x00003E00
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_SMPH_AUTOTAKE_DONE 0x00003D00
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00003C00
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00003B00
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_IRQ 0x00003A00
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_DONE 0x00003900
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_ISRC_RESET_N 0x00003800
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TDC_DONE 0x00003700
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER0_EV 0x00003600
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER1_EV 0x00003500
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_PULSE 0x00003400
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV3 0x00003300
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV2 0x00003200
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV1 0x00003100
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV0 0x00003000
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPB 0x00002F00
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPA 0x00002E00
+#define AUX_TDC_TRIGSRC_STOP_SRC_MCU_OBSMUX1 0x00002D00
+#define AUX_TDC_TRIGSRC_STOP_SRC_MCU_OBSMUX0 0x00002C00
+#define AUX_TDC_TRIGSRC_STOP_SRC_MCU_EV 0x00002B00
+#define AUX_TDC_TRIGSRC_STOP_SRC_ACLK_REF 0x00002A00
+#define AUX_TDC_TRIGSRC_STOP_SRC_VDDR_RECHARGE 0x00002900
+#define AUX_TDC_TRIGSRC_STOP_SRC_MCU_ACTIVE 0x00002800
+#define AUX_TDC_TRIGSRC_STOP_SRC_PWR_DWN 0x00002700
+#define AUX_TDC_TRIGSRC_STOP_SRC_SCLK_LF 0x00002600
+#define AUX_TDC_TRIGSRC_STOP_SRC_AON_BATMON_TEMP_UPD 0x00002500
+#define AUX_TDC_TRIGSRC_STOP_SRC_AON_BATMON_BAT_UPD 0x00002400
+#define AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_4KHZ 0x00002300
+#define AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2_DLY 0x00002200
+#define AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2 0x00002100
+#define AUX_TDC_TRIGSRC_STOP_SRC_MANUAL_EV 0x00002000
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO31 0x00001F00
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO30 0x00001E00
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO29 0x00001D00
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO28 0x00001C00
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO27 0x00001B00
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO26 0x00001A00
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO25 0x00001900
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO24 0x00001800
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO23 0x00001700
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO22 0x00001600
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO21 0x00001500
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO20 0x00001400
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO19 0x00001300
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO18 0x00001200
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO17 0x00001100
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO16 0x00001000
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO15 0x00000F00
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO14 0x00000E00
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO13 0x00000D00
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO12 0x00000C00
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO11 0x00000B00
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO10 0x00000A00
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO9 0x00000900
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO8 0x00000800
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO7 0x00000700
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO6 0x00000600
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO5 0x00000500
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO4 0x00000400
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO3 0x00000300
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO2 0x00000200
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO1 0x00000100
+#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO0 0x00000000
+
+// Field: [6] START_POL
+//
+// Polarity of start source.
+//
+// Change only while STAT.STATE is IDLE.
+// ENUMs:
+// LOW TDC conversion starts when low level is detected.
+// HIGH TDC conversion starts when high level is detected.
+#define AUX_TDC_TRIGSRC_START_POL 0x00000040
+#define AUX_TDC_TRIGSRC_START_POL_BITN 6
+#define AUX_TDC_TRIGSRC_START_POL_M 0x00000040
+#define AUX_TDC_TRIGSRC_START_POL_S 6
+#define AUX_TDC_TRIGSRC_START_POL_LOW 0x00000040
+#define AUX_TDC_TRIGSRC_START_POL_HIGH 0x00000000
+
+// Field: [5:0] START_SRC
+//
+// Select start source from the asynchronous AUX event bus.
+//
+// Change only while STAT.STATE is IDLE.
+// ENUMs:
+// NO_EVENT No event.
+// AUX_TDC_PRE Select TDC Prescaler event which is generated by
+// configuration of PRECTL.
+// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE
+// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY
+// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL
+// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ
+// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE
+// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N
+// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE
+// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV
+// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV
+// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE
+// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3
+// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2
+// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1
+// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0
+// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB
+// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA
+// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1
+// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0
+// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV
+// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF
+// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE
+// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE
+// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN
+// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF
+// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD
+// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD
+// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ
+// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY
+// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2
+// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV
+// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31
+// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30
+// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29
+// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28
+// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27
+// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26
+// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25
+// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24
+// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23
+// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22
+// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21
+// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20
+// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19
+// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18
+// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17
+// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16
+// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15
+// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14
+// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13
+// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12
+// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11
+// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10
+// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9
+// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8
+// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7
+// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6
+// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5
+// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4
+// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3
+// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2
+// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1
+// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0
+#define AUX_TDC_TRIGSRC_START_SRC_W 6
+#define AUX_TDC_TRIGSRC_START_SRC_M 0x0000003F
+#define AUX_TDC_TRIGSRC_START_SRC_S 0
+#define AUX_TDC_TRIGSRC_START_SRC_NO_EVENT 0x0000003F
+#define AUX_TDC_TRIGSRC_START_SRC_AUX_TDC_PRE 0x0000003E
+#define AUX_TDC_TRIGSRC_START_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000003D
+#define AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C
+#define AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B
+#define AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_IRQ 0x0000003A
+#define AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_DONE 0x00000039
+#define AUX_TDC_TRIGSRC_START_SRC_AUX_ISRC_RESET_N 0x00000038
+#define AUX_TDC_TRIGSRC_START_SRC_AUX_TDC_DONE 0x00000037
+#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER0_EV 0x00000036
+#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER1_EV 0x00000035
+#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_PULSE 0x00000034
+#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV3 0x00000033
+#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV2 0x00000032
+#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV1 0x00000031
+#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV0 0x00000030
+#define AUX_TDC_TRIGSRC_START_SRC_AUX_COMPB 0x0000002F
+#define AUX_TDC_TRIGSRC_START_SRC_AUX_COMPA 0x0000002E
+#define AUX_TDC_TRIGSRC_START_SRC_MCU_OBSMUX1 0x0000002D
+#define AUX_TDC_TRIGSRC_START_SRC_MCU_OBSMUX0 0x0000002C
+#define AUX_TDC_TRIGSRC_START_SRC_MCU_EV 0x0000002B
+#define AUX_TDC_TRIGSRC_START_SRC_ACLK_REF 0x0000002A
+#define AUX_TDC_TRIGSRC_START_SRC_VDDR_RECHARGE 0x00000029
+#define AUX_TDC_TRIGSRC_START_SRC_MCU_ACTIVE 0x00000028
+#define AUX_TDC_TRIGSRC_START_SRC_PWR_DWN 0x00000027
+#define AUX_TDC_TRIGSRC_START_SRC_SCLK_LF 0x00000026
+#define AUX_TDC_TRIGSRC_START_SRC_AON_BATMON_TEMP_UPD 0x00000025
+#define AUX_TDC_TRIGSRC_START_SRC_AON_BATMON_BAT_UPD 0x00000024
+#define AUX_TDC_TRIGSRC_START_SRC_AON_RTC_4KHZ 0x00000023
+#define AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2_DLY 0x00000022
+#define AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2 0x00000021
+#define AUX_TDC_TRIGSRC_START_SRC_MANUAL_EV 0x00000020
+#define AUX_TDC_TRIGSRC_START_SRC_AUXIO31 0x0000001F
+#define AUX_TDC_TRIGSRC_START_SRC_AUXIO30 0x0000001E
+#define AUX_TDC_TRIGSRC_START_SRC_AUXIO29 0x0000001D
+#define AUX_TDC_TRIGSRC_START_SRC_AUXIO28 0x0000001C
+#define AUX_TDC_TRIGSRC_START_SRC_AUXIO27 0x0000001B
+#define AUX_TDC_TRIGSRC_START_SRC_AUXIO26 0x0000001A
+#define AUX_TDC_TRIGSRC_START_SRC_AUXIO25 0x00000019
+#define AUX_TDC_TRIGSRC_START_SRC_AUXIO24 0x00000018
+#define AUX_TDC_TRIGSRC_START_SRC_AUXIO23 0x00000017
+#define AUX_TDC_TRIGSRC_START_SRC_AUXIO22 0x00000016
+#define AUX_TDC_TRIGSRC_START_SRC_AUXIO21 0x00000015
+#define AUX_TDC_TRIGSRC_START_SRC_AUXIO20 0x00000014
+#define AUX_TDC_TRIGSRC_START_SRC_AUXIO19 0x00000013
+#define AUX_TDC_TRIGSRC_START_SRC_AUXIO18 0x00000012
+#define AUX_TDC_TRIGSRC_START_SRC_AUXIO17 0x00000011
+#define AUX_TDC_TRIGSRC_START_SRC_AUXIO16 0x00000010
+#define AUX_TDC_TRIGSRC_START_SRC_AUXIO15 0x0000000F
+#define AUX_TDC_TRIGSRC_START_SRC_AUXIO14 0x0000000E
+#define AUX_TDC_TRIGSRC_START_SRC_AUXIO13 0x0000000D
+#define AUX_TDC_TRIGSRC_START_SRC_AUXIO12 0x0000000C
+#define AUX_TDC_TRIGSRC_START_SRC_AUXIO11 0x0000000B
+#define AUX_TDC_TRIGSRC_START_SRC_AUXIO10 0x0000000A
+#define AUX_TDC_TRIGSRC_START_SRC_AUXIO9 0x00000009
+#define AUX_TDC_TRIGSRC_START_SRC_AUXIO8 0x00000008
+#define AUX_TDC_TRIGSRC_START_SRC_AUXIO7 0x00000007
+#define AUX_TDC_TRIGSRC_START_SRC_AUXIO6 0x00000006
+#define AUX_TDC_TRIGSRC_START_SRC_AUXIO5 0x00000005
+#define AUX_TDC_TRIGSRC_START_SRC_AUXIO4 0x00000004
+#define AUX_TDC_TRIGSRC_START_SRC_AUXIO3 0x00000003
+#define AUX_TDC_TRIGSRC_START_SRC_AUXIO2 0x00000002
+#define AUX_TDC_TRIGSRC_START_SRC_AUXIO1 0x00000001
+#define AUX_TDC_TRIGSRC_START_SRC_AUXIO0 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_TDC_O_TRIGCNT
+//
+//*****************************************************************************
+// Field: [15:0] CNT
+//
+// Number of stop events to ignore when AUX_TDC:TRIGCNTCFG.EN is 1.
+//
+// Read CNT to get the remaining number of stop events to ignore during a TDC
+// measurement.
+//
+// Write CNT to update the remaining number of stop events to ignore during a
+// TDC measurement. The TDC measurement ignores updates of CNT if there are no
+// more stop events left to ignore.
+//
+// When AUX_TDC:TRIGCNTCFG.EN is 1, TRIGCNTLOAD.CNT is loaded into CNT at the
+// start of the measurement.
+#define AUX_TDC_TRIGCNT_CNT_W 16
+#define AUX_TDC_TRIGCNT_CNT_M 0x0000FFFF
+#define AUX_TDC_TRIGCNT_CNT_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_TDC_O_TRIGCNTLOAD
+//
+//*****************************************************************************
+// Field: [15:0] CNT
+//
+// Number of stop events to ignore when AUX_TDC:TRIGCNTCFG.EN is 1.
+//
+// To measure frequency of an event source:
+// - Set start event equal to stop event.
+// - Set CNT to number of periods to measure. Both 0 and 1 values measures a
+// single event source period.
+//
+// To measure pulse width of an event source:
+// - Set start event source equal to stop event source.
+// - Select different polarity for start and stop event.
+// - Set CNT to 0.
+//
+// To measure time from the start event to the Nth stop event when N > 1:
+// - Select different start and stop event source.
+// - Set CNT to (N-1).
+//
+// See the Technical Reference Manual for event timing requirements.
+//
+// When AUX_TDC:TRIGCNTCFG.EN is 1, CNT is loaded into TRIGCNT.CNT at the start
+// of the measurement.
+#define AUX_TDC_TRIGCNTLOAD_CNT_W 16
+#define AUX_TDC_TRIGCNTLOAD_CNT_M 0x0000FFFF
+#define AUX_TDC_TRIGCNTLOAD_CNT_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_TDC_O_TRIGCNTCFG
+//
+//*****************************************************************************
+// Field: [0] EN
+//
+// Enable stop-counter.
+//
+// 0: Disable stop-counter.
+// 1: Enable stop-counter.
+//
+// Change only while STAT.STATE is IDLE.
+#define AUX_TDC_TRIGCNTCFG_EN 0x00000001
+#define AUX_TDC_TRIGCNTCFG_EN_BITN 0
+#define AUX_TDC_TRIGCNTCFG_EN_M 0x00000001
+#define AUX_TDC_TRIGCNTCFG_EN_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_TDC_O_PRECTL
+//
+//*****************************************************************************
+// Field: [7] RESET_N
+//
+// Prescaler reset.
+//
+// 0: Reset prescaler.
+// 1: Release reset of prescaler.
+//
+// AUX_TDC_PRE event becomes 0 when you reset the prescaler.
+#define AUX_TDC_PRECTL_RESET_N 0x00000080
+#define AUX_TDC_PRECTL_RESET_N_BITN 7
+#define AUX_TDC_PRECTL_RESET_N_M 0x00000080
+#define AUX_TDC_PRECTL_RESET_N_S 7
+
+// Field: [6] RATIO
+//
+// Prescaler ratio.
+//
+// This controls how often the AUX_TDC_PRE event is generated by the prescaler.
+// ENUMs:
+// DIV64 Prescaler divides input by 64.
+//
+// AUX_TDC_PRE event has a
+// rising edge for every 64 rising edges of the
+// input. AUX_TDC_PRE event toggles on every 32nd
+// rising edge of the input.
+// DIV16 Prescaler divides input by 16.
+//
+// AUX_TDC_PRE event has a
+// rising edge for every 16 rising edges of the
+// input. AUX_TDC_PRE event toggles on every 8th
+// rising edge of the input.
+#define AUX_TDC_PRECTL_RATIO 0x00000040
+#define AUX_TDC_PRECTL_RATIO_BITN 6
+#define AUX_TDC_PRECTL_RATIO_M 0x00000040
+#define AUX_TDC_PRECTL_RATIO_S 6
+#define AUX_TDC_PRECTL_RATIO_DIV64 0x00000040
+#define AUX_TDC_PRECTL_RATIO_DIV16 0x00000000
+
+// Field: [5:0] SRC
+//
+// Prescaler event source.
+//
+// Select an event from the asynchronous AUX event bus to connect to the
+// prescaler input.
+//
+// Configure only while RESET_N is 0.
+// ENUMs:
+// NO_EVENT No event.
+// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE
+// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY
+// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL
+// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ
+// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE
+// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N
+// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE
+// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV
+// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV
+// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE
+// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3
+// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2
+// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1
+// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0
+// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB
+// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA
+// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1
+// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0
+// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV
+// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF
+// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE
+// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE
+// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN
+// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF
+// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD
+// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD
+// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ
+// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY
+// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2
+// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV
+// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31
+// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30
+// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29
+// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28
+// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27
+// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26
+// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25
+// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24
+// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23
+// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22
+// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21
+// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20
+// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19
+// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18
+// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17
+// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16
+// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15
+// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14
+// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13
+// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12
+// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11
+// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10
+// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9
+// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8
+// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7
+// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6
+// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5
+// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4
+// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3
+// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2
+// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1
+// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0
+#define AUX_TDC_PRECTL_SRC_W 6
+#define AUX_TDC_PRECTL_SRC_M 0x0000003F
+#define AUX_TDC_PRECTL_SRC_S 0
+#define AUX_TDC_PRECTL_SRC_NO_EVENT 0x0000003F
+#define AUX_TDC_PRECTL_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000003D
+#define AUX_TDC_PRECTL_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C
+#define AUX_TDC_PRECTL_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B
+#define AUX_TDC_PRECTL_SRC_AUX_ADC_IRQ 0x0000003A
+#define AUX_TDC_PRECTL_SRC_AUX_ADC_DONE 0x00000039
+#define AUX_TDC_PRECTL_SRC_AUX_ISRC_RESET_N 0x00000038
+#define AUX_TDC_PRECTL_SRC_AUX_TDC_DONE 0x00000037
+#define AUX_TDC_PRECTL_SRC_AUX_TIMER0_EV 0x00000036
+#define AUX_TDC_PRECTL_SRC_AUX_TIMER1_EV 0x00000035
+#define AUX_TDC_PRECTL_SRC_AUX_TIMER2_PULSE 0x00000034
+#define AUX_TDC_PRECTL_SRC_AUX_TIMER2_EV3 0x00000033
+#define AUX_TDC_PRECTL_SRC_AUX_TIMER2_EV2 0x00000032
+#define AUX_TDC_PRECTL_SRC_AUX_TIMER2_EV1 0x00000031
+#define AUX_TDC_PRECTL_SRC_AUX_TIMER2_EV0 0x00000030
+#define AUX_TDC_PRECTL_SRC_AUX_COMPB 0x0000002F
+#define AUX_TDC_PRECTL_SRC_AUX_COMPA 0x0000002E
+#define AUX_TDC_PRECTL_SRC_MCU_OBSMUX1 0x0000002D
+#define AUX_TDC_PRECTL_SRC_MCU_OBSMUX0 0x0000002C
+#define AUX_TDC_PRECTL_SRC_MCU_EV 0x0000002B
+#define AUX_TDC_PRECTL_SRC_ACLK_REF 0x0000002A
+#define AUX_TDC_PRECTL_SRC_VDDR_RECHARGE 0x00000029
+#define AUX_TDC_PRECTL_SRC_MCU_ACTIVE 0x00000028
+#define AUX_TDC_PRECTL_SRC_PWR_DWN 0x00000027
+#define AUX_TDC_PRECTL_SRC_SCLK_LF 0x00000026
+#define AUX_TDC_PRECTL_SRC_AON_BATMON_TEMP_UPD 0x00000025
+#define AUX_TDC_PRECTL_SRC_AON_BATMON_BAT_UPD 0x00000024
+#define AUX_TDC_PRECTL_SRC_AON_RTC_4KHZ 0x00000023
+#define AUX_TDC_PRECTL_SRC_AON_RTC_CH2_DLY 0x00000022
+#define AUX_TDC_PRECTL_SRC_AON_RTC_CH2 0x00000021
+#define AUX_TDC_PRECTL_SRC_MANUAL_EV 0x00000020
+#define AUX_TDC_PRECTL_SRC_AUXIO31 0x0000001F
+#define AUX_TDC_PRECTL_SRC_AUXIO30 0x0000001E
+#define AUX_TDC_PRECTL_SRC_AUXIO29 0x0000001D
+#define AUX_TDC_PRECTL_SRC_AUXIO28 0x0000001C
+#define AUX_TDC_PRECTL_SRC_AUXIO27 0x0000001B
+#define AUX_TDC_PRECTL_SRC_AUXIO26 0x0000001A
+#define AUX_TDC_PRECTL_SRC_AUXIO25 0x00000019
+#define AUX_TDC_PRECTL_SRC_AUXIO24 0x00000018
+#define AUX_TDC_PRECTL_SRC_AUXIO23 0x00000017
+#define AUX_TDC_PRECTL_SRC_AUXIO22 0x00000016
+#define AUX_TDC_PRECTL_SRC_AUXIO21 0x00000015
+#define AUX_TDC_PRECTL_SRC_AUXIO20 0x00000014
+#define AUX_TDC_PRECTL_SRC_AUXIO19 0x00000013
+#define AUX_TDC_PRECTL_SRC_AUXIO18 0x00000012
+#define AUX_TDC_PRECTL_SRC_AUXIO17 0x00000011
+#define AUX_TDC_PRECTL_SRC_AUXIO16 0x00000010
+#define AUX_TDC_PRECTL_SRC_AUXIO15 0x0000000F
+#define AUX_TDC_PRECTL_SRC_AUXIO14 0x0000000E
+#define AUX_TDC_PRECTL_SRC_AUXIO13 0x0000000D
+#define AUX_TDC_PRECTL_SRC_AUXIO12 0x0000000C
+#define AUX_TDC_PRECTL_SRC_AUXIO11 0x0000000B
+#define AUX_TDC_PRECTL_SRC_AUXIO10 0x0000000A
+#define AUX_TDC_PRECTL_SRC_AUXIO9 0x00000009
+#define AUX_TDC_PRECTL_SRC_AUXIO8 0x00000008
+#define AUX_TDC_PRECTL_SRC_AUXIO7 0x00000007
+#define AUX_TDC_PRECTL_SRC_AUXIO6 0x00000006
+#define AUX_TDC_PRECTL_SRC_AUXIO5 0x00000005
+#define AUX_TDC_PRECTL_SRC_AUXIO4 0x00000004
+#define AUX_TDC_PRECTL_SRC_AUXIO3 0x00000003
+#define AUX_TDC_PRECTL_SRC_AUXIO2 0x00000002
+#define AUX_TDC_PRECTL_SRC_AUXIO1 0x00000001
+#define AUX_TDC_PRECTL_SRC_AUXIO0 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_TDC_O_PRECNTR
+//
+//*****************************************************************************
+// Field: [15:0] CNT
+//
+// Prescaler counter value.
+//
+// Write a value to CNT to capture the value of the 16-bit prescaler counter
+// into CNT. Read CNT to get the captured value.
+//
+// The read value gets 1 LSB uncertainty if the event source level rises when
+// you release the reset.
+// The read value gets 1 LSB uncertainty if the event source level rises when
+// you capture the prescaler counter.
+//
+// Please note the following:
+// - The prescaler counter is reset to 2 by PRECTL.RESET_N.
+// - The captured value is 2 when the number of rising edges on prescaler input
+// is less than 3. Otherwise, captured value equals number of event pulses - 1.
+#define AUX_TDC_PRECNTR_CNT_W 16
+#define AUX_TDC_PRECNTR_CNT_M 0x0000FFFF
+#define AUX_TDC_PRECNTR_CNT_S 0
+
+
+#endif // __AUX_TDC__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_timer01.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_timer01.h
new file mode 100644
index 0000000..288a8fd
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_timer01.h
@@ -0,0 +1,611 @@
+/******************************************************************************
+* Filename: hw_aux_timer01_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_AUX_TIMER01_H__
+#define __HW_AUX_TIMER01_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// AUX_TIMER01 component
+//
+//*****************************************************************************
+// Timer 0 Configuration
+#define AUX_TIMER01_O_T0CFG 0x00000000
+
+// Timer 0 Control
+#define AUX_TIMER01_O_T0CTL 0x00000004
+
+// Timer 0 Target
+#define AUX_TIMER01_O_T0TARGET 0x00000008
+
+// Timer 0 Counter
+#define AUX_TIMER01_O_T0CNTR 0x0000000C
+
+// Timer 1 Configuration
+#define AUX_TIMER01_O_T1CFG 0x00000010
+
+// Timer 1 Control
+#define AUX_TIMER01_O_T1CTL 0x00000014
+
+// Timer 1 Target
+#define AUX_TIMER01_O_T1TARGET 0x00000018
+
+// Timer 1 Counter
+#define AUX_TIMER01_O_T1CNTR 0x0000001C
+
+//*****************************************************************************
+//
+// Register: AUX_TIMER01_O_T0CFG
+//
+//*****************************************************************************
+// Field: [14] TICK_SRC_POL
+//
+// Tick source polarity for Timer 0.
+// ENUMs:
+// FALL Count on falling edges of TICK_SRC.
+// RISE Count on rising edges of TICK_SRC.
+#define AUX_TIMER01_T0CFG_TICK_SRC_POL 0x00004000
+#define AUX_TIMER01_T0CFG_TICK_SRC_POL_BITN 14
+#define AUX_TIMER01_T0CFG_TICK_SRC_POL_M 0x00004000
+#define AUX_TIMER01_T0CFG_TICK_SRC_POL_S 14
+#define AUX_TIMER01_T0CFG_TICK_SRC_POL_FALL 0x00004000
+#define AUX_TIMER01_T0CFG_TICK_SRC_POL_RISE 0x00000000
+
+// Field: [13:8] TICK_SRC
+//
+// Select Timer 0 tick source from the synchronous event bus.
+// ENUMs:
+// AUX_TIMER2_CLKSW_RDY AUX_EVCTL:EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY
+// AUX_DAC_HOLD_ACTIVE AUX_EVCTL:EVSTAT3.AUX_DAC_HOLD_ACTIVE
+// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE
+// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY
+// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL
+// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ
+// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE
+// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N
+// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE
+// NO_EVENT No event.
+// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV
+// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE
+// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3
+// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2
+// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1
+// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0
+// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB
+// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA
+// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1
+// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0
+// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV
+// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF
+// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE
+// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE
+// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN
+// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF
+// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD
+// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD
+// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ
+// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY
+// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2
+// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV
+// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31
+// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30
+// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29
+// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28
+// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27
+// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26
+// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25
+// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24
+// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23
+// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22
+// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21
+// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20
+// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19
+// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18
+// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17
+// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16
+// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15
+// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14
+// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13
+// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12
+// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11
+// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10
+// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9
+// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8
+// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7
+// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6
+// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5
+// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4
+// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3
+// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2
+// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1
+// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0
+#define AUX_TIMER01_T0CFG_TICK_SRC_W 6
+#define AUX_TIMER01_T0CFG_TICK_SRC_M 0x00003F00
+#define AUX_TIMER01_T0CFG_TICK_SRC_S 8
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_CLKSW_RDY 0x00003F00
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_DAC_HOLD_ACTIVE 0x00003E00
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_SMPH_AUTOTAKE_DONE 0x00003D00
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00003C00
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00003B00
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_ADC_IRQ 0x00003A00
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_ADC_DONE 0x00003900
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_ISRC_RESET_N 0x00003800
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TDC_DONE 0x00003700
+#define AUX_TIMER01_T0CFG_TICK_SRC_NO_EVENT 0x00003600
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER1_EV 0x00003500
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_PULSE 0x00003400
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_EV3 0x00003300
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_EV2 0x00003200
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_EV1 0x00003100
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_EV0 0x00003000
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_COMPB 0x00002F00
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_COMPA 0x00002E00
+#define AUX_TIMER01_T0CFG_TICK_SRC_MCU_OBSMUX1 0x00002D00
+#define AUX_TIMER01_T0CFG_TICK_SRC_MCU_OBSMUX0 0x00002C00
+#define AUX_TIMER01_T0CFG_TICK_SRC_MCU_EV 0x00002B00
+#define AUX_TIMER01_T0CFG_TICK_SRC_ACLK_REF 0x00002A00
+#define AUX_TIMER01_T0CFG_TICK_SRC_VDDR_RECHARGE 0x00002900
+#define AUX_TIMER01_T0CFG_TICK_SRC_MCU_ACTIVE 0x00002800
+#define AUX_TIMER01_T0CFG_TICK_SRC_PWR_DWN 0x00002700
+#define AUX_TIMER01_T0CFG_TICK_SRC_SCLK_LF 0x00002600
+#define AUX_TIMER01_T0CFG_TICK_SRC_AON_BATMON_TEMP_UPD 0x00002500
+#define AUX_TIMER01_T0CFG_TICK_SRC_AON_BATMON_BAT_UPD 0x00002400
+#define AUX_TIMER01_T0CFG_TICK_SRC_AON_RTC_4KHZ 0x00002300
+#define AUX_TIMER01_T0CFG_TICK_SRC_AON_RTC_CH2_DLY 0x00002200
+#define AUX_TIMER01_T0CFG_TICK_SRC_AON_RTC_CH2 0x00002100
+#define AUX_TIMER01_T0CFG_TICK_SRC_MANUAL_EV 0x00002000
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO31 0x00001F00
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO30 0x00001E00
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO29 0x00001D00
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO28 0x00001C00
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO27 0x00001B00
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO26 0x00001A00
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO25 0x00001900
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO24 0x00001800
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO23 0x00001700
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO22 0x00001600
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO21 0x00001500
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO20 0x00001400
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO19 0x00001300
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO18 0x00001200
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO17 0x00001100
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO16 0x00001000
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO15 0x00000F00
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO14 0x00000E00
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO13 0x00000D00
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO12 0x00000C00
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO11 0x00000B00
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO10 0x00000A00
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO9 0x00000900
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO8 0x00000800
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO7 0x00000700
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO6 0x00000600
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO5 0x00000500
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO4 0x00000400
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO3 0x00000300
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO2 0x00000200
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO1 0x00000100
+#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO0 0x00000000
+
+// Field: [7:4] PRE
+//
+// Prescaler division ratio is 2^PRE:
+//
+// 0x0: Divide by 1.
+// 0x1: Divide by 2.
+// 0x2: Divide by 4.
+// ...
+// 0xF: Divide by 32,768.
+#define AUX_TIMER01_T0CFG_PRE_W 4
+#define AUX_TIMER01_T0CFG_PRE_M 0x000000F0
+#define AUX_TIMER01_T0CFG_PRE_S 4
+
+// Field: [1] MODE
+//
+// Timer 0 mode.
+//
+// Configure source for Timer 0 prescaler.
+// ENUMs:
+// TICK Use event set by TICK_SRC as source for prescaler.
+// CLK Use clock as source for prescaler. Note that
+// AUX_SYSIF:PEROPRATE.TIMER01_OP_RATE sets the
+// clock frequency.
+#define AUX_TIMER01_T0CFG_MODE 0x00000002
+#define AUX_TIMER01_T0CFG_MODE_BITN 1
+#define AUX_TIMER01_T0CFG_MODE_M 0x00000002
+#define AUX_TIMER01_T0CFG_MODE_S 1
+#define AUX_TIMER01_T0CFG_MODE_TICK 0x00000002
+#define AUX_TIMER01_T0CFG_MODE_CLK 0x00000000
+
+// Field: [0] RELOAD
+//
+// Timer 0 reload mode.
+// ENUMs:
+// CONT Continuous mode.
+//
+// Timer 0 restarts when the
+// counter value becomes equal to or greater than
+// ( T0TARGET.VALUE - 1).
+// MAN Manual mode.
+//
+// Timer 0 stops and
+// T0CTL.EN becomes 0 when the counter value
+// becomes equal to or greater than
+// T0TARGET.VALUE.
+#define AUX_TIMER01_T0CFG_RELOAD 0x00000001
+#define AUX_TIMER01_T0CFG_RELOAD_BITN 0
+#define AUX_TIMER01_T0CFG_RELOAD_M 0x00000001
+#define AUX_TIMER01_T0CFG_RELOAD_S 0
+#define AUX_TIMER01_T0CFG_RELOAD_CONT 0x00000001
+#define AUX_TIMER01_T0CFG_RELOAD_MAN 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_TIMER01_O_T0CTL
+//
+//*****************************************************************************
+// Field: [0] EN
+//
+// Timer 0 enable.
+//
+// 0: Disable Timer 0.
+// 1: Enable Timer 0.
+//
+// The counter restarts from 0 when you enable Timer 0.
+#define AUX_TIMER01_T0CTL_EN 0x00000001
+#define AUX_TIMER01_T0CTL_EN_BITN 0
+#define AUX_TIMER01_T0CTL_EN_M 0x00000001
+#define AUX_TIMER01_T0CTL_EN_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_TIMER01_O_T0TARGET
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Timer 0 target value.
+//
+// Manual Reload Mode:
+// - Timer 0 increments until the counter value becomes equal to or greater
+// than VALUE.
+// - AUX_TIMER0_EV pulses high for 1 peripheral clock period when the counter
+// value is equal to or greater than VALUE.
+//
+// Note: When VALUE is 0, Timer 0 counts to 1. AUX_TIMER0_EV pulses high for 1
+// peripheral clock period.
+//
+// Continuous Reload Mode:
+// - Timer 0 increments until the counter value becomes equal to or greater
+// than ( VALUE - 1), then restarts from 0.
+// - AUX_TIMER0_EV pulses high for 1 peripheral clock period when the counter
+// value is 0, except for when you enable the timer.
+//
+// Note: When VALUE is less than 2, Timer 0 counter value remains 0.
+// AUX_TIMER0_EV goes high and remains high 1 peripheral clock period after you
+// enable the timer.
+//
+//
+// It is allowed to update the VALUE while the timer runs.
+#define AUX_TIMER01_T0TARGET_VALUE_W 16
+#define AUX_TIMER01_T0TARGET_VALUE_M 0x0000FFFF
+#define AUX_TIMER01_T0TARGET_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_TIMER01_O_T0CNTR
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Timer 0 counter value.
+#define AUX_TIMER01_T0CNTR_VALUE_W 16
+#define AUX_TIMER01_T0CNTR_VALUE_M 0x0000FFFF
+#define AUX_TIMER01_T0CNTR_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_TIMER01_O_T1CFG
+//
+//*****************************************************************************
+// Field: [14] TICK_SRC_POL
+//
+// Tick source polarity for Timer 1.
+// ENUMs:
+// FALL Count on falling edges of TICK_SRC.
+// RISE Count on rising edges of TICK_SRC.
+#define AUX_TIMER01_T1CFG_TICK_SRC_POL 0x00004000
+#define AUX_TIMER01_T1CFG_TICK_SRC_POL_BITN 14
+#define AUX_TIMER01_T1CFG_TICK_SRC_POL_M 0x00004000
+#define AUX_TIMER01_T1CFG_TICK_SRC_POL_S 14
+#define AUX_TIMER01_T1CFG_TICK_SRC_POL_FALL 0x00004000
+#define AUX_TIMER01_T1CFG_TICK_SRC_POL_RISE 0x00000000
+
+// Field: [13:8] TICK_SRC
+//
+// Select Timer 1 tick source from the synchronous event bus.
+// ENUMs:
+// AUX_TIMER2_CLKSW_RDY AUX_EVCTL:EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY
+// AUX_DAC_HOLD_ACTIVE AUX_EVCTL:EVSTAT3.AUX_DAC_HOLD_ACTIVE
+// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE
+// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY
+// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL
+// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ
+// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE
+// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N
+// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE
+// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV
+// NO_EVENT No event.
+// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE
+// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3
+// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2
+// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1
+// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0
+// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB
+// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA
+// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1
+// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0
+// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV
+// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF
+// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE
+// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE
+// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN
+// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF
+// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD
+// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD
+// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ
+// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY
+// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2
+// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV
+// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31
+// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30
+// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29
+// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28
+// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27
+// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26
+// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25
+// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24
+// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23
+// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22
+// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21
+// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20
+// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19
+// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18
+// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17
+// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16
+// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15
+// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14
+// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13
+// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12
+// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11
+// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10
+// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9
+// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8
+// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7
+// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6
+// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5
+// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4
+// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3
+// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2
+// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1
+// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0
+#define AUX_TIMER01_T1CFG_TICK_SRC_W 6
+#define AUX_TIMER01_T1CFG_TICK_SRC_M 0x00003F00
+#define AUX_TIMER01_T1CFG_TICK_SRC_S 8
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_CLKSW_RDY 0x00003F00
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_DAC_HOLD_ACTIVE 0x00003E00
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_SMPH_AUTOTAKE_DONE 0x00003D00
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00003C00
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00003B00
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_ADC_IRQ 0x00003A00
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_ADC_DONE 0x00003900
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_ISRC_RESET_N 0x00003800
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TDC_DONE 0x00003700
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER0_EV 0x00003600
+#define AUX_TIMER01_T1CFG_TICK_SRC_NO_EVENT 0x00003500
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_PULSE 0x00003400
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_EV3 0x00003300
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_EV2 0x00003200
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_EV1 0x00003100
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_EV0 0x00003000
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_COMPB 0x00002F00
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_COMPA 0x00002E00
+#define AUX_TIMER01_T1CFG_TICK_SRC_MCU_OBSMUX1 0x00002D00
+#define AUX_TIMER01_T1CFG_TICK_SRC_MCU_OBSMUX0 0x00002C00
+#define AUX_TIMER01_T1CFG_TICK_SRC_MCU_EV 0x00002B00
+#define AUX_TIMER01_T1CFG_TICK_SRC_ACLK_REF 0x00002A00
+#define AUX_TIMER01_T1CFG_TICK_SRC_VDDR_RECHARGE 0x00002900
+#define AUX_TIMER01_T1CFG_TICK_SRC_MCU_ACTIVE 0x00002800
+#define AUX_TIMER01_T1CFG_TICK_SRC_PWR_DWN 0x00002700
+#define AUX_TIMER01_T1CFG_TICK_SRC_SCLK_LF 0x00002600
+#define AUX_TIMER01_T1CFG_TICK_SRC_AON_BATMON_TEMP_UPD 0x00002500
+#define AUX_TIMER01_T1CFG_TICK_SRC_AON_BATMON_BAT_UPD 0x00002400
+#define AUX_TIMER01_T1CFG_TICK_SRC_AON_RTC_4KHZ 0x00002300
+#define AUX_TIMER01_T1CFG_TICK_SRC_AON_RTC_CH2_DLY 0x00002200
+#define AUX_TIMER01_T1CFG_TICK_SRC_AON_RTC_CH2 0x00002100
+#define AUX_TIMER01_T1CFG_TICK_SRC_MANUAL_EV 0x00002000
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO31 0x00001F00
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO30 0x00001E00
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO29 0x00001D00
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO28 0x00001C00
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO27 0x00001B00
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO26 0x00001A00
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO25 0x00001900
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO24 0x00001800
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO23 0x00001700
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO22 0x00001600
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO21 0x00001500
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO20 0x00001400
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO19 0x00001300
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO18 0x00001200
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO17 0x00001100
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO16 0x00001000
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO15 0x00000F00
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO14 0x00000E00
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO13 0x00000D00
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO12 0x00000C00
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO11 0x00000B00
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO10 0x00000A00
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO9 0x00000900
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO8 0x00000800
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO7 0x00000700
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO6 0x00000600
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO5 0x00000500
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO4 0x00000400
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO3 0x00000300
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO2 0x00000200
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO1 0x00000100
+#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO0 0x00000000
+
+// Field: [7:4] PRE
+//
+// Prescaler division ratio is 2^PRE:
+//
+// 0x0: Divide by 1.
+// 0x1: Divide by 2.
+// 0x2: Divide by 4.
+// ...
+// 0xF: Divide by 32,768.
+#define AUX_TIMER01_T1CFG_PRE_W 4
+#define AUX_TIMER01_T1CFG_PRE_M 0x000000F0
+#define AUX_TIMER01_T1CFG_PRE_S 4
+
+// Field: [1] MODE
+//
+// Timer 1 mode.
+//
+// Configure source for Timer 1 prescaler.
+// ENUMs:
+// TICK Use event set by TICK_SRC as source for prescaler.
+// CLK Use clock as source for prescaler. Note that
+// AUX_SYSIF:PEROPRATE.TIMER01_OP_RATE sets the
+// clock frequency.
+#define AUX_TIMER01_T1CFG_MODE 0x00000002
+#define AUX_TIMER01_T1CFG_MODE_BITN 1
+#define AUX_TIMER01_T1CFG_MODE_M 0x00000002
+#define AUX_TIMER01_T1CFG_MODE_S 1
+#define AUX_TIMER01_T1CFG_MODE_TICK 0x00000002
+#define AUX_TIMER01_T1CFG_MODE_CLK 0x00000000
+
+// Field: [0] RELOAD
+//
+// Timer 1 reload mode.
+// ENUMs:
+// CONT Continuous mode.
+//
+// Timer 1 restarts when the
+// counter value becomes equal to or greater than
+// ( T1TARGET.VALUE - 1).
+// MAN Manual mode.
+//
+// Timer 1 stops and
+// T1CTL.EN becomes 0 when the counter value
+// becomes equal to or greater than
+// T1TARGET.VALUE.
+#define AUX_TIMER01_T1CFG_RELOAD 0x00000001
+#define AUX_TIMER01_T1CFG_RELOAD_BITN 0
+#define AUX_TIMER01_T1CFG_RELOAD_M 0x00000001
+#define AUX_TIMER01_T1CFG_RELOAD_S 0
+#define AUX_TIMER01_T1CFG_RELOAD_CONT 0x00000001
+#define AUX_TIMER01_T1CFG_RELOAD_MAN 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_TIMER01_O_T1CTL
+//
+//*****************************************************************************
+// Field: [0] EN
+//
+// Timer 1 enable.
+//
+// 0: Disable Timer 1.
+// 1: Enable Timer 1.
+//
+// The counter restarts from 0 when you enable Timer 1.
+#define AUX_TIMER01_T1CTL_EN 0x00000001
+#define AUX_TIMER01_T1CTL_EN_BITN 0
+#define AUX_TIMER01_T1CTL_EN_M 0x00000001
+#define AUX_TIMER01_T1CTL_EN_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_TIMER01_O_T1TARGET
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Timer 1 target value.
+//
+// Manual Reload Mode:
+// - Timer 1 increments until the counter value becomes equal to or greater
+// than VALUE.
+// - AUX_TIMER1_EV pulses high for 1 peripheral clock period when the counter
+// value is equal to or greater than VALUE.
+//
+// Note: When VALUE is 0, Timer 1 counts to 1. AUX_TIMER1_EV pulses high for 1
+// peripheral clock period.
+//
+// Continuous Reload Mode:
+// - Timer 1 increments until the counter value becomes equal to or greater
+// than ( VALUE - 1), then restarts from 0.
+// - AUX_TIMER1_EV pulses high for 1 peripheral clock period when the counter
+// value is 0, except for when you enable the timer.
+//
+// Note: When VALUE is less than 2, Timer 1 counter value remains 0.
+// AUX_TIMER1_EV goes high and remains high 1 peripheral clock period after you
+// enable the timer.
+//
+//
+// It is allowed to update the VALUE while the timer runs.
+#define AUX_TIMER01_T1TARGET_VALUE_W 16
+#define AUX_TIMER01_T1TARGET_VALUE_M 0x0000FFFF
+#define AUX_TIMER01_T1TARGET_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_TIMER01_O_T1CNTR
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Timer 1 counter value.
+#define AUX_TIMER01_T1CNTR_VALUE_W 16
+#define AUX_TIMER01_T1CNTR_VALUE_M 0x0000FFFF
+#define AUX_TIMER01_T1CNTR_VALUE_S 0
+
+
+#endif // __AUX_TIMER01__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_timer2.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_timer2.h
new file mode 100644
index 0000000..aa7423f
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_timer2.h
@@ -0,0 +1,2491 @@
+/******************************************************************************
+* Filename: hw_aux_timer2_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_AUX_TIMER2_H__
+#define __HW_AUX_TIMER2_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// AUX_TIMER2 component
+//
+//*****************************************************************************
+// Timer Control
+#define AUX_TIMER2_O_CTL 0x00000000
+
+// Target
+#define AUX_TIMER2_O_TARGET 0x00000004
+
+// Shadow Target
+#define AUX_TIMER2_O_SHDWTARGET 0x00000008
+
+// Counter
+#define AUX_TIMER2_O_CNTR 0x0000000C
+
+// Clock Prescaler Configuration
+#define AUX_TIMER2_O_PRECFG 0x00000010
+
+// Event Control
+#define AUX_TIMER2_O_EVCTL 0x00000014
+
+// Pulse Trigger
+#define AUX_TIMER2_O_PULSETRIG 0x00000018
+
+// Channel 0 Event Configuration
+#define AUX_TIMER2_O_CH0EVCFG 0x00000080
+
+// Channel 0 Capture Configuration
+#define AUX_TIMER2_O_CH0CCFG 0x00000084
+
+// Channel 0 Pipeline Capture Compare
+#define AUX_TIMER2_O_CH0PCC 0x00000088
+
+// Channel 0 Capture Compare
+#define AUX_TIMER2_O_CH0CC 0x0000008C
+
+// Channel 1 Event Configuration
+#define AUX_TIMER2_O_CH1EVCFG 0x00000090
+
+// Channel 1 Capture Configuration
+#define AUX_TIMER2_O_CH1CCFG 0x00000094
+
+// Channel 1 Pipeline Capture Compare
+#define AUX_TIMER2_O_CH1PCC 0x00000098
+
+// Channel 1 Capture Compare
+#define AUX_TIMER2_O_CH1CC 0x0000009C
+
+// Channel 2 Event Configuration
+#define AUX_TIMER2_O_CH2EVCFG 0x000000A0
+
+// Channel 2 Capture Configuration
+#define AUX_TIMER2_O_CH2CCFG 0x000000A4
+
+// Channel 2 Pipeline Capture Compare
+#define AUX_TIMER2_O_CH2PCC 0x000000A8
+
+// Channel 2 Capture Compare
+#define AUX_TIMER2_O_CH2CC 0x000000AC
+
+// Channel 3 Event Configuration
+#define AUX_TIMER2_O_CH3EVCFG 0x000000B0
+
+// Channel 3 Capture Configuration
+#define AUX_TIMER2_O_CH3CCFG 0x000000B4
+
+// Channel 3 Pipeline Capture Compare
+#define AUX_TIMER2_O_CH3PCC 0x000000B8
+
+// Channel 3 Capture Compare
+#define AUX_TIMER2_O_CH3CC 0x000000BC
+
+//*****************************************************************************
+//
+// Register: AUX_TIMER2_O_CTL
+//
+//*****************************************************************************
+// Field: [6] CH3_RESET
+//
+// Channel 3 reset.
+//
+// 0: No effect.
+// 1: Reset CH3CC, CH3PCC, CH3EVCFG, and CH3CCFG.
+//
+// Read returns 0.
+#define AUX_TIMER2_CTL_CH3_RESET 0x00000040
+#define AUX_TIMER2_CTL_CH3_RESET_BITN 6
+#define AUX_TIMER2_CTL_CH3_RESET_M 0x00000040
+#define AUX_TIMER2_CTL_CH3_RESET_S 6
+
+// Field: [5] CH2_RESET
+//
+// Channel 2 reset.
+//
+// 0: No effect.
+// 1: Reset CH2CC, CH2PCC, CH2EVCFG, and CH2CCFG.
+//
+// Read returns 0.
+#define AUX_TIMER2_CTL_CH2_RESET 0x00000020
+#define AUX_TIMER2_CTL_CH2_RESET_BITN 5
+#define AUX_TIMER2_CTL_CH2_RESET_M 0x00000020
+#define AUX_TIMER2_CTL_CH2_RESET_S 5
+
+// Field: [4] CH1_RESET
+//
+// Channel 1 reset.
+//
+// 0: No effect.
+// 1: Reset CH1CC, CH1PCC, CH1EVCFG, and CH1CCFG.
+//
+// Read returns 0.
+#define AUX_TIMER2_CTL_CH1_RESET 0x00000010
+#define AUX_TIMER2_CTL_CH1_RESET_BITN 4
+#define AUX_TIMER2_CTL_CH1_RESET_M 0x00000010
+#define AUX_TIMER2_CTL_CH1_RESET_S 4
+
+// Field: [3] CH0_RESET
+//
+// Channel 0 reset.
+//
+// 0: No effect.
+// 1: Reset CH0CC, CH0PCC, CH0EVCFG, and CH0CCFG.
+//
+// Read returns 0.
+#define AUX_TIMER2_CTL_CH0_RESET 0x00000008
+#define AUX_TIMER2_CTL_CH0_RESET_BITN 3
+#define AUX_TIMER2_CTL_CH0_RESET_M 0x00000008
+#define AUX_TIMER2_CTL_CH0_RESET_S 3
+
+// Field: [2] TARGET_EN
+//
+// Select counter target value.
+//
+// You must select TARGET to use shadow target functionality.
+// ENUMs:
+// TARGET TARGET.VALUE
+// CNTR_MAX 65535
+#define AUX_TIMER2_CTL_TARGET_EN 0x00000004
+#define AUX_TIMER2_CTL_TARGET_EN_BITN 2
+#define AUX_TIMER2_CTL_TARGET_EN_M 0x00000004
+#define AUX_TIMER2_CTL_TARGET_EN_S 2
+#define AUX_TIMER2_CTL_TARGET_EN_TARGET 0x00000004
+#define AUX_TIMER2_CTL_TARGET_EN_CNTR_MAX 0x00000000
+
+// Field: [1:0] MODE
+//
+// Timer mode control.
+//
+// The timer restarts from 0 when you set MODE to UP_ONCE, UP_PER, or
+// UPDWN_PER.
+//
+// When you write MODE all internally queued updates to [CHnCC.*] and TARGET
+// clear.
+// ENUMs:
+// UPDWN_PER Count up and down periodically. The timer counts
+// from 0 to target value and back to 0,
+// repeatedly.
+//
+// Period = (target value *
+// 2) * timer clock period
+// UP_PER Count up periodically. The timer increments from 0
+// to target value, repeatedly.
+//
+// Period = (target value +
+// 1) * timer clock period
+// UP_ONCE Count up once. The timer increments from 0 to
+// target value, then stops and sets MODE to DIS.
+// DIS Disable timer. Updates to counter, channels, and
+// events stop.
+#define AUX_TIMER2_CTL_MODE_W 2
+#define AUX_TIMER2_CTL_MODE_M 0x00000003
+#define AUX_TIMER2_CTL_MODE_S 0
+#define AUX_TIMER2_CTL_MODE_UPDWN_PER 0x00000003
+#define AUX_TIMER2_CTL_MODE_UP_PER 0x00000002
+#define AUX_TIMER2_CTL_MODE_UP_ONCE 0x00000001
+#define AUX_TIMER2_CTL_MODE_DIS 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_TIMER2_O_TARGET
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// 16 bit user defined counter target value, which is used when selected by
+// CTL.TARGET_EN.
+#define AUX_TIMER2_TARGET_VALUE_W 16
+#define AUX_TIMER2_TARGET_VALUE_M 0x0000FFFF
+#define AUX_TIMER2_TARGET_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_TIMER2_O_SHDWTARGET
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Target value for next counter period.
+//
+// The timer copies VALUE to TARGET.VALUE when CNTR.VALUE becomes 0. The copy
+// does not happen when you restart the timer.
+//
+// This is useful to avoid period jitter in PWM applications with time-varying
+// period, sometimes referenced as phase corrected PWM.
+#define AUX_TIMER2_SHDWTARGET_VALUE_W 16
+#define AUX_TIMER2_SHDWTARGET_VALUE_M 0x0000FFFF
+#define AUX_TIMER2_SHDWTARGET_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_TIMER2_O_CNTR
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// 16 bit current counter value.
+#define AUX_TIMER2_CNTR_VALUE_W 16
+#define AUX_TIMER2_CNTR_VALUE_M 0x0000FFFF
+#define AUX_TIMER2_CNTR_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_TIMER2_O_PRECFG
+//
+//*****************************************************************************
+// Field: [7:0] CLKDIV
+//
+// Clock division.
+//
+// CLKDIV determines the timer clock frequency for counter, synchronization,
+// and timer event updates. The timer clock frequency is the clock selected by
+// AUX_SYSIF:TIMER2CLKCTL.SRC divided by (CLKDIV + 1). This inverse is the
+// timer clock period.
+//
+// 0x00: Divide by 1.
+// 0x01: Divide by 2.
+// ...
+// 0xFF: Divide by 256.
+#define AUX_TIMER2_PRECFG_CLKDIV_W 8
+#define AUX_TIMER2_PRECFG_CLKDIV_M 0x000000FF
+#define AUX_TIMER2_PRECFG_CLKDIV_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_TIMER2_O_EVCTL
+//
+//*****************************************************************************
+// Field: [7] EV3_SET
+//
+// Set event 3.
+//
+// Write 1 to set event 3.
+#define AUX_TIMER2_EVCTL_EV3_SET 0x00000080
+#define AUX_TIMER2_EVCTL_EV3_SET_BITN 7
+#define AUX_TIMER2_EVCTL_EV3_SET_M 0x00000080
+#define AUX_TIMER2_EVCTL_EV3_SET_S 7
+
+// Field: [6] EV3_CLR
+//
+// Clear event 3.
+//
+// Write 1 to clear event 3.
+#define AUX_TIMER2_EVCTL_EV3_CLR 0x00000040
+#define AUX_TIMER2_EVCTL_EV3_CLR_BITN 6
+#define AUX_TIMER2_EVCTL_EV3_CLR_M 0x00000040
+#define AUX_TIMER2_EVCTL_EV3_CLR_S 6
+
+// Field: [5] EV2_SET
+//
+// Set event 2.
+//
+// Write 1 to set event 2.
+#define AUX_TIMER2_EVCTL_EV2_SET 0x00000020
+#define AUX_TIMER2_EVCTL_EV2_SET_BITN 5
+#define AUX_TIMER2_EVCTL_EV2_SET_M 0x00000020
+#define AUX_TIMER2_EVCTL_EV2_SET_S 5
+
+// Field: [4] EV2_CLR
+//
+// Clear event 2.
+//
+// Write 1 to clear event 2.
+#define AUX_TIMER2_EVCTL_EV2_CLR 0x00000010
+#define AUX_TIMER2_EVCTL_EV2_CLR_BITN 4
+#define AUX_TIMER2_EVCTL_EV2_CLR_M 0x00000010
+#define AUX_TIMER2_EVCTL_EV2_CLR_S 4
+
+// Field: [3] EV1_SET
+//
+// Set event 1.
+//
+// Write 1 to set event 1.
+#define AUX_TIMER2_EVCTL_EV1_SET 0x00000008
+#define AUX_TIMER2_EVCTL_EV1_SET_BITN 3
+#define AUX_TIMER2_EVCTL_EV1_SET_M 0x00000008
+#define AUX_TIMER2_EVCTL_EV1_SET_S 3
+
+// Field: [2] EV1_CLR
+//
+// Clear event 1.
+//
+// Write 1 to clear event 1.
+#define AUX_TIMER2_EVCTL_EV1_CLR 0x00000004
+#define AUX_TIMER2_EVCTL_EV1_CLR_BITN 2
+#define AUX_TIMER2_EVCTL_EV1_CLR_M 0x00000004
+#define AUX_TIMER2_EVCTL_EV1_CLR_S 2
+
+// Field: [1] EV0_SET
+//
+// Set event 0.
+//
+// Write 1 to set event 0.
+#define AUX_TIMER2_EVCTL_EV0_SET 0x00000002
+#define AUX_TIMER2_EVCTL_EV0_SET_BITN 1
+#define AUX_TIMER2_EVCTL_EV0_SET_M 0x00000002
+#define AUX_TIMER2_EVCTL_EV0_SET_S 1
+
+// Field: [0] EV0_CLR
+//
+// Clear event 0.
+//
+// Write 1 to clear event 0.
+#define AUX_TIMER2_EVCTL_EV0_CLR 0x00000001
+#define AUX_TIMER2_EVCTL_EV0_CLR_BITN 0
+#define AUX_TIMER2_EVCTL_EV0_CLR_M 0x00000001
+#define AUX_TIMER2_EVCTL_EV0_CLR_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_TIMER2_O_PULSETRIG
+//
+//*****************************************************************************
+// Field: [0] TRIG
+//
+// Pulse trigger.
+//
+// Write 1 to generate a pulse to AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. Pulse
+// width equals the duty cycle of AUX_SYSIF:TIMER2CLKCTL.SRC.
+#define AUX_TIMER2_PULSETRIG_TRIG 0x00000001
+#define AUX_TIMER2_PULSETRIG_TRIG_BITN 0
+#define AUX_TIMER2_PULSETRIG_TRIG_M 0x00000001
+#define AUX_TIMER2_PULSETRIG_TRIG_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_TIMER2_O_CH0EVCFG
+//
+//*****************************************************************************
+// Field: [7] EV3_GEN
+//
+// Event 3 enable.
+//
+// 0: Channel 0 does not control event 3.
+// 1: Channel 0 controls event 3.
+//
+// When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event.
+#define AUX_TIMER2_CH0EVCFG_EV3_GEN 0x00000080
+#define AUX_TIMER2_CH0EVCFG_EV3_GEN_BITN 7
+#define AUX_TIMER2_CH0EVCFG_EV3_GEN_M 0x00000080
+#define AUX_TIMER2_CH0EVCFG_EV3_GEN_S 7
+
+// Field: [6] EV2_GEN
+//
+// Event 2 enable.
+//
+// 0: Channel 0 does not control event 2.
+// 1: Channel 0 controls event 2.
+//
+// When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event.
+#define AUX_TIMER2_CH0EVCFG_EV2_GEN 0x00000040
+#define AUX_TIMER2_CH0EVCFG_EV2_GEN_BITN 6
+#define AUX_TIMER2_CH0EVCFG_EV2_GEN_M 0x00000040
+#define AUX_TIMER2_CH0EVCFG_EV2_GEN_S 6
+
+// Field: [5] EV1_GEN
+//
+// Event 1 enable.
+//
+// 0: Channel 0 does not control event 1.
+// 1: Channel 0 controls event 1.
+//
+// When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event.
+#define AUX_TIMER2_CH0EVCFG_EV1_GEN 0x00000020
+#define AUX_TIMER2_CH0EVCFG_EV1_GEN_BITN 5
+#define AUX_TIMER2_CH0EVCFG_EV1_GEN_M 0x00000020
+#define AUX_TIMER2_CH0EVCFG_EV1_GEN_S 5
+
+// Field: [4] EV0_GEN
+//
+// Event 0 enable.
+//
+// 0: Channel 0 does not control event 0.
+// 1: Channel 0 controls event 0.
+//
+// When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event.
+#define AUX_TIMER2_CH0EVCFG_EV0_GEN 0x00000010
+#define AUX_TIMER2_CH0EVCFG_EV0_GEN_BITN 4
+#define AUX_TIMER2_CH0EVCFG_EV0_GEN_M 0x00000010
+#define AUX_TIMER2_CH0EVCFG_EV0_GEN_S 4
+
+// Field: [3:0] CCACT
+//
+// Capture-Compare action.
+//
+// Capture-Compare action defines 15 different channel functions that utilize
+// capture, compare, and zero events.
+// ENUMs:
+// PULSE_ON_CMP Pulse on compare repeatedly.
+//
+// Channel function
+// sequence:
+// - Pulse enabled events
+// when CH0CC.VALUE = CNTR.VALUE.
+//
+// The event is high for
+// two timer clock periods.
+// TGL_ON_CMP Toggle on compare repeatedly.
+//
+// Channel function
+// sequence:
+// - Toggle enabled events
+// when CH0CC.VALUE = CNTR.VALUE.
+// SET_ON_CMP Set on compare repeatedly.
+//
+// Channel function
+// sequence:
+// - Set enabled events
+// when CH0CC.VALUE = CNTR.VALUE.
+// CLR_ON_CMP Clear on compare repeatedly.
+//
+// Channel function
+// sequence:
+// - Clear enabled events
+// when CH0CC.VALUE = CNTR.VALUE.
+// SET_ON_0_TGL_ON_CMP Set on zero, toggle on compare repeatedly.
+//
+// Channel function
+// sequence:
+// - Set enabled events when
+// CNTR.VALUE = 0.
+// - Toggle enabled events
+// when CH0CC.VALUE = CNTR.VALUE.
+//
+// Set CTL.MODE to UP_PER
+// for edge-aligned PWM generation. Duty cycle is
+// given by:
+//
+// When CH0CC.VALUE <=
+// TARGET.VALUE:
+// Duty cycle =
+// CH0CC.VALUE / ( TARGET.VALUE + 1 ).
+//
+// When CH0CC.VALUE >
+// TARGET.VALUE:
+// Duty cycle = 1.
+//
+// Enabled events are
+// cleared when CH0CC.VALUE = 0 and CNTR.VALUE =
+// 0.
+// CLR_ON_0_TGL_ON_CMP Clear on zero, toggle on compare repeatedly.
+//
+// Channel function
+// sequence:
+// - Clear enabled events
+// when CNTR.VALUE = 0.
+// - Toggle enabled events
+// when CH0CC.VALUE = CNTR.VALUE.
+//
+// Set CTL.MODE to UPDWN_PER
+// for center-aligned PWM generation. Duty cycle
+// is given by:
+//
+// When CH0CC.VALUE <=
+// TARGET.VALUE:
+// Duty cycle = 1 - (
+// CH0CC.VALUE / TARGET.VALUE ).
+//
+// When CH0CC.VALUE >
+// TARGET.VALUE:
+// Duty cycle = 0.
+//
+// Enabled events are set
+// when CH0CC.VALUE = 0 and CNTR.VALUE = 0.
+// SET_ON_CAPT Set on capture repeatedly.
+//
+// Channel function
+// sequence:
+// - Set enabled events on
+// capture event and copy CNTR.VALUE to
+// CH0CC.VALUE.
+//
+// Primary use scenario is
+// to select this function before you start the
+// timer.
+// Follow these steps if you
+// need to select this function while CTL.MODE is
+// different from DIS:
+// - Select this function
+// with no event enable.
+// - Configure CH0CCFG
+// (optional).
+// - Wait for three timer
+// clock periods as defined in PRECFG before you
+// enable events.
+//
+// These steps prevent
+// capture events caused by expired signal values
+// in edge-detection circuit.
+// PER_PULSE_WIDTH_MEAS Period and pulse width measurement.
+//
+// Continuously capture
+// period and pulse width of the signal selected
+// by CH0CCFG.CAPT_SRC relative to the signal edge
+// given by CH0CCFG.EDGE.
+//
+// Set enabled events when
+// CH0CC.VALUE contains signal period and
+// CH0PCC.VALUE contains signal pulse width.
+//
+// Notes:
+// - Make sure that you
+// configure CH0CCFG.CAPT_SRC and CCACT when
+// CTL.MODE equals DIS, then set CTL.MODE to
+// UP_ONCE or UP_PER.
+// - The counter restarts in
+// the selected timer mode when CH0CC.VALUE
+// contains the signal period.
+// - If more than one
+// channel uses this function, the channels will
+// perform this function one at a time. The
+// channel with lowest number has priority and
+// performs the function first. Next measurement
+// starts when current measurement completes
+// successfully or times out. A timeout occurs
+// when counter equals target.
+// - If you want to observe
+// a timeout event configure another channel to
+// SET_ON_CAPT.
+//
+// Signal property
+// requirements:
+// - Signal Period >= 2 * (
+// 1 + PRECFG.CLKDIV ) * timer clock period.
+// - Signal Period <= 65535
+// * (1 + PRECFG.CLKDIV ) * timer clock period.
+// - Signal low and high
+// phase >= (1 + PRECFG.CLKDIV ) * timer clock
+// period.
+// PULSE_ON_CMP_DIS Pulse on compare, and then disable channel.
+//
+// Channel function
+// sequence:
+// - Pulse enabled events
+// when CH0CC.VALUE = CNTR.VALUE.
+// - Disable channel.
+//
+// The event is high for
+// two timer clock periods.
+// TGL_ON_CMP_DIS Toggle on compare, and then disable channel.
+//
+// Channel function
+// sequence:
+// - Toggle enabled events
+// when CH0CC.VALUE = CNTR.VALUE.
+// - Disable channel.
+// SET_ON_CMP_DIS Set on compare, and then disable channel.
+//
+// Channel function
+// sequence:
+// - Set enabled events when
+// CH0CC.VALUE = CNTR.VALUE.
+// - Disable channel.
+// CLR_ON_CMP_DIS Clear on compare, and then disable channel.
+//
+// Channel function
+// sequence:
+// - Clear enabled events
+// when CH0CC.VALUE = CNTR.VALUE.
+// - Disable channel.
+// SET_ON_0_TGL_ON_CMP_DIS Set on zero, toggle on compare, and then disable
+// channel.
+//
+// Channel function
+// sequence:
+// - Set enabled events when
+// CNTR.VALUE = 0.
+// - Toggle enabled events
+// when CH0CC.VALUE = CNTR.VALUE.
+// - Disable channel.
+//
+// Enabled events are
+// cleared when CH0CC.VALUE = 0 and CNTR.VALUE =
+// 0.
+// CLR_ON_0_TGL_ON_CMP_DIS Clear on zero, toggle on compare, and then disable
+// channel.
+//
+// Channel function
+// sequence:
+// - Clear enabled events
+// when CNTR.VALUE = 0.
+// - Toggle enabled events
+// when CH0CC.VALUE = CNTR.VALUE.
+// - Disable channel.
+//
+// Enabled events are set
+// when CH0CC.VALUE = 0 and CNTR.VALUE = 0.
+// SET_ON_CAPT_DIS Set on capture, and then disable channel.
+//
+// Channel function
+// sequence:
+// - Set enabled events on
+// capture event and copy CNTR.VALUE to
+// CH0CC.VALUE.
+// - Disable channel.
+//
+// Primary use scenario is
+// to select this function before you start the
+// timer.
+// Follow these steps if you
+// need to select this function while CTL.MODE is
+// different from DIS:
+// - Set CCACT to
+// SET_ON_CAPT with no event enable.
+// - Configure CH0CCFG
+// (optional).
+// - Wait for three timer
+// clock periods as defined in PRECFG before you
+// set CCACT to SET_ON_CAPT_DIS. Event enable is
+// optional.
+//
+// These steps prevent
+// capture events caused by expired signal values
+// in edge-detection circuit.
+// DIS Disable channel.
+#define AUX_TIMER2_CH0EVCFG_CCACT_W 4
+#define AUX_TIMER2_CH0EVCFG_CCACT_M 0x0000000F
+#define AUX_TIMER2_CH0EVCFG_CCACT_S 0
+#define AUX_TIMER2_CH0EVCFG_CCACT_PULSE_ON_CMP 0x0000000F
+#define AUX_TIMER2_CH0EVCFG_CCACT_TGL_ON_CMP 0x0000000E
+#define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_CMP 0x0000000D
+#define AUX_TIMER2_CH0EVCFG_CCACT_CLR_ON_CMP 0x0000000C
+#define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000B
+#define AUX_TIMER2_CH0EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000A
+#define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_CAPT 0x00000009
+#define AUX_TIMER2_CH0EVCFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008
+#define AUX_TIMER2_CH0EVCFG_CCACT_PULSE_ON_CMP_DIS 0x00000007
+#define AUX_TIMER2_CH0EVCFG_CCACT_TGL_ON_CMP_DIS 0x00000006
+#define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_CMP_DIS 0x00000005
+#define AUX_TIMER2_CH0EVCFG_CCACT_CLR_ON_CMP_DIS 0x00000004
+#define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003
+#define AUX_TIMER2_CH0EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002
+#define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_CAPT_DIS 0x00000001
+#define AUX_TIMER2_CH0EVCFG_CCACT_DIS 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_TIMER2_O_CH0CCFG
+//
+//*****************************************************************************
+// Field: [6:1] CAPT_SRC
+//
+// Select capture signal source from the asynchronous AUX event bus.
+//
+// The selected signal enters the edge-detection circuit. False capture events
+// can occur when:
+// - the edge-detection circuit contains expired signal samples and the circuit
+// is enabled without flush as described in CH0EVCFG
+// - this register is reconfigured while CTL.MODE is different from DIS.
+//
+// You can avoid false capture events. When wanted channel function is:
+// - SET_ON_CAPT_DIS, see description for SET_ON_CAPT_DIS in CH0EVCFG.CCACT.
+// - SET_ON_CAPT, see description for SET_ON_CAPT in CH0EVCFG.CCACT.
+// - PER_PULSE_WIDTH_MEAS, see description for PER_PULSE_WIDTH_MEAS in
+// CH0EVCFG.CCACT.
+//
+// If you write a non-enumerated value the behavior is identical to NO_EVENT.
+// The written value is returned when read.
+// ENUMs:
+// NO_EVENT No event.
+// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE
+// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY
+// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL
+// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ
+// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE
+// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N
+// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE
+// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV
+// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV
+// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3
+// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2
+// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1
+// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0
+// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB
+// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA
+// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1
+// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0
+// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV
+// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF
+// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE
+// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE
+// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN
+// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF
+// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD
+// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD
+// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ
+// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY
+// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2
+// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV
+// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31
+// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30
+// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29
+// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28
+// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27
+// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26
+// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25
+// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24
+// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23
+// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22
+// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21
+// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20
+// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19
+// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18
+// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17
+// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16
+// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15
+// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14
+// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13
+// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12
+// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11
+// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10
+// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9
+// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8
+// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7
+// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6
+// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5
+// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4
+// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3
+// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2
+// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1
+// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_W 6
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_M 0x0000007E
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_S 1
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_NO_EVENT 0x0000007E
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000007A
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00000078
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00000076
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_ADC_IRQ 0x00000074
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_ADC_DONE 0x00000072
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_ISRC_RESET_N 0x00000070
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TDC_DONE 0x0000006E
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER0_EV 0x0000006C
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER1_EV 0x0000006A
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER2_EV3 0x00000066
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER2_EV2 0x00000064
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER2_EV1 0x00000062
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER2_EV0 0x00000060
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_COMPB 0x0000005E
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_COMPA 0x0000005C
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_MCU_OBSMUX1 0x0000005A
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_MCU_OBSMUX0 0x00000058
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_MCU_EV 0x00000056
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_ACLK_REF 0x00000054
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_VDDR_RECHARGE 0x00000052
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_MCU_ACTIVE 0x00000050
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_PWR_DWN 0x0000004E
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_SCLK_LF 0x0000004C
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AON_BATMON_TEMP_UPD 0x0000004A
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AON_BATMON_BAT_UPD 0x00000048
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AON_RTC_4KHZ 0x00000046
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AON_RTC_CH2_DLY 0x00000044
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AON_RTC_CH2 0x00000042
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_MANUAL_EV 0x00000040
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO31 0x0000003E
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO30 0x0000003C
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO29 0x0000003A
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO28 0x00000038
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO27 0x00000036
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO26 0x00000034
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO25 0x00000032
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO24 0x00000030
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO23 0x0000002E
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO22 0x0000002C
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO21 0x0000002A
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO20 0x00000028
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO19 0x00000026
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO18 0x00000024
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO17 0x00000022
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO16 0x00000020
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO15 0x0000001E
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO14 0x0000001C
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO13 0x0000001A
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO12 0x00000018
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO11 0x00000016
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO10 0x00000014
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO9 0x00000012
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO8 0x00000010
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO7 0x0000000E
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO6 0x0000000C
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO5 0x0000000A
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO4 0x00000008
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO3 0x00000006
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO2 0x00000004
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO1 0x00000002
+#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO0 0x00000000
+
+// Field: [0] EDGE
+//
+// Edge configuration.
+//
+// Channel captures counter value at selected edge on signal source selected by
+// CAPT_SRC. See CH0EVCFG.CCACT.
+// ENUMs:
+// RISING Capture CNTR.VALUE at rising edge of CAPT_SRC.
+// FALLING Capture CNTR.VALUE at falling edge of CAPT_SRC.
+#define AUX_TIMER2_CH0CCFG_EDGE 0x00000001
+#define AUX_TIMER2_CH0CCFG_EDGE_BITN 0
+#define AUX_TIMER2_CH0CCFG_EDGE_M 0x00000001
+#define AUX_TIMER2_CH0CCFG_EDGE_S 0
+#define AUX_TIMER2_CH0CCFG_EDGE_RISING 0x00000001
+#define AUX_TIMER2_CH0CCFG_EDGE_FALLING 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_TIMER2_O_CH0PCC
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Pipeline Capture Compare value.
+//
+// 16-bit user defined pipeline compare value or channel-updated capture value.
+//
+// Compare mode:
+// An update of VALUE will be transferred to CH0CC.VALUE when the next
+// CNTR.VALUE is zero and CTL.MODE is different from DIS. This is useful for
+// PWM generation and prevents jitter on the edges of the generated signal.
+//
+// Capture mode:
+// When CH0EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the
+// width of the low or high phase of the selected signal. This is specified by
+// CH0CCFG.EDGE and CH0CCFG.CAPT_SRC.
+#define AUX_TIMER2_CH0PCC_VALUE_W 16
+#define AUX_TIMER2_CH0PCC_VALUE_M 0x0000FFFF
+#define AUX_TIMER2_CH0PCC_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_TIMER2_O_CH0CC
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Capture Compare value.
+//
+// 16-bit user defined compare value or channel-updated capture value.
+//
+// Compare mode:
+// VALUE is compared against CNTR.VALUE and an event is generated as specified
+// by CH0EVCFG.CCACT when these are equal.
+//
+// Capture mode:
+// The current counter value is stored in VALUE when a capture event occurs.
+// CH0EVCFG.CCACT determines if VALUE is a signal period or a regular capture
+// value.
+#define AUX_TIMER2_CH0CC_VALUE_W 16
+#define AUX_TIMER2_CH0CC_VALUE_M 0x0000FFFF
+#define AUX_TIMER2_CH0CC_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_TIMER2_O_CH1EVCFG
+//
+//*****************************************************************************
+// Field: [7] EV3_GEN
+//
+// Event 3 enable.
+//
+// 0: Channel 1 does not control event 3.
+// 1: Channel 1 controls event 3.
+//
+// When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event.
+#define AUX_TIMER2_CH1EVCFG_EV3_GEN 0x00000080
+#define AUX_TIMER2_CH1EVCFG_EV3_GEN_BITN 7
+#define AUX_TIMER2_CH1EVCFG_EV3_GEN_M 0x00000080
+#define AUX_TIMER2_CH1EVCFG_EV3_GEN_S 7
+
+// Field: [6] EV2_GEN
+//
+// Event 2 enable.
+//
+// 0: Channel 1 does not control event 2.
+// 1: Channel 1 controls event 2.
+//
+// When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event.
+#define AUX_TIMER2_CH1EVCFG_EV2_GEN 0x00000040
+#define AUX_TIMER2_CH1EVCFG_EV2_GEN_BITN 6
+#define AUX_TIMER2_CH1EVCFG_EV2_GEN_M 0x00000040
+#define AUX_TIMER2_CH1EVCFG_EV2_GEN_S 6
+
+// Field: [5] EV1_GEN
+//
+// Event 1 enable.
+//
+// 0: Channel 1 does not control event 1.
+// 1: Channel 1 controls event 1.
+//
+// When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event.
+#define AUX_TIMER2_CH1EVCFG_EV1_GEN 0x00000020
+#define AUX_TIMER2_CH1EVCFG_EV1_GEN_BITN 5
+#define AUX_TIMER2_CH1EVCFG_EV1_GEN_M 0x00000020
+#define AUX_TIMER2_CH1EVCFG_EV1_GEN_S 5
+
+// Field: [4] EV0_GEN
+//
+// Event 0 enable.
+//
+// 0: Channel 1 does not control event 0.
+// 1: Channel 1 controls event 0.
+//
+// When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event.
+#define AUX_TIMER2_CH1EVCFG_EV0_GEN 0x00000010
+#define AUX_TIMER2_CH1EVCFG_EV0_GEN_BITN 4
+#define AUX_TIMER2_CH1EVCFG_EV0_GEN_M 0x00000010
+#define AUX_TIMER2_CH1EVCFG_EV0_GEN_S 4
+
+// Field: [3:0] CCACT
+//
+// Capture-Compare action.
+//
+// Capture-Compare action defines 15 different channel functions that utilize
+// capture, compare, and zero events.
+// ENUMs:
+// PULSE_ON_CMP Pulse on compare repeatedly.
+//
+// Channel function
+// sequence:
+// - Pulse enabled events
+// when CH1CC.VALUE = CNTR.VALUE.
+//
+// The event is high for
+// two timer clock periods.
+// TGL_ON_CMP Toggle on compare repeatedly.
+//
+// Channel function
+// sequence:
+// - Toggle enabled events
+// when CH1CC.VALUE = CNTR.VALUE.
+// SET_ON_CMP Set on compare repeatedly.
+//
+// Channel function
+// sequence:
+// - Set enabled events
+// when CH1CC.VALUE = CNTR.VALUE.
+// CLR_ON_CMP Clear on compare repeatedly.
+//
+// Channel function
+// sequence:
+// - Clear enabled events
+// when CH1CC.VALUE = CNTR.VALUE.
+// SET_ON_0_TGL_ON_CMP Set on zero, toggle on compare repeatedly.
+//
+// Channel function
+// sequence:
+// - Set enabled events when
+// CNTR.VALUE = 0.
+// - Toggle enabled events
+// when CH1CC.VALUE = CNTR.VALUE.
+//
+// Set CTL.MODE to UP_PER
+// for edge-aligned PWM generation. Duty cycle is
+// given by:
+//
+// When CH1CC.VALUE <=
+// TARGET.VALUE:
+// Duty cycle =
+// CH1CC.VALUE / ( TARGET.VALUE + 1 ).
+//
+// When CH1CC.VALUE >
+// TARGET.VALUE:
+// Duty cycle = 1.
+//
+// Enabled events are
+// cleared when CH1CC.VALUE = 0 and CNTR.VALUE =
+// 0.
+// CLR_ON_0_TGL_ON_CMP Clear on zero, toggle on compare repeatedly.
+//
+// Channel function
+// sequence:
+// - Clear enabled events
+// when CNTR.VALUE = 0.
+// - Toggle enabled events
+// when CH1CC.VALUE = CNTR.VALUE.
+//
+// Set CTL.MODE to UPDWN_PER
+// for center-aligned PWM generation. Duty cycle
+// is given by:
+//
+// When CH1CC.VALUE <=
+// TARGET.VALUE:
+// Duty cycle = 1 - (
+// CH1CC.VALUE / TARGET.VALUE ).
+//
+// When CH1CC.VALUE >
+// TARGET.VALUE:
+// Duty cycle = 0.
+//
+// Enabled events are set
+// when CH1CC.VALUE = 0 and CNTR.VALUE = 0.
+// SET_ON_CAPT Set on capture repeatedly.
+//
+// Channel function
+// sequence:
+// - Set enabled events on
+// capture event and copy CNTR.VALUE to
+// CH1CC.VALUE.
+//
+// Primary use scenario is
+// to select this function before you start the
+// timer.
+// Follow these steps if you
+// need to select this function while CTL.MODE is
+// different from DIS:
+// - Select this function
+// with no event enable.
+// - Configure CH1CCFG
+// (optional).
+// - Wait for three timer
+// clock periods as defined in PRECFG before you
+// enable events.
+//
+// These steps prevent
+// capture events caused by expired signal values
+// in edge-detection circuit.
+// PER_PULSE_WIDTH_MEAS Period and pulse width measurement.
+//
+// Continuously capture
+// period and pulse width of the signal selected
+// by CH1CCFG.CAPT_SRC relative to the signal edge
+// given by CH1CCFG.EDGE.
+//
+// Set enabled events when
+// CH1CC.VALUE contains signal period and
+// CH1PCC.VALUE contains signal pulse width.
+//
+// Notes:
+// - Make sure that you
+// configure CH1CCFG.CAPT_SRC and CCACT when
+// CTL.MODE equals DIS, then set CTL.MODE to
+// UP_ONCE or UP_PER.
+// - The counter restarts in
+// the selected timer mode when CH1CC.VALUE
+// contains the signal period.
+// - If more than one
+// channel uses this function, the channels will
+// perform this function one at a time. The
+// channel with lowest number has priority and
+// performs the function first. Next measurement
+// starts when current measurement completes
+// successfully or times out. A timeout occurs
+// when counter equals target.
+// - If you want to observe
+// a timeout event configure another channel to
+// SET_ON_CAPT.
+//
+// Signal property
+// requirements:
+// - Signal Period >= 2 * (
+// 1 + PRECFG.CLKDIV ) * timer clock period.
+// - Signal Period <= 65535
+// * (1 + PRECFG.CLKDIV ) * timer clock period.
+// - Signal low and high
+// phase >= (1 + PRECFG.CLKDIV ) * timer clock
+// period.
+// PULSE_ON_CMP_DIS Pulse on compare, and then disable channel.
+//
+// Channel function
+// sequence:
+// - Pulse enabled events
+// when CH1CC.VALUE = CNTR.VALUE.
+// - Disable channel.
+//
+// The event is high for
+// two timer clock periods.
+// TGL_ON_CMP_DIS Toggle on compare, and then disable channel.
+//
+// Channel function
+// sequence:
+// - Toggle enabled events
+// when CH1CC.VALUE = CNTR.VALUE.
+// - Disable channel.
+// SET_ON_CMP_DIS Set on compare, and then disable channel.
+//
+// Channel function
+// sequence:
+// - Set enabled events when
+// CH1CC.VALUE = CNTR.VALUE.
+// - Disable channel.
+// CLR_ON_CMP_DIS Clear on compare, and then disable channel.
+//
+// Channel function
+// sequence:
+// - Clear enabled events
+// when CH1CC.VALUE = CNTR.VALUE.
+// - Disable channel.
+// SET_ON_0_TGL_ON_CMP_DIS Set on zero, toggle on compare, and then disable
+// channel.
+//
+// Channel function
+// sequence:
+// - Set enabled events when
+// CNTR.VALUE = 0.
+// - Toggle enabled events
+// when CH1CC.VALUE = CNTR.VALUE.
+// - Disable channel.
+//
+// Enabled events are
+// cleared when CH1CC.VALUE = 0 and CNTR.VALUE =
+// 0.
+// CLR_ON_0_TGL_ON_CMP_DIS Clear on zero, toggle on compare, and then disable
+// channel.
+//
+// Channel function
+// sequence:
+// - Clear enabled events
+// when CNTR.VALUE = 0.
+// - Toggle enabled events
+// when CH1CC.VALUE = CNTR.VALUE.
+// - Disable channel.
+//
+// Enabled events are set
+// when CH1CC.VALUE = 0 and CNTR.VALUE = 0.
+// SET_ON_CAPT_DIS Set on capture, and then disable channel.
+//
+// Channel function
+// sequence:
+// - Set enabled events on
+// capture event and copy CNTR.VALUE to
+// CH1CC.VALUE.
+// - Disable channel.
+//
+// Primary use scenario is
+// to select this function before you start the
+// timer.
+// Follow these steps if you
+// need to select this function while CTL.MODE is
+// different from DIS:
+// - Set CCACT to
+// SET_ON_CAPT with no event enable.
+// - Configure CH1CCFG
+// (optional).
+// - Wait for three timer
+// clock periods as defined in PRECFG before you
+// set CCACT to SET_ON_CAPT_DIS. Event enable is
+// optional.
+//
+// These steps prevent
+// capture events caused by expired signal values
+// in edge-detection circuit.
+// DIS Disable channel.
+#define AUX_TIMER2_CH1EVCFG_CCACT_W 4
+#define AUX_TIMER2_CH1EVCFG_CCACT_M 0x0000000F
+#define AUX_TIMER2_CH1EVCFG_CCACT_S 0
+#define AUX_TIMER2_CH1EVCFG_CCACT_PULSE_ON_CMP 0x0000000F
+#define AUX_TIMER2_CH1EVCFG_CCACT_TGL_ON_CMP 0x0000000E
+#define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_CMP 0x0000000D
+#define AUX_TIMER2_CH1EVCFG_CCACT_CLR_ON_CMP 0x0000000C
+#define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000B
+#define AUX_TIMER2_CH1EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000A
+#define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_CAPT 0x00000009
+#define AUX_TIMER2_CH1EVCFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008
+#define AUX_TIMER2_CH1EVCFG_CCACT_PULSE_ON_CMP_DIS 0x00000007
+#define AUX_TIMER2_CH1EVCFG_CCACT_TGL_ON_CMP_DIS 0x00000006
+#define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_CMP_DIS 0x00000005
+#define AUX_TIMER2_CH1EVCFG_CCACT_CLR_ON_CMP_DIS 0x00000004
+#define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003
+#define AUX_TIMER2_CH1EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002
+#define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_CAPT_DIS 0x00000001
+#define AUX_TIMER2_CH1EVCFG_CCACT_DIS 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_TIMER2_O_CH1CCFG
+//
+//*****************************************************************************
+// Field: [6:1] CAPT_SRC
+//
+// Select capture signal source from the asynchronous AUX event bus.
+//
+// The selected signal enters the edge-detection circuit. False capture events
+// can occur when:
+// - the edge-detection circuit contains expired signal samples and the circuit
+// is enabled without flush as described in CH1EVCFG
+// - this register is reconfigured while CTL.MODE is different from DIS.
+//
+// You can avoid false capture events. When wanted channel function is:
+// - SET_ON_CAPT_DIS, see description for SET_ON_CAPT_DIS in CH1EVCFG.CCACT.
+// - SET_ON_CAPT, see description for SET_ON_CAPT in CH1EVCFG.CCACT.
+// - PER_PULSE_WIDTH_MEAS, see description for PER_PULSE_WIDTH_MEAS in
+// CH1EVCFG.CCACT.
+//
+// If you write a non-enumerated value the behavior is identical to NO_EVENT.
+// The written value is returned when read.
+// ENUMs:
+// NO_EVENT No event.
+// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE
+// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY
+// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL
+// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ
+// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE
+// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N
+// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE
+// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV
+// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV
+// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3
+// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2
+// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1
+// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0
+// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB
+// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA
+// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1
+// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0
+// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV
+// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF
+// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE
+// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE
+// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN
+// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF
+// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD
+// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD
+// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ
+// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY
+// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2
+// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV
+// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31
+// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30
+// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29
+// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28
+// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27
+// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26
+// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25
+// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24
+// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23
+// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22
+// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21
+// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20
+// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19
+// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18
+// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17
+// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16
+// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15
+// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14
+// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13
+// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12
+// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11
+// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10
+// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9
+// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8
+// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7
+// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6
+// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5
+// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4
+// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3
+// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2
+// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1
+// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_W 6
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_M 0x0000007E
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_S 1
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_NO_EVENT 0x0000007E
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000007A
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00000078
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00000076
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_ADC_IRQ 0x00000074
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_ADC_DONE 0x00000072
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_ISRC_RESET_N 0x00000070
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TDC_DONE 0x0000006E
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER0_EV 0x0000006C
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER1_EV 0x0000006A
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER2_EV3 0x00000066
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER2_EV2 0x00000064
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER2_EV1 0x00000062
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER2_EV0 0x00000060
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_COMPB 0x0000005E
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_COMPA 0x0000005C
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_MCU_OBSMUX1 0x0000005A
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_MCU_OBSMUX0 0x00000058
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_MCU_EV 0x00000056
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_ACLK_REF 0x00000054
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_VDDR_RECHARGE 0x00000052
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_MCU_ACTIVE 0x00000050
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_PWR_DWN 0x0000004E
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_SCLK_LF 0x0000004C
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AON_BATMON_TEMP_UPD 0x0000004A
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AON_BATMON_BAT_UPD 0x00000048
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AON_RTC_4KHZ 0x00000046
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AON_RTC_CH2_DLY 0x00000044
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AON_RTC_CH2 0x00000042
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_MANUAL_EV 0x00000040
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO31 0x0000003E
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO30 0x0000003C
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO29 0x0000003A
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO28 0x00000038
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO27 0x00000036
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO26 0x00000034
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO25 0x00000032
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO24 0x00000030
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO23 0x0000002E
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO22 0x0000002C
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO21 0x0000002A
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO20 0x00000028
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO19 0x00000026
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO18 0x00000024
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO17 0x00000022
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO16 0x00000020
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO15 0x0000001E
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO14 0x0000001C
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO13 0x0000001A
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO12 0x00000018
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO11 0x00000016
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO10 0x00000014
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO9 0x00000012
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO8 0x00000010
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO7 0x0000000E
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO6 0x0000000C
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO5 0x0000000A
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO4 0x00000008
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO3 0x00000006
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO2 0x00000004
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO1 0x00000002
+#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO0 0x00000000
+
+// Field: [0] EDGE
+//
+// Edge configuration.
+//
+// Channel captures counter value at selected edge on signal source selected by
+// CAPT_SRC. See CH1EVCFG.CCACT.
+// ENUMs:
+// RISING Capture CNTR.VALUE at rising edge of CAPT_SRC.
+// FALLING Capture CNTR.VALUE at falling edge of CAPT_SRC.
+#define AUX_TIMER2_CH1CCFG_EDGE 0x00000001
+#define AUX_TIMER2_CH1CCFG_EDGE_BITN 0
+#define AUX_TIMER2_CH1CCFG_EDGE_M 0x00000001
+#define AUX_TIMER2_CH1CCFG_EDGE_S 0
+#define AUX_TIMER2_CH1CCFG_EDGE_RISING 0x00000001
+#define AUX_TIMER2_CH1CCFG_EDGE_FALLING 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_TIMER2_O_CH1PCC
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Pipeline Capture Compare value.
+//
+// 16-bit user defined pipeline compare value or channel-updated capture value.
+//
+// Compare mode:
+// An update of VALUE will be transferred to CH1CC.VALUE when the next
+// CNTR.VALUE is zero and CTL.MODE is different from DIS. This is useful for
+// PWM generation and prevents jitter on the edges of the generated signal.
+//
+// Capture mode:
+// When CH1EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the
+// width of the low or high phase of the selected signal. This is specified by
+// CH1CCFG.EDGE and CH1CCFG.CAPT_SRC.
+#define AUX_TIMER2_CH1PCC_VALUE_W 16
+#define AUX_TIMER2_CH1PCC_VALUE_M 0x0000FFFF
+#define AUX_TIMER2_CH1PCC_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_TIMER2_O_CH1CC
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Capture Compare value.
+//
+// 16-bit user defined compare value or channel-updated capture value.
+//
+// Compare mode:
+// VALUE is compared against CNTR.VALUE and an event is generated as specified
+// by CH1EVCFG.CCACT when these are equal.
+//
+// Capture mode:
+// The current counter value is stored in VALUE when a capture event occurs.
+// CH1EVCFG.CCACT determines if VALUE is a signal period or a regular capture
+// value.
+#define AUX_TIMER2_CH1CC_VALUE_W 16
+#define AUX_TIMER2_CH1CC_VALUE_M 0x0000FFFF
+#define AUX_TIMER2_CH1CC_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_TIMER2_O_CH2EVCFG
+//
+//*****************************************************************************
+// Field: [7] EV3_GEN
+//
+// Event 3 enable.
+//
+// 0: Channel 2 does not control event 3.
+// 1: Channel 2 controls event 3.
+//
+// When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event.
+#define AUX_TIMER2_CH2EVCFG_EV3_GEN 0x00000080
+#define AUX_TIMER2_CH2EVCFG_EV3_GEN_BITN 7
+#define AUX_TIMER2_CH2EVCFG_EV3_GEN_M 0x00000080
+#define AUX_TIMER2_CH2EVCFG_EV3_GEN_S 7
+
+// Field: [6] EV2_GEN
+//
+// Event 2 enable.
+//
+// 0: Channel 2 does not control event 2.
+// 1: Channel 2 controls event 2.
+//
+// When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event.
+#define AUX_TIMER2_CH2EVCFG_EV2_GEN 0x00000040
+#define AUX_TIMER2_CH2EVCFG_EV2_GEN_BITN 6
+#define AUX_TIMER2_CH2EVCFG_EV2_GEN_M 0x00000040
+#define AUX_TIMER2_CH2EVCFG_EV2_GEN_S 6
+
+// Field: [5] EV1_GEN
+//
+// Event 1 enable.
+//
+// 0: Channel 2 does not control event 1.
+// 1: Channel 2 controls event 1.
+//
+// When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event.
+#define AUX_TIMER2_CH2EVCFG_EV1_GEN 0x00000020
+#define AUX_TIMER2_CH2EVCFG_EV1_GEN_BITN 5
+#define AUX_TIMER2_CH2EVCFG_EV1_GEN_M 0x00000020
+#define AUX_TIMER2_CH2EVCFG_EV1_GEN_S 5
+
+// Field: [4] EV0_GEN
+//
+// Event 0 enable.
+//
+// 0: Channel 2 does not control event 0.
+// 1: Channel 2 controls event 0.
+//
+// When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event.
+#define AUX_TIMER2_CH2EVCFG_EV0_GEN 0x00000010
+#define AUX_TIMER2_CH2EVCFG_EV0_GEN_BITN 4
+#define AUX_TIMER2_CH2EVCFG_EV0_GEN_M 0x00000010
+#define AUX_TIMER2_CH2EVCFG_EV0_GEN_S 4
+
+// Field: [3:0] CCACT
+//
+// Capture-Compare action.
+//
+// Capture-Compare action defines 15 different channel functions that utilize
+// capture, compare, and zero events.
+// ENUMs:
+// PULSE_ON_CMP Pulse on compare repeatedly.
+//
+// Channel function
+// sequence:
+// - Pulse enabled events
+// when CH2CC.VALUE = CNTR.VALUE.
+//
+// The event is high for
+// two timer clock periods.
+// TGL_ON_CMP Toggle on compare repeatedly.
+//
+// Channel function
+// sequence:
+// - Toggle enabled events
+// when CH2CC.VALUE = CNTR.VALUE.
+// SET_ON_CMP Set on compare repeatedly.
+//
+// Channel function
+// sequence:
+// - Set enabled events
+// when CH2CC.VALUE = CNTR.VALUE.
+// CLR_ON_CMP Clear on compare repeatedly.
+//
+// Channel function
+// sequence:
+// - Clear enabled events
+// when CH2CC.VALUE = CNTR.VALUE.
+// SET_ON_0_TGL_ON_CMP Set on zero, toggle on compare repeatedly.
+//
+// Channel function
+// sequence:
+// - Set enabled events when
+// CNTR.VALUE = 0.
+// - Toggle enabled events
+// when CH2CC.VALUE = CNTR.VALUE.
+//
+// Set CTL.MODE to UP_PER
+// for edge-aligned PWM generation. Duty cycle is
+// given by:
+//
+// When CH2CC.VALUE <=
+// TARGET.VALUE:
+// Duty cycle =
+// CH2CC.VALUE / ( TARGET.VALUE + 1 ).
+//
+// When CH2CC.VALUE >
+// TARGET.VALUE:
+// Duty cycle = 1.
+//
+// Enabled events are
+// cleared when CH2CC.VALUE = 0 and CNTR.VALUE =
+// 0.
+// CLR_ON_0_TGL_ON_CMP Clear on zero, toggle on compare repeatedly.
+//
+// Channel function
+// sequence:
+// - Clear enabled events
+// when CNTR.VALUE = 0.
+// - Toggle enabled events
+// when CH2CC.VALUE = CNTR.VALUE.
+//
+// Set CTL.MODE to UPDWN_PER
+// for center-aligned PWM generation. Duty cycle
+// is given by:
+//
+// When CH2CC.VALUE <=
+// TARGET.VALUE:
+// Duty cycle = 1 - (
+// CH2CC.VALUE / TARGET.VALUE ).
+//
+// When CH2CC.VALUE >
+// TARGET.VALUE:
+// Duty cycle = 0.
+//
+// Enabled events are set
+// when CH2CC.VALUE = 0 and CNTR.VALUE = 0.
+// SET_ON_CAPT Set on capture repeatedly.
+//
+// Channel function
+// sequence:
+// - Set enabled events on
+// capture event and copy CNTR.VALUE to
+// CH2CC.VALUE.
+//
+// Primary use scenario is
+// to select this function before you start the
+// timer.
+// Follow these steps if you
+// need to select this function while CTL.MODE is
+// different from DIS:
+// - Select this function
+// with no event enable.
+// - Configure CH2CCFG
+// (optional).
+// - Wait for three timer
+// clock periods as defined in PRECFG before you
+// enable events.
+//
+// These steps prevent
+// capture events caused by expired signal values
+// in edge-detection circuit.
+// PER_PULSE_WIDTH_MEAS Period and pulse width measurement.
+//
+// Continuously capture
+// period and pulse width of the signal selected
+// by CH2CCFG.CAPT_SRC relative to the signal edge
+// given by CH2CCFG.EDGE.
+//
+// Set enabled events when
+// CH2CC.VALUE contains signal period and
+// CH2PCC.VALUE contains signal pulse width.
+//
+// Notes:
+// - Make sure that you
+// configure CH2CCFG.CAPT_SRC and CCACT when
+// CTL.MODE equals DIS, then set CTL.MODE to
+// UP_ONCE or UP_PER.
+// - The counter restarts in
+// the selected timer mode when CH2CC.VALUE
+// contains the signal period.
+// - If more than one
+// channel uses this function, the channels will
+// perform this function one at a time. The
+// channel with lowest number has priority and
+// performs the function first. Next measurement
+// starts when current measurement completes
+// successfully or times out. A timeout occurs
+// when counter equals target.
+// - If you want to observe
+// a timeout event configure another channel to
+// SET_ON_CAPT.
+//
+// Signal property
+// requirements:
+// - Signal Period >= 2 * (
+// 1 + PRECFG.CLKDIV ) * timer clock period.
+// - Signal Period <= 65535
+// * (1 + PRECFG.CLKDIV ) * timer clock period.
+// - Signal low and high
+// phase >= (1 + PRECFG.CLKDIV ) * timer clock
+// period.
+// PULSE_ON_CMP_DIS Pulse on compare, and then disable channel.
+//
+// Channel function
+// sequence:
+// - Pulse enabled events
+// when CH2CC.VALUE = CNTR.VALUE.
+// - Disable channel.
+//
+// The event is high for
+// two timer clock periods.
+// TGL_ON_CMP_DIS Toggle on compare, and then disable channel.
+//
+// Channel function
+// sequence:
+// - Toggle enabled events
+// when CH2CC.VALUE = CNTR.VALUE.
+// - Disable channel.
+// SET_ON_CMP_DIS Set on compare, and then disable channel.
+//
+// Channel function
+// sequence:
+// - Set enabled events when
+// CH2CC.VALUE = CNTR.VALUE.
+// - Disable channel.
+// CLR_ON_CMP_DIS Clear on compare, and then disable channel.
+//
+// Channel function
+// sequence:
+// - Clear enabled events
+// when CH2CC.VALUE = CNTR.VALUE.
+// - Disable channel.
+// SET_ON_0_TGL_ON_CMP_DIS Set on zero, toggle on compare, and then disable
+// channel.
+//
+// Channel function
+// sequence:
+// - Set enabled events when
+// CNTR.VALUE = 0.
+// - Toggle enabled events
+// when CH2CC.VALUE = CNTR.VALUE.
+// - Disable channel.
+//
+// Enabled events are
+// cleared when CH2CC.VALUE = 0 and CNTR.VALUE =
+// 0.
+// CLR_ON_0_TGL_ON_CMP_DIS Clear on zero, toggle on compare, and then disable
+// channel.
+//
+// Channel function
+// sequence:
+// - Clear enabled events
+// when CNTR.VALUE = 0.
+// - Toggle enabled events
+// when CH2CC.VALUE = CNTR.VALUE.
+// - Disable channel.
+//
+// Enabled events are set
+// when CH2CC.VALUE = 0 and CNTR.VALUE = 0.
+// SET_ON_CAPT_DIS Set on capture, and then disable channel.
+//
+// Channel function
+// sequence:
+// - Set enabled events on
+// capture event and copy CNTR.VALUE to
+// CH2CC.VALUE.
+// - Disable channel.
+//
+// Primary use scenario is
+// to select this function before you start the
+// timer.
+// Follow these steps if you
+// need to select this function while CTL.MODE is
+// different from DIS:
+// - Set to SET_ON_CAPT
+// with no event enable.
+// - Configure CH2CCFG
+// (optional).
+// - Wait for three timer
+// clock periods as defined in PRECFG before you
+// set to SET_ON_CAPT_DIS. Event enable is
+// optional.
+//
+// These steps prevent
+// capture events caused by expired signal values
+// in edge-detection circuit.
+// DIS Disable channel.
+#define AUX_TIMER2_CH2EVCFG_CCACT_W 4
+#define AUX_TIMER2_CH2EVCFG_CCACT_M 0x0000000F
+#define AUX_TIMER2_CH2EVCFG_CCACT_S 0
+#define AUX_TIMER2_CH2EVCFG_CCACT_PULSE_ON_CMP 0x0000000F
+#define AUX_TIMER2_CH2EVCFG_CCACT_TGL_ON_CMP 0x0000000E
+#define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_CMP 0x0000000D
+#define AUX_TIMER2_CH2EVCFG_CCACT_CLR_ON_CMP 0x0000000C
+#define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000B
+#define AUX_TIMER2_CH2EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000A
+#define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_CAPT 0x00000009
+#define AUX_TIMER2_CH2EVCFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008
+#define AUX_TIMER2_CH2EVCFG_CCACT_PULSE_ON_CMP_DIS 0x00000007
+#define AUX_TIMER2_CH2EVCFG_CCACT_TGL_ON_CMP_DIS 0x00000006
+#define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_CMP_DIS 0x00000005
+#define AUX_TIMER2_CH2EVCFG_CCACT_CLR_ON_CMP_DIS 0x00000004
+#define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003
+#define AUX_TIMER2_CH2EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002
+#define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_CAPT_DIS 0x00000001
+#define AUX_TIMER2_CH2EVCFG_CCACT_DIS 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_TIMER2_O_CH2CCFG
+//
+//*****************************************************************************
+// Field: [6:1] CAPT_SRC
+//
+// Select capture signal source from the asynchronous AUX event bus.
+//
+// The selected signal enters the edge-detection circuit. False capture events
+// can occur when:
+// - the edge-detection circuit contains expired signal samples and the circuit
+// is enabled without flush as described in CH2EVCFG
+// - this register is reconfigured while CTL.MODE is different from DIS.
+//
+// You can avoid false capture events. When wanted channel function is:
+// - SET_ON_CAPT_DIS, see description for SET_ON_CAPT_DIS in CH2EVCFG.CCACT.
+// - SET_ON_CAPT, see description for SET_ON_CAPT in CH2EVCFG.CCACT.
+// - PER_PULSE_WIDTH_MEAS, see description for PER_PULSE_WIDTH_MEAS in
+// CH2EVCFG.CCACT.
+//
+// If you write a non-enumerated value the behavior is identical to NO_EVENT.
+// The written value is returned when read.
+// ENUMs:
+// NO_EVENT No event.
+// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE
+// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY
+// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL
+// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ
+// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE
+// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N
+// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE
+// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV
+// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV
+// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3
+// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2
+// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1
+// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0
+// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB
+// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA
+// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1
+// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0
+// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV
+// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF
+// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE
+// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE
+// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN
+// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF
+// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD
+// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD
+// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ
+// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY
+// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2
+// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV
+// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31
+// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30
+// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29
+// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28
+// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27
+// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26
+// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25
+// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24
+// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23
+// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22
+// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21
+// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20
+// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19
+// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18
+// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17
+// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16
+// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15
+// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14
+// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13
+// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12
+// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11
+// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10
+// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9
+// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8
+// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7
+// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6
+// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5
+// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4
+// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3
+// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2
+// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1
+// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_W 6
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_M 0x0000007E
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_S 1
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_NO_EVENT 0x0000007E
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000007A
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00000078
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00000076
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_ADC_IRQ 0x00000074
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_ADC_DONE 0x00000072
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_ISRC_RESET_N 0x00000070
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TDC_DONE 0x0000006E
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER0_EV 0x0000006C
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER1_EV 0x0000006A
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER2_EV3 0x00000066
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER2_EV2 0x00000064
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER2_EV1 0x00000062
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER2_EV0 0x00000060
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_COMPB 0x0000005E
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_COMPA 0x0000005C
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_MCU_OBSMUX1 0x0000005A
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_MCU_OBSMUX0 0x00000058
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_MCU_EV 0x00000056
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_ACLK_REF 0x00000054
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_VDDR_RECHARGE 0x00000052
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_MCU_ACTIVE 0x00000050
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_PWR_DWN 0x0000004E
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_SCLK_LF 0x0000004C
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AON_BATMON_TEMP_UPD 0x0000004A
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AON_BATMON_BAT_UPD 0x00000048
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AON_RTC_4KHZ 0x00000046
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AON_RTC_CH2_DLY 0x00000044
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AON_RTC_CH2 0x00000042
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_MANUAL_EV 0x00000040
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO31 0x0000003E
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO30 0x0000003C
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO29 0x0000003A
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO28 0x00000038
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO27 0x00000036
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO26 0x00000034
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO25 0x00000032
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO24 0x00000030
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO23 0x0000002E
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO22 0x0000002C
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO21 0x0000002A
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO20 0x00000028
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO19 0x00000026
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO18 0x00000024
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO17 0x00000022
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO16 0x00000020
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO15 0x0000001E
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO14 0x0000001C
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO13 0x0000001A
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO12 0x00000018
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO11 0x00000016
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO10 0x00000014
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO9 0x00000012
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO8 0x00000010
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO7 0x0000000E
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO6 0x0000000C
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO5 0x0000000A
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO4 0x00000008
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO3 0x00000006
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO2 0x00000004
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO1 0x00000002
+#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO0 0x00000000
+
+// Field: [0] EDGE
+//
+// Edge configuration.
+//
+// Channel captures counter value at selected edge on signal source selected by
+// CAPT_SRC. See CH2EVCFG.CCACT.
+// ENUMs:
+// RISING Capture CNTR.VALUE at rising edge of CAPT_SRC.
+// FALLING Capture CNTR.VALUE at falling edge of CAPT_SRC.
+#define AUX_TIMER2_CH2CCFG_EDGE 0x00000001
+#define AUX_TIMER2_CH2CCFG_EDGE_BITN 0
+#define AUX_TIMER2_CH2CCFG_EDGE_M 0x00000001
+#define AUX_TIMER2_CH2CCFG_EDGE_S 0
+#define AUX_TIMER2_CH2CCFG_EDGE_RISING 0x00000001
+#define AUX_TIMER2_CH2CCFG_EDGE_FALLING 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_TIMER2_O_CH2PCC
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Pipeline Capture Compare value.
+//
+// 16-bit user defined pipeline compare value or channel-updated capture value.
+//
+// Compare mode:
+// An update of VALUE will be transferred to CH2CC.VALUE when the next
+// CNTR.VALUE is zero and CTL.MODE is different from DIS. This is useful for
+// PWM generation and prevents jitter on the edges of the generated signal.
+//
+// Capture mode:
+// When CH2EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the
+// width of the low or high phase of the selected signal. This is specified by
+// CH2CCFG.EDGE and CH2CCFG.CAPT_SRC.
+#define AUX_TIMER2_CH2PCC_VALUE_W 16
+#define AUX_TIMER2_CH2PCC_VALUE_M 0x0000FFFF
+#define AUX_TIMER2_CH2PCC_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_TIMER2_O_CH2CC
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Capture Compare value.
+//
+// 16-bit user defined compare value or channel-updated capture value.
+//
+// Compare mode:
+// VALUE is compared against CNTR.VALUE and an event is generated as specified
+// by CH2EVCFG.CCACT when these are equal.
+//
+// Capture mode:
+// The current counter value is stored in VALUE when a capture event occurs.
+// CH2EVCFG.CCACT determines if VALUE is a signal period or a regular capture
+// value.
+#define AUX_TIMER2_CH2CC_VALUE_W 16
+#define AUX_TIMER2_CH2CC_VALUE_M 0x0000FFFF
+#define AUX_TIMER2_CH2CC_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_TIMER2_O_CH3EVCFG
+//
+//*****************************************************************************
+// Field: [7] EV3_GEN
+//
+// Event 3 enable.
+//
+// 0: Channel 3 does not control event 3.
+// 1: Channel 3 controls event 3.
+//
+// When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event.
+#define AUX_TIMER2_CH3EVCFG_EV3_GEN 0x00000080
+#define AUX_TIMER2_CH3EVCFG_EV3_GEN_BITN 7
+#define AUX_TIMER2_CH3EVCFG_EV3_GEN_M 0x00000080
+#define AUX_TIMER2_CH3EVCFG_EV3_GEN_S 7
+
+// Field: [6] EV2_GEN
+//
+// Event 2 enable.
+//
+// 0: Channel 3 does not control event 2.
+// 1: Channel 3 controls event 2.
+//
+// When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event.
+#define AUX_TIMER2_CH3EVCFG_EV2_GEN 0x00000040
+#define AUX_TIMER2_CH3EVCFG_EV2_GEN_BITN 6
+#define AUX_TIMER2_CH3EVCFG_EV2_GEN_M 0x00000040
+#define AUX_TIMER2_CH3EVCFG_EV2_GEN_S 6
+
+// Field: [5] EV1_GEN
+//
+// Event 1 enable.
+//
+// 0: Channel 3 does not control event 1.
+// 1: Channel 3 controls event 1.
+//
+// When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event.
+#define AUX_TIMER2_CH3EVCFG_EV1_GEN 0x00000020
+#define AUX_TIMER2_CH3EVCFG_EV1_GEN_BITN 5
+#define AUX_TIMER2_CH3EVCFG_EV1_GEN_M 0x00000020
+#define AUX_TIMER2_CH3EVCFG_EV1_GEN_S 5
+
+// Field: [4] EV0_GEN
+//
+// Event 0 enable.
+//
+// 0: Channel 3 does not control event 0.
+// 1: Channel 3 controls event 0.
+//
+// When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event.
+#define AUX_TIMER2_CH3EVCFG_EV0_GEN 0x00000010
+#define AUX_TIMER2_CH3EVCFG_EV0_GEN_BITN 4
+#define AUX_TIMER2_CH3EVCFG_EV0_GEN_M 0x00000010
+#define AUX_TIMER2_CH3EVCFG_EV0_GEN_S 4
+
+// Field: [3:0] CCACT
+//
+// Capture-Compare action.
+//
+// Capture-Compare action defines 15 different channel functions that utilize
+// capture, compare, and zero events.
+// ENUMs:
+// PULSE_ON_CMP Pulse on compare repeatedly.
+//
+// Channel function
+// sequence:
+// - Pulse enabled events
+// when CH3CC.VALUE = CNTR.VALUE.
+//
+// The event is high for
+// two timer clock periods.
+// TGL_ON_CMP Toggle on compare repeatedly.
+//
+// Channel function
+// sequence:
+// - Toggle enabled events
+// when CH3CC.VALUE = CNTR.VALUE.
+// SET_ON_CMP Set on compare repeatedly.
+//
+// Channel function
+// sequence:
+// - Set enabled events
+// when CH3CC.VALUE = CNTR.VALUE.
+// CLR_ON_CMP Clear on compare repeatedly.
+//
+// Channel function
+// sequence:
+// - Clear enabled events
+// when CH3CC.VALUE = CNTR.VALUE.
+// SET_ON_0_TGL_ON_CMP Set on zero, toggle on compare repeatedly.
+//
+// Channel function
+// sequence:
+// - Set enabled events when
+// CNTR.VALUE = 0.
+// - Toggle enabled events
+// when CH3CC.VALUE = CNTR.VALUE.
+//
+// Set CTL.MODE to UP_PER
+// for edge-aligned PWM generation. Duty cycle is
+// given by:
+//
+// When CH3CC.VALUE <=
+// TARGET.VALUE:
+// Duty cycle =
+// CH3CC.VALUE / ( TARGET.VALUE + 1 ).
+//
+// When CH3CC.VALUE >
+// TARGET.VALUE:
+// Duty cycle = 1.
+//
+// Enabled events are
+// cleared when CH3CC.VALUE = 0 and CNTR.VALUE =
+// 0.
+// CLR_ON_0_TGL_ON_CMP Clear on zero, toggle on compare repeatedly.
+//
+// Channel function
+// sequence:
+// - Clear enabled events
+// when CNTR.VALUE = 0.
+// - Toggle enabled events
+// when CH3CC.VALUE = CNTR.VALUE.
+//
+// Set CTL.MODE to UPDWN_PER
+// for center-aligned PWM generation. Duty cycle
+// is given by:
+//
+// When CH3CC.VALUE <=
+// TARGET.VALUE:
+// Duty cycle = 1 - (
+// CH3CC.VALUE / TARGET.VALUE ).
+//
+// When CH3CC.VALUE >
+// TARGET.VALUE:
+// Duty cycle = 0.
+//
+// Enabled events are set
+// when CH3CC.VALUE = 0 and CNTR.VALUE = 0.
+// SET_ON_CAPT Set on capture repeatedly.
+//
+// Channel function
+// sequence:
+// - Set enabled events on
+// capture event and copy CNTR.VALUE to
+// CH3CC.VALUE.
+//
+// Primary use scenario is
+// to select this function before you start the
+// timer.
+// Follow these steps if you
+// need to select this function while CTL.MODE is
+// different from DIS:
+// - Select this function
+// with no event enable.
+// - Configure CH3CCFG
+// (optional).
+// - Wait for three timer
+// clock periods as defined in PRECFG before you
+// enable events.
+//
+// These steps prevent
+// capture events caused by expired signal values
+// in edge-detection circuit.
+// PER_PULSE_WIDTH_MEAS Period and pulse width measurement.
+//
+// Continuously capture
+// period and pulse width of the signal selected
+// by CH3CCFG.CAPT_SRC relative to the signal edge
+// given by CH3CCFG.EDGE.
+//
+// Set enabled events when
+// CH3CC.VALUE contains signal period and
+// CH3PCC.VALUE contains signal pulse width.
+//
+// Notes:
+// - Make sure that you
+// configure CH3CCFG.CAPT_SRC and CCACT when
+// CTL.MODE equals DIS, then set CTL.MODE to
+// UP_ONCE or UP_PER.
+// - The counter restarts in
+// the selected timer mode when CH3CC.VALUE
+// contains the signal period.
+// - If more than one
+// channel uses this function, the channels will
+// perform this function one at a time. The
+// channel with lowest number has priority and
+// performs the function first. Next measurement
+// starts when current measurement completes
+// successfully or times out. A timeout occurs
+// when counter equals target.
+// - If you want to observe
+// a timeout event configure another channel to
+// SET_ON_CAPT.
+//
+// Signal property
+// requirements:
+// - Signal Period >= 2 * (
+// 1 + PRECFG.CLKDIV ) * timer clock period.
+// - Signal Period <= 65535
+// * (1 + PRECFG.CLKDIV ) * timer clock period.
+// - Signal low and high
+// phase >= (1 + PRECFG.CLKDIV ) * timer clock
+// period.
+// PULSE_ON_CMP_DIS Pulse on compare, and then disable channel.
+//
+// Channel function
+// sequence:
+// - Pulse enabled events
+// when CH3CC.VALUE = CNTR.VALUE.
+// - Disable channel.
+//
+// The event is high for
+// two timer clock periods.
+// TGL_ON_CMP_DIS Toggle on compare, and then disable channel.
+//
+// Channel function
+// sequence:
+// - Toggle enabled events
+// when CH3CC.VALUE = CNTR.VALUE.
+// - Disable channel.
+// SET_ON_CMP_DIS Set on compare, and then disable channel.
+//
+// Channel function
+// sequence:
+// - Set enabled events when
+// CH3CC.VALUE = CNTR.VALUE.
+// - Disable channel.
+// CLR_ON_CMP_DIS Clear on compare, and then disable channel.
+//
+// Channel function
+// sequence:
+// - Clear enabled events
+// when CH3CC.VALUE = CNTR.VALUE.
+// - Disable channel.
+// SET_ON_0_TGL_ON_CMP_DIS Set on zero, toggle on compare, and then disable
+// channel.
+//
+// Channel function
+// sequence:
+// - Set enabled events when
+// CNTR.VALUE = 0.
+// - Toggle enabled events
+// when CH3CC.VALUE = CNTR.VALUE.
+// - Disable channel.
+//
+// Enabled events are
+// cleared when CH3CC.VALUE = 0 and CNTR.VALUE =
+// 0.
+// CLR_ON_0_TGL_ON_CMP_DIS Clear on zero, toggle on compare, and then disable
+// channel.
+//
+// Channel function
+// sequence:
+// - Clear enabled events
+// when CNTR.VALUE = 0.
+// - Toggle enabled events
+// when CH3CC.VALUE = CNTR.VALUE.
+// - Disable channel.
+//
+// Enabled events are set
+// when CH3CC.VALUE = 0 and CNTR.VALUE = 0.
+// SET_ON_CAPT_DIS Set on capture, and then disable channel.
+//
+// Channel function
+// sequence:
+// - Set enabled events on
+// capture event and copy CNTR.VALUE to
+// CH3CC.VALUE.
+// - Disable channel.
+//
+// Primary use scenario is
+// to select this function before you start the
+// timer.
+// Follow these steps if you
+// need to select this function while CTL.MODE is
+// different from DIS:
+// - Set CCACT to
+// SET_ON_CAPT with no event enable.
+// - Configure CH3CCFG
+// (optional).
+// - Wait for three timer
+// clock periods as defined in PRECFG before you
+// set CCACT to SET_ON_CAPT_DIS. Event enable is
+// optional.
+//
+// These steps prevent
+// capture events caused by expired signal values
+// in edge-detection circuit.
+// DIS Disable channel.
+#define AUX_TIMER2_CH3EVCFG_CCACT_W 4
+#define AUX_TIMER2_CH3EVCFG_CCACT_M 0x0000000F
+#define AUX_TIMER2_CH3EVCFG_CCACT_S 0
+#define AUX_TIMER2_CH3EVCFG_CCACT_PULSE_ON_CMP 0x0000000F
+#define AUX_TIMER2_CH3EVCFG_CCACT_TGL_ON_CMP 0x0000000E
+#define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_CMP 0x0000000D
+#define AUX_TIMER2_CH3EVCFG_CCACT_CLR_ON_CMP 0x0000000C
+#define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000B
+#define AUX_TIMER2_CH3EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000A
+#define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_CAPT 0x00000009
+#define AUX_TIMER2_CH3EVCFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008
+#define AUX_TIMER2_CH3EVCFG_CCACT_PULSE_ON_CMP_DIS 0x00000007
+#define AUX_TIMER2_CH3EVCFG_CCACT_TGL_ON_CMP_DIS 0x00000006
+#define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_CMP_DIS 0x00000005
+#define AUX_TIMER2_CH3EVCFG_CCACT_CLR_ON_CMP_DIS 0x00000004
+#define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003
+#define AUX_TIMER2_CH3EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002
+#define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_CAPT_DIS 0x00000001
+#define AUX_TIMER2_CH3EVCFG_CCACT_DIS 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_TIMER2_O_CH3CCFG
+//
+//*****************************************************************************
+// Field: [6:1] CAPT_SRC
+//
+// Select capture signal source from the asynchronous AUX event bus.
+//
+// The selected signal enters the edge-detection circuit. False capture events
+// can occur when:
+// - the edge-detection circuit contains expired signal samples and the circuit
+// is enabled without flush as described in CH3EVCFG
+// - this register is reconfigured while CTL.MODE is different from DIS.
+//
+// You can avoid false capture events. When wanted channel function:
+// - SET_ON_CAPT_DIS, see description for SET_ON_CAPT_DIS in CH3EVCFG.CCACT.
+// - SET_ON_CAPT, see description for SET_ON_CAPT in CH3EVCFG.CCACT.
+// - PER_PULSE_WIDTH_MEAS, see description for PER_PULSE_WIDTH_MEAS in
+// CH3EVCFG.CCACT.
+//
+// If you write a non-enumerated value the behavior is identical to NO_EVENT.
+// The written value is returned when read.
+// ENUMs:
+// NO_EVENT No event.
+// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE
+// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY
+// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL
+// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ
+// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE
+// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N
+// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE
+// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV
+// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV
+// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3
+// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2
+// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1
+// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0
+// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB
+// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA
+// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1
+// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0
+// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV
+// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF
+// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE
+// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE
+// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN
+// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF
+// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD
+// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD
+// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ
+// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY
+// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2
+// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV
+// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31
+// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30
+// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29
+// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28
+// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27
+// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26
+// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25
+// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24
+// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23
+// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22
+// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21
+// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20
+// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19
+// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18
+// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17
+// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16
+// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15
+// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14
+// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13
+// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12
+// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11
+// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10
+// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9
+// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8
+// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7
+// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6
+// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5
+// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4
+// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3
+// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2
+// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1
+// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_W 6
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_M 0x0000007E
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_S 1
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_NO_EVENT 0x0000007E
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000007A
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00000078
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00000076
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_ADC_IRQ 0x00000074
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_ADC_DONE 0x00000072
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_ISRC_RESET_N 0x00000070
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TDC_DONE 0x0000006E
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER0_EV 0x0000006C
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER1_EV 0x0000006A
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER2_EV3 0x00000066
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER2_EV2 0x00000064
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER2_EV1 0x00000062
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER2_EV0 0x00000060
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_COMPB 0x0000005E
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_COMPA 0x0000005C
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_MCU_OBSMUX1 0x0000005A
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_MCU_OBSMUX0 0x00000058
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_MCU_EV 0x00000056
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_ACLK_REF 0x00000054
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_VDDR_RECHARGE 0x00000052
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_MCU_ACTIVE 0x00000050
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_PWR_DWN 0x0000004E
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_SCLK_LF 0x0000004C
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AON_BATMON_TEMP_UPD 0x0000004A
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AON_BATMON_BAT_UPD 0x00000048
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AON_RTC_4KHZ 0x00000046
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AON_RTC_CH2_DLY 0x00000044
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AON_RTC_CH2 0x00000042
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_MANUAL_EV 0x00000040
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO31 0x0000003E
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO30 0x0000003C
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO29 0x0000003A
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO28 0x00000038
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO27 0x00000036
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO26 0x00000034
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO25 0x00000032
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO24 0x00000030
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO23 0x0000002E
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO22 0x0000002C
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO21 0x0000002A
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO20 0x00000028
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO19 0x00000026
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO18 0x00000024
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO17 0x00000022
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO16 0x00000020
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO15 0x0000001E
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO14 0x0000001C
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO13 0x0000001A
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO12 0x00000018
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO11 0x00000016
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO10 0x00000014
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO9 0x00000012
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO8 0x00000010
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO7 0x0000000E
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO6 0x0000000C
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO5 0x0000000A
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO4 0x00000008
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO3 0x00000006
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO2 0x00000004
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO1 0x00000002
+#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO0 0x00000000
+
+// Field: [0] EDGE
+//
+// Edge configuration.
+//
+// Channel captures counter value at selected edge on signal source selected by
+// CAPT_SRC. See CH3EVCFG.CCACT.
+// ENUMs:
+// RISING Capture CNTR.VALUE at rising edge of CAPT_SRC.
+// FALLING Capture CNTR.VALUE at falling edge of CAPT_SRC.
+#define AUX_TIMER2_CH3CCFG_EDGE 0x00000001
+#define AUX_TIMER2_CH3CCFG_EDGE_BITN 0
+#define AUX_TIMER2_CH3CCFG_EDGE_M 0x00000001
+#define AUX_TIMER2_CH3CCFG_EDGE_S 0
+#define AUX_TIMER2_CH3CCFG_EDGE_RISING 0x00000001
+#define AUX_TIMER2_CH3CCFG_EDGE_FALLING 0x00000000
+
+//*****************************************************************************
+//
+// Register: AUX_TIMER2_O_CH3PCC
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Pipeline Capture Compare value.
+//
+// 16-bit user defined pipeline compare value or channel-updated capture value.
+//
+// Compare mode:
+// An update of VALUE will be transferred to CH3CC.VALUE when the next
+// CNTR.VALUE is zero and CTL.MODE is different from DIS. This is useful for
+// PWM generation and prevents jitter on the edges of the generated signal.
+//
+// Capture mode:
+// When CH3EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the
+// width of the low or high phase of the selected signal. This is specified by
+// CH3CCFG.EDGE and CH3CCFG.CAPT_SRC.
+#define AUX_TIMER2_CH3PCC_VALUE_W 16
+#define AUX_TIMER2_CH3PCC_VALUE_M 0x0000FFFF
+#define AUX_TIMER2_CH3PCC_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: AUX_TIMER2_O_CH3CC
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Capture Compare value.
+//
+// 16-bit user defined compare value or channel-updated capture value.
+//
+// Compare mode:
+// VALUE is compared against CNTR.VALUE and an event is generated as specified
+// by CH3EVCFG.CCACT when these are equal.
+//
+// Capture mode:
+// The current counter value is stored in VALUE when a capture event occurs.
+// CH3EVCFG.CCACT determines if VALUE is a signal period or a regular capture
+// value.
+#define AUX_TIMER2_CH3CC_VALUE_W 16
+#define AUX_TIMER2_CH3CC_VALUE_M 0x0000FFFF
+#define AUX_TIMER2_CH3CC_VALUE_S 0
+
+
+#endif // __AUX_TIMER2__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ccfg.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ccfg.h
new file mode 100644
index 0000000..568eca0
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ccfg.h
@@ -0,0 +1,1910 @@
+/******************************************************************************
+* Filename: hw_ccfg_h
+* Revised: 2018-10-19 08:48:09 +0200 (Fri, 19 Oct 2018)
+* Revision: 52957
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_CCFG_H__
+#define __HW_CCFG_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// CCFG component
+//
+//*****************************************************************************
+// Extern LF clock configuration
+#define CCFG_O_EXT_LF_CLK 0x00001FA8
+
+// Mode Configuration 1
+#define CCFG_O_MODE_CONF_1 0x00001FAC
+
+// CCFG Size and Disable Flags
+#define CCFG_O_SIZE_AND_DIS_FLAGS 0x00001FB0
+
+// Mode Configuration 0
+#define CCFG_O_MODE_CONF 0x00001FB4
+
+// Voltage Load 0
+#define CCFG_O_VOLT_LOAD_0 0x00001FB8
+
+// Voltage Load 1
+#define CCFG_O_VOLT_LOAD_1 0x00001FBC
+
+// Real Time Clock Offset
+#define CCFG_O_RTC_OFFSET 0x00001FC0
+
+// Frequency Offset
+#define CCFG_O_FREQ_OFFSET 0x00001FC4
+
+// IEEE MAC Address 0
+#define CCFG_O_IEEE_MAC_0 0x00001FC8
+
+// IEEE MAC Address 1
+#define CCFG_O_IEEE_MAC_1 0x00001FCC
+
+// IEEE BLE Address 0
+#define CCFG_O_IEEE_BLE_0 0x00001FD0
+
+// IEEE BLE Address 1
+#define CCFG_O_IEEE_BLE_1 0x00001FD4
+
+// Bootloader Configuration
+#define CCFG_O_BL_CONFIG 0x00001FD8
+
+// Erase Configuration
+#define CCFG_O_ERASE_CONF 0x00001FDC
+
+// TI Options
+#define CCFG_O_CCFG_TI_OPTIONS 0x00001FE0
+
+// Test Access Points Enable 0
+#define CCFG_O_CCFG_TAP_DAP_0 0x00001FE4
+
+// Test Access Points Enable 1
+#define CCFG_O_CCFG_TAP_DAP_1 0x00001FE8
+
+// Image Valid
+#define CCFG_O_IMAGE_VALID_CONF 0x00001FEC
+
+// Protect Sectors 0-31
+#define CCFG_O_CCFG_PROT_31_0 0x00001FF0
+
+// Protect Sectors 32-63
+#define CCFG_O_CCFG_PROT_63_32 0x00001FF4
+
+// Protect Sectors 64-95
+#define CCFG_O_CCFG_PROT_95_64 0x00001FF8
+
+// Protect Sectors 96-127
+#define CCFG_O_CCFG_PROT_127_96 0x00001FFC
+
+//*****************************************************************************
+//
+// Register: CCFG_O_EXT_LF_CLK
+//
+//*****************************************************************************
+// Field: [31:24] DIO
+//
+// Unsigned integer, selecting the DIO to supply external 32kHz clock as
+// SCLK_LF when MODE_CONF.SCLK_LF_OPTION is set to EXTERNAL. The selected DIO
+// will be marked as reserved by the pin driver (TI-RTOS environment) and hence
+// not selectable for other usage.
+#define CCFG_EXT_LF_CLK_DIO_W 8
+#define CCFG_EXT_LF_CLK_DIO_M 0xFF000000
+#define CCFG_EXT_LF_CLK_DIO_S 24
+
+// Field: [23:0] RTC_INCREMENT
+//
+// Unsigned integer, defining the input frequency of the external clock and is
+// written to AON_RTC:SUBSECINC.VALUEINC. Defined as follows:
+// EXT_LF_CLK.RTC_INCREMENT = 2^38/InputClockFrequency in Hertz (e.g.:
+// RTC_INCREMENT=0x800000 for InputClockFrequency=32768 Hz)
+#define CCFG_EXT_LF_CLK_RTC_INCREMENT_W 24
+#define CCFG_EXT_LF_CLK_RTC_INCREMENT_M 0x00FFFFFF
+#define CCFG_EXT_LF_CLK_RTC_INCREMENT_S 0
+
+//*****************************************************************************
+//
+// Register: CCFG_O_MODE_CONF_1
+//
+//*****************************************************************************
+// Field: [23:20] ALT_DCDC_VMIN
+//
+// Minimum voltage for when DC/DC should be used if alternate DC/DC setting is
+// enabled (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0).
+// Voltage = (28 + ALT_DCDC_VMIN) / 16.
+// 0: 1.75V
+// 1: 1.8125V
+// ...
+// 14: 2.625V
+// 15: 2.6875V
+//
+// NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must
+// be called regularly to apply this field (handled automatically if using TI
+// RTOS!).
+#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_W 4
+#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M 0x00F00000
+#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S 20
+
+// Field: [19] ALT_DCDC_DITHER_EN
+//
+// Enable DC/DC dithering if alternate DC/DC setting is enabled
+// (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0).
+// 0: Dither disable
+// 1: Dither enable
+#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x00080000
+#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_BITN 19
+#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_M 0x00080000
+#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_S 19
+
+// Field: [18:16] ALT_DCDC_IPEAK
+//
+// Inductor peak current if alternate DC/DC setting is enabled
+// (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). Assuming 10uH external
+// inductor!
+// Peak current = 31 + ( 4 * ALT_DCDC_IPEAK ) :
+// 0: 31mA (min)
+// ...
+// 4: 47mA
+// ...
+// 7: 59mA (max)
+#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_W 3
+#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_M 0x00070000
+#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S 16
+
+// Field: [15:12] DELTA_IBIAS_INIT
+//
+// Signed delta value for IBIAS_INIT. Delta value only applies if
+// SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0.
+// See FCFG1:AMPCOMP_CTRL1.IBIAS_INIT
+#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W 4
+#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_M 0x0000F000
+#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S 12
+
+// Field: [11:8] DELTA_IBIAS_OFFSET
+//
+// Signed delta value for IBIAS_OFFSET. Delta value only applies if
+// SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0.
+// See FCFG1:AMPCOMP_CTRL1.IBIAS_OFFSET
+#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W 4
+#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_M 0x00000F00
+#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S 8
+
+// Field: [7:0] XOSC_MAX_START
+//
+// Unsigned value of maximum XOSC startup time (worst case) in units of 100us.
+// Value only applies if SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0.
+#define CCFG_MODE_CONF_1_XOSC_MAX_START_W 8
+#define CCFG_MODE_CONF_1_XOSC_MAX_START_M 0x000000FF
+#define CCFG_MODE_CONF_1_XOSC_MAX_START_S 0
+
+//*****************************************************************************
+//
+// Register: CCFG_O_SIZE_AND_DIS_FLAGS
+//
+//*****************************************************************************
+// Field: [31:16] SIZE_OF_CCFG
+//
+// Total size of CCFG in bytes.
+#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_W 16
+#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_M 0xFFFF0000
+#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_S 16
+
+// Field: [15:4] DISABLE_FLAGS
+//
+// Reserved for future use. Software should not rely on the value of a
+// reserved. Writing any other value than the reset/default value may result in
+// undefined behavior.
+#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_W 12
+#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M 0x0000FFF0
+#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S 4
+
+// Field: [3] DIS_TCXO
+//
+// Disable TCXO.
+// 0: TCXO functionality enabled.
+// 1: TCXO functionality disabled.
+// Note:
+// An external TCXO is required if DIS_TCXO = 0.
+#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x00000008
+#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_BITN 3
+#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_M 0x00000008
+#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_S 3
+
+// Field: [2] DIS_GPRAM
+//
+// Disable GPRAM (or use the 8K VIMS RAM as CACHE RAM).
+// 0: GPRAM is enabled and hence CACHE disabled.
+// 1: GPRAM is disabled and instead CACHE is enabled (default).
+// Notes:
+// - Disabling CACHE will reduce CPU execution speed (up to 60%).
+// - GPRAM is 8 K-bytes in size and located at 0x11000000-0x11001FFF if
+// enabled.
+// See:
+// VIMS:CTL.MODE
+#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x00000004
+#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_BITN 2
+#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M 0x00000004
+#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S 2
+
+// Field: [1] DIS_ALT_DCDC_SETTING
+//
+// Disable alternate DC/DC settings.
+// 0: Enable alternate DC/DC settings.
+// 1: Disable alternate DC/DC settings.
+// See:
+// MODE_CONF_1.ALT_DCDC_VMIN
+// MODE_CONF_1.ALT_DCDC_DITHER_EN
+// MODE_CONF_1.ALT_DCDC_IPEAK
+//
+// NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must
+// be called regularly to apply this field (handled automatically if using TI
+// RTOS!).
+#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x00000002
+#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_BITN 1
+#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_M 0x00000002
+#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_S 1
+
+// Field: [0] DIS_XOSC_OVR
+//
+// Disable XOSC override functionality.
+// 0: Enable XOSC override functionality.
+// 1: Disable XOSC override functionality.
+// See:
+// MODE_CONF_1.DELTA_IBIAS_INIT
+// MODE_CONF_1.DELTA_IBIAS_OFFSET
+// MODE_CONF_1.XOSC_MAX_START
+#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x00000001
+#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_BITN 0
+#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M 0x00000001
+#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_S 0
+
+//*****************************************************************************
+//
+// Register: CCFG_O_MODE_CONF
+//
+//*****************************************************************************
+// Field: [31:28] VDDR_TRIM_SLEEP_DELTA
+//
+// Signed delta value to apply to the
+// VDDR_TRIM_SLEEP target, minus one. See FCFG1:VOLT_TRIM.VDDR_TRIM_SLEEP_H.
+// 0x8 (-8) : Delta = -7
+// ...
+// 0xF (-1) : Delta = 0
+// 0x0 (0) : Delta = +1
+// ...
+// 0x7 (7) : Delta = +8
+#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W 4
+#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_M 0xF0000000
+#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S 28
+
+// Field: [27] DCDC_RECHARGE
+//
+// DC/DC during recharge in powerdown.
+// 0: Use the DC/DC during recharge in powerdown.
+// 1: Do not use the DC/DC during recharge in powerdown (default).
+//
+// NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must
+// be called regularly to apply this field (handled automatically if using TI
+// RTOS!).
+#define CCFG_MODE_CONF_DCDC_RECHARGE 0x08000000
+#define CCFG_MODE_CONF_DCDC_RECHARGE_BITN 27
+#define CCFG_MODE_CONF_DCDC_RECHARGE_M 0x08000000
+#define CCFG_MODE_CONF_DCDC_RECHARGE_S 27
+
+// Field: [26] DCDC_ACTIVE
+//
+// DC/DC in active mode.
+// 0: Use the DC/DC during active mode.
+// 1: Do not use the DC/DC during active mode (default).
+//
+// NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must
+// be called regularly to apply this field (handled automatically if using TI
+// RTOS!).
+#define CCFG_MODE_CONF_DCDC_ACTIVE 0x04000000
+#define CCFG_MODE_CONF_DCDC_ACTIVE_BITN 26
+#define CCFG_MODE_CONF_DCDC_ACTIVE_M 0x04000000
+#define CCFG_MODE_CONF_DCDC_ACTIVE_S 26
+
+// Field: [25] VDDR_EXT_LOAD
+//
+// Reserved for future use. Software should not rely on the value of a
+// reserved. Writing any other value than the reset/default value may result in
+// undefined behavior.
+#define CCFG_MODE_CONF_VDDR_EXT_LOAD 0x02000000
+#define CCFG_MODE_CONF_VDDR_EXT_LOAD_BITN 25
+#define CCFG_MODE_CONF_VDDR_EXT_LOAD_M 0x02000000
+#define CCFG_MODE_CONF_VDDR_EXT_LOAD_S 25
+
+// Field: [24] VDDS_BOD_LEVEL
+//
+// VDDS BOD level.
+// 0: VDDS BOD level is 2.0V (necessary for external load mode, or for maximum
+// PA output power on CC13xx).
+// 1: VDDS BOD level is 1.8V (or 1.65V for external regulator mode) (default).
+#define CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x01000000
+#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_BITN 24
+#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_M 0x01000000
+#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_S 24
+
+// Field: [23:22] SCLK_LF_OPTION
+//
+// Select source for SCLK_LF.
+// ENUMs:
+// RCOSC_LF Low frequency RCOSC (default)
+// XOSC_LF 32.768kHz low frequency XOSC
+// EXTERNAL_LF External low frequency clock on DIO defined by
+// EXT_LF_CLK.DIO. The RTC tick speed
+// AON_RTC:SUBSECINC is updated to
+// EXT_LF_CLK.RTC_INCREMENT (done in the
+// trimDevice() xxWare boot function). External
+// clock must always be running when the chip is
+// in standby for VDDR recharge timing.
+// XOSC_HF_DLF 31.25kHz clock derived from 24MHz XOSC (dividing
+// by 768 in HW). The RTC tick speed
+// [AON_RTC.SUBSECINC.*] is updated to 0x8637BD,
+// corresponding to a 31.25kHz clock (done in the
+// trimDevice() xxWare boot function). Standby
+// power mode is not supported when using this
+// clock source.
+#define CCFG_MODE_CONF_SCLK_LF_OPTION_W 2
+#define CCFG_MODE_CONF_SCLK_LF_OPTION_M 0x00C00000
+#define CCFG_MODE_CONF_SCLK_LF_OPTION_S 22
+#define CCFG_MODE_CONF_SCLK_LF_OPTION_RCOSC_LF 0x00C00000
+#define CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_LF 0x00800000
+#define CCFG_MODE_CONF_SCLK_LF_OPTION_EXTERNAL_LF 0x00400000
+#define CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_HF_DLF 0x00000000
+
+// Field: [21] VDDR_TRIM_SLEEP_TC
+//
+// 0x1: VDDR_TRIM_SLEEP_DELTA is not temperature compensated
+// 0x0: RTOS/driver temperature compensates VDDR_TRIM_SLEEP_DELTA every time
+// standby mode is entered. This improves low-temperature RCOSC_LF frequency
+// stability in standby mode.
+//
+// When temperature compensation is performed, the delta is calculates this
+// way:
+// Delta = max (delta, min(8, floor(62-temp)/8))
+// Here, delta is given by VDDR_TRIM_SLEEP_DELTA, and temp is the current
+// temperature in degrees C.
+#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x00200000
+#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_BITN 21
+#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_M 0x00200000
+#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_S 21
+
+// Field: [20] RTC_COMP
+//
+// Reserved for future use. Software should not rely on the value of a
+// reserved. Writing any other value than the reset/default value may result in
+// undefined behavior.
+#define CCFG_MODE_CONF_RTC_COMP 0x00100000
+#define CCFG_MODE_CONF_RTC_COMP_BITN 20
+#define CCFG_MODE_CONF_RTC_COMP_M 0x00100000
+#define CCFG_MODE_CONF_RTC_COMP_S 20
+
+// Field: [19:18] XOSC_FREQ
+//
+// Selects high precision HF oscillator (activated when using the radio).
+// ENUMs:
+// 24M 24 MHz XOSC_HF
+// 48M 48 MHz XOSC_HF
+// HPOSC HPOSC
+#define CCFG_MODE_CONF_XOSC_FREQ_W 2
+#define CCFG_MODE_CONF_XOSC_FREQ_M 0x000C0000
+#define CCFG_MODE_CONF_XOSC_FREQ_S 18
+#define CCFG_MODE_CONF_XOSC_FREQ_24M 0x000C0000
+#define CCFG_MODE_CONF_XOSC_FREQ_48M 0x00080000
+#define CCFG_MODE_CONF_XOSC_FREQ_HPOSC 0x00040000
+
+// Field: [17] XOSC_CAP_MOD
+//
+// Enable modification (delta) to XOSC cap-array. Value specified in
+// XOSC_CAPARRAY_DELTA.
+// 0: Apply cap-array delta
+// 1: Do not apply cap-array delta (default)
+#define CCFG_MODE_CONF_XOSC_CAP_MOD 0x00020000
+#define CCFG_MODE_CONF_XOSC_CAP_MOD_BITN 17
+#define CCFG_MODE_CONF_XOSC_CAP_MOD_M 0x00020000
+#define CCFG_MODE_CONF_XOSC_CAP_MOD_S 17
+
+// Field: [16] HF_COMP
+//
+// Reserved for future use. Software should not rely on the value of a
+// reserved. Writing any other value than the reset/default value may result in
+// undefined behavior.
+#define CCFG_MODE_CONF_HF_COMP 0x00010000
+#define CCFG_MODE_CONF_HF_COMP_BITN 16
+#define CCFG_MODE_CONF_HF_COMP_M 0x00010000
+#define CCFG_MODE_CONF_HF_COMP_S 16
+
+// Field: [15:8] XOSC_CAPARRAY_DELTA
+//
+// Signed 8-bit value, directly modifying trimmed XOSC cap-array step value.
+// Enabled by XOSC_CAP_MOD.
+#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W 8
+#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M 0x0000FF00
+#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S 8
+
+// Field: [7:0] VDDR_CAP
+//
+// Unsigned 8-bit integer, representing the minimum decoupling capacitance
+// (worst case) on VDDR, in units of 100nF. This should take into account
+// capacitor tolerance and voltage dependent capacitance variation. This bit
+// affects the recharge period calculation when going into powerdown or
+// standby.
+//
+// NOTE! If using the following functions this field must be configured (used
+// by TI RTOS):
+// SysCtrlSetRechargeBeforePowerDown() SysCtrlAdjustRechargeAfterPowerDown()
+#define CCFG_MODE_CONF_VDDR_CAP_W 8
+#define CCFG_MODE_CONF_VDDR_CAP_M 0x000000FF
+#define CCFG_MODE_CONF_VDDR_CAP_S 0
+
+//*****************************************************************************
+//
+// Register: CCFG_O_VOLT_LOAD_0
+//
+//*****************************************************************************
+// Field: [31:24] VDDR_EXT_TP45
+//
+// Reserved for future use. Software should not rely on the value of a
+// reserved. Writing any other value than the reset/default value may result in
+// undefined behavior.
+#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_W 8
+#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_M 0xFF000000
+#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_S 24
+
+// Field: [23:16] VDDR_EXT_TP25
+//
+// Reserved for future use. Software should not rely on the value of a
+// reserved. Writing any other value than the reset/default value may result in
+// undefined behavior.
+#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_W 8
+#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_M 0x00FF0000
+#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_S 16
+
+// Field: [15:8] VDDR_EXT_TP5
+//
+// Reserved for future use. Software should not rely on the value of a
+// reserved. Writing any other value than the reset/default value may result in
+// undefined behavior.
+#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_W 8
+#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_M 0x0000FF00
+#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_S 8
+
+// Field: [7:0] VDDR_EXT_TM15
+//
+// Reserved for future use. Software should not rely on the value of a
+// reserved. Writing any other value than the reset/default value may result in
+// undefined behavior.
+#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_W 8
+#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_M 0x000000FF
+#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_S 0
+
+//*****************************************************************************
+//
+// Register: CCFG_O_VOLT_LOAD_1
+//
+//*****************************************************************************
+// Field: [31:24] VDDR_EXT_TP125
+//
+// Reserved for future use. Software should not rely on the value of a
+// reserved. Writing any other value than the reset/default value may result in
+// undefined behavior.
+#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_W 8
+#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_M 0xFF000000
+#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_S 24
+
+// Field: [23:16] VDDR_EXT_TP105
+//
+// Reserved for future use. Software should not rely on the value of a
+// reserved. Writing any other value than the reset/default value may result in
+// undefined behavior.
+#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_W 8
+#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_M 0x00FF0000
+#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_S 16
+
+// Field: [15:8] VDDR_EXT_TP85
+//
+// Reserved for future use. Software should not rely on the value of a
+// reserved. Writing any other value than the reset/default value may result in
+// undefined behavior.
+#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_W 8
+#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_M 0x0000FF00
+#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_S 8
+
+// Field: [7:0] VDDR_EXT_TP65
+//
+// Reserved for future use. Software should not rely on the value of a
+// reserved. Writing any other value than the reset/default value may result in
+// undefined behavior.
+#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_W 8
+#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_M 0x000000FF
+#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_S 0
+
+//*****************************************************************************
+//
+// Register: CCFG_O_RTC_OFFSET
+//
+//*****************************************************************************
+// Field: [31:16] RTC_COMP_P0
+//
+// Reserved for future use. Software should not rely on the value of a
+// reserved. Writing any other value than the reset/default value may result in
+// undefined behavior.
+#define CCFG_RTC_OFFSET_RTC_COMP_P0_W 16
+#define CCFG_RTC_OFFSET_RTC_COMP_P0_M 0xFFFF0000
+#define CCFG_RTC_OFFSET_RTC_COMP_P0_S 16
+
+// Field: [15:8] RTC_COMP_P1
+//
+// Reserved for future use. Software should not rely on the value of a
+// reserved. Writing any other value than the reset/default value may result in
+// undefined behavior.
+#define CCFG_RTC_OFFSET_RTC_COMP_P1_W 8
+#define CCFG_RTC_OFFSET_RTC_COMP_P1_M 0x0000FF00
+#define CCFG_RTC_OFFSET_RTC_COMP_P1_S 8
+
+// Field: [7:0] RTC_COMP_P2
+//
+// Reserved for future use. Software should not rely on the value of a
+// reserved. Writing any other value than the reset/default value may result in
+// undefined behavior.
+#define CCFG_RTC_OFFSET_RTC_COMP_P2_W 8
+#define CCFG_RTC_OFFSET_RTC_COMP_P2_M 0x000000FF
+#define CCFG_RTC_OFFSET_RTC_COMP_P2_S 0
+
+//*****************************************************************************
+//
+// Register: CCFG_O_FREQ_OFFSET
+//
+//*****************************************************************************
+// Field: [31:16] HF_COMP_P0
+//
+// Reserved for future use. Software should not rely on the value of a
+// reserved. Writing any other value than the reset/default value may result in
+// undefined behavior.
+#define CCFG_FREQ_OFFSET_HF_COMP_P0_W 16
+#define CCFG_FREQ_OFFSET_HF_COMP_P0_M 0xFFFF0000
+#define CCFG_FREQ_OFFSET_HF_COMP_P0_S 16
+
+// Field: [15:8] HF_COMP_P1
+//
+// Reserved for future use. Software should not rely on the value of a
+// reserved. Writing any other value than the reset/default value may result in
+// undefined behavior.
+#define CCFG_FREQ_OFFSET_HF_COMP_P1_W 8
+#define CCFG_FREQ_OFFSET_HF_COMP_P1_M 0x0000FF00
+#define CCFG_FREQ_OFFSET_HF_COMP_P1_S 8
+
+// Field: [7:0] HF_COMP_P2
+//
+// Reserved for future use. Software should not rely on the value of a
+// reserved. Writing any other value than the reset/default value may result in
+// undefined behavior.
+#define CCFG_FREQ_OFFSET_HF_COMP_P2_W 8
+#define CCFG_FREQ_OFFSET_HF_COMP_P2_M 0x000000FF
+#define CCFG_FREQ_OFFSET_HF_COMP_P2_S 0
+
+//*****************************************************************************
+//
+// Register: CCFG_O_IEEE_MAC_0
+//
+//*****************************************************************************
+// Field: [31:0] ADDR
+//
+// Bits[31:0] of the 64-bits custom IEEE MAC address.
+// If different from 0xFFFFFFFF then the value of this field is applied;
+// otherwise use value from FCFG.
+#define CCFG_IEEE_MAC_0_ADDR_W 32
+#define CCFG_IEEE_MAC_0_ADDR_M 0xFFFFFFFF
+#define CCFG_IEEE_MAC_0_ADDR_S 0
+
+//*****************************************************************************
+//
+// Register: CCFG_O_IEEE_MAC_1
+//
+//*****************************************************************************
+// Field: [31:0] ADDR
+//
+// Bits[63:32] of the 64-bits custom IEEE MAC address.
+// If different from 0xFFFFFFFF then the value of this field is applied;
+// otherwise use value from FCFG.
+#define CCFG_IEEE_MAC_1_ADDR_W 32
+#define CCFG_IEEE_MAC_1_ADDR_M 0xFFFFFFFF
+#define CCFG_IEEE_MAC_1_ADDR_S 0
+
+//*****************************************************************************
+//
+// Register: CCFG_O_IEEE_BLE_0
+//
+//*****************************************************************************
+// Field: [31:0] ADDR
+//
+// Bits[31:0] of the 64-bits custom IEEE BLE address.
+// If different from 0xFFFFFFFF then the value of this field is applied;
+// otherwise use value from FCFG.
+#define CCFG_IEEE_BLE_0_ADDR_W 32
+#define CCFG_IEEE_BLE_0_ADDR_M 0xFFFFFFFF
+#define CCFG_IEEE_BLE_0_ADDR_S 0
+
+//*****************************************************************************
+//
+// Register: CCFG_O_IEEE_BLE_1
+//
+//*****************************************************************************
+// Field: [31:0] ADDR
+//
+// Bits[63:32] of the 64-bits custom IEEE BLE address.
+// If different from 0xFFFFFFFF then the value of this field is applied;
+// otherwise use value from FCFG.
+#define CCFG_IEEE_BLE_1_ADDR_W 32
+#define CCFG_IEEE_BLE_1_ADDR_M 0xFFFFFFFF
+#define CCFG_IEEE_BLE_1_ADDR_S 0
+
+//*****************************************************************************
+//
+// Register: CCFG_O_BL_CONFIG
+//
+//*****************************************************************************
+// Field: [31:24] BOOTLOADER_ENABLE
+//
+// Bootloader enable. Boot loader can be accessed if
+// IMAGE_VALID_CONF.IMAGE_VALID is non-zero or BL_ENABLE is enabled (and
+// conditions for boot loader backdoor are met).
+// 0xC5: Boot loader is enabled.
+// Any other value: Boot loader is disabled.
+#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_W 8
+#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_M 0xFF000000
+#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_S 24
+
+// Field: [16] BL_LEVEL
+//
+// Sets the active level of the selected DIO number BL_PIN_NUMBER if boot
+// loader backdoor is enabled by the BL_ENABLE field.
+// 0: Active low.
+// 1: Active high.
+#define CCFG_BL_CONFIG_BL_LEVEL 0x00010000
+#define CCFG_BL_CONFIG_BL_LEVEL_BITN 16
+#define CCFG_BL_CONFIG_BL_LEVEL_M 0x00010000
+#define CCFG_BL_CONFIG_BL_LEVEL_S 16
+
+// Field: [15:8] BL_PIN_NUMBER
+//
+// DIO number that is level checked if the boot loader backdoor is enabled by
+// the BL_ENABLE field.
+#define CCFG_BL_CONFIG_BL_PIN_NUMBER_W 8
+#define CCFG_BL_CONFIG_BL_PIN_NUMBER_M 0x0000FF00
+#define CCFG_BL_CONFIG_BL_PIN_NUMBER_S 8
+
+// Field: [7:0] BL_ENABLE
+//
+// Enables the boot loader backdoor.
+// 0xC5: Boot loader backdoor is enabled.
+// Any other value: Boot loader backdoor is disabled.
+//
+// NOTE! Boot loader must be enabled (see BOOTLOADER_ENABLE) if boot loader
+// backdoor is enabled.
+#define CCFG_BL_CONFIG_BL_ENABLE_W 8
+#define CCFG_BL_CONFIG_BL_ENABLE_M 0x000000FF
+#define CCFG_BL_CONFIG_BL_ENABLE_S 0
+
+//*****************************************************************************
+//
+// Register: CCFG_O_ERASE_CONF
+//
+//*****************************************************************************
+// Field: [8] CHIP_ERASE_DIS_N
+//
+// Chip erase.
+// This bit controls if a chip erase requested through the JTAG WUC TAP will be
+// ignored in a following boot caused by a reset of the MCU VD.
+// A successful chip erase operation will force the content of the flash main
+// bank back to the state as it was when delivered by TI.
+// 0: Disable. Any chip erase request detected during boot will be ignored.
+// 1: Enable. Any chip erase request detected during boot will be performed by
+// the boot FW.
+#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x00000100
+#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_BITN 8
+#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_M 0x00000100
+#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_S 8
+
+// Field: [0] BANK_ERASE_DIS_N
+//
+// Bank erase.
+// This bit controls if the ROM serial boot loader will accept a received Bank
+// Erase command (COMMAND_BANK_ERASE).
+// A successful Bank Erase operation will erase all main bank sectors not
+// protected by write protect configuration bits in CCFG.
+// 0: Disable the boot loader bank erase function.
+// 1: Enable the boot loader bank erase function.
+#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x00000001
+#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_BITN 0
+#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_M 0x00000001
+#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_S 0
+
+//*****************************************************************************
+//
+// Register: CCFG_O_CCFG_TI_OPTIONS
+//
+//*****************************************************************************
+// Field: [7:0] TI_FA_ENABLE
+//
+// TI Failure Analysis.
+// 0xC5: Enable the functionality of unlocking the TI FA (TI Failure Analysis)
+// option with the unlock code.
+// All other values: Disable the functionality of unlocking the TI FA option
+// with the unlock code.
+#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_W 8
+#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_M 0x000000FF
+#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_S 0
+
+//*****************************************************************************
+//
+// Register: CCFG_O_CCFG_TAP_DAP_0
+//
+//*****************************************************************************
+// Field: [23:16] CPU_DAP_ENABLE
+//
+// Enable CPU DAP.
+// 0xC5: Main CPU DAP access is enabled during power-up/system-reset by ROM
+// boot FW.
+// Any other value: Main CPU DAP access will remain disabled out of
+// power-up/system-reset.
+#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_W 8
+#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_M 0x00FF0000
+#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_S 16
+
+// Field: [15:8] PWRPROF_TAP_ENABLE
+//
+// Enable PWRPROF TAP.
+// 0xC5: PWRPROF TAP access is enabled during power-up/system-reset by ROM boot
+// FW if enabled by corresponding configuration value in FCFG1 defined by TI.
+// Any other value: PWRPROF TAP access will remain disabled out of
+// power-up/system-reset.
+#define CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_W 8
+#define CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_M 0x0000FF00
+#define CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_S 8
+
+// Field: [7:0] TEST_TAP_ENABLE
+//
+// Enable Test TAP.
+// 0xC5: TEST TAP access is enabled during power-up/system-reset by ROM boot FW
+// if enabled by corresponding configuration value in FCFG1 defined by TI.
+// Any other value: TEST TAP access will remain disabled out of
+// power-up/system-reset.
+#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_W 8
+#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_M 0x000000FF
+#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_S 0
+
+//*****************************************************************************
+//
+// Register: CCFG_O_CCFG_TAP_DAP_1
+//
+//*****************************************************************************
+// Field: [23:16] PBIST2_TAP_ENABLE
+//
+// Enable PBIST2 TAP.
+// 0xC5: PBIST2 TAP access is enabled during power-up/system-reset by ROM boot
+// FW if enabled by corresponding configuration value in FCFG1 defined by TI.
+// Any other value: PBIST2 TAP access will remain disabled out of
+// power-up/system-reset.
+#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_W 8
+#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_M 0x00FF0000
+#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_S 16
+
+// Field: [15:8] PBIST1_TAP_ENABLE
+//
+// Enable PBIST1 TAP.
+// 0xC5: PBIST1 TAP access is enabled during power-up/system-reset by ROM boot
+// FW if enabled by corresponding configuration value in FCFG1 defined by TI.
+// Any other value: PBIST1 TAP access will remain disabled out of
+// power-up/system-reset.
+#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_W 8
+#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_M 0x0000FF00
+#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_S 8
+
+// Field: [7:0] AON_TAP_ENABLE
+//
+// Enable AON TAP
+// 0xC5: AON TAP access is enabled during power-up/system-reset by ROM boot FW
+// if enabled by corresponding configuration value in FCFG1 defined by TI.
+// Any other value: AON TAP access will remain disabled out of
+// power-up/system-reset.
+#define CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE_W 8
+#define CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE_M 0x000000FF
+#define CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE_S 0
+
+//*****************************************************************************
+//
+// Register: CCFG_O_IMAGE_VALID_CONF
+//
+//*****************************************************************************
+// Field: [31:0] IMAGE_VALID
+//
+// This field must have the address value of the start of the flash vector
+// table in order to enable the boot FW in ROM to transfer control to a flash
+// image.
+// Any illegal vector table start address value will force the boot FW in ROM
+// to transfer control to the serial boot loader in ROM.
+#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_W 32
+#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_M 0xFFFFFFFF
+#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_S 0
+
+//*****************************************************************************
+//
+// Register: CCFG_O_CCFG_PROT_31_0
+//
+//*****************************************************************************
+// Field: [31] WRT_PROT_SEC_31
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31 0x80000000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_BITN 31
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_M 0x80000000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_S 31
+
+// Field: [30] WRT_PROT_SEC_30
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30 0x40000000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_BITN 30
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_M 0x40000000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_S 30
+
+// Field: [29] WRT_PROT_SEC_29
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29 0x20000000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_BITN 29
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_M 0x20000000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_S 29
+
+// Field: [28] WRT_PROT_SEC_28
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28 0x10000000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_BITN 28
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_M 0x10000000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_S 28
+
+// Field: [27] WRT_PROT_SEC_27
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27 0x08000000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_BITN 27
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_M 0x08000000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_S 27
+
+// Field: [26] WRT_PROT_SEC_26
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26 0x04000000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_BITN 26
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_M 0x04000000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_S 26
+
+// Field: [25] WRT_PROT_SEC_25
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25 0x02000000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_BITN 25
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_M 0x02000000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_S 25
+
+// Field: [24] WRT_PROT_SEC_24
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24 0x01000000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_BITN 24
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_M 0x01000000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_S 24
+
+// Field: [23] WRT_PROT_SEC_23
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23 0x00800000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_BITN 23
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_M 0x00800000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_S 23
+
+// Field: [22] WRT_PROT_SEC_22
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22 0x00400000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_BITN 22
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_M 0x00400000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_S 22
+
+// Field: [21] WRT_PROT_SEC_21
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21 0x00200000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_BITN 21
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_M 0x00200000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_S 21
+
+// Field: [20] WRT_PROT_SEC_20
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20 0x00100000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_BITN 20
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_M 0x00100000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_S 20
+
+// Field: [19] WRT_PROT_SEC_19
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19 0x00080000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_BITN 19
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_M 0x00080000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_S 19
+
+// Field: [18] WRT_PROT_SEC_18
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18 0x00040000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_BITN 18
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_M 0x00040000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_S 18
+
+// Field: [17] WRT_PROT_SEC_17
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17 0x00020000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_BITN 17
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_M 0x00020000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_S 17
+
+// Field: [16] WRT_PROT_SEC_16
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16 0x00010000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_BITN 16
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_M 0x00010000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_S 16
+
+// Field: [15] WRT_PROT_SEC_15
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15 0x00008000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_BITN 15
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_M 0x00008000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_S 15
+
+// Field: [14] WRT_PROT_SEC_14
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14 0x00004000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_BITN 14
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_M 0x00004000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_S 14
+
+// Field: [13] WRT_PROT_SEC_13
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13 0x00002000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_BITN 13
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_M 0x00002000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_S 13
+
+// Field: [12] WRT_PROT_SEC_12
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12 0x00001000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_BITN 12
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_M 0x00001000
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_S 12
+
+// Field: [11] WRT_PROT_SEC_11
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11 0x00000800
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_BITN 11
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_M 0x00000800
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_S 11
+
+// Field: [10] WRT_PROT_SEC_10
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10 0x00000400
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_BITN 10
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_M 0x00000400
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_S 10
+
+// Field: [9] WRT_PROT_SEC_9
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9 0x00000200
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_BITN 9
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_M 0x00000200
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_S 9
+
+// Field: [8] WRT_PROT_SEC_8
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8 0x00000100
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_BITN 8
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_M 0x00000100
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_S 8
+
+// Field: [7] WRT_PROT_SEC_7
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7 0x00000080
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_BITN 7
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_M 0x00000080
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_S 7
+
+// Field: [6] WRT_PROT_SEC_6
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6 0x00000040
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_BITN 6
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_M 0x00000040
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_S 6
+
+// Field: [5] WRT_PROT_SEC_5
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5 0x00000020
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_BITN 5
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_M 0x00000020
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_S 5
+
+// Field: [4] WRT_PROT_SEC_4
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4 0x00000010
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_BITN 4
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_M 0x00000010
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_S 4
+
+// Field: [3] WRT_PROT_SEC_3
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3 0x00000008
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_BITN 3
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_M 0x00000008
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_S 3
+
+// Field: [2] WRT_PROT_SEC_2
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2 0x00000004
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_BITN 2
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_M 0x00000004
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_S 2
+
+// Field: [1] WRT_PROT_SEC_1
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1 0x00000002
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_BITN 1
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_M 0x00000002
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_S 1
+
+// Field: [0] WRT_PROT_SEC_0
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0 0x00000001
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_BITN 0
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_M 0x00000001
+#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_S 0
+
+//*****************************************************************************
+//
+// Register: CCFG_O_CCFG_PROT_63_32
+//
+//*****************************************************************************
+// Field: [31] WRT_PROT_SEC_63
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63 0x80000000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_BITN 31
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_M 0x80000000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_S 31
+
+// Field: [30] WRT_PROT_SEC_62
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62 0x40000000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_BITN 30
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_M 0x40000000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_S 30
+
+// Field: [29] WRT_PROT_SEC_61
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61 0x20000000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_BITN 29
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_M 0x20000000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_S 29
+
+// Field: [28] WRT_PROT_SEC_60
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60 0x10000000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_BITN 28
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_M 0x10000000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_S 28
+
+// Field: [27] WRT_PROT_SEC_59
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59 0x08000000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_BITN 27
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_M 0x08000000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_S 27
+
+// Field: [26] WRT_PROT_SEC_58
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58 0x04000000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_BITN 26
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_M 0x04000000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_S 26
+
+// Field: [25] WRT_PROT_SEC_57
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57 0x02000000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_BITN 25
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_M 0x02000000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_S 25
+
+// Field: [24] WRT_PROT_SEC_56
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56 0x01000000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_BITN 24
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_M 0x01000000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_S 24
+
+// Field: [23] WRT_PROT_SEC_55
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55 0x00800000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_BITN 23
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_M 0x00800000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_S 23
+
+// Field: [22] WRT_PROT_SEC_54
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54 0x00400000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_BITN 22
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_M 0x00400000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_S 22
+
+// Field: [21] WRT_PROT_SEC_53
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53 0x00200000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_BITN 21
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_M 0x00200000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_S 21
+
+// Field: [20] WRT_PROT_SEC_52
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52 0x00100000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_BITN 20
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_M 0x00100000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_S 20
+
+// Field: [19] WRT_PROT_SEC_51
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51 0x00080000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_BITN 19
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_M 0x00080000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_S 19
+
+// Field: [18] WRT_PROT_SEC_50
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50 0x00040000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_BITN 18
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_M 0x00040000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_S 18
+
+// Field: [17] WRT_PROT_SEC_49
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49 0x00020000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_BITN 17
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_M 0x00020000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_S 17
+
+// Field: [16] WRT_PROT_SEC_48
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48 0x00010000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_BITN 16
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_M 0x00010000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_S 16
+
+// Field: [15] WRT_PROT_SEC_47
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47 0x00008000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_BITN 15
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_M 0x00008000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_S 15
+
+// Field: [14] WRT_PROT_SEC_46
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46 0x00004000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_BITN 14
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_M 0x00004000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_S 14
+
+// Field: [13] WRT_PROT_SEC_45
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45 0x00002000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_BITN 13
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_M 0x00002000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_S 13
+
+// Field: [12] WRT_PROT_SEC_44
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44 0x00001000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_BITN 12
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_M 0x00001000
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_S 12
+
+// Field: [11] WRT_PROT_SEC_43
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43 0x00000800
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_BITN 11
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_M 0x00000800
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_S 11
+
+// Field: [10] WRT_PROT_SEC_42
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42 0x00000400
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_BITN 10
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_M 0x00000400
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_S 10
+
+// Field: [9] WRT_PROT_SEC_41
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41 0x00000200
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_BITN 9
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_M 0x00000200
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_S 9
+
+// Field: [8] WRT_PROT_SEC_40
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40 0x00000100
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_BITN 8
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_M 0x00000100
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_S 8
+
+// Field: [7] WRT_PROT_SEC_39
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39 0x00000080
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_BITN 7
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_M 0x00000080
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_S 7
+
+// Field: [6] WRT_PROT_SEC_38
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38 0x00000040
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_BITN 6
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_M 0x00000040
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_S 6
+
+// Field: [5] WRT_PROT_SEC_37
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37 0x00000020
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_BITN 5
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_M 0x00000020
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_S 5
+
+// Field: [4] WRT_PROT_SEC_36
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36 0x00000010
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_BITN 4
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_M 0x00000010
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_S 4
+
+// Field: [3] WRT_PROT_SEC_35
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35 0x00000008
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_BITN 3
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_M 0x00000008
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_S 3
+
+// Field: [2] WRT_PROT_SEC_34
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34 0x00000004
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_BITN 2
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_M 0x00000004
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_S 2
+
+// Field: [1] WRT_PROT_SEC_33
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33 0x00000002
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_BITN 1
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_M 0x00000002
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_S 1
+
+// Field: [0] WRT_PROT_SEC_32
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32 0x00000001
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_BITN 0
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_M 0x00000001
+#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_S 0
+
+//*****************************************************************************
+//
+// Register: CCFG_O_CCFG_PROT_95_64
+//
+//*****************************************************************************
+// Field: [31] WRT_PROT_SEC_95
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95 0x80000000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_BITN 31
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_M 0x80000000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_S 31
+
+// Field: [30] WRT_PROT_SEC_94
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94 0x40000000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_BITN 30
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_M 0x40000000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_S 30
+
+// Field: [29] WRT_PROT_SEC_93
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93 0x20000000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_BITN 29
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_M 0x20000000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_S 29
+
+// Field: [28] WRT_PROT_SEC_92
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92 0x10000000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_BITN 28
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_M 0x10000000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_S 28
+
+// Field: [27] WRT_PROT_SEC_91
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91 0x08000000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_BITN 27
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_M 0x08000000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_S 27
+
+// Field: [26] WRT_PROT_SEC_90
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90 0x04000000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_BITN 26
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_M 0x04000000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_S 26
+
+// Field: [25] WRT_PROT_SEC_89
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89 0x02000000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_BITN 25
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_M 0x02000000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_S 25
+
+// Field: [24] WRT_PROT_SEC_88
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88 0x01000000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_BITN 24
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_M 0x01000000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_S 24
+
+// Field: [23] WRT_PROT_SEC_87
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87 0x00800000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_BITN 23
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_M 0x00800000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_S 23
+
+// Field: [22] WRT_PROT_SEC_86
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86 0x00400000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_BITN 22
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_M 0x00400000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_S 22
+
+// Field: [21] WRT_PROT_SEC_85
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85 0x00200000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_BITN 21
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_M 0x00200000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_S 21
+
+// Field: [20] WRT_PROT_SEC_84
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84 0x00100000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_BITN 20
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_M 0x00100000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_S 20
+
+// Field: [19] WRT_PROT_SEC_83
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83 0x00080000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_BITN 19
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_M 0x00080000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_S 19
+
+// Field: [18] WRT_PROT_SEC_82
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82 0x00040000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_BITN 18
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_M 0x00040000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_S 18
+
+// Field: [17] WRT_PROT_SEC_81
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81 0x00020000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_BITN 17
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_M 0x00020000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_S 17
+
+// Field: [16] WRT_PROT_SEC_80
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80 0x00010000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_BITN 16
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_M 0x00010000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_S 16
+
+// Field: [15] WRT_PROT_SEC_79
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79 0x00008000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_BITN 15
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_M 0x00008000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_S 15
+
+// Field: [14] WRT_PROT_SEC_78
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78 0x00004000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_BITN 14
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_M 0x00004000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_S 14
+
+// Field: [13] WRT_PROT_SEC_77
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77 0x00002000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_BITN 13
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_M 0x00002000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_S 13
+
+// Field: [12] WRT_PROT_SEC_76
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76 0x00001000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_BITN 12
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_M 0x00001000
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_S 12
+
+// Field: [11] WRT_PROT_SEC_75
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75 0x00000800
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_BITN 11
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_M 0x00000800
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_S 11
+
+// Field: [10] WRT_PROT_SEC_74
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74 0x00000400
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_BITN 10
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_M 0x00000400
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_S 10
+
+// Field: [9] WRT_PROT_SEC_73
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73 0x00000200
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_BITN 9
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_M 0x00000200
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_S 9
+
+// Field: [8] WRT_PROT_SEC_72
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72 0x00000100
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_BITN 8
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_M 0x00000100
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_S 8
+
+// Field: [7] WRT_PROT_SEC_71
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71 0x00000080
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_BITN 7
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_M 0x00000080
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_S 7
+
+// Field: [6] WRT_PROT_SEC_70
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70 0x00000040
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_BITN 6
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_M 0x00000040
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_S 6
+
+// Field: [5] WRT_PROT_SEC_69
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69 0x00000020
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_BITN 5
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_M 0x00000020
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_S 5
+
+// Field: [4] WRT_PROT_SEC_68
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68 0x00000010
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_BITN 4
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_M 0x00000010
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_S 4
+
+// Field: [3] WRT_PROT_SEC_67
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67 0x00000008
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_BITN 3
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_M 0x00000008
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_S 3
+
+// Field: [2] WRT_PROT_SEC_66
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66 0x00000004
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_BITN 2
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_M 0x00000004
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_S 2
+
+// Field: [1] WRT_PROT_SEC_65
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65 0x00000002
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_BITN 1
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_M 0x00000002
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_S 1
+
+// Field: [0] WRT_PROT_SEC_64
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64 0x00000001
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_BITN 0
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_M 0x00000001
+#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_S 0
+
+//*****************************************************************************
+//
+// Register: CCFG_O_CCFG_PROT_127_96
+//
+//*****************************************************************************
+// Field: [31] WRT_PROT_SEC_127
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127 0x80000000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_BITN 31
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_M 0x80000000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_S 31
+
+// Field: [30] WRT_PROT_SEC_126
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126 0x40000000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_BITN 30
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_M 0x40000000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_S 30
+
+// Field: [29] WRT_PROT_SEC_125
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125 0x20000000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_BITN 29
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_M 0x20000000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_S 29
+
+// Field: [28] WRT_PROT_SEC_124
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124 0x10000000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_BITN 28
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_M 0x10000000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_S 28
+
+// Field: [27] WRT_PROT_SEC_123
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123 0x08000000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_BITN 27
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_M 0x08000000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_S 27
+
+// Field: [26] WRT_PROT_SEC_122
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122 0x04000000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_BITN 26
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_M 0x04000000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_S 26
+
+// Field: [25] WRT_PROT_SEC_121
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121 0x02000000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_BITN 25
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_M 0x02000000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_S 25
+
+// Field: [24] WRT_PROT_SEC_120
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120 0x01000000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_BITN 24
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_M 0x01000000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_S 24
+
+// Field: [23] WRT_PROT_SEC_119
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119 0x00800000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_BITN 23
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_M 0x00800000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_S 23
+
+// Field: [22] WRT_PROT_SEC_118
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118 0x00400000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_BITN 22
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_M 0x00400000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_S 22
+
+// Field: [21] WRT_PROT_SEC_117
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117 0x00200000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_BITN 21
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_M 0x00200000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_S 21
+
+// Field: [20] WRT_PROT_SEC_116
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116 0x00100000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_BITN 20
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_M 0x00100000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_S 20
+
+// Field: [19] WRT_PROT_SEC_115
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115 0x00080000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_BITN 19
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_M 0x00080000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_S 19
+
+// Field: [18] WRT_PROT_SEC_114
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114 0x00040000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_BITN 18
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_M 0x00040000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_S 18
+
+// Field: [17] WRT_PROT_SEC_113
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113 0x00020000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_BITN 17
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_M 0x00020000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_S 17
+
+// Field: [16] WRT_PROT_SEC_112
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112 0x00010000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_BITN 16
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_M 0x00010000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_S 16
+
+// Field: [15] WRT_PROT_SEC_111
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111 0x00008000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_BITN 15
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_M 0x00008000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_S 15
+
+// Field: [14] WRT_PROT_SEC_110
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110 0x00004000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_BITN 14
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_M 0x00004000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_S 14
+
+// Field: [13] WRT_PROT_SEC_109
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109 0x00002000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_BITN 13
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_M 0x00002000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_S 13
+
+// Field: [12] WRT_PROT_SEC_108
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108 0x00001000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_BITN 12
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_M 0x00001000
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_S 12
+
+// Field: [11] WRT_PROT_SEC_107
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107 0x00000800
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_BITN 11
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_M 0x00000800
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_S 11
+
+// Field: [10] WRT_PROT_SEC_106
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106 0x00000400
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_BITN 10
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_M 0x00000400
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_S 10
+
+// Field: [9] WRT_PROT_SEC_105
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105 0x00000200
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_BITN 9
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_M 0x00000200
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_S 9
+
+// Field: [8] WRT_PROT_SEC_104
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104 0x00000100
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_BITN 8
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_M 0x00000100
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_S 8
+
+// Field: [7] WRT_PROT_SEC_103
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103 0x00000080
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_BITN 7
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_M 0x00000080
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_S 7
+
+// Field: [6] WRT_PROT_SEC_102
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102 0x00000040
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_BITN 6
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_M 0x00000040
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_S 6
+
+// Field: [5] WRT_PROT_SEC_101
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101 0x00000020
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_BITN 5
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_M 0x00000020
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_S 5
+
+// Field: [4] WRT_PROT_SEC_100
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100 0x00000010
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_BITN 4
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_M 0x00000010
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_S 4
+
+// Field: [3] WRT_PROT_SEC_99
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99 0x00000008
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_BITN 3
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_M 0x00000008
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_S 3
+
+// Field: [2] WRT_PROT_SEC_98
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98 0x00000004
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_BITN 2
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_M 0x00000004
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_S 2
+
+// Field: [1] WRT_PROT_SEC_97
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97 0x00000002
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_BITN 1
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_M 0x00000002
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_S 1
+
+// Field: [0] WRT_PROT_SEC_96
+//
+// 0: Sector protected
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96 0x00000001
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_BITN 0
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_M 0x00000001
+#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_S 0
+
+
+#endif // __CCFG__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ccfg_simple_struct.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ccfg_simple_struct.h
new file mode 100644
index 0000000..59fec58
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ccfg_simple_struct.h
@@ -0,0 +1,81 @@
+/******************************************************************************
+* Filename: hw_ccfg_simple_struct_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_CCFG_SIMPLE_STRUCT_H__
+#define __HW_CCFG_SIMPLE_STRUCT_H__
+
+//*****************************************************************************
+//
+// Customer configuration (ccfg) typedef.
+// The implementation of this struct is required by device ROM boot code
+// and must be placed at the end of flash. Do not modify this struct!
+//
+//*****************************************************************************
+typedef struct
+{ // Mapped to address
+ uint32_t CCFG_EXT_LF_CLK ; // 0x50004FA8
+ uint32_t CCFG_MODE_CONF_1 ; // 0x50004FAC
+ uint32_t CCFG_SIZE_AND_DIS_FLAGS ; // 0x50004FB0
+ uint32_t CCFG_MODE_CONF ; // 0x50004FB4
+ uint32_t CCFG_VOLT_LOAD_0 ; // 0x50004FB8
+ uint32_t CCFG_VOLT_LOAD_1 ; // 0x50004FBC
+ uint32_t CCFG_RTC_OFFSET ; // 0x50004FC0
+ uint32_t CCFG_FREQ_OFFSET ; // 0x50004FC4
+ uint32_t CCFG_IEEE_MAC_0 ; // 0x50004FC8
+ uint32_t CCFG_IEEE_MAC_1 ; // 0x50004FCC
+ uint32_t CCFG_IEEE_BLE_0 ; // 0x50004FD0
+ uint32_t CCFG_IEEE_BLE_1 ; // 0x50004FD4
+ uint32_t CCFG_BL_CONFIG ; // 0x50004FD8
+ uint32_t CCFG_ERASE_CONF ; // 0x50004FDC
+ uint32_t CCFG_CCFG_TI_OPTIONS ; // 0x50004FE0
+ uint32_t CCFG_CCFG_TAP_DAP_0 ; // 0x50004FE4
+ uint32_t CCFG_CCFG_TAP_DAP_1 ; // 0x50004FE8
+ uint32_t CCFG_IMAGE_VALID_CONF ; // 0x50004FEC
+ uint32_t CCFG_CCFG_PROT_31_0 ; // 0x50004FF0
+ uint32_t CCFG_CCFG_PROT_63_32 ; // 0x50004FF4
+ uint32_t CCFG_CCFG_PROT_95_64 ; // 0x50004FF8
+ uint32_t CCFG_CCFG_PROT_127_96 ; // 0x50004FFC
+} ccfg_t;
+
+//*****************************************************************************
+//
+// Define the extern ccfg structure (__ccfg)
+//
+//*****************************************************************************
+extern const ccfg_t __ccfg;
+
+
+#endif // __HW_CCFG_SIMPLE_STRUCT__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_chip_def.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_chip_def.h
new file mode 100644
index 0000000..19f70e0
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_chip_def.h
@@ -0,0 +1,234 @@
+/******************************************************************************
+* Filename: hw_chip_def.h
+* Revised: 2017-06-26 09:33:33 +0200 (Mon, 26 Jun 2017)
+* Revision: 49227
+*
+* Description: Defines for device properties.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+//*****************************************************************************
+//
+//! \addtogroup config_api
+//! @{
+//
+//*****************************************************************************
+
+#ifndef __HW_CHIP_DEF_H__
+#define __HW_CHIP_DEF_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Define CC_CHIP_ID code used in the following macros defined at the bottom:
+// CC_GET_CHIP_FAMILY/DEVICE/PACKAGE/HWREV
+//
+//*****************************************************************************
+/* CC2620F128 */
+#if defined(CC2620F128RGZ_R20) || defined(CC2620F128RGZ_R21)
+ #define CC_CHIP_ID 0x26200720
+#elif defined(CC2620F128RHB_R20) || defined(CC2620F128RHB_R21)
+ #define CC_CHIP_ID 0x26200520
+#elif defined(CC2620F128RSM_R20) || defined(CC2620F128RSM_R21)
+ #define CC_CHIP_ID 0x26200420
+#elif defined(CC2620F128_R20) || defined(CC2620F128_R21)
+ #define CC_CHIP_ID 0x26200020
+#elif defined(CC2620F128RGZ_R22) || defined(CC2620F128RGZ)
+ #define CC_CHIP_ID 0x26200722
+#elif defined(CC2620F128RHB_R22) || defined(CC2620F128RHB)
+ #define CC_CHIP_ID 0x26200522
+#elif defined(CC2620F128RSM_R22) || defined(CC2620F128RSM)
+ #define CC_CHIP_ID 0x26200422
+#elif defined(CC2620F128_R22) || defined(CC2620F128)
+ #define CC_CHIP_ID 0x26200022
+/* CC2630F128 */
+#elif defined(CC2630F128RGZ_R20) || defined(CC2630F128RGZ_R21)
+ #define CC_CHIP_ID 0x26300720
+#elif defined(CC2630F128RHB_R20) || defined(CC2630F128RHB_R21)
+ #define CC_CHIP_ID 0x26300520
+#elif defined(CC2630F128RSM_R20) || defined(CC2630F128RSM_R21)
+ #define CC_CHIP_ID 0x26300420
+#elif defined(CC2630F128_R20) || defined(CC2630F128_R21)
+ #define CC_CHIP_ID 0x26300020
+#elif defined(CC2630F128RGZ_R22) || defined(CC2630F128RGZ)
+ #define CC_CHIP_ID 0x26300722
+#elif defined(CC2630F128RHB_R22) || defined(CC2630F128RHB)
+ #define CC_CHIP_ID 0x26300522
+#elif defined(CC2630F128RSM_R22) || defined(CC2630F128RSM)
+ #define CC_CHIP_ID 0x26300422
+#elif defined(CC2630F128_R22) || defined(CC2630F128)
+ #define CC_CHIP_ID 0x26300022
+/* CC2640F128 */
+#elif defined(CC2640F128RGZ_R20) || defined(CC2640F128RGZ_R21)
+ #define CC_CHIP_ID 0x26400720
+#elif defined(CC2640F128RHB_R20) || defined(CC2640F128RHB_R21)
+ #define CC_CHIP_ID 0x26400520
+#elif defined(CC2640F128RSM_R20) || defined(CC2640F128RSM_R21)
+ #define CC_CHIP_ID 0x26400420
+#elif defined(CC2640F128_R20) || defined(CC2640F128_R21)
+ #define CC_CHIP_ID 0x26400020
+#elif defined(CC2640F128RGZ_R22) || defined(CC2640F128RGZ)
+ #define CC_CHIP_ID 0x26400722
+#elif defined(CC2640F128RHB_R22) || defined(CC2640F128RHB)
+ #define CC_CHIP_ID 0x26400522
+#elif defined(CC2640F128RSM_R22) || defined(CC2640F128RSM)
+ #define CC_CHIP_ID 0x26400422
+#elif defined(CC2640F128_R22) || defined(CC2640F128)
+ #define CC_CHIP_ID 0x26400022
+/* CC2650F128 */
+#elif defined(CC2650F128RGZ_R20) || defined(CC2650F128RGZ_R21)
+ #define CC_CHIP_ID 0x26500720
+#elif defined(CC2650F128RHB_R20) || defined(CC2650F128RHB_R21)
+ #define CC_CHIP_ID 0x26500520
+#elif defined(CC2650F128RSM_R20) || defined(CC2650F128RSM_R21)
+ #define CC_CHIP_ID 0x26500420
+#elif defined(CC2650F128_R20) || defined(CC2650F128_R21)
+ #define CC_CHIP_ID 0x26500020
+#elif defined(CC2650F128RGZ_R22) || defined(CC2650F128RGZ)
+ #define CC_CHIP_ID 0x26500722
+#elif defined(CC2650F128RHB_R22) || defined(CC2650F128RHB)
+ #define CC_CHIP_ID 0x26500522
+#elif defined(CC2650F128RSM_R22) || defined(CC2650F128RSM)
+ #define CC_CHIP_ID 0x26500422
+#elif defined(CC2650F128_R22) || defined(CC2650F128)
+ #define CC_CHIP_ID 0x26500022
+/* CC2650L128 (OTP) */
+#elif defined(CC2650L128)
+ #define CC_CHIP_ID 0x26501710
+/* CC1310F128 */
+#elif defined(CC1310F128RGZ_R20) || defined(CC1310F128RGZ)
+ #define CC_CHIP_ID 0x13100720
+#elif defined(CC1310F128RHB_R20) || defined(CC1310F128RHB)
+ #define CC_CHIP_ID 0x13100520
+#elif defined(CC1310F128RSM_R20) || defined(CC1310F128RSM)
+ #define CC_CHIP_ID 0x13100420
+#elif defined(CC1310F128_R20) || defined(CC1310F128)
+ #define CC_CHIP_ID 0x13100020
+/* CC1350F128 */
+#elif defined(CC1350F128RGZ_R20) || defined(CC1350F128RGZ)
+ #define CC_CHIP_ID 0x13500720
+#elif defined(CC1350F128RHB_R20) || defined(CC1350F128RHB)
+ #define CC_CHIP_ID 0x13500520
+#elif defined(CC1350F128RSM_R20) || defined(CC1350F128RSM)
+ #define CC_CHIP_ID 0x13500420
+#elif defined(CC1350F128_R20) || defined(CC1350F128)
+ #define CC_CHIP_ID 0x13500020
+/* CC2640R2F */
+#elif defined(CC2640R2FRGZ_R25) || defined(CC2640R2FRGZ)
+ #define CC_CHIP_ID 0x26401710
+#elif defined(CC2640R2FRHB_R25) || defined(CC2640R2FRHB)
+ #define CC_CHIP_ID 0x26401510
+#elif defined(CC2640R2FRSM_R25) || defined(CC2640R2FRSM)
+ #define CC_CHIP_ID 0x26401410
+#elif defined(CC2640R2F_R25) || defined(CC2640R2F)
+ #define CC_CHIP_ID 0x26401010
+/* CC2652R1F */
+#elif defined(CC2652R1FRGZ_R10) || defined(CC2652R1FRGZ)
+ #define CC_CHIP_ID 0x26523710
+#elif defined(CC2652R1F_R10) || defined(CC2652R1F)
+ #define CC_CHIP_ID 0x26523010
+/* CC2644R1F */
+#elif defined(CC2644R1FRGZ_R10) || defined(CC2644R1FRGZ)
+ #define CC_CHIP_ID 0x26443710
+#elif defined(CC2644R1F_R10) || defined(CC2644R1F)
+ #define CC_CHIP_ID 0x26443010
+/* CC2642R1F */
+#elif defined(CC2642R1FRGZ_R10) || defined(CC2642R1FRGZ)
+ #define CC_CHIP_ID 0x26423710
+#elif defined(CC2642R1F_R10) || defined(CC2642R1F)
+ #define CC_CHIP_ID 0x26423010
+/* CC1354R1F */
+#elif defined(CC1354R1FRGZ_R10) || defined(CC1354R1FRGZ)
+ #define CC_CHIP_ID 0x13543710
+#elif defined(CC1354R1F_R10) || defined(CC1354R1F)
+ #define CC_CHIP_ID 0x13543010
+/* CC1352R1F */
+#elif defined(CC1352R1FRGZ_R10) || defined(CC1352R1FRGZ)
+ #define CC_CHIP_ID 0x13523710
+#elif defined(CC1352R1F_R10) || defined(CC1352R1F)
+ #define CC_CHIP_ID 0x13523010
+/* CC1312R1F */
+#elif defined(CC1312R1FRGZ_R10) || defined(CC1312R1FRGZ)
+ #define CC_CHIP_ID 0x13123710
+#elif defined(CC1312R1F_R10) || defined(CC1312R1F)
+ #define CC_CHIP_ID 0x13123010
+#endif
+
+#define CC_GET_CHIP_FAMILY 0x26
+#define CC_GET_CHIP_OPTION 0x3
+#define CC_GET_CHIP_HWREV 0x20
+
+#ifdef CC_CHIP_ID
+ /* Define chip package only if specified */
+ #if (CC_CHIP_ID & 0x00000F00) != 0
+ #define CC_GET_CHIP_PACKAGE (((CC_CHIP_ID) & 0x00000F00) >> 8)
+ #endif
+
+ /* Define chip device */
+ #define CC_GET_CHIP_DEVICE (((CC_CHIP_ID) & 0xFFFF0000) >> 16)
+
+ /* The chip family, option and package shall match the DriverLib release */
+ #if (CC_GET_CHIP_OPTION != ((CC_CHIP_ID & 0x0000F000) >> 12))
+ #error "Specified chip option does not match DriverLib release"
+ #endif
+ #if (CC_GET_CHIP_HWREV != ((CC_CHIP_ID & 0x000000FF) >> 0))
+ #error "Specified chip hardware revision does not match DriverLib release"
+ #endif
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __HW_CHIP_DEF_H__
+
+//*****************************************************************************
+//
+//! Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_dwt.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_dwt.h
new file mode 100644
index 0000000..fa62b89
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_dwt.h
@@ -0,0 +1,856 @@
+/******************************************************************************
+* Filename: hw_cpu_dwt_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_CPU_DWT_H__
+#define __HW_CPU_DWT_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// CPU_DWT component
+//
+//*****************************************************************************
+// Control
+#define CPU_DWT_O_CTRL 0x00000000
+
+// Current PC Sampler Cycle Count
+#define CPU_DWT_O_CYCCNT 0x00000004
+
+// CPI Count
+#define CPU_DWT_O_CPICNT 0x00000008
+
+// Exception Overhead Count
+#define CPU_DWT_O_EXCCNT 0x0000000C
+
+// Sleep Count
+#define CPU_DWT_O_SLEEPCNT 0x00000010
+
+// LSU Count
+#define CPU_DWT_O_LSUCNT 0x00000014
+
+// Fold Count
+#define CPU_DWT_O_FOLDCNT 0x00000018
+
+// Program Counter Sample
+#define CPU_DWT_O_PCSR 0x0000001C
+
+// Comparator 0
+#define CPU_DWT_O_COMP0 0x00000020
+
+// Mask 0
+#define CPU_DWT_O_MASK0 0x00000024
+
+// Function 0
+#define CPU_DWT_O_FUNCTION0 0x00000028
+
+// Comparator 1
+#define CPU_DWT_O_COMP1 0x00000030
+
+// Mask 1
+#define CPU_DWT_O_MASK1 0x00000034
+
+// Function 1
+#define CPU_DWT_O_FUNCTION1 0x00000038
+
+// Comparator 2
+#define CPU_DWT_O_COMP2 0x00000040
+
+// Mask 2
+#define CPU_DWT_O_MASK2 0x00000044
+
+// Function 2
+#define CPU_DWT_O_FUNCTION2 0x00000048
+
+// Comparator 3
+#define CPU_DWT_O_COMP3 0x00000050
+
+// Mask 3
+#define CPU_DWT_O_MASK3 0x00000054
+
+// Function 3
+#define CPU_DWT_O_FUNCTION3 0x00000058
+
+//*****************************************************************************
+//
+// Register: CPU_DWT_O_CTRL
+//
+//*****************************************************************************
+// Field: [25] NOCYCCNT
+//
+// When set, CYCCNT is not supported.
+#define CPU_DWT_CTRL_NOCYCCNT 0x02000000
+#define CPU_DWT_CTRL_NOCYCCNT_BITN 25
+#define CPU_DWT_CTRL_NOCYCCNT_M 0x02000000
+#define CPU_DWT_CTRL_NOCYCCNT_S 25
+
+// Field: [24] NOPRFCNT
+//
+// When set, FOLDCNT, LSUCNT, SLEEPCNT, EXCCNT, and CPICNT are not supported.
+#define CPU_DWT_CTRL_NOPRFCNT 0x01000000
+#define CPU_DWT_CTRL_NOPRFCNT_BITN 24
+#define CPU_DWT_CTRL_NOPRFCNT_M 0x01000000
+#define CPU_DWT_CTRL_NOPRFCNT_S 24
+
+// Field: [22] CYCEVTENA
+//
+// Enables Cycle count event. Emits an event when the POSTCNT counter triggers
+// it. See CYCTAP and POSTPRESET for details. This event is only emitted if
+// PCSAMPLEENA is disabled. PCSAMPLEENA overrides the setting of this bit.
+//
+// 0: Cycle count events disabled
+// 1: Cycle count events enabled
+#define CPU_DWT_CTRL_CYCEVTENA 0x00400000
+#define CPU_DWT_CTRL_CYCEVTENA_BITN 22
+#define CPU_DWT_CTRL_CYCEVTENA_M 0x00400000
+#define CPU_DWT_CTRL_CYCEVTENA_S 22
+
+// Field: [21] FOLDEVTENA
+//
+// Enables Folded instruction count event. Emits an event when FOLDCNT
+// overflows (every 256 cycles of folded instructions). A folded instruction is
+// one that does not incur even one cycle to execute. For example, an IT
+// instruction is folded away and so does not use up one cycle.
+//
+// 0: Folded instruction count events disabled.
+// 1: Folded instruction count events enabled.
+#define CPU_DWT_CTRL_FOLDEVTENA 0x00200000
+#define CPU_DWT_CTRL_FOLDEVTENA_BITN 21
+#define CPU_DWT_CTRL_FOLDEVTENA_M 0x00200000
+#define CPU_DWT_CTRL_FOLDEVTENA_S 21
+
+// Field: [20] LSUEVTENA
+//
+// Enables LSU count event. Emits an event when LSUCNT overflows (every 256
+// cycles of LSU operation). LSU counts include all LSU costs after the initial
+// cycle for the instruction.
+//
+// 0: LSU count events disabled.
+// 1: LSU count events enabled.
+#define CPU_DWT_CTRL_LSUEVTENA 0x00100000
+#define CPU_DWT_CTRL_LSUEVTENA_BITN 20
+#define CPU_DWT_CTRL_LSUEVTENA_M 0x00100000
+#define CPU_DWT_CTRL_LSUEVTENA_S 20
+
+// Field: [19] SLEEPEVTENA
+//
+// Enables Sleep count event. Emits an event when SLEEPCNT overflows (every 256
+// cycles that the processor is sleeping).
+//
+// 0: Sleep count events disabled.
+// 1: Sleep count events enabled.
+#define CPU_DWT_CTRL_SLEEPEVTENA 0x00080000
+#define CPU_DWT_CTRL_SLEEPEVTENA_BITN 19
+#define CPU_DWT_CTRL_SLEEPEVTENA_M 0x00080000
+#define CPU_DWT_CTRL_SLEEPEVTENA_S 19
+
+// Field: [18] EXCEVTENA
+//
+// Enables Interrupt overhead event. Emits an event when EXCCNT overflows
+// (every 256 cycles of interrupt overhead).
+//
+// 0x0: Interrupt overhead event disabled.
+// 0x1: Interrupt overhead event enabled.
+#define CPU_DWT_CTRL_EXCEVTENA 0x00040000
+#define CPU_DWT_CTRL_EXCEVTENA_BITN 18
+#define CPU_DWT_CTRL_EXCEVTENA_M 0x00040000
+#define CPU_DWT_CTRL_EXCEVTENA_S 18
+
+// Field: [17] CPIEVTENA
+//
+// Enables CPI count event. Emits an event when CPICNT overflows (every 256
+// cycles of multi-cycle instructions).
+//
+// 0: CPI counter events disabled.
+// 1: CPI counter events enabled.
+#define CPU_DWT_CTRL_CPIEVTENA 0x00020000
+#define CPU_DWT_CTRL_CPIEVTENA_BITN 17
+#define CPU_DWT_CTRL_CPIEVTENA_M 0x00020000
+#define CPU_DWT_CTRL_CPIEVTENA_S 17
+
+// Field: [16] EXCTRCENA
+//
+// Enables Interrupt event tracing.
+//
+// 0: Interrupt event trace disabled.
+// 1: Interrupt event trace enabled.
+#define CPU_DWT_CTRL_EXCTRCENA 0x00010000
+#define CPU_DWT_CTRL_EXCTRCENA_BITN 16
+#define CPU_DWT_CTRL_EXCTRCENA_M 0x00010000
+#define CPU_DWT_CTRL_EXCTRCENA_S 16
+
+// Field: [12] PCSAMPLEENA
+//
+// Enables PC Sampling event. A PC sample event is emitted when the POSTCNT
+// counter triggers it. See CYCTAP and POSTPRESET for details. Enabling this
+// bit overrides CYCEVTENA.
+//
+// 0: PC Sampling event disabled.
+// 1: Sampling event enabled.
+#define CPU_DWT_CTRL_PCSAMPLEENA 0x00001000
+#define CPU_DWT_CTRL_PCSAMPLEENA_BITN 12
+#define CPU_DWT_CTRL_PCSAMPLEENA_M 0x00001000
+#define CPU_DWT_CTRL_PCSAMPLEENA_S 12
+
+// Field: [11:10] SYNCTAP
+//
+// Selects a synchronization packet rate. CYCCNTENA and CPU_ITM:TCR.SYNCENA
+// must also be enabled for this feature.
+// Synchronization packets (if enabled) are generated on tap transitions (0 to1
+// or 1 to 0).
+// ENUMs:
+// BIT28 Tap at bit 28 of CYCCNT
+// BIT26 Tap at bit 26 of CYCCNT
+// BIT24 Tap at bit 24 of CYCCNT
+// DIS Disabled. No synchronization packets
+#define CPU_DWT_CTRL_SYNCTAP_W 2
+#define CPU_DWT_CTRL_SYNCTAP_M 0x00000C00
+#define CPU_DWT_CTRL_SYNCTAP_S 10
+#define CPU_DWT_CTRL_SYNCTAP_BIT28 0x00000C00
+#define CPU_DWT_CTRL_SYNCTAP_BIT26 0x00000800
+#define CPU_DWT_CTRL_SYNCTAP_BIT24 0x00000400
+#define CPU_DWT_CTRL_SYNCTAP_DIS 0x00000000
+
+// Field: [9] CYCTAP
+//
+// Selects a tap on CYCCNT. These are spaced at bits [6] and [10]. When the
+// selected bit in CYCCNT changes from 0 to 1 or 1 to 0, it emits into the
+// POSTCNT, post-scalar counter. That counter then counts down. On a bit change
+// when post-scalar is 0, it triggers an event for PC sampling or cycle count
+// event (see details in CYCEVTENA).
+// ENUMs:
+// BIT10 Selects bit [10] to tap
+// BIT6 Selects bit [6] to tap
+#define CPU_DWT_CTRL_CYCTAP 0x00000200
+#define CPU_DWT_CTRL_CYCTAP_BITN 9
+#define CPU_DWT_CTRL_CYCTAP_M 0x00000200
+#define CPU_DWT_CTRL_CYCTAP_S 9
+#define CPU_DWT_CTRL_CYCTAP_BIT10 0x00000200
+#define CPU_DWT_CTRL_CYCTAP_BIT6 0x00000000
+
+// Field: [8:5] POSTCNT
+//
+// Post-scalar counter for CYCTAP. When the selected tapped bit changes from 0
+// to 1 or 1 to 0, the post scalar counter is down-counted when not 0. If 0, it
+// triggers an event for PCSAMPLEENA or CYCEVTENA use. It also reloads with the
+// value from POSTPRESET.
+#define CPU_DWT_CTRL_POSTCNT_W 4
+#define CPU_DWT_CTRL_POSTCNT_M 0x000001E0
+#define CPU_DWT_CTRL_POSTCNT_S 5
+
+// Field: [4:1] POSTPRESET
+//
+// Reload value for post-scalar counter POSTCNT. When 0, events are triggered
+// on each tap change (a power of 2). If this field has a non-0 value, it forms
+// a count-down value, to be reloaded into POSTCNT each time it reaches 0. For
+// example, a value 1 in this register means an event is formed every other tap
+// change.
+#define CPU_DWT_CTRL_POSTPRESET_W 4
+#define CPU_DWT_CTRL_POSTPRESET_M 0x0000001E
+#define CPU_DWT_CTRL_POSTPRESET_S 1
+
+// Field: [0] CYCCNTENA
+//
+// Enable CYCCNT, allowing it to increment and generate synchronization and
+// count events. If NOCYCCNT = 1, this bit reads zero and ignore writes.
+#define CPU_DWT_CTRL_CYCCNTENA 0x00000001
+#define CPU_DWT_CTRL_CYCCNTENA_BITN 0
+#define CPU_DWT_CTRL_CYCCNTENA_M 0x00000001
+#define CPU_DWT_CTRL_CYCCNTENA_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_DWT_O_CYCCNT
+//
+//*****************************************************************************
+// Field: [31:0] CYCCNT
+//
+// Current PC Sampler Cycle Counter count value. When enabled, this counter
+// counts the number of core cycles, except when the core is halted. The cycle
+// counter is a free running counter, counting upwards (this counter will not
+// advance in power modes where free-running clock to CPU stops). It wraps
+// around to 0 on overflow. The debugger must initialize this to 0 when first
+// enabling.
+#define CPU_DWT_CYCCNT_CYCCNT_W 32
+#define CPU_DWT_CYCCNT_CYCCNT_M 0xFFFFFFFF
+#define CPU_DWT_CYCCNT_CYCCNT_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_DWT_O_CPICNT
+//
+//*****************************************************************************
+// Field: [7:0] CPICNT
+//
+// Current CPI counter value. Increments on the additional cycles (the first
+// cycle is not counted) required to execute all instructions except those
+// recorded by LSUCNT. This counter also increments on all instruction fetch
+// stalls. If CTRL.CPIEVTENA is set, an event is emitted when the counter
+// overflows. This counter initializes to 0 when it is enabled using
+// CTRL.CPIEVTENA.
+#define CPU_DWT_CPICNT_CPICNT_W 8
+#define CPU_DWT_CPICNT_CPICNT_M 0x000000FF
+#define CPU_DWT_CPICNT_CPICNT_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_DWT_O_EXCCNT
+//
+//*****************************************************************************
+// Field: [7:0] EXCCNT
+//
+// Current interrupt overhead counter value. Counts the total cycles spent in
+// interrupt processing (for example entry stacking, return unstacking,
+// pre-emption). An event is emitted on counter overflow (every 256 cycles).
+// This counter initializes to 0 when it is enabled using CTRL.EXCEVTENA.
+#define CPU_DWT_EXCCNT_EXCCNT_W 8
+#define CPU_DWT_EXCCNT_EXCCNT_M 0x000000FF
+#define CPU_DWT_EXCCNT_EXCCNT_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_DWT_O_SLEEPCNT
+//
+//*****************************************************************************
+// Field: [7:0] SLEEPCNT
+//
+// Sleep counter. Counts the number of cycles during which the processor is
+// sleeping. An event is emitted on counter overflow (every 256 cycles). This
+// counter initializes to 0 when it is enabled using CTRL.SLEEPEVTENA. Note
+// that the sleep counter is clocked using CPU's free-running clock. In some
+// power modes the free-running clock to CPU is gated to minimize power
+// consumption. This means that the sleep counter will be invalid in these
+// power modes.
+#define CPU_DWT_SLEEPCNT_SLEEPCNT_W 8
+#define CPU_DWT_SLEEPCNT_SLEEPCNT_M 0x000000FF
+#define CPU_DWT_SLEEPCNT_SLEEPCNT_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_DWT_O_LSUCNT
+//
+//*****************************************************************************
+// Field: [7:0] LSUCNT
+//
+// LSU counter. This counts the total number of cycles that the processor is
+// processing an LSU operation. The initial execution cost of the instruction
+// is not counted. For example, an LDR that takes two cycles to complete
+// increments this counter one cycle. Equivalently, an LDR that stalls for two
+// cycles (i.e. takes four cycles to execute), increments this counter three
+// times. An event is emitted on counter overflow (every 256 cycles). This
+// counter initializes to 0 when it is enabled using CTRL.LSUEVTENA.
+#define CPU_DWT_LSUCNT_LSUCNT_W 8
+#define CPU_DWT_LSUCNT_LSUCNT_M 0x000000FF
+#define CPU_DWT_LSUCNT_LSUCNT_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_DWT_O_FOLDCNT
+//
+//*****************************************************************************
+// Field: [7:0] FOLDCNT
+//
+// This counts the total number folded instructions. This counter initializes
+// to 0 when it is enabled using CTRL.FOLDEVTENA.
+#define CPU_DWT_FOLDCNT_FOLDCNT_W 8
+#define CPU_DWT_FOLDCNT_FOLDCNT_M 0x000000FF
+#define CPU_DWT_FOLDCNT_FOLDCNT_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_DWT_O_PCSR
+//
+//*****************************************************************************
+// Field: [31:0] EIASAMPLE
+//
+// Execution instruction address sample, or 0xFFFFFFFF if the core is halted.
+#define CPU_DWT_PCSR_EIASAMPLE_W 32
+#define CPU_DWT_PCSR_EIASAMPLE_M 0xFFFFFFFF
+#define CPU_DWT_PCSR_EIASAMPLE_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_DWT_O_COMP0
+//
+//*****************************************************************************
+// Field: [31:0] COMP
+//
+// Reference value to compare against PC or the data address as given by
+// FUNCTION0. Comparator 0 can also compare against the value of the PC Sampler
+// Counter (CYCCNT).
+#define CPU_DWT_COMP0_COMP_W 32
+#define CPU_DWT_COMP0_COMP_M 0xFFFFFFFF
+#define CPU_DWT_COMP0_COMP_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_DWT_O_MASK0
+//
+//*****************************************************************************
+// Field: [3:0] MASK
+//
+// Mask on data address when matching against COMP0. This is the size of the
+// ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF
+// left bit-shifted by MASK)) == COMP0. However, the actual comparison is
+// slightly more complex to enable matching an address wherever it appears on a
+// bus. So, if COMP0 is 3, this matches a word access of 0, because 3 would be
+// within the word.
+#define CPU_DWT_MASK0_MASK_W 4
+#define CPU_DWT_MASK0_MASK_M 0x0000000F
+#define CPU_DWT_MASK0_MASK_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_DWT_O_FUNCTION0
+//
+//*****************************************************************************
+// Field: [24] MATCHED
+//
+// This bit is set when the comparator matches, and indicates that the
+// operation defined by FUNCTION has occurred since this bit was last read.
+// This bit is cleared on read.
+#define CPU_DWT_FUNCTION0_MATCHED 0x01000000
+#define CPU_DWT_FUNCTION0_MATCHED_BITN 24
+#define CPU_DWT_FUNCTION0_MATCHED_M 0x01000000
+#define CPU_DWT_FUNCTION0_MATCHED_S 24
+
+// Field: [7] CYCMATCH
+//
+// This bit is only available in comparator 0. When set, COMP0 will compare
+// against the cycle counter (CYCCNT).
+#define CPU_DWT_FUNCTION0_CYCMATCH 0x00000080
+#define CPU_DWT_FUNCTION0_CYCMATCH_BITN 7
+#define CPU_DWT_FUNCTION0_CYCMATCH_M 0x00000080
+#define CPU_DWT_FUNCTION0_CYCMATCH_S 7
+
+// Field: [5] EMITRANGE
+//
+// Emit range field. This bit permits emitting offset when range match occurs.
+// PC sampling is not supported when emit range is enabled.
+// This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15.
+#define CPU_DWT_FUNCTION0_EMITRANGE 0x00000020
+#define CPU_DWT_FUNCTION0_EMITRANGE_BITN 5
+#define CPU_DWT_FUNCTION0_EMITRANGE_M 0x00000020
+#define CPU_DWT_FUNCTION0_EMITRANGE_S 5
+
+// Field: [3:0] FUNCTION
+//
+// Function settings.
+//
+// 0x0: Disabled
+// 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit
+// address offset through ITM
+// 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1,
+// emit data and address offset through ITM on read or write.
+// 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write.
+// EMITRANGE = 1, emit address offset and data value through ITM on read or
+// write.
+// 0x4: Watchpoint on PC match.
+// 0x5: Watchpoint on read.
+// 0x6: Watchpoint on write.
+// 0x7: Watchpoint on read or write.
+// 0x8: ETM trigger on PC match
+// 0x9: ETM trigger on read
+// 0xA: ETM trigger on write
+// 0xB: ETM trigger on read or write
+// 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample
+// Daddr (lower 16 bits) for read transfers
+// 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample
+// Daddr (lower 16 bits) for write transfers
+// 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1,
+// sample Daddr (lower 16 bits) + data for read transfers
+// 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1,
+// sample Daddr (lower 16 bits) + data for write transfers
+//
+// Note 1: If the ETM is not fitted, then ETM trigger is not possible.
+// Note 2: Data value is only sampled for accesses that do not fault (MPU or
+// bus fault). The PC is sampled irrespective of any faults. The PC is only
+// sampled for the first address of a burst.
+// Note 3: PC match is not recommended for watchpoints because it stops after
+// the instruction. It mainly guards and triggers the ETM.
+#define CPU_DWT_FUNCTION0_FUNCTION_W 4
+#define CPU_DWT_FUNCTION0_FUNCTION_M 0x0000000F
+#define CPU_DWT_FUNCTION0_FUNCTION_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_DWT_O_COMP1
+//
+//*****************************************************************************
+// Field: [31:0] COMP
+//
+// Reference value to compare against PC or the data address as given by
+// FUNCTION1.
+// Comparator 1 can also compare data values. So this register can contain
+// reference values for data matching.
+#define CPU_DWT_COMP1_COMP_W 32
+#define CPU_DWT_COMP1_COMP_M 0xFFFFFFFF
+#define CPU_DWT_COMP1_COMP_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_DWT_O_MASK1
+//
+//*****************************************************************************
+// Field: [3:0] MASK
+//
+// Mask on data address when matching against COMP1. This is the size of the
+// ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF
+// left bit-shifted by MASK)) == COMP1. However, the actual comparison is
+// slightly more complex to enable matching an address wherever it appears on a
+// bus. So, if COMP1 is 3, this matches a word access of 0, because 3 would be
+// within the word.
+#define CPU_DWT_MASK1_MASK_W 4
+#define CPU_DWT_MASK1_MASK_M 0x0000000F
+#define CPU_DWT_MASK1_MASK_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_DWT_O_FUNCTION1
+//
+//*****************************************************************************
+// Field: [24] MATCHED
+//
+// This bit is set when the comparator matches, and indicates that the
+// operation defined by FUNCTION has occurred since this bit was last read.
+// This bit is cleared on read.
+#define CPU_DWT_FUNCTION1_MATCHED 0x01000000
+#define CPU_DWT_FUNCTION1_MATCHED_BITN 24
+#define CPU_DWT_FUNCTION1_MATCHED_M 0x01000000
+#define CPU_DWT_FUNCTION1_MATCHED_S 24
+
+// Field: [19:16] DATAVADDR1
+//
+// Identity of a second linked address comparator for data value matching when
+// DATAVMATCH == 1 and LNK1ENA == 1.
+#define CPU_DWT_FUNCTION1_DATAVADDR1_W 4
+#define CPU_DWT_FUNCTION1_DATAVADDR1_M 0x000F0000
+#define CPU_DWT_FUNCTION1_DATAVADDR1_S 16
+
+// Field: [15:12] DATAVADDR0
+//
+// Identity of a linked address comparator for data value matching when
+// DATAVMATCH == 1.
+#define CPU_DWT_FUNCTION1_DATAVADDR0_W 4
+#define CPU_DWT_FUNCTION1_DATAVADDR0_M 0x0000F000
+#define CPU_DWT_FUNCTION1_DATAVADDR0_S 12
+
+// Field: [11:10] DATAVSIZE
+//
+// Defines the size of the data in the COMP1 register that is to be matched:
+//
+// 0x0: Byte
+// 0x1: Halfword
+// 0x2: Word
+// 0x3: Unpredictable.
+#define CPU_DWT_FUNCTION1_DATAVSIZE_W 2
+#define CPU_DWT_FUNCTION1_DATAVSIZE_M 0x00000C00
+#define CPU_DWT_FUNCTION1_DATAVSIZE_S 10
+
+// Field: [9] LNK1ENA
+//
+// Read only bit-field only supported in comparator 1.
+//
+// 0: DATAVADDR1 not supported
+// 1: DATAVADDR1 supported (enabled)
+#define CPU_DWT_FUNCTION1_LNK1ENA 0x00000200
+#define CPU_DWT_FUNCTION1_LNK1ENA_BITN 9
+#define CPU_DWT_FUNCTION1_LNK1ENA_M 0x00000200
+#define CPU_DWT_FUNCTION1_LNK1ENA_S 9
+
+// Field: [8] DATAVMATCH
+//
+// Data match feature:
+//
+// 0: Perform address comparison
+// 1: Perform data value compare. The comparators given by DATAVADDR0 and
+// DATAVADDR1 provide the address for the data comparison. The FUNCTION setting
+// for the comparators given by DATAVADDR0 and DATAVADDR1 are overridden and
+// those comparators only provide the address match for the data comparison.
+//
+// This bit is only available in comparator 1.
+#define CPU_DWT_FUNCTION1_DATAVMATCH 0x00000100
+#define CPU_DWT_FUNCTION1_DATAVMATCH_BITN 8
+#define CPU_DWT_FUNCTION1_DATAVMATCH_M 0x00000100
+#define CPU_DWT_FUNCTION1_DATAVMATCH_S 8
+
+// Field: [5] EMITRANGE
+//
+// Emit range field. This bit permits emitting offset when range match occurs.
+// PC sampling is not supported when emit range is enabled.
+// This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15.
+#define CPU_DWT_FUNCTION1_EMITRANGE 0x00000020
+#define CPU_DWT_FUNCTION1_EMITRANGE_BITN 5
+#define CPU_DWT_FUNCTION1_EMITRANGE_M 0x00000020
+#define CPU_DWT_FUNCTION1_EMITRANGE_S 5
+
+// Field: [3:0] FUNCTION
+//
+// Function settings:
+//
+// 0x0: Disabled
+// 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit
+// address offset through ITM
+// 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1,
+// emit data and address offset through ITM on read or write.
+// 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write.
+// EMITRANGE = 1, emit address offset and data value through ITM on read or
+// write.
+// 0x4: Watchpoint on PC match.
+// 0x5: Watchpoint on read.
+// 0x6: Watchpoint on write.
+// 0x7: Watchpoint on read or write.
+// 0x8: ETM trigger on PC match
+// 0x9: ETM trigger on read
+// 0xA: ETM trigger on write
+// 0xB: ETM trigger on read or write
+// 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample
+// Daddr (lower 16 bits) for read transfers
+// 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample
+// Daddr (lower 16 bits) for write transfers
+// 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1,
+// sample Daddr (lower 16 bits) + data for read transfers
+// 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1,
+// sample Daddr (lower 16 bits) + data for write transfers
+//
+// Note 1: If the ETM is not fitted, then ETM trigger is not possible.
+// Note 2: Data value is only sampled for accesses that do not fault (MPU or
+// bus fault). The PC is sampled irrespective of any faults. The PC is only
+// sampled for the first address of a burst.
+// Note 3: FUNCTION is overridden for comparators given by DATAVADDR0 and
+// DATAVADDR1 if DATAVMATCH is also set. The comparators given by DATAVADDR0
+// and DATAVADDR1 can then only perform address comparator matches for
+// comparator 1 data matches.
+// Note 4: If the data matching functionality is not included during
+// implementation it is not possible to set DATAVADDR0, DATAVADDR1, or
+// DATAVMATCH. This means that the data matching functionality is not available
+// in the implementation. Test the availability of data matching by writing and
+// reading DATAVMATCH. If it is not settable then data matching is unavailable.
+// Note 5: PC match is not recommended for watchpoints because it stops after
+// the instruction. It mainly guards and triggers the ETM.
+#define CPU_DWT_FUNCTION1_FUNCTION_W 4
+#define CPU_DWT_FUNCTION1_FUNCTION_M 0x0000000F
+#define CPU_DWT_FUNCTION1_FUNCTION_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_DWT_O_COMP2
+//
+//*****************************************************************************
+// Field: [31:0] COMP
+//
+// Reference value to compare against PC or the data address as given by
+// FUNCTION2.
+#define CPU_DWT_COMP2_COMP_W 32
+#define CPU_DWT_COMP2_COMP_M 0xFFFFFFFF
+#define CPU_DWT_COMP2_COMP_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_DWT_O_MASK2
+//
+//*****************************************************************************
+// Field: [3:0] MASK
+//
+// Mask on data address when matching against COMP2. This is the size of the
+// ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF
+// left bit-shifted by MASK)) == COMP2. However, the actual comparison is
+// slightly more complex to enable matching an address wherever it appears on a
+// bus. So, if COMP2 is 3, this matches a word access of 0, because 3 would be
+// within the word.
+#define CPU_DWT_MASK2_MASK_W 4
+#define CPU_DWT_MASK2_MASK_M 0x0000000F
+#define CPU_DWT_MASK2_MASK_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_DWT_O_FUNCTION2
+//
+//*****************************************************************************
+// Field: [24] MATCHED
+//
+// This bit is set when the comparator matches, and indicates that the
+// operation defined by FUNCTION has occurred since this bit was last read.
+// This bit is cleared on read.
+#define CPU_DWT_FUNCTION2_MATCHED 0x01000000
+#define CPU_DWT_FUNCTION2_MATCHED_BITN 24
+#define CPU_DWT_FUNCTION2_MATCHED_M 0x01000000
+#define CPU_DWT_FUNCTION2_MATCHED_S 24
+
+// Field: [5] EMITRANGE
+//
+// Emit range field. This bit permits emitting offset when range match occurs.
+// PC sampling is not supported when emit range is enabled.
+// This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15.
+#define CPU_DWT_FUNCTION2_EMITRANGE 0x00000020
+#define CPU_DWT_FUNCTION2_EMITRANGE_BITN 5
+#define CPU_DWT_FUNCTION2_EMITRANGE_M 0x00000020
+#define CPU_DWT_FUNCTION2_EMITRANGE_S 5
+
+// Field: [3:0] FUNCTION
+//
+// Function settings.
+//
+// 0x0: Disabled
+// 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit
+// address offset through ITM
+// 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1,
+// emit data and address offset through ITM on read or write.
+// 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write.
+// EMITRANGE = 1, emit address offset and data value through ITM on read or
+// write.
+// 0x4: Watchpoint on PC match.
+// 0x5: Watchpoint on read.
+// 0x6: Watchpoint on write.
+// 0x7: Watchpoint on read or write.
+// 0x8: ETM trigger on PC match
+// 0x9: ETM trigger on read
+// 0xA: ETM trigger on write
+// 0xB: ETM trigger on read or write
+// 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample
+// Daddr (lower 16 bits) for read transfers
+// 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample
+// Daddr (lower 16 bits) for write transfers
+// 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1,
+// sample Daddr (lower 16 bits) + data for read transfers
+// 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1,
+// sample Daddr (lower 16 bits) + data for write transfers
+//
+// Note 1: If the ETM is not fitted, then ETM trigger is not possible.
+// Note 2: Data value is only sampled for accesses that do not fault (MPU or
+// bus fault). The PC is sampled irrespective of any faults. The PC is only
+// sampled for the first address of a burst.
+// Note 3: PC match is not recommended for watchpoints because it stops after
+// the instruction. It mainly guards and triggers the ETM.
+#define CPU_DWT_FUNCTION2_FUNCTION_W 4
+#define CPU_DWT_FUNCTION2_FUNCTION_M 0x0000000F
+#define CPU_DWT_FUNCTION2_FUNCTION_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_DWT_O_COMP3
+//
+//*****************************************************************************
+// Field: [31:0] COMP
+//
+// Reference value to compare against PC or the data address as given by
+// FUNCTION3.
+#define CPU_DWT_COMP3_COMP_W 32
+#define CPU_DWT_COMP3_COMP_M 0xFFFFFFFF
+#define CPU_DWT_COMP3_COMP_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_DWT_O_MASK3
+//
+//*****************************************************************************
+// Field: [3:0] MASK
+//
+// Mask on data address when matching against COMP3. This is the size of the
+// ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF
+// left bit-shifted by MASK)) == COMP3. However, the actual comparison is
+// slightly more complex to enable matching an address wherever it appears on a
+// bus. So, if COMP3 is 3, this matches a word access of 0, because 3 would be
+// within the word.
+#define CPU_DWT_MASK3_MASK_W 4
+#define CPU_DWT_MASK3_MASK_M 0x0000000F
+#define CPU_DWT_MASK3_MASK_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_DWT_O_FUNCTION3
+//
+//*****************************************************************************
+// Field: [24] MATCHED
+//
+// This bit is set when the comparator matches, and indicates that the
+// operation defined by FUNCTION has occurred since this bit was last read.
+// This bit is cleared on read.
+#define CPU_DWT_FUNCTION3_MATCHED 0x01000000
+#define CPU_DWT_FUNCTION3_MATCHED_BITN 24
+#define CPU_DWT_FUNCTION3_MATCHED_M 0x01000000
+#define CPU_DWT_FUNCTION3_MATCHED_S 24
+
+// Field: [5] EMITRANGE
+//
+// Emit range field. This bit permits emitting offset when range match occurs.
+// PC sampling is not supported when emit range is enabled.
+// This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15.
+#define CPU_DWT_FUNCTION3_EMITRANGE 0x00000020
+#define CPU_DWT_FUNCTION3_EMITRANGE_BITN 5
+#define CPU_DWT_FUNCTION3_EMITRANGE_M 0x00000020
+#define CPU_DWT_FUNCTION3_EMITRANGE_S 5
+
+// Field: [3:0] FUNCTION
+//
+// Function settings.
+//
+// 0x0: Disabled
+// 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit
+// address offset through ITM
+// 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1,
+// emit data and address offset through ITM on read or write.
+// 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write.
+// EMITRANGE = 1, emit address offset and data value through ITM on read or
+// write.
+// 0x4: Watchpoint on PC match.
+// 0x5: Watchpoint on read.
+// 0x6: Watchpoint on write.
+// 0x7: Watchpoint on read or write.
+// 0x8: ETM trigger on PC match
+// 0x9: ETM trigger on read
+// 0xA: ETM trigger on write
+// 0xB: ETM trigger on read or write
+// 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample
+// Daddr (lower 16 bits) for read transfers
+// 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample
+// Daddr (lower 16 bits) for write transfers
+// 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1,
+// sample Daddr (lower 16 bits) + data for read transfers
+// 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1,
+// sample Daddr (lower 16 bits) + data for write transfers
+//
+// Note 1: If the ETM is not fitted, then ETM trigger is not possible.
+// Note 2: Data value is only sampled for accesses that do not fault (MPU or
+// bus fault). The PC is sampled irrespective of any faults. The PC is only
+// sampled for the first address of a burst.
+// Note 3: PC match is not recommended for watchpoints because it stops after
+// the instruction. It mainly guards and triggers the ETM.
+#define CPU_DWT_FUNCTION3_FUNCTION_W 4
+#define CPU_DWT_FUNCTION3_FUNCTION_M 0x0000000F
+#define CPU_DWT_FUNCTION3_FUNCTION_S 0
+
+
+#endif // __CPU_DWT__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_fpb.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_fpb.h
new file mode 100644
index 0000000..efc475c
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_fpb.h
@@ -0,0 +1,443 @@
+/******************************************************************************
+* Filename: hw_cpu_fpb_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_CPU_FPB_H__
+#define __HW_CPU_FPB_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// CPU_FPB component
+//
+//*****************************************************************************
+// Control
+#define CPU_FPB_O_CTRL 0x00000000
+
+// Remap
+#define CPU_FPB_O_REMAP 0x00000004
+
+// Comparator 0
+#define CPU_FPB_O_COMP0 0x00000008
+
+// Comparator 1
+#define CPU_FPB_O_COMP1 0x0000000C
+
+// Comparator 2
+#define CPU_FPB_O_COMP2 0x00000010
+
+// Comparator 3
+#define CPU_FPB_O_COMP3 0x00000014
+
+// Comparator 4
+#define CPU_FPB_O_COMP4 0x00000018
+
+// Comparator 5
+#define CPU_FPB_O_COMP5 0x0000001C
+
+// Comparator 6
+#define CPU_FPB_O_COMP6 0x00000020
+
+// Comparator 7
+#define CPU_FPB_O_COMP7 0x00000024
+
+//*****************************************************************************
+//
+// Register: CPU_FPB_O_CTRL
+//
+//*****************************************************************************
+// Field: [13:12] NUM_CODE2
+//
+// Number of full banks of code comparators, sixteen comparators per bank.
+// Where less than sixteen code comparators are provided, the bank count is
+// zero, and the number present indicated by NUM_CODE1. This read only field
+// contains 3'b000 to indicate 0 banks for Cortex-M processor.
+#define CPU_FPB_CTRL_NUM_CODE2_W 2
+#define CPU_FPB_CTRL_NUM_CODE2_M 0x00003000
+#define CPU_FPB_CTRL_NUM_CODE2_S 12
+
+// Field: [11:8] NUM_LIT
+//
+// Number of literal slots field.
+//
+// 0x0: No literal slots
+// 0x2: Two literal slots
+#define CPU_FPB_CTRL_NUM_LIT_W 4
+#define CPU_FPB_CTRL_NUM_LIT_M 0x00000F00
+#define CPU_FPB_CTRL_NUM_LIT_S 8
+
+// Field: [7:4] NUM_CODE1
+//
+// Number of code slots field.
+//
+// 0x0: No code slots
+// 0x2: Two code slots
+// 0x6: Six code slots
+#define CPU_FPB_CTRL_NUM_CODE1_W 4
+#define CPU_FPB_CTRL_NUM_CODE1_M 0x000000F0
+#define CPU_FPB_CTRL_NUM_CODE1_S 4
+
+// Field: [1] KEY
+//
+// Key field. In order to write to this register, this bit-field must be
+// written to '1'. This bit always reads 0.
+#define CPU_FPB_CTRL_KEY 0x00000002
+#define CPU_FPB_CTRL_KEY_BITN 1
+#define CPU_FPB_CTRL_KEY_M 0x00000002
+#define CPU_FPB_CTRL_KEY_S 1
+
+// Field: [0] ENABLE
+//
+// Flash patch unit enable bit
+//
+// 0x0: Flash patch unit disabled
+// 0x1: Flash patch unit enabled
+#define CPU_FPB_CTRL_ENABLE 0x00000001
+#define CPU_FPB_CTRL_ENABLE_BITN 0
+#define CPU_FPB_CTRL_ENABLE_M 0x00000001
+#define CPU_FPB_CTRL_ENABLE_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_FPB_O_REMAP
+//
+//*****************************************************************************
+// Field: [28:5] REMAP
+//
+// Remap base address field.
+#define CPU_FPB_REMAP_REMAP_W 24
+#define CPU_FPB_REMAP_REMAP_M 0x1FFFFFE0
+#define CPU_FPB_REMAP_REMAP_S 5
+
+//*****************************************************************************
+//
+// Register: CPU_FPB_O_COMP0
+//
+//*****************************************************************************
+// Field: [31:30] REPLACE
+//
+// This selects what happens when the COMP address is matched. Address
+// remapping only takes place for the 0x0 setting.
+//
+// 0x0: Remap to remap address. See REMAP.REMAP
+// 0x1: Set BKPT on lower halfword, upper is unaffected
+// 0x2: Set BKPT on upper halfword, lower is unaffected
+// 0x3: Set BKPT on both lower and upper halfwords.
+#define CPU_FPB_COMP0_REPLACE_W 2
+#define CPU_FPB_COMP0_REPLACE_M 0xC0000000
+#define CPU_FPB_COMP0_REPLACE_S 30
+
+// Field: [28:2] COMP
+//
+// Comparison address.
+#define CPU_FPB_COMP0_COMP_W 27
+#define CPU_FPB_COMP0_COMP_M 0x1FFFFFFC
+#define CPU_FPB_COMP0_COMP_S 2
+
+// Field: [0] ENABLE
+//
+// Compare and remap enable comparator 0. CTRL.ENABLE must also be set to
+// enable comparisons.
+//
+// 0x0: Compare and remap for comparator 0 disabled
+// 0x1: Compare and remap for comparator 0 enabled
+#define CPU_FPB_COMP0_ENABLE 0x00000001
+#define CPU_FPB_COMP0_ENABLE_BITN 0
+#define CPU_FPB_COMP0_ENABLE_M 0x00000001
+#define CPU_FPB_COMP0_ENABLE_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_FPB_O_COMP1
+//
+//*****************************************************************************
+// Field: [31:30] REPLACE
+//
+// This selects what happens when the COMP address is matched. Address
+// remapping only takes place for the 0x0 setting.
+//
+// 0x0: Remap to remap address. See REMAP.REMAP
+// 0x1: Set BKPT on lower halfword, upper is unaffected
+// 0x2: Set BKPT on upper halfword, lower is unaffected
+// 0x3: Set BKPT on both lower and upper halfwords.
+#define CPU_FPB_COMP1_REPLACE_W 2
+#define CPU_FPB_COMP1_REPLACE_M 0xC0000000
+#define CPU_FPB_COMP1_REPLACE_S 30
+
+// Field: [28:2] COMP
+//
+// Comparison address.
+#define CPU_FPB_COMP1_COMP_W 27
+#define CPU_FPB_COMP1_COMP_M 0x1FFFFFFC
+#define CPU_FPB_COMP1_COMP_S 2
+
+// Field: [0] ENABLE
+//
+// Compare and remap enable comparator 1. CTRL.ENABLE must also be set to
+// enable comparisons.
+//
+// 0x0: Compare and remap for comparator 1 disabled
+// 0x1: Compare and remap for comparator 1 enabled
+#define CPU_FPB_COMP1_ENABLE 0x00000001
+#define CPU_FPB_COMP1_ENABLE_BITN 0
+#define CPU_FPB_COMP1_ENABLE_M 0x00000001
+#define CPU_FPB_COMP1_ENABLE_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_FPB_O_COMP2
+//
+//*****************************************************************************
+// Field: [31:30] REPLACE
+//
+// This selects what happens when the COMP address is matched. Address
+// remapping only takes place for the 0x0 setting.
+//
+// 0x0: Remap to remap address. See REMAP.REMAP
+// 0x1: Set BKPT on lower halfword, upper is unaffected
+// 0x2: Set BKPT on upper halfword, lower is unaffected
+// 0x3: Set BKPT on both lower and upper halfwords.
+#define CPU_FPB_COMP2_REPLACE_W 2
+#define CPU_FPB_COMP2_REPLACE_M 0xC0000000
+#define CPU_FPB_COMP2_REPLACE_S 30
+
+// Field: [28:2] COMP
+//
+// Comparison address.
+#define CPU_FPB_COMP2_COMP_W 27
+#define CPU_FPB_COMP2_COMP_M 0x1FFFFFFC
+#define CPU_FPB_COMP2_COMP_S 2
+
+// Field: [0] ENABLE
+//
+// Compare and remap enable comparator 2. CTRL.ENABLE must also be set to
+// enable comparisons.
+//
+// 0x0: Compare and remap for comparator 2 disabled
+// 0x1: Compare and remap for comparator 2 enabled
+#define CPU_FPB_COMP2_ENABLE 0x00000001
+#define CPU_FPB_COMP2_ENABLE_BITN 0
+#define CPU_FPB_COMP2_ENABLE_M 0x00000001
+#define CPU_FPB_COMP2_ENABLE_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_FPB_O_COMP3
+//
+//*****************************************************************************
+// Field: [31:30] REPLACE
+//
+// This selects what happens when the COMP address is matched. Address
+// remapping only takes place for the 0x0 setting.
+//
+// 0x0: Remap to remap address. See REMAP.REMAP
+// 0x1: Set BKPT on lower halfword, upper is unaffected
+// 0x2: Set BKPT on upper halfword, lower is unaffected
+// 0x3: Set BKPT on both lower and upper halfwords.
+#define CPU_FPB_COMP3_REPLACE_W 2
+#define CPU_FPB_COMP3_REPLACE_M 0xC0000000
+#define CPU_FPB_COMP3_REPLACE_S 30
+
+// Field: [28:2] COMP
+//
+// Comparison address.
+#define CPU_FPB_COMP3_COMP_W 27
+#define CPU_FPB_COMP3_COMP_M 0x1FFFFFFC
+#define CPU_FPB_COMP3_COMP_S 2
+
+// Field: [0] ENABLE
+//
+// Compare and remap enable comparator 3. CTRL.ENABLE must also be set to
+// enable comparisons.
+//
+// 0x0: Compare and remap for comparator 3 disabled
+// 0x1: Compare and remap for comparator 3 enabled
+#define CPU_FPB_COMP3_ENABLE 0x00000001
+#define CPU_FPB_COMP3_ENABLE_BITN 0
+#define CPU_FPB_COMP3_ENABLE_M 0x00000001
+#define CPU_FPB_COMP3_ENABLE_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_FPB_O_COMP4
+//
+//*****************************************************************************
+// Field: [31:30] REPLACE
+//
+// This selects what happens when the COMP address is matched. Address
+// remapping only takes place for the 0x0 setting.
+//
+// 0x0: Remap to remap address. See REMAP.REMAP
+// 0x1: Set BKPT on lower halfword, upper is unaffected
+// 0x2: Set BKPT on upper halfword, lower is unaffected
+// 0x3: Set BKPT on both lower and upper halfwords.
+#define CPU_FPB_COMP4_REPLACE_W 2
+#define CPU_FPB_COMP4_REPLACE_M 0xC0000000
+#define CPU_FPB_COMP4_REPLACE_S 30
+
+// Field: [28:2] COMP
+//
+// Comparison address.
+#define CPU_FPB_COMP4_COMP_W 27
+#define CPU_FPB_COMP4_COMP_M 0x1FFFFFFC
+#define CPU_FPB_COMP4_COMP_S 2
+
+// Field: [0] ENABLE
+//
+// Compare and remap enable comparator 4. CTRL.ENABLE must also be set to
+// enable comparisons.
+//
+// 0x0: Compare and remap for comparator 4 disabled
+// 0x1: Compare and remap for comparator 4 enabled
+#define CPU_FPB_COMP4_ENABLE 0x00000001
+#define CPU_FPB_COMP4_ENABLE_BITN 0
+#define CPU_FPB_COMP4_ENABLE_M 0x00000001
+#define CPU_FPB_COMP4_ENABLE_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_FPB_O_COMP5
+//
+//*****************************************************************************
+// Field: [31:30] REPLACE
+//
+// This selects what happens when the COMP address is matched. Address
+// remapping only takes place for the 0x0 setting.
+//
+// 0x0: Remap to remap address. See REMAP.REMAP
+// 0x1: Set BKPT on lower halfword, upper is unaffected
+// 0x2: Set BKPT on upper halfword, lower is unaffected
+// 0x3: Set BKPT on both lower and upper halfwords.
+#define CPU_FPB_COMP5_REPLACE_W 2
+#define CPU_FPB_COMP5_REPLACE_M 0xC0000000
+#define CPU_FPB_COMP5_REPLACE_S 30
+
+// Field: [28:2] COMP
+//
+// Comparison address.
+#define CPU_FPB_COMP5_COMP_W 27
+#define CPU_FPB_COMP5_COMP_M 0x1FFFFFFC
+#define CPU_FPB_COMP5_COMP_S 2
+
+// Field: [0] ENABLE
+//
+// Compare and remap enable comparator 5. CTRL.ENABLE must also be set to
+// enable comparisons.
+//
+// 0x0: Compare and remap for comparator 5 disabled
+// 0x1: Compare and remap for comparator 5 enabled
+#define CPU_FPB_COMP5_ENABLE 0x00000001
+#define CPU_FPB_COMP5_ENABLE_BITN 0
+#define CPU_FPB_COMP5_ENABLE_M 0x00000001
+#define CPU_FPB_COMP5_ENABLE_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_FPB_O_COMP6
+//
+//*****************************************************************************
+// Field: [31:30] REPLACE
+//
+// This selects what happens when the COMP address is matched. Comparator 6 is
+// a literal comparator and the only supported setting is 0x0. Other settings
+// will be ignored.
+//
+// 0x0: Remap to remap address. See REMAP.REMAP
+// 0x1: Set BKPT on lower halfword, upper is unaffected
+// 0x2: Set BKPT on upper halfword, lower is unaffected
+// 0x3: Set BKPT on both lower and upper halfwords.
+#define CPU_FPB_COMP6_REPLACE_W 2
+#define CPU_FPB_COMP6_REPLACE_M 0xC0000000
+#define CPU_FPB_COMP6_REPLACE_S 30
+
+// Field: [28:2] COMP
+//
+// Comparison address.
+#define CPU_FPB_COMP6_COMP_W 27
+#define CPU_FPB_COMP6_COMP_M 0x1FFFFFFC
+#define CPU_FPB_COMP6_COMP_S 2
+
+// Field: [0] ENABLE
+//
+// Compare and remap enable comparator 6. CTRL.ENABLE must also be set to
+// enable comparisons.
+//
+// 0x0: Compare and remap for comparator 6 disabled
+// 0x1: Compare and remap for comparator 6 enabled
+#define CPU_FPB_COMP6_ENABLE 0x00000001
+#define CPU_FPB_COMP6_ENABLE_BITN 0
+#define CPU_FPB_COMP6_ENABLE_M 0x00000001
+#define CPU_FPB_COMP6_ENABLE_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_FPB_O_COMP7
+//
+//*****************************************************************************
+// Field: [31:30] REPLACE
+//
+// This selects what happens when the COMP address is matched. Comparator 7 is
+// a literal comparator and the only supported setting is 0x0. Other settings
+// will be ignored.
+//
+// 0x0: Remap to remap address. See REMAP.REMAP
+// 0x1: Set BKPT on lower halfword, upper is unaffected
+// 0x2: Set BKPT on upper halfword, lower is unaffected
+// 0x3: Set BKPT on both lower and upper halfwords.
+#define CPU_FPB_COMP7_REPLACE_W 2
+#define CPU_FPB_COMP7_REPLACE_M 0xC0000000
+#define CPU_FPB_COMP7_REPLACE_S 30
+
+// Field: [28:2] COMP
+//
+// Comparison address.
+#define CPU_FPB_COMP7_COMP_W 27
+#define CPU_FPB_COMP7_COMP_M 0x1FFFFFFC
+#define CPU_FPB_COMP7_COMP_S 2
+
+// Field: [0] ENABLE
+//
+// Compare and remap enable comparator 7. CTRL.ENABLE must also be set to
+// enable comparisons.
+//
+// 0x0: Compare and remap for comparator 7 disabled
+// 0x1: Compare and remap for comparator 7 enabled
+#define CPU_FPB_COMP7_ENABLE 0x00000001
+#define CPU_FPB_COMP7_ENABLE_BITN 0
+#define CPU_FPB_COMP7_ENABLE_M 0x00000001
+#define CPU_FPB_COMP7_ENABLE_S 0
+
+
+#endif // __CPU_FPB__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_itm.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_itm.h
new file mode 100644
index 0000000..430c0b0
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_itm.h
@@ -0,0 +1,1122 @@
+/******************************************************************************
+* Filename: hw_cpu_itm_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_CPU_ITM_H__
+#define __HW_CPU_ITM_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// CPU_ITM component
+//
+//*****************************************************************************
+// Stimulus Port 0
+#define CPU_ITM_O_STIM0 0x00000000
+
+// Stimulus Port 1
+#define CPU_ITM_O_STIM1 0x00000004
+
+// Stimulus Port 2
+#define CPU_ITM_O_STIM2 0x00000008
+
+// Stimulus Port 3
+#define CPU_ITM_O_STIM3 0x0000000C
+
+// Stimulus Port 4
+#define CPU_ITM_O_STIM4 0x00000010
+
+// Stimulus Port 5
+#define CPU_ITM_O_STIM5 0x00000014
+
+// Stimulus Port 6
+#define CPU_ITM_O_STIM6 0x00000018
+
+// Stimulus Port 7
+#define CPU_ITM_O_STIM7 0x0000001C
+
+// Stimulus Port 8
+#define CPU_ITM_O_STIM8 0x00000020
+
+// Stimulus Port 9
+#define CPU_ITM_O_STIM9 0x00000024
+
+// Stimulus Port 10
+#define CPU_ITM_O_STIM10 0x00000028
+
+// Stimulus Port 11
+#define CPU_ITM_O_STIM11 0x0000002C
+
+// Stimulus Port 12
+#define CPU_ITM_O_STIM12 0x00000030
+
+// Stimulus Port 13
+#define CPU_ITM_O_STIM13 0x00000034
+
+// Stimulus Port 14
+#define CPU_ITM_O_STIM14 0x00000038
+
+// Stimulus Port 15
+#define CPU_ITM_O_STIM15 0x0000003C
+
+// Stimulus Port 16
+#define CPU_ITM_O_STIM16 0x00000040
+
+// Stimulus Port 17
+#define CPU_ITM_O_STIM17 0x00000044
+
+// Stimulus Port 18
+#define CPU_ITM_O_STIM18 0x00000048
+
+// Stimulus Port 19
+#define CPU_ITM_O_STIM19 0x0000004C
+
+// Stimulus Port 20
+#define CPU_ITM_O_STIM20 0x00000050
+
+// Stimulus Port 21
+#define CPU_ITM_O_STIM21 0x00000054
+
+// Stimulus Port 22
+#define CPU_ITM_O_STIM22 0x00000058
+
+// Stimulus Port 23
+#define CPU_ITM_O_STIM23 0x0000005C
+
+// Stimulus Port 24
+#define CPU_ITM_O_STIM24 0x00000060
+
+// Stimulus Port 25
+#define CPU_ITM_O_STIM25 0x00000064
+
+// Stimulus Port 26
+#define CPU_ITM_O_STIM26 0x00000068
+
+// Stimulus Port 27
+#define CPU_ITM_O_STIM27 0x0000006C
+
+// Stimulus Port 28
+#define CPU_ITM_O_STIM28 0x00000070
+
+// Stimulus Port 29
+#define CPU_ITM_O_STIM29 0x00000074
+
+// Stimulus Port 30
+#define CPU_ITM_O_STIM30 0x00000078
+
+// Stimulus Port 31
+#define CPU_ITM_O_STIM31 0x0000007C
+
+// Trace Enable
+#define CPU_ITM_O_TER 0x00000E00
+
+// Trace Privilege
+#define CPU_ITM_O_TPR 0x00000E40
+
+// Trace Control
+#define CPU_ITM_O_TCR 0x00000E80
+
+// Lock Access
+#define CPU_ITM_O_LAR 0x00000FB0
+
+// Lock Status
+#define CPU_ITM_O_LSR 0x00000FB4
+
+//*****************************************************************************
+//
+// Register: CPU_ITM_O_STIM0
+//
+//*****************************************************************************
+// Field: [31:0] STIM0
+//
+// A write to this location causes data to be written into the FIFO if
+// TER.STIMENA0 is set. Reading from the stimulus port returns the FIFO status
+// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
+// provide an atomic read-modify-write, so it's users responsibility to ensure
+// exclusive read-modify-write if this ITM port is used concurrently by
+// interrupts or other threads.
+#define CPU_ITM_STIM0_STIM0_W 32
+#define CPU_ITM_STIM0_STIM0_M 0xFFFFFFFF
+#define CPU_ITM_STIM0_STIM0_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ITM_O_STIM1
+//
+//*****************************************************************************
+// Field: [31:0] STIM1
+//
+// A write to this location causes data to be written into the FIFO if
+// TER.STIMENA1 is set. Reading from the stimulus port returns the FIFO status
+// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
+// provide an atomic read-modify-write, so it's users responsibility to ensure
+// exclusive read-modify-write if this ITM port is used concurrently by
+// interrupts or other threads.
+#define CPU_ITM_STIM1_STIM1_W 32
+#define CPU_ITM_STIM1_STIM1_M 0xFFFFFFFF
+#define CPU_ITM_STIM1_STIM1_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ITM_O_STIM2
+//
+//*****************************************************************************
+// Field: [31:0] STIM2
+//
+// A write to this location causes data to be written into the FIFO if
+// TER.STIMENA2 is set. Reading from the stimulus port returns the FIFO status
+// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
+// provide an atomic read-modify-write, so it's users responsibility to ensure
+// exclusive read-modify-write if this ITM port is used concurrently by
+// interrupts or other threads.
+#define CPU_ITM_STIM2_STIM2_W 32
+#define CPU_ITM_STIM2_STIM2_M 0xFFFFFFFF
+#define CPU_ITM_STIM2_STIM2_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ITM_O_STIM3
+//
+//*****************************************************************************
+// Field: [31:0] STIM3
+//
+// A write to this location causes data to be written into the FIFO if
+// TER.STIMENA3 is set. Reading from the stimulus port returns the FIFO status
+// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
+// provide an atomic read-modify-write, so it's users responsibility to ensure
+// exclusive read-modify-write if this ITM port is used concurrently by
+// interrupts or other threads.
+#define CPU_ITM_STIM3_STIM3_W 32
+#define CPU_ITM_STIM3_STIM3_M 0xFFFFFFFF
+#define CPU_ITM_STIM3_STIM3_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ITM_O_STIM4
+//
+//*****************************************************************************
+// Field: [31:0] STIM4
+//
+// A write to this location causes data to be written into the FIFO if
+// TER.STIMENA4 is set. Reading from the stimulus port returns the FIFO status
+// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
+// provide an atomic read-modify-write, so it's users responsibility to ensure
+// exclusive read-modify-write if this ITM port is used concurrently by
+// interrupts or other threads.
+#define CPU_ITM_STIM4_STIM4_W 32
+#define CPU_ITM_STIM4_STIM4_M 0xFFFFFFFF
+#define CPU_ITM_STIM4_STIM4_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ITM_O_STIM5
+//
+//*****************************************************************************
+// Field: [31:0] STIM5
+//
+// A write to this location causes data to be written into the FIFO if
+// TER.STIMENA5 is set. Reading from the stimulus port returns the FIFO status
+// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
+// provide an atomic read-modify-write, so it's users responsibility to ensure
+// exclusive read-modify-write if this ITM port is used concurrently by
+// interrupts or other threads.
+#define CPU_ITM_STIM5_STIM5_W 32
+#define CPU_ITM_STIM5_STIM5_M 0xFFFFFFFF
+#define CPU_ITM_STIM5_STIM5_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ITM_O_STIM6
+//
+//*****************************************************************************
+// Field: [31:0] STIM6
+//
+// A write to this location causes data to be written into the FIFO if
+// TER.STIMENA6 is set. Reading from the stimulus port returns the FIFO status
+// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
+// provide an atomic read-modify-write, so it's users responsibility to ensure
+// exclusive read-modify-write if this ITM port is used concurrently by
+// interrupts or other threads.
+#define CPU_ITM_STIM6_STIM6_W 32
+#define CPU_ITM_STIM6_STIM6_M 0xFFFFFFFF
+#define CPU_ITM_STIM6_STIM6_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ITM_O_STIM7
+//
+//*****************************************************************************
+// Field: [31:0] STIM7
+//
+// A write to this location causes data to be written into the FIFO if
+// TER.STIMENA7 is set. Reading from the stimulus port returns the FIFO status
+// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
+// provide an atomic read-modify-write, so it's users responsibility to ensure
+// exclusive read-modify-write if this ITM port is used concurrently by
+// interrupts or other threads.
+#define CPU_ITM_STIM7_STIM7_W 32
+#define CPU_ITM_STIM7_STIM7_M 0xFFFFFFFF
+#define CPU_ITM_STIM7_STIM7_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ITM_O_STIM8
+//
+//*****************************************************************************
+// Field: [31:0] STIM8
+//
+// A write to this location causes data to be written into the FIFO if
+// TER.STIMENA8 is set. Reading from the stimulus port returns the FIFO status
+// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
+// provide an atomic read-modify-write, so it's users responsibility to ensure
+// exclusive read-modify-write if this ITM port is used concurrently by
+// interrupts or other threads.
+#define CPU_ITM_STIM8_STIM8_W 32
+#define CPU_ITM_STIM8_STIM8_M 0xFFFFFFFF
+#define CPU_ITM_STIM8_STIM8_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ITM_O_STIM9
+//
+//*****************************************************************************
+// Field: [31:0] STIM9
+//
+// A write to this location causes data to be written into the FIFO if
+// TER.STIMENA9 is set. Reading from the stimulus port returns the FIFO status
+// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
+// provide an atomic read-modify-write, so it's users responsibility to ensure
+// exclusive read-modify-write if this ITM port is used concurrently by
+// interrupts or other threads.
+#define CPU_ITM_STIM9_STIM9_W 32
+#define CPU_ITM_STIM9_STIM9_M 0xFFFFFFFF
+#define CPU_ITM_STIM9_STIM9_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ITM_O_STIM10
+//
+//*****************************************************************************
+// Field: [31:0] STIM10
+//
+// A write to this location causes data to be written into the FIFO if
+// TER.STIMENA10 is set. Reading from the stimulus port returns the FIFO status
+// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
+// provide an atomic read-modify-write, so it's users responsibility to ensure
+// exclusive read-modify-write if this ITM port is used concurrently by
+// interrupts or other threads.
+#define CPU_ITM_STIM10_STIM10_W 32
+#define CPU_ITM_STIM10_STIM10_M 0xFFFFFFFF
+#define CPU_ITM_STIM10_STIM10_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ITM_O_STIM11
+//
+//*****************************************************************************
+// Field: [31:0] STIM11
+//
+// A write to this location causes data to be written into the FIFO if
+// TER.STIMENA11 is set. Reading from the stimulus port returns the FIFO status
+// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
+// provide an atomic read-modify-write, so it's users responsibility to ensure
+// exclusive read-modify-write if this ITM port is used concurrently by
+// interrupts or other threads.
+#define CPU_ITM_STIM11_STIM11_W 32
+#define CPU_ITM_STIM11_STIM11_M 0xFFFFFFFF
+#define CPU_ITM_STIM11_STIM11_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ITM_O_STIM12
+//
+//*****************************************************************************
+// Field: [31:0] STIM12
+//
+// A write to this location causes data to be written into the FIFO if
+// TER.STIMENA12 is set. Reading from the stimulus port returns the FIFO status
+// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
+// provide an atomic read-modify-write, so it's users responsibility to ensure
+// exclusive read-modify-write if this ITM port is used concurrently by
+// interrupts or other threads.
+#define CPU_ITM_STIM12_STIM12_W 32
+#define CPU_ITM_STIM12_STIM12_M 0xFFFFFFFF
+#define CPU_ITM_STIM12_STIM12_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ITM_O_STIM13
+//
+//*****************************************************************************
+// Field: [31:0] STIM13
+//
+// A write to this location causes data to be written into the FIFO if
+// TER.STIMENA13 is set. Reading from the stimulus port returns the FIFO status
+// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
+// provide an atomic read-modify-write, so it's users responsibility to ensure
+// exclusive read-modify-write if this ITM port is used concurrently by
+// interrupts or other threads.
+#define CPU_ITM_STIM13_STIM13_W 32
+#define CPU_ITM_STIM13_STIM13_M 0xFFFFFFFF
+#define CPU_ITM_STIM13_STIM13_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ITM_O_STIM14
+//
+//*****************************************************************************
+// Field: [31:0] STIM14
+//
+// A write to this location causes data to be written into the FIFO if
+// TER.STIMENA14 is set. Reading from the stimulus port returns the FIFO status
+// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
+// provide an atomic read-modify-write, so it's users responsibility to ensure
+// exclusive read-modify-write if this ITM port is used concurrently by
+// interrupts or other threads.
+#define CPU_ITM_STIM14_STIM14_W 32
+#define CPU_ITM_STIM14_STIM14_M 0xFFFFFFFF
+#define CPU_ITM_STIM14_STIM14_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ITM_O_STIM15
+//
+//*****************************************************************************
+// Field: [31:0] STIM15
+//
+// A write to this location causes data to be written into the FIFO if
+// TER.STIMENA15 is set. Reading from the stimulus port returns the FIFO status
+// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
+// provide an atomic read-modify-write, so it's users responsibility to ensure
+// exclusive read-modify-write if this ITM port is used concurrently by
+// interrupts or other threads.
+#define CPU_ITM_STIM15_STIM15_W 32
+#define CPU_ITM_STIM15_STIM15_M 0xFFFFFFFF
+#define CPU_ITM_STIM15_STIM15_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ITM_O_STIM16
+//
+//*****************************************************************************
+// Field: [31:0] STIM16
+//
+// A write to this location causes data to be written into the FIFO if
+// TER.STIMENA16 is set. Reading from the stimulus port returns the FIFO status
+// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
+// provide an atomic read-modify-write, so it's users responsibility to ensure
+// exclusive read-modify-write if this ITM port is used concurrently by
+// interrupts or other threads.
+#define CPU_ITM_STIM16_STIM16_W 32
+#define CPU_ITM_STIM16_STIM16_M 0xFFFFFFFF
+#define CPU_ITM_STIM16_STIM16_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ITM_O_STIM17
+//
+//*****************************************************************************
+// Field: [31:0] STIM17
+//
+// A write to this location causes data to be written into the FIFO if
+// TER.STIMENA17 is set. Reading from the stimulus port returns the FIFO status
+// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
+// provide an atomic read-modify-write, so it's users responsibility to ensure
+// exclusive read-modify-write if this ITM port is used concurrently by
+// interrupts or other threads.
+#define CPU_ITM_STIM17_STIM17_W 32
+#define CPU_ITM_STIM17_STIM17_M 0xFFFFFFFF
+#define CPU_ITM_STIM17_STIM17_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ITM_O_STIM18
+//
+//*****************************************************************************
+// Field: [31:0] STIM18
+//
+// A write to this location causes data to be written into the FIFO if
+// TER.STIMENA18 is set. Reading from the stimulus port returns the FIFO status
+// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
+// provide an atomic read-modify-write, so it's users responsibility to ensure
+// exclusive read-modify-write if this ITM port is used concurrently by
+// interrupts or other threads.
+#define CPU_ITM_STIM18_STIM18_W 32
+#define CPU_ITM_STIM18_STIM18_M 0xFFFFFFFF
+#define CPU_ITM_STIM18_STIM18_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ITM_O_STIM19
+//
+//*****************************************************************************
+// Field: [31:0] STIM19
+//
+// A write to this location causes data to be written into the FIFO if
+// TER.STIMENA19 is set. Reading from the stimulus port returns the FIFO status
+// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
+// provide an atomic read-modify-write, so it's users responsibility to ensure
+// exclusive read-modify-write if this ITM port is used concurrently by
+// interrupts or other threads.
+#define CPU_ITM_STIM19_STIM19_W 32
+#define CPU_ITM_STIM19_STIM19_M 0xFFFFFFFF
+#define CPU_ITM_STIM19_STIM19_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ITM_O_STIM20
+//
+//*****************************************************************************
+// Field: [31:0] STIM20
+//
+// A write to this location causes data to be written into the FIFO if
+// TER.STIMENA20 is set. Reading from the stimulus port returns the FIFO status
+// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
+// provide an atomic read-modify-write, so it's users responsibility to ensure
+// exclusive read-modify-write if this ITM port is used concurrently by
+// interrupts or other threads.
+#define CPU_ITM_STIM20_STIM20_W 32
+#define CPU_ITM_STIM20_STIM20_M 0xFFFFFFFF
+#define CPU_ITM_STIM20_STIM20_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ITM_O_STIM21
+//
+//*****************************************************************************
+// Field: [31:0] STIM21
+//
+// A write to this location causes data to be written into the FIFO if
+// TER.STIMENA21 is set. Reading from the stimulus port returns the FIFO status
+// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
+// provide an atomic read-modify-write, so it's users responsibility to ensure
+// exclusive read-modify-write if this ITM port is used concurrently by
+// interrupts or other threads.
+#define CPU_ITM_STIM21_STIM21_W 32
+#define CPU_ITM_STIM21_STIM21_M 0xFFFFFFFF
+#define CPU_ITM_STIM21_STIM21_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ITM_O_STIM22
+//
+//*****************************************************************************
+// Field: [31:0] STIM22
+//
+// A write to this location causes data to be written into the FIFO if
+// TER.STIMENA22 is set. Reading from the stimulus port returns the FIFO status
+// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
+// provide an atomic read-modify-write, so it's users responsibility to ensure
+// exclusive read-modify-write if this ITM port is used concurrently by
+// interrupts or other threads.
+#define CPU_ITM_STIM22_STIM22_W 32
+#define CPU_ITM_STIM22_STIM22_M 0xFFFFFFFF
+#define CPU_ITM_STIM22_STIM22_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ITM_O_STIM23
+//
+//*****************************************************************************
+// Field: [31:0] STIM23
+//
+// A write to this location causes data to be written into the FIFO if
+// TER.STIMENA23 is set. Reading from the stimulus port returns the FIFO status
+// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
+// provide an atomic read-modify-write, so it's users responsibility to ensure
+// exclusive read-modify-write if this ITM port is used concurrently by
+// interrupts or other threads.
+#define CPU_ITM_STIM23_STIM23_W 32
+#define CPU_ITM_STIM23_STIM23_M 0xFFFFFFFF
+#define CPU_ITM_STIM23_STIM23_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ITM_O_STIM24
+//
+//*****************************************************************************
+// Field: [31:0] STIM24
+//
+// A write to this location causes data to be written into the FIFO if
+// TER.STIMENA24 is set. Reading from the stimulus port returns the FIFO status
+// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
+// provide an atomic read-modify-write, so it's users responsibility to ensure
+// exclusive read-modify-write if this ITM port is used concurrently by
+// interrupts or other threads.
+#define CPU_ITM_STIM24_STIM24_W 32
+#define CPU_ITM_STIM24_STIM24_M 0xFFFFFFFF
+#define CPU_ITM_STIM24_STIM24_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ITM_O_STIM25
+//
+//*****************************************************************************
+// Field: [31:0] STIM25
+//
+// A write to this location causes data to be written into the FIFO if
+// TER.STIMENA25 is set. Reading from the stimulus port returns the FIFO status
+// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
+// provide an atomic read-modify-write, so it's users responsibility to ensure
+// exclusive read-modify-write if this ITM port is used concurrently by
+// interrupts or other threads.
+#define CPU_ITM_STIM25_STIM25_W 32
+#define CPU_ITM_STIM25_STIM25_M 0xFFFFFFFF
+#define CPU_ITM_STIM25_STIM25_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ITM_O_STIM26
+//
+//*****************************************************************************
+// Field: [31:0] STIM26
+//
+// A write to this location causes data to be written into the FIFO if
+// TER.STIMENA26 is set. Reading from the stimulus port returns the FIFO status
+// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
+// provide an atomic read-modify-write, so it's users responsibility to ensure
+// exclusive read-modify-write if this ITM port is used concurrently by
+// interrupts or other threads.
+#define CPU_ITM_STIM26_STIM26_W 32
+#define CPU_ITM_STIM26_STIM26_M 0xFFFFFFFF
+#define CPU_ITM_STIM26_STIM26_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ITM_O_STIM27
+//
+//*****************************************************************************
+// Field: [31:0] STIM27
+//
+// A write to this location causes data to be written into the FIFO if
+// TER.STIMENA27 is set. Reading from the stimulus port returns the FIFO status
+// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
+// provide an atomic read-modify-write, so it's users responsibility to ensure
+// exclusive read-modify-write if this ITM port is used concurrently by
+// interrupts or other threads.
+#define CPU_ITM_STIM27_STIM27_W 32
+#define CPU_ITM_STIM27_STIM27_M 0xFFFFFFFF
+#define CPU_ITM_STIM27_STIM27_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ITM_O_STIM28
+//
+//*****************************************************************************
+// Field: [31:0] STIM28
+//
+// A write to this location causes data to be written into the FIFO if
+// TER.STIMENA28 is set. Reading from the stimulus port returns the FIFO status
+// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
+// provide an atomic read-modify-write, so it's users responsibility to ensure
+// exclusive read-modify-write if this ITM port is used concurrently by
+// interrupts or other threads.
+#define CPU_ITM_STIM28_STIM28_W 32
+#define CPU_ITM_STIM28_STIM28_M 0xFFFFFFFF
+#define CPU_ITM_STIM28_STIM28_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ITM_O_STIM29
+//
+//*****************************************************************************
+// Field: [31:0] STIM29
+//
+// A write to this location causes data to be written into the FIFO if
+// TER.STIMENA29 is set. Reading from the stimulus port returns the FIFO status
+// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
+// provide an atomic read-modify-write, so it's users responsibility to ensure
+// exclusive read-modify-write if this ITM port is used concurrently by
+// interrupts or other threads.
+#define CPU_ITM_STIM29_STIM29_W 32
+#define CPU_ITM_STIM29_STIM29_M 0xFFFFFFFF
+#define CPU_ITM_STIM29_STIM29_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ITM_O_STIM30
+//
+//*****************************************************************************
+// Field: [31:0] STIM30
+//
+// A write to this location causes data to be written into the FIFO if
+// TER.STIMENA30 is set. Reading from the stimulus port returns the FIFO status
+// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
+// provide an atomic read-modify-write, so it's users responsibility to ensure
+// exclusive read-modify-write if this ITM port is used concurrently by
+// interrupts or other threads.
+#define CPU_ITM_STIM30_STIM30_W 32
+#define CPU_ITM_STIM30_STIM30_M 0xFFFFFFFF
+#define CPU_ITM_STIM30_STIM30_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ITM_O_STIM31
+//
+//*****************************************************************************
+// Field: [31:0] STIM31
+//
+// A write to this location causes data to be written into the FIFO if
+// TER.STIMENA31 is set. Reading from the stimulus port returns the FIFO status
+// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not
+// provide an atomic read-modify-write, so it's users responsibility to ensure
+// exclusive read-modify-write if this ITM port is used concurrently by
+// interrupts or other threads.
+#define CPU_ITM_STIM31_STIM31_W 32
+#define CPU_ITM_STIM31_STIM31_M 0xFFFFFFFF
+#define CPU_ITM_STIM31_STIM31_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ITM_O_TER
+//
+//*****************************************************************************
+// Field: [31] STIMENA31
+//
+// Bit mask to enable tracing on ITM stimulus port 31.
+#define CPU_ITM_TER_STIMENA31 0x80000000
+#define CPU_ITM_TER_STIMENA31_BITN 31
+#define CPU_ITM_TER_STIMENA31_M 0x80000000
+#define CPU_ITM_TER_STIMENA31_S 31
+
+// Field: [30] STIMENA30
+//
+// Bit mask to enable tracing on ITM stimulus port 30.
+#define CPU_ITM_TER_STIMENA30 0x40000000
+#define CPU_ITM_TER_STIMENA30_BITN 30
+#define CPU_ITM_TER_STIMENA30_M 0x40000000
+#define CPU_ITM_TER_STIMENA30_S 30
+
+// Field: [29] STIMENA29
+//
+// Bit mask to enable tracing on ITM stimulus port 29.
+#define CPU_ITM_TER_STIMENA29 0x20000000
+#define CPU_ITM_TER_STIMENA29_BITN 29
+#define CPU_ITM_TER_STIMENA29_M 0x20000000
+#define CPU_ITM_TER_STIMENA29_S 29
+
+// Field: [28] STIMENA28
+//
+// Bit mask to enable tracing on ITM stimulus port 28.
+#define CPU_ITM_TER_STIMENA28 0x10000000
+#define CPU_ITM_TER_STIMENA28_BITN 28
+#define CPU_ITM_TER_STIMENA28_M 0x10000000
+#define CPU_ITM_TER_STIMENA28_S 28
+
+// Field: [27] STIMENA27
+//
+// Bit mask to enable tracing on ITM stimulus port 27.
+#define CPU_ITM_TER_STIMENA27 0x08000000
+#define CPU_ITM_TER_STIMENA27_BITN 27
+#define CPU_ITM_TER_STIMENA27_M 0x08000000
+#define CPU_ITM_TER_STIMENA27_S 27
+
+// Field: [26] STIMENA26
+//
+// Bit mask to enable tracing on ITM stimulus port 26.
+#define CPU_ITM_TER_STIMENA26 0x04000000
+#define CPU_ITM_TER_STIMENA26_BITN 26
+#define CPU_ITM_TER_STIMENA26_M 0x04000000
+#define CPU_ITM_TER_STIMENA26_S 26
+
+// Field: [25] STIMENA25
+//
+// Bit mask to enable tracing on ITM stimulus port 25.
+#define CPU_ITM_TER_STIMENA25 0x02000000
+#define CPU_ITM_TER_STIMENA25_BITN 25
+#define CPU_ITM_TER_STIMENA25_M 0x02000000
+#define CPU_ITM_TER_STIMENA25_S 25
+
+// Field: [24] STIMENA24
+//
+// Bit mask to enable tracing on ITM stimulus port 24.
+#define CPU_ITM_TER_STIMENA24 0x01000000
+#define CPU_ITM_TER_STIMENA24_BITN 24
+#define CPU_ITM_TER_STIMENA24_M 0x01000000
+#define CPU_ITM_TER_STIMENA24_S 24
+
+// Field: [23] STIMENA23
+//
+// Bit mask to enable tracing on ITM stimulus port 23.
+#define CPU_ITM_TER_STIMENA23 0x00800000
+#define CPU_ITM_TER_STIMENA23_BITN 23
+#define CPU_ITM_TER_STIMENA23_M 0x00800000
+#define CPU_ITM_TER_STIMENA23_S 23
+
+// Field: [22] STIMENA22
+//
+// Bit mask to enable tracing on ITM stimulus port 22.
+#define CPU_ITM_TER_STIMENA22 0x00400000
+#define CPU_ITM_TER_STIMENA22_BITN 22
+#define CPU_ITM_TER_STIMENA22_M 0x00400000
+#define CPU_ITM_TER_STIMENA22_S 22
+
+// Field: [21] STIMENA21
+//
+// Bit mask to enable tracing on ITM stimulus port 21.
+#define CPU_ITM_TER_STIMENA21 0x00200000
+#define CPU_ITM_TER_STIMENA21_BITN 21
+#define CPU_ITM_TER_STIMENA21_M 0x00200000
+#define CPU_ITM_TER_STIMENA21_S 21
+
+// Field: [20] STIMENA20
+//
+// Bit mask to enable tracing on ITM stimulus port 20.
+#define CPU_ITM_TER_STIMENA20 0x00100000
+#define CPU_ITM_TER_STIMENA20_BITN 20
+#define CPU_ITM_TER_STIMENA20_M 0x00100000
+#define CPU_ITM_TER_STIMENA20_S 20
+
+// Field: [19] STIMENA19
+//
+// Bit mask to enable tracing on ITM stimulus port 19.
+#define CPU_ITM_TER_STIMENA19 0x00080000
+#define CPU_ITM_TER_STIMENA19_BITN 19
+#define CPU_ITM_TER_STIMENA19_M 0x00080000
+#define CPU_ITM_TER_STIMENA19_S 19
+
+// Field: [18] STIMENA18
+//
+// Bit mask to enable tracing on ITM stimulus port 18.
+#define CPU_ITM_TER_STIMENA18 0x00040000
+#define CPU_ITM_TER_STIMENA18_BITN 18
+#define CPU_ITM_TER_STIMENA18_M 0x00040000
+#define CPU_ITM_TER_STIMENA18_S 18
+
+// Field: [17] STIMENA17
+//
+// Bit mask to enable tracing on ITM stimulus port 17.
+#define CPU_ITM_TER_STIMENA17 0x00020000
+#define CPU_ITM_TER_STIMENA17_BITN 17
+#define CPU_ITM_TER_STIMENA17_M 0x00020000
+#define CPU_ITM_TER_STIMENA17_S 17
+
+// Field: [16] STIMENA16
+//
+// Bit mask to enable tracing on ITM stimulus port 16.
+#define CPU_ITM_TER_STIMENA16 0x00010000
+#define CPU_ITM_TER_STIMENA16_BITN 16
+#define CPU_ITM_TER_STIMENA16_M 0x00010000
+#define CPU_ITM_TER_STIMENA16_S 16
+
+// Field: [15] STIMENA15
+//
+// Bit mask to enable tracing on ITM stimulus port 15.
+#define CPU_ITM_TER_STIMENA15 0x00008000
+#define CPU_ITM_TER_STIMENA15_BITN 15
+#define CPU_ITM_TER_STIMENA15_M 0x00008000
+#define CPU_ITM_TER_STIMENA15_S 15
+
+// Field: [14] STIMENA14
+//
+// Bit mask to enable tracing on ITM stimulus port 14.
+#define CPU_ITM_TER_STIMENA14 0x00004000
+#define CPU_ITM_TER_STIMENA14_BITN 14
+#define CPU_ITM_TER_STIMENA14_M 0x00004000
+#define CPU_ITM_TER_STIMENA14_S 14
+
+// Field: [13] STIMENA13
+//
+// Bit mask to enable tracing on ITM stimulus port 13.
+#define CPU_ITM_TER_STIMENA13 0x00002000
+#define CPU_ITM_TER_STIMENA13_BITN 13
+#define CPU_ITM_TER_STIMENA13_M 0x00002000
+#define CPU_ITM_TER_STIMENA13_S 13
+
+// Field: [12] STIMENA12
+//
+// Bit mask to enable tracing on ITM stimulus port 12.
+#define CPU_ITM_TER_STIMENA12 0x00001000
+#define CPU_ITM_TER_STIMENA12_BITN 12
+#define CPU_ITM_TER_STIMENA12_M 0x00001000
+#define CPU_ITM_TER_STIMENA12_S 12
+
+// Field: [11] STIMENA11
+//
+// Bit mask to enable tracing on ITM stimulus port 11.
+#define CPU_ITM_TER_STIMENA11 0x00000800
+#define CPU_ITM_TER_STIMENA11_BITN 11
+#define CPU_ITM_TER_STIMENA11_M 0x00000800
+#define CPU_ITM_TER_STIMENA11_S 11
+
+// Field: [10] STIMENA10
+//
+// Bit mask to enable tracing on ITM stimulus port 10.
+#define CPU_ITM_TER_STIMENA10 0x00000400
+#define CPU_ITM_TER_STIMENA10_BITN 10
+#define CPU_ITM_TER_STIMENA10_M 0x00000400
+#define CPU_ITM_TER_STIMENA10_S 10
+
+// Field: [9] STIMENA9
+//
+// Bit mask to enable tracing on ITM stimulus port 9.
+#define CPU_ITM_TER_STIMENA9 0x00000200
+#define CPU_ITM_TER_STIMENA9_BITN 9
+#define CPU_ITM_TER_STIMENA9_M 0x00000200
+#define CPU_ITM_TER_STIMENA9_S 9
+
+// Field: [8] STIMENA8
+//
+// Bit mask to enable tracing on ITM stimulus port 8.
+#define CPU_ITM_TER_STIMENA8 0x00000100
+#define CPU_ITM_TER_STIMENA8_BITN 8
+#define CPU_ITM_TER_STIMENA8_M 0x00000100
+#define CPU_ITM_TER_STIMENA8_S 8
+
+// Field: [7] STIMENA7
+//
+// Bit mask to enable tracing on ITM stimulus port 7.
+#define CPU_ITM_TER_STIMENA7 0x00000080
+#define CPU_ITM_TER_STIMENA7_BITN 7
+#define CPU_ITM_TER_STIMENA7_M 0x00000080
+#define CPU_ITM_TER_STIMENA7_S 7
+
+// Field: [6] STIMENA6
+//
+// Bit mask to enable tracing on ITM stimulus port 6.
+#define CPU_ITM_TER_STIMENA6 0x00000040
+#define CPU_ITM_TER_STIMENA6_BITN 6
+#define CPU_ITM_TER_STIMENA6_M 0x00000040
+#define CPU_ITM_TER_STIMENA6_S 6
+
+// Field: [5] STIMENA5
+//
+// Bit mask to enable tracing on ITM stimulus port 5.
+#define CPU_ITM_TER_STIMENA5 0x00000020
+#define CPU_ITM_TER_STIMENA5_BITN 5
+#define CPU_ITM_TER_STIMENA5_M 0x00000020
+#define CPU_ITM_TER_STIMENA5_S 5
+
+// Field: [4] STIMENA4
+//
+// Bit mask to enable tracing on ITM stimulus port 4.
+#define CPU_ITM_TER_STIMENA4 0x00000010
+#define CPU_ITM_TER_STIMENA4_BITN 4
+#define CPU_ITM_TER_STIMENA4_M 0x00000010
+#define CPU_ITM_TER_STIMENA4_S 4
+
+// Field: [3] STIMENA3
+//
+// Bit mask to enable tracing on ITM stimulus port 3.
+#define CPU_ITM_TER_STIMENA3 0x00000008
+#define CPU_ITM_TER_STIMENA3_BITN 3
+#define CPU_ITM_TER_STIMENA3_M 0x00000008
+#define CPU_ITM_TER_STIMENA3_S 3
+
+// Field: [2] STIMENA2
+//
+// Bit mask to enable tracing on ITM stimulus port 2.
+#define CPU_ITM_TER_STIMENA2 0x00000004
+#define CPU_ITM_TER_STIMENA2_BITN 2
+#define CPU_ITM_TER_STIMENA2_M 0x00000004
+#define CPU_ITM_TER_STIMENA2_S 2
+
+// Field: [1] STIMENA1
+//
+// Bit mask to enable tracing on ITM stimulus port 1.
+#define CPU_ITM_TER_STIMENA1 0x00000002
+#define CPU_ITM_TER_STIMENA1_BITN 1
+#define CPU_ITM_TER_STIMENA1_M 0x00000002
+#define CPU_ITM_TER_STIMENA1_S 1
+
+// Field: [0] STIMENA0
+//
+// Bit mask to enable tracing on ITM stimulus port 0.
+#define CPU_ITM_TER_STIMENA0 0x00000001
+#define CPU_ITM_TER_STIMENA0_BITN 0
+#define CPU_ITM_TER_STIMENA0_M 0x00000001
+#define CPU_ITM_TER_STIMENA0_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ITM_O_TPR
+//
+//*****************************************************************************
+// Field: [3:0] PRIVMASK
+//
+// Bit mask to enable unprivileged (User) access to ITM stimulus ports:
+//
+// Bit [0] enables stimulus ports 0, 1, ..., and 7.
+// Bit [1] enables stimulus ports 8, 9, ..., and 15.
+// Bit [2] enables stimulus ports 16, 17, ..., and 23.
+// Bit [3] enables stimulus ports 24, 25, ..., and 31.
+//
+// 0: User access allowed to stimulus ports
+// 1: Privileged access only to stimulus ports
+#define CPU_ITM_TPR_PRIVMASK_W 4
+#define CPU_ITM_TPR_PRIVMASK_M 0x0000000F
+#define CPU_ITM_TPR_PRIVMASK_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ITM_O_TCR
+//
+//*****************************************************************************
+// Field: [23] BUSY
+//
+// Set when ITM events present and being drained.
+#define CPU_ITM_TCR_BUSY 0x00800000
+#define CPU_ITM_TCR_BUSY_BITN 23
+#define CPU_ITM_TCR_BUSY_M 0x00800000
+#define CPU_ITM_TCR_BUSY_S 23
+
+// Field: [22:16] ATBID
+//
+// Trace Bus ID for CoreSight system. Optional identifier for multi-source
+// trace stream formatting. If multi-source trace is in use, this field must be
+// written with a non-zero value.
+#define CPU_ITM_TCR_ATBID_W 7
+#define CPU_ITM_TCR_ATBID_M 0x007F0000
+#define CPU_ITM_TCR_ATBID_S 16
+
+// Field: [9:8] TSPRESCALE
+//
+// Timestamp prescaler
+// ENUMs:
+// DIV64 Divide by 64
+// DIV16 Divide by 16
+// DIV4 Divide by 4
+// NOPRESCALING No prescaling
+#define CPU_ITM_TCR_TSPRESCALE_W 2
+#define CPU_ITM_TCR_TSPRESCALE_M 0x00000300
+#define CPU_ITM_TCR_TSPRESCALE_S 8
+#define CPU_ITM_TCR_TSPRESCALE_DIV64 0x00000300
+#define CPU_ITM_TCR_TSPRESCALE_DIV16 0x00000200
+#define CPU_ITM_TCR_TSPRESCALE_DIV4 0x00000100
+#define CPU_ITM_TCR_TSPRESCALE_NOPRESCALING 0x00000000
+
+// Field: [4] SWOENA
+//
+// Enables asynchronous clocking of the timestamp counter (when TSENA = 1). If
+// TSENA = 0, writing this bit to 1 does not enable asynchronous clocking of
+// the timestamp counter.
+//
+// 0x0: Mode disabled. Timestamp counter uses system clock from the core and
+// counts continuously.
+// 0x1: Timestamp counter uses lineout (data related) clock from TPIU
+// interface. The timestamp counter is held in reset while the output line is
+// idle.
+#define CPU_ITM_TCR_SWOENA 0x00000010
+#define CPU_ITM_TCR_SWOENA_BITN 4
+#define CPU_ITM_TCR_SWOENA_M 0x00000010
+#define CPU_ITM_TCR_SWOENA_S 4
+
+// Field: [3] DWTENA
+//
+// Enables the DWT stimulus (hardware event packet emission to the TPIU from
+// the DWT)
+#define CPU_ITM_TCR_DWTENA 0x00000008
+#define CPU_ITM_TCR_DWTENA_BITN 3
+#define CPU_ITM_TCR_DWTENA_M 0x00000008
+#define CPU_ITM_TCR_DWTENA_S 3
+
+// Field: [2] SYNCENA
+//
+// Enables synchronization packet transmission for a synchronous TPIU.
+// CPU_DWT:CTRL.SYNCTAP must be configured for the correct synchronization
+// speed.
+#define CPU_ITM_TCR_SYNCENA 0x00000004
+#define CPU_ITM_TCR_SYNCENA_BITN 2
+#define CPU_ITM_TCR_SYNCENA_M 0x00000004
+#define CPU_ITM_TCR_SYNCENA_S 2
+
+// Field: [1] TSENA
+//
+// Enables differential timestamps. Differential timestamps are emitted when a
+// packet is written to the FIFO with a non-zero timestamp counter, and when
+// the timestamp counter overflows. Timestamps are emitted during idle times
+// after a fixed number of two million cycles. This provides a time reference
+// for packets and inter-packet gaps. If SWOENA (bit [4]) is set, timestamps
+// are triggered by activity on the internal trace bus only. In this case there
+// is no regular timestamp output when the ITM is idle.
+#define CPU_ITM_TCR_TSENA 0x00000002
+#define CPU_ITM_TCR_TSENA_BITN 1
+#define CPU_ITM_TCR_TSENA_M 0x00000002
+#define CPU_ITM_TCR_TSENA_S 1
+
+// Field: [0] ITMENA
+//
+// Enables ITM. This is the master enable, and must be set before ITM Stimulus
+// and Trace Enable registers can be written.
+#define CPU_ITM_TCR_ITMENA 0x00000001
+#define CPU_ITM_TCR_ITMENA_BITN 0
+#define CPU_ITM_TCR_ITMENA_M 0x00000001
+#define CPU_ITM_TCR_ITMENA_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ITM_O_LAR
+//
+//*****************************************************************************
+// Field: [31:0] LOCK_ACCESS
+//
+// A privileged write of 0xC5ACCE55 enables more write access to Control
+// Registers TER, TPR and TCR. An invalid write removes write access.
+#define CPU_ITM_LAR_LOCK_ACCESS_W 32
+#define CPU_ITM_LAR_LOCK_ACCESS_M 0xFFFFFFFF
+#define CPU_ITM_LAR_LOCK_ACCESS_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ITM_O_LSR
+//
+//*****************************************************************************
+// Field: [2] BYTEACC
+//
+// Reads 0 which means 8-bit lock access is not be implemented.
+#define CPU_ITM_LSR_BYTEACC 0x00000004
+#define CPU_ITM_LSR_BYTEACC_BITN 2
+#define CPU_ITM_LSR_BYTEACC_M 0x00000004
+#define CPU_ITM_LSR_BYTEACC_S 2
+
+// Field: [1] ACCESS
+//
+// Write access to component is blocked. All writes are ignored, reads are
+// permitted.
+#define CPU_ITM_LSR_ACCESS 0x00000002
+#define CPU_ITM_LSR_ACCESS_BITN 1
+#define CPU_ITM_LSR_ACCESS_M 0x00000002
+#define CPU_ITM_LSR_ACCESS_S 1
+
+// Field: [0] PRESENT
+//
+// Indicates that a lock mechanism exists for this component.
+#define CPU_ITM_LSR_PRESENT 0x00000001
+#define CPU_ITM_LSR_PRESENT_BITN 0
+#define CPU_ITM_LSR_PRESENT_M 0x00000001
+#define CPU_ITM_LSR_PRESENT_S 0
+
+
+#endif // __CPU_ITM__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_rom_table.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_rom_table.h
new file mode 100644
index 0000000..e9e9e06
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_rom_table.h
@@ -0,0 +1,220 @@
+/******************************************************************************
+* Filename: hw_cpu_rom_table_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_CPU_ROM_TABLE_H__
+#define __HW_CPU_ROM_TABLE_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// CPU_ROM_TABLE component
+//
+//*****************************************************************************
+// System Control Space Component
+#define CPU_ROM_TABLE_O_SCS 0x00000000
+
+// Data Watchpoint and Trace Component
+#define CPU_ROM_TABLE_O_DWT 0x00000004
+
+// Flash Patch and Breakpoint Component
+#define CPU_ROM_TABLE_O_FPB 0x00000008
+
+// Instrumentation Trace Component
+#define CPU_ROM_TABLE_O_ITM 0x0000000C
+
+// Trace Port Interface Component
+#define CPU_ROM_TABLE_O_TPIU 0x00000010
+
+// Enhanced Trace Component
+#define CPU_ROM_TABLE_O_ETM 0x00000014
+
+// End Marker
+#define CPU_ROM_TABLE_O_END 0x00000018
+
+// System Memory Map Access for DAP
+#define CPU_ROM_TABLE_O_SYSTEM_ACCESS 0x00000FCC
+
+//*****************************************************************************
+//
+// Register: CPU_ROM_TABLE_O_SCS
+//
+//*****************************************************************************
+// Field: [31:0] SCS
+//
+// Points to the SCS at 0xE000E000.
+// (SCS + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE000E000.
+#define CPU_ROM_TABLE_SCS_SCS_W 32
+#define CPU_ROM_TABLE_SCS_SCS_M 0xFFFFFFFF
+#define CPU_ROM_TABLE_SCS_SCS_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ROM_TABLE_O_DWT
+//
+//*****************************************************************************
+// Field: [31:1] DWT
+//
+// Points to the Data Watchpoint and Trace block at 0xE0001000.
+// (2*DWT + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0001000.
+#define CPU_ROM_TABLE_DWT_DWT_W 31
+#define CPU_ROM_TABLE_DWT_DWT_M 0xFFFFFFFE
+#define CPU_ROM_TABLE_DWT_DWT_S 1
+
+// Field: [0] DWT_PRESENT
+//
+// 0: DWT is not present
+// 1: DWT is present.
+#define CPU_ROM_TABLE_DWT_DWT_PRESENT 0x00000001
+#define CPU_ROM_TABLE_DWT_DWT_PRESENT_BITN 0
+#define CPU_ROM_TABLE_DWT_DWT_PRESENT_M 0x00000001
+#define CPU_ROM_TABLE_DWT_DWT_PRESENT_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ROM_TABLE_O_FPB
+//
+//*****************************************************************************
+// Field: [31:1] FPB
+//
+// Points to the Flash Patch and Breakpoint block at 0xE0002000.
+// (2*FPB + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0002000.
+#define CPU_ROM_TABLE_FPB_FPB_W 31
+#define CPU_ROM_TABLE_FPB_FPB_M 0xFFFFFFFE
+#define CPU_ROM_TABLE_FPB_FPB_S 1
+
+// Field: [0] FPB_PRESENT
+//
+// 0: FPB is not present
+// 1: FPB is present.
+#define CPU_ROM_TABLE_FPB_FPB_PRESENT 0x00000001
+#define CPU_ROM_TABLE_FPB_FPB_PRESENT_BITN 0
+#define CPU_ROM_TABLE_FPB_FPB_PRESENT_M 0x00000001
+#define CPU_ROM_TABLE_FPB_FPB_PRESENT_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ROM_TABLE_O_ITM
+//
+//*****************************************************************************
+// Field: [31:1] ITM
+//
+// Points to the Instrumentation Trace block at 0xE0000000.
+// (2*ITM + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0000000.
+#define CPU_ROM_TABLE_ITM_ITM_W 31
+#define CPU_ROM_TABLE_ITM_ITM_M 0xFFFFFFFE
+#define CPU_ROM_TABLE_ITM_ITM_S 1
+
+// Field: [0] ITM_PRESENT
+//
+// 0: ITM is not present
+// 1: ITM is present.
+#define CPU_ROM_TABLE_ITM_ITM_PRESENT 0x00000001
+#define CPU_ROM_TABLE_ITM_ITM_PRESENT_BITN 0
+#define CPU_ROM_TABLE_ITM_ITM_PRESENT_M 0x00000001
+#define CPU_ROM_TABLE_ITM_ITM_PRESENT_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ROM_TABLE_O_TPIU
+//
+//*****************************************************************************
+// Field: [31:1] TPIU
+//
+// Points to the TPIU. TPIU is at 0xE0040000.
+// (2*TPIU + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0040000.
+#define CPU_ROM_TABLE_TPIU_TPIU_W 31
+#define CPU_ROM_TABLE_TPIU_TPIU_M 0xFFFFFFFE
+#define CPU_ROM_TABLE_TPIU_TPIU_S 1
+
+// Field: [0] TPIU_PRESENT
+//
+// 0: TPIU is not present
+// 1: TPIU is present.
+#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT 0x00000001
+#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_BITN 0
+#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_M 0x00000001
+#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ROM_TABLE_O_ETM
+//
+//*****************************************************************************
+// Field: [31:1] ETM
+//
+// Points to the ETM. ETM is at 0xE0041000.
+// (2*ETM + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0041000.
+#define CPU_ROM_TABLE_ETM_ETM_W 31
+#define CPU_ROM_TABLE_ETM_ETM_M 0xFFFFFFFE
+#define CPU_ROM_TABLE_ETM_ETM_S 1
+
+// Field: [0] ETM_PRESENT
+//
+// 0: ETM is not present
+// 1: ETM is present.
+#define CPU_ROM_TABLE_ETM_ETM_PRESENT 0x00000001
+#define CPU_ROM_TABLE_ETM_ETM_PRESENT_BITN 0
+#define CPU_ROM_TABLE_ETM_ETM_PRESENT_M 0x00000001
+#define CPU_ROM_TABLE_ETM_ETM_PRESENT_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ROM_TABLE_O_END
+//
+//*****************************************************************************
+// Field: [31:0] END
+//
+// End of the ROM table
+#define CPU_ROM_TABLE_END_END_W 32
+#define CPU_ROM_TABLE_END_END_M 0xFFFFFFFF
+#define CPU_ROM_TABLE_END_END_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_ROM_TABLE_O_SYSTEM_ACCESS
+//
+//*****************************************************************************
+// Field: [0] SYSTEM_ACCESS
+//
+// 1: The system memory map is accessible using the DAP
+// 0: Only debug resources are accessible using the DAP
+#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS 0x00000001
+#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_BITN 0
+#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_M 0x00000001
+#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_S 0
+
+
+#endif // __CPU_ROM_TABLE__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_scs.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_scs.h
new file mode 100644
index 0000000..2906f44
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_scs.h
@@ -0,0 +1,4789 @@
+/******************************************************************************
+* Filename: hw_cpu_scs_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_CPU_SCS_H__
+#define __HW_CPU_SCS_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// CPU_SCS component
+//
+//*****************************************************************************
+// Interrupt Control Type
+#define CPU_SCS_O_ICTR 0x00000004
+
+// Auxiliary Control
+#define CPU_SCS_O_ACTLR 0x00000008
+
+// SysTick Control and Status
+#define CPU_SCS_O_STCSR 0x00000010
+
+// SysTick Reload Value
+#define CPU_SCS_O_STRVR 0x00000014
+
+// SysTick Current Value
+#define CPU_SCS_O_STCVR 0x00000018
+
+// SysTick Calibration Value
+#define CPU_SCS_O_STCR 0x0000001C
+
+// Irq 0 to 31 Set Enable
+#define CPU_SCS_O_NVIC_ISER0 0x00000100
+
+// Irq 32 to 63 Set Enable
+#define CPU_SCS_O_NVIC_ISER1 0x00000104
+
+// Irq 0 to 31 Clear Enable
+#define CPU_SCS_O_NVIC_ICER0 0x00000180
+
+// Irq 32 to 63 Clear Enable
+#define CPU_SCS_O_NVIC_ICER1 0x00000184
+
+// Irq 0 to 31 Set Pending
+#define CPU_SCS_O_NVIC_ISPR0 0x00000200
+
+// Irq 32 to 63 Set Pending
+#define CPU_SCS_O_NVIC_ISPR1 0x00000204
+
+// Irq 0 to 31 Clear Pending
+#define CPU_SCS_O_NVIC_ICPR0 0x00000280
+
+// Irq 32 to 63 Clear Pending
+#define CPU_SCS_O_NVIC_ICPR1 0x00000284
+
+// Irq 0 to 31 Active Bit
+#define CPU_SCS_O_NVIC_IABR0 0x00000300
+
+// Irq 32 to 63 Active Bit
+#define CPU_SCS_O_NVIC_IABR1 0x00000304
+
+// Irq 0 to 3 Priority
+#define CPU_SCS_O_NVIC_IPR0 0x00000400
+
+// Irq 4 to 7 Priority
+#define CPU_SCS_O_NVIC_IPR1 0x00000404
+
+// Irq 8 to 11 Priority
+#define CPU_SCS_O_NVIC_IPR2 0x00000408
+
+// Irq 12 to 15 Priority
+#define CPU_SCS_O_NVIC_IPR3 0x0000040C
+
+// Irq 16 to 19 Priority
+#define CPU_SCS_O_NVIC_IPR4 0x00000410
+
+// Irq 20 to 23 Priority
+#define CPU_SCS_O_NVIC_IPR5 0x00000414
+
+// Irq 24 to 27 Priority
+#define CPU_SCS_O_NVIC_IPR6 0x00000418
+
+// Irq 28 to 31 Priority
+#define CPU_SCS_O_NVIC_IPR7 0x0000041C
+
+// Irq 32 to 35 Priority
+#define CPU_SCS_O_NVIC_IPR8 0x00000420
+
+// Irq 32 to 35 Priority
+#define CPU_SCS_O_NVIC_IPR9 0x00000424
+
+// CPUID Base
+#define CPU_SCS_O_CPUID 0x00000D00
+
+// Interrupt Control State
+#define CPU_SCS_O_ICSR 0x00000D04
+
+// Vector Table Offset
+#define CPU_SCS_O_VTOR 0x00000D08
+
+// Application Interrupt/Reset Control
+#define CPU_SCS_O_AIRCR 0x00000D0C
+
+// System Control
+#define CPU_SCS_O_SCR 0x00000D10
+
+// Configuration Control
+#define CPU_SCS_O_CCR 0x00000D14
+
+// System Handlers 4-7 Priority
+#define CPU_SCS_O_SHPR1 0x00000D18
+
+// System Handlers 8-11 Priority
+#define CPU_SCS_O_SHPR2 0x00000D1C
+
+// System Handlers 12-15 Priority
+#define CPU_SCS_O_SHPR3 0x00000D20
+
+// System Handler Control and State
+#define CPU_SCS_O_SHCSR 0x00000D24
+
+// Configurable Fault Status
+#define CPU_SCS_O_CFSR 0x00000D28
+
+// Hard Fault Status
+#define CPU_SCS_O_HFSR 0x00000D2C
+
+// Debug Fault Status
+#define CPU_SCS_O_DFSR 0x00000D30
+
+// Mem Manage Fault Address
+#define CPU_SCS_O_MMFAR 0x00000D34
+
+// Bus Fault Address
+#define CPU_SCS_O_BFAR 0x00000D38
+
+// Auxiliary Fault Status
+#define CPU_SCS_O_AFSR 0x00000D3C
+
+// Processor Feature 0
+#define CPU_SCS_O_ID_PFR0 0x00000D40
+
+// Processor Feature 1
+#define CPU_SCS_O_ID_PFR1 0x00000D44
+
+// Debug Feature 0
+#define CPU_SCS_O_ID_DFR0 0x00000D48
+
+// Auxiliary Feature 0
+#define CPU_SCS_O_ID_AFR0 0x00000D4C
+
+// Memory Model Feature 0
+#define CPU_SCS_O_ID_MMFR0 0x00000D50
+
+// Memory Model Feature 1
+#define CPU_SCS_O_ID_MMFR1 0x00000D54
+
+// Memory Model Feature 2
+#define CPU_SCS_O_ID_MMFR2 0x00000D58
+
+// Memory Model Feature 3
+#define CPU_SCS_O_ID_MMFR3 0x00000D5C
+
+// ISA Feature 0
+#define CPU_SCS_O_ID_ISAR0 0x00000D60
+
+// ISA Feature 1
+#define CPU_SCS_O_ID_ISAR1 0x00000D64
+
+// ISA Feature 2
+#define CPU_SCS_O_ID_ISAR2 0x00000D68
+
+// ISA Feature 3
+#define CPU_SCS_O_ID_ISAR3 0x00000D6C
+
+// ISA Feature 4
+#define CPU_SCS_O_ID_ISAR4 0x00000D70
+
+// Coprocessor Access Control
+#define CPU_SCS_O_CPACR 0x00000D88
+
+// MPU Type
+#define CPU_SCS_O_MPU_TYPE 0x00000D90
+
+// MPU Control
+#define CPU_SCS_O_MPU_CTRL 0x00000D94
+
+// MPU Region Number
+#define CPU_SCS_O_MPU_RNR 0x00000D98
+
+// MPU Region Base Address
+#define CPU_SCS_O_MPU_RBAR 0x00000D9C
+
+// MPU Region Attribute and Size
+#define CPU_SCS_O_MPU_RASR 0x00000DA0
+
+// MPU Alias 1 Region Base Address
+#define CPU_SCS_O_MPU_RBAR_A1 0x00000DA4
+
+// MPU Alias 1 Region Attribute and Size
+#define CPU_SCS_O_MPU_RASR_A1 0x00000DA8
+
+// MPU Alias 2 Region Base Address
+#define CPU_SCS_O_MPU_RBAR_A2 0x00000DAC
+
+// MPU Alias 2 Region Attribute and Size
+#define CPU_SCS_O_MPU_RASR_A2 0x00000DB0
+
+// MPU Alias 3 Region Base Address
+#define CPU_SCS_O_MPU_RBAR_A3 0x00000DB4
+
+// MPU Alias 3 Region Attribute and Size
+#define CPU_SCS_O_MPU_RASR_A3 0x00000DB8
+
+// Debug Halting Control and Status
+#define CPU_SCS_O_DHCSR 0x00000DF0
+
+// Deubg Core Register Selector
+#define CPU_SCS_O_DCRSR 0x00000DF4
+
+// Debug Core Register Data
+#define CPU_SCS_O_DCRDR 0x00000DF8
+
+// Debug Exception and Monitor Control
+#define CPU_SCS_O_DEMCR 0x00000DFC
+
+// Software Trigger Interrupt
+#define CPU_SCS_O_STIR 0x00000F00
+
+// Floating Point Context Control
+#define CPU_SCS_O_FPCCR 0x00000F34
+
+// Floating-Point Context Address
+#define CPU_SCS_O_FPCAR 0x00000F38
+
+// Floating Point Default Status Control
+#define CPU_SCS_O_FPDSCR 0x00000F3C
+
+// Media and FP Feature 0
+#define CPU_SCS_O_MVFR0 0x00000F40
+
+// Media and FP Feature 1
+#define CPU_SCS_O_MVFR1 0x00000F44
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_ICTR
+//
+//*****************************************************************************
+// Field: [2:0] INTLINESNUM
+//
+// Total number of interrupt lines in groups of 32.
+//
+// 0: 0...32
+// 1: 33...64
+// 2: 65...96
+// 3: 97...128
+// 4: 129...160
+// 5: 161...192
+// 6: 193...224
+// 7: 225...256
+#define CPU_SCS_ICTR_INTLINESNUM_W 3
+#define CPU_SCS_ICTR_INTLINESNUM_M 0x00000007
+#define CPU_SCS_ICTR_INTLINESNUM_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_ACTLR
+//
+//*****************************************************************************
+// Field: [9] DISOOFP
+//
+// Disables floating point instructions completing out of order with respect to
+// integer instructions.
+#define CPU_SCS_ACTLR_DISOOFP 0x00000200
+#define CPU_SCS_ACTLR_DISOOFP_BITN 9
+#define CPU_SCS_ACTLR_DISOOFP_M 0x00000200
+#define CPU_SCS_ACTLR_DISOOFP_S 9
+
+// Field: [8] DISFPCA
+//
+// Disable automatic update of CONTROL.FPCA
+#define CPU_SCS_ACTLR_DISFPCA 0x00000100
+#define CPU_SCS_ACTLR_DISFPCA_BITN 8
+#define CPU_SCS_ACTLR_DISFPCA_M 0x00000100
+#define CPU_SCS_ACTLR_DISFPCA_S 8
+
+// Field: [2] DISFOLD
+//
+// Disables folding of IT instruction.
+#define CPU_SCS_ACTLR_DISFOLD 0x00000004
+#define CPU_SCS_ACTLR_DISFOLD_BITN 2
+#define CPU_SCS_ACTLR_DISFOLD_M 0x00000004
+#define CPU_SCS_ACTLR_DISFOLD_S 2
+
+// Field: [1] DISDEFWBUF
+//
+// Disables write buffer use during default memory map accesses. This causes
+// all bus faults to be precise bus faults but decreases the performance of the
+// processor because the stores to memory have to complete before the next
+// instruction can be executed.
+#define CPU_SCS_ACTLR_DISDEFWBUF 0x00000002
+#define CPU_SCS_ACTLR_DISDEFWBUF_BITN 1
+#define CPU_SCS_ACTLR_DISDEFWBUF_M 0x00000002
+#define CPU_SCS_ACTLR_DISDEFWBUF_S 1
+
+// Field: [0] DISMCYCINT
+//
+// Disables interruption of multi-cycle instructions. This increases the
+// interrupt latency of the processor becuase LDM/STM completes before
+// interrupt stacking occurs.
+#define CPU_SCS_ACTLR_DISMCYCINT 0x00000001
+#define CPU_SCS_ACTLR_DISMCYCINT_BITN 0
+#define CPU_SCS_ACTLR_DISMCYCINT_M 0x00000001
+#define CPU_SCS_ACTLR_DISMCYCINT_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_STCSR
+//
+//*****************************************************************************
+// Field: [16] COUNTFLAG
+//
+// Returns 1 if timer counted to 0 since last time this was read. Clears on
+// read by application of any part of the SysTick Control and Status Register.
+// If read by the debugger using the DAP, this bit is cleared on read-only if
+// the MasterType bit in the **AHB-AP** Control Register is set to 0.
+// Otherwise, COUNTFLAG is not changed by the debugger read.
+#define CPU_SCS_STCSR_COUNTFLAG 0x00010000
+#define CPU_SCS_STCSR_COUNTFLAG_BITN 16
+#define CPU_SCS_STCSR_COUNTFLAG_M 0x00010000
+#define CPU_SCS_STCSR_COUNTFLAG_S 16
+
+// Field: [2] CLKSOURCE
+//
+// Clock source:
+//
+// 0: External reference clock.
+// 1: Core clock
+//
+// External clock is not available in this device. Writes to this field will be
+// ignored.
+#define CPU_SCS_STCSR_CLKSOURCE 0x00000004
+#define CPU_SCS_STCSR_CLKSOURCE_BITN 2
+#define CPU_SCS_STCSR_CLKSOURCE_M 0x00000004
+#define CPU_SCS_STCSR_CLKSOURCE_S 2
+
+// Field: [1] TICKINT
+//
+// 0: Counting down to zero does not pend the SysTick handler. Software can use
+// COUNTFLAG to determine if the SysTick handler has ever counted to zero.
+// 1: Counting down to zero pends the SysTick handler.
+#define CPU_SCS_STCSR_TICKINT 0x00000002
+#define CPU_SCS_STCSR_TICKINT_BITN 1
+#define CPU_SCS_STCSR_TICKINT_M 0x00000002
+#define CPU_SCS_STCSR_TICKINT_S 1
+
+// Field: [0] ENABLE
+//
+// Enable SysTick counter
+//
+// 0: Counter disabled
+// 1: Counter operates in a multi-shot way. That is, counter loads with the
+// Reload value STRVR.RELOAD and then begins counting down. On reaching 0, it
+// sets COUNTFLAG to 1 and optionally pends the SysTick handler, based on
+// TICKINT. It then loads STRVR.RELOAD again, and begins counting.
+#define CPU_SCS_STCSR_ENABLE 0x00000001
+#define CPU_SCS_STCSR_ENABLE_BITN 0
+#define CPU_SCS_STCSR_ENABLE_M 0x00000001
+#define CPU_SCS_STCSR_ENABLE_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_STRVR
+//
+//*****************************************************************************
+// Field: [23:0] RELOAD
+//
+// Value to load into the SysTick Current Value Register STCVR.CURRENT when the
+// counter reaches 0.
+#define CPU_SCS_STRVR_RELOAD_W 24
+#define CPU_SCS_STRVR_RELOAD_M 0x00FFFFFF
+#define CPU_SCS_STRVR_RELOAD_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_STCVR
+//
+//*****************************************************************************
+// Field: [23:0] CURRENT
+//
+// Current value at the time the register is accessed. No read-modify-write
+// protection is provided, so change with care. Writing to it with any value
+// clears the register to 0. Clearing this register also clears
+// STCSR.COUNTFLAG.
+#define CPU_SCS_STCVR_CURRENT_W 24
+#define CPU_SCS_STCVR_CURRENT_M 0x00FFFFFF
+#define CPU_SCS_STCVR_CURRENT_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_STCR
+//
+//*****************************************************************************
+// Field: [31] NOREF
+//
+// Reads as one. Indicates that no separate reference clock is provided.
+#define CPU_SCS_STCR_NOREF 0x80000000
+#define CPU_SCS_STCR_NOREF_BITN 31
+#define CPU_SCS_STCR_NOREF_M 0x80000000
+#define CPU_SCS_STCR_NOREF_S 31
+
+// Field: [30] SKEW
+//
+// Reads as one. The calibration value is not exactly 10ms because of clock
+// frequency. This could affect its suitability as a software real time clock.
+#define CPU_SCS_STCR_SKEW 0x40000000
+#define CPU_SCS_STCR_SKEW_BITN 30
+#define CPU_SCS_STCR_SKEW_M 0x40000000
+#define CPU_SCS_STCR_SKEW_S 30
+
+// Field: [23:0] TENMS
+//
+// An optional Reload value to be used for 10ms (100Hz) timing, subject to
+// system clock skew errors. The value read is valid only when core clock is at
+// 48MHz.
+#define CPU_SCS_STCR_TENMS_W 24
+#define CPU_SCS_STCR_TENMS_M 0x00FFFFFF
+#define CPU_SCS_STCR_TENMS_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_NVIC_ISER0
+//
+//*****************************************************************************
+// Field: [31] SETENA31
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER0_SETENA31 0x80000000
+#define CPU_SCS_NVIC_ISER0_SETENA31_BITN 31
+#define CPU_SCS_NVIC_ISER0_SETENA31_M 0x80000000
+#define CPU_SCS_NVIC_ISER0_SETENA31_S 31
+
+// Field: [30] SETENA30
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER0_SETENA30 0x40000000
+#define CPU_SCS_NVIC_ISER0_SETENA30_BITN 30
+#define CPU_SCS_NVIC_ISER0_SETENA30_M 0x40000000
+#define CPU_SCS_NVIC_ISER0_SETENA30_S 30
+
+// Field: [29] SETENA29
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER0_SETENA29 0x20000000
+#define CPU_SCS_NVIC_ISER0_SETENA29_BITN 29
+#define CPU_SCS_NVIC_ISER0_SETENA29_M 0x20000000
+#define CPU_SCS_NVIC_ISER0_SETENA29_S 29
+
+// Field: [28] SETENA28
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER0_SETENA28 0x10000000
+#define CPU_SCS_NVIC_ISER0_SETENA28_BITN 28
+#define CPU_SCS_NVIC_ISER0_SETENA28_M 0x10000000
+#define CPU_SCS_NVIC_ISER0_SETENA28_S 28
+
+// Field: [27] SETENA27
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER0_SETENA27 0x08000000
+#define CPU_SCS_NVIC_ISER0_SETENA27_BITN 27
+#define CPU_SCS_NVIC_ISER0_SETENA27_M 0x08000000
+#define CPU_SCS_NVIC_ISER0_SETENA27_S 27
+
+// Field: [26] SETENA26
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER0_SETENA26 0x04000000
+#define CPU_SCS_NVIC_ISER0_SETENA26_BITN 26
+#define CPU_SCS_NVIC_ISER0_SETENA26_M 0x04000000
+#define CPU_SCS_NVIC_ISER0_SETENA26_S 26
+
+// Field: [25] SETENA25
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER0_SETENA25 0x02000000
+#define CPU_SCS_NVIC_ISER0_SETENA25_BITN 25
+#define CPU_SCS_NVIC_ISER0_SETENA25_M 0x02000000
+#define CPU_SCS_NVIC_ISER0_SETENA25_S 25
+
+// Field: [24] SETENA24
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER0_SETENA24 0x01000000
+#define CPU_SCS_NVIC_ISER0_SETENA24_BITN 24
+#define CPU_SCS_NVIC_ISER0_SETENA24_M 0x01000000
+#define CPU_SCS_NVIC_ISER0_SETENA24_S 24
+
+// Field: [23] SETENA23
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER0_SETENA23 0x00800000
+#define CPU_SCS_NVIC_ISER0_SETENA23_BITN 23
+#define CPU_SCS_NVIC_ISER0_SETENA23_M 0x00800000
+#define CPU_SCS_NVIC_ISER0_SETENA23_S 23
+
+// Field: [22] SETENA22
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER0_SETENA22 0x00400000
+#define CPU_SCS_NVIC_ISER0_SETENA22_BITN 22
+#define CPU_SCS_NVIC_ISER0_SETENA22_M 0x00400000
+#define CPU_SCS_NVIC_ISER0_SETENA22_S 22
+
+// Field: [21] SETENA21
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER0_SETENA21 0x00200000
+#define CPU_SCS_NVIC_ISER0_SETENA21_BITN 21
+#define CPU_SCS_NVIC_ISER0_SETENA21_M 0x00200000
+#define CPU_SCS_NVIC_ISER0_SETENA21_S 21
+
+// Field: [20] SETENA20
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER0_SETENA20 0x00100000
+#define CPU_SCS_NVIC_ISER0_SETENA20_BITN 20
+#define CPU_SCS_NVIC_ISER0_SETENA20_M 0x00100000
+#define CPU_SCS_NVIC_ISER0_SETENA20_S 20
+
+// Field: [19] SETENA19
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER0_SETENA19 0x00080000
+#define CPU_SCS_NVIC_ISER0_SETENA19_BITN 19
+#define CPU_SCS_NVIC_ISER0_SETENA19_M 0x00080000
+#define CPU_SCS_NVIC_ISER0_SETENA19_S 19
+
+// Field: [18] SETENA18
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER0_SETENA18 0x00040000
+#define CPU_SCS_NVIC_ISER0_SETENA18_BITN 18
+#define CPU_SCS_NVIC_ISER0_SETENA18_M 0x00040000
+#define CPU_SCS_NVIC_ISER0_SETENA18_S 18
+
+// Field: [17] SETENA17
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER0_SETENA17 0x00020000
+#define CPU_SCS_NVIC_ISER0_SETENA17_BITN 17
+#define CPU_SCS_NVIC_ISER0_SETENA17_M 0x00020000
+#define CPU_SCS_NVIC_ISER0_SETENA17_S 17
+
+// Field: [16] SETENA16
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER0_SETENA16 0x00010000
+#define CPU_SCS_NVIC_ISER0_SETENA16_BITN 16
+#define CPU_SCS_NVIC_ISER0_SETENA16_M 0x00010000
+#define CPU_SCS_NVIC_ISER0_SETENA16_S 16
+
+// Field: [15] SETENA15
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER0_SETENA15 0x00008000
+#define CPU_SCS_NVIC_ISER0_SETENA15_BITN 15
+#define CPU_SCS_NVIC_ISER0_SETENA15_M 0x00008000
+#define CPU_SCS_NVIC_ISER0_SETENA15_S 15
+
+// Field: [14] SETENA14
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER0_SETENA14 0x00004000
+#define CPU_SCS_NVIC_ISER0_SETENA14_BITN 14
+#define CPU_SCS_NVIC_ISER0_SETENA14_M 0x00004000
+#define CPU_SCS_NVIC_ISER0_SETENA14_S 14
+
+// Field: [13] SETENA13
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER0_SETENA13 0x00002000
+#define CPU_SCS_NVIC_ISER0_SETENA13_BITN 13
+#define CPU_SCS_NVIC_ISER0_SETENA13_M 0x00002000
+#define CPU_SCS_NVIC_ISER0_SETENA13_S 13
+
+// Field: [12] SETENA12
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER0_SETENA12 0x00001000
+#define CPU_SCS_NVIC_ISER0_SETENA12_BITN 12
+#define CPU_SCS_NVIC_ISER0_SETENA12_M 0x00001000
+#define CPU_SCS_NVIC_ISER0_SETENA12_S 12
+
+// Field: [11] SETENA11
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER0_SETENA11 0x00000800
+#define CPU_SCS_NVIC_ISER0_SETENA11_BITN 11
+#define CPU_SCS_NVIC_ISER0_SETENA11_M 0x00000800
+#define CPU_SCS_NVIC_ISER0_SETENA11_S 11
+
+// Field: [10] SETENA10
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER0_SETENA10 0x00000400
+#define CPU_SCS_NVIC_ISER0_SETENA10_BITN 10
+#define CPU_SCS_NVIC_ISER0_SETENA10_M 0x00000400
+#define CPU_SCS_NVIC_ISER0_SETENA10_S 10
+
+// Field: [9] SETENA9
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER0_SETENA9 0x00000200
+#define CPU_SCS_NVIC_ISER0_SETENA9_BITN 9
+#define CPU_SCS_NVIC_ISER0_SETENA9_M 0x00000200
+#define CPU_SCS_NVIC_ISER0_SETENA9_S 9
+
+// Field: [8] SETENA8
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER0_SETENA8 0x00000100
+#define CPU_SCS_NVIC_ISER0_SETENA8_BITN 8
+#define CPU_SCS_NVIC_ISER0_SETENA8_M 0x00000100
+#define CPU_SCS_NVIC_ISER0_SETENA8_S 8
+
+// Field: [7] SETENA7
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER0_SETENA7 0x00000080
+#define CPU_SCS_NVIC_ISER0_SETENA7_BITN 7
+#define CPU_SCS_NVIC_ISER0_SETENA7_M 0x00000080
+#define CPU_SCS_NVIC_ISER0_SETENA7_S 7
+
+// Field: [6] SETENA6
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER0_SETENA6 0x00000040
+#define CPU_SCS_NVIC_ISER0_SETENA6_BITN 6
+#define CPU_SCS_NVIC_ISER0_SETENA6_M 0x00000040
+#define CPU_SCS_NVIC_ISER0_SETENA6_S 6
+
+// Field: [5] SETENA5
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER0_SETENA5 0x00000020
+#define CPU_SCS_NVIC_ISER0_SETENA5_BITN 5
+#define CPU_SCS_NVIC_ISER0_SETENA5_M 0x00000020
+#define CPU_SCS_NVIC_ISER0_SETENA5_S 5
+
+// Field: [4] SETENA4
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER0_SETENA4 0x00000010
+#define CPU_SCS_NVIC_ISER0_SETENA4_BITN 4
+#define CPU_SCS_NVIC_ISER0_SETENA4_M 0x00000010
+#define CPU_SCS_NVIC_ISER0_SETENA4_S 4
+
+// Field: [3] SETENA3
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER0_SETENA3 0x00000008
+#define CPU_SCS_NVIC_ISER0_SETENA3_BITN 3
+#define CPU_SCS_NVIC_ISER0_SETENA3_M 0x00000008
+#define CPU_SCS_NVIC_ISER0_SETENA3_S 3
+
+// Field: [2] SETENA2
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER0_SETENA2 0x00000004
+#define CPU_SCS_NVIC_ISER0_SETENA2_BITN 2
+#define CPU_SCS_NVIC_ISER0_SETENA2_M 0x00000004
+#define CPU_SCS_NVIC_ISER0_SETENA2_S 2
+
+// Field: [1] SETENA1
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER0_SETENA1 0x00000002
+#define CPU_SCS_NVIC_ISER0_SETENA1_BITN 1
+#define CPU_SCS_NVIC_ISER0_SETENA1_M 0x00000002
+#define CPU_SCS_NVIC_ISER0_SETENA1_S 1
+
+// Field: [0] SETENA0
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER0_SETENA0 0x00000001
+#define CPU_SCS_NVIC_ISER0_SETENA0_BITN 0
+#define CPU_SCS_NVIC_ISER0_SETENA0_M 0x00000001
+#define CPU_SCS_NVIC_ISER0_SETENA0_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_NVIC_ISER1
+//
+//*****************************************************************************
+// Field: [5] SETENA37
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER1_SETENA37 0x00000020
+#define CPU_SCS_NVIC_ISER1_SETENA37_BITN 5
+#define CPU_SCS_NVIC_ISER1_SETENA37_M 0x00000020
+#define CPU_SCS_NVIC_ISER1_SETENA37_S 5
+
+// Field: [4] SETENA36
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER1_SETENA36 0x00000010
+#define CPU_SCS_NVIC_ISER1_SETENA36_BITN 4
+#define CPU_SCS_NVIC_ISER1_SETENA36_M 0x00000010
+#define CPU_SCS_NVIC_ISER1_SETENA36_S 4
+
+// Field: [3] SETENA35
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER1_SETENA35 0x00000008
+#define CPU_SCS_NVIC_ISER1_SETENA35_BITN 3
+#define CPU_SCS_NVIC_ISER1_SETENA35_M 0x00000008
+#define CPU_SCS_NVIC_ISER1_SETENA35_S 3
+
+// Field: [2] SETENA34
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER1_SETENA34 0x00000004
+#define CPU_SCS_NVIC_ISER1_SETENA34_BITN 2
+#define CPU_SCS_NVIC_ISER1_SETENA34_M 0x00000004
+#define CPU_SCS_NVIC_ISER1_SETENA34_S 2
+
+// Field: [1] SETENA33
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER1_SETENA33 0x00000002
+#define CPU_SCS_NVIC_ISER1_SETENA33_BITN 1
+#define CPU_SCS_NVIC_ISER1_SETENA33_M 0x00000002
+#define CPU_SCS_NVIC_ISER1_SETENA33_S 1
+
+// Field: [0] SETENA32
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit enables the
+// interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ISER1_SETENA32 0x00000001
+#define CPU_SCS_NVIC_ISER1_SETENA32_BITN 0
+#define CPU_SCS_NVIC_ISER1_SETENA32_M 0x00000001
+#define CPU_SCS_NVIC_ISER1_SETENA32_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_NVIC_ICER0
+//
+//*****************************************************************************
+// Field: [31] CLRENA31
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER0_CLRENA31 0x80000000
+#define CPU_SCS_NVIC_ICER0_CLRENA31_BITN 31
+#define CPU_SCS_NVIC_ICER0_CLRENA31_M 0x80000000
+#define CPU_SCS_NVIC_ICER0_CLRENA31_S 31
+
+// Field: [30] CLRENA30
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER0_CLRENA30 0x40000000
+#define CPU_SCS_NVIC_ICER0_CLRENA30_BITN 30
+#define CPU_SCS_NVIC_ICER0_CLRENA30_M 0x40000000
+#define CPU_SCS_NVIC_ICER0_CLRENA30_S 30
+
+// Field: [29] CLRENA29
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER0_CLRENA29 0x20000000
+#define CPU_SCS_NVIC_ICER0_CLRENA29_BITN 29
+#define CPU_SCS_NVIC_ICER0_CLRENA29_M 0x20000000
+#define CPU_SCS_NVIC_ICER0_CLRENA29_S 29
+
+// Field: [28] CLRENA28
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER0_CLRENA28 0x10000000
+#define CPU_SCS_NVIC_ICER0_CLRENA28_BITN 28
+#define CPU_SCS_NVIC_ICER0_CLRENA28_M 0x10000000
+#define CPU_SCS_NVIC_ICER0_CLRENA28_S 28
+
+// Field: [27] CLRENA27
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER0_CLRENA27 0x08000000
+#define CPU_SCS_NVIC_ICER0_CLRENA27_BITN 27
+#define CPU_SCS_NVIC_ICER0_CLRENA27_M 0x08000000
+#define CPU_SCS_NVIC_ICER0_CLRENA27_S 27
+
+// Field: [26] CLRENA26
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER0_CLRENA26 0x04000000
+#define CPU_SCS_NVIC_ICER0_CLRENA26_BITN 26
+#define CPU_SCS_NVIC_ICER0_CLRENA26_M 0x04000000
+#define CPU_SCS_NVIC_ICER0_CLRENA26_S 26
+
+// Field: [25] CLRENA25
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER0_CLRENA25 0x02000000
+#define CPU_SCS_NVIC_ICER0_CLRENA25_BITN 25
+#define CPU_SCS_NVIC_ICER0_CLRENA25_M 0x02000000
+#define CPU_SCS_NVIC_ICER0_CLRENA25_S 25
+
+// Field: [24] CLRENA24
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER0_CLRENA24 0x01000000
+#define CPU_SCS_NVIC_ICER0_CLRENA24_BITN 24
+#define CPU_SCS_NVIC_ICER0_CLRENA24_M 0x01000000
+#define CPU_SCS_NVIC_ICER0_CLRENA24_S 24
+
+// Field: [23] CLRENA23
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER0_CLRENA23 0x00800000
+#define CPU_SCS_NVIC_ICER0_CLRENA23_BITN 23
+#define CPU_SCS_NVIC_ICER0_CLRENA23_M 0x00800000
+#define CPU_SCS_NVIC_ICER0_CLRENA23_S 23
+
+// Field: [22] CLRENA22
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER0_CLRENA22 0x00400000
+#define CPU_SCS_NVIC_ICER0_CLRENA22_BITN 22
+#define CPU_SCS_NVIC_ICER0_CLRENA22_M 0x00400000
+#define CPU_SCS_NVIC_ICER0_CLRENA22_S 22
+
+// Field: [21] CLRENA21
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER0_CLRENA21 0x00200000
+#define CPU_SCS_NVIC_ICER0_CLRENA21_BITN 21
+#define CPU_SCS_NVIC_ICER0_CLRENA21_M 0x00200000
+#define CPU_SCS_NVIC_ICER0_CLRENA21_S 21
+
+// Field: [20] CLRENA20
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER0_CLRENA20 0x00100000
+#define CPU_SCS_NVIC_ICER0_CLRENA20_BITN 20
+#define CPU_SCS_NVIC_ICER0_CLRENA20_M 0x00100000
+#define CPU_SCS_NVIC_ICER0_CLRENA20_S 20
+
+// Field: [19] CLRENA19
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER0_CLRENA19 0x00080000
+#define CPU_SCS_NVIC_ICER0_CLRENA19_BITN 19
+#define CPU_SCS_NVIC_ICER0_CLRENA19_M 0x00080000
+#define CPU_SCS_NVIC_ICER0_CLRENA19_S 19
+
+// Field: [18] CLRENA18
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER0_CLRENA18 0x00040000
+#define CPU_SCS_NVIC_ICER0_CLRENA18_BITN 18
+#define CPU_SCS_NVIC_ICER0_CLRENA18_M 0x00040000
+#define CPU_SCS_NVIC_ICER0_CLRENA18_S 18
+
+// Field: [17] CLRENA17
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER0_CLRENA17 0x00020000
+#define CPU_SCS_NVIC_ICER0_CLRENA17_BITN 17
+#define CPU_SCS_NVIC_ICER0_CLRENA17_M 0x00020000
+#define CPU_SCS_NVIC_ICER0_CLRENA17_S 17
+
+// Field: [16] CLRENA16
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER0_CLRENA16 0x00010000
+#define CPU_SCS_NVIC_ICER0_CLRENA16_BITN 16
+#define CPU_SCS_NVIC_ICER0_CLRENA16_M 0x00010000
+#define CPU_SCS_NVIC_ICER0_CLRENA16_S 16
+
+// Field: [15] CLRENA15
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER0_CLRENA15 0x00008000
+#define CPU_SCS_NVIC_ICER0_CLRENA15_BITN 15
+#define CPU_SCS_NVIC_ICER0_CLRENA15_M 0x00008000
+#define CPU_SCS_NVIC_ICER0_CLRENA15_S 15
+
+// Field: [14] CLRENA14
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER0_CLRENA14 0x00004000
+#define CPU_SCS_NVIC_ICER0_CLRENA14_BITN 14
+#define CPU_SCS_NVIC_ICER0_CLRENA14_M 0x00004000
+#define CPU_SCS_NVIC_ICER0_CLRENA14_S 14
+
+// Field: [13] CLRENA13
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER0_CLRENA13 0x00002000
+#define CPU_SCS_NVIC_ICER0_CLRENA13_BITN 13
+#define CPU_SCS_NVIC_ICER0_CLRENA13_M 0x00002000
+#define CPU_SCS_NVIC_ICER0_CLRENA13_S 13
+
+// Field: [12] CLRENA12
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER0_CLRENA12 0x00001000
+#define CPU_SCS_NVIC_ICER0_CLRENA12_BITN 12
+#define CPU_SCS_NVIC_ICER0_CLRENA12_M 0x00001000
+#define CPU_SCS_NVIC_ICER0_CLRENA12_S 12
+
+// Field: [11] CLRENA11
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER0_CLRENA11 0x00000800
+#define CPU_SCS_NVIC_ICER0_CLRENA11_BITN 11
+#define CPU_SCS_NVIC_ICER0_CLRENA11_M 0x00000800
+#define CPU_SCS_NVIC_ICER0_CLRENA11_S 11
+
+// Field: [10] CLRENA10
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER0_CLRENA10 0x00000400
+#define CPU_SCS_NVIC_ICER0_CLRENA10_BITN 10
+#define CPU_SCS_NVIC_ICER0_CLRENA10_M 0x00000400
+#define CPU_SCS_NVIC_ICER0_CLRENA10_S 10
+
+// Field: [9] CLRENA9
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER0_CLRENA9 0x00000200
+#define CPU_SCS_NVIC_ICER0_CLRENA9_BITN 9
+#define CPU_SCS_NVIC_ICER0_CLRENA9_M 0x00000200
+#define CPU_SCS_NVIC_ICER0_CLRENA9_S 9
+
+// Field: [8] CLRENA8
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER0_CLRENA8 0x00000100
+#define CPU_SCS_NVIC_ICER0_CLRENA8_BITN 8
+#define CPU_SCS_NVIC_ICER0_CLRENA8_M 0x00000100
+#define CPU_SCS_NVIC_ICER0_CLRENA8_S 8
+
+// Field: [7] CLRENA7
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER0_CLRENA7 0x00000080
+#define CPU_SCS_NVIC_ICER0_CLRENA7_BITN 7
+#define CPU_SCS_NVIC_ICER0_CLRENA7_M 0x00000080
+#define CPU_SCS_NVIC_ICER0_CLRENA7_S 7
+
+// Field: [6] CLRENA6
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER0_CLRENA6 0x00000040
+#define CPU_SCS_NVIC_ICER0_CLRENA6_BITN 6
+#define CPU_SCS_NVIC_ICER0_CLRENA6_M 0x00000040
+#define CPU_SCS_NVIC_ICER0_CLRENA6_S 6
+
+// Field: [5] CLRENA5
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER0_CLRENA5 0x00000020
+#define CPU_SCS_NVIC_ICER0_CLRENA5_BITN 5
+#define CPU_SCS_NVIC_ICER0_CLRENA5_M 0x00000020
+#define CPU_SCS_NVIC_ICER0_CLRENA5_S 5
+
+// Field: [4] CLRENA4
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER0_CLRENA4 0x00000010
+#define CPU_SCS_NVIC_ICER0_CLRENA4_BITN 4
+#define CPU_SCS_NVIC_ICER0_CLRENA4_M 0x00000010
+#define CPU_SCS_NVIC_ICER0_CLRENA4_S 4
+
+// Field: [3] CLRENA3
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER0_CLRENA3 0x00000008
+#define CPU_SCS_NVIC_ICER0_CLRENA3_BITN 3
+#define CPU_SCS_NVIC_ICER0_CLRENA3_M 0x00000008
+#define CPU_SCS_NVIC_ICER0_CLRENA3_S 3
+
+// Field: [2] CLRENA2
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER0_CLRENA2 0x00000004
+#define CPU_SCS_NVIC_ICER0_CLRENA2_BITN 2
+#define CPU_SCS_NVIC_ICER0_CLRENA2_M 0x00000004
+#define CPU_SCS_NVIC_ICER0_CLRENA2_S 2
+
+// Field: [1] CLRENA1
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER0_CLRENA1 0x00000002
+#define CPU_SCS_NVIC_ICER0_CLRENA1_BITN 1
+#define CPU_SCS_NVIC_ICER0_CLRENA1_M 0x00000002
+#define CPU_SCS_NVIC_ICER0_CLRENA1_S 1
+
+// Field: [0] CLRENA0
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER0_CLRENA0 0x00000001
+#define CPU_SCS_NVIC_ICER0_CLRENA0_BITN 0
+#define CPU_SCS_NVIC_ICER0_CLRENA0_M 0x00000001
+#define CPU_SCS_NVIC_ICER0_CLRENA0_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_NVIC_ICER1
+//
+//*****************************************************************************
+// Field: [5] CLRENA37
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER1_CLRENA37 0x00000020
+#define CPU_SCS_NVIC_ICER1_CLRENA37_BITN 5
+#define CPU_SCS_NVIC_ICER1_CLRENA37_M 0x00000020
+#define CPU_SCS_NVIC_ICER1_CLRENA37_S 5
+
+// Field: [4] CLRENA36
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER1_CLRENA36 0x00000010
+#define CPU_SCS_NVIC_ICER1_CLRENA36_BITN 4
+#define CPU_SCS_NVIC_ICER1_CLRENA36_M 0x00000010
+#define CPU_SCS_NVIC_ICER1_CLRENA36_S 4
+
+// Field: [3] CLRENA35
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER1_CLRENA35 0x00000008
+#define CPU_SCS_NVIC_ICER1_CLRENA35_BITN 3
+#define CPU_SCS_NVIC_ICER1_CLRENA35_M 0x00000008
+#define CPU_SCS_NVIC_ICER1_CLRENA35_S 3
+
+// Field: [2] CLRENA34
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER1_CLRENA34 0x00000004
+#define CPU_SCS_NVIC_ICER1_CLRENA34_BITN 2
+#define CPU_SCS_NVIC_ICER1_CLRENA34_M 0x00000004
+#define CPU_SCS_NVIC_ICER1_CLRENA34_S 2
+
+// Field: [1] CLRENA33
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER1_CLRENA33 0x00000002
+#define CPU_SCS_NVIC_ICER1_CLRENA33_BITN 1
+#define CPU_SCS_NVIC_ICER1_CLRENA33_M 0x00000002
+#define CPU_SCS_NVIC_ICER1_CLRENA33_S 1
+
+// Field: [0] CLRENA32
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit disables the
+// interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit
+// returns its current enable state.
+#define CPU_SCS_NVIC_ICER1_CLRENA32 0x00000001
+#define CPU_SCS_NVIC_ICER1_CLRENA32_BITN 0
+#define CPU_SCS_NVIC_ICER1_CLRENA32_M 0x00000001
+#define CPU_SCS_NVIC_ICER1_CLRENA32_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_NVIC_ISPR0
+//
+//*****************************************************************************
+// Field: [31] SETPEND31
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR0_SETPEND31 0x80000000
+#define CPU_SCS_NVIC_ISPR0_SETPEND31_BITN 31
+#define CPU_SCS_NVIC_ISPR0_SETPEND31_M 0x80000000
+#define CPU_SCS_NVIC_ISPR0_SETPEND31_S 31
+
+// Field: [30] SETPEND30
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR0_SETPEND30 0x40000000
+#define CPU_SCS_NVIC_ISPR0_SETPEND30_BITN 30
+#define CPU_SCS_NVIC_ISPR0_SETPEND30_M 0x40000000
+#define CPU_SCS_NVIC_ISPR0_SETPEND30_S 30
+
+// Field: [29] SETPEND29
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR0_SETPEND29 0x20000000
+#define CPU_SCS_NVIC_ISPR0_SETPEND29_BITN 29
+#define CPU_SCS_NVIC_ISPR0_SETPEND29_M 0x20000000
+#define CPU_SCS_NVIC_ISPR0_SETPEND29_S 29
+
+// Field: [28] SETPEND28
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR0_SETPEND28 0x10000000
+#define CPU_SCS_NVIC_ISPR0_SETPEND28_BITN 28
+#define CPU_SCS_NVIC_ISPR0_SETPEND28_M 0x10000000
+#define CPU_SCS_NVIC_ISPR0_SETPEND28_S 28
+
+// Field: [27] SETPEND27
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR0_SETPEND27 0x08000000
+#define CPU_SCS_NVIC_ISPR0_SETPEND27_BITN 27
+#define CPU_SCS_NVIC_ISPR0_SETPEND27_M 0x08000000
+#define CPU_SCS_NVIC_ISPR0_SETPEND27_S 27
+
+// Field: [26] SETPEND26
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR0_SETPEND26 0x04000000
+#define CPU_SCS_NVIC_ISPR0_SETPEND26_BITN 26
+#define CPU_SCS_NVIC_ISPR0_SETPEND26_M 0x04000000
+#define CPU_SCS_NVIC_ISPR0_SETPEND26_S 26
+
+// Field: [25] SETPEND25
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR0_SETPEND25 0x02000000
+#define CPU_SCS_NVIC_ISPR0_SETPEND25_BITN 25
+#define CPU_SCS_NVIC_ISPR0_SETPEND25_M 0x02000000
+#define CPU_SCS_NVIC_ISPR0_SETPEND25_S 25
+
+// Field: [24] SETPEND24
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR0_SETPEND24 0x01000000
+#define CPU_SCS_NVIC_ISPR0_SETPEND24_BITN 24
+#define CPU_SCS_NVIC_ISPR0_SETPEND24_M 0x01000000
+#define CPU_SCS_NVIC_ISPR0_SETPEND24_S 24
+
+// Field: [23] SETPEND23
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR0_SETPEND23 0x00800000
+#define CPU_SCS_NVIC_ISPR0_SETPEND23_BITN 23
+#define CPU_SCS_NVIC_ISPR0_SETPEND23_M 0x00800000
+#define CPU_SCS_NVIC_ISPR0_SETPEND23_S 23
+
+// Field: [22] SETPEND22
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR0_SETPEND22 0x00400000
+#define CPU_SCS_NVIC_ISPR0_SETPEND22_BITN 22
+#define CPU_SCS_NVIC_ISPR0_SETPEND22_M 0x00400000
+#define CPU_SCS_NVIC_ISPR0_SETPEND22_S 22
+
+// Field: [21] SETPEND21
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR0_SETPEND21 0x00200000
+#define CPU_SCS_NVIC_ISPR0_SETPEND21_BITN 21
+#define CPU_SCS_NVIC_ISPR0_SETPEND21_M 0x00200000
+#define CPU_SCS_NVIC_ISPR0_SETPEND21_S 21
+
+// Field: [20] SETPEND20
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR0_SETPEND20 0x00100000
+#define CPU_SCS_NVIC_ISPR0_SETPEND20_BITN 20
+#define CPU_SCS_NVIC_ISPR0_SETPEND20_M 0x00100000
+#define CPU_SCS_NVIC_ISPR0_SETPEND20_S 20
+
+// Field: [19] SETPEND19
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR0_SETPEND19 0x00080000
+#define CPU_SCS_NVIC_ISPR0_SETPEND19_BITN 19
+#define CPU_SCS_NVIC_ISPR0_SETPEND19_M 0x00080000
+#define CPU_SCS_NVIC_ISPR0_SETPEND19_S 19
+
+// Field: [18] SETPEND18
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR0_SETPEND18 0x00040000
+#define CPU_SCS_NVIC_ISPR0_SETPEND18_BITN 18
+#define CPU_SCS_NVIC_ISPR0_SETPEND18_M 0x00040000
+#define CPU_SCS_NVIC_ISPR0_SETPEND18_S 18
+
+// Field: [17] SETPEND17
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR0_SETPEND17 0x00020000
+#define CPU_SCS_NVIC_ISPR0_SETPEND17_BITN 17
+#define CPU_SCS_NVIC_ISPR0_SETPEND17_M 0x00020000
+#define CPU_SCS_NVIC_ISPR0_SETPEND17_S 17
+
+// Field: [16] SETPEND16
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR0_SETPEND16 0x00010000
+#define CPU_SCS_NVIC_ISPR0_SETPEND16_BITN 16
+#define CPU_SCS_NVIC_ISPR0_SETPEND16_M 0x00010000
+#define CPU_SCS_NVIC_ISPR0_SETPEND16_S 16
+
+// Field: [15] SETPEND15
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR0_SETPEND15 0x00008000
+#define CPU_SCS_NVIC_ISPR0_SETPEND15_BITN 15
+#define CPU_SCS_NVIC_ISPR0_SETPEND15_M 0x00008000
+#define CPU_SCS_NVIC_ISPR0_SETPEND15_S 15
+
+// Field: [14] SETPEND14
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR0_SETPEND14 0x00004000
+#define CPU_SCS_NVIC_ISPR0_SETPEND14_BITN 14
+#define CPU_SCS_NVIC_ISPR0_SETPEND14_M 0x00004000
+#define CPU_SCS_NVIC_ISPR0_SETPEND14_S 14
+
+// Field: [13] SETPEND13
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR0_SETPEND13 0x00002000
+#define CPU_SCS_NVIC_ISPR0_SETPEND13_BITN 13
+#define CPU_SCS_NVIC_ISPR0_SETPEND13_M 0x00002000
+#define CPU_SCS_NVIC_ISPR0_SETPEND13_S 13
+
+// Field: [12] SETPEND12
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR0_SETPEND12 0x00001000
+#define CPU_SCS_NVIC_ISPR0_SETPEND12_BITN 12
+#define CPU_SCS_NVIC_ISPR0_SETPEND12_M 0x00001000
+#define CPU_SCS_NVIC_ISPR0_SETPEND12_S 12
+
+// Field: [11] SETPEND11
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR0_SETPEND11 0x00000800
+#define CPU_SCS_NVIC_ISPR0_SETPEND11_BITN 11
+#define CPU_SCS_NVIC_ISPR0_SETPEND11_M 0x00000800
+#define CPU_SCS_NVIC_ISPR0_SETPEND11_S 11
+
+// Field: [10] SETPEND10
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR0_SETPEND10 0x00000400
+#define CPU_SCS_NVIC_ISPR0_SETPEND10_BITN 10
+#define CPU_SCS_NVIC_ISPR0_SETPEND10_M 0x00000400
+#define CPU_SCS_NVIC_ISPR0_SETPEND10_S 10
+
+// Field: [9] SETPEND9
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR0_SETPEND9 0x00000200
+#define CPU_SCS_NVIC_ISPR0_SETPEND9_BITN 9
+#define CPU_SCS_NVIC_ISPR0_SETPEND9_M 0x00000200
+#define CPU_SCS_NVIC_ISPR0_SETPEND9_S 9
+
+// Field: [8] SETPEND8
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR0_SETPEND8 0x00000100
+#define CPU_SCS_NVIC_ISPR0_SETPEND8_BITN 8
+#define CPU_SCS_NVIC_ISPR0_SETPEND8_M 0x00000100
+#define CPU_SCS_NVIC_ISPR0_SETPEND8_S 8
+
+// Field: [7] SETPEND7
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR0_SETPEND7 0x00000080
+#define CPU_SCS_NVIC_ISPR0_SETPEND7_BITN 7
+#define CPU_SCS_NVIC_ISPR0_SETPEND7_M 0x00000080
+#define CPU_SCS_NVIC_ISPR0_SETPEND7_S 7
+
+// Field: [6] SETPEND6
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR0_SETPEND6 0x00000040
+#define CPU_SCS_NVIC_ISPR0_SETPEND6_BITN 6
+#define CPU_SCS_NVIC_ISPR0_SETPEND6_M 0x00000040
+#define CPU_SCS_NVIC_ISPR0_SETPEND6_S 6
+
+// Field: [5] SETPEND5
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR0_SETPEND5 0x00000020
+#define CPU_SCS_NVIC_ISPR0_SETPEND5_BITN 5
+#define CPU_SCS_NVIC_ISPR0_SETPEND5_M 0x00000020
+#define CPU_SCS_NVIC_ISPR0_SETPEND5_S 5
+
+// Field: [4] SETPEND4
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR0_SETPEND4 0x00000010
+#define CPU_SCS_NVIC_ISPR0_SETPEND4_BITN 4
+#define CPU_SCS_NVIC_ISPR0_SETPEND4_M 0x00000010
+#define CPU_SCS_NVIC_ISPR0_SETPEND4_S 4
+
+// Field: [3] SETPEND3
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR0_SETPEND3 0x00000008
+#define CPU_SCS_NVIC_ISPR0_SETPEND3_BITN 3
+#define CPU_SCS_NVIC_ISPR0_SETPEND3_M 0x00000008
+#define CPU_SCS_NVIC_ISPR0_SETPEND3_S 3
+
+// Field: [2] SETPEND2
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR0_SETPEND2 0x00000004
+#define CPU_SCS_NVIC_ISPR0_SETPEND2_BITN 2
+#define CPU_SCS_NVIC_ISPR0_SETPEND2_M 0x00000004
+#define CPU_SCS_NVIC_ISPR0_SETPEND2_S 2
+
+// Field: [1] SETPEND1
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR0_SETPEND1 0x00000002
+#define CPU_SCS_NVIC_ISPR0_SETPEND1_BITN 1
+#define CPU_SCS_NVIC_ISPR0_SETPEND1_M 0x00000002
+#define CPU_SCS_NVIC_ISPR0_SETPEND1_S 1
+
+// Field: [0] SETPEND0
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR0_SETPEND0 0x00000001
+#define CPU_SCS_NVIC_ISPR0_SETPEND0_BITN 0
+#define CPU_SCS_NVIC_ISPR0_SETPEND0_M 0x00000001
+#define CPU_SCS_NVIC_ISPR0_SETPEND0_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_NVIC_ISPR1
+//
+//*****************************************************************************
+// Field: [5] SETPEND37
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR1_SETPEND37 0x00000020
+#define CPU_SCS_NVIC_ISPR1_SETPEND37_BITN 5
+#define CPU_SCS_NVIC_ISPR1_SETPEND37_M 0x00000020
+#define CPU_SCS_NVIC_ISPR1_SETPEND37_S 5
+
+// Field: [4] SETPEND36
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR1_SETPEND36 0x00000010
+#define CPU_SCS_NVIC_ISPR1_SETPEND36_BITN 4
+#define CPU_SCS_NVIC_ISPR1_SETPEND36_M 0x00000010
+#define CPU_SCS_NVIC_ISPR1_SETPEND36_S 4
+
+// Field: [3] SETPEND35
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR1_SETPEND35 0x00000008
+#define CPU_SCS_NVIC_ISPR1_SETPEND35_BITN 3
+#define CPU_SCS_NVIC_ISPR1_SETPEND35_M 0x00000008
+#define CPU_SCS_NVIC_ISPR1_SETPEND35_S 3
+
+// Field: [2] SETPEND34
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR1_SETPEND34 0x00000004
+#define CPU_SCS_NVIC_ISPR1_SETPEND34_BITN 2
+#define CPU_SCS_NVIC_ISPR1_SETPEND34_M 0x00000004
+#define CPU_SCS_NVIC_ISPR1_SETPEND34_S 2
+
+// Field: [1] SETPEND33
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR1_SETPEND33 0x00000002
+#define CPU_SCS_NVIC_ISPR1_SETPEND33_BITN 1
+#define CPU_SCS_NVIC_ISPR1_SETPEND33_M 0x00000002
+#define CPU_SCS_NVIC_ISPR1_SETPEND33_S 1
+
+// Field: [0] SETPEND32
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit pends the
+// interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit
+// returns its current state.
+#define CPU_SCS_NVIC_ISPR1_SETPEND32 0x00000001
+#define CPU_SCS_NVIC_ISPR1_SETPEND32_BITN 0
+#define CPU_SCS_NVIC_ISPR1_SETPEND32_M 0x00000001
+#define CPU_SCS_NVIC_ISPR1_SETPEND32_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_NVIC_ICPR0
+//
+//*****************************************************************************
+// Field: [31] CLRPEND31
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 31 (See EVENT:CPUIRQSEL31.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR0_CLRPEND31 0x80000000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND31_BITN 31
+#define CPU_SCS_NVIC_ICPR0_CLRPEND31_M 0x80000000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND31_S 31
+
+// Field: [30] CLRPEND30
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 30 (See EVENT:CPUIRQSEL30.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR0_CLRPEND30 0x40000000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND30_BITN 30
+#define CPU_SCS_NVIC_ICPR0_CLRPEND30_M 0x40000000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND30_S 30
+
+// Field: [29] CLRPEND29
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 29 (See EVENT:CPUIRQSEL29.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR0_CLRPEND29 0x20000000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND29_BITN 29
+#define CPU_SCS_NVIC_ICPR0_CLRPEND29_M 0x20000000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND29_S 29
+
+// Field: [28] CLRPEND28
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 28 (See EVENT:CPUIRQSEL28.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR0_CLRPEND28 0x10000000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND28_BITN 28
+#define CPU_SCS_NVIC_ICPR0_CLRPEND28_M 0x10000000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND28_S 28
+
+// Field: [27] CLRPEND27
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 27 (See EVENT:CPUIRQSEL27.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR0_CLRPEND27 0x08000000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND27_BITN 27
+#define CPU_SCS_NVIC_ICPR0_CLRPEND27_M 0x08000000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND27_S 27
+
+// Field: [26] CLRPEND26
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 26 (See EVENT:CPUIRQSEL26.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR0_CLRPEND26 0x04000000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND26_BITN 26
+#define CPU_SCS_NVIC_ICPR0_CLRPEND26_M 0x04000000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND26_S 26
+
+// Field: [25] CLRPEND25
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 25 (See EVENT:CPUIRQSEL25.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR0_CLRPEND25 0x02000000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND25_BITN 25
+#define CPU_SCS_NVIC_ICPR0_CLRPEND25_M 0x02000000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND25_S 25
+
+// Field: [24] CLRPEND24
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 24 (See EVENT:CPUIRQSEL24.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR0_CLRPEND24 0x01000000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND24_BITN 24
+#define CPU_SCS_NVIC_ICPR0_CLRPEND24_M 0x01000000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND24_S 24
+
+// Field: [23] CLRPEND23
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 23 (See EVENT:CPUIRQSEL23.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR0_CLRPEND23 0x00800000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND23_BITN 23
+#define CPU_SCS_NVIC_ICPR0_CLRPEND23_M 0x00800000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND23_S 23
+
+// Field: [22] CLRPEND22
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 22 (See EVENT:CPUIRQSEL22.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR0_CLRPEND22 0x00400000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND22_BITN 22
+#define CPU_SCS_NVIC_ICPR0_CLRPEND22_M 0x00400000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND22_S 22
+
+// Field: [21] CLRPEND21
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 21 (See EVENT:CPUIRQSEL21.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR0_CLRPEND21 0x00200000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND21_BITN 21
+#define CPU_SCS_NVIC_ICPR0_CLRPEND21_M 0x00200000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND21_S 21
+
+// Field: [20] CLRPEND20
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 20 (See EVENT:CPUIRQSEL20.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR0_CLRPEND20 0x00100000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND20_BITN 20
+#define CPU_SCS_NVIC_ICPR0_CLRPEND20_M 0x00100000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND20_S 20
+
+// Field: [19] CLRPEND19
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 19 (See EVENT:CPUIRQSEL19.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR0_CLRPEND19 0x00080000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND19_BITN 19
+#define CPU_SCS_NVIC_ICPR0_CLRPEND19_M 0x00080000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND19_S 19
+
+// Field: [18] CLRPEND18
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 18 (See EVENT:CPUIRQSEL18.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR0_CLRPEND18 0x00040000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND18_BITN 18
+#define CPU_SCS_NVIC_ICPR0_CLRPEND18_M 0x00040000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND18_S 18
+
+// Field: [17] CLRPEND17
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 17 (See EVENT:CPUIRQSEL17.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR0_CLRPEND17 0x00020000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND17_BITN 17
+#define CPU_SCS_NVIC_ICPR0_CLRPEND17_M 0x00020000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND17_S 17
+
+// Field: [16] CLRPEND16
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 16 (See EVENT:CPUIRQSEL16.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR0_CLRPEND16 0x00010000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND16_BITN 16
+#define CPU_SCS_NVIC_ICPR0_CLRPEND16_M 0x00010000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND16_S 16
+
+// Field: [15] CLRPEND15
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 15 (See EVENT:CPUIRQSEL15.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR0_CLRPEND15 0x00008000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND15_BITN 15
+#define CPU_SCS_NVIC_ICPR0_CLRPEND15_M 0x00008000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND15_S 15
+
+// Field: [14] CLRPEND14
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 14 (See EVENT:CPUIRQSEL14.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR0_CLRPEND14 0x00004000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND14_BITN 14
+#define CPU_SCS_NVIC_ICPR0_CLRPEND14_M 0x00004000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND14_S 14
+
+// Field: [13] CLRPEND13
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 13 (See EVENT:CPUIRQSEL13.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR0_CLRPEND13 0x00002000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND13_BITN 13
+#define CPU_SCS_NVIC_ICPR0_CLRPEND13_M 0x00002000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND13_S 13
+
+// Field: [12] CLRPEND12
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 12 (See EVENT:CPUIRQSEL12.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR0_CLRPEND12 0x00001000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND12_BITN 12
+#define CPU_SCS_NVIC_ICPR0_CLRPEND12_M 0x00001000
+#define CPU_SCS_NVIC_ICPR0_CLRPEND12_S 12
+
+// Field: [11] CLRPEND11
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 11 (See EVENT:CPUIRQSEL11.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR0_CLRPEND11 0x00000800
+#define CPU_SCS_NVIC_ICPR0_CLRPEND11_BITN 11
+#define CPU_SCS_NVIC_ICPR0_CLRPEND11_M 0x00000800
+#define CPU_SCS_NVIC_ICPR0_CLRPEND11_S 11
+
+// Field: [10] CLRPEND10
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 10 (See EVENT:CPUIRQSEL10.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR0_CLRPEND10 0x00000400
+#define CPU_SCS_NVIC_ICPR0_CLRPEND10_BITN 10
+#define CPU_SCS_NVIC_ICPR0_CLRPEND10_M 0x00000400
+#define CPU_SCS_NVIC_ICPR0_CLRPEND10_S 10
+
+// Field: [9] CLRPEND9
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 9 (See EVENT:CPUIRQSEL9.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR0_CLRPEND9 0x00000200
+#define CPU_SCS_NVIC_ICPR0_CLRPEND9_BITN 9
+#define CPU_SCS_NVIC_ICPR0_CLRPEND9_M 0x00000200
+#define CPU_SCS_NVIC_ICPR0_CLRPEND9_S 9
+
+// Field: [8] CLRPEND8
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 8 (See EVENT:CPUIRQSEL8.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR0_CLRPEND8 0x00000100
+#define CPU_SCS_NVIC_ICPR0_CLRPEND8_BITN 8
+#define CPU_SCS_NVIC_ICPR0_CLRPEND8_M 0x00000100
+#define CPU_SCS_NVIC_ICPR0_CLRPEND8_S 8
+
+// Field: [7] CLRPEND7
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 7 (See EVENT:CPUIRQSEL7.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR0_CLRPEND7 0x00000080
+#define CPU_SCS_NVIC_ICPR0_CLRPEND7_BITN 7
+#define CPU_SCS_NVIC_ICPR0_CLRPEND7_M 0x00000080
+#define CPU_SCS_NVIC_ICPR0_CLRPEND7_S 7
+
+// Field: [6] CLRPEND6
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 6 (See EVENT:CPUIRQSEL6.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR0_CLRPEND6 0x00000040
+#define CPU_SCS_NVIC_ICPR0_CLRPEND6_BITN 6
+#define CPU_SCS_NVIC_ICPR0_CLRPEND6_M 0x00000040
+#define CPU_SCS_NVIC_ICPR0_CLRPEND6_S 6
+
+// Field: [5] CLRPEND5
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 5 (See EVENT:CPUIRQSEL5.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR0_CLRPEND5 0x00000020
+#define CPU_SCS_NVIC_ICPR0_CLRPEND5_BITN 5
+#define CPU_SCS_NVIC_ICPR0_CLRPEND5_M 0x00000020
+#define CPU_SCS_NVIC_ICPR0_CLRPEND5_S 5
+
+// Field: [4] CLRPEND4
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 4 (See EVENT:CPUIRQSEL4.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR0_CLRPEND4 0x00000010
+#define CPU_SCS_NVIC_ICPR0_CLRPEND4_BITN 4
+#define CPU_SCS_NVIC_ICPR0_CLRPEND4_M 0x00000010
+#define CPU_SCS_NVIC_ICPR0_CLRPEND4_S 4
+
+// Field: [3] CLRPEND3
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 3 (See EVENT:CPUIRQSEL3.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR0_CLRPEND3 0x00000008
+#define CPU_SCS_NVIC_ICPR0_CLRPEND3_BITN 3
+#define CPU_SCS_NVIC_ICPR0_CLRPEND3_M 0x00000008
+#define CPU_SCS_NVIC_ICPR0_CLRPEND3_S 3
+
+// Field: [2] CLRPEND2
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 2 (See EVENT:CPUIRQSEL2.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR0_CLRPEND2 0x00000004
+#define CPU_SCS_NVIC_ICPR0_CLRPEND2_BITN 2
+#define CPU_SCS_NVIC_ICPR0_CLRPEND2_M 0x00000004
+#define CPU_SCS_NVIC_ICPR0_CLRPEND2_S 2
+
+// Field: [1] CLRPEND1
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 1 (See EVENT:CPUIRQSEL1.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR0_CLRPEND1 0x00000002
+#define CPU_SCS_NVIC_ICPR0_CLRPEND1_BITN 1
+#define CPU_SCS_NVIC_ICPR0_CLRPEND1_M 0x00000002
+#define CPU_SCS_NVIC_ICPR0_CLRPEND1_S 1
+
+// Field: [0] CLRPEND0
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 0 (See EVENT:CPUIRQSEL0.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR0_CLRPEND0 0x00000001
+#define CPU_SCS_NVIC_ICPR0_CLRPEND0_BITN 0
+#define CPU_SCS_NVIC_ICPR0_CLRPEND0_M 0x00000001
+#define CPU_SCS_NVIC_ICPR0_CLRPEND0_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_NVIC_ICPR1
+//
+//*****************************************************************************
+// Field: [5] CLRPEND37
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 37 (See EVENT:CPUIRQSEL37.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR1_CLRPEND37 0x00000020
+#define CPU_SCS_NVIC_ICPR1_CLRPEND37_BITN 5
+#define CPU_SCS_NVIC_ICPR1_CLRPEND37_M 0x00000020
+#define CPU_SCS_NVIC_ICPR1_CLRPEND37_S 5
+
+// Field: [4] CLRPEND36
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 36 (See EVENT:CPUIRQSEL36.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR1_CLRPEND36 0x00000010
+#define CPU_SCS_NVIC_ICPR1_CLRPEND36_BITN 4
+#define CPU_SCS_NVIC_ICPR1_CLRPEND36_M 0x00000010
+#define CPU_SCS_NVIC_ICPR1_CLRPEND36_S 4
+
+// Field: [3] CLRPEND35
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 35 (See EVENT:CPUIRQSEL35.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR1_CLRPEND35 0x00000008
+#define CPU_SCS_NVIC_ICPR1_CLRPEND35_BITN 3
+#define CPU_SCS_NVIC_ICPR1_CLRPEND35_M 0x00000008
+#define CPU_SCS_NVIC_ICPR1_CLRPEND35_S 3
+
+// Field: [2] CLRPEND34
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 34 (See EVENT:CPUIRQSEL34.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR1_CLRPEND34 0x00000004
+#define CPU_SCS_NVIC_ICPR1_CLRPEND34_BITN 2
+#define CPU_SCS_NVIC_ICPR1_CLRPEND34_M 0x00000004
+#define CPU_SCS_NVIC_ICPR1_CLRPEND34_S 2
+
+// Field: [1] CLRPEND33
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 33 (See EVENT:CPUIRQSEL33.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR1_CLRPEND33 0x00000002
+#define CPU_SCS_NVIC_ICPR1_CLRPEND33_BITN 1
+#define CPU_SCS_NVIC_ICPR1_CLRPEND33_M 0x00000002
+#define CPU_SCS_NVIC_ICPR1_CLRPEND33_S 1
+
+// Field: [0] CLRPEND32
+//
+// Writing 0 to this bit has no effect, writing 1 to this bit clears the
+// corresponding pending interrupt 32 (See EVENT:CPUIRQSEL32.EV for details).
+// Reading the bit returns its current state.
+#define CPU_SCS_NVIC_ICPR1_CLRPEND32 0x00000001
+#define CPU_SCS_NVIC_ICPR1_CLRPEND32_BITN 0
+#define CPU_SCS_NVIC_ICPR1_CLRPEND32_M 0x00000001
+#define CPU_SCS_NVIC_ICPR1_CLRPEND32_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_NVIC_IABR0
+//
+//*****************************************************************************
+// Field: [31] ACTIVE31
+//
+// Reading 0 from this bit implies that interrupt line 31 is not active.
+// Reading 1 from this bit implies that the interrupt line 31 is active (See
+// EVENT:CPUIRQSEL31.EV for details).
+#define CPU_SCS_NVIC_IABR0_ACTIVE31 0x80000000
+#define CPU_SCS_NVIC_IABR0_ACTIVE31_BITN 31
+#define CPU_SCS_NVIC_IABR0_ACTIVE31_M 0x80000000
+#define CPU_SCS_NVIC_IABR0_ACTIVE31_S 31
+
+// Field: [30] ACTIVE30
+//
+// Reading 0 from this bit implies that interrupt line 30 is not active.
+// Reading 1 from this bit implies that the interrupt line 30 is active (See
+// EVENT:CPUIRQSEL30.EV for details).
+#define CPU_SCS_NVIC_IABR0_ACTIVE30 0x40000000
+#define CPU_SCS_NVIC_IABR0_ACTIVE30_BITN 30
+#define CPU_SCS_NVIC_IABR0_ACTIVE30_M 0x40000000
+#define CPU_SCS_NVIC_IABR0_ACTIVE30_S 30
+
+// Field: [29] ACTIVE29
+//
+// Reading 0 from this bit implies that interrupt line 29 is not active.
+// Reading 1 from this bit implies that the interrupt line 29 is active (See
+// EVENT:CPUIRQSEL29.EV for details).
+#define CPU_SCS_NVIC_IABR0_ACTIVE29 0x20000000
+#define CPU_SCS_NVIC_IABR0_ACTIVE29_BITN 29
+#define CPU_SCS_NVIC_IABR0_ACTIVE29_M 0x20000000
+#define CPU_SCS_NVIC_IABR0_ACTIVE29_S 29
+
+// Field: [28] ACTIVE28
+//
+// Reading 0 from this bit implies that interrupt line 28 is not active.
+// Reading 1 from this bit implies that the interrupt line 28 is active (See
+// EVENT:CPUIRQSEL28.EV for details).
+#define CPU_SCS_NVIC_IABR0_ACTIVE28 0x10000000
+#define CPU_SCS_NVIC_IABR0_ACTIVE28_BITN 28
+#define CPU_SCS_NVIC_IABR0_ACTIVE28_M 0x10000000
+#define CPU_SCS_NVIC_IABR0_ACTIVE28_S 28
+
+// Field: [27] ACTIVE27
+//
+// Reading 0 from this bit implies that interrupt line 27 is not active.
+// Reading 1 from this bit implies that the interrupt line 27 is active (See
+// EVENT:CPUIRQSEL27.EV for details).
+#define CPU_SCS_NVIC_IABR0_ACTIVE27 0x08000000
+#define CPU_SCS_NVIC_IABR0_ACTIVE27_BITN 27
+#define CPU_SCS_NVIC_IABR0_ACTIVE27_M 0x08000000
+#define CPU_SCS_NVIC_IABR0_ACTIVE27_S 27
+
+// Field: [26] ACTIVE26
+//
+// Reading 0 from this bit implies that interrupt line 26 is not active.
+// Reading 1 from this bit implies that the interrupt line 26 is active (See
+// EVENT:CPUIRQSEL26.EV for details).
+#define CPU_SCS_NVIC_IABR0_ACTIVE26 0x04000000
+#define CPU_SCS_NVIC_IABR0_ACTIVE26_BITN 26
+#define CPU_SCS_NVIC_IABR0_ACTIVE26_M 0x04000000
+#define CPU_SCS_NVIC_IABR0_ACTIVE26_S 26
+
+// Field: [25] ACTIVE25
+//
+// Reading 0 from this bit implies that interrupt line 25 is not active.
+// Reading 1 from this bit implies that the interrupt line 25 is active (See
+// EVENT:CPUIRQSEL25.EV for details).
+#define CPU_SCS_NVIC_IABR0_ACTIVE25 0x02000000
+#define CPU_SCS_NVIC_IABR0_ACTIVE25_BITN 25
+#define CPU_SCS_NVIC_IABR0_ACTIVE25_M 0x02000000
+#define CPU_SCS_NVIC_IABR0_ACTIVE25_S 25
+
+// Field: [24] ACTIVE24
+//
+// Reading 0 from this bit implies that interrupt line 24 is not active.
+// Reading 1 from this bit implies that the interrupt line 24 is active (See
+// EVENT:CPUIRQSEL24.EV for details).
+#define CPU_SCS_NVIC_IABR0_ACTIVE24 0x01000000
+#define CPU_SCS_NVIC_IABR0_ACTIVE24_BITN 24
+#define CPU_SCS_NVIC_IABR0_ACTIVE24_M 0x01000000
+#define CPU_SCS_NVIC_IABR0_ACTIVE24_S 24
+
+// Field: [23] ACTIVE23
+//
+// Reading 0 from this bit implies that interrupt line 23 is not active.
+// Reading 1 from this bit implies that the interrupt line 23 is active (See
+// EVENT:CPUIRQSEL23.EV for details).
+#define CPU_SCS_NVIC_IABR0_ACTIVE23 0x00800000
+#define CPU_SCS_NVIC_IABR0_ACTIVE23_BITN 23
+#define CPU_SCS_NVIC_IABR0_ACTIVE23_M 0x00800000
+#define CPU_SCS_NVIC_IABR0_ACTIVE23_S 23
+
+// Field: [22] ACTIVE22
+//
+// Reading 0 from this bit implies that interrupt line 22 is not active.
+// Reading 1 from this bit implies that the interrupt line 22 is active (See
+// EVENT:CPUIRQSEL22.EV for details).
+#define CPU_SCS_NVIC_IABR0_ACTIVE22 0x00400000
+#define CPU_SCS_NVIC_IABR0_ACTIVE22_BITN 22
+#define CPU_SCS_NVIC_IABR0_ACTIVE22_M 0x00400000
+#define CPU_SCS_NVIC_IABR0_ACTIVE22_S 22
+
+// Field: [21] ACTIVE21
+//
+// Reading 0 from this bit implies that interrupt line 21 is not active.
+// Reading 1 from this bit implies that the interrupt line 21 is active (See
+// EVENT:CPUIRQSEL21.EV for details).
+#define CPU_SCS_NVIC_IABR0_ACTIVE21 0x00200000
+#define CPU_SCS_NVIC_IABR0_ACTIVE21_BITN 21
+#define CPU_SCS_NVIC_IABR0_ACTIVE21_M 0x00200000
+#define CPU_SCS_NVIC_IABR0_ACTIVE21_S 21
+
+// Field: [20] ACTIVE20
+//
+// Reading 0 from this bit implies that interrupt line 20 is not active.
+// Reading 1 from this bit implies that the interrupt line 20 is active (See
+// EVENT:CPUIRQSEL20.EV for details).
+#define CPU_SCS_NVIC_IABR0_ACTIVE20 0x00100000
+#define CPU_SCS_NVIC_IABR0_ACTIVE20_BITN 20
+#define CPU_SCS_NVIC_IABR0_ACTIVE20_M 0x00100000
+#define CPU_SCS_NVIC_IABR0_ACTIVE20_S 20
+
+// Field: [19] ACTIVE19
+//
+// Reading 0 from this bit implies that interrupt line 19 is not active.
+// Reading 1 from this bit implies that the interrupt line 19 is active (See
+// EVENT:CPUIRQSEL19.EV for details).
+#define CPU_SCS_NVIC_IABR0_ACTIVE19 0x00080000
+#define CPU_SCS_NVIC_IABR0_ACTIVE19_BITN 19
+#define CPU_SCS_NVIC_IABR0_ACTIVE19_M 0x00080000
+#define CPU_SCS_NVIC_IABR0_ACTIVE19_S 19
+
+// Field: [18] ACTIVE18
+//
+// Reading 0 from this bit implies that interrupt line 18 is not active.
+// Reading 1 from this bit implies that the interrupt line 18 is active (See
+// EVENT:CPUIRQSEL18.EV for details).
+#define CPU_SCS_NVIC_IABR0_ACTIVE18 0x00040000
+#define CPU_SCS_NVIC_IABR0_ACTIVE18_BITN 18
+#define CPU_SCS_NVIC_IABR0_ACTIVE18_M 0x00040000
+#define CPU_SCS_NVIC_IABR0_ACTIVE18_S 18
+
+// Field: [17] ACTIVE17
+//
+// Reading 0 from this bit implies that interrupt line 17 is not active.
+// Reading 1 from this bit implies that the interrupt line 17 is active (See
+// EVENT:CPUIRQSEL17.EV for details).
+#define CPU_SCS_NVIC_IABR0_ACTIVE17 0x00020000
+#define CPU_SCS_NVIC_IABR0_ACTIVE17_BITN 17
+#define CPU_SCS_NVIC_IABR0_ACTIVE17_M 0x00020000
+#define CPU_SCS_NVIC_IABR0_ACTIVE17_S 17
+
+// Field: [16] ACTIVE16
+//
+// Reading 0 from this bit implies that interrupt line 16 is not active.
+// Reading 1 from this bit implies that the interrupt line 16 is active (See
+// EVENT:CPUIRQSEL16.EV for details).
+#define CPU_SCS_NVIC_IABR0_ACTIVE16 0x00010000
+#define CPU_SCS_NVIC_IABR0_ACTIVE16_BITN 16
+#define CPU_SCS_NVIC_IABR0_ACTIVE16_M 0x00010000
+#define CPU_SCS_NVIC_IABR0_ACTIVE16_S 16
+
+// Field: [15] ACTIVE15
+//
+// Reading 0 from this bit implies that interrupt line 15 is not active.
+// Reading 1 from this bit implies that the interrupt line 15 is active (See
+// EVENT:CPUIRQSEL15.EV for details).
+#define CPU_SCS_NVIC_IABR0_ACTIVE15 0x00008000
+#define CPU_SCS_NVIC_IABR0_ACTIVE15_BITN 15
+#define CPU_SCS_NVIC_IABR0_ACTIVE15_M 0x00008000
+#define CPU_SCS_NVIC_IABR0_ACTIVE15_S 15
+
+// Field: [14] ACTIVE14
+//
+// Reading 0 from this bit implies that interrupt line 14 is not active.
+// Reading 1 from this bit implies that the interrupt line 14 is active (See
+// EVENT:CPUIRQSEL14.EV for details).
+#define CPU_SCS_NVIC_IABR0_ACTIVE14 0x00004000
+#define CPU_SCS_NVIC_IABR0_ACTIVE14_BITN 14
+#define CPU_SCS_NVIC_IABR0_ACTIVE14_M 0x00004000
+#define CPU_SCS_NVIC_IABR0_ACTIVE14_S 14
+
+// Field: [13] ACTIVE13
+//
+// Reading 0 from this bit implies that interrupt line 13 is not active.
+// Reading 1 from this bit implies that the interrupt line 13 is active (See
+// EVENT:CPUIRQSEL13.EV for details).
+#define CPU_SCS_NVIC_IABR0_ACTIVE13 0x00002000
+#define CPU_SCS_NVIC_IABR0_ACTIVE13_BITN 13
+#define CPU_SCS_NVIC_IABR0_ACTIVE13_M 0x00002000
+#define CPU_SCS_NVIC_IABR0_ACTIVE13_S 13
+
+// Field: [12] ACTIVE12
+//
+// Reading 0 from this bit implies that interrupt line 12 is not active.
+// Reading 1 from this bit implies that the interrupt line 12 is active (See
+// EVENT:CPUIRQSEL12.EV for details).
+#define CPU_SCS_NVIC_IABR0_ACTIVE12 0x00001000
+#define CPU_SCS_NVIC_IABR0_ACTIVE12_BITN 12
+#define CPU_SCS_NVIC_IABR0_ACTIVE12_M 0x00001000
+#define CPU_SCS_NVIC_IABR0_ACTIVE12_S 12
+
+// Field: [11] ACTIVE11
+//
+// Reading 0 from this bit implies that interrupt line 11 is not active.
+// Reading 1 from this bit implies that the interrupt line 11 is active (See
+// EVENT:CPUIRQSEL11.EV for details).
+#define CPU_SCS_NVIC_IABR0_ACTIVE11 0x00000800
+#define CPU_SCS_NVIC_IABR0_ACTIVE11_BITN 11
+#define CPU_SCS_NVIC_IABR0_ACTIVE11_M 0x00000800
+#define CPU_SCS_NVIC_IABR0_ACTIVE11_S 11
+
+// Field: [10] ACTIVE10
+//
+// Reading 0 from this bit implies that interrupt line 10 is not active.
+// Reading 1 from this bit implies that the interrupt line 10 is active (See
+// EVENT:CPUIRQSEL10.EV for details).
+#define CPU_SCS_NVIC_IABR0_ACTIVE10 0x00000400
+#define CPU_SCS_NVIC_IABR0_ACTIVE10_BITN 10
+#define CPU_SCS_NVIC_IABR0_ACTIVE10_M 0x00000400
+#define CPU_SCS_NVIC_IABR0_ACTIVE10_S 10
+
+// Field: [9] ACTIVE9
+//
+// Reading 0 from this bit implies that interrupt line 9 is not active. Reading
+// 1 from this bit implies that the interrupt line 9 is active (See
+// EVENT:CPUIRQSEL9.EV for details).
+#define CPU_SCS_NVIC_IABR0_ACTIVE9 0x00000200
+#define CPU_SCS_NVIC_IABR0_ACTIVE9_BITN 9
+#define CPU_SCS_NVIC_IABR0_ACTIVE9_M 0x00000200
+#define CPU_SCS_NVIC_IABR0_ACTIVE9_S 9
+
+// Field: [8] ACTIVE8
+//
+// Reading 0 from this bit implies that interrupt line 8 is not active. Reading
+// 1 from this bit implies that the interrupt line 8 is active (See
+// EVENT:CPUIRQSEL8.EV for details).
+#define CPU_SCS_NVIC_IABR0_ACTIVE8 0x00000100
+#define CPU_SCS_NVIC_IABR0_ACTIVE8_BITN 8
+#define CPU_SCS_NVIC_IABR0_ACTIVE8_M 0x00000100
+#define CPU_SCS_NVIC_IABR0_ACTIVE8_S 8
+
+// Field: [7] ACTIVE7
+//
+// Reading 0 from this bit implies that interrupt line 7 is not active. Reading
+// 1 from this bit implies that the interrupt line 7 is active (See
+// EVENT:CPUIRQSEL7.EV for details).
+#define CPU_SCS_NVIC_IABR0_ACTIVE7 0x00000080
+#define CPU_SCS_NVIC_IABR0_ACTIVE7_BITN 7
+#define CPU_SCS_NVIC_IABR0_ACTIVE7_M 0x00000080
+#define CPU_SCS_NVIC_IABR0_ACTIVE7_S 7
+
+// Field: [6] ACTIVE6
+//
+// Reading 0 from this bit implies that interrupt line 6 is not active. Reading
+// 1 from this bit implies that the interrupt line 6 is active (See
+// EVENT:CPUIRQSEL6.EV for details).
+#define CPU_SCS_NVIC_IABR0_ACTIVE6 0x00000040
+#define CPU_SCS_NVIC_IABR0_ACTIVE6_BITN 6
+#define CPU_SCS_NVIC_IABR0_ACTIVE6_M 0x00000040
+#define CPU_SCS_NVIC_IABR0_ACTIVE6_S 6
+
+// Field: [5] ACTIVE5
+//
+// Reading 0 from this bit implies that interrupt line 5 is not active. Reading
+// 1 from this bit implies that the interrupt line 5 is active (See
+// EVENT:CPUIRQSEL5.EV for details).
+#define CPU_SCS_NVIC_IABR0_ACTIVE5 0x00000020
+#define CPU_SCS_NVIC_IABR0_ACTIVE5_BITN 5
+#define CPU_SCS_NVIC_IABR0_ACTIVE5_M 0x00000020
+#define CPU_SCS_NVIC_IABR0_ACTIVE5_S 5
+
+// Field: [4] ACTIVE4
+//
+// Reading 0 from this bit implies that interrupt line 4 is not active. Reading
+// 1 from this bit implies that the interrupt line 4 is active (See
+// EVENT:CPUIRQSEL4.EV for details).
+#define CPU_SCS_NVIC_IABR0_ACTIVE4 0x00000010
+#define CPU_SCS_NVIC_IABR0_ACTIVE4_BITN 4
+#define CPU_SCS_NVIC_IABR0_ACTIVE4_M 0x00000010
+#define CPU_SCS_NVIC_IABR0_ACTIVE4_S 4
+
+// Field: [3] ACTIVE3
+//
+// Reading 0 from this bit implies that interrupt line 3 is not active. Reading
+// 1 from this bit implies that the interrupt line 3 is active (See
+// EVENT:CPUIRQSEL3.EV for details).
+#define CPU_SCS_NVIC_IABR0_ACTIVE3 0x00000008
+#define CPU_SCS_NVIC_IABR0_ACTIVE3_BITN 3
+#define CPU_SCS_NVIC_IABR0_ACTIVE3_M 0x00000008
+#define CPU_SCS_NVIC_IABR0_ACTIVE3_S 3
+
+// Field: [2] ACTIVE2
+//
+// Reading 0 from this bit implies that interrupt line 2 is not active. Reading
+// 1 from this bit implies that the interrupt line 2 is active (See
+// EVENT:CPUIRQSEL2.EV for details).
+#define CPU_SCS_NVIC_IABR0_ACTIVE2 0x00000004
+#define CPU_SCS_NVIC_IABR0_ACTIVE2_BITN 2
+#define CPU_SCS_NVIC_IABR0_ACTIVE2_M 0x00000004
+#define CPU_SCS_NVIC_IABR0_ACTIVE2_S 2
+
+// Field: [1] ACTIVE1
+//
+// Reading 0 from this bit implies that interrupt line 1 is not active. Reading
+// 1 from this bit implies that the interrupt line 1 is active (See
+// EVENT:CPUIRQSEL1.EV for details).
+#define CPU_SCS_NVIC_IABR0_ACTIVE1 0x00000002
+#define CPU_SCS_NVIC_IABR0_ACTIVE1_BITN 1
+#define CPU_SCS_NVIC_IABR0_ACTIVE1_M 0x00000002
+#define CPU_SCS_NVIC_IABR0_ACTIVE1_S 1
+
+// Field: [0] ACTIVE0
+//
+// Reading 0 from this bit implies that interrupt line 0 is not active. Reading
+// 1 from this bit implies that the interrupt line 0 is active (See
+// EVENT:CPUIRQSEL0.EV for details).
+#define CPU_SCS_NVIC_IABR0_ACTIVE0 0x00000001
+#define CPU_SCS_NVIC_IABR0_ACTIVE0_BITN 0
+#define CPU_SCS_NVIC_IABR0_ACTIVE0_M 0x00000001
+#define CPU_SCS_NVIC_IABR0_ACTIVE0_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_NVIC_IABR1
+//
+//*****************************************************************************
+// Field: [5] ACTIVE37
+//
+// Reading 0 from this bit implies that interrupt line 37 is not active.
+// Reading 1 from this bit implies that the interrupt line 37 is active (See
+// EVENT:CPUIRQSEL37.EV for details).
+#define CPU_SCS_NVIC_IABR1_ACTIVE37 0x00000020
+#define CPU_SCS_NVIC_IABR1_ACTIVE37_BITN 5
+#define CPU_SCS_NVIC_IABR1_ACTIVE37_M 0x00000020
+#define CPU_SCS_NVIC_IABR1_ACTIVE37_S 5
+
+// Field: [4] ACTIVE36
+//
+// Reading 0 from this bit implies that interrupt line 36 is not active.
+// Reading 1 from this bit implies that the interrupt line 36 is active (See
+// EVENT:CPUIRQSEL36.EV for details).
+#define CPU_SCS_NVIC_IABR1_ACTIVE36 0x00000010
+#define CPU_SCS_NVIC_IABR1_ACTIVE36_BITN 4
+#define CPU_SCS_NVIC_IABR1_ACTIVE36_M 0x00000010
+#define CPU_SCS_NVIC_IABR1_ACTIVE36_S 4
+
+// Field: [3] ACTIVE35
+//
+// Reading 0 from this bit implies that interrupt line 35 is not active.
+// Reading 1 from this bit implies that the interrupt line 35 is active (See
+// EVENT:CPUIRQSEL35.EV for details).
+#define CPU_SCS_NVIC_IABR1_ACTIVE35 0x00000008
+#define CPU_SCS_NVIC_IABR1_ACTIVE35_BITN 3
+#define CPU_SCS_NVIC_IABR1_ACTIVE35_M 0x00000008
+#define CPU_SCS_NVIC_IABR1_ACTIVE35_S 3
+
+// Field: [2] ACTIVE34
+//
+// Reading 0 from this bit implies that interrupt line 34 is not active.
+// Reading 1 from this bit implies that the interrupt line 34 is active (See
+// EVENT:CPUIRQSEL34.EV for details).
+#define CPU_SCS_NVIC_IABR1_ACTIVE34 0x00000004
+#define CPU_SCS_NVIC_IABR1_ACTIVE34_BITN 2
+#define CPU_SCS_NVIC_IABR1_ACTIVE34_M 0x00000004
+#define CPU_SCS_NVIC_IABR1_ACTIVE34_S 2
+
+// Field: [1] ACTIVE33
+//
+// Reading 0 from this bit implies that interrupt line 33 is not active.
+// Reading 1 from this bit implies that the interrupt line 33 is active (See
+// EVENT:CPUIRQSEL33.EV for details).
+#define CPU_SCS_NVIC_IABR1_ACTIVE33 0x00000002
+#define CPU_SCS_NVIC_IABR1_ACTIVE33_BITN 1
+#define CPU_SCS_NVIC_IABR1_ACTIVE33_M 0x00000002
+#define CPU_SCS_NVIC_IABR1_ACTIVE33_S 1
+
+// Field: [0] ACTIVE32
+//
+// Reading 0 from this bit implies that interrupt line 32 is not active.
+// Reading 1 from this bit implies that the interrupt line 32 is active (See
+// EVENT:CPUIRQSEL32.EV for details).
+#define CPU_SCS_NVIC_IABR1_ACTIVE32 0x00000001
+#define CPU_SCS_NVIC_IABR1_ACTIVE32_BITN 0
+#define CPU_SCS_NVIC_IABR1_ACTIVE32_M 0x00000001
+#define CPU_SCS_NVIC_IABR1_ACTIVE32_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_NVIC_IPR0
+//
+//*****************************************************************************
+// Field: [31:24] PRI_3
+//
+// Priority of interrupt 3 (See EVENT:CPUIRQSEL3.EV for details).
+#define CPU_SCS_NVIC_IPR0_PRI_3_W 8
+#define CPU_SCS_NVIC_IPR0_PRI_3_M 0xFF000000
+#define CPU_SCS_NVIC_IPR0_PRI_3_S 24
+
+// Field: [23:16] PRI_2
+//
+// Priority of interrupt 2 (See EVENT:CPUIRQSEL2.EV for details).
+#define CPU_SCS_NVIC_IPR0_PRI_2_W 8
+#define CPU_SCS_NVIC_IPR0_PRI_2_M 0x00FF0000
+#define CPU_SCS_NVIC_IPR0_PRI_2_S 16
+
+// Field: [15:8] PRI_1
+//
+// Priority of interrupt 1 (See EVENT:CPUIRQSEL1.EV for details).
+#define CPU_SCS_NVIC_IPR0_PRI_1_W 8
+#define CPU_SCS_NVIC_IPR0_PRI_1_M 0x0000FF00
+#define CPU_SCS_NVIC_IPR0_PRI_1_S 8
+
+// Field: [7:0] PRI_0
+//
+// Priority of interrupt 0 (See EVENT:CPUIRQSEL0.EV for details).
+#define CPU_SCS_NVIC_IPR0_PRI_0_W 8
+#define CPU_SCS_NVIC_IPR0_PRI_0_M 0x000000FF
+#define CPU_SCS_NVIC_IPR0_PRI_0_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_NVIC_IPR1
+//
+//*****************************************************************************
+// Field: [31:24] PRI_7
+//
+// Priority of interrupt 7 (See EVENT:CPUIRQSEL7.EV for details).
+#define CPU_SCS_NVIC_IPR1_PRI_7_W 8
+#define CPU_SCS_NVIC_IPR1_PRI_7_M 0xFF000000
+#define CPU_SCS_NVIC_IPR1_PRI_7_S 24
+
+// Field: [23:16] PRI_6
+//
+// Priority of interrupt 6 (See EVENT:CPUIRQSEL6.EV for details).
+#define CPU_SCS_NVIC_IPR1_PRI_6_W 8
+#define CPU_SCS_NVIC_IPR1_PRI_6_M 0x00FF0000
+#define CPU_SCS_NVIC_IPR1_PRI_6_S 16
+
+// Field: [15:8] PRI_5
+//
+// Priority of interrupt 5 (See EVENT:CPUIRQSEL5.EV for details).
+#define CPU_SCS_NVIC_IPR1_PRI_5_W 8
+#define CPU_SCS_NVIC_IPR1_PRI_5_M 0x0000FF00
+#define CPU_SCS_NVIC_IPR1_PRI_5_S 8
+
+// Field: [7:0] PRI_4
+//
+// Priority of interrupt 4 (See EVENT:CPUIRQSEL4.EV for details).
+#define CPU_SCS_NVIC_IPR1_PRI_4_W 8
+#define CPU_SCS_NVIC_IPR1_PRI_4_M 0x000000FF
+#define CPU_SCS_NVIC_IPR1_PRI_4_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_NVIC_IPR2
+//
+//*****************************************************************************
+// Field: [31:24] PRI_11
+//
+// Priority of interrupt 11 (See EVENT:CPUIRQSEL11.EV for details).
+#define CPU_SCS_NVIC_IPR2_PRI_11_W 8
+#define CPU_SCS_NVIC_IPR2_PRI_11_M 0xFF000000
+#define CPU_SCS_NVIC_IPR2_PRI_11_S 24
+
+// Field: [23:16] PRI_10
+//
+// Priority of interrupt 10 (See EVENT:CPUIRQSEL10.EV for details).
+#define CPU_SCS_NVIC_IPR2_PRI_10_W 8
+#define CPU_SCS_NVIC_IPR2_PRI_10_M 0x00FF0000
+#define CPU_SCS_NVIC_IPR2_PRI_10_S 16
+
+// Field: [15:8] PRI_9
+//
+// Priority of interrupt 9 (See EVENT:CPUIRQSEL9.EV for details).
+#define CPU_SCS_NVIC_IPR2_PRI_9_W 8
+#define CPU_SCS_NVIC_IPR2_PRI_9_M 0x0000FF00
+#define CPU_SCS_NVIC_IPR2_PRI_9_S 8
+
+// Field: [7:0] PRI_8
+//
+// Priority of interrupt 8 (See EVENT:CPUIRQSEL8.EV for details).
+#define CPU_SCS_NVIC_IPR2_PRI_8_W 8
+#define CPU_SCS_NVIC_IPR2_PRI_8_M 0x000000FF
+#define CPU_SCS_NVIC_IPR2_PRI_8_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_NVIC_IPR3
+//
+//*****************************************************************************
+// Field: [31:24] PRI_15
+//
+// Priority of interrupt 15 (See EVENT:CPUIRQSEL15.EV for details).
+#define CPU_SCS_NVIC_IPR3_PRI_15_W 8
+#define CPU_SCS_NVIC_IPR3_PRI_15_M 0xFF000000
+#define CPU_SCS_NVIC_IPR3_PRI_15_S 24
+
+// Field: [23:16] PRI_14
+//
+// Priority of interrupt 14 (See EVENT:CPUIRQSEL14.EV for details).
+#define CPU_SCS_NVIC_IPR3_PRI_14_W 8
+#define CPU_SCS_NVIC_IPR3_PRI_14_M 0x00FF0000
+#define CPU_SCS_NVIC_IPR3_PRI_14_S 16
+
+// Field: [15:8] PRI_13
+//
+// Priority of interrupt 13 (See EVENT:CPUIRQSEL13.EV for details).
+#define CPU_SCS_NVIC_IPR3_PRI_13_W 8
+#define CPU_SCS_NVIC_IPR3_PRI_13_M 0x0000FF00
+#define CPU_SCS_NVIC_IPR3_PRI_13_S 8
+
+// Field: [7:0] PRI_12
+//
+// Priority of interrupt 12 (See EVENT:CPUIRQSEL12.EV for details).
+#define CPU_SCS_NVIC_IPR3_PRI_12_W 8
+#define CPU_SCS_NVIC_IPR3_PRI_12_M 0x000000FF
+#define CPU_SCS_NVIC_IPR3_PRI_12_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_NVIC_IPR4
+//
+//*****************************************************************************
+// Field: [31:24] PRI_19
+//
+// Priority of interrupt 19 (See EVENT:CPUIRQSEL19.EV for details).
+#define CPU_SCS_NVIC_IPR4_PRI_19_W 8
+#define CPU_SCS_NVIC_IPR4_PRI_19_M 0xFF000000
+#define CPU_SCS_NVIC_IPR4_PRI_19_S 24
+
+// Field: [23:16] PRI_18
+//
+// Priority of interrupt 18 (See EVENT:CPUIRQSEL18.EV for details).
+#define CPU_SCS_NVIC_IPR4_PRI_18_W 8
+#define CPU_SCS_NVIC_IPR4_PRI_18_M 0x00FF0000
+#define CPU_SCS_NVIC_IPR4_PRI_18_S 16
+
+// Field: [15:8] PRI_17
+//
+// Priority of interrupt 17 (See EVENT:CPUIRQSEL17.EV for details).
+#define CPU_SCS_NVIC_IPR4_PRI_17_W 8
+#define CPU_SCS_NVIC_IPR4_PRI_17_M 0x0000FF00
+#define CPU_SCS_NVIC_IPR4_PRI_17_S 8
+
+// Field: [7:0] PRI_16
+//
+// Priority of interrupt 16 (See EVENT:CPUIRQSEL16.EV for details).
+#define CPU_SCS_NVIC_IPR4_PRI_16_W 8
+#define CPU_SCS_NVIC_IPR4_PRI_16_M 0x000000FF
+#define CPU_SCS_NVIC_IPR4_PRI_16_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_NVIC_IPR5
+//
+//*****************************************************************************
+// Field: [31:24] PRI_23
+//
+// Priority of interrupt 23 (See EVENT:CPUIRQSEL23.EV for details).
+#define CPU_SCS_NVIC_IPR5_PRI_23_W 8
+#define CPU_SCS_NVIC_IPR5_PRI_23_M 0xFF000000
+#define CPU_SCS_NVIC_IPR5_PRI_23_S 24
+
+// Field: [23:16] PRI_22
+//
+// Priority of interrupt 22 (See EVENT:CPUIRQSEL22.EV for details).
+#define CPU_SCS_NVIC_IPR5_PRI_22_W 8
+#define CPU_SCS_NVIC_IPR5_PRI_22_M 0x00FF0000
+#define CPU_SCS_NVIC_IPR5_PRI_22_S 16
+
+// Field: [15:8] PRI_21
+//
+// Priority of interrupt 21 (See EVENT:CPUIRQSEL21.EV for details).
+#define CPU_SCS_NVIC_IPR5_PRI_21_W 8
+#define CPU_SCS_NVIC_IPR5_PRI_21_M 0x0000FF00
+#define CPU_SCS_NVIC_IPR5_PRI_21_S 8
+
+// Field: [7:0] PRI_20
+//
+// Priority of interrupt 20 (See EVENT:CPUIRQSEL20.EV for details).
+#define CPU_SCS_NVIC_IPR5_PRI_20_W 8
+#define CPU_SCS_NVIC_IPR5_PRI_20_M 0x000000FF
+#define CPU_SCS_NVIC_IPR5_PRI_20_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_NVIC_IPR6
+//
+//*****************************************************************************
+// Field: [31:24] PRI_27
+//
+// Priority of interrupt 27 (See EVENT:CPUIRQSEL27.EV for details).
+#define CPU_SCS_NVIC_IPR6_PRI_27_W 8
+#define CPU_SCS_NVIC_IPR6_PRI_27_M 0xFF000000
+#define CPU_SCS_NVIC_IPR6_PRI_27_S 24
+
+// Field: [23:16] PRI_26
+//
+// Priority of interrupt 26 (See EVENT:CPUIRQSEL26.EV for details).
+#define CPU_SCS_NVIC_IPR6_PRI_26_W 8
+#define CPU_SCS_NVIC_IPR6_PRI_26_M 0x00FF0000
+#define CPU_SCS_NVIC_IPR6_PRI_26_S 16
+
+// Field: [15:8] PRI_25
+//
+// Priority of interrupt 25 (See EVENT:CPUIRQSEL25.EV for details).
+#define CPU_SCS_NVIC_IPR6_PRI_25_W 8
+#define CPU_SCS_NVIC_IPR6_PRI_25_M 0x0000FF00
+#define CPU_SCS_NVIC_IPR6_PRI_25_S 8
+
+// Field: [7:0] PRI_24
+//
+// Priority of interrupt 24 (See EVENT:CPUIRQSEL24.EV for details).
+#define CPU_SCS_NVIC_IPR6_PRI_24_W 8
+#define CPU_SCS_NVIC_IPR6_PRI_24_M 0x000000FF
+#define CPU_SCS_NVIC_IPR6_PRI_24_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_NVIC_IPR7
+//
+//*****************************************************************************
+// Field: [31:24] PRI_31
+//
+// Priority of interrupt 31 (See EVENT:CPUIRQSEL31.EV for details).
+#define CPU_SCS_NVIC_IPR7_PRI_31_W 8
+#define CPU_SCS_NVIC_IPR7_PRI_31_M 0xFF000000
+#define CPU_SCS_NVIC_IPR7_PRI_31_S 24
+
+// Field: [23:16] PRI_30
+//
+// Priority of interrupt 30 (See EVENT:CPUIRQSEL30.EV for details).
+#define CPU_SCS_NVIC_IPR7_PRI_30_W 8
+#define CPU_SCS_NVIC_IPR7_PRI_30_M 0x00FF0000
+#define CPU_SCS_NVIC_IPR7_PRI_30_S 16
+
+// Field: [15:8] PRI_29
+//
+// Priority of interrupt 29 (See EVENT:CPUIRQSEL29.EV for details).
+#define CPU_SCS_NVIC_IPR7_PRI_29_W 8
+#define CPU_SCS_NVIC_IPR7_PRI_29_M 0x0000FF00
+#define CPU_SCS_NVIC_IPR7_PRI_29_S 8
+
+// Field: [7:0] PRI_28
+//
+// Priority of interrupt 28 (See EVENT:CPUIRQSEL28.EV for details).
+#define CPU_SCS_NVIC_IPR7_PRI_28_W 8
+#define CPU_SCS_NVIC_IPR7_PRI_28_M 0x000000FF
+#define CPU_SCS_NVIC_IPR7_PRI_28_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_NVIC_IPR8
+//
+//*****************************************************************************
+// Field: [31:24] PRI_35
+//
+// Priority of interrupt 35 (See EVENT:CPUIRQSEL35.EV for details).
+#define CPU_SCS_NVIC_IPR8_PRI_35_W 8
+#define CPU_SCS_NVIC_IPR8_PRI_35_M 0xFF000000
+#define CPU_SCS_NVIC_IPR8_PRI_35_S 24
+
+// Field: [23:16] PRI_34
+//
+// Priority of interrupt 34 (See EVENT:CPUIRQSEL34.EV for details).
+#define CPU_SCS_NVIC_IPR8_PRI_34_W 8
+#define CPU_SCS_NVIC_IPR8_PRI_34_M 0x00FF0000
+#define CPU_SCS_NVIC_IPR8_PRI_34_S 16
+
+// Field: [15:8] PRI_33
+//
+// Priority of interrupt 33 (See EVENT:CPUIRQSEL33.EV for details).
+#define CPU_SCS_NVIC_IPR8_PRI_33_W 8
+#define CPU_SCS_NVIC_IPR8_PRI_33_M 0x0000FF00
+#define CPU_SCS_NVIC_IPR8_PRI_33_S 8
+
+// Field: [7:0] PRI_32
+//
+// Priority of interrupt 32 (See EVENT:CPUIRQSEL32.EV for details).
+#define CPU_SCS_NVIC_IPR8_PRI_32_W 8
+#define CPU_SCS_NVIC_IPR8_PRI_32_M 0x000000FF
+#define CPU_SCS_NVIC_IPR8_PRI_32_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_NVIC_IPR9
+//
+//*****************************************************************************
+// Field: [15:8] PRI_37
+//
+// Priority of interrupt 37 (See EVENT:CPUIRQSEL37.EV for details).
+#define CPU_SCS_NVIC_IPR9_PRI_37_W 8
+#define CPU_SCS_NVIC_IPR9_PRI_37_M 0x0000FF00
+#define CPU_SCS_NVIC_IPR9_PRI_37_S 8
+
+// Field: [7:0] PRI_36
+//
+// Priority of interrupt 36 (See EVENT:CPUIRQSEL36.EV for details).
+#define CPU_SCS_NVIC_IPR9_PRI_36_W 8
+#define CPU_SCS_NVIC_IPR9_PRI_36_M 0x000000FF
+#define CPU_SCS_NVIC_IPR9_PRI_36_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_CPUID
+//
+//*****************************************************************************
+// Field: [31:24] IMPLEMENTER
+//
+// Implementor code.
+#define CPU_SCS_CPUID_IMPLEMENTER_W 8
+#define CPU_SCS_CPUID_IMPLEMENTER_M 0xFF000000
+#define CPU_SCS_CPUID_IMPLEMENTER_S 24
+
+// Field: [23:20] VARIANT
+//
+// Implementation defined variant number.
+#define CPU_SCS_CPUID_VARIANT_W 4
+#define CPU_SCS_CPUID_VARIANT_M 0x00F00000
+#define CPU_SCS_CPUID_VARIANT_S 20
+
+// Field: [19:16] CONSTANT
+//
+// Reads as 0xF
+#define CPU_SCS_CPUID_CONSTANT_W 4
+#define CPU_SCS_CPUID_CONSTANT_M 0x000F0000
+#define CPU_SCS_CPUID_CONSTANT_S 16
+
+// Field: [15:4] PARTNO
+//
+// Number of processor within family.
+#define CPU_SCS_CPUID_PARTNO_W 12
+#define CPU_SCS_CPUID_PARTNO_M 0x0000FFF0
+#define CPU_SCS_CPUID_PARTNO_S 4
+
+// Field: [3:0] REVISION
+//
+// Implementation defined revision number.
+#define CPU_SCS_CPUID_REVISION_W 4
+#define CPU_SCS_CPUID_REVISION_M 0x0000000F
+#define CPU_SCS_CPUID_REVISION_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_ICSR
+//
+//*****************************************************************************
+// Field: [31] NMIPENDSET
+//
+// Set pending NMI bit. Setting this bit pends and activates an NMI. Because
+// NMI is the highest-priority interrupt, it takes effect as soon as it
+// registers.
+//
+// 0: No action
+// 1: Set pending NMI
+#define CPU_SCS_ICSR_NMIPENDSET 0x80000000
+#define CPU_SCS_ICSR_NMIPENDSET_BITN 31
+#define CPU_SCS_ICSR_NMIPENDSET_M 0x80000000
+#define CPU_SCS_ICSR_NMIPENDSET_S 31
+
+// Field: [28] PENDSVSET
+//
+// Set pending pendSV bit.
+//
+// 0: No action
+// 1: Set pending PendSV
+#define CPU_SCS_ICSR_PENDSVSET 0x10000000
+#define CPU_SCS_ICSR_PENDSVSET_BITN 28
+#define CPU_SCS_ICSR_PENDSVSET_M 0x10000000
+#define CPU_SCS_ICSR_PENDSVSET_S 28
+
+// Field: [27] PENDSVCLR
+//
+// Clear pending pendSV bit
+//
+// 0: No action
+// 1: Clear pending pendSV
+#define CPU_SCS_ICSR_PENDSVCLR 0x08000000
+#define CPU_SCS_ICSR_PENDSVCLR_BITN 27
+#define CPU_SCS_ICSR_PENDSVCLR_M 0x08000000
+#define CPU_SCS_ICSR_PENDSVCLR_S 27
+
+// Field: [26] PENDSTSET
+//
+// Set a pending SysTick bit.
+//
+// 0: No action
+// 1: Set pending SysTick
+#define CPU_SCS_ICSR_PENDSTSET 0x04000000
+#define CPU_SCS_ICSR_PENDSTSET_BITN 26
+#define CPU_SCS_ICSR_PENDSTSET_M 0x04000000
+#define CPU_SCS_ICSR_PENDSTSET_S 26
+
+// Field: [25] PENDSTCLR
+//
+// Clear pending SysTick bit
+//
+// 0: No action
+// 1: Clear pending SysTick
+#define CPU_SCS_ICSR_PENDSTCLR 0x02000000
+#define CPU_SCS_ICSR_PENDSTCLR_BITN 25
+#define CPU_SCS_ICSR_PENDSTCLR_M 0x02000000
+#define CPU_SCS_ICSR_PENDSTCLR_S 25
+
+// Field: [23] ISRPREEMPT
+//
+// This field can only be used at debug time. It indicates that a pending
+// interrupt is to be taken in the next running cycle. If DHCSR.C_MASKINTS= 0,
+// the interrupt is serviced.
+//
+// 0: A pending exception is not serviced.
+// 1: A pending exception is serviced on exit from the debug halt state
+#define CPU_SCS_ICSR_ISRPREEMPT 0x00800000
+#define CPU_SCS_ICSR_ISRPREEMPT_BITN 23
+#define CPU_SCS_ICSR_ISRPREEMPT_M 0x00800000
+#define CPU_SCS_ICSR_ISRPREEMPT_S 23
+
+// Field: [22] ISRPENDING
+//
+// Interrupt pending flag. Excludes NMI and faults.
+//
+// 0x0: Interrupt not pending
+// 0x1: Interrupt pending
+#define CPU_SCS_ICSR_ISRPENDING 0x00400000
+#define CPU_SCS_ICSR_ISRPENDING_BITN 22
+#define CPU_SCS_ICSR_ISRPENDING_M 0x00400000
+#define CPU_SCS_ICSR_ISRPENDING_S 22
+
+// Field: [17:12] VECTPENDING
+//
+// Pending ISR number field. This field contains the interrupt number of the
+// highest priority pending ISR.
+#define CPU_SCS_ICSR_VECTPENDING_W 6
+#define CPU_SCS_ICSR_VECTPENDING_M 0x0003F000
+#define CPU_SCS_ICSR_VECTPENDING_S 12
+
+// Field: [11] RETTOBASE
+//
+// Indicates whether there are preempted active exceptions:
+//
+// 0: There are preempted active exceptions to execute
+// 1: There are no active exceptions, or the currently-executing exception is
+// the only active exception.
+#define CPU_SCS_ICSR_RETTOBASE 0x00000800
+#define CPU_SCS_ICSR_RETTOBASE_BITN 11
+#define CPU_SCS_ICSR_RETTOBASE_M 0x00000800
+#define CPU_SCS_ICSR_RETTOBASE_S 11
+
+// Field: [8:0] VECTACTIVE
+//
+// Active ISR number field. Reset clears this field.
+#define CPU_SCS_ICSR_VECTACTIVE_W 9
+#define CPU_SCS_ICSR_VECTACTIVE_M 0x000001FF
+#define CPU_SCS_ICSR_VECTACTIVE_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_VTOR
+//
+//*****************************************************************************
+// Field: [29:7] TBLOFF
+//
+// Bits 29 down to 7 of the vector table base offset.
+#define CPU_SCS_VTOR_TBLOFF_W 23
+#define CPU_SCS_VTOR_TBLOFF_M 0x3FFFFF80
+#define CPU_SCS_VTOR_TBLOFF_S 7
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_AIRCR
+//
+//*****************************************************************************
+// Field: [31:16] VECTKEY
+//
+// Register key. Writing to this register (AIRCR) requires 0x05FA in VECTKEY.
+// Otherwise the write value is ignored. Read always returns 0xFA05.
+#define CPU_SCS_AIRCR_VECTKEY_W 16
+#define CPU_SCS_AIRCR_VECTKEY_M 0xFFFF0000
+#define CPU_SCS_AIRCR_VECTKEY_S 16
+
+// Field: [15] ENDIANESS
+//
+// Data endianness bit
+// ENUMs:
+// BIG Big endian
+// LITTLE Little endian
+#define CPU_SCS_AIRCR_ENDIANESS 0x00008000
+#define CPU_SCS_AIRCR_ENDIANESS_BITN 15
+#define CPU_SCS_AIRCR_ENDIANESS_M 0x00008000
+#define CPU_SCS_AIRCR_ENDIANESS_S 15
+#define CPU_SCS_AIRCR_ENDIANESS_BIG 0x00008000
+#define CPU_SCS_AIRCR_ENDIANESS_LITTLE 0x00000000
+
+// Field: [10:8] PRIGROUP
+//
+// Interrupt priority grouping field. This field is a binary point position
+// indicator for creating subpriorities for exceptions that share the same
+// pre-emption level. It divides the PRI_n field in the Interrupt Priority
+// Registers (NVIC_IPR0, NVIC_IPR1,..., and NVIC_IPR8) into a pre-emption
+// level and a subpriority level. The binary point is a left-of value. This
+// means that the PRIGROUP value represents a point starting at the left of the
+// Least Significant Bit (LSB). The lowest value might not be 0 depending on
+// the number of bits allocated for priorities, and implementation choices.
+#define CPU_SCS_AIRCR_PRIGROUP_W 3
+#define CPU_SCS_AIRCR_PRIGROUP_M 0x00000700
+#define CPU_SCS_AIRCR_PRIGROUP_S 8
+
+// Field: [2] SYSRESETREQ
+//
+// Requests a warm reset. Setting this bit does not prevent Halting Debug from
+// running.
+#define CPU_SCS_AIRCR_SYSRESETREQ 0x00000004
+#define CPU_SCS_AIRCR_SYSRESETREQ_BITN 2
+#define CPU_SCS_AIRCR_SYSRESETREQ_M 0x00000004
+#define CPU_SCS_AIRCR_SYSRESETREQ_S 2
+
+// Field: [1] VECTCLRACTIVE
+//
+// Clears all active state information for active NMI, fault, and interrupts.
+// It is the responsibility of the application to reinitialize the stack. This
+// bit is for returning to a known state during debug. The bit self-clears.
+// IPSR is not cleared by this operation. So, if used by an application, it
+// must only be used at the base level of activation, or within a system
+// handler whose active bit can be set.
+#define CPU_SCS_AIRCR_VECTCLRACTIVE 0x00000002
+#define CPU_SCS_AIRCR_VECTCLRACTIVE_BITN 1
+#define CPU_SCS_AIRCR_VECTCLRACTIVE_M 0x00000002
+#define CPU_SCS_AIRCR_VECTCLRACTIVE_S 1
+
+// Field: [0] VECTRESET
+//
+// System Reset bit. Resets the system, with the exception of debug components.
+// This bit is reserved for debug use and can be written to 1 only when the
+// core is halted. The bit self-clears. Writing this bit to 1 while core is not
+// halted may result in unpredictable behavior.
+#define CPU_SCS_AIRCR_VECTRESET 0x00000001
+#define CPU_SCS_AIRCR_VECTRESET_BITN 0
+#define CPU_SCS_AIRCR_VECTRESET_M 0x00000001
+#define CPU_SCS_AIRCR_VECTRESET_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_SCR
+//
+//*****************************************************************************
+// Field: [4] SEVONPEND
+//
+// Send Event on Pending bit:
+//
+// 0: Only enabled interrupts or events can wakeup the processor, disabled
+// interrupts are excluded
+// 1: Enabled events and all interrupts, including disabled interrupts, can
+// wakeup the processor.
+//
+// When an event or interrupt enters pending state, the event signal wakes up
+// the processor from WFE. If
+// the processor is not waiting for an event, the event is registered and
+// affects the next WFE.
+// The processor also wakes up on execution of an SEV instruction.
+#define CPU_SCS_SCR_SEVONPEND 0x00000010
+#define CPU_SCS_SCR_SEVONPEND_BITN 4
+#define CPU_SCS_SCR_SEVONPEND_M 0x00000010
+#define CPU_SCS_SCR_SEVONPEND_S 4
+
+// Field: [2] SLEEPDEEP
+//
+// Controls whether the processor uses sleep or deep sleep as its low power
+// mode
+// ENUMs:
+// DEEPSLEEP Deep sleep
+// SLEEP Sleep
+#define CPU_SCS_SCR_SLEEPDEEP 0x00000004
+#define CPU_SCS_SCR_SLEEPDEEP_BITN 2
+#define CPU_SCS_SCR_SLEEPDEEP_M 0x00000004
+#define CPU_SCS_SCR_SLEEPDEEP_S 2
+#define CPU_SCS_SCR_SLEEPDEEP_DEEPSLEEP 0x00000004
+#define CPU_SCS_SCR_SLEEPDEEP_SLEEP 0x00000000
+
+// Field: [1] SLEEPONEXIT
+//
+// Sleep on exit when returning from Handler mode to Thread mode. Enables
+// interrupt driven applications to avoid returning to empty main application.
+//
+// 0: Do not sleep when returning to thread mode
+// 1: Sleep on ISR exit
+#define CPU_SCS_SCR_SLEEPONEXIT 0x00000002
+#define CPU_SCS_SCR_SLEEPONEXIT_BITN 1
+#define CPU_SCS_SCR_SLEEPONEXIT_M 0x00000002
+#define CPU_SCS_SCR_SLEEPONEXIT_S 1
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_CCR
+//
+//*****************************************************************************
+// Field: [9] STKALIGN
+//
+// Stack alignment bit.
+//
+// 0: Only 4-byte alignment is guaranteed for the SP used prior to the
+// exception on exception entry.
+// 1: On exception entry, the SP used prior to the exception is adjusted to be
+// 8-byte aligned and the context to restore it is saved. The SP is restored on
+// the associated exception return.
+#define CPU_SCS_CCR_STKALIGN 0x00000200
+#define CPU_SCS_CCR_STKALIGN_BITN 9
+#define CPU_SCS_CCR_STKALIGN_M 0x00000200
+#define CPU_SCS_CCR_STKALIGN_S 9
+
+// Field: [8] BFHFNMIGN
+//
+// Enables handlers with priority -1 or -2 to ignore data BusFaults caused by
+// load and store instructions. This applies to the HardFault, NMI, and
+// FAULTMASK escalated handlers:
+//
+// 0: Data BusFaults caused by load and store instructions cause a lock-up
+// 1: Data BusFaults caused by load and store instructions are ignored.
+//
+// Set this bit to 1 only when the handler and its data are in absolutely safe
+// memory. The normal use
+// of this bit is to probe system devices and bridges to detect problems.
+#define CPU_SCS_CCR_BFHFNMIGN 0x00000100
+#define CPU_SCS_CCR_BFHFNMIGN_BITN 8
+#define CPU_SCS_CCR_BFHFNMIGN_M 0x00000100
+#define CPU_SCS_CCR_BFHFNMIGN_S 8
+
+// Field: [4] DIV_0_TRP
+//
+// Enables faulting or halting when the processor executes an SDIV or UDIV
+// instruction with a divisor of 0:
+//
+// 0: Do not trap divide by 0. In this mode, a divide by zero returns a
+// quotient of 0.
+// 1: Trap divide by 0. The relevant Usage Fault Status Register bit is
+// CFSR.DIVBYZERO.
+#define CPU_SCS_CCR_DIV_0_TRP 0x00000010
+#define CPU_SCS_CCR_DIV_0_TRP_BITN 4
+#define CPU_SCS_CCR_DIV_0_TRP_M 0x00000010
+#define CPU_SCS_CCR_DIV_0_TRP_S 4
+
+// Field: [3] UNALIGN_TRP
+//
+// Enables unaligned access traps:
+//
+// 0: Do not trap unaligned halfword and word accesses
+// 1: Trap unaligned halfword and word accesses. The relevant Usage Fault
+// Status Register bit is CFSR.UNALIGNED.
+//
+// If this bit is set to 1, an unaligned access generates a UsageFault.
+// Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of
+// the value in UNALIGN_TRP.
+#define CPU_SCS_CCR_UNALIGN_TRP 0x00000008
+#define CPU_SCS_CCR_UNALIGN_TRP_BITN 3
+#define CPU_SCS_CCR_UNALIGN_TRP_M 0x00000008
+#define CPU_SCS_CCR_UNALIGN_TRP_S 3
+
+// Field: [1] USERSETMPEND
+//
+// Enables unprivileged software access to STIR:
+//
+// 0: User code is not allowed to write to the Software Trigger Interrupt
+// register (STIR).
+// 1: User code can write the Software Trigger Interrupt register (STIR) to
+// trigger (pend) a Main exception, which is associated with the Main stack
+// pointer.
+#define CPU_SCS_CCR_USERSETMPEND 0x00000002
+#define CPU_SCS_CCR_USERSETMPEND_BITN 1
+#define CPU_SCS_CCR_USERSETMPEND_M 0x00000002
+#define CPU_SCS_CCR_USERSETMPEND_S 1
+
+// Field: [0] NONBASETHREDENA
+//
+// Indicates how the processor enters Thread mode:
+//
+// 0: Processor can enter Thread mode only when no exception is active.
+// 1: Processor can enter Thread mode from any level using the appropriate
+// return value (EXC_RETURN).
+//
+// Exception returns occur when one of the following instructions loads a value
+// of 0xFXXXXXXX into the PC while in Handler mode:
+// - POP/LDM which includes loading the PC.
+// - LDR with PC as a destination.
+// - BX with any register.
+// The value written to the PC is intercepted and is referred to as the
+// EXC_RETURN value.
+#define CPU_SCS_CCR_NONBASETHREDENA 0x00000001
+#define CPU_SCS_CCR_NONBASETHREDENA_BITN 0
+#define CPU_SCS_CCR_NONBASETHREDENA_M 0x00000001
+#define CPU_SCS_CCR_NONBASETHREDENA_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_SHPR1
+//
+//*****************************************************************************
+// Field: [23:16] PRI_6
+//
+// Priority of system handler 6. UsageFault
+#define CPU_SCS_SHPR1_PRI_6_W 8
+#define CPU_SCS_SHPR1_PRI_6_M 0x00FF0000
+#define CPU_SCS_SHPR1_PRI_6_S 16
+
+// Field: [15:8] PRI_5
+//
+// Priority of system handler 5: BusFault
+#define CPU_SCS_SHPR1_PRI_5_W 8
+#define CPU_SCS_SHPR1_PRI_5_M 0x0000FF00
+#define CPU_SCS_SHPR1_PRI_5_S 8
+
+// Field: [7:0] PRI_4
+//
+// Priority of system handler 4: MemManage
+#define CPU_SCS_SHPR1_PRI_4_W 8
+#define CPU_SCS_SHPR1_PRI_4_M 0x000000FF
+#define CPU_SCS_SHPR1_PRI_4_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_SHPR2
+//
+//*****************************************************************************
+// Field: [31:24] PRI_11
+//
+// Priority of system handler 11. SVCall
+#define CPU_SCS_SHPR2_PRI_11_W 8
+#define CPU_SCS_SHPR2_PRI_11_M 0xFF000000
+#define CPU_SCS_SHPR2_PRI_11_S 24
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_SHPR3
+//
+//*****************************************************************************
+// Field: [31:24] PRI_15
+//
+// Priority of system handler 15. SysTick exception
+#define CPU_SCS_SHPR3_PRI_15_W 8
+#define CPU_SCS_SHPR3_PRI_15_M 0xFF000000
+#define CPU_SCS_SHPR3_PRI_15_S 24
+
+// Field: [23:16] PRI_14
+//
+// Priority of system handler 14. Pend SV
+#define CPU_SCS_SHPR3_PRI_14_W 8
+#define CPU_SCS_SHPR3_PRI_14_M 0x00FF0000
+#define CPU_SCS_SHPR3_PRI_14_S 16
+
+// Field: [7:0] PRI_12
+//
+// Priority of system handler 12. Debug Monitor
+#define CPU_SCS_SHPR3_PRI_12_W 8
+#define CPU_SCS_SHPR3_PRI_12_M 0x000000FF
+#define CPU_SCS_SHPR3_PRI_12_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_SHCSR
+//
+//*****************************************************************************
+// Field: [18] USGFAULTENA
+//
+// Usage fault system handler enable
+// ENUMs:
+// EN Exception enabled
+// DIS Exception disabled
+#define CPU_SCS_SHCSR_USGFAULTENA 0x00040000
+#define CPU_SCS_SHCSR_USGFAULTENA_BITN 18
+#define CPU_SCS_SHCSR_USGFAULTENA_M 0x00040000
+#define CPU_SCS_SHCSR_USGFAULTENA_S 18
+#define CPU_SCS_SHCSR_USGFAULTENA_EN 0x00040000
+#define CPU_SCS_SHCSR_USGFAULTENA_DIS 0x00000000
+
+// Field: [17] BUSFAULTENA
+//
+// Bus fault system handler enable
+// ENUMs:
+// EN Exception enabled
+// DIS Exception disabled
+#define CPU_SCS_SHCSR_BUSFAULTENA 0x00020000
+#define CPU_SCS_SHCSR_BUSFAULTENA_BITN 17
+#define CPU_SCS_SHCSR_BUSFAULTENA_M 0x00020000
+#define CPU_SCS_SHCSR_BUSFAULTENA_S 17
+#define CPU_SCS_SHCSR_BUSFAULTENA_EN 0x00020000
+#define CPU_SCS_SHCSR_BUSFAULTENA_DIS 0x00000000
+
+// Field: [16] MEMFAULTENA
+//
+// MemManage fault system handler enable
+// ENUMs:
+// EN Exception enabled
+// DIS Exception disabled
+#define CPU_SCS_SHCSR_MEMFAULTENA 0x00010000
+#define CPU_SCS_SHCSR_MEMFAULTENA_BITN 16
+#define CPU_SCS_SHCSR_MEMFAULTENA_M 0x00010000
+#define CPU_SCS_SHCSR_MEMFAULTENA_S 16
+#define CPU_SCS_SHCSR_MEMFAULTENA_EN 0x00010000
+#define CPU_SCS_SHCSR_MEMFAULTENA_DIS 0x00000000
+
+// Field: [15] SVCALLPENDED
+//
+// SVCall pending
+// ENUMs:
+// PENDING Exception is pending.
+// NOTPENDING Exception is not active
+#define CPU_SCS_SHCSR_SVCALLPENDED 0x00008000
+#define CPU_SCS_SHCSR_SVCALLPENDED_BITN 15
+#define CPU_SCS_SHCSR_SVCALLPENDED_M 0x00008000
+#define CPU_SCS_SHCSR_SVCALLPENDED_S 15
+#define CPU_SCS_SHCSR_SVCALLPENDED_PENDING 0x00008000
+#define CPU_SCS_SHCSR_SVCALLPENDED_NOTPENDING 0x00000000
+
+// Field: [14] BUSFAULTPENDED
+//
+// BusFault pending
+// ENUMs:
+// PENDING Exception is pending.
+// NOTPENDING Exception is not active
+#define CPU_SCS_SHCSR_BUSFAULTPENDED 0x00004000
+#define CPU_SCS_SHCSR_BUSFAULTPENDED_BITN 14
+#define CPU_SCS_SHCSR_BUSFAULTPENDED_M 0x00004000
+#define CPU_SCS_SHCSR_BUSFAULTPENDED_S 14
+#define CPU_SCS_SHCSR_BUSFAULTPENDED_PENDING 0x00004000
+#define CPU_SCS_SHCSR_BUSFAULTPENDED_NOTPENDING 0x00000000
+
+// Field: [13] MEMFAULTPENDED
+//
+// MemManage exception pending
+// ENUMs:
+// PENDING Exception is pending.
+// NOTPENDING Exception is not active
+#define CPU_SCS_SHCSR_MEMFAULTPENDED 0x00002000
+#define CPU_SCS_SHCSR_MEMFAULTPENDED_BITN 13
+#define CPU_SCS_SHCSR_MEMFAULTPENDED_M 0x00002000
+#define CPU_SCS_SHCSR_MEMFAULTPENDED_S 13
+#define CPU_SCS_SHCSR_MEMFAULTPENDED_PENDING 0x00002000
+#define CPU_SCS_SHCSR_MEMFAULTPENDED_NOTPENDING 0x00000000
+
+// Field: [12] USGFAULTPENDED
+//
+// Usage fault pending
+// ENUMs:
+// PENDING Exception is pending.
+// NOTPENDING Exception is not active
+#define CPU_SCS_SHCSR_USGFAULTPENDED 0x00001000
+#define CPU_SCS_SHCSR_USGFAULTPENDED_BITN 12
+#define CPU_SCS_SHCSR_USGFAULTPENDED_M 0x00001000
+#define CPU_SCS_SHCSR_USGFAULTPENDED_S 12
+#define CPU_SCS_SHCSR_USGFAULTPENDED_PENDING 0x00001000
+#define CPU_SCS_SHCSR_USGFAULTPENDED_NOTPENDING 0x00000000
+
+// Field: [11] SYSTICKACT
+//
+// SysTick active flag.
+//
+// 0x0: Not active
+// 0x1: Active
+// ENUMs:
+// ACTIVE Exception is active
+// NOTACTIVE Exception is not active
+#define CPU_SCS_SHCSR_SYSTICKACT 0x00000800
+#define CPU_SCS_SHCSR_SYSTICKACT_BITN 11
+#define CPU_SCS_SHCSR_SYSTICKACT_M 0x00000800
+#define CPU_SCS_SHCSR_SYSTICKACT_S 11
+#define CPU_SCS_SHCSR_SYSTICKACT_ACTIVE 0x00000800
+#define CPU_SCS_SHCSR_SYSTICKACT_NOTACTIVE 0x00000000
+
+// Field: [10] PENDSVACT
+//
+// PendSV active
+//
+// 0x0: Not active
+// 0x1: Active
+#define CPU_SCS_SHCSR_PENDSVACT 0x00000400
+#define CPU_SCS_SHCSR_PENDSVACT_BITN 10
+#define CPU_SCS_SHCSR_PENDSVACT_M 0x00000400
+#define CPU_SCS_SHCSR_PENDSVACT_S 10
+
+// Field: [8] MONITORACT
+//
+// Debug monitor active
+// ENUMs:
+// ACTIVE Exception is active
+// NOTACTIVE Exception is not active
+#define CPU_SCS_SHCSR_MONITORACT 0x00000100
+#define CPU_SCS_SHCSR_MONITORACT_BITN 8
+#define CPU_SCS_SHCSR_MONITORACT_M 0x00000100
+#define CPU_SCS_SHCSR_MONITORACT_S 8
+#define CPU_SCS_SHCSR_MONITORACT_ACTIVE 0x00000100
+#define CPU_SCS_SHCSR_MONITORACT_NOTACTIVE 0x00000000
+
+// Field: [7] SVCALLACT
+//
+// SVCall active
+// ENUMs:
+// ACTIVE Exception is active
+// NOTACTIVE Exception is not active
+#define CPU_SCS_SHCSR_SVCALLACT 0x00000080
+#define CPU_SCS_SHCSR_SVCALLACT_BITN 7
+#define CPU_SCS_SHCSR_SVCALLACT_M 0x00000080
+#define CPU_SCS_SHCSR_SVCALLACT_S 7
+#define CPU_SCS_SHCSR_SVCALLACT_ACTIVE 0x00000080
+#define CPU_SCS_SHCSR_SVCALLACT_NOTACTIVE 0x00000000
+
+// Field: [3] USGFAULTACT
+//
+// UsageFault exception active
+// ENUMs:
+// ACTIVE Exception is active
+// NOTACTIVE Exception is not active
+#define CPU_SCS_SHCSR_USGFAULTACT 0x00000008
+#define CPU_SCS_SHCSR_USGFAULTACT_BITN 3
+#define CPU_SCS_SHCSR_USGFAULTACT_M 0x00000008
+#define CPU_SCS_SHCSR_USGFAULTACT_S 3
+#define CPU_SCS_SHCSR_USGFAULTACT_ACTIVE 0x00000008
+#define CPU_SCS_SHCSR_USGFAULTACT_NOTACTIVE 0x00000000
+
+// Field: [1] BUSFAULTACT
+//
+// BusFault exception active
+// ENUMs:
+// ACTIVE Exception is active
+// NOTACTIVE Exception is not active
+#define CPU_SCS_SHCSR_BUSFAULTACT 0x00000002
+#define CPU_SCS_SHCSR_BUSFAULTACT_BITN 1
+#define CPU_SCS_SHCSR_BUSFAULTACT_M 0x00000002
+#define CPU_SCS_SHCSR_BUSFAULTACT_S 1
+#define CPU_SCS_SHCSR_BUSFAULTACT_ACTIVE 0x00000002
+#define CPU_SCS_SHCSR_BUSFAULTACT_NOTACTIVE 0x00000000
+
+// Field: [0] MEMFAULTACT
+//
+// MemManage exception active
+// ENUMs:
+// ACTIVE Exception is active
+// NOTACTIVE Exception is not active
+#define CPU_SCS_SHCSR_MEMFAULTACT 0x00000001
+#define CPU_SCS_SHCSR_MEMFAULTACT_BITN 0
+#define CPU_SCS_SHCSR_MEMFAULTACT_M 0x00000001
+#define CPU_SCS_SHCSR_MEMFAULTACT_S 0
+#define CPU_SCS_SHCSR_MEMFAULTACT_ACTIVE 0x00000001
+#define CPU_SCS_SHCSR_MEMFAULTACT_NOTACTIVE 0x00000000
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_CFSR
+//
+//*****************************************************************************
+// Field: [25] DIVBYZERO
+//
+// When CCR.DIV_0_TRP (see Configuration Control Register on page 8-26) is
+// enabled and an SDIV or UDIV instruction is used with a divisor of 0, this
+// fault occurs The instruction is executed and the return PC points to it. If
+// CCR.DIV_0_TRP is not set, then the divide returns a quotient of 0.
+#define CPU_SCS_CFSR_DIVBYZERO 0x02000000
+#define CPU_SCS_CFSR_DIVBYZERO_BITN 25
+#define CPU_SCS_CFSR_DIVBYZERO_M 0x02000000
+#define CPU_SCS_CFSR_DIVBYZERO_S 25
+
+// Field: [24] UNALIGNED
+//
+// When CCR.UNALIGN_TRP is enabled, and there is an attempt to make an
+// unaligned memory access, then this fault occurs. Unaligned LDM/STM/LDRD/STRD
+// instructions always fault irrespective of the setting of CCR.UNALIGN_TRP.
+#define CPU_SCS_CFSR_UNALIGNED 0x01000000
+#define CPU_SCS_CFSR_UNALIGNED_BITN 24
+#define CPU_SCS_CFSR_UNALIGNED_M 0x01000000
+#define CPU_SCS_CFSR_UNALIGNED_S 24
+
+// Field: [19] NOCP
+//
+// Attempt to use a coprocessor instruction. The processor does not support
+// coprocessor instructions.
+#define CPU_SCS_CFSR_NOCP 0x00080000
+#define CPU_SCS_CFSR_NOCP_BITN 19
+#define CPU_SCS_CFSR_NOCP_M 0x00080000
+#define CPU_SCS_CFSR_NOCP_S 19
+
+// Field: [18] INVPC
+//
+// Attempt to load EXC_RETURN into PC illegally. Invalid instruction, invalid
+// context, invalid value. The return PC points to the instruction that tried
+// to set the PC.
+#define CPU_SCS_CFSR_INVPC 0x00040000
+#define CPU_SCS_CFSR_INVPC_BITN 18
+#define CPU_SCS_CFSR_INVPC_M 0x00040000
+#define CPU_SCS_CFSR_INVPC_S 18
+
+// Field: [17] INVSTATE
+//
+// Indicates an attempt to execute in an invalid EPSR state (e.g. after a BX
+// type instruction has changed state). This includes state change after entry
+// to or return from exception, as well as from inter-working instructions.
+// Return PC points to faulting instruction, with the invalid state.
+#define CPU_SCS_CFSR_INVSTATE 0x00020000
+#define CPU_SCS_CFSR_INVSTATE_BITN 17
+#define CPU_SCS_CFSR_INVSTATE_M 0x00020000
+#define CPU_SCS_CFSR_INVSTATE_S 17
+
+// Field: [16] UNDEFINSTR
+//
+// This bit is set when the processor attempts to execute an undefined
+// instruction. This is an instruction that the processor cannot decode. The
+// return PC points to the undefined instruction.
+#define CPU_SCS_CFSR_UNDEFINSTR 0x00010000
+#define CPU_SCS_CFSR_UNDEFINSTR_BITN 16
+#define CPU_SCS_CFSR_UNDEFINSTR_M 0x00010000
+#define CPU_SCS_CFSR_UNDEFINSTR_S 16
+
+// Field: [15] BFARVALID
+//
+// This bit is set if the Bus Fault Address Register (BFAR) contains a valid
+// address. This is true after a bus fault where the address is known. Other
+// faults can clear this bit, such as a Mem Manage fault occurring later. If a
+// Bus fault occurs that is escalated to a Hard Fault because of priority, the
+// Hard Fault handler must clear this bit. This prevents problems if returning
+// to a stacked active Bus fault handler whose BFAR value has been overwritten.
+#define CPU_SCS_CFSR_BFARVALID 0x00008000
+#define CPU_SCS_CFSR_BFARVALID_BITN 15
+#define CPU_SCS_CFSR_BFARVALID_M 0x00008000
+#define CPU_SCS_CFSR_BFARVALID_S 15
+
+// Field: [12] STKERR
+//
+// Stacking from exception has caused one or more bus faults. The SP is still
+// adjusted and the values in the context area on the stack might be incorrect.
+// BFAR is not written.
+#define CPU_SCS_CFSR_STKERR 0x00001000
+#define CPU_SCS_CFSR_STKERR_BITN 12
+#define CPU_SCS_CFSR_STKERR_M 0x00001000
+#define CPU_SCS_CFSR_STKERR_S 12
+
+// Field: [11] UNSTKERR
+//
+// Unstack from exception return has caused one or more bus faults. This is
+// chained to the handler, so that the original return stack is still present.
+// SP is not adjusted from failing return and new save is not performed. BFAR
+// is not written.
+#define CPU_SCS_CFSR_UNSTKERR 0x00000800
+#define CPU_SCS_CFSR_UNSTKERR_BITN 11
+#define CPU_SCS_CFSR_UNSTKERR_M 0x00000800
+#define CPU_SCS_CFSR_UNSTKERR_S 11
+
+// Field: [10] IMPRECISERR
+//
+// Imprecise data bus error. It is a BusFault, but the Return PC is not related
+// to the causing instruction. This is not a synchronous fault. So, if detected
+// when the priority of the current activation is higher than the Bus Fault, it
+// only pends. Bus fault activates when returning to a lower priority
+// activation. If a precise fault occurs before returning to a lower priority
+// exception, the handler detects both IMPRECISERR set and one of the precise
+// fault status bits set at the same time. BFAR is not written.
+#define CPU_SCS_CFSR_IMPRECISERR 0x00000400
+#define CPU_SCS_CFSR_IMPRECISERR_BITN 10
+#define CPU_SCS_CFSR_IMPRECISERR_M 0x00000400
+#define CPU_SCS_CFSR_IMPRECISERR_S 10
+
+// Field: [9] PRECISERR
+//
+// Precise data bus error return.
+#define CPU_SCS_CFSR_PRECISERR 0x00000200
+#define CPU_SCS_CFSR_PRECISERR_BITN 9
+#define CPU_SCS_CFSR_PRECISERR_M 0x00000200
+#define CPU_SCS_CFSR_PRECISERR_S 9
+
+// Field: [8] IBUSERR
+//
+// Instruction bus error flag. This flag is set by a prefetch error. The fault
+// stops on the instruction, so if the error occurs under a branch shadow, no
+// fault occurs. BFAR is not written.
+#define CPU_SCS_CFSR_IBUSERR 0x00000100
+#define CPU_SCS_CFSR_IBUSERR_BITN 8
+#define CPU_SCS_CFSR_IBUSERR_M 0x00000100
+#define CPU_SCS_CFSR_IBUSERR_S 8
+
+// Field: [7] MMARVALID
+//
+// Memory Manage Address Register (MMFAR) address valid flag. A later-arriving
+// fault, such as a bus fault, can clear a memory manage fault.. If a MemManage
+// fault occurs that is escalated to a Hard Fault because of priority, the Hard
+// Fault handler must clear this bit. This prevents problems on return to a
+// stacked active MemManage handler whose MMFAR value has been overwritten.
+#define CPU_SCS_CFSR_MMARVALID 0x00000080
+#define CPU_SCS_CFSR_MMARVALID_BITN 7
+#define CPU_SCS_CFSR_MMARVALID_M 0x00000080
+#define CPU_SCS_CFSR_MMARVALID_S 7
+
+// Field: [4] MSTKERR
+//
+// Stacking from exception has caused one or more access violations. The SP is
+// still adjusted and the values in the context area on the stack might be
+// incorrect. MMFAR is not written.
+#define CPU_SCS_CFSR_MSTKERR 0x00000010
+#define CPU_SCS_CFSR_MSTKERR_BITN 4
+#define CPU_SCS_CFSR_MSTKERR_M 0x00000010
+#define CPU_SCS_CFSR_MSTKERR_S 4
+
+// Field: [3] MUNSTKERR
+//
+// Unstack from exception return has caused one or more access violations. This
+// is chained to the handler, so that the original return stack is still
+// present. SP is not adjusted from failing return and new save is not
+// performed. MMFAR is not written.
+#define CPU_SCS_CFSR_MUNSTKERR 0x00000008
+#define CPU_SCS_CFSR_MUNSTKERR_BITN 3
+#define CPU_SCS_CFSR_MUNSTKERR_M 0x00000008
+#define CPU_SCS_CFSR_MUNSTKERR_S 3
+
+// Field: [1] DACCVIOL
+//
+// Data access violation flag. Attempting to load or store at a location that
+// does not permit the operation sets this flag. The return PC points to the
+// faulting instruction. This error loads MMFAR with the address of the
+// attempted access.
+#define CPU_SCS_CFSR_DACCVIOL 0x00000002
+#define CPU_SCS_CFSR_DACCVIOL_BITN 1
+#define CPU_SCS_CFSR_DACCVIOL_M 0x00000002
+#define CPU_SCS_CFSR_DACCVIOL_S 1
+
+// Field: [0] IACCVIOL
+//
+// Instruction access violation flag. Attempting to fetch an instruction from a
+// location that does not permit execution sets this flag. This occurs on any
+// access to an XN region, even when the MPU is disabled or not present. The
+// return PC points to the faulting instruction. MMFAR is not written.
+#define CPU_SCS_CFSR_IACCVIOL 0x00000001
+#define CPU_SCS_CFSR_IACCVIOL_BITN 0
+#define CPU_SCS_CFSR_IACCVIOL_M 0x00000001
+#define CPU_SCS_CFSR_IACCVIOL_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_HFSR
+//
+//*****************************************************************************
+// Field: [31] DEBUGEVT
+//
+// This bit is set if there is a fault related to debug. This is only possible
+// when halting debug is not enabled. For monitor enabled debug, it only
+// happens for BKPT when the current priority is higher than the monitor. When
+// both halting and monitor debug are disabled, it only happens for debug
+// events that are not ignored (minimally, BKPT). The Debug Fault Status
+// Register is updated.
+#define CPU_SCS_HFSR_DEBUGEVT 0x80000000
+#define CPU_SCS_HFSR_DEBUGEVT_BITN 31
+#define CPU_SCS_HFSR_DEBUGEVT_M 0x80000000
+#define CPU_SCS_HFSR_DEBUGEVT_S 31
+
+// Field: [30] FORCED
+//
+// Hard Fault activated because a Configurable Fault was received and cannot
+// activate because of priority or because the Configurable Fault is disabled.
+// The Hard Fault handler then has to read the other fault status registers to
+// determine cause.
+#define CPU_SCS_HFSR_FORCED 0x40000000
+#define CPU_SCS_HFSR_FORCED_BITN 30
+#define CPU_SCS_HFSR_FORCED_M 0x40000000
+#define CPU_SCS_HFSR_FORCED_S 30
+
+// Field: [1] VECTTBL
+//
+// This bit is set if there is a fault because of vector table read on
+// exception processing (Bus Fault). This case is always a Hard Fault. The
+// return PC points to the pre-empted instruction.
+#define CPU_SCS_HFSR_VECTTBL 0x00000002
+#define CPU_SCS_HFSR_VECTTBL_BITN 1
+#define CPU_SCS_HFSR_VECTTBL_M 0x00000002
+#define CPU_SCS_HFSR_VECTTBL_S 1
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_DFSR
+//
+//*****************************************************************************
+// Field: [4] EXTERNAL
+//
+// External debug request flag. The processor stops on next instruction
+// boundary.
+//
+// 0x0: External debug request signal not asserted
+// 0x1: External debug request signal asserted
+#define CPU_SCS_DFSR_EXTERNAL 0x00000010
+#define CPU_SCS_DFSR_EXTERNAL_BITN 4
+#define CPU_SCS_DFSR_EXTERNAL_M 0x00000010
+#define CPU_SCS_DFSR_EXTERNAL_S 4
+
+// Field: [3] VCATCH
+//
+// Vector catch flag. When this flag is set, a flag in one of the local fault
+// status registers is also set to indicate the type of fault.
+//
+// 0x0: No vector catch occurred
+// 0x1: Vector catch occurred
+#define CPU_SCS_DFSR_VCATCH 0x00000008
+#define CPU_SCS_DFSR_VCATCH_BITN 3
+#define CPU_SCS_DFSR_VCATCH_M 0x00000008
+#define CPU_SCS_DFSR_VCATCH_S 3
+
+// Field: [2] DWTTRAP
+//
+// Data Watchpoint and Trace (DWT) flag. The processor stops at the current
+// instruction or at the next instruction.
+//
+// 0x0: No DWT match
+// 0x1: DWT match
+#define CPU_SCS_DFSR_DWTTRAP 0x00000004
+#define CPU_SCS_DFSR_DWTTRAP_BITN 2
+#define CPU_SCS_DFSR_DWTTRAP_M 0x00000004
+#define CPU_SCS_DFSR_DWTTRAP_S 2
+
+// Field: [1] BKPT
+//
+// BKPT flag. The BKPT flag is set by a BKPT instruction in flash patch code,
+// and also by normal code. Return PC points to breakpoint containing
+// instruction.
+//
+// 0x0: No BKPT instruction execution
+// 0x1: BKPT instruction execution
+#define CPU_SCS_DFSR_BKPT 0x00000002
+#define CPU_SCS_DFSR_BKPT_BITN 1
+#define CPU_SCS_DFSR_BKPT_M 0x00000002
+#define CPU_SCS_DFSR_BKPT_S 1
+
+// Field: [0] HALTED
+//
+// Halt request flag. The processor is halted on the next instruction.
+//
+// 0x0: No halt request
+// 0x1: Halt requested by NVIC, including step
+#define CPU_SCS_DFSR_HALTED 0x00000001
+#define CPU_SCS_DFSR_HALTED_BITN 0
+#define CPU_SCS_DFSR_HALTED_M 0x00000001
+#define CPU_SCS_DFSR_HALTED_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_MMFAR
+//
+//*****************************************************************************
+// Field: [31:0] ADDRESS
+//
+// Mem Manage fault address field.
+// This field is the data address of a faulted load or store attempt. When an
+// unaligned access faults, the address is the actual address that faulted.
+// Because an access can be split into multiple parts, each aligned, this
+// address can be any offset in the range of the requested size. Flags
+// CFSR.IACCVIOL, CFSR.DACCVIOL ,CFSR.MUNSTKERR and CFSR.MSTKERR in combination
+// with CFSR.MMARVALIDindicate the cause of the fault.
+#define CPU_SCS_MMFAR_ADDRESS_W 32
+#define CPU_SCS_MMFAR_ADDRESS_M 0xFFFFFFFF
+#define CPU_SCS_MMFAR_ADDRESS_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_BFAR
+//
+//*****************************************************************************
+// Field: [31:0] ADDRESS
+//
+// Bus fault address field. This field is the data address of a faulted load or
+// store attempt. When an unaligned access faults, the address is the address
+// requested by the instruction, even if that is not the address that faulted.
+// Flags CFSR.IBUSERR, CFSR.PRECISERR, CFSR.IMPRECISERR, CFSR.UNSTKERR and
+// CFSR.STKERR in combination with CFSR.BFARVALID indicate the cause of the
+// fault.
+#define CPU_SCS_BFAR_ADDRESS_W 32
+#define CPU_SCS_BFAR_ADDRESS_M 0xFFFFFFFF
+#define CPU_SCS_BFAR_ADDRESS_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_AFSR
+//
+//*****************************************************************************
+// Field: [31:0] IMPDEF
+//
+// Implementation defined. The bits map directly onto the signal assignment to
+// the auxiliary fault inputs. Tied to 0
+#define CPU_SCS_AFSR_IMPDEF_W 32
+#define CPU_SCS_AFSR_IMPDEF_M 0xFFFFFFFF
+#define CPU_SCS_AFSR_IMPDEF_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_ID_PFR0
+//
+//*****************************************************************************
+// Field: [7:4] STATE1
+//
+// State1 (T-bit == 1)
+//
+// 0x0: N/A
+// 0x1: N/A
+// 0x2: Thumb-2 encoding with the 16-bit basic instructions plus 32-bit
+// Buncond/BL but no other 32-bit basic instructions (Note non-basic 32-bit
+// instructions can be added using the appropriate instruction attribute, but
+// other 32-bit basic instructions cannot.)
+// 0x3: Thumb-2 encoding with all Thumb-2 basic instructions
+#define CPU_SCS_ID_PFR0_STATE1_W 4
+#define CPU_SCS_ID_PFR0_STATE1_M 0x000000F0
+#define CPU_SCS_ID_PFR0_STATE1_S 4
+
+// Field: [3:0] STATE0
+//
+// State0 (T-bit == 0)
+//
+// 0x0: No ARM encoding
+// 0x1: N/A
+#define CPU_SCS_ID_PFR0_STATE0_W 4
+#define CPU_SCS_ID_PFR0_STATE0_M 0x0000000F
+#define CPU_SCS_ID_PFR0_STATE0_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_ID_PFR1
+//
+//*****************************************************************************
+// Field: [11:8] MICROCONTROLLER_PROGRAMMERS_MODEL
+//
+// Microcontroller programmer's model
+//
+// 0x0: Not supported
+// 0x2: Two-stack support
+#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_W 4
+#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_M 0x00000F00
+#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_S 8
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_ID_DFR0
+//
+//*****************************************************************************
+// Field: [23:20] MICROCONTROLLER_DEBUG_MODEL
+//
+// Microcontroller Debug Model - memory mapped
+//
+// 0x0: Not supported
+// 0x1: Microcontroller debug v1 (ITMv1 and DWTv1)
+#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_W 4
+#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_M 0x00F00000
+#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_S 20
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_ID_AFR0
+//
+//*****************************************************************************
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_ID_MMFR0
+//
+//*****************************************************************************
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_ID_MMFR1
+//
+//*****************************************************************************
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_ID_MMFR2
+//
+//*****************************************************************************
+// Field: [24] WAIT_FOR_INTERRUPT_STALLING
+//
+// wait for interrupt stalling
+//
+// 0x0: Not supported
+// 0x1: Wait for interrupt supported
+#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING 0x01000000
+#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_BITN 24
+#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_M 0x01000000
+#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_S 24
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_ID_MMFR3
+//
+//*****************************************************************************
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_ID_ISAR0
+//
+//*****************************************************************************
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_ID_ISAR1
+//
+//*****************************************************************************
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_ID_ISAR2
+//
+//*****************************************************************************
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_ID_ISAR3
+//
+//*****************************************************************************
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_ID_ISAR4
+//
+//*****************************************************************************
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_CPACR
+//
+//*****************************************************************************
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_MPU_TYPE
+//
+//*****************************************************************************
+// Field: [23:16] IREGION
+//
+// The processor core uses only a unified MPU, this field always reads 0x0.
+#define CPU_SCS_MPU_TYPE_IREGION_W 8
+#define CPU_SCS_MPU_TYPE_IREGION_M 0x00FF0000
+#define CPU_SCS_MPU_TYPE_IREGION_S 16
+
+// Field: [15:8] DREGION
+//
+// Number of supported MPU regions field. This field reads 0x08 indicating
+// eight MPU regions.
+#define CPU_SCS_MPU_TYPE_DREGION_W 8
+#define CPU_SCS_MPU_TYPE_DREGION_M 0x0000FF00
+#define CPU_SCS_MPU_TYPE_DREGION_S 8
+
+// Field: [0] SEPARATE
+//
+// The processor core uses only a unified MPU, thus this field is always 0.
+#define CPU_SCS_MPU_TYPE_SEPARATE 0x00000001
+#define CPU_SCS_MPU_TYPE_SEPARATE_BITN 0
+#define CPU_SCS_MPU_TYPE_SEPARATE_M 0x00000001
+#define CPU_SCS_MPU_TYPE_SEPARATE_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_MPU_CTRL
+//
+//*****************************************************************************
+// Field: [2] PRIVDEFENA
+//
+// This bit enables the default memory map for privileged access, as a
+// background region, when the MPU is enabled. The background region acts as if
+// it was region number 1 before any settable regions. Any region that is set
+// up overlays this default map, and overrides it. If this bit is not set, the
+// default memory map is disabled, and memory not covered by a region faults.
+// This applies to memory type, Execute Never (XN), cache and shareable rules.
+// However, this only applies to privileged mode (fetch and data access). User
+// mode code faults unless a region has been set up for its code and data. When
+// the MPU is disabled, the default map acts on both privileged and user mode
+// code. XN and SO rules always apply to the system partition whether this
+// enable is set or not. If the MPU is disabled, this bit is ignored.
+#define CPU_SCS_MPU_CTRL_PRIVDEFENA 0x00000004
+#define CPU_SCS_MPU_CTRL_PRIVDEFENA_BITN 2
+#define CPU_SCS_MPU_CTRL_PRIVDEFENA_M 0x00000004
+#define CPU_SCS_MPU_CTRL_PRIVDEFENA_S 2
+
+// Field: [1] HFNMIENA
+//
+// This bit enables the MPU when in Hard Fault, NMI, and FAULTMASK escalated
+// handlers. If this bit and ENABLE are set, the MPU is enabled when in these
+// handlers. If this bit is not set, the MPU is disabled when in these
+// handlers, regardless of the value of ENABLE bit. If this bit is set and
+// ENABLE is not set, behavior is unpredictable.
+#define CPU_SCS_MPU_CTRL_HFNMIENA 0x00000002
+#define CPU_SCS_MPU_CTRL_HFNMIENA_BITN 1
+#define CPU_SCS_MPU_CTRL_HFNMIENA_M 0x00000002
+#define CPU_SCS_MPU_CTRL_HFNMIENA_S 1
+
+// Field: [0] ENABLE
+//
+// Enable MPU
+//
+// 0: MPU disabled
+// 1: MPU enabled
+#define CPU_SCS_MPU_CTRL_ENABLE 0x00000001
+#define CPU_SCS_MPU_CTRL_ENABLE_BITN 0
+#define CPU_SCS_MPU_CTRL_ENABLE_M 0x00000001
+#define CPU_SCS_MPU_CTRL_ENABLE_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_MPU_RNR
+//
+//*****************************************************************************
+// Field: [7:0] REGION
+//
+// Region select field.
+// This field selects the region to operate on when using the MPU_RASR and
+// MPU_RBAR. It must be written first except when the address MPU_RBAR.VALID
+// and MPU_RBAR.REGION fields are written, which overwrites this.
+#define CPU_SCS_MPU_RNR_REGION_W 8
+#define CPU_SCS_MPU_RNR_REGION_M 0x000000FF
+#define CPU_SCS_MPU_RNR_REGION_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_MPU_RBAR
+//
+//*****************************************************************************
+// Field: [31:5] ADDR
+//
+// Region base address field.
+// The position of the LSB depends on the region size, so that the base address
+// is aligned according to an even multiple of size. The power of 2 size
+// specified by the SZENABLE field of the MPU Region Attribute and Size
+// Register defines how many bits of base address are used.
+#define CPU_SCS_MPU_RBAR_ADDR_W 27
+#define CPU_SCS_MPU_RBAR_ADDR_M 0xFFFFFFE0
+#define CPU_SCS_MPU_RBAR_ADDR_S 5
+
+// Field: [4] VALID
+//
+// MPU region number valid:
+// 0: MPU_RNR remains unchanged and is interpreted.
+// 1: MPU_RNR is overwritten by REGION.
+#define CPU_SCS_MPU_RBAR_VALID 0x00000010
+#define CPU_SCS_MPU_RBAR_VALID_BITN 4
+#define CPU_SCS_MPU_RBAR_VALID_M 0x00000010
+#define CPU_SCS_MPU_RBAR_VALID_S 4
+
+// Field: [3:0] REGION
+//
+// MPU region override field
+#define CPU_SCS_MPU_RBAR_REGION_W 4
+#define CPU_SCS_MPU_RBAR_REGION_M 0x0000000F
+#define CPU_SCS_MPU_RBAR_REGION_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_MPU_RASR
+//
+//*****************************************************************************
+// Field: [28] XN
+//
+// Instruction access disable:
+// 0: Enable instruction fetches
+// 1: Disable instruction fetches
+#define CPU_SCS_MPU_RASR_XN 0x10000000
+#define CPU_SCS_MPU_RASR_XN_BITN 28
+#define CPU_SCS_MPU_RASR_XN_M 0x10000000
+#define CPU_SCS_MPU_RASR_XN_S 28
+
+// Field: [26:24] AP
+//
+// Data access permission:
+// 0x0: Priviliged permissions: No access. User permissions: No access.
+// 0x1: Priviliged permissions: Read-write. User permissions: No access.
+// 0x2: Priviliged permissions: Read-write. User permissions: Read-only.
+// 0x3: Priviliged permissions: Read-write. User permissions: Read-write.
+// 0x4: Reserved
+// 0x5: Priviliged permissions: Read-only. User permissions: No access.
+// 0x6: Priviliged permissions: Read-only. User permissions: Read-only.
+// 0x7: Priviliged permissions: Read-only. User permissions: Read-only.
+#define CPU_SCS_MPU_RASR_AP_W 3
+#define CPU_SCS_MPU_RASR_AP_M 0x07000000
+#define CPU_SCS_MPU_RASR_AP_S 24
+
+// Field: [21:19] TEX
+//
+// Type extension
+#define CPU_SCS_MPU_RASR_TEX_W 3
+#define CPU_SCS_MPU_RASR_TEX_M 0x00380000
+#define CPU_SCS_MPU_RASR_TEX_S 19
+
+// Field: [18] S
+//
+// Shareable bit:
+// 0: Not shareable
+// 1: Shareable
+#define CPU_SCS_MPU_RASR_S 0x00040000
+#define CPU_SCS_MPU_RASR_S_BITN 18
+#define CPU_SCS_MPU_RASR_S_M 0x00040000
+#define CPU_SCS_MPU_RASR_S_S 18
+
+// Field: [17] C
+//
+// Cacheable bit:
+// 0: Not cacheable
+// 1: Cacheable
+#define CPU_SCS_MPU_RASR_C 0x00020000
+#define CPU_SCS_MPU_RASR_C_BITN 17
+#define CPU_SCS_MPU_RASR_C_M 0x00020000
+#define CPU_SCS_MPU_RASR_C_S 17
+
+// Field: [16] B
+//
+// Bufferable bit:
+// 0: Not bufferable
+// 1: Bufferable
+#define CPU_SCS_MPU_RASR_B 0x00010000
+#define CPU_SCS_MPU_RASR_B_BITN 16
+#define CPU_SCS_MPU_RASR_B_M 0x00010000
+#define CPU_SCS_MPU_RASR_B_S 16
+
+// Field: [15:8] SRD
+//
+// Sub-Region Disable field:
+// Setting a bit in this field disables the corresponding sub-region. Regions
+// are split into eight equal-sized sub-regions. Sub-regions are not supported
+// for region sizes of 128 bytes and less.
+#define CPU_SCS_MPU_RASR_SRD_W 8
+#define CPU_SCS_MPU_RASR_SRD_M 0x0000FF00
+#define CPU_SCS_MPU_RASR_SRD_S 8
+
+// Field: [5:1] SIZE
+//
+// MPU Protection Region Size Field:
+// 0x04: 32B
+// 0x05: 64B
+// 0x06: 128B
+// 0x07: 256B
+// 0x08: 512B
+// 0x09: 1KB
+// 0x0A: 2KB
+// 0x0B: 4KB
+// 0x0C: 8KB
+// 0x0D: 16KB
+// 0x0E: 32KB
+// 0x0F: 64KB
+// 0x10: 128KB
+// 0x11: 256KB
+// 0x12: 512KB
+// 0x13: 1MB
+// 0x14: 2MB
+// 0x15: 4MB
+// 0x16: 8MB
+// 0x17: 16MB
+// 0x18: 32MB
+// 0x19: 64MB
+// 0x1A: 128MB
+// 0x1B: 256MB
+// 0x1C: 512MB
+// 0x1D: 1GB
+// 0x1E: 2GB
+// 0x1F: 4GB
+#define CPU_SCS_MPU_RASR_SIZE_W 5
+#define CPU_SCS_MPU_RASR_SIZE_M 0x0000003E
+#define CPU_SCS_MPU_RASR_SIZE_S 1
+
+// Field: [0] ENABLE
+//
+// Region enable bit:
+// 0: Disable region
+// 1: Enable region
+#define CPU_SCS_MPU_RASR_ENABLE 0x00000001
+#define CPU_SCS_MPU_RASR_ENABLE_BITN 0
+#define CPU_SCS_MPU_RASR_ENABLE_M 0x00000001
+#define CPU_SCS_MPU_RASR_ENABLE_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_MPU_RBAR_A1
+//
+//*****************************************************************************
+// Field: [31:0] MPU_RBAR_A1
+//
+// Alias for MPU_RBAR
+#define CPU_SCS_MPU_RBAR_A1_MPU_RBAR_A1_W 32
+#define CPU_SCS_MPU_RBAR_A1_MPU_RBAR_A1_M 0xFFFFFFFF
+#define CPU_SCS_MPU_RBAR_A1_MPU_RBAR_A1_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_MPU_RASR_A1
+//
+//*****************************************************************************
+// Field: [31:0] MPU_RASR_A1
+//
+// Alias for MPU_RASR
+#define CPU_SCS_MPU_RASR_A1_MPU_RASR_A1_W 32
+#define CPU_SCS_MPU_RASR_A1_MPU_RASR_A1_M 0xFFFFFFFF
+#define CPU_SCS_MPU_RASR_A1_MPU_RASR_A1_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_MPU_RBAR_A2
+//
+//*****************************************************************************
+// Field: [31:0] MPU_RBAR_A2
+//
+// Alias for MPU_RBAR
+#define CPU_SCS_MPU_RBAR_A2_MPU_RBAR_A2_W 32
+#define CPU_SCS_MPU_RBAR_A2_MPU_RBAR_A2_M 0xFFFFFFFF
+#define CPU_SCS_MPU_RBAR_A2_MPU_RBAR_A2_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_MPU_RASR_A2
+//
+//*****************************************************************************
+// Field: [31:0] MPU_RASR_A2
+//
+// Alias for MPU_RASR
+#define CPU_SCS_MPU_RASR_A2_MPU_RASR_A2_W 32
+#define CPU_SCS_MPU_RASR_A2_MPU_RASR_A2_M 0xFFFFFFFF
+#define CPU_SCS_MPU_RASR_A2_MPU_RASR_A2_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_MPU_RBAR_A3
+//
+//*****************************************************************************
+// Field: [31:0] MPU_RBAR_A3
+//
+// Alias for MPU_RBAR
+#define CPU_SCS_MPU_RBAR_A3_MPU_RBAR_A3_W 32
+#define CPU_SCS_MPU_RBAR_A3_MPU_RBAR_A3_M 0xFFFFFFFF
+#define CPU_SCS_MPU_RBAR_A3_MPU_RBAR_A3_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_MPU_RASR_A3
+//
+//*****************************************************************************
+// Field: [31:0] MPU_RASR_A3
+//
+// Alias for MPU_RASR
+#define CPU_SCS_MPU_RASR_A3_MPU_RASR_A3_W 32
+#define CPU_SCS_MPU_RASR_A3_MPU_RASR_A3_M 0xFFFFFFFF
+#define CPU_SCS_MPU_RASR_A3_MPU_RASR_A3_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_DHCSR
+//
+//*****************************************************************************
+// Field: [25] S_RESET_ST
+//
+// Indicates that the core has been reset, or is now being reset, since the
+// last time this bit was read. This a sticky bit that clears on read. So,
+// reading twice and getting 1 then 0 means it was reset in the past. Reading
+// twice and getting 1 both times means that it is being reset now (held in
+// reset still).
+// When writing to this register, 0 must be written this bit-field, otherwise
+// the write operation is ignored and no bits are written into the register.
+#define CPU_SCS_DHCSR_S_RESET_ST 0x02000000
+#define CPU_SCS_DHCSR_S_RESET_ST_BITN 25
+#define CPU_SCS_DHCSR_S_RESET_ST_M 0x02000000
+#define CPU_SCS_DHCSR_S_RESET_ST_S 25
+
+// Field: [24] S_RETIRE_ST
+//
+// Indicates that an instruction has completed since last read. This is a
+// sticky bit that clears on read. This determines if the core is stalled on a
+// load/store or fetch.
+// When writing to this register, 0 must be written this bit-field, otherwise
+// the write operation is ignored and no bits are written into the register.
+#define CPU_SCS_DHCSR_S_RETIRE_ST 0x01000000
+#define CPU_SCS_DHCSR_S_RETIRE_ST_BITN 24
+#define CPU_SCS_DHCSR_S_RETIRE_ST_M 0x01000000
+#define CPU_SCS_DHCSR_S_RETIRE_ST_S 24
+
+// Field: [19] S_LOCKUP
+//
+// Reads as one if the core is running (not halted) and a lockup condition is
+// present.
+// When writing to this register, 1 must be written this bit-field, otherwise
+// the write operation is ignored and no bits are written into the register.
+#define CPU_SCS_DHCSR_S_LOCKUP 0x00080000
+#define CPU_SCS_DHCSR_S_LOCKUP_BITN 19
+#define CPU_SCS_DHCSR_S_LOCKUP_M 0x00080000
+#define CPU_SCS_DHCSR_S_LOCKUP_S 19
+
+// Field: [18] S_SLEEP
+//
+// Indicates that the core is sleeping (WFI, WFE, or **SLEEP-ON-EXIT**). Must
+// use C_HALT to gain control or wait for interrupt to wake-up.
+// When writing to this register, 1 must be written this bit-field, otherwise
+// the write operation is ignored and no bits are written into the register.
+#define CPU_SCS_DHCSR_S_SLEEP 0x00040000
+#define CPU_SCS_DHCSR_S_SLEEP_BITN 18
+#define CPU_SCS_DHCSR_S_SLEEP_M 0x00040000
+#define CPU_SCS_DHCSR_S_SLEEP_S 18
+
+// Field: [17] S_HALT
+//
+// The core is in debug state when this bit is set.
+// When writing to this register, 1 must be written this bit-field, otherwise
+// the write operation is ignored and no bits are written into the register.
+#define CPU_SCS_DHCSR_S_HALT 0x00020000
+#define CPU_SCS_DHCSR_S_HALT_BITN 17
+#define CPU_SCS_DHCSR_S_HALT_M 0x00020000
+#define CPU_SCS_DHCSR_S_HALT_S 17
+
+// Field: [16] S_REGRDY
+//
+// Register Read/Write on the Debug Core Register Selector register is
+// available. Last transfer is complete.
+// When writing to this register, 1 must be written this bit-field, otherwise
+// the write operation is ignored and no bits are written into the register.
+#define CPU_SCS_DHCSR_S_REGRDY 0x00010000
+#define CPU_SCS_DHCSR_S_REGRDY_BITN 16
+#define CPU_SCS_DHCSR_S_REGRDY_M 0x00010000
+#define CPU_SCS_DHCSR_S_REGRDY_S 16
+
+// Field: [5] C_SNAPSTALL
+//
+// If the core is stalled on a load/store operation the stall ceases and the
+// instruction is forced to complete. This enables Halting debug to gain
+// control of the core. It can only be set if: C_DEBUGEN = 1 and C_HALT = 1.
+// The core reads S_RETIRE_ST as 0. This indicates that no instruction has
+// advanced. This prevents misuse. The bus state is Unpredictable when this is
+// used. S_RETIRE_ST can detect core stalls on load/store operations.
+#define CPU_SCS_DHCSR_C_SNAPSTALL 0x00000020
+#define CPU_SCS_DHCSR_C_SNAPSTALL_BITN 5
+#define CPU_SCS_DHCSR_C_SNAPSTALL_M 0x00000020
+#define CPU_SCS_DHCSR_C_SNAPSTALL_S 5
+
+// Field: [3] C_MASKINTS
+//
+// Mask interrupts when stepping or running in halted debug. This masking does
+// not affect NMI, fault exceptions and SVC caused by execution of the
+// instructions. This bit must only be modified when the processor is halted
+// (S_HALT == 1). C_MASKINTS must be set or cleared before halt is released
+// (i.e., the writes to set or clear C_MASKINTS and to set or clear C_HALT must
+// be separate). Modifying C_MASKINTS while the system is running with halting
+// debug support enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable
+// behavior.
+#define CPU_SCS_DHCSR_C_MASKINTS 0x00000008
+#define CPU_SCS_DHCSR_C_MASKINTS_BITN 3
+#define CPU_SCS_DHCSR_C_MASKINTS_M 0x00000008
+#define CPU_SCS_DHCSR_C_MASKINTS_S 3
+
+// Field: [2] C_STEP
+//
+// Steps the core in halted debug. When C_DEBUGEN = 0, this bit has no effect.
+// Must only be modified when the processor is halted (S_HALT == 1).
+// Modifying C_STEP while the system is running with halting debug support
+// enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable behavior.
+#define CPU_SCS_DHCSR_C_STEP 0x00000004
+#define CPU_SCS_DHCSR_C_STEP_BITN 2
+#define CPU_SCS_DHCSR_C_STEP_M 0x00000004
+#define CPU_SCS_DHCSR_C_STEP_S 2
+
+// Field: [1] C_HALT
+//
+// Halts the core. This bit is set automatically when the core Halts. For
+// example Breakpoint. This bit clears on core reset.
+#define CPU_SCS_DHCSR_C_HALT 0x00000002
+#define CPU_SCS_DHCSR_C_HALT_BITN 1
+#define CPU_SCS_DHCSR_C_HALT_M 0x00000002
+#define CPU_SCS_DHCSR_C_HALT_S 1
+
+// Field: [0] C_DEBUGEN
+//
+// Enables debug. This can only be written by AHB-AP and not by the core. It is
+// ignored when written by the core, which cannot set or clear it. The core
+// must write a 1 to it when writing C_HALT to halt itself.
+// The values of C_HALT, C_STEP and C_MASKINTS are ignored by hardware when
+// C_DEBUGEN = 0. The read values for C_HALT, C_STEP and C_MASKINTS fields will
+// be unknown to software when C_DEBUGEN = 0.
+#define CPU_SCS_DHCSR_C_DEBUGEN 0x00000001
+#define CPU_SCS_DHCSR_C_DEBUGEN_BITN 0
+#define CPU_SCS_DHCSR_C_DEBUGEN_M 0x00000001
+#define CPU_SCS_DHCSR_C_DEBUGEN_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_DCRSR
+//
+//*****************************************************************************
+// Field: [16] REGWNR
+//
+// 1: Write
+// 0: Read
+#define CPU_SCS_DCRSR_REGWNR 0x00010000
+#define CPU_SCS_DCRSR_REGWNR_BITN 16
+#define CPU_SCS_DCRSR_REGWNR_M 0x00010000
+#define CPU_SCS_DCRSR_REGWNR_S 16
+
+// Field: [4:0] REGSEL
+//
+// Register select
+//
+// 0x00: R0
+// 0x01: R1
+// 0x02: R2
+// 0x03: R3
+// 0x04: R4
+// 0x05: R5
+// 0x06: R6
+// 0x07: R7
+// 0x08: R8
+// 0x09: R9
+// 0x0A: R10
+// 0x0B: R11
+// 0x0C: R12
+// 0x0D: Current SP
+// 0x0E: LR
+// 0x0F: DebugReturnAddress
+// 0x10: XPSR/flags, execution state information, and exception number
+// 0x11: MSP (Main SP)
+// 0x12: PSP (Process SP)
+// 0x14: CONTROL<<24 | FAULTMASK<<16 | BASEPRI<<8 | PRIMASK
+#define CPU_SCS_DCRSR_REGSEL_W 5
+#define CPU_SCS_DCRSR_REGSEL_M 0x0000001F
+#define CPU_SCS_DCRSR_REGSEL_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_DCRDR
+//
+//*****************************************************************************
+// Field: [31:0] DCRDR
+//
+// This register holds data for reading and writing registers to and from the
+// processor. This is the data value written to the register selected by DCRSR.
+// When the processor receives a request from DCRSR, this register is read or
+// written by the processor using a normal load-store unit operation. If core
+// register transfers are not being performed, software-based debug monitors
+// can use this register for communication in non-halting debug. This enables
+// flags and bits to acknowledge state and indicate if commands have been
+// accepted to, replied to, or accepted and replied to.
+#define CPU_SCS_DCRDR_DCRDR_W 32
+#define CPU_SCS_DCRDR_DCRDR_M 0xFFFFFFFF
+#define CPU_SCS_DCRDR_DCRDR_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_DEMCR
+//
+//*****************************************************************************
+// Field: [24] TRCENA
+//
+// This bit must be set to 1 to enable use of the trace and debug blocks: DWT,
+// ITM, ETM and TPIU. This enables control of power usage unless tracing is
+// required. The application can enable this, for ITM use, or use by a
+// debugger.
+#define CPU_SCS_DEMCR_TRCENA 0x01000000
+#define CPU_SCS_DEMCR_TRCENA_BITN 24
+#define CPU_SCS_DEMCR_TRCENA_M 0x01000000
+#define CPU_SCS_DEMCR_TRCENA_S 24
+
+// Field: [19] MON_REQ
+//
+// This enables the monitor to identify how it wakes up. This bit clears on a
+// Core Reset.
+//
+// 0x0: Woken up by debug exception.
+// 0x1: Woken up by MON_PEND
+#define CPU_SCS_DEMCR_MON_REQ 0x00080000
+#define CPU_SCS_DEMCR_MON_REQ_BITN 19
+#define CPU_SCS_DEMCR_MON_REQ_M 0x00080000
+#define CPU_SCS_DEMCR_MON_REQ_S 19
+
+// Field: [18] MON_STEP
+//
+// When MON_EN = 1, this steps the core. When MON_EN = 0, this bit is ignored.
+// This is the equivalent to DHCSR.C_STEP. Interrupts are only stepped
+// according to the priority of the monitor and settings of PRIMASK, FAULTMASK,
+// or BASEPRI.
+#define CPU_SCS_DEMCR_MON_STEP 0x00040000
+#define CPU_SCS_DEMCR_MON_STEP_BITN 18
+#define CPU_SCS_DEMCR_MON_STEP_M 0x00040000
+#define CPU_SCS_DEMCR_MON_STEP_S 18
+
+// Field: [17] MON_PEND
+//
+// Pend the monitor to activate when priority permits. This can wake up the
+// monitor through the AHB-AP port. It is the equivalent to DHCSR.C_HALT for
+// Monitor debug. This register does not reset on a system reset. It is only
+// reset by a power-on reset. Software in the reset handler or later, or by the
+// DAP must enable the debug monitor.
+#define CPU_SCS_DEMCR_MON_PEND 0x00020000
+#define CPU_SCS_DEMCR_MON_PEND_BITN 17
+#define CPU_SCS_DEMCR_MON_PEND_M 0x00020000
+#define CPU_SCS_DEMCR_MON_PEND_S 17
+
+// Field: [16] MON_EN
+//
+// Enable the debug monitor.
+// When enabled, the System handler priority register controls its priority
+// level. If disabled, then all debug events go to Hard fault. DHCSR.C_DEBUGEN
+// overrides this bit. Vector catching is semi-synchronous. When a matching
+// event is seen, a Halt is requested. Because the processor can only halt on
+// an instruction boundary, it must wait until the next instruction boundary.
+// As a result, it stops on the first instruction of the exception handler.
+// However, two special cases exist when a vector catch has triggered: 1. If a
+// fault is taken during vectoring, vector read or stack push error, the halt
+// occurs on the corresponding fault handler, for the vector error or stack
+// push. 2. If a late arriving interrupt comes in during vectoring, it is not
+// taken. That is, an implementation that supports the late arrival
+// optimization must suppress it in this case.
+#define CPU_SCS_DEMCR_MON_EN 0x00010000
+#define CPU_SCS_DEMCR_MON_EN_BITN 16
+#define CPU_SCS_DEMCR_MON_EN_M 0x00010000
+#define CPU_SCS_DEMCR_MON_EN_S 16
+
+// Field: [10] VC_HARDERR
+//
+// Debug trap on Hard Fault. Ignored when DHCSR.C_DEBUGEN is cleared.
+#define CPU_SCS_DEMCR_VC_HARDERR 0x00000400
+#define CPU_SCS_DEMCR_VC_HARDERR_BITN 10
+#define CPU_SCS_DEMCR_VC_HARDERR_M 0x00000400
+#define CPU_SCS_DEMCR_VC_HARDERR_S 10
+
+// Field: [9] VC_INTERR
+//
+// Debug trap on a fault occurring during an exception entry or return
+// sequence. Ignored when DHCSR.C_DEBUGEN is cleared.
+#define CPU_SCS_DEMCR_VC_INTERR 0x00000200
+#define CPU_SCS_DEMCR_VC_INTERR_BITN 9
+#define CPU_SCS_DEMCR_VC_INTERR_M 0x00000200
+#define CPU_SCS_DEMCR_VC_INTERR_S 9
+
+// Field: [8] VC_BUSERR
+//
+// Debug Trap on normal Bus error. Ignored when DHCSR.C_DEBUGEN is cleared.
+#define CPU_SCS_DEMCR_VC_BUSERR 0x00000100
+#define CPU_SCS_DEMCR_VC_BUSERR_BITN 8
+#define CPU_SCS_DEMCR_VC_BUSERR_M 0x00000100
+#define CPU_SCS_DEMCR_VC_BUSERR_S 8
+
+// Field: [7] VC_STATERR
+//
+// Debug trap on Usage Fault state errors. Ignored when DHCSR.C_DEBUGEN is
+// cleared.
+#define CPU_SCS_DEMCR_VC_STATERR 0x00000080
+#define CPU_SCS_DEMCR_VC_STATERR_BITN 7
+#define CPU_SCS_DEMCR_VC_STATERR_M 0x00000080
+#define CPU_SCS_DEMCR_VC_STATERR_S 7
+
+// Field: [6] VC_CHKERR
+//
+// Debug trap on Usage Fault enabled checking errors. Ignored when
+// DHCSR.C_DEBUGEN is cleared.
+#define CPU_SCS_DEMCR_VC_CHKERR 0x00000040
+#define CPU_SCS_DEMCR_VC_CHKERR_BITN 6
+#define CPU_SCS_DEMCR_VC_CHKERR_M 0x00000040
+#define CPU_SCS_DEMCR_VC_CHKERR_S 6
+
+// Field: [5] VC_NOCPERR
+//
+// Debug trap on a UsageFault access to a Coprocessor. Ignored when
+// DHCSR.C_DEBUGEN is cleared.
+#define CPU_SCS_DEMCR_VC_NOCPERR 0x00000020
+#define CPU_SCS_DEMCR_VC_NOCPERR_BITN 5
+#define CPU_SCS_DEMCR_VC_NOCPERR_M 0x00000020
+#define CPU_SCS_DEMCR_VC_NOCPERR_S 5
+
+// Field: [4] VC_MMERR
+//
+// Debug trap on Memory Management faults. Ignored when DHCSR.C_DEBUGEN is
+// cleared.
+#define CPU_SCS_DEMCR_VC_MMERR 0x00000010
+#define CPU_SCS_DEMCR_VC_MMERR_BITN 4
+#define CPU_SCS_DEMCR_VC_MMERR_M 0x00000010
+#define CPU_SCS_DEMCR_VC_MMERR_S 4
+
+// Field: [0] VC_CORERESET
+//
+// Reset Vector Catch. Halt running system if Core reset occurs. Ignored when
+// DHCSR.C_DEBUGEN is cleared.
+#define CPU_SCS_DEMCR_VC_CORERESET 0x00000001
+#define CPU_SCS_DEMCR_VC_CORERESET_BITN 0
+#define CPU_SCS_DEMCR_VC_CORERESET_M 0x00000001
+#define CPU_SCS_DEMCR_VC_CORERESET_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_STIR
+//
+//*****************************************************************************
+// Field: [8:0] INTID
+//
+// Interrupt ID field. Writing a value to this bit-field is the same as
+// manually pending an interrupt by setting the corresponding interrupt bit in
+// an Interrupt Set Pending Register in NVIC_ISPR0 or NVIC_ISPR1.
+#define CPU_SCS_STIR_INTID_W 9
+#define CPU_SCS_STIR_INTID_M 0x000001FF
+#define CPU_SCS_STIR_INTID_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_FPCCR
+//
+//*****************************************************************************
+// Field: [31] ASPEN
+//
+// Automatic State Preservation enable.
+// When this bit is set is will cause bit [2] of the Special CONTROL register
+// to be set (FPCA) on execution of a floating point instruction which results
+// in the floating point state automatically being preserved on exception
+// entry.
+#define CPU_SCS_FPCCR_ASPEN 0x80000000
+#define CPU_SCS_FPCCR_ASPEN_BITN 31
+#define CPU_SCS_FPCCR_ASPEN_M 0x80000000
+#define CPU_SCS_FPCCR_ASPEN_S 31
+
+// Field: [30] LSPEN
+//
+// Lazy State Preservation enable.
+// Lazy state preservation is when the processor performs a context save, space
+// on the stack is reserved for the floating point state but it is not stacked
+// until the new context performs a floating point operation.
+// 0: Disable automatic lazy state preservation for floating-point context.
+// 1: Enable automatic lazy state preservation for floating-point context.
+#define CPU_SCS_FPCCR_LSPEN 0x40000000
+#define CPU_SCS_FPCCR_LSPEN_BITN 30
+#define CPU_SCS_FPCCR_LSPEN_M 0x40000000
+#define CPU_SCS_FPCCR_LSPEN_S 30
+
+// Field: [8] MONRDY
+//
+// Indicates whether the the software executing when the processor allocated
+// the FP stack frame was able to set the DebugMonitor exception to pending.
+// 0: DebugMonitor is disabled or priority did not permit setting
+// DEMCR.MON_PEND when the floating-point stack frame was allocated.
+// 1: DebugMonitor is enabled and priority permits setting DEMCR.MON_PEND when
+// the floating-point stack frame was allocated.
+#define CPU_SCS_FPCCR_MONRDY 0x00000100
+#define CPU_SCS_FPCCR_MONRDY_BITN 8
+#define CPU_SCS_FPCCR_MONRDY_M 0x00000100
+#define CPU_SCS_FPCCR_MONRDY_S 8
+
+// Field: [6] BFRDY
+//
+// Indicates whether the software executing when the processor allocated the FP
+// stack frame was able to set the BusFault exception to pending.
+// 0: BusFault is disabled or priority did not permit setting the BusFault
+// handler to the pending state when the floating-point stack frame was
+// allocated.
+// 1: BusFault is enabled and priority permitted setting the BusFault handler
+// to the pending state when the floating-point stack frame was allocated.
+#define CPU_SCS_FPCCR_BFRDY 0x00000040
+#define CPU_SCS_FPCCR_BFRDY_BITN 6
+#define CPU_SCS_FPCCR_BFRDY_M 0x00000040
+#define CPU_SCS_FPCCR_BFRDY_S 6
+
+// Field: [5] MMRDY
+//
+// Indicates whether the software executing when the processor allocated the FP
+// stack frame was able to set the MemManage exception to pending.
+// 0: MemManage is disabled or priority did not permit setting the MemManage
+// handler to the pending state when the floating-point stack frame was
+// allocated.
+// 1: MemManage is enabled and priority permitted setting the MemManage handler
+// to the pending state when the floating-point stack frame was allocated.
+#define CPU_SCS_FPCCR_MMRDY 0x00000020
+#define CPU_SCS_FPCCR_MMRDY_BITN 5
+#define CPU_SCS_FPCCR_MMRDY_M 0x00000020
+#define CPU_SCS_FPCCR_MMRDY_S 5
+
+// Field: [4] HFRDY
+//
+// Indicates whether the software executing when the processor allocated the FP
+// stack frame was able to set the HardFault exception to pending.
+// 0: Priority did not permit setting the HardFault handler to the pending
+// state when the floating-point stack frame was allocated.
+// 1: Priority permitted setting the HardFault handler to the pending state
+// when the floating-point stack frame was allocated.
+#define CPU_SCS_FPCCR_HFRDY 0x00000010
+#define CPU_SCS_FPCCR_HFRDY_BITN 4
+#define CPU_SCS_FPCCR_HFRDY_M 0x00000010
+#define CPU_SCS_FPCCR_HFRDY_S 4
+
+// Field: [3] THREAD
+//
+// Indicates the processor mode was Thread when it allocated the FP stack
+// frame.
+// 0: Mode was not Thread Mode when the floating-point stack frame was
+// allocated.
+// 1: Mode was Thread Mode when the floating-point stack frame was allocated.
+#define CPU_SCS_FPCCR_THREAD 0x00000008
+#define CPU_SCS_FPCCR_THREAD_BITN 3
+#define CPU_SCS_FPCCR_THREAD_M 0x00000008
+#define CPU_SCS_FPCCR_THREAD_S 3
+
+// Field: [1] USER
+//
+// Indicates the privilege level of the software executing was User
+// (Unpriviledged) when the processor allocated the FP stack frame:
+// 0: Privilege level was not user when the floating-point stack frame was
+// allocated.
+// 1: Privilege level was user when the floating-point stack frame was
+// allocated.
+#define CPU_SCS_FPCCR_USER 0x00000002
+#define CPU_SCS_FPCCR_USER_BITN 1
+#define CPU_SCS_FPCCR_USER_M 0x00000002
+#define CPU_SCS_FPCCR_USER_S 1
+
+// Field: [0] LSPACT
+//
+// Indicates whether Lazy preservation of the FP state is active:
+// 0: Lazy state preservation is not active.
+// 1: Lazy state preservation is active. floating-point stack frame has been
+// allocated but saving state to it has been deferred.
+#define CPU_SCS_FPCCR_LSPACT 0x00000001
+#define CPU_SCS_FPCCR_LSPACT_BITN 0
+#define CPU_SCS_FPCCR_LSPACT_M 0x00000001
+#define CPU_SCS_FPCCR_LSPACT_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_FPCAR
+//
+//*****************************************************************************
+// Field: [31:2] ADDRESS
+//
+// Holds the (double-word-aligned) location of the unpopulated floating-point
+// register space allocated on an exception stack frame.
+#define CPU_SCS_FPCAR_ADDRESS_W 30
+#define CPU_SCS_FPCAR_ADDRESS_M 0xFFFFFFFC
+#define CPU_SCS_FPCAR_ADDRESS_S 2
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_FPDSCR
+//
+//*****************************************************************************
+// Field: [26] AHP
+//
+// Default value for Alternative Half Precision bit. (If this bit is set to 1
+// then Alternative half-precision format is selected).
+#define CPU_SCS_FPDSCR_AHP 0x04000000
+#define CPU_SCS_FPDSCR_AHP_BITN 26
+#define CPU_SCS_FPDSCR_AHP_M 0x04000000
+#define CPU_SCS_FPDSCR_AHP_S 26
+
+// Field: [25] DN
+//
+// Default value for Default NaN mode bit. (If this bit is set to 1 then any
+// operation involving one or more NaNs returns the Default NaN).
+#define CPU_SCS_FPDSCR_DN 0x02000000
+#define CPU_SCS_FPDSCR_DN_BITN 25
+#define CPU_SCS_FPDSCR_DN_M 0x02000000
+#define CPU_SCS_FPDSCR_DN_S 25
+
+// Field: [24] FZ
+//
+// Default value for Flush-to-Zero mode bit. (If this bit is set to 1 then
+// Flush-to-zero mode is enabled).
+#define CPU_SCS_FPDSCR_FZ 0x01000000
+#define CPU_SCS_FPDSCR_FZ_BITN 24
+#define CPU_SCS_FPDSCR_FZ_M 0x01000000
+#define CPU_SCS_FPDSCR_FZ_S 24
+
+// Field: [23:22] RMODE
+//
+// Default value for Rounding Mode control field. (The encoding for this field
+// is:
+// 0b00 Round to Nearest (RN) mode
+// 0b01 Round towards Plus Infinity (RP) mode
+// 0b10 Round towards Minus Infinity (RM) mode
+// 0b11 Round towards Zero (RZ) mode.
+// The specified rounding mode is used by almost all floating-point
+// instructions).
+#define CPU_SCS_FPDSCR_RMODE_W 2
+#define CPU_SCS_FPDSCR_RMODE_M 0x00C00000
+#define CPU_SCS_FPDSCR_RMODE_S 22
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_MVFR0
+//
+//*****************************************************************************
+// Field: [31:28] FP_ROUNDING_MODES
+//
+// Indicates the rounding modes supported by the FP floating-point hardware.
+// The value of this field is: 0b0001 - all rounding modes supported.
+#define CPU_SCS_MVFR0_FP_ROUNDING_MODES_W 4
+#define CPU_SCS_MVFR0_FP_ROUNDING_MODES_M 0xF0000000
+#define CPU_SCS_MVFR0_FP_ROUNDING_MODES_S 28
+
+// Field: [27:24] SHORT_VECTORS
+//
+// Indicates the hardware support for FP short vectors. The value of this field
+// is: 0b0000 - not supported.
+#define CPU_SCS_MVFR0_SHORT_VECTORS_W 4
+#define CPU_SCS_MVFR0_SHORT_VECTORS_M 0x0F000000
+#define CPU_SCS_MVFR0_SHORT_VECTORS_S 24
+
+// Field: [23:20] SQUARE_ROOT
+//
+// Indicates the hardware support for FP square root operations. The value of
+// this field is: 0b0001 - supported.
+#define CPU_SCS_MVFR0_SQUARE_ROOT_W 4
+#define CPU_SCS_MVFR0_SQUARE_ROOT_M 0x00F00000
+#define CPU_SCS_MVFR0_SQUARE_ROOT_S 20
+
+// Field: [19:16] DIVIDE
+//
+// Indicates the hardware support for FP divide operations. The value of this
+// field is: 0b0001 - supported.
+#define CPU_SCS_MVFR0_DIVIDE_W 4
+#define CPU_SCS_MVFR0_DIVIDE_M 0x000F0000
+#define CPU_SCS_MVFR0_DIVIDE_S 16
+
+// Field: [15:12] FP_EXCEPTION_TRAPPING
+//
+// Indicates whether the FP hardware implementation supports exception
+// trapping. The value of this field is: 0b0000 - not supported.
+#define CPU_SCS_MVFR0_FP_EXCEPTION_TRAPPING_W 4
+#define CPU_SCS_MVFR0_FP_EXCEPTION_TRAPPING_M 0x0000F000
+#define CPU_SCS_MVFR0_FP_EXCEPTION_TRAPPING_S 12
+
+// Field: [11:8] DOUBLE_PRECISION
+//
+// Indicates the hardware support for FP double-precision operations. The value
+// of this field is: 0b0000 - not supported.
+#define CPU_SCS_MVFR0_DOUBLE_PRECISION_W 4
+#define CPU_SCS_MVFR0_DOUBLE_PRECISION_M 0x00000F00
+#define CPU_SCS_MVFR0_DOUBLE_PRECISION_S 8
+
+// Field: [7:4] SINGLE_PRECISION
+//
+// Indicates the hardware support for FP single-precision operations. The value
+// of this field is: 0b0010 - supported.
+#define CPU_SCS_MVFR0_SINGLE_PRECISION_W 4
+#define CPU_SCS_MVFR0_SINGLE_PRECISION_M 0x000000F0
+#define CPU_SCS_MVFR0_SINGLE_PRECISION_S 4
+
+// Field: [3:0] A_SIMD
+//
+// Indicates the size of the FP register bank. The value of this field is:
+// 0b0001 - supported, 16 x 64-bit registers.
+#define CPU_SCS_MVFR0_A_SIMD_W 4
+#define CPU_SCS_MVFR0_A_SIMD_M 0x0000000F
+#define CPU_SCS_MVFR0_A_SIMD_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_SCS_O_MVFR1
+//
+//*****************************************************************************
+// Field: [31:28] FP_FUSED_MAC
+//
+// Indicates whether the FP supports fused multiply accumulate operations. The
+// value of this field is: 0b0001 - supported.
+#define CPU_SCS_MVFR1_FP_FUSED_MAC_W 4
+#define CPU_SCS_MVFR1_FP_FUSED_MAC_M 0xF0000000
+#define CPU_SCS_MVFR1_FP_FUSED_MAC_S 28
+
+// Field: [27:24] FP_HPFP
+//
+// Indicates whether the FP supports half-precision floating-point conversion
+// operations. The value of this field is: 0b0001 - supported.
+#define CPU_SCS_MVFR1_FP_HPFP_W 4
+#define CPU_SCS_MVFR1_FP_HPFP_M 0x0F000000
+#define CPU_SCS_MVFR1_FP_HPFP_S 24
+
+// Field: [7:4] D_NAN_MODE
+//
+// Indicates whether the FP hardware implementation supports only the Default
+// NaN mode. The value of this field is: 0b0001 - hardware supports propagation
+// of NaN values.
+#define CPU_SCS_MVFR1_D_NAN_MODE_W 4
+#define CPU_SCS_MVFR1_D_NAN_MODE_M 0x000000F0
+#define CPU_SCS_MVFR1_D_NAN_MODE_S 4
+
+// Field: [3:0] FTZ_MODE
+//
+// Indicates whether the FP hardware implementation supports only the
+// Flush-to-Zero mode of operation. The value of this field is: 0b0001 -
+// hardware supports full denormalized number arithmetic.
+#define CPU_SCS_MVFR1_FTZ_MODE_W 4
+#define CPU_SCS_MVFR1_FTZ_MODE_M 0x0000000F
+#define CPU_SCS_MVFR1_FTZ_MODE_S 0
+
+
+#endif // __CPU_SCS__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_tiprop.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_tiprop.h
new file mode 100644
index 0000000..29e314e
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_tiprop.h
@@ -0,0 +1,68 @@
+/******************************************************************************
+* Filename: hw_cpu_tiprop_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_CPU_TIPROP_H__
+#define __HW_CPU_TIPROP_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// CPU_TIPROP component
+//
+//*****************************************************************************
+// Internal
+#define CPU_TIPROP_O_TRACECLKMUX 0x00000FF8
+
+//*****************************************************************************
+//
+// Register: CPU_TIPROP_O_TRACECLKMUX
+//
+//*****************************************************************************
+// Field: [0] TRACECLK_N_SWV
+//
+// Internal. Only to be used through TI provided API.
+// ENUMs:
+// TRACECLK Internal. Only to be used through TI provided API.
+// SWV Internal. Only to be used through TI provided API.
+#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV 0x00000001
+#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_BITN 0
+#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_M 0x00000001
+#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_S 0
+#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_TRACECLK 0x00000001
+#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_SWV 0x00000000
+
+
+#endif // __CPU_TIPROP__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_tpiu.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_tpiu.h
new file mode 100644
index 0000000..43c7c8e
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_tpiu.h
@@ -0,0 +1,347 @@
+/******************************************************************************
+* Filename: hw_cpu_tpiu_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_CPU_TPIU_H__
+#define __HW_CPU_TPIU_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// CPU_TPIU component
+//
+//*****************************************************************************
+// Supported Sync Port Sizes
+#define CPU_TPIU_O_SSPSR 0x00000000
+
+// Current Sync Port Size
+#define CPU_TPIU_O_CSPSR 0x00000004
+
+// Async Clock Prescaler
+#define CPU_TPIU_O_ACPR 0x00000010
+
+// Selected Pin Protocol
+#define CPU_TPIU_O_SPPR 0x000000F0
+
+// Formatter and Flush Status
+#define CPU_TPIU_O_FFSR 0x00000300
+
+// Formatter and Flush Control
+#define CPU_TPIU_O_FFCR 0x00000304
+
+// Formatter Synchronization Counter
+#define CPU_TPIU_O_FSCR 0x00000308
+
+// Claim Tag Mask
+#define CPU_TPIU_O_CLAIMMASK 0x00000FA0
+
+// Claim Tag Set
+#define CPU_TPIU_O_CLAIMSET 0x00000FA0
+
+// Current Claim Tag
+#define CPU_TPIU_O_CLAIMTAG 0x00000FA4
+
+// Claim Tag Clear
+#define CPU_TPIU_O_CLAIMCLR 0x00000FA4
+
+// Device ID
+#define CPU_TPIU_O_DEVID 0x00000FC8
+
+//*****************************************************************************
+//
+// Register: CPU_TPIU_O_SSPSR
+//
+//*****************************************************************************
+// Field: [3] FOUR
+//
+// 4-bit port size support
+//
+// 0x0: Not supported
+// 0x1: Supported
+#define CPU_TPIU_SSPSR_FOUR 0x00000008
+#define CPU_TPIU_SSPSR_FOUR_BITN 3
+#define CPU_TPIU_SSPSR_FOUR_M 0x00000008
+#define CPU_TPIU_SSPSR_FOUR_S 3
+
+// Field: [2] THREE
+//
+// 3-bit port size support
+//
+// 0x0: Not supported
+// 0x1: Supported
+#define CPU_TPIU_SSPSR_THREE 0x00000004
+#define CPU_TPIU_SSPSR_THREE_BITN 2
+#define CPU_TPIU_SSPSR_THREE_M 0x00000004
+#define CPU_TPIU_SSPSR_THREE_S 2
+
+// Field: [1] TWO
+//
+// 2-bit port size support
+//
+// 0x0: Not supported
+// 0x1: Supported
+#define CPU_TPIU_SSPSR_TWO 0x00000002
+#define CPU_TPIU_SSPSR_TWO_BITN 1
+#define CPU_TPIU_SSPSR_TWO_M 0x00000002
+#define CPU_TPIU_SSPSR_TWO_S 1
+
+// Field: [0] ONE
+//
+// 1-bit port size support
+//
+// 0x0: Not supported
+// 0x1: Supported
+#define CPU_TPIU_SSPSR_ONE 0x00000001
+#define CPU_TPIU_SSPSR_ONE_BITN 0
+#define CPU_TPIU_SSPSR_ONE_M 0x00000001
+#define CPU_TPIU_SSPSR_ONE_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_TPIU_O_CSPSR
+//
+//*****************************************************************************
+// Field: [3] FOUR
+//
+// 4-bit port enable
+// Writing values with more than one bit set in CSPSR, or setting a bit that is
+// not indicated as supported in SSPSR can cause Unpredictable behavior.
+#define CPU_TPIU_CSPSR_FOUR 0x00000008
+#define CPU_TPIU_CSPSR_FOUR_BITN 3
+#define CPU_TPIU_CSPSR_FOUR_M 0x00000008
+#define CPU_TPIU_CSPSR_FOUR_S 3
+
+// Field: [2] THREE
+//
+// 3-bit port enable
+// Writing values with more than one bit set in CSPSR, or setting a bit that is
+// not indicated as supported in SSPSR can cause Unpredictable behavior.
+#define CPU_TPIU_CSPSR_THREE 0x00000004
+#define CPU_TPIU_CSPSR_THREE_BITN 2
+#define CPU_TPIU_CSPSR_THREE_M 0x00000004
+#define CPU_TPIU_CSPSR_THREE_S 2
+
+// Field: [1] TWO
+//
+// 2-bit port enable
+// Writing values with more than one bit set in CSPSR, or setting a bit that is
+// not indicated as supported in SSPSR can cause Unpredictable behavior.
+#define CPU_TPIU_CSPSR_TWO 0x00000002
+#define CPU_TPIU_CSPSR_TWO_BITN 1
+#define CPU_TPIU_CSPSR_TWO_M 0x00000002
+#define CPU_TPIU_CSPSR_TWO_S 1
+
+// Field: [0] ONE
+//
+// 1-bit port enable
+// Writing values with more than one bit set in CSPSR, or setting a bit that is
+// not indicated as supported in SSPSR can cause Unpredictable behavior.
+#define CPU_TPIU_CSPSR_ONE 0x00000001
+#define CPU_TPIU_CSPSR_ONE_BITN 0
+#define CPU_TPIU_CSPSR_ONE_M 0x00000001
+#define CPU_TPIU_CSPSR_ONE_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_TPIU_O_ACPR
+//
+//*****************************************************************************
+// Field: [12:0] PRESCALER
+//
+// Divisor for input trace clock is (PRESCALER + 1).
+#define CPU_TPIU_ACPR_PRESCALER_W 13
+#define CPU_TPIU_ACPR_PRESCALER_M 0x00001FFF
+#define CPU_TPIU_ACPR_PRESCALER_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_TPIU_O_SPPR
+//
+//*****************************************************************************
+// Field: [1:0] PROTOCOL
+//
+// Trace output protocol
+// ENUMs:
+// SWO_NRZ SerialWire Output (NRZ)
+// SWO_MANCHESTER SerialWire Output (Manchester). This is the reset
+// value.
+// TRACEPORT TracePort mode
+#define CPU_TPIU_SPPR_PROTOCOL_W 2
+#define CPU_TPIU_SPPR_PROTOCOL_M 0x00000003
+#define CPU_TPIU_SPPR_PROTOCOL_S 0
+#define CPU_TPIU_SPPR_PROTOCOL_SWO_NRZ 0x00000002
+#define CPU_TPIU_SPPR_PROTOCOL_SWO_MANCHESTER 0x00000001
+#define CPU_TPIU_SPPR_PROTOCOL_TRACEPORT 0x00000000
+
+//*****************************************************************************
+//
+// Register: CPU_TPIU_O_FFSR
+//
+//*****************************************************************************
+// Field: [3] FTNONSTOP
+//
+// 0: Formatter can be stopped
+// 1: Formatter cannot be stopped
+#define CPU_TPIU_FFSR_FTNONSTOP 0x00000008
+#define CPU_TPIU_FFSR_FTNONSTOP_BITN 3
+#define CPU_TPIU_FFSR_FTNONSTOP_M 0x00000008
+#define CPU_TPIU_FFSR_FTNONSTOP_S 3
+
+//*****************************************************************************
+//
+// Register: CPU_TPIU_O_FFCR
+//
+//*****************************************************************************
+// Field: [8] TRIGIN
+//
+// Indicates that triggers are inserted when a trigger pin is asserted.
+#define CPU_TPIU_FFCR_TRIGIN 0x00000100
+#define CPU_TPIU_FFCR_TRIGIN_BITN 8
+#define CPU_TPIU_FFCR_TRIGIN_M 0x00000100
+#define CPU_TPIU_FFCR_TRIGIN_S 8
+
+// Field: [1] ENFCONT
+//
+// Enable continuous formatting:
+//
+// 0: Continuous formatting disabled
+// 1: Continuous formatting enabled
+#define CPU_TPIU_FFCR_ENFCONT 0x00000002
+#define CPU_TPIU_FFCR_ENFCONT_BITN 1
+#define CPU_TPIU_FFCR_ENFCONT_M 0x00000002
+#define CPU_TPIU_FFCR_ENFCONT_S 1
+
+//*****************************************************************************
+//
+// Register: CPU_TPIU_O_FSCR
+//
+//*****************************************************************************
+// Field: [31:0] FSCR
+//
+// The global synchronization trigger is generated by the Program Counter (PC)
+// Sampler block. This means that there is no synchronization counter in the
+// TPIU.
+#define CPU_TPIU_FSCR_FSCR_W 32
+#define CPU_TPIU_FSCR_FSCR_M 0xFFFFFFFF
+#define CPU_TPIU_FSCR_FSCR_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_TPIU_O_CLAIMMASK
+//
+//*****************************************************************************
+// Field: [31:0] CLAIMMASK
+//
+// This register forms one half of the Claim Tag value. When reading this
+// register returns the number of bits that can be set (each bit is considered
+// separately):
+//
+// 0: This claim tag bit is not implemented
+// 1: This claim tag bit is not implemented
+//
+// The behavior when writing to this register is described in CLAIMSET.
+#define CPU_TPIU_CLAIMMASK_CLAIMMASK_W 32
+#define CPU_TPIU_CLAIMMASK_CLAIMMASK_M 0xFFFFFFFF
+#define CPU_TPIU_CLAIMMASK_CLAIMMASK_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_TPIU_O_CLAIMSET
+//
+//*****************************************************************************
+// Field: [31:0] CLAIMSET
+//
+// This register forms one half of the Claim Tag value. Writing to this
+// location allows individual bits to be set (each bit is considered
+// separately):
+//
+// 0: No effect
+// 1: Set this bit in the claim tag
+//
+// The behavior when reading from this location is described in CLAIMMASK.
+#define CPU_TPIU_CLAIMSET_CLAIMSET_W 32
+#define CPU_TPIU_CLAIMSET_CLAIMSET_M 0xFFFFFFFF
+#define CPU_TPIU_CLAIMSET_CLAIMSET_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_TPIU_O_CLAIMTAG
+//
+//*****************************************************************************
+// Field: [31:0] CLAIMTAG
+//
+// This register forms one half of the Claim Tag value. Reading this register
+// returns the current Claim Tag value.
+// Reading CLAIMMASK determines how many bits from this register must be used.
+//
+// The behavior when writing to this register is described in CLAIMCLR.
+#define CPU_TPIU_CLAIMTAG_CLAIMTAG_W 32
+#define CPU_TPIU_CLAIMTAG_CLAIMTAG_M 0xFFFFFFFF
+#define CPU_TPIU_CLAIMTAG_CLAIMTAG_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_TPIU_O_CLAIMCLR
+//
+//*****************************************************************************
+// Field: [31:0] CLAIMCLR
+//
+// This register forms one half of the Claim Tag value. Writing to this
+// location enables individual bits to be cleared (each bit is considered
+// separately):
+//
+// 0: No effect
+// 1: Clear this bit in the claim tag.
+//
+// The behavior when reading from this location is described in CLAIMTAG.
+#define CPU_TPIU_CLAIMCLR_CLAIMCLR_W 32
+#define CPU_TPIU_CLAIMCLR_CLAIMCLR_M 0xFFFFFFFF
+#define CPU_TPIU_CLAIMCLR_CLAIMCLR_S 0
+
+//*****************************************************************************
+//
+// Register: CPU_TPIU_O_DEVID
+//
+//*****************************************************************************
+// Field: [31:0] DEVID
+//
+// This field returns: 0xCA1 if there is an ETM present. 0xCA0 if there is no
+// ETM present.
+#define CPU_TPIU_DEVID_DEVID_W 32
+#define CPU_TPIU_DEVID_DEVID_M 0xFFFFFFFF
+#define CPU_TPIU_DEVID_DEVID_S 0
+
+
+#endif // __CPU_TPIU__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_crypto.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_crypto.h
new file mode 100644
index 0000000..2952afd
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_crypto.h
@@ -0,0 +1,3966 @@
+/******************************************************************************
+* Filename: hw_crypto_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_CRYPTO_H__
+#define __HW_CRYPTO_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// CRYPTO component
+//
+//*****************************************************************************
+// Channel 0 Control
+#define CRYPTO_O_DMACH0CTL 0x00000000
+
+// Channel 0 External Address
+#define CRYPTO_O_DMACH0EXTADDR 0x00000004
+
+// Channel 0 DMA Length
+#define CRYPTO_O_DMACH0LEN 0x0000000C
+
+// DMAC Status
+#define CRYPTO_O_DMASTAT 0x00000018
+
+// DMAC Software Reset
+#define CRYPTO_O_DMASWRESET 0x0000001C
+
+// Channel 1 Control
+#define CRYPTO_O_DMACH1CTL 0x00000020
+
+// Channel 1 External Address
+#define CRYPTO_O_DMACH1EXTADDR 0x00000024
+
+// Channel 1 DMA Length
+#define CRYPTO_O_DMACH1LEN 0x0000002C
+
+// DMAC Master Run-time Parameters
+#define CRYPTO_O_DMABUSCFG 0x00000078
+
+// DMAC Port Error Raw Status
+#define CRYPTO_O_DMAPORTERR 0x0000007C
+
+// DMAC Version
+#define CRYPTO_O_DMAHWVER 0x000000FC
+
+// Key Store Write Area
+#define CRYPTO_O_KEYWRITEAREA 0x00000400
+
+// Key Store Written Area
+#define CRYPTO_O_KEYWRITTENAREA 0x00000404
+
+// Key Store Size
+#define CRYPTO_O_KEYSIZE 0x00000408
+
+// Key Store Read Area
+#define CRYPTO_O_KEYREADAREA 0x0000040C
+
+// AES_KEY2_0 / AES_GHASH_H_IN_0
+#define CRYPTO_O_AESKEY20 0x00000500
+
+// AES_KEY2_0 / AES_GHASH_H_IN_0
+#define CRYPTO_O_AESKEY21 0x00000504
+
+// AES_KEY2_0 / AES_GHASH_H_IN_0
+#define CRYPTO_O_AESKEY22 0x00000508
+
+// AES_KEY2_0 / AES_GHASH_H_IN_0
+#define CRYPTO_O_AESKEY23 0x0000050C
+
+// AES_KEY3_0 / AES_KEY2_4
+#define CRYPTO_O_AESKEY30 0x00000510
+
+// AES_KEY3_0 / AES_KEY2_4
+#define CRYPTO_O_AESKEY31 0x00000514
+
+// AES_KEY3_0 / AES_KEY2_4
+#define CRYPTO_O_AESKEY32 0x00000518
+
+// AES_KEY3_0 / AES_KEY2_4
+#define CRYPTO_O_AESKEY33 0x0000051C
+
+// AES initialization vector registers
+#define CRYPTO_O_AESIV0 0x00000540
+
+// AES initialization vector registers
+#define CRYPTO_O_AESIV1 0x00000544
+
+// AES initialization vector registers
+#define CRYPTO_O_AESIV2 0x00000548
+
+// AES initialization vector registers
+#define CRYPTO_O_AESIV3 0x0000054C
+
+// AES Control
+#define CRYPTO_O_AESCTL 0x00000550
+
+// AES Crypto Length 0 (LSW)
+#define CRYPTO_O_AESDATALEN0 0x00000554
+
+// AES Crypto Length 1 (MSW)
+#define CRYPTO_O_AESDATALEN1 0x00000558
+
+// AES Authentication Length
+#define CRYPTO_O_AESAUTHLEN 0x0000055C
+
+// Data Input/Output
+#define CRYPTO_O_AESDATAOUT0 0x00000560
+
+// AES Data Input_Output 0
+#define CRYPTO_O_AESDATAIN0 0x00000560
+
+// Data Input/Output
+#define CRYPTO_O_AESDATAOUT1 0x00000564
+
+// AES Data Input_Output 0
+#define CRYPTO_O_AESDATAIN1 0x00000564
+
+// Data Input/Output
+#define CRYPTO_O_AESDATAOUT2 0x00000568
+
+// AES Data Input_Output 2
+#define CRYPTO_O_AESDATAIN2 0x00000568
+
+// Data Input/Output
+#define CRYPTO_O_AESDATAOUT3 0x0000056C
+
+// AES Data Input_Output 3
+#define CRYPTO_O_AESDATAIN3 0x0000056C
+
+// AES Tag Out 0
+#define CRYPTO_O_AESTAGOUT0 0x00000570
+
+// AES Tag Out 0
+#define CRYPTO_O_AESTAGOUT1 0x00000574
+
+// AES Tag Out 0
+#define CRYPTO_O_AESTAGOUT2 0x00000578
+
+// AES Tag Out 0
+#define CRYPTO_O_AESTAGOUT3 0x0000057C
+
+// HASH Data Input 1
+#define CRYPTO_O_HASHDATAIN1 0x00000604
+
+// HASH Data Input 2
+#define CRYPTO_O_HASHDATAIN2 0x00000608
+
+// HASH Data Input 3
+#define CRYPTO_O_HASHDATAIN3 0x0000060C
+
+// HASH Data Input 4
+#define CRYPTO_O_HASHDATAIN4 0x00000610
+
+// HASH Data Input 5
+#define CRYPTO_O_HASHDATAIN5 0x00000614
+
+// HASH Data Input 6
+#define CRYPTO_O_HASHDATAIN6 0x00000618
+
+// HASH Data Input 7
+#define CRYPTO_O_HASHDATAIN7 0x0000061C
+
+// HASH Data Input 8
+#define CRYPTO_O_HASHDATAIN8 0x00000620
+
+// HASH Data Input 9
+#define CRYPTO_O_HASHDATAIN9 0x00000624
+
+// HASH Data Input 10
+#define CRYPTO_O_HASHDATAIN10 0x00000628
+
+// HASH Data Input 11
+#define CRYPTO_O_HASHDATAIN11 0x0000062C
+
+// HASH Data Input 12
+#define CRYPTO_O_HASHDATAIN12 0x00000630
+
+// HASH Data Input 13
+#define CRYPTO_O_HASHDATAIN13 0x00000634
+
+// HASH Data Input 14
+#define CRYPTO_O_HASHDATAIN14 0x00000638
+
+// HASH Data Input 15
+#define CRYPTO_O_HASHDATAIN15 0x0000063C
+
+// HASH Data Input 16
+#define CRYPTO_O_HASHDATAIN16 0x00000640
+
+// HASH Data Input 17
+#define CRYPTO_O_HASHDATAIN17 0x00000644
+
+// HASH Data Input 18
+#define CRYPTO_O_HASHDATAIN18 0x00000648
+
+// HASH Data Input 19
+#define CRYPTO_O_HASHDATAIN19 0x0000064C
+
+// HASH Data Input 20
+#define CRYPTO_O_HASHDATAIN20 0x00000650
+
+// HASH Data Input 21
+#define CRYPTO_O_HASHDATAIN21 0x00000654
+
+// HASH Data Input 22
+#define CRYPTO_O_HASHDATAIN22 0x00000658
+
+// HASH Data Input 23
+#define CRYPTO_O_HASHDATAIN23 0x0000065C
+
+// HASH Data Input 24
+#define CRYPTO_O_HASHDATAIN24 0x00000660
+
+// HASH Data Input 25
+#define CRYPTO_O_HASHDATAIN25 0x00000664
+
+// HASH Data Input 26
+#define CRYPTO_O_HASHDATAIN26 0x00000668
+
+// HASH Data Input 27
+#define CRYPTO_O_HASHDATAIN27 0x0000066C
+
+// HASH Data Input 28
+#define CRYPTO_O_HASHDATAIN28 0x00000670
+
+// HASH Data Input 29
+#define CRYPTO_O_HASHDATAIN29 0x00000674
+
+// HASH Data Input 30
+#define CRYPTO_O_HASHDATAIN30 0x00000678
+
+// HASH Data Input 31
+#define CRYPTO_O_HASHDATAIN31 0x0000067C
+
+// HASH Input_Output Buffer Control
+#define CRYPTO_O_HASHIOBUFCTRL 0x00000680
+
+// HASH Mode
+#define CRYPTO_O_HASHMODE 0x00000684
+
+// HASH Input Length LSB
+#define CRYPTO_O_HASHINLENL 0x00000688
+
+// HASH Input Length MSB
+#define CRYPTO_O_HASHINLENH 0x0000068C
+
+// HASH Digest A
+#define CRYPTO_O_HASHDIGESTA 0x000006C0
+
+// HASH Digest B
+#define CRYPTO_O_HASHDIGESTB 0x000006C4
+
+// HASH Digest C
+#define CRYPTO_O_HASHDIGESTC 0x000006C8
+
+// HASH Digest D
+#define CRYPTO_O_HASHDIGESTD 0x000006CC
+
+// HASH Digest E
+#define CRYPTO_O_HASHDIGESTE 0x000006D0
+
+// HASH Digest F
+#define CRYPTO_O_HASHDIGESTF 0x000006D4
+
+// HASH Digest G
+#define CRYPTO_O_HASHDIGESTG 0x000006D8
+
+// HASH Digest H
+#define CRYPTO_O_HASHDIGESTH 0x000006DC
+
+// HASH Digest I
+#define CRYPTO_O_HASHDIGESTI 0x000006E0
+
+// HASH Digest J
+#define CRYPTO_O_HASHDIGESTJ 0x000006E4
+
+// HASH Digest K
+#define CRYPTO_O_HASHDIGESTK 0x000006E8
+
+// HASH Digest L
+#define CRYPTO_O_HASHDIGESTL 0x000006EC
+
+// HASH Digest M
+#define CRYPTO_O_HASHDIGESTM 0x000006F0
+
+// HASH Digest N
+#define CRYPTO_O_HASHDIGESTN 0x000006F4
+
+// HASH Digest 0
+#define CRYPTO_O_HASHDIGESTO 0x000006F8
+
+// HASH Digest P
+#define CRYPTO_O_HASHDIGESTP 0x000006FC
+
+// Algorithm Select
+#define CRYPTO_O_ALGSEL 0x00000700
+
+// DMA Protection Control
+#define CRYPTO_O_DMAPROTCTL 0x00000704
+
+// Software Reset
+#define CRYPTO_O_SWRESET 0x00000740
+
+// Control Interrupt Configuration
+#define CRYPTO_O_IRQTYPE 0x00000780
+
+// Control Interrupt Enable
+#define CRYPTO_O_IRQEN 0x00000784
+
+// Control Interrupt Clear
+#define CRYPTO_O_IRQCLR 0x00000788
+
+// Control Interrupt Set
+#define CRYPTO_O_IRQSET 0x0000078C
+
+// Control Interrupt Status
+#define CRYPTO_O_IRQSTAT 0x00000790
+
+// Hardware Version
+#define CRYPTO_O_HWVER 0x000007FC
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_DMACH0CTL
+//
+//*****************************************************************************
+// Field: [1] PRIO
+//
+// Channel priority
+// 0: Low
+// 1: High
+// If both channels have the same priority, access of the channels to the
+// external port is arbitrated using the round robin scheme. If one channel has
+// a high priority and another one low, the channel with the high priority is
+// served first, in case of simultaneous access requests.
+#define CRYPTO_DMACH0CTL_PRIO 0x00000002
+#define CRYPTO_DMACH0CTL_PRIO_BITN 1
+#define CRYPTO_DMACH0CTL_PRIO_M 0x00000002
+#define CRYPTO_DMACH0CTL_PRIO_S 1
+
+// Field: [0] EN
+//
+// Channel enable
+// 0: Disabled
+// 1: Enable
+// Note: Disabling an active channel interrupts the DMA operation. The ongoing
+// block transfer completes, but no new transfers are requested.
+#define CRYPTO_DMACH0CTL_EN 0x00000001
+#define CRYPTO_DMACH0CTL_EN_BITN 0
+#define CRYPTO_DMACH0CTL_EN_M 0x00000001
+#define CRYPTO_DMACH0CTL_EN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_DMACH0EXTADDR
+//
+//*****************************************************************************
+// Field: [31:0] ADDR
+//
+// Channel external address value
+// When read during operation, it holds the last updated external address after
+// being sent to the master interface. Note: The crypto DMA copies out upto 3
+// bytes until it hits a word boundary, thus the address need not be word
+// aligned.
+#define CRYPTO_DMACH0EXTADDR_ADDR_W 32
+#define CRYPTO_DMACH0EXTADDR_ADDR_M 0xFFFFFFFF
+#define CRYPTO_DMACH0EXTADDR_ADDR_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_DMACH0LEN
+//
+//*****************************************************************************
+// Field: [15:0] DMALEN
+//
+// Channel DMA length in bytes
+// During configuration, this register contains the DMA transfer length in
+// bytes. During operation, it contains the last updated value of the DMA
+// transfer length after being sent to the master interface.
+// Note: Setting this register to a nonzero value starts the transfer if the
+// channel is enabled. Therefore, this register must be written last when
+// setting up a DMA channel.
+#define CRYPTO_DMACH0LEN_DMALEN_W 16
+#define CRYPTO_DMACH0LEN_DMALEN_M 0x0000FFFF
+#define CRYPTO_DMACH0LEN_DMALEN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_DMASTAT
+//
+//*****************************************************************************
+// Field: [17] PORT_ERR
+//
+// Reflects possible transfer errors on the AHB port.
+#define CRYPTO_DMASTAT_PORT_ERR 0x00020000
+#define CRYPTO_DMASTAT_PORT_ERR_BITN 17
+#define CRYPTO_DMASTAT_PORT_ERR_M 0x00020000
+#define CRYPTO_DMASTAT_PORT_ERR_S 17
+
+// Field: [1] CH1_ACT
+//
+// A value of 1 indicates that channel 1 is active (DMA transfer on-going).
+#define CRYPTO_DMASTAT_CH1_ACT 0x00000002
+#define CRYPTO_DMASTAT_CH1_ACT_BITN 1
+#define CRYPTO_DMASTAT_CH1_ACT_M 0x00000002
+#define CRYPTO_DMASTAT_CH1_ACT_S 1
+
+// Field: [0] CH0_ACT
+//
+// A value of 1 indicates that channel 0 is active (DMA transfer on-going).
+#define CRYPTO_DMASTAT_CH0_ACT 0x00000001
+#define CRYPTO_DMASTAT_CH0_ACT_BITN 0
+#define CRYPTO_DMASTAT_CH0_ACT_M 0x00000001
+#define CRYPTO_DMASTAT_CH0_ACT_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_DMASWRESET
+//
+//*****************************************************************************
+// Field: [0] SWRES
+//
+// Software reset enable
+// 0 : Disabled
+// 1 : Enabled (self-cleared to 0)
+// Completion of the software reset must be checked through the DMASTAT
+#define CRYPTO_DMASWRESET_SWRES 0x00000001
+#define CRYPTO_DMASWRESET_SWRES_BITN 0
+#define CRYPTO_DMASWRESET_SWRES_M 0x00000001
+#define CRYPTO_DMASWRESET_SWRES_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_DMACH1CTL
+//
+//*****************************************************************************
+// Field: [1] PRIO
+//
+// Channel priority
+// 0: Low
+// 1: High
+// If both channels have the same priority, access of the channels to the
+// external port is arbitrated using the round robin scheme. If one channel has
+// a high priority and another one low, the channel with the high priority is
+// served first, in case of simultaneous access requests.
+#define CRYPTO_DMACH1CTL_PRIO 0x00000002
+#define CRYPTO_DMACH1CTL_PRIO_BITN 1
+#define CRYPTO_DMACH1CTL_PRIO_M 0x00000002
+#define CRYPTO_DMACH1CTL_PRIO_S 1
+
+// Field: [0] EN
+//
+// Channel enable
+// 0: Disabled
+// 1: Enable
+// Note: Disabling an active channel interrupts the DMA operation. The ongoing
+// block transfer completes, but no new transfers are requested.
+#define CRYPTO_DMACH1CTL_EN 0x00000001
+#define CRYPTO_DMACH1CTL_EN_BITN 0
+#define CRYPTO_DMACH1CTL_EN_M 0x00000001
+#define CRYPTO_DMACH1CTL_EN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_DMACH1EXTADDR
+//
+//*****************************************************************************
+// Field: [31:0] ADDR
+//
+// Channel external address value.
+// When read during operation, it holds the last updated external address after
+// being sent to the master interface. Note: The crypto DMA copies out upto 3
+// bytes until it hits a word boundary, thus the address need not be word
+// aligned.
+#define CRYPTO_DMACH1EXTADDR_ADDR_W 32
+#define CRYPTO_DMACH1EXTADDR_ADDR_M 0xFFFFFFFF
+#define CRYPTO_DMACH1EXTADDR_ADDR_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_DMACH1LEN
+//
+//*****************************************************************************
+// Field: [15:0] DMALEN
+//
+// Channel DMA length in bytes.
+// During configuration, this register contains the DMA transfer length in
+// bytes. During operation, it contains the last updated value of the DMA
+// transfer length after being sent to the master interface.
+// Note: Setting this register to a nonzero value starts the transfer if the
+// channel is enabled. Therefore, this register must be written last when
+// setting up a DMA channel.
+#define CRYPTO_DMACH1LEN_DMALEN_W 16
+#define CRYPTO_DMACH1LEN_DMALEN_M 0x0000FFFF
+#define CRYPTO_DMACH1LEN_DMALEN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_DMABUSCFG
+//
+//*****************************************************************************
+// Field: [15:12] AHB_MST1_BURST_SIZE
+//
+// Maximum burst size that can be performed on the AHB bus
+// ENUMs:
+// 64_BYTE 64 bytes
+// 32_BYTE 32 bytes
+// 16_BYTE 16 bytes
+// 8_BYTE 8 bytes
+// 4_BYTE 4 bytes
+#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_W 4
+#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_M 0x0000F000
+#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_S 12
+#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_64_BYTE 0x00006000
+#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_32_BYTE 0x00005000
+#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_16_BYTE 0x00004000
+#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_8_BYTE 0x00003000
+#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_4_BYTE 0x00002000
+
+// Field: [11] AHB_MST1_IDLE_EN
+//
+// Idle insertion between consecutive burst transfers on AHB
+// ENUMs:
+// IDLE Idle transfer insertion enabled
+// NO_IDLE Do not insert idle transfers.
+#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN 0x00000800
+#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_BITN 11
+#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_M 0x00000800
+#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_S 11
+#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_IDLE 0x00000800
+#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_NO_IDLE 0x00000000
+
+// Field: [10] AHB_MST1_INCR_EN
+//
+// Burst length type of AHB transfer
+// ENUMs:
+// SPECIFIED Fixed length bursts or single transfers
+// UNSPECIFIED Unspecified length burst transfers
+#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN 0x00000400
+#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_BITN 10
+#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_M 0x00000400
+#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_S 10
+#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_SPECIFIED 0x00000400
+#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_UNSPECIFIED 0x00000000
+
+// Field: [9] AHB_MST1_LOCK_EN
+//
+// Locked transform on AHB
+// ENUMs:
+// LOCKED Transfers are locked
+// NOT_LOCKED Transfers are not locked
+#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN 0x00000200
+#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_BITN 9
+#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_M 0x00000200
+#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_S 9
+#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_LOCKED 0x00000200
+#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_NOT_LOCKED 0x00000000
+
+// Field: [8] AHB_MST1_BIGEND
+//
+// Endianess for the AHB master
+// ENUMs:
+// BIG_ENDIAN Big Endian
+// LITTLE_ENDIAN Little Endian
+#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND 0x00000100
+#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_BITN 8
+#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_M 0x00000100
+#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_S 8
+#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_BIG_ENDIAN 0x00000100
+#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_LITTLE_ENDIAN 0x00000000
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_DMAPORTERR
+//
+//*****************************************************************************
+// Field: [12] PORT1_AHB_ERROR
+//
+// A value of 1 indicates that the EIP-101 has detected an AHB bus error
+#define CRYPTO_DMAPORTERR_PORT1_AHB_ERROR 0x00001000
+#define CRYPTO_DMAPORTERR_PORT1_AHB_ERROR_BITN 12
+#define CRYPTO_DMAPORTERR_PORT1_AHB_ERROR_M 0x00001000
+#define CRYPTO_DMAPORTERR_PORT1_AHB_ERROR_S 12
+
+// Field: [9] PORT1_CHANNEL
+//
+// Indicates which channel has serviced last (channel 0 or channel 1) by AHB
+// master port.
+#define CRYPTO_DMAPORTERR_PORT1_CHANNEL 0x00000200
+#define CRYPTO_DMAPORTERR_PORT1_CHANNEL_BITN 9
+#define CRYPTO_DMAPORTERR_PORT1_CHANNEL_M 0x00000200
+#define CRYPTO_DMAPORTERR_PORT1_CHANNEL_S 9
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_DMAHWVER
+//
+//*****************************************************************************
+// Field: [27:24] HW_MAJOR_VERSION
+//
+// Major version number
+#define CRYPTO_DMAHWVER_HW_MAJOR_VERSION_W 4
+#define CRYPTO_DMAHWVER_HW_MAJOR_VERSION_M 0x0F000000
+#define CRYPTO_DMAHWVER_HW_MAJOR_VERSION_S 24
+
+// Field: [23:20] HW_MINOR_VERSION
+//
+// Minor version number
+#define CRYPTO_DMAHWVER_HW_MINOR_VERSION_W 4
+#define CRYPTO_DMAHWVER_HW_MINOR_VERSION_M 0x00F00000
+#define CRYPTO_DMAHWVER_HW_MINOR_VERSION_S 20
+
+// Field: [19:16] HW_PATCH_LEVEL
+//
+// Patch level
+// Starts at 0 at first delivery of this version
+#define CRYPTO_DMAHWVER_HW_PATCH_LEVEL_W 4
+#define CRYPTO_DMAHWVER_HW_PATCH_LEVEL_M 0x000F0000
+#define CRYPTO_DMAHWVER_HW_PATCH_LEVEL_S 16
+
+// Field: [15:8] EIP_NUMBER_COMPL
+//
+// Bit-by-bit complement of the EIP_NUMBER field bits.
+#define CRYPTO_DMAHWVER_EIP_NUMBER_COMPL_W 8
+#define CRYPTO_DMAHWVER_EIP_NUMBER_COMPL_M 0x0000FF00
+#define CRYPTO_DMAHWVER_EIP_NUMBER_COMPL_S 8
+
+// Field: [7:0] EIP_NUMBER
+//
+// Binary encoding of the EIP-number of this DMA controller (209)
+#define CRYPTO_DMAHWVER_EIP_NUMBER_W 8
+#define CRYPTO_DMAHWVER_EIP_NUMBER_M 0x000000FF
+#define CRYPTO_DMAHWVER_EIP_NUMBER_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_KEYWRITEAREA
+//
+//*****************************************************************************
+// Field: [7] RAM_AREA7
+//
+// Each RAM_AREAx represents an area of 128 bits.
+// Select the key store RAM area(s) where the key(s) needs to be written
+// 0: RAM_AREA7 is not selected to be written.
+// 1: RAM_AREA7 is selected to be written.
+// Writing to multiple RAM locations is possible only when the selected RAM
+// areas are sequential.
+// Keys that require more than one RAM locations (key size is 192 or 256 bits),
+// must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4,
+// or RAM_AREA6.
+// ENUMs:
+// SEL This RAM area is selected to be written
+// NOT_SEL This RAM area is not selected to be written
+#define CRYPTO_KEYWRITEAREA_RAM_AREA7 0x00000080
+#define CRYPTO_KEYWRITEAREA_RAM_AREA7_BITN 7
+#define CRYPTO_KEYWRITEAREA_RAM_AREA7_M 0x00000080
+#define CRYPTO_KEYWRITEAREA_RAM_AREA7_S 7
+#define CRYPTO_KEYWRITEAREA_RAM_AREA7_SEL 0x00000080
+#define CRYPTO_KEYWRITEAREA_RAM_AREA7_NOT_SEL 0x00000000
+
+// Field: [6] RAM_AREA6
+//
+// Each RAM_AREAx represents an area of 128 bits.
+// Select the key store RAM area(s) where the key(s) needs to be written
+// 0: RAM_AREA6 is not selected to be written.
+// 1: RAM_AREA6 is selected to be written.
+// Writing to multiple RAM locations is possible only when the selected RAM
+// areas are sequential.
+// Keys that require more than one RAM locations (key size is 192 or 256 bits),
+// must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4,
+// or RAM_AREA6.
+// ENUMs:
+// SEL This RAM area is selected to be written
+// NOT_SEL This RAM area is not selected to be written
+#define CRYPTO_KEYWRITEAREA_RAM_AREA6 0x00000040
+#define CRYPTO_KEYWRITEAREA_RAM_AREA6_BITN 6
+#define CRYPTO_KEYWRITEAREA_RAM_AREA6_M 0x00000040
+#define CRYPTO_KEYWRITEAREA_RAM_AREA6_S 6
+#define CRYPTO_KEYWRITEAREA_RAM_AREA6_SEL 0x00000040
+#define CRYPTO_KEYWRITEAREA_RAM_AREA6_NOT_SEL 0x00000000
+
+// Field: [5] RAM_AREA5
+//
+// Each RAM_AREAx represents an area of 128 bits.
+// Select the key store RAM area(s) where the key(s) needs to be written
+// 0: RAM_AREA5 is not selected to be written.
+// 1: RAM_AREA5 is selected to be written.
+// Writing to multiple RAM locations is possible only when the selected RAM
+// areas are sequential.
+// Keys that require more than one RAM locations (key size is 192 or 256 bits),
+// must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4,
+// or RAM_AREA6.
+// ENUMs:
+// SEL This RAM area is selected to be written
+// NOT_SEL This RAM area is not selected to be written
+#define CRYPTO_KEYWRITEAREA_RAM_AREA5 0x00000020
+#define CRYPTO_KEYWRITEAREA_RAM_AREA5_BITN 5
+#define CRYPTO_KEYWRITEAREA_RAM_AREA5_M 0x00000020
+#define CRYPTO_KEYWRITEAREA_RAM_AREA5_S 5
+#define CRYPTO_KEYWRITEAREA_RAM_AREA5_SEL 0x00000020
+#define CRYPTO_KEYWRITEAREA_RAM_AREA5_NOT_SEL 0x00000000
+
+// Field: [4] RAM_AREA4
+//
+// Each RAM_AREAx represents an area of 128 bits.
+// Select the key store RAM area(s) where the key(s) needs to be written
+// 0: RAM_AREA4 is not selected to be written.
+// 1: RAM_AREA4 is selected to be written.
+// Writing to multiple RAM locations is possible only when the selected RAM
+// areas are sequential.
+// Keys that require more than one RAM locations (key size is 192 or 256 bits),
+// must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4,
+// or RAM_AREA6.
+// ENUMs:
+// SEL This RAM area is selected to be written
+// NOT_SEL This RAM area is not selected to be written
+#define CRYPTO_KEYWRITEAREA_RAM_AREA4 0x00000010
+#define CRYPTO_KEYWRITEAREA_RAM_AREA4_BITN 4
+#define CRYPTO_KEYWRITEAREA_RAM_AREA4_M 0x00000010
+#define CRYPTO_KEYWRITEAREA_RAM_AREA4_S 4
+#define CRYPTO_KEYWRITEAREA_RAM_AREA4_SEL 0x00000010
+#define CRYPTO_KEYWRITEAREA_RAM_AREA4_NOT_SEL 0x00000000
+
+// Field: [3] RAM_AREA3
+//
+// Each RAM_AREAx represents an area of 128 bits.
+// Select the key store RAM area(s) where the key(s) needs to be written
+// 0: RAM_AREA3 is not selected to be written.
+// 1: RAM_AREA3 is selected to be written.
+// Writing to multiple RAM locations is possible only when the selected RAM
+// areas are sequential.
+// Keys that require more than one RAM locations (key size is 192 or 256 bits),
+// must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4,
+// or RAM_AREA6.
+// ENUMs:
+// SEL This RAM area is selected to be written
+// NOT_SEL This RAM area is not selected to be written
+#define CRYPTO_KEYWRITEAREA_RAM_AREA3 0x00000008
+#define CRYPTO_KEYWRITEAREA_RAM_AREA3_BITN 3
+#define CRYPTO_KEYWRITEAREA_RAM_AREA3_M 0x00000008
+#define CRYPTO_KEYWRITEAREA_RAM_AREA3_S 3
+#define CRYPTO_KEYWRITEAREA_RAM_AREA3_SEL 0x00000008
+#define CRYPTO_KEYWRITEAREA_RAM_AREA3_NOT_SEL 0x00000000
+
+// Field: [2] RAM_AREA2
+//
+// Each RAM_AREAx represents an area of 128 bits.
+// Select the key store RAM area(s) where the key(s) needs to be written
+// 0: RAM_AREA2 is not selected to be written.
+// 1: RAM_AREA2 is selected to be written.
+// Writing to multiple RAM locations is possible only when the selected RAM
+// areas are sequential.
+// Keys that require more than one RAM locations (key size is 192 or 256 bits),
+// must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4,
+// or RAM_AREA6.
+// ENUMs:
+// SEL This RAM area is selected to be written
+// NOT_SEL This RAM area is not selected to be written
+#define CRYPTO_KEYWRITEAREA_RAM_AREA2 0x00000004
+#define CRYPTO_KEYWRITEAREA_RAM_AREA2_BITN 2
+#define CRYPTO_KEYWRITEAREA_RAM_AREA2_M 0x00000004
+#define CRYPTO_KEYWRITEAREA_RAM_AREA2_S 2
+#define CRYPTO_KEYWRITEAREA_RAM_AREA2_SEL 0x00000004
+#define CRYPTO_KEYWRITEAREA_RAM_AREA2_NOT_SEL 0x00000000
+
+// Field: [1] RAM_AREA1
+//
+// Each RAM_AREAx represents an area of 128 bits.
+// Select the key store RAM area(s) where the key(s) needs to be written
+// 0: RAM_AREA1 is not selected to be written.
+// 1: RAM_AREA1 is selected to be written.
+// Writing to multiple RAM locations is possible only when the selected RAM
+// areas are sequential.
+// Keys that require more than one RAM locations (key size is 192 or 256 bits),
+// must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4,
+// or RAM_AREA6.
+// ENUMs:
+// SEL This RAM area is selected to be written
+// NOT_SEL This RAM area is not selected to be written
+#define CRYPTO_KEYWRITEAREA_RAM_AREA1 0x00000002
+#define CRYPTO_KEYWRITEAREA_RAM_AREA1_BITN 1
+#define CRYPTO_KEYWRITEAREA_RAM_AREA1_M 0x00000002
+#define CRYPTO_KEYWRITEAREA_RAM_AREA1_S 1
+#define CRYPTO_KEYWRITEAREA_RAM_AREA1_SEL 0x00000002
+#define CRYPTO_KEYWRITEAREA_RAM_AREA1_NOT_SEL 0x00000000
+
+// Field: [0] RAM_AREA0
+//
+// Each RAM_AREAx represents an area of 128 bits.
+// Select the key store RAM area(s) where the key(s) needs to be written
+// 0: RAM_AREA0 is not selected to be written.
+// 1: RAM_AREA0 is selected to be written.
+// Writing to multiple RAM locations is possible only when the selected RAM
+// areas are sequential.
+// Keys that require more than one RAM locations (key size is 192 or 256 bits),
+// must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4,
+// or RAM_AREA6.
+// ENUMs:
+// SEL This RAM area is selected to be written
+// NOT_SEL This RAM area is not selected to be written
+#define CRYPTO_KEYWRITEAREA_RAM_AREA0 0x00000001
+#define CRYPTO_KEYWRITEAREA_RAM_AREA0_BITN 0
+#define CRYPTO_KEYWRITEAREA_RAM_AREA0_M 0x00000001
+#define CRYPTO_KEYWRITEAREA_RAM_AREA0_S 0
+#define CRYPTO_KEYWRITEAREA_RAM_AREA0_SEL 0x00000001
+#define CRYPTO_KEYWRITEAREA_RAM_AREA0_NOT_SEL 0x00000000
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_KEYWRITTENAREA
+//
+//*****************************************************************************
+// Field: [7] RAM_AREA_WRITTEN7
+//
+// On read this bit returns the key area written status.
+//
+// This bit can be reset by writing a 1.
+//
+// Note: This register will be reset on a soft reset initiated by writing to
+// DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key
+// store memory.
+// ENUMs:
+// WRITTEN This RAM area is written with valid key
+// information
+// NOT_WRITTEN This RAM area is not written with valid key
+// information
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7 0x00000080
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_BITN 7
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_M 0x00000080
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_S 7
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_WRITTEN 0x00000080
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_NOT_WRITTEN 0x00000000
+
+// Field: [6] RAM_AREA_WRITTEN6
+//
+// On read this bit returns the key area written status.
+//
+// This bit can be reset by writing a 1.
+//
+// Note: This register will be reset on a soft reset initiated by writing to
+// DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key
+// store memory.
+// ENUMs:
+// WRITTEN This RAM area is written with valid key
+// information
+// NOT_WRITTEN This RAM area is not written with valid key
+// information
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6 0x00000040
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_BITN 6
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_M 0x00000040
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_S 6
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_WRITTEN 0x00000040
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_NOT_WRITTEN 0x00000000
+
+// Field: [5] RAM_AREA_WRITTEN5
+//
+// On read this bit returns the key area written status.
+//
+// This bit can be reset by writing a 1.
+//
+// Note: This register will be reset on a soft reset initiated by writing to
+// DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key
+// store memory.
+// ENUMs:
+// WRITTEN This RAM area is written with valid key
+// information
+// NOT_WRITTEN This RAM area is not written with valid key
+// information
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5 0x00000020
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_BITN 5
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_M 0x00000020
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_S 5
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_WRITTEN 0x00000020
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_NOT_WRITTEN 0x00000000
+
+// Field: [4] RAM_AREA_WRITTEN4
+//
+// On read this bit returns the key area written status.
+//
+// This bit can be reset by writing a 1.
+//
+// Note: This register will be reset on a soft reset initiated by writing to
+// DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key
+// store memory.
+// ENUMs:
+// WRITTEN This RAM area is written with valid key
+// information
+// NOT_WRITTEN This RAM area is not written with valid key
+// information
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4 0x00000010
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_BITN 4
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_M 0x00000010
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_S 4
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_WRITTEN 0x00000010
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_NOT_WRITTEN 0x00000000
+
+// Field: [3] RAM_AREA_WRITTEN3
+//
+// On read this bit returns the key area written status.
+//
+// This bit can be reset by writing a 1.
+//
+// Note: This register will be reset on a soft reset initiated by writing to
+// DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key
+// store memory.
+// ENUMs:
+// WRITTEN This RAM area is written with valid key
+// information
+// NOT_WRITTEN This RAM area is not written with valid key
+// information
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3 0x00000008
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_BITN 3
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_M 0x00000008
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_S 3
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_WRITTEN 0x00000008
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_NOT_WRITTEN 0x00000000
+
+// Field: [2] RAM_AREA_WRITTEN2
+//
+// On read this bit returns the key area written status.
+//
+// This bit can be reset by writing a 1.
+//
+// Note: This register will be reset on a soft reset initiated by writing to
+// DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key
+// store memory.
+// ENUMs:
+// WRITTEN This RAM area is written with valid key
+// information
+// NOT_WRITTEN This RAM area is not written with valid key
+// information
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2 0x00000004
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_BITN 2
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_M 0x00000004
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_S 2
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_WRITTEN 0x00000004
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_NOT_WRITTEN 0x00000000
+
+// Field: [1] RAM_AREA_WRITTEN1
+//
+// On read this bit returns the key area written status.
+//
+// This bit can be reset by writing a 1.
+//
+// Note: This register will be reset on a soft reset initiated by writing to
+// DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key
+// store memory.
+// ENUMs:
+// WRITTEN This RAM area is written with valid key
+// information
+// NOT_WRITTEN This RAM area is not written with valid key
+// information
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1 0x00000002
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_BITN 1
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_M 0x00000002
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_S 1
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_WRITTEN 0x00000002
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_NOT_WRITTEN 0x00000000
+
+// Field: [0] RAM_AREA_WRITTEN0
+//
+// On read this bit returns the key area written status.
+//
+// This bit can be reset by writing a 1.
+//
+// Note: This register will be reset on a soft reset initiated by writing to
+// DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key
+// store memory.
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0 0x00000001
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_BITN 0
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_M 0x00000001
+#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_KEYSIZE
+//
+//*****************************************************************************
+// Field: [1:0] SIZE
+//
+// Key size:
+// 00: Reserved
+// When writing this to this register, the KEY_STORE_WRITTEN_AREA register is
+// reset.
+// ENUMs:
+// 256_BIT 256 bits
+// 192_BIT 192 bits
+// 128_BIT 128 bits
+#define CRYPTO_KEYSIZE_SIZE_W 2
+#define CRYPTO_KEYSIZE_SIZE_M 0x00000003
+#define CRYPTO_KEYSIZE_SIZE_S 0
+#define CRYPTO_KEYSIZE_SIZE_256_BIT 0x00000003
+#define CRYPTO_KEYSIZE_SIZE_192_BIT 0x00000002
+#define CRYPTO_KEYSIZE_SIZE_128_BIT 0x00000001
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_KEYREADAREA
+//
+//*****************************************************************************
+// Field: [31] BUSY
+//
+// Key store operation busy status flag (read only):
+// 0: Operation is complete.
+// 1: Operation is not completed and the key store is busy.
+#define CRYPTO_KEYREADAREA_BUSY 0x80000000
+#define CRYPTO_KEYREADAREA_BUSY_BITN 31
+#define CRYPTO_KEYREADAREA_BUSY_M 0x80000000
+#define CRYPTO_KEYREADAREA_BUSY_S 31
+
+// Field: [3:0] RAM_AREA
+//
+// Selects the area of the key store RAM from where the key needs to be read
+// that will be writen to the AES engine
+// RAM_AREA:
+//
+// RAM areas RAM_AREA0, RAM_AREA2, RAM_AREA4 and RAM_AREA6 are the only valid
+// read areas for 192 and 256 bits key sizes.
+// Only RAM areas that contain valid written keys can be selected.
+// ENUMs:
+// NO_RAM No RAM
+// RAM_AREA7 RAM Area 7
+// RAM_AREA6 RAM Area 6
+// RAM_AREA5 RAM Area 5
+// RAM_AREA4 RAM Area 4
+// RAM_AREA3 RAM Area 3
+// RAM_AREA2 RAM Area 2
+// RAM_AREA1 RAM Area 1
+// RAM_AREA0 RAM Area 0
+#define CRYPTO_KEYREADAREA_RAM_AREA_W 4
+#define CRYPTO_KEYREADAREA_RAM_AREA_M 0x0000000F
+#define CRYPTO_KEYREADAREA_RAM_AREA_S 0
+#define CRYPTO_KEYREADAREA_RAM_AREA_NO_RAM 0x00000008
+#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA7 0x00000007
+#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA6 0x00000006
+#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA5 0x00000005
+#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA4 0x00000004
+#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA3 0x00000003
+#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA2 0x00000002
+#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA1 0x00000001
+#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA0 0x00000000
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_AESKEY20
+//
+//*****************************************************************************
+// Field: [31:0] AES_KEY2
+//
+// AES_KEY2/AES_GHASH_H[31:0]
+//
+// For GCM:
+// -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these
+// registers. Only used for modes that use the GHASH function (GCM).
+// -[255:128] - This register is used to store intermediate values and is
+// initialized with 0s when loading a new key.
+//
+// For CCM:
+// -[255:0] - This register is used to store intermediate values.
+//
+// For CBC-MAC:
+// -[255:0] - ZEROES - This register must remain 0.
+#define CRYPTO_AESKEY20_AES_KEY2_W 32
+#define CRYPTO_AESKEY20_AES_KEY2_M 0xFFFFFFFF
+#define CRYPTO_AESKEY20_AES_KEY2_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_AESKEY21
+//
+//*****************************************************************************
+// Field: [31:0] AES_KEY2
+//
+// AES_KEY2/AES_GHASH_H[31:0]
+//
+// For GCM:
+// -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these
+// registers. Only used for modes that use the GHASH function (GCM).
+// -[255:128] - This register is used to store intermediate values and is
+// initialized with 0s when loading a new key.
+//
+// For CCM:
+// -[255:0] - This register is used to store intermediate values.
+//
+// For CBC-MAC:
+// -[255:0] - ZEROES - This register must remain 0.
+#define CRYPTO_AESKEY21_AES_KEY2_W 32
+#define CRYPTO_AESKEY21_AES_KEY2_M 0xFFFFFFFF
+#define CRYPTO_AESKEY21_AES_KEY2_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_AESKEY22
+//
+//*****************************************************************************
+// Field: [31:0] AES_KEY2
+//
+// AES_KEY2/AES_GHASH_H[31:0]
+//
+// For GCM:
+// -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these
+// registers. Only used for modes that use the GHASH function (GCM).
+// -[255:128] - This register is used to store intermediate values and is
+// initialized with 0s when loading a new key.
+//
+// For CCM:
+// -[255:0] - This register is used to store intermediate values.
+//
+// For CBC-MAC:
+// -[255:0] - ZEROES - This register must remain 0.
+#define CRYPTO_AESKEY22_AES_KEY2_W 32
+#define CRYPTO_AESKEY22_AES_KEY2_M 0xFFFFFFFF
+#define CRYPTO_AESKEY22_AES_KEY2_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_AESKEY23
+//
+//*****************************************************************************
+// Field: [31:0] AES_KEY2
+//
+// AES_KEY2/AES_GHASH_H[31:0]
+//
+// For GCM:
+// -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these
+// registers. Only used for modes that use the GHASH function (GCM).
+// -[255:128] - This register is used to store intermediate values and is
+// initialized with 0s when loading a new key.
+//
+// For CCM:
+// -[255:0] - This register is used to store intermediate values.
+//
+// For CBC-MAC:
+// -[255:0] - ZEROES - This register must remain 0.
+#define CRYPTO_AESKEY23_AES_KEY2_W 32
+#define CRYPTO_AESKEY23_AES_KEY2_M 0xFFFFFFFF
+#define CRYPTO_AESKEY23_AES_KEY2_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_AESKEY30
+//
+//*****************************************************************************
+// Field: [31:0] AES_KEY3
+//
+// AES_KEY3[31:0]/AES_KEY2[159:128]
+//
+// For GCM:
+// -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these
+// registers. Only used for modes that use the GHASH function (GCM).
+// -[255:128] - This register is used to store intermediate values and is
+// initialized with 0s when loading a new key.
+//
+// For CCM:
+// -[255:0] - This register is used to store intermediate values.
+//
+// For CBC-MAC:
+// -[255:0] - ZEROES - This register must remain 0.
+#define CRYPTO_AESKEY30_AES_KEY3_W 32
+#define CRYPTO_AESKEY30_AES_KEY3_M 0xFFFFFFFF
+#define CRYPTO_AESKEY30_AES_KEY3_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_AESKEY31
+//
+//*****************************************************************************
+// Field: [31:0] AES_KEY3
+//
+// AES_KEY3[31:0]/AES_KEY2[159:128]
+//
+// For GCM:
+// -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these
+// registers. Only used for modes that use the GHASH function (GCM).
+// -[255:128] - This register is used to store intermediate values and is
+// initialized with 0s when loading a new key.
+//
+// For CCM:
+// -[255:0] - This register is used to store intermediate values.
+//
+// For CBC-MAC:
+// -[255:0] - ZEROES - This register must remain 0.
+#define CRYPTO_AESKEY31_AES_KEY3_W 32
+#define CRYPTO_AESKEY31_AES_KEY3_M 0xFFFFFFFF
+#define CRYPTO_AESKEY31_AES_KEY3_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_AESKEY32
+//
+//*****************************************************************************
+// Field: [31:0] AES_KEY3
+//
+// AES_KEY3[31:0]/AES_KEY2[159:128]
+//
+// For GCM:
+// -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these
+// registers. Only used for modes that use the GHASH function (GCM).
+// -[255:128] - This register is used to store intermediate values and is
+// initialized with 0s when loading a new key.
+//
+// For CCM:
+// -[255:0] - This register is used to store intermediate values.
+//
+// For CBC-MAC:
+// -[255:0] - ZEROES - This register must remain 0.
+#define CRYPTO_AESKEY32_AES_KEY3_W 32
+#define CRYPTO_AESKEY32_AES_KEY3_M 0xFFFFFFFF
+#define CRYPTO_AESKEY32_AES_KEY3_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_AESKEY33
+//
+//*****************************************************************************
+// Field: [31:0] AES_KEY3
+//
+// AES_KEY3[31:0]/AES_KEY2[159:128]
+//
+// For GCM:
+// -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these
+// registers. Only used for modes that use the GHASH function (GCM).
+// -[255:128] - This register is used to store intermediate values and is
+// initialized with 0s when loading a new key.
+//
+// For CCM:
+// -[255:0] - This register is used to store intermediate values.
+//
+// For CBC-MAC:
+// -[255:0] - ZEROES - This register must remain 0.
+#define CRYPTO_AESKEY33_AES_KEY3_W 32
+#define CRYPTO_AESKEY33_AES_KEY3_M 0xFFFFFFFF
+#define CRYPTO_AESKEY33_AES_KEY3_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_AESIV0
+//
+//*****************************************************************************
+// Field: [31:0] AES_IV
+//
+// AES_IV[31:0]
+//
+// Initialization vector
+// Used for regular non-ECB modes (CBC/CTR):
+// -[127:0] - AES_IV - For regular AES operations (CBC and CTR) these registers
+// must be written with a new 128-bit IV. After an operation, these registers
+// contain the latest 128-bit result IV, generated by the EIP-120t. If CTR mode
+// is selected, this value is incremented with 0x1: After first use - When a
+// new data block is submitted to the engine
+//
+// For GCM:
+// -[127:0] - AES_IV - For GCM operations, these registers must be written with
+// a new 128-bit IV.
+// After an operation, these registers contain the updated 128-bit result IV,
+// generated by the EIP-120t. Note that bits [127:96] of the IV represent the
+// initial counter value (which is 1 for GCM) and must therefore be initialized
+// to 0x01000000. This value is incremented with 0x1: After first use - When a
+// new data block is submitted to the engine.
+//
+// For CCM:
+// -[127:0] - A0: For CCM this field must be written with value A0, this value
+// is the concatenation of: A0-flags (5-bits of 0 and 3-bits 'L'), Nonce and
+// counter value. 'L' must be a copy from the 'L' value of the AES_CTRL
+// register. This 'L' indicates the width of the Nonce and counter. The loaded
+// counter must be initialized to 0. The total width of A0 is 128-bit.
+//
+// For CBC-MAC:
+// -[127:0] - Zeroes - For CBC-MAC this register must be written with 0s at the
+// start of each operation. After an operation, these registers contain the
+// 128-bit TAG output, generated by the EIP-120t.
+#define CRYPTO_AESIV0_AES_IV_W 32
+#define CRYPTO_AESIV0_AES_IV_M 0xFFFFFFFF
+#define CRYPTO_AESIV0_AES_IV_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_AESIV1
+//
+//*****************************************************************************
+// Field: [31:0] AES_IV
+//
+// AES_IV[31:0]
+//
+// Initialization vector
+// Used for regular non-ECB modes (CBC/CTR):
+// -[127:0] - AES_IV - For regular AES operations (CBC and CTR) these registers
+// must be written with a new 128-bit IV. After an operation, these registers
+// contain the latest 128-bit result IV, generated by the EIP-120t. If CTR mode
+// is selected, this value is incremented with 0x1: After first use - When a
+// new data block is submitted to the engine
+//
+// For GCM:
+// -[127:0] - AES_IV - For GCM operations, these registers must be written with
+// a new 128-bit IV.
+// After an operation, these registers contain the updated 128-bit result IV,
+// generated by the EIP-120t. Note that bits [127:96] of the IV represent the
+// initial counter value (which is 1 for GCM) and must therefore be initialized
+// to 0x01000000. This value is incremented with 0x1: After first use - When a
+// new data block is submitted to the engine.
+//
+// For CCM:
+// -[127:0] - A0: For CCM this field must be written with value A0, this value
+// is the concatenation of: A0-flags (5-bits of 0 and 3-bits 'L'), Nonce and
+// counter value. 'L' must be a copy from the 'L' value of the AES_CTRL
+// register. This 'L' indicates the width of the Nonce and counter. The loaded
+// counter must be initialized to 0. The total width of A0 is 128-bit.
+//
+// For CBC-MAC:
+// -[127:0] - Zeroes - For CBC-MAC this register must be written with 0s at the
+// start of each operation. After an operation, these registers contain the
+// 128-bit TAG output, generated by the EIP-120t.
+#define CRYPTO_AESIV1_AES_IV_W 32
+#define CRYPTO_AESIV1_AES_IV_M 0xFFFFFFFF
+#define CRYPTO_AESIV1_AES_IV_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_AESIV2
+//
+//*****************************************************************************
+// Field: [31:0] AES_IV
+//
+// AES_IV[31:0]
+//
+// Initialization vector
+// Used for regular non-ECB modes (CBC/CTR):
+// -[127:0] - AES_IV - For regular AES operations (CBC and CTR) these registers
+// must be written with a new 128-bit IV. After an operation, these registers
+// contain the latest 128-bit result IV, generated by the EIP-120t. If CTR mode
+// is selected, this value is incremented with 0x1: After first use - When a
+// new data block is submitted to the engine
+//
+// For GCM:
+// -[127:0] - AES_IV - For GCM operations, these registers must be written with
+// a new 128-bit IV.
+// After an operation, these registers contain the updated 128-bit result IV,
+// generated by the EIP-120t. Note that bits [127:96] of the IV represent the
+// initial counter value (which is 1 for GCM) and must therefore be initialized
+// to 0x01000000. This value is incremented with 0x1: After first use - When a
+// new data block is submitted to the engine.
+//
+// For CCM:
+// -[127:0] - A0: For CCM this field must be written with value A0, this value
+// is the concatenation of: A0-flags (5-bits of 0 and 3-bits 'L'), Nonce and
+// counter value. 'L' must be a copy from the 'L' value of the AES_CTRL
+// register. This 'L' indicates the width of the Nonce and counter. The loaded
+// counter must be initialized to 0. The total width of A0 is 128-bit.
+//
+// For CBC-MAC:
+// -[127:0] - Zeroes - For CBC-MAC this register must be written with 0s at the
+// start of each operation. After an operation, these registers contain the
+// 128-bit TAG output, generated by the EIP-120t.
+#define CRYPTO_AESIV2_AES_IV_W 32
+#define CRYPTO_AESIV2_AES_IV_M 0xFFFFFFFF
+#define CRYPTO_AESIV2_AES_IV_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_AESIV3
+//
+//*****************************************************************************
+// Field: [31:0] AES_IV
+//
+// AES_IV[31:0]
+//
+// Initialization vector
+// Used for regular non-ECB modes (CBC/CTR):
+// -[127:0] - AES_IV - For regular AES operations (CBC and CTR) these registers
+// must be written with a new 128-bit IV. After an operation, these registers
+// contain the latest 128-bit result IV, generated by the EIP-120t. If CTR mode
+// is selected, this value is incremented with 0x1: After first use - When a
+// new data block is submitted to the engine
+//
+// For GCM:
+// -[127:0] - AES_IV - For GCM operations, these registers must be written with
+// a new 128-bit IV.
+// After an operation, these registers contain the updated 128-bit result IV,
+// generated by the EIP-120t. Note that bits [127:96] of the IV represent the
+// initial counter value (which is 1 for GCM) and must therefore be initialized
+// to 0x01000000. This value is incremented with 0x1: After first use - When a
+// new data block is submitted to the engine.
+//
+// For CCM:
+// -[127:0] - A0: For CCM this field must be written with value A0, this value
+// is the concatenation of: A0-flags (5-bits of 0 and 3-bits 'L'), Nonce and
+// counter value. 'L' must be a copy from the 'L' value of the AES_CTRL
+// register. This 'L' indicates the width of the Nonce and counter. The loaded
+// counter must be initialized to 0. The total width of A0 is 128-bit.
+//
+// For CBC-MAC:
+// -[127:0] - Zeroes - For CBC-MAC this register must be written with 0s at the
+// start of each operation. After an operation, these registers contain the
+// 128-bit TAG output, generated by the EIP-120t.
+#define CRYPTO_AESIV3_AES_IV_W 32
+#define CRYPTO_AESIV3_AES_IV_M 0xFFFFFFFF
+#define CRYPTO_AESIV3_AES_IV_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_AESCTL
+//
+//*****************************************************************************
+// Field: [31] CONTEXT_READY
+//
+// If 1, this read-only status bit indicates that the context data registers
+// can be overwritten and the host is permitted to write the next context.
+#define CRYPTO_AESCTL_CONTEXT_READY 0x80000000
+#define CRYPTO_AESCTL_CONTEXT_READY_BITN 31
+#define CRYPTO_AESCTL_CONTEXT_READY_M 0x80000000
+#define CRYPTO_AESCTL_CONTEXT_READY_S 31
+
+// Field: [30] SAVED_CONTEXT_RDY
+//
+// If 1, this status bit indicates that an AES authentication TAG and/or IV
+// block(s) is/are available for the host to retrieve. This bit is only
+// asserted if the save_context bit is set to 1. The bit is mutual exclusive
+// with the context_ready bit.
+// Writing one clears the bit to 0, indicating the AES core can start its next
+// operation. This bit is also cleared when the 4th word of the output TAG
+// and/or IV is read.
+// Note: All other mode bit writes are ignored when this mode bit is written
+// with 1.
+// Note: This bit is controlled automatically by the EIP-120t for TAG read DMA
+// operations.
+#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY 0x40000000
+#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_BITN 30
+#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_M 0x40000000
+#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_S 30
+
+// Field: [29] SAVE_CONTEXT
+//
+// This bit indicates that an authentication TAG or result IV needs to be
+// stored as a result context.
+// Typically this bit must be set for authentication modes returning a TAG
+// (CBC-MAC, GCM and CCM), or for basic encryption modes that require future
+// continuation with the current result IV.
+// If this bit is set, the engine retains its full context until the TAG and/or
+// IV registers are read.
+// The TAG or IV must be read before the AES engine can start a new operation.
+#define CRYPTO_AESCTL_SAVE_CONTEXT 0x20000000
+#define CRYPTO_AESCTL_SAVE_CONTEXT_BITN 29
+#define CRYPTO_AESCTL_SAVE_CONTEXT_M 0x20000000
+#define CRYPTO_AESCTL_SAVE_CONTEXT_S 29
+
+// Field: [24:22] CCM_M
+//
+// Defines M, which indicates the length of the authentication field for CCM
+// operations; the authentication field length equals two times (the value of
+// CCM-M plus one).
+// Note: The EIP-120t always returns a 128-bit authentication field, of which
+// the M least significant bytes are valid. All values are supported.
+#define CRYPTO_AESCTL_CCM_M_W 3
+#define CRYPTO_AESCTL_CCM_M_M 0x01C00000
+#define CRYPTO_AESCTL_CCM_M_S 22
+
+// Field: [21:19] CCM_L
+//
+// Defines L, which indicates the width of the length field for CCM operations;
+// the length field in bytes equals the value of CMM-L plus one. All values are
+// supported.
+#define CRYPTO_AESCTL_CCM_L_W 3
+#define CRYPTO_AESCTL_CCM_L_M 0x00380000
+#define CRYPTO_AESCTL_CCM_L_S 19
+
+// Field: [18] CCM
+//
+// If set to 1, AES-CCM is selected
+// AES-CCM is a combined mode, using AES for authentication and encryption.
+// Note: Selecting AES-CCM mode requires writing of the AAD length register
+// after all other registers.
+// Note: The CTR mode bit in this register must also be set to 1 to enable
+// AES-CTR; selecting other AES modes than CTR mode is invalid.
+#define CRYPTO_AESCTL_CCM 0x00040000
+#define CRYPTO_AESCTL_CCM_BITN 18
+#define CRYPTO_AESCTL_CCM_M 0x00040000
+#define CRYPTO_AESCTL_CCM_S 18
+
+// Field: [17:16] GCM
+//
+// Set these bits to 11 to select AES-GCM mode.
+// AES-GCM is a combined mode, using the Galois field multiplier GF(2 to the
+// power of 128) for authentication and AES-CTR mode for encryption.
+// Note: The CTR mode bit in this register must also be set to 1 to enable
+// AES-CTR
+// Bit combination description:
+// 00 = No GCM mode
+// 01 = Reserved, do not select
+// 10 = Reserved, do not select
+// 11 = Autonomous GHASH (both H- and Y0-encrypted calculated internally)
+// Note: The EIP-120t-1 configuration only supports mode 11 (autonomous GHASH),
+// other GCM modes are not allowed.
+#define CRYPTO_AESCTL_GCM_W 2
+#define CRYPTO_AESCTL_GCM_M 0x00030000
+#define CRYPTO_AESCTL_GCM_S 16
+
+// Field: [15] CBC_MAC
+//
+// Set to 1 to select AES-CBC MAC mode.
+// The direction bit must be set to 1 for this mode.
+// Selecting this mode requires writing the length register after all other
+// registers.
+#define CRYPTO_AESCTL_CBC_MAC 0x00008000
+#define CRYPTO_AESCTL_CBC_MAC_BITN 15
+#define CRYPTO_AESCTL_CBC_MAC_M 0x00008000
+#define CRYPTO_AESCTL_CBC_MAC_S 15
+
+// Field: [8:7] CTR_WIDTH
+//
+// Specifies the counter width for AES-CTR mode
+// 00 = 32-bit counter
+// 01 = 64-bit counter
+// 10 = 96-bit counter
+// 11 = 128-bit counter
+// ENUMs:
+// 128_BIT 128 bits
+// 96_BIT 96 bits
+// 64_BIT 64 bits
+// 32_BIT 32 bits
+#define CRYPTO_AESCTL_CTR_WIDTH_W 2
+#define CRYPTO_AESCTL_CTR_WIDTH_M 0x00000180
+#define CRYPTO_AESCTL_CTR_WIDTH_S 7
+#define CRYPTO_AESCTL_CTR_WIDTH_128_BIT 0x00000180
+#define CRYPTO_AESCTL_CTR_WIDTH_96_BIT 0x00000100
+#define CRYPTO_AESCTL_CTR_WIDTH_64_BIT 0x00000080
+#define CRYPTO_AESCTL_CTR_WIDTH_32_BIT 0x00000000
+
+// Field: [6] CTR
+//
+// If set to 1, AES counter mode (CTR) is selected.
+// Note: This bit must also be set for GCM and CCM, when encryption/decryption
+// is required.
+#define CRYPTO_AESCTL_CTR 0x00000040
+#define CRYPTO_AESCTL_CTR_BITN 6
+#define CRYPTO_AESCTL_CTR_M 0x00000040
+#define CRYPTO_AESCTL_CTR_S 6
+
+// Field: [5] CBC
+//
+// If set to 1, cipher-block-chaining (CBC) mode is selected.
+#define CRYPTO_AESCTL_CBC 0x00000020
+#define CRYPTO_AESCTL_CBC_BITN 5
+#define CRYPTO_AESCTL_CBC_M 0x00000020
+#define CRYPTO_AESCTL_CBC_S 5
+
+// Field: [4:3] KEY_SIZE
+//
+// This read-only field specifies the key size.
+// The key size is automatically configured when a new key is loaded through
+// the key store module.
+// 00 = N/A - Reserved
+// 01 = 128-bit
+// 10 = 192-bit
+// 11 = 256-bit
+#define CRYPTO_AESCTL_KEY_SIZE_W 2
+#define CRYPTO_AESCTL_KEY_SIZE_M 0x00000018
+#define CRYPTO_AESCTL_KEY_SIZE_S 3
+
+// Field: [2] DIR
+//
+// If set to 1 an encrypt operation is performed.
+// If set to 0 a decrypt operation is performed.
+// This bit must be written with a 1 when CBC-MAC is selected.
+#define CRYPTO_AESCTL_DIR 0x00000004
+#define CRYPTO_AESCTL_DIR_BITN 2
+#define CRYPTO_AESCTL_DIR_M 0x00000004
+#define CRYPTO_AESCTL_DIR_S 2
+
+// Field: [1] INPUT_READY
+//
+// If 1, this status bit indicates that the 16-byte AES input buffer is empty.
+// The host is permitted to write the next block of data.
+// Writing 0 clears the bit to 0 and indicates that the AES core can use the
+// provided input data block.
+// Writing 1 to this bit is ignored.
+// Note: For DMA operations, this bit is automatically controlled by the
+// EIP-120t.
+// After reset, this bit is 0. After writing a context, this bit becomes 1.
+#define CRYPTO_AESCTL_INPUT_READY 0x00000002
+#define CRYPTO_AESCTL_INPUT_READY_BITN 1
+#define CRYPTO_AESCTL_INPUT_READY_M 0x00000002
+#define CRYPTO_AESCTL_INPUT_READY_S 1
+
+// Field: [0] OUTPUT_READY
+//
+// If 1, this status bit indicates that an AES output block is available to be
+// retrieved by the host.
+// Writing 0 clears the bit to 0 and indicates that output data is read by the
+// host. The AES core can provide a next output data block.
+// Writing 1 to this bit is ignored.
+// Note: For DMA operations, this bit is automatically controlled by the
+// EIP-120t.
+#define CRYPTO_AESCTL_OUTPUT_READY 0x00000001
+#define CRYPTO_AESCTL_OUTPUT_READY_BITN 0
+#define CRYPTO_AESCTL_OUTPUT_READY_M 0x00000001
+#define CRYPTO_AESCTL_OUTPUT_READY_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_AESDATALEN0
+//
+//*****************************************************************************
+// Field: [31:0] C_LENGTH
+//
+// C_LENGTH[31:0]
+// Bits [60:0] of the crypto length registers (LSW and MSW) store the
+// cryptographic data length in bytes for all modes. Once processing with this
+// context is started, this length decrements to 0. Data lengths up to (261: 1)
+// bytes are allowed.
+// For GCM, any value up to 236 - 32 bytes can be used. This is because a
+// 32-bit counter mode is used; the maximum number of 128-bit blocks is 232 -
+// 2, resulting in a maximum number of bytes of 236 - 32.
+// A write to this register triggers the engine to start using this context.
+// This is valid for all modes except GCM and CCM.
+// Note: For the combined modes (GCM and CCM), this length does not include the
+// authentication only data; the authentication length is specified in the
+// AESAUTHLEN register
+// All modes must have a length greater than 0. For the combined modes, it is
+// allowed to have one of the lengths equal to 0.
+// For the basic encryption modes (ECB, CBC, and CTR) it is allowed to program
+// zero to the length field; in that case the length is assumed infinite.
+// All data must be byte (8-bit) aligned for stream cipher modes; bit aligned
+// data streams are not supported by the EIP-120t. For block cipher modes, the
+// data length must be programmed in multiples of the block cipher size, 16
+// bytes.
+// For a host read operation, these registers return all-0s.
+#define CRYPTO_AESDATALEN0_C_LENGTH_W 32
+#define CRYPTO_AESDATALEN0_C_LENGTH_M 0xFFFFFFFF
+#define CRYPTO_AESDATALEN0_C_LENGTH_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_AESDATALEN1
+//
+//*****************************************************************************
+// Field: [28:0] C_LENGTH
+//
+// C_LENGTH[60:32]
+// Bits [60:0] of the crypto length registers (LSW and MSW) store the
+// cryptographic data length in bytes for all modes. Once processing with this
+// context is started, this length decrements to 0. Data lengths up to (261: 1)
+// bytes are allowed.
+// For GCM, any value up to 236 - 32 bytes can be used. This is because a
+// 32-bit counter mode is used; the maximum number of 128-bit blocks is 232 -
+// 2, resulting in a maximum number of bytes of 236 - 32.
+// A write to this register triggers the engine to start using this context.
+// This is valid for all modes except GCM and CCM.
+// Note: For the combined modes (GCM and CCM), this length does not include the
+// authentication only data; the authentication length is specified in the
+// AESAUTHLEN register
+// All modes must have a length greater than 0. For the combined modes, it is
+// allowed to have one of the lengths equal to 0.
+// For the basic encryption modes (ECB, CBC, and CTR) it is allowed to program
+// zero to the length field; in that case the length is assumed infinite.
+// All data must be byte (8-bit) aligned for stream cipher modes; bit aligned
+// data streams are not supported by the EIP-120t. For block cipher modes, the
+// data length must be programmed in multiples of the block cipher size, 16
+// bytes.
+// For a host read operation, these registers return all-0s.
+#define CRYPTO_AESDATALEN1_C_LENGTH_W 29
+#define CRYPTO_AESDATALEN1_C_LENGTH_M 0x1FFFFFFF
+#define CRYPTO_AESDATALEN1_C_LENGTH_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_AESAUTHLEN
+//
+//*****************************************************************************
+// Field: [31:0] AUTH_LENGTH
+//
+// Bits [31:0] of the authentication length register store the authentication
+// data length in bytes for combined modes only (GCM or CCM).
+// Supported AAD-lengths for CCM are from 0 to (2^16 - 2^8) bytes. For GCM any
+// value up to (2^32 - 1) bytes can be used. Once processing with this context
+// is started, this length decrements to 0.
+// A write to this register triggers the engine to start using this context for
+// GCM and CCM.
+// For a host read operation, these registers return all-0s.
+#define CRYPTO_AESAUTHLEN_AUTH_LENGTH_W 32
+#define CRYPTO_AESAUTHLEN_AUTH_LENGTH_M 0xFFFFFFFF
+#define CRYPTO_AESAUTHLEN_AUTH_LENGTH_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_AESDATAOUT0
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// Data register 0 for output block data from the Crypto peripheral.
+// These bits = AES Output Data[31:0] of {127:0]
+//
+// For normal operations, this register is not used, since data input and
+// output is transferred from and to the AES engine via DMA.
+//
+// For a Host read operation, these registers contain the 128-bit output block
+// from the latest AES operation. Reading from a word-aligned offset within
+// this address range will read one word (4 bytes) of data out the 4-word deep
+// (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one
+// full block) should be read before the core will move the next block to the
+// data output buffer. To empty the data output buffer, AESCTL.OUTPUT_READY
+// must be written.
+// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid
+// (message) bytes/words can be written with any data.
+//
+// Note: The AAD / authentication only data is not copied to the output buffer
+// but only used for authentication.
+#define CRYPTO_AESDATAOUT0_DATA_W 32
+#define CRYPTO_AESDATAOUT0_DATA_M 0xFFFFFFFF
+#define CRYPTO_AESDATAOUT0_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_AESDATAIN0
+//
+//*****************************************************************************
+// Field: [31:0] AES_DATA_IN_OUT
+//
+// AES input data[31:0] / AES output data[31:0]
+// Data registers for input/output block data to/from the EIP-120t.
+// For normal operations, this register is not used, since data input and
+// output is transferred from and to the AES core via DMA. For a host write
+// operation, these registers must be written with the 128-bit input block for
+// the next AES operation. Writing at a word-aligned offset within this address
+// range stores the word (4 bytes) of data into the corresponding position of
+// 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is
+// used for the next AES operation. If the last data block is not completely
+// filled with valid data (see notes below), it is allowed to write only the
+// words with valid data. Next AES operation is triggered by writing to the
+// input_ready flag of the AES_CTRL register.
+// For a host read operation, these registers contain the 128-bit output block
+// from the latest AES operation. Reading from a word-aligned offset within
+// this address range reads one word (4 bytes) of data out the 4-word deep (16
+// bytes = 128-bits AES block) data output buffer. The words (4 words, one full
+// block) should be read before the core will move the next block to the data
+// output buffer. To empty the data output buffer, the output_ready flag of the
+// AES_CTRL register must be written.
+// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid
+// (message) bytes/words can be written with any data.
+// Note: AES typically operates on 128 bits block multiple input data. The CTR,
+// GCM and CCM modes form an exception. The last block of a CTR-mode message
+// may contain less than 128 bits (refer to [NIST 800-38A]). For GCM/CCM, the
+// last block of both AAD and message data may contain less than 128 bits
+// (refer to [NIST 800-38D]). The EIP-120t automatically pads or masks
+// misaligned ending data blocks with 0s for GCM, CCM and CBC-MAC. For CTR
+// mode, the remaining data in an unaligned data block is ignored.
+// Note: The AAD / authentication only data is not copied to the output buffer
+// but only used for authentication.
+#define CRYPTO_AESDATAIN0_AES_DATA_IN_OUT_W 32
+#define CRYPTO_AESDATAIN0_AES_DATA_IN_OUT_M 0xFFFFFFFF
+#define CRYPTO_AESDATAIN0_AES_DATA_IN_OUT_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_AESDATAOUT1
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// Data register 0 for output block data from the Crypto peripheral.
+// These bits = AES Output Data[31:0] of {127:0]
+//
+// For normal operations, this register is not used, since data input and
+// output is transferred from and to the AES engine via DMA.
+//
+// For a Host read operation, these registers contain the 128-bit output block
+// from the latest AES operation. Reading from a word-aligned offset within
+// this address range will read one word (4 bytes) of data out the 4-word deep
+// (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one
+// full block) should be read before the core will move the next block to the
+// data output buffer. To empty the data output buffer, AESCTL.OUTPUT_READY
+// must be written.
+// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid
+// (message) bytes/words can be written with any data.
+//
+// Note: The AAD / authentication only data is not copied to the output buffer
+// but only used for authentication.
+#define CRYPTO_AESDATAOUT1_DATA_W 32
+#define CRYPTO_AESDATAOUT1_DATA_M 0xFFFFFFFF
+#define CRYPTO_AESDATAOUT1_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_AESDATAIN1
+//
+//*****************************************************************************
+// Field: [31:0] AES_DATA_IN_OUT
+//
+// AES input data[31:0] / AES output data[63:32]
+// Data registers for input/output block data to/from the EIP-120t.
+// For normal operations, this register is not used, since data input and
+// output is transferred from and to the AES core via DMA. For a host write
+// operation, these registers must be written with the 128-bit input block for
+// the next AES operation. Writing at a word-aligned offset within this address
+// range stores the word (4 bytes) of data into the corresponding position of
+// 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is
+// used for the next AES operation. If the last data block is not completely
+// filled with valid data (see notes below), it is allowed to write only the
+// words with valid data. Next AES operation is triggered by writing to the
+// input_ready flag of the AES_CTRL register.
+// For a host read operation, these registers contain the 128-bit output block
+// from the latest AES operation. Reading from a word-aligned offset within
+// this address range reads one word (4 bytes) of data out the 4-word deep (16
+// bytes = 128-bits AES block) data output buffer. The words (4 words, one full
+// block) should be read before the core will move the next block to the data
+// output buffer. To empty the data output buffer, the output_ready flag of the
+// AES_CTRL register must be written.
+// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid
+// (message) bytes/words can be written with any data.
+// Note: AES typically operates on 128 bits block multiple input data. The CTR,
+// GCM and CCM modes form an exception. The last block of a CTR-mode message
+// may contain less than 128 bits (refer to [NIST 800-38A]). For GCM/CCM, the
+// last block of both AAD and message data may contain less than 128 bits
+// (refer to [NIST 800-38D]). The EIP-120t automatically pads or masks
+// misaligned ending data blocks with 0s for GCM, CCM and CBC-MAC. For CTR
+// mode, the remaining data in an unaligned data block is ignored.
+// Note: The AAD / authentication only data is not copied to the output buffer
+// but only used for authentication.
+#define CRYPTO_AESDATAIN1_AES_DATA_IN_OUT_W 32
+#define CRYPTO_AESDATAIN1_AES_DATA_IN_OUT_M 0xFFFFFFFF
+#define CRYPTO_AESDATAIN1_AES_DATA_IN_OUT_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_AESDATAOUT2
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// Data register 0 for output block data from the Crypto peripheral.
+// These bits = AES Output Data[31:0] of {127:0]
+//
+// For normal operations, this register is not used, since data input and
+// output is transferred from and to the AES engine via DMA.
+//
+// For a Host read operation, these registers contain the 128-bit output block
+// from the latest AES operation. Reading from a word-aligned offset within
+// this address range will read one word (4 bytes) of data out the 4-word deep
+// (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one
+// full block) should be read before the core will move the next block to the
+// data output buffer. To empty the data output buffer, AESCTL.OUTPUT_READY
+// must be written.
+// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid
+// (message) bytes/words can be written with any data.
+//
+// Note: The AAD / authentication only data is not copied to the output buffer
+// but only used for authentication.
+#define CRYPTO_AESDATAOUT2_DATA_W 32
+#define CRYPTO_AESDATAOUT2_DATA_M 0xFFFFFFFF
+#define CRYPTO_AESDATAOUT2_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_AESDATAIN2
+//
+//*****************************************************************************
+// Field: [31:0] AES_DATA_IN_OUT
+//
+// AES input data[95:64] / AES output data[95:64]
+// Data registers for input/output block data to/from the EIP-120t.
+// For normal operations, this register is not used, since data input and
+// output is transferred from and to the AES core via DMA. For a host write
+// operation, these registers must be written with the 128-bit input block for
+// the next AES operation. Writing at a word-aligned offset within this address
+// range stores the word (4 bytes) of data into the corresponding position of
+// 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is
+// used for the next AES operation. If the last data block is not completely
+// filled with valid data (see notes below), it is allowed to write only the
+// words with valid data. Next AES operation is triggered by writing to the
+// input_ready flag of the AES_CTRL register.
+// For a host read operation, these registers contain the 128-bit output block
+// from the latest AES operation. Reading from a word-aligned offset within
+// this address range reads one word (4 bytes) of data out the 4-word deep (16
+// bytes = 128-bits AES block) data output buffer. The words (4 words, one full
+// block) should be read before the core will move the next block to the data
+// output buffer. To empty the data output buffer, the output_ready flag of the
+// AES_CTRL register must be written.
+// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid
+// (message) bytes/words can be written with any data.
+// Note: AES typically operates on 128 bits block multiple input data. The CTR,
+// GCM and CCM modes form an exception. The last block of a CTR-mode message
+// may contain less than 128 bits (refer to [NIST 800-38A]). For GCM/CCM, the
+// last block of both AAD and message data may contain less than 128 bits
+// (refer to [NIST 800-38D]). The EIP-120t automatically pads or masks
+// misaligned ending data blocks with 0s for GCM, CCM and CBC-MAC. For CTR
+// mode, the remaining data in an unaligned data block is ignored.
+// Note: The AAD / authentication only data is not copied to the output buffer
+// but only used for authentication.
+#define CRYPTO_AESDATAIN2_AES_DATA_IN_OUT_W 32
+#define CRYPTO_AESDATAIN2_AES_DATA_IN_OUT_M 0xFFFFFFFF
+#define CRYPTO_AESDATAIN2_AES_DATA_IN_OUT_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_AESDATAOUT3
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// Data register 0 for output block data from the Crypto peripheral.
+// These bits = AES Output Data[31:0] of {127:0]
+//
+// For normal operations, this register is not used, since data input and
+// output is transferred from and to the AES engine via DMA.
+//
+// For a Host read operation, these registers contain the 128-bit output block
+// from the latest AES operation. Reading from a word-aligned offset within
+// this address range will read one word (4 bytes) of data out the 4-word deep
+// (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one
+// full block) should be read before the core will move the next block to the
+// data output buffer. To empty the data output buffer, AESCTL.OUTPUT_READY
+// must be written.
+// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid
+// (message) bytes/words can be written with any data.
+//
+// Note: The AAD / authentication only data is not copied to the output buffer
+// but only used for authentication.
+#define CRYPTO_AESDATAOUT3_DATA_W 32
+#define CRYPTO_AESDATAOUT3_DATA_M 0xFFFFFFFF
+#define CRYPTO_AESDATAOUT3_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_AESDATAIN3
+//
+//*****************************************************************************
+// Field: [31:0] AES_DATA_IN_OUT
+//
+// AES input data[127:96] / AES output data[127:96]
+// Data registers for input/output block data to/from the EIP-120t.
+// For normal operations, this register is not used, since data input and
+// output is transferred from and to the AES core via DMA. For a host write
+// operation, these registers must be written with the 128-bit input block for
+// the next AES operation. Writing at a word-aligned offset within this address
+// range stores the word (4 bytes) of data into the corresponding position of
+// 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is
+// used for the next AES operation. If the last data block is not completely
+// filled with valid data (see notes below), it is allowed to write only the
+// words with valid data. Next AES operation is triggered by writing to the
+// input_ready flag of the AES_CTRL register.
+// For a host read operation, these registers contain the 128-bit output block
+// from the latest AES operation. Reading from a word-aligned offset within
+// this address range reads one word (4 bytes) of data out the 4-word deep (16
+// bytes = 128-bits AES block) data output buffer. The words (4 words, one full
+// block) should be read before the core will move the next block to the data
+// output buffer. To empty the data output buffer, the output_ready flag of the
+// AES_CTRL register must be written.
+// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid
+// (message) bytes/words can be written with any data.
+// Note: AES typically operates on 128 bits block multiple input data. The CTR,
+// GCM and CCM modes form an exception. The last block of a CTR-mode message
+// may contain less than 128 bits (refer to [NIST 800-38A]). For GCM/CCM, the
+// last block of both AAD and message data may contain less than 128 bits
+// (refer to [NIST 800-38D]). The EIP-120t automatically pads or masks
+// misaligned ending data blocks with 0s for GCM, CCM and CBC-MAC. For CTR
+// mode, the remaining data in an unaligned data block is ignored.
+// Note: The AAD / authentication only data is not copied to the output buffer
+// but only used for authentication.
+#define CRYPTO_AESDATAIN3_AES_DATA_IN_OUT_W 32
+#define CRYPTO_AESDATAIN3_AES_DATA_IN_OUT_M 0xFFFFFFFF
+#define CRYPTO_AESDATAIN3_AES_DATA_IN_OUT_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_AESTAGOUT0
+//
+//*****************************************************************************
+// Field: [31:0] AES_TAG
+//
+// AES_TAG[31:0]
+// Bits [31:0] of this register stores the authentication value for the
+// combined and authentication only modes.
+// For a host read operation, these registers contain the last 128-bit TAG
+// output of the EIP-120t; the TAG is available until the next context is
+// written.
+// This register will only contain valid data if the TAG is available and when
+// the AESCTL.SAVED_CONTEXT_RDY register is set. During processing or for
+// operations/modes that do not return a TAG, reads from this register return
+// data from the IV register.
+#define CRYPTO_AESTAGOUT0_AES_TAG_W 32
+#define CRYPTO_AESTAGOUT0_AES_TAG_M 0xFFFFFFFF
+#define CRYPTO_AESTAGOUT0_AES_TAG_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_AESTAGOUT1
+//
+//*****************************************************************************
+// Field: [31:0] AES_TAG
+//
+// AES_TAG[31:0]
+// Bits [31:0] of this register stores the authentication value for the
+// combined and authentication only modes.
+// For a host read operation, these registers contain the last 128-bit TAG
+// output of the EIP-120t; the TAG is available until the next context is
+// written.
+// This register will only contain valid data if the TAG is available and when
+// the AESCTL.SAVED_CONTEXT_RDY register is set. During processing or for
+// operations/modes that do not return a TAG, reads from this register return
+// data from the IV register.
+#define CRYPTO_AESTAGOUT1_AES_TAG_W 32
+#define CRYPTO_AESTAGOUT1_AES_TAG_M 0xFFFFFFFF
+#define CRYPTO_AESTAGOUT1_AES_TAG_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_AESTAGOUT2
+//
+//*****************************************************************************
+// Field: [31:0] AES_TAG
+//
+// AES_TAG[31:0]
+// Bits [31:0] of this register stores the authentication value for the
+// combined and authentication only modes.
+// For a host read operation, these registers contain the last 128-bit TAG
+// output of the EIP-120t; the TAG is available until the next context is
+// written.
+// This register will only contain valid data if the TAG is available and when
+// the AESCTL.SAVED_CONTEXT_RDY register is set. During processing or for
+// operations/modes that do not return a TAG, reads from this register return
+// data from the IV register.
+#define CRYPTO_AESTAGOUT2_AES_TAG_W 32
+#define CRYPTO_AESTAGOUT2_AES_TAG_M 0xFFFFFFFF
+#define CRYPTO_AESTAGOUT2_AES_TAG_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_AESTAGOUT3
+//
+//*****************************************************************************
+// Field: [31:0] AES_TAG
+//
+// AES_TAG[31:0]
+// Bits [31:0] of this register stores the authentication value for the
+// combined and authentication only modes.
+// For a host read operation, these registers contain the last 128-bit TAG
+// output of the EIP-120t; the TAG is available until the next context is
+// written.
+// This register will only contain valid data if the TAG is available and when
+// the AESCTL.SAVED_CONTEXT_RDY register is set. During processing or for
+// operations/modes that do not return a TAG, reads from this register return
+// data from the IV register.
+#define CRYPTO_AESTAGOUT3_AES_TAG_W 32
+#define CRYPTO_AESTAGOUT3_AES_TAG_M 0xFFFFFFFF
+#define CRYPTO_AESTAGOUT3_AES_TAG_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDATAIN1
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DATA_IN
+//
+// HASH_DATA_IN[63:32]
+// These registers must be written with the 512-bit input data. The data lines
+// are connected directly to the data input of the hash module and hence into
+// the engine's internal data buffer. Writing to each of the registers triggers
+// a corresponding 32-bit write enable to the internal buffer.
+// Note: The host may only write the input data buffer when
+// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is
+// busy with processing. During processing, it is not allowed to write new
+// input data.
+// For message lengths larger than 64 bytes, multiple blocks of data are
+// written to this input buffer using a handshake through flags of the
+// HASHIOBUFCTRL register. All blocks except the last are required to be 512
+// bits in size. If the last block is not 512 bits long, only the least
+// significant bits of data must be written, but they must be padded with 0s to
+// the next 32-bit boundary.
+// Host read operations from these register addresses return 0s.
+#define CRYPTO_HASHDATAIN1_HASH_DATA_IN_W 32
+#define CRYPTO_HASHDATAIN1_HASH_DATA_IN_M 0xFFFFFFFF
+#define CRYPTO_HASHDATAIN1_HASH_DATA_IN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDATAIN2
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DATA_IN
+//
+// HASH_DATA_IN[95:64]
+// These registers must be written with the 512-bit input data. The data lines
+// are connected directly to the data input of the hash module and hence into
+// the engine's internal data buffer. Writing to each of the registers triggers
+// a corresponding 32-bit write enable to the internal buffer.
+// Note: The host may only write the input data buffer when
+// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is
+// busy with processing. During processing, it is not allowed to write new
+// input data.
+// For message lengths larger than 64 bytes, multiple blocks of data are
+// written to this input buffer using a handshake through flags of the
+// HASHIOBUFCTRL register. All blocks except the last are required to be 512
+// bits in size. If the last block is not 512 bits long, only the least
+// significant bits of data must be written, but they must be padded with 0s to
+// the next 32-bit boundary.
+// Host read operations from these register addresses return 0s.
+#define CRYPTO_HASHDATAIN2_HASH_DATA_IN_W 32
+#define CRYPTO_HASHDATAIN2_HASH_DATA_IN_M 0xFFFFFFFF
+#define CRYPTO_HASHDATAIN2_HASH_DATA_IN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDATAIN3
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DATA_IN
+//
+// HASH_DATA_IN[127:96]
+// These registers must be written with the 512-bit input data. The data lines
+// are connected directly to the data input of the hash module and hence into
+// the engine's internal data buffer. Writing to each of the registers triggers
+// a corresponding 32-bit write enable to the internal buffer.
+// Note: The host may only write the input data buffer when the rfd_in bit of
+// the HASH_IO_BUF_CTRL register is high. If the rfd_in bit is 0, the engine is
+// busy with processing. During processing, it is not allowed to write new
+// input data.
+// For message lengths larger than 64 bytes, multiple blocks of data are
+// written to this input buffer using a handshake through flags of the
+// HASH_IO_BUF_CTRL register. All blocks except the last are required to be 512
+// bits in size. If the last block is not 512 bits long, only the least
+// significant bits of data must be written, but they must be padded with 0s to
+// the next 32-bit boundary.
+// Host read operations from these register addresses return 0s.
+#define CRYPTO_HASHDATAIN3_HASH_DATA_IN_W 32
+#define CRYPTO_HASHDATAIN3_HASH_DATA_IN_M 0xFFFFFFFF
+#define CRYPTO_HASHDATAIN3_HASH_DATA_IN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDATAIN4
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DATA_IN
+//
+// HASH_DATA_IN[159:128]
+// These registers must be written with the 512-bit input data. The data lines
+// are connected directly to the data input of the hash module and hence into
+// the engine's internal data buffer. Writing to each of the registers triggers
+// a corresponding 32-bit write enable to the internal buffer.
+// Note: The host may only write the input data buffer when
+// HASHIOBUFCTRL.RFD_IN is '1'. If the HASHIOBUFCTRL.RFD_IN is 0, the engine
+// is busy with processing. During processing, it is not allowed to write new
+// input data.
+// For message lengths larger than 64 bytes, multiple blocks of data are
+// written to this input buffer using a handshake through flags of the
+// HASHIOBUFCTRL register. All blocks except the last are required to be 512
+// bits in size. If the last block is not 512 bits long, only the least
+// significant bits of data must be written, but they must be padded with 0s to
+// the next 32-bit boundary.
+// Host read operations from these register addresses return 0s.
+#define CRYPTO_HASHDATAIN4_HASH_DATA_IN_W 32
+#define CRYPTO_HASHDATAIN4_HASH_DATA_IN_M 0xFFFFFFFF
+#define CRYPTO_HASHDATAIN4_HASH_DATA_IN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDATAIN5
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DATA_IN
+//
+// HASH_DATA_IN[191:160]
+// These registers must be written with the 512-bit input data. The data lines
+// are connected directly to the data input of the hash module and hence into
+// the engine's internal data buffer. Writing to each of the registers triggers
+// a corresponding 32-bit write enable to the internal buffer.
+// Note: The host may only write the input data buffer when
+// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine
+// is busy with processing. During processing, it is not allowed to write new
+// input data.
+// For message lengths larger than 64 bytes, multiple blocks of data are
+// written to this input buffer using a handshake through flags of the
+// HASHIOBUFCTRL register. All blocks except the last are required to be 512
+// bits in size. If the last block is not 512 bits long, only the least
+// significant bits of data must be written, but they must be padded with 0s to
+// the next 32-bit boundary.
+// Host read operations from these register addresses return 0s.
+#define CRYPTO_HASHDATAIN5_HASH_DATA_IN_W 32
+#define CRYPTO_HASHDATAIN5_HASH_DATA_IN_M 0xFFFFFFFF
+#define CRYPTO_HASHDATAIN5_HASH_DATA_IN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDATAIN6
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DATA_IN
+//
+// HASH_DATA_IN[223:192]
+// These registers must be written with the 512-bit input data. The data lines
+// are connected directly to the data input of the hash module and hence into
+// the engine's internal data buffer. Writing to each of the registers triggers
+// a corresponding 32-bit write enable to the internal buffer.
+// Note: The host may only write the input data buffer when
+// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine
+// is busy with processing. During processing, it is not allowed to write new
+// input data.
+// For message lengths larger than 64 bytes, multiple blocks of data are
+// written to this input buffer using a handshake through flags of the
+// HASHIOBUFCTRL register. All blocks except the last are required to be 512
+// bits in size. If the last block is not 512 bits long, only the least
+// significant bits of data must be written, but they must be padded with 0s to
+// the next 32-bit boundary.
+// Host read operations from these register addresses return 0s.
+#define CRYPTO_HASHDATAIN6_HASH_DATA_IN_W 32
+#define CRYPTO_HASHDATAIN6_HASH_DATA_IN_M 0xFFFFFFFF
+#define CRYPTO_HASHDATAIN6_HASH_DATA_IN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDATAIN7
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DATA_IN
+//
+// HASH_DATA_IN[255:224]
+// These registers must be written with the 512-bit input data. The data lines
+// are connected directly to the data input of the hash module and hence into
+// the engine's internal data buffer. Writing to each of the registers triggers
+// a corresponding 32-bit write enable to the internal buffer.
+// Note: The host may only write the input data buffer when
+// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine
+// is busy with processing. During processing, it is not allowed to write new
+// input data.
+// For message lengths larger than 64 bytes, multiple blocks of data are
+// written to this input buffer using a handshake through flags of the
+// HASHIOBUFCTRL register. All blocks except the last are required to be 512
+// bits in size. If the last block is not 512 bits long, only the least
+// significant bits of data must be written, but they must be padded with 0s to
+// the next 32-bit boundary.
+// Host read operations from these register addresses return 0s.
+#define CRYPTO_HASHDATAIN7_HASH_DATA_IN_W 32
+#define CRYPTO_HASHDATAIN7_HASH_DATA_IN_M 0xFFFFFFFF
+#define CRYPTO_HASHDATAIN7_HASH_DATA_IN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDATAIN8
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DATA_IN
+//
+// HASH_DATA_IN[287:256]
+// These registers must be written with the 512-bit input data. The data lines
+// are connected directly to the data input of the hash module and hence into
+// the engine's internal data buffer. Writing to each of the registers triggers
+// a corresponding 32-bit write enable to the internal buffer.
+// Note: The host may only write the input data buffer when
+// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine
+// is busy with processing. During processing, it is not allowed to write new
+// input data.
+// For message lengths larger than 64 bytes, multiple blocks of data are
+// written to this input buffer using a handshake through flags of the
+// HASHIOBUFCTRL register. All blocks except the last are required to be 512
+// bits in size. If the last block is not 512 bits long, only the least
+// significant bits of data must be written, but they must be padded with 0s to
+// the next 32-bit boundary.
+// Host read operations from these register addresses return 0s.
+#define CRYPTO_HASHDATAIN8_HASH_DATA_IN_W 32
+#define CRYPTO_HASHDATAIN8_HASH_DATA_IN_M 0xFFFFFFFF
+#define CRYPTO_HASHDATAIN8_HASH_DATA_IN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDATAIN9
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DATA_IN
+//
+// HASH_DATA_IN[319:288]
+// These registers must be written with the 512-bit input data. The data lines
+// are connected directly to the data input of the hash module and hence into
+// the engine's internal data buffer. Writing to each of the registers triggers
+// a corresponding 32-bit write enable to the internal buffer.
+// Note: The host may only write the input data buffer when
+// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine
+// is busy with processing. During processing, it is not allowed to write new
+// input data.
+// For message lengths larger than 64 bytes, multiple blocks of data are
+// written to this input buffer using a handshake through flags of the
+// HASHIOBUFCTRL register. All blocks except the last are required to be 512
+// bits in size. If the last block is not 512 bits long, only the least
+// significant bits of data must be written, but they must be padded with 0s to
+// the next 32-bit boundary.
+// Host read operations from these register addresses return 0s.
+#define CRYPTO_HASHDATAIN9_HASH_DATA_IN_W 32
+#define CRYPTO_HASHDATAIN9_HASH_DATA_IN_M 0xFFFFFFFF
+#define CRYPTO_HASHDATAIN9_HASH_DATA_IN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDATAIN10
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DATA_IN
+//
+// HASH_DATA_IN[351:320]
+// These registers must be written with the 512-bit input data. The data lines
+// are connected directly to the data input of the hash module and hence into
+// the engine's internal data buffer. Writing to each of the registers triggers
+// a corresponding 32-bit write enable to the internal buffer.
+// Note: The host may only write the input data buffer when
+// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine
+// is busy with processing. During processing, it is not allowed to write new
+// input data.
+// For message lengths larger than 64 bytes, multiple blocks of data are
+// written to this input buffer using a handshake through flags of the
+// HASHIOBUFCTRL register. All blocks except the last are required to be 512
+// bits in size. If the last block is not 512 bits long, only the least
+// significant bits of data must be written, but they must be padded with 0s to
+// the next 32-bit boundary.
+// Host read operations from these register addresses return 0s.
+#define CRYPTO_HASHDATAIN10_HASH_DATA_IN_W 32
+#define CRYPTO_HASHDATAIN10_HASH_DATA_IN_M 0xFFFFFFFF
+#define CRYPTO_HASHDATAIN10_HASH_DATA_IN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDATAIN11
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DATA_IN
+//
+// HASH_DATA_IN[383:352]
+// These registers must be written with the 512-bit input data. The data lines
+// are connected directly to the data input of the hash module and hence into
+// the engine's internal data buffer. Writing to each of the registers triggers
+// a corresponding 32-bit write enable to the internal buffer.
+// Note: The host may only write the input data buffer when
+// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine
+// is busy with processing. During processing, it is not allowed to write new
+// input data.
+// For message lengths larger than 64 bytes, multiple blocks of data are
+// written to this input buffer using a handshake through flags of the
+// HASHIOBUFCTRL register. All blocks except the last are required to be 512
+// bits in size. If the last block is not 512 bits long, only the least
+// significant bits of data must be written, but they must be padded with 0s to
+// the next 32-bit boundary.
+// Host read operations from these register addresses return 0s.
+#define CRYPTO_HASHDATAIN11_HASH_DATA_IN_W 32
+#define CRYPTO_HASHDATAIN11_HASH_DATA_IN_M 0xFFFFFFFF
+#define CRYPTO_HASHDATAIN11_HASH_DATA_IN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDATAIN12
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DATA_IN
+//
+// HASH_DATA_IN[415:384]
+// These registers must be written with the 512-bit input data. The data lines
+// are connected directly to the data input of the hash module and hence into
+// the engine's internal data buffer. Writing to each of the registers triggers
+// a corresponding 32-bit write enable to the internal buffer.
+// Note: The host may only write the input data buffer when
+// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine
+// is busy with processing. During processing, it is not allowed to write new
+// input data.
+// For message lengths larger than 64 bytes, multiple blocks of data are
+// written to this input buffer using a handshake through flags of the
+// HASHIOBUFCTRL register. All blocks except the last are required to be 512
+// bits in size. If the last block is not 512 bits long, only the least
+// significant bits of data must be written, but they must be padded with 0s to
+// the next 32-bit boundary.
+// Host read operations from these register addresses return 0s.
+#define CRYPTO_HASHDATAIN12_HASH_DATA_IN_W 32
+#define CRYPTO_HASHDATAIN12_HASH_DATA_IN_M 0xFFFFFFFF
+#define CRYPTO_HASHDATAIN12_HASH_DATA_IN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDATAIN13
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DATA_IN
+//
+// HASH_DATA_IN[447:416]
+// These registers must be written with the 512-bit input data. The data lines
+// are connected directly to the data input of the hash module and hence into
+// the engine's internal data buffer. Writing to each of the registers triggers
+// a corresponding 32-bit write enable to the internal buffer.
+// Note: The host may only write the input data buffer when
+// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine
+// is busy with processing. During processing, it is not allowed to write new
+// input data.
+// For message lengths larger than 64 bytes, multiple blocks of data are
+// written to this input buffer using a handshake through flags of the
+// HASHIOBUFCTRL register. All blocks except the last are required to be 512
+// bits in size. If the last block is not 512 bits long, only the least
+// significant bits of data must be written, but they must be padded with 0s to
+// the next 32-bit boundary.
+// Host read operations from these register addresses return 0s.
+#define CRYPTO_HASHDATAIN13_HASH_DATA_IN_W 32
+#define CRYPTO_HASHDATAIN13_HASH_DATA_IN_M 0xFFFFFFFF
+#define CRYPTO_HASHDATAIN13_HASH_DATA_IN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDATAIN14
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DATA_IN
+//
+// HASH_DATA_IN[479:448]
+// These registers must be written with the 512-bit input data. The data lines
+// are connected directly to the data input of the hash module and hence into
+// the engine's internal data buffer. Writing to each of the registers triggers
+// a corresponding 32-bit write enable to the internal buffer.
+// Note: The host may only write the input data buffer when
+// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine
+// is busy with processing. During processing, it is not allowed to write new
+// input data.
+// For message lengths larger than 64 bytes, multiple blocks of data are
+// written to this input buffer using a handshake through flags of the
+// HASHIOBUFCTRL register. All blocks except the last are required to be 512
+// bits in size. If the last block is not 512 bits long, only the least
+// significant bits of data must be written, but they must be padded with 0s to
+// the next 32-bit boundary.
+// Host read operations from these register addresses return 0s.
+#define CRYPTO_HASHDATAIN14_HASH_DATA_IN_W 32
+#define CRYPTO_HASHDATAIN14_HASH_DATA_IN_M 0xFFFFFFFF
+#define CRYPTO_HASHDATAIN14_HASH_DATA_IN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDATAIN15
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DATA_IN
+//
+// HASH_DATA_IN[511:480]
+// These registers must be written with the 512-bit input data. The data lines
+// are connected directly to the data input of the hash module and hence into
+// the engine's internal data buffer. Writing to each of the registers triggers
+// a corresponding 32-bit write enable to the internal buffer.
+// Note: The host may only write the input data buffer when
+// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine
+// is busy with processing. During processing, it is not allowed to write new
+// input data.
+// For message lengths larger than 64 bytes, multiple blocks of data are
+// written to this input buffer using a handshake through flags of the
+// HASHIOBUFCTRL register. All blocks except the last are required to be 512
+// bits in size. If the last block is not 512 bits long, only the least
+// significant bits of data must be written, but they must be padded with 0s to
+// the next 32-bit boundary.
+// Host read operations from these register addresses return 0s.
+#define CRYPTO_HASHDATAIN15_HASH_DATA_IN_W 32
+#define CRYPTO_HASHDATAIN15_HASH_DATA_IN_M 0xFFFFFFFF
+#define CRYPTO_HASHDATAIN15_HASH_DATA_IN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDATAIN16
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DATA_IN
+//
+// HASH_DATA_IN[543:512]
+// These registers must be written with the 512-bit input data. The data lines
+// are connected directly to the data input of the hash module and hence into
+// the engine's internal data buffer. Writing to each of the registers triggers
+// a corresponding 32-bit write enable to the internal buffer.
+// Note: The host may only write the input data buffer when
+// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine
+// is busy with processing. During processing, it is not allowed to write new
+// input data.
+// For message lengths larger than 64 bytes, multiple blocks of data are
+// written to this input buffer using a handshake through flags of the
+// HASHIOBUFCTRL register. All blocks except the last are required to be 512
+// bits in size. If the last block is not 512 bits long, only the least
+// significant bits of data must be written, but they must be padded with 0s to
+// the next 32-bit boundary.
+// Host read operations from these register addresses return 0s.
+#define CRYPTO_HASHDATAIN16_HASH_DATA_IN_W 32
+#define CRYPTO_HASHDATAIN16_HASH_DATA_IN_M 0xFFFFFFFF
+#define CRYPTO_HASHDATAIN16_HASH_DATA_IN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDATAIN17
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DATA_IN
+//
+// HASH_DATA_IN[575:544]
+// These registers must be written with the 512-bit input data. The data lines
+// are connected directly to the data input of the hash module and hence into
+// the engine's internal data buffer. Writing to each of the registers triggers
+// a corresponding 32-bit write enable to the internal buffer.
+// Note: The host may only write the input data buffer when
+// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine
+// is busy with processing. During processing, it is not allowed to write new
+// input data.
+// For message lengths larger than 64 bytes, multiple blocks of data are
+// written to this input buffer using a handshake through flags of the
+// HASHIOBUFCTRL register. All blocks except the last are required to be 512
+// bits in size. If the last block is not 512 bits long, only the least
+// significant bits of data must be written, but they must be padded with 0s to
+// the next 32-bit boundary.
+// Host read operations from these register addresses return 0s.
+#define CRYPTO_HASHDATAIN17_HASH_DATA_IN_W 32
+#define CRYPTO_HASHDATAIN17_HASH_DATA_IN_M 0xFFFFFFFF
+#define CRYPTO_HASHDATAIN17_HASH_DATA_IN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDATAIN18
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DATA_IN
+//
+// HASH_DATA_IN[607:576]
+// These registers must be written with the 512-bit input data. The data lines
+// are connected directly to the data input of the hash module and hence into
+// the engine's internal data buffer. Writing to each of the registers triggers
+// a corresponding 32-bit write enable to the internal buffer.
+// Note: The host may only write the input data buffer when
+// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine
+// is busy with processing. During processing, it is not allowed to write new
+// input data.
+// For message lengths larger than 64 bytes, multiple blocks of data are
+// written to this input buffer using a handshake through flags of the
+// HASHIOBUFCTRL register. All blocks except the last are required to be 512
+// bits in size. If the last block is not 512 bits long, only the least
+// significant bits of data must be written, but they must be padded with 0s to
+// the next 32-bit boundary.
+// Host read operations from these register addresses return 0s.
+#define CRYPTO_HASHDATAIN18_HASH_DATA_IN_W 32
+#define CRYPTO_HASHDATAIN18_HASH_DATA_IN_M 0xFFFFFFFF
+#define CRYPTO_HASHDATAIN18_HASH_DATA_IN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDATAIN19
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DATA_IN
+//
+// HASH_DATA_IN[639:608]
+// These registers must be written with the 512-bit input data. The data lines
+// are connected directly to the data input of the hash module and hence into
+// the engine's internal data buffer. Writing to each of the registers triggers
+// a corresponding 32-bit write enable to the internal buffer.
+// Note: The host may only write the input data buffer when
+// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine
+// is busy with processing. During processing, it is not allowed to write new
+// input data.
+// For message lengths larger than 64 bytes, multiple blocks of data are
+// written to this input buffer using a handshake through flags of the
+// HASHIOBUFCTRL register. All blocks except the last are required to be 512
+// bits in size. If the last block is not 512 bits long, only the least
+// significant bits of data must be written, but they must be padded with 0s to
+// the next 32-bit boundary.
+// Host read operations from these register addresses return 0s.
+#define CRYPTO_HASHDATAIN19_HASH_DATA_IN_W 32
+#define CRYPTO_HASHDATAIN19_HASH_DATA_IN_M 0xFFFFFFFF
+#define CRYPTO_HASHDATAIN19_HASH_DATA_IN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDATAIN20
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DATA_IN
+//
+// HASH_DATA_IN[671:640]
+// These registers must be written with the 512-bit input data. The data lines
+// are connected directly to the data input of the hash module and hence into
+// the engine's internal data buffer. Writing to each of the registers triggers
+// a corresponding 32-bit write enable to the internal buffer.
+// Note: The host may only write the input data buffer when
+// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine
+// is busy with processing. During processing, it is not allowed to write new
+// input data.
+// For message lengths larger than 64 bytes, multiple blocks of data are
+// written to this input buffer using a handshake through flags of the
+// HASHIOBUFCTRL register. All blocks except the last are required to be 512
+// bits in size. If the last block is not 512 bits long, only the least
+// significant bits of data must be written, but they must be padded with 0s to
+// the next 32-bit boundary.
+// Host read operations from these register addresses return 0s.
+#define CRYPTO_HASHDATAIN20_HASH_DATA_IN_W 32
+#define CRYPTO_HASHDATAIN20_HASH_DATA_IN_M 0xFFFFFFFF
+#define CRYPTO_HASHDATAIN20_HASH_DATA_IN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDATAIN21
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DATA_IN
+//
+// HASH_DATA_IN[703:672]
+// These registers must be written with the 512-bit input data. The data lines
+// are connected directly to the data input of the hash module and hence into
+// the engine's internal data buffer. Writing to each of the registers triggers
+// a corresponding 32-bit write enable to the internal buffer.
+// Note: The host may only write the input data buffer when
+// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine
+// is busy with processing. During processing, it is not allowed to write new
+// input data.
+// For message lengths larger than 64 bytes, multiple blocks of data are
+// written to this input buffer using a handshake through flags of the
+// HASHIOBUFCTRL register. All blocks except the last are required to be 512
+// bits in size. If the last block is not 512 bits long, only the least
+// significant bits of data must be written, but they must be padded with 0s to
+// the next 32-bit boundary.
+// Host read operations from these register addresses return 0s.
+#define CRYPTO_HASHDATAIN21_HASH_DATA_IN_W 32
+#define CRYPTO_HASHDATAIN21_HASH_DATA_IN_M 0xFFFFFFFF
+#define CRYPTO_HASHDATAIN21_HASH_DATA_IN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDATAIN22
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DATA_IN
+//
+// HASH_DATA_IN[735:704]
+// These registers must be written with the 512-bit input data. The data lines
+// are connected directly to the data input of the hash module and hence into
+// the engine's internal data buffer. Writing to each of the registers triggers
+// a corresponding 32-bit write enable to the internal buffer.
+// Note: The host may only write the input data buffer when
+// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine
+// is busy with processing. During processing, it is not allowed to write new
+// input data.
+// For message lengths larger than 64 bytes, multiple blocks of data are
+// written to this input buffer using a handshake through flags of the
+// HASHIOBUFCTRL register. All blocks except the last are required to be 512
+// bits in size. If the last block is not 512 bits long, only the least
+// significant bits of data must be written, but they must be padded with 0s to
+// the next 32-bit boundary.
+// Host read operations from these register addresses return 0s.
+#define CRYPTO_HASHDATAIN22_HASH_DATA_IN_W 32
+#define CRYPTO_HASHDATAIN22_HASH_DATA_IN_M 0xFFFFFFFF
+#define CRYPTO_HASHDATAIN22_HASH_DATA_IN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDATAIN23
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DATA_IN
+//
+// HASH_DATA_IN[767:736]
+// These registers must be written with the 512-bit input data. The data lines
+// are connected directly to the data input of the hash module and hence into
+// the engine's internal data buffer. Writing to each of the registers triggers
+// a corresponding 32-bit write enable to the internal buffer.
+// Note: The host may only write the input data buffer when
+// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine
+// is busy with processing. During processing, it is not allowed to write new
+// input data.
+// For message lengths larger than 64 bytes, multiple blocks of data are
+// written to this input buffer using a handshake through flags of the
+// HASHIOBUFCTRL register. All blocks except the last are required to be 512
+// bits in size. If the last block is not 512 bits long, only the least
+// significant bits of data must be written, but they must be padded with 0s to
+// the next 32-bit boundary.
+// Host read operations from these register addresses return 0s.
+#define CRYPTO_HASHDATAIN23_HASH_DATA_IN_W 32
+#define CRYPTO_HASHDATAIN23_HASH_DATA_IN_M 0xFFFFFFFF
+#define CRYPTO_HASHDATAIN23_HASH_DATA_IN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDATAIN24
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DATA_IN
+//
+// HASH_DATA_IN[799:768]
+// These registers must be written with the 512-bit input data. The data lines
+// are connected directly to the data input of the hash module and hence into
+// the engine's internal data buffer. Writing to each of the registers triggers
+// a corresponding 32-bit write enable to the internal buffer.
+// Note: The host may only write the input data buffer when
+// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine
+// is busy with processing. During processing, it is not allowed to write new
+// input data.
+// For message lengths larger than 64 bytes, multiple blocks of data are
+// written to this input buffer using a handshake through flags of the
+// HASHIOBUFCTRL register. All blocks except the last are required to be 512
+// bits in size. If the last block is not 512 bits long, only the least
+// significant bits of data must be written, but they must be padded with 0s to
+// the next 32-bit boundary.
+// Host read operations from these register addresses return 0s.
+#define CRYPTO_HASHDATAIN24_HASH_DATA_IN_W 32
+#define CRYPTO_HASHDATAIN24_HASH_DATA_IN_M 0xFFFFFFFF
+#define CRYPTO_HASHDATAIN24_HASH_DATA_IN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDATAIN25
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DATA_IN
+//
+// HASH_DATA_IN[831:800]
+// These registers must be written with the 512-bit input data. The data lines
+// are connected directly to the data input of the hash module and hence into
+// the engine's internal data buffer. Writing to each of the registers triggers
+// a corresponding 32-bit write enable to the internal buffer.
+// Note: The host may only write the input data buffer when
+// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine
+// is busy with processing. During processing, it is not allowed to write new
+// input data.
+// For message lengths larger than 64 bytes, multiple blocks of data are
+// written to this input buffer using a handshake through flags of the
+// HASHIOBUFCTRL register. All blocks except the last are required to be 512
+// bits in size. If the last block is not 512 bits long, only the least
+// significant bits of data must be written, but they must be padded with 0s to
+// the next 32-bit boundary.
+// Host read operations from these register addresses return 0s.
+#define CRYPTO_HASHDATAIN25_HASH_DATA_IN_W 32
+#define CRYPTO_HASHDATAIN25_HASH_DATA_IN_M 0xFFFFFFFF
+#define CRYPTO_HASHDATAIN25_HASH_DATA_IN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDATAIN26
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DATA_IN
+//
+// HASH_DATA_IN[863:832]
+// These registers must be written with the 512-bit input data. The data lines
+// are connected directly to the data input of the hash module and hence into
+// the engine's internal data buffer. Writing to each of the registers triggers
+// a corresponding 32-bit write enable to the internal buffer.
+// Note: The host may only write the input data buffer when
+// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine
+// is busy with processing. During processing, it is not allowed to write new
+// input data.
+// For message lengths larger than 64 bytes, multiple blocks of data are
+// written to this input buffer using a handshake through flags of the
+// HASHIOBUFCTRL register. All blocks except the last are required to be 512
+// bits in size. If the last block is not 512 bits long, only the least
+// significant bits of data must be written, but they must be padded with 0s to
+// the next 32-bit boundary.
+// Host read operations from these register addresses return 0s.
+#define CRYPTO_HASHDATAIN26_HASH_DATA_IN_W 32
+#define CRYPTO_HASHDATAIN26_HASH_DATA_IN_M 0xFFFFFFFF
+#define CRYPTO_HASHDATAIN26_HASH_DATA_IN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDATAIN27
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DATA_IN
+//
+// HASH_DATA_IN[895:864]
+// These registers must be written with the 512-bit input data. The data lines
+// are connected directly to the data input of the hash module and hence into
+// the engine's internal data buffer. Writing to each of the registers triggers
+// a corresponding 32-bit write enable to the internal buffer.
+// Note: The host may only write the input data buffer when
+// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine
+// is busy with processing. During processing, it is not allowed to write new
+// input data.
+// For message lengths larger than 64 bytes, multiple blocks of data are
+// written to this input buffer using a handshake through flags of the
+// HASHIOBUFCTRL register. All blocks except the last are required to be 512
+// bits in size. If the last block is not 512 bits long, only the least
+// significant bits of data must be written, but they must be padded with 0s to
+// the next 32-bit boundary.
+// Host read operations from these register addresses return 0s.
+#define CRYPTO_HASHDATAIN27_HASH_DATA_IN_W 32
+#define CRYPTO_HASHDATAIN27_HASH_DATA_IN_M 0xFFFFFFFF
+#define CRYPTO_HASHDATAIN27_HASH_DATA_IN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDATAIN28
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DATA_IN
+//
+// HASH_DATA_IN[923:896]
+// These registers must be written with the 512-bit input data. The data lines
+// are connected directly to the data input of the hash module and hence into
+// the engine's internal data buffer. Writing to each of the registers triggers
+// a corresponding 32-bit write enable to the internal buffer.
+// Note: The host may only write the input data buffer when
+// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine
+// is busy with processing. During processing, it is not allowed to write new
+// input data.
+// For message lengths larger than 64 bytes, multiple blocks of data are
+// written to this input buffer using a handshake through flags of the
+// HASHIOBUFCTRL register. All blocks except the last are required to be 512
+// bits in size. If the last block is not 512 bits long, only the least
+// significant bits of data must be written, but they must be padded with 0s to
+// the next 32-bit boundary.
+// Host read operations from these register addresses return 0s.
+#define CRYPTO_HASHDATAIN28_HASH_DATA_IN_W 32
+#define CRYPTO_HASHDATAIN28_HASH_DATA_IN_M 0xFFFFFFFF
+#define CRYPTO_HASHDATAIN28_HASH_DATA_IN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDATAIN29
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DATA_IN
+//
+// HASH_DATA_IN[959:924]
+// These registers must be written with the 512-bit input data. The data lines
+// are connected directly to the data input of the hash module and hence into
+// the engine's internal data buffer. Writing to each of the registers triggers
+// a corresponding 32-bit write enable to the internal buffer.
+// Note: The host may only write the input data buffer when
+// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine
+// is busy with processing. During processing, it is not allowed to write new
+// input data.
+// For message lengths larger than 64 bytes, multiple blocks of data are
+// written to this input buffer using a handshake through flags of the
+// HASHIOBUFCTRL register. All blocks except the last are required to be 512
+// bits in size. If the last block is not 512 bits long, only the least
+// significant bits of data must be written, but they must be padded with 0s to
+// the next 32-bit boundary.
+// Host read operations from these register addresses return 0s.
+#define CRYPTO_HASHDATAIN29_HASH_DATA_IN_W 32
+#define CRYPTO_HASHDATAIN29_HASH_DATA_IN_M 0xFFFFFFFF
+#define CRYPTO_HASHDATAIN29_HASH_DATA_IN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDATAIN30
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DATA_IN
+//
+// HASH_DATA_IN[991:960]
+// These registers must be written with the 512-bit input data. The data lines
+// are connected directly to the data input of the hash module and hence into
+// the engine's internal data buffer. Writing to each of the registers triggers
+// a corresponding 32-bit write enable to the internal buffer.
+// Note: The host may only write the input data buffer when
+// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine
+// is busy with processing. During processing, it is not allowed to write new
+// input data.
+// For message lengths larger than 64 bytes, multiple blocks of data are
+// written to this input buffer using a handshake through flags of the
+// HASHIOBUFCTRL register. All blocks except the last are required to be 512
+// bits in size. If the last block is not 512 bits long, only the least
+// significant bits of data must be written, but they must be padded with 0s to
+// the next 32-bit boundary.
+// Host read operations from these register addresses return 0s.
+#define CRYPTO_HASHDATAIN30_HASH_DATA_IN_W 32
+#define CRYPTO_HASHDATAIN30_HASH_DATA_IN_M 0xFFFFFFFF
+#define CRYPTO_HASHDATAIN30_HASH_DATA_IN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDATAIN31
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DATA_IN
+//
+// HASH_DATA_IN[1023:992]
+// These registers must be written with the 512-bit input data. The data lines
+// are connected directly to the data input of the hash module and hence into
+// the engine's internal data buffer. Writing to each of the registers triggers
+// a corresponding 32-bit write enable to the internal buffer.
+// Note: The host may only write the input data buffer when
+// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine
+// is busy with processing. During processing, it is not allowed to write new
+// input data.
+// For message lengths larger than 64 bytes, multiple blocks of data are
+// written to this input buffer using a handshake through flags of the
+// HASHIOBUFCTRL register. All blocks except the last are required to be 512
+// bits in size. If the last block is not 512 bits long, only the least
+// significant bits of data must be written, but they must be padded with 0s to
+// the next 32-bit boundary.
+// Host read operations from these register addresses return 0s.
+#define CRYPTO_HASHDATAIN31_HASH_DATA_IN_W 32
+#define CRYPTO_HASHDATAIN31_HASH_DATA_IN_M 0xFFFFFFFF
+#define CRYPTO_HASHDATAIN31_HASH_DATA_IN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHIOBUFCTRL
+//
+//*****************************************************************************
+// Field: [7] PAD_DMA_MESSAGE
+//
+// Note: This bit must only be used when data is supplied through the DMA. It
+// should not be used when data is supplied through the slave interface.
+// This bit indicates whether the hash engine has to pad the message, received
+// through the DMA and finalize the hash.
+// When set to 1, the hash engine pads the last block using the programmed
+// length. After padding, the final hash result is calculated.
+// When set to 0, the hash engine treats the last written block as block-size
+// aligned and calculates the intermediate digest.
+// This bit is automatically cleared when the last DMA data block is arrived in
+// the hash engine.
+#define CRYPTO_HASHIOBUFCTRL_PAD_DMA_MESSAGE 0x00000080
+#define CRYPTO_HASHIOBUFCTRL_PAD_DMA_MESSAGE_BITN 7
+#define CRYPTO_HASHIOBUFCTRL_PAD_DMA_MESSAGE_M 0x00000080
+#define CRYPTO_HASHIOBUFCTRL_PAD_DMA_MESSAGE_S 7
+
+// Field: [6] GET_DIGEST
+//
+// Note: The bit description below is only applicable when data is sent through
+// the slave interface. This bit must be set to 0 when data is received through
+// the DMA.
+// This bit indicates whether the hash engine should provide the hash digest.
+// When provided simultaneously with data_in_av, the hash digest is provided
+// after processing the data that is currently in the HASHDATAINn register.
+// When provided without data_in_av, the current internal digest buffer value
+// is copied to the HASHDIGESTn registers.
+// The host must write a 1 to this bit to make the intermediate hash digest
+// available.
+// Writing 0 to this bit has no effect.
+// This bit is automatically cleared (that is, reads 0) when the hash engine
+// has processed the contents of the HASHDATAINn register. In the period
+// between this bit is set by the host and the actual HASHDATAINn processing,
+// this bit reads 1.
+#define CRYPTO_HASHIOBUFCTRL_GET_DIGEST 0x00000040
+#define CRYPTO_HASHIOBUFCTRL_GET_DIGEST_BITN 6
+#define CRYPTO_HASHIOBUFCTRL_GET_DIGEST_M 0x00000040
+#define CRYPTO_HASHIOBUFCTRL_GET_DIGEST_S 6
+
+// Field: [5] PAD_MESSAGE
+//
+// Note: The bit description below is only applicable when data is sent through
+// the slave interface. This bit must be set to 0 when data is received through
+// the DMA.
+// This bit indicates that the HASHDATAINn registers hold the last data of the
+// message and hash padding must be applied.
+// The host must write this bit to 1 in order to indicate to the hash engine
+// that the HASHDATAINn register currently holds the last data of the message.
+// When pad_message is set to 1, the hash engine will add padding bits to the
+// data currently in the HASHDATAINn register.
+// When the last message block is smaller than 512 bits, the pad_message bit
+// must be set to 1 together with the data_in_av bit.
+// When the last message block is equal to 512 bits, pad_message may be set
+// together with data_in_av. In this case the pad_message bit may also be set
+// after the last data block has been written to the hash engine (so when the
+// rfd_in bit has become 1 again after writing the last data block).
+// Writing 0 to this bit has no effect.
+// This bit is automatically cleared (i.e. reads 0) by the hash engine. This
+// bit reads 1 between the time it was set by the host and the hash engine
+// interpreted its value.
+#define CRYPTO_HASHIOBUFCTRL_PAD_MESSAGE 0x00000020
+#define CRYPTO_HASHIOBUFCTRL_PAD_MESSAGE_BITN 5
+#define CRYPTO_HASHIOBUFCTRL_PAD_MESSAGE_M 0x00000020
+#define CRYPTO_HASHIOBUFCTRL_PAD_MESSAGE_S 5
+
+// Field: [2] RFD_IN
+//
+// Note: The bit description below is only applicable when data is sent through
+// the slave interface. This bit can be ignored when data is received through
+// the DMA.
+// Read-only status of the input buffer of the hash engine.
+// When 1, the input buffer of the hash engine can accept new data; the
+// HASHDATAINn registers can safely be populated with new data.
+// When 0, the input buffer of the hash engine is processing the data that is
+// currently in HASHDATAINn; writing new data to these registers is not
+// allowed.
+#define CRYPTO_HASHIOBUFCTRL_RFD_IN 0x00000004
+#define CRYPTO_HASHIOBUFCTRL_RFD_IN_BITN 2
+#define CRYPTO_HASHIOBUFCTRL_RFD_IN_M 0x00000004
+#define CRYPTO_HASHIOBUFCTRL_RFD_IN_S 2
+
+// Field: [1] DATA_IN_AV
+//
+// Note: The bit description below is only applicable when data is sent through
+// the slave interface. This bit must be set to 0 when data is received through
+// the DMA.
+// This bit indicates that the HASHDATAINn registers contain new input data for
+// processing.
+// The host must write a 1 to this bit to start processing the data in
+// HASHDATAINn; the hash engine will process the new data as soon as it is
+// ready for it (rfd_in bit is 1).
+// Writing 0 to this bit has no effect.
+// This bit is automatically cleared (i.e. reads as 0) when the hash engine
+// starts processing the HASHDATAINn contents. This bit reads 1 between the
+// time it was set by the host and the hash engine actually starts processing
+// the input data block.
+#define CRYPTO_HASHIOBUFCTRL_DATA_IN_AV 0x00000002
+#define CRYPTO_HASHIOBUFCTRL_DATA_IN_AV_BITN 1
+#define CRYPTO_HASHIOBUFCTRL_DATA_IN_AV_M 0x00000002
+#define CRYPTO_HASHIOBUFCTRL_DATA_IN_AV_S 1
+
+// Field: [0] OUTPUT_FULL
+//
+// Indicates that the output buffer registers (HASHDIGESTn) are available for
+// reading by the host.
+// When this bit reads 0, the output buffer registers are released; the hash
+// engine is allowed to write new data to it. In this case, the registers
+// should not be read by the host.
+// When this bit reads 1, the hash engine has stored the result of the latest
+// hash operation in the output buffer registers. As long as this bit reads 1,
+// the host may read output buffer registers and the hash engine is prevented
+// from writing new data to the output buffer.
+// After retrieving the hash result data from the output buffer, the host must
+// write a 1 to this bit to clear it. This makes the digest output buffer
+// available for the hash engine to store new hash results.
+// Writing 0 to this bit has no effect.
+// Note: If this bit is asserted (1) no new operation should be started before
+// the digest is retrieved from the hash engine and this bit is cleared (0).
+#define CRYPTO_HASHIOBUFCTRL_OUTPUT_FULL 0x00000001
+#define CRYPTO_HASHIOBUFCTRL_OUTPUT_FULL_BITN 0
+#define CRYPTO_HASHIOBUFCTRL_OUTPUT_FULL_M 0x00000001
+#define CRYPTO_HASHIOBUFCTRL_OUTPUT_FULL_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHMODE
+//
+//*****************************************************************************
+// Field: [6] SHA384_MODE
+//
+// The host must write this bit with 1 prior to processing a SHA 384 session.
+#define CRYPTO_HASHMODE_SHA384_MODE 0x00000040
+#define CRYPTO_HASHMODE_SHA384_MODE_BITN 6
+#define CRYPTO_HASHMODE_SHA384_MODE_M 0x00000040
+#define CRYPTO_HASHMODE_SHA384_MODE_S 6
+
+// Field: [5] SHA512_MODE
+//
+// The host must write this bit with 1 prior to processing a SHA 512 session.
+#define CRYPTO_HASHMODE_SHA512_MODE 0x00000020
+#define CRYPTO_HASHMODE_SHA512_MODE_BITN 5
+#define CRYPTO_HASHMODE_SHA512_MODE_M 0x00000020
+#define CRYPTO_HASHMODE_SHA512_MODE_S 5
+
+// Field: [4] SHA224_MODE
+//
+// The host must write this bit with 1 prior to processing a SHA 224 session.
+#define CRYPTO_HASHMODE_SHA224_MODE 0x00000010
+#define CRYPTO_HASHMODE_SHA224_MODE_BITN 4
+#define CRYPTO_HASHMODE_SHA224_MODE_M 0x00000010
+#define CRYPTO_HASHMODE_SHA224_MODE_S 4
+
+// Field: [3] SHA256_MODE
+//
+// The host must write this bit with 1 prior to processing a SHA 256 session.
+#define CRYPTO_HASHMODE_SHA256_MODE 0x00000008
+#define CRYPTO_HASHMODE_SHA256_MODE_BITN 3
+#define CRYPTO_HASHMODE_SHA256_MODE_M 0x00000008
+#define CRYPTO_HASHMODE_SHA256_MODE_S 3
+
+// Field: [0] NEW_HASH
+//
+// When set to 1, it indicates that the hash engine must start processing a new
+// hash session. The [HASHDIGESTn.* ] registers will automatically be loaded
+// with the initial hash algorithm constants of the selected hash algorithm.
+// When this bit is 0 while the hash processing is started, the initial hash
+// algorithm constants are not loaded in the HASHDIGESTn registers. The hash
+// engine will start processing with the digest that is currently in its
+// internal HASHDIGESTn registers.
+// This bit is automatically cleared when hash processing is started.
+#define CRYPTO_HASHMODE_NEW_HASH 0x00000001
+#define CRYPTO_HASHMODE_NEW_HASH_BITN 0
+#define CRYPTO_HASHMODE_NEW_HASH_M 0x00000001
+#define CRYPTO_HASHMODE_NEW_HASH_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHINLENL
+//
+//*****************************************************************************
+// Field: [31:0] LENGTH_IN
+//
+// LENGTH_IN[31:0]
+// Message length registers. The content of these registers is used by the hash
+// engine during the message padding phase of the hash session. The data lines
+// of this registers are directly connected to the interface of the hash
+// engine.
+// For a write operation by the host, these registers should be written with
+// the message length in bits.
+//
+// Final hash operations:
+// The total input data length must be programmed for new hash operations that
+// require finalization (padding). The input data must be provided through the
+// slave or DMA interface.
+//
+// Continued hash operations (finalized):
+// For continued hash operations that require finalization, the total message
+// length must be programmed, including the length of previously hashed data
+// that corresponds to the written input digest.
+//
+// Non-final hash operations:
+// For hash operations that do not require finalization (input data length is
+// multiple of 512-bits which is SHA-256 data block size), the length field
+// does not need to be programmed since not used by the operation.
+//
+// If the message length in bits is below (2^32-1), then only this register
+// needs to be written. The hardware automatically sets HASH_LENGTH_IN_H to 0s
+// in this case.
+// The host may write the length register at any time during the hash session
+// when the HASHIOBUFCTRL.RFD_IN is high. The length register must be written
+// before the last data of the active hash session is written into the hash
+// engine.
+// host read operations from these register locations will return 0s.
+// Note: When getting data from DMA, this register must be programmed before
+// DMA is programmed to start.
+#define CRYPTO_HASHINLENL_LENGTH_IN_W 32
+#define CRYPTO_HASHINLENL_LENGTH_IN_M 0xFFFFFFFF
+#define CRYPTO_HASHINLENL_LENGTH_IN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHINLENH
+//
+//*****************************************************************************
+// Field: [31:0] LENGTH_IN
+//
+// LENGTH_IN[63:32]
+// Message length registers. The content of these registers is used by the hash
+// engine during the message padding phase of the hash session. The data lines
+// of this registers are directly connected to the interface of the hash
+// engine.
+// For a write operation by the host, these registers should be written with
+// the message length in bits.
+//
+// Final hash operations:
+// The total input data length must be programmed for new hash operations that
+// require finalization (padding). The input data must be provided through the
+// slave or DMA interface.
+//
+// Continued hash operations (finalized):
+// For continued hash operations that require finalization, the total message
+// length must be programmed, including the length of previously hashed data
+// that corresponds to the written input digest.
+//
+// Non-final hash operations:
+// For hash operations that do not require finalization (input data length is
+// multiple of 512-bits which is SHA-256 data block size), the length field
+// does not need to be programmed since not used by the operation.
+//
+// If the message length in bits is below (2^32-1), then only HASHINLENL needs
+// to be written. The hardware automatically sets HASH_LENGTH_IN_H to 0s in
+// this case.
+// The host may write the length register at any time during the hash session
+// when the HASHIOBUFCTRL.RFD_IN is high. The length register must be written
+// before the last data of the active hash session is written into the hash
+// engine.
+// host read operations from these register locations will return 0s.
+// Note: When getting data from DMA, this register must be programmed before
+// DMA is programmed to start.
+#define CRYPTO_HASHINLENH_LENGTH_IN_W 32
+#define CRYPTO_HASHINLENH_LENGTH_IN_M 0xFFFFFFFF
+#define CRYPTO_HASHINLENH_LENGTH_IN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDIGESTA
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DIGEST
+//
+// HASH_DIGEST[31:0]
+// Hash digest registers
+// Write operation:
+//
+// Continued hash:
+// These registers should be written with the context data, before the start of
+// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash
+// session).
+//
+// New hash:
+// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the
+// internal digest registers are automatically set to the SHA-256 algorithm
+// constant and these register should not be written.
+//
+// Reading from these registers provides the intermediate hash result
+// (non-final hash operation) or the final hash result (final hash operation)
+// after data processing.
+#define CRYPTO_HASHDIGESTA_HASH_DIGEST_W 32
+#define CRYPTO_HASHDIGESTA_HASH_DIGEST_M 0xFFFFFFFF
+#define CRYPTO_HASHDIGESTA_HASH_DIGEST_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDIGESTB
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DIGEST
+//
+// HASH_DIGEST[63:32]
+// Hash digest registers
+// Write operation:
+//
+// Continued hash:
+// These registers should be written with the context data, before the start of
+// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash
+// session).
+//
+// New hash:
+// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the
+// internal digest registers are automatically set to the SHA-256 algorithm
+// constant and these register should not be written.
+//
+// Reading from these registers provides the intermediate hash result
+// (non-final hash operation) or the final hash result (final hash operation)
+// after data processing.
+#define CRYPTO_HASHDIGESTB_HASH_DIGEST_W 32
+#define CRYPTO_HASHDIGESTB_HASH_DIGEST_M 0xFFFFFFFF
+#define CRYPTO_HASHDIGESTB_HASH_DIGEST_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDIGESTC
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DIGEST
+//
+// HASH_DIGEST[95:64]
+// Hash digest registers
+// Write operation:
+//
+// Continued hash:
+// These registers should be written with the context data, before the start of
+// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash
+// session).
+//
+// New hash:
+// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the
+// internal digest registers are automatically set to the SHA-256 algorithm
+// constant and these register should not be written.
+//
+// Reading from these registers provides the intermediate hash result
+// (non-final hash operation) or the final hash result (final hash operation)
+// after data processing.
+#define CRYPTO_HASHDIGESTC_HASH_DIGEST_W 32
+#define CRYPTO_HASHDIGESTC_HASH_DIGEST_M 0xFFFFFFFF
+#define CRYPTO_HASHDIGESTC_HASH_DIGEST_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDIGESTD
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DIGEST
+//
+// HASH_DIGEST[127:96]
+// Hash digest registers
+// Write operation:
+//
+// Continued hash:
+// These registers should be written with the context data, before the start of
+// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash
+// session).
+//
+// New hash:
+// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the
+// internal digest registers are automatically set to the SHA-256 algorithm
+// constant and these register should not be written.
+//
+// Reading from these registers provides the intermediate hash result
+// (non-final hash operation) or the final hash result (final hash operation)
+// after data processing.
+#define CRYPTO_HASHDIGESTD_HASH_DIGEST_W 32
+#define CRYPTO_HASHDIGESTD_HASH_DIGEST_M 0xFFFFFFFF
+#define CRYPTO_HASHDIGESTD_HASH_DIGEST_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDIGESTE
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DIGEST
+//
+// HASH_DIGEST[159:128]
+// Hash digest registers
+// Write operation:
+//
+// Continued hash:
+// These registers should be written with the context data, before the start of
+// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash
+// session).
+//
+// New hash:
+// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the
+// internal digest registers are automatically set to the SHA-256 algorithm
+// constant and these register should not be written.
+//
+// Reading from these registers provides the intermediate hash result
+// (non-final hash operation) or the final hash result (final hash operation)
+// after data processing.
+#define CRYPTO_HASHDIGESTE_HASH_DIGEST_W 32
+#define CRYPTO_HASHDIGESTE_HASH_DIGEST_M 0xFFFFFFFF
+#define CRYPTO_HASHDIGESTE_HASH_DIGEST_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDIGESTF
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DIGEST
+//
+// HASH_DIGEST[191:160]
+// Hash digest registers
+// Write operation:
+//
+// Continued hash:
+// These registers should be written with the context data, before the start of
+// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash
+// session).
+//
+// New hash:
+// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the
+// internal digest registers are automatically set to the SHA-256 algorithm
+// constant and these register should not be written.
+//
+// Reading from these registers provides the intermediate hash result
+// (non-final hash operation) or the final hash result (final hash operation)
+// after data processing.
+#define CRYPTO_HASHDIGESTF_HASH_DIGEST_W 32
+#define CRYPTO_HASHDIGESTF_HASH_DIGEST_M 0xFFFFFFFF
+#define CRYPTO_HASHDIGESTF_HASH_DIGEST_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDIGESTG
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DIGEST
+//
+// HASH_DIGEST[223:192]
+// Hash digest registers
+// Write operation:
+//
+// Continued hash:
+// These registers should be written with the context data, before the start of
+// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash
+// session).
+//
+// New hash:
+// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the
+// internal digest registers are automatically set to the SHA-256 algorithm
+// constant and these register should not be written.
+//
+// Reading from these registers provides the intermediate hash result
+// (non-final hash operation) or the final hash result (final hash operation)
+// after data processing.
+#define CRYPTO_HASHDIGESTG_HASH_DIGEST_W 32
+#define CRYPTO_HASHDIGESTG_HASH_DIGEST_M 0xFFFFFFFF
+#define CRYPTO_HASHDIGESTG_HASH_DIGEST_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDIGESTH
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DIGEST
+//
+// HASH_DIGEST[255:224]
+// Hash digest registers
+// Write operation:
+//
+// Continued hash:
+// These registers should be written with the context data, before the start of
+// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash
+// session).
+//
+// New hash:
+// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the
+// internal digest registers are automatically set to the SHA-256 algorithm
+// constant and these register should not be written.
+//
+// Reading from these registers provides the intermediate hash result
+// (non-final hash operation) or the final hash result (final hash operation)
+// after data processing.
+#define CRYPTO_HASHDIGESTH_HASH_DIGEST_W 32
+#define CRYPTO_HASHDIGESTH_HASH_DIGEST_M 0xFFFFFFFF
+#define CRYPTO_HASHDIGESTH_HASH_DIGEST_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDIGESTI
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DIGEST
+//
+// HASH_DIGEST[287:256]
+// Hash digest registers
+// Write operation:
+//
+// Continued hash:
+// These registers should be written with the context data, before the start of
+// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash
+// session).
+//
+// New hash:
+// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the
+// internal digest registers are automatically set to the SHA-256 algorithm
+// constant and these register should not be written.
+//
+// Reading from these registers provides the intermediate hash result
+// (non-final hash operation) or the final hash result (final hash operation)
+// after data processing.
+#define CRYPTO_HASHDIGESTI_HASH_DIGEST_W 32
+#define CRYPTO_HASHDIGESTI_HASH_DIGEST_M 0xFFFFFFFF
+#define CRYPTO_HASHDIGESTI_HASH_DIGEST_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDIGESTJ
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DIGEST
+//
+// HASH_DIGEST[319:288]
+// Hash digest registers
+// Write operation:
+//
+// Continued hash:
+// These registers should be written with the context data, before the start of
+// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash
+// session).
+//
+// New hash:
+// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the
+// internal digest registers are automatically set to the SHA-256 algorithm
+// constant and these register should not be written.
+//
+// Reading from these registers provides the intermediate hash result
+// (non-final hash operation) or the final hash result (final hash operation)
+// after data processing.
+#define CRYPTO_HASHDIGESTJ_HASH_DIGEST_W 32
+#define CRYPTO_HASHDIGESTJ_HASH_DIGEST_M 0xFFFFFFFF
+#define CRYPTO_HASHDIGESTJ_HASH_DIGEST_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDIGESTK
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DIGEST
+//
+// HASH_DIGEST[351:320]
+// Hash digest registers
+// Write operation:
+//
+// Continued hash:
+// These registers should be written with the context data, before the start of
+// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash
+// session).
+//
+// New hash:
+// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the
+// internal digest registers are automatically set to the SHA-256 algorithm
+// constant and these register should not be written.
+//
+// Reading from these registers provides the intermediate hash result
+// (non-final hash operation) or the final hash result (final hash operation)
+// after data processing.
+#define CRYPTO_HASHDIGESTK_HASH_DIGEST_W 32
+#define CRYPTO_HASHDIGESTK_HASH_DIGEST_M 0xFFFFFFFF
+#define CRYPTO_HASHDIGESTK_HASH_DIGEST_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDIGESTL
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DIGEST
+//
+// HASH_DIGEST[383:352]
+// Hash digest registers
+// Write operation:
+//
+// Continued hash:
+// These registers should be written with the context data, before the start of
+// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash
+// session).
+//
+// New hash:
+// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the
+// internal digest registers are automatically set to the SHA-256 algorithm
+// constant and these register should not be written.
+//
+// Reading from these registers provides the intermediate hash result
+// (non-final hash operation) or the final hash result (final hash operation)
+// after data processing.
+#define CRYPTO_HASHDIGESTL_HASH_DIGEST_W 32
+#define CRYPTO_HASHDIGESTL_HASH_DIGEST_M 0xFFFFFFFF
+#define CRYPTO_HASHDIGESTL_HASH_DIGEST_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDIGESTM
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DIGEST
+//
+// HASH_DIGEST[415:384]
+// Hash digest registers
+// Write operation:
+//
+// Continued hash:
+// These registers should be written with the context data, before the start of
+// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash
+// session).
+//
+// New hash:
+// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the
+// internal digest registers are automatically set to the SHA-256 algorithm
+// constant and these register should not be written.
+//
+// Reading from these registers provides the intermediate hash result
+// (non-final hash operation) or the final hash result (final hash operation)
+// after data processing.
+#define CRYPTO_HASHDIGESTM_HASH_DIGEST_W 32
+#define CRYPTO_HASHDIGESTM_HASH_DIGEST_M 0xFFFFFFFF
+#define CRYPTO_HASHDIGESTM_HASH_DIGEST_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDIGESTN
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DIGEST
+//
+// HASH_DIGEST[447:416]
+// Hash digest registers
+// Write operation:
+//
+// Continued hash:
+// These registers should be written with the context data, before the start of
+// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash
+// session).
+//
+// New hash:
+// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the
+// internal digest registers are automatically set to the SHA-256 algorithm
+// constant and these register should not be written.
+//
+// Reading from these registers provides the intermediate hash result
+// (non-final hash operation) or the final hash result (final hash operation)
+// after data processing.
+#define CRYPTO_HASHDIGESTN_HASH_DIGEST_W 32
+#define CRYPTO_HASHDIGESTN_HASH_DIGEST_M 0xFFFFFFFF
+#define CRYPTO_HASHDIGESTN_HASH_DIGEST_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDIGESTO
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DIGEST
+//
+// HASH_DIGEST[479:448]
+// Hash digest registers
+// Write operation:
+//
+// Continued hash:
+// These registers should be written with the context data, before the start of
+// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash
+// session).
+//
+// New hash:
+// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the
+// internal digest registers are automatically set to the SHA-256 algorithm
+// constant and these register should not be written.
+//
+// Reading from these registers provides the intermediate hash result
+// (non-final hash operation) or the final hash result (final hash operation)
+// after data processing.
+#define CRYPTO_HASHDIGESTO_HASH_DIGEST_W 32
+#define CRYPTO_HASHDIGESTO_HASH_DIGEST_M 0xFFFFFFFF
+#define CRYPTO_HASHDIGESTO_HASH_DIGEST_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HASHDIGESTP
+//
+//*****************************************************************************
+// Field: [31:0] HASH_DIGEST
+//
+// HASH_DIGEST[511:480]
+// Hash digest registers
+// Write operation:
+//
+// Continued hash:
+// These registers should be written with the context data, before the start of
+// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash
+// session).
+//
+// New hash:
+// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the
+// internal digest registers are automatically set to the SHA-256 algorithm
+// constant and these register should not be written.
+//
+// Reading from these registers provides the intermediate hash result
+// (non-final hash operation) or the final hash result (final hash operation)
+// after data processing.
+#define CRYPTO_HASHDIGESTP_HASH_DIGEST_W 32
+#define CRYPTO_HASHDIGESTP_HASH_DIGEST_M 0xFFFFFFFF
+#define CRYPTO_HASHDIGESTP_HASH_DIGEST_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_ALGSEL
+//
+//*****************************************************************************
+// Field: [32] HASH_SHA_512
+//
+// If set to one, selects the hash engine in 512B mode as destination for the
+// DMA
+// The maximum transfer size to DMA engine is set to 64 bytes for reading and
+// 32 bytes for writing (the latter is only applicable if the hash result is
+// written out through the DMA).
+#define CRYPTO_ALGSEL_HASH_SHA_512 0x100000000
+#define CRYPTO_ALGSEL_HASH_SHA_512_BITN 32
+#define CRYPTO_ALGSEL_HASH_SHA_512_M 0x100000000
+#define CRYPTO_ALGSEL_HASH_SHA_512_S 32
+
+// Field: [31] TAG
+//
+// If this bit is cleared to 0, the DMA operation involves only data.
+// If this bit is set, the DMA operation includes a TAG (Authentication Result
+// / Digest).
+// For SHA-256 operation, a DMA must be set up for both input data and TAG. For
+// any other selected module, setting this bit only allows a DMA that reads the
+// TAG. No data allowed to be transferred to or from the selected module via
+// the DMA.
+#define CRYPTO_ALGSEL_TAG 0x80000000
+#define CRYPTO_ALGSEL_TAG_BITN 31
+#define CRYPTO_ALGSEL_TAG_M 0x80000000
+#define CRYPTO_ALGSEL_TAG_S 31
+
+// Field: [2] HASH_SHA_256
+//
+// If set to one, selects the hash engine in 256B mode as destination for the
+// DMA
+// The maximum transfer size to DMA engine is set to 64 bytes for reading and
+// 32 bytes for writing (the latter is only applicable if the hash result is
+// written out through the DMA).
+#define CRYPTO_ALGSEL_HASH_SHA_256 0x00000004
+#define CRYPTO_ALGSEL_HASH_SHA_256_BITN 2
+#define CRYPTO_ALGSEL_HASH_SHA_256_M 0x00000004
+#define CRYPTO_ALGSEL_HASH_SHA_256_S 2
+
+// Field: [1] AES
+//
+// If set to one, selects the AES engine as source/destination for the DMA
+// The read and write maximum transfer size to the DMA engine is set to 16
+// bytes.
+#define CRYPTO_ALGSEL_AES 0x00000002
+#define CRYPTO_ALGSEL_AES_BITN 1
+#define CRYPTO_ALGSEL_AES_M 0x00000002
+#define CRYPTO_ALGSEL_AES_S 1
+
+// Field: [0] KEY_STORE
+//
+// If set to one, selects the Key Store as destination for the DMA
+// The maximum transfer size to DMA engine is set to 32 bytes (however
+// transfers of 16, 24 and 32 bytes are allowed)
+#define CRYPTO_ALGSEL_KEY_STORE 0x00000001
+#define CRYPTO_ALGSEL_KEY_STORE_BITN 0
+#define CRYPTO_ALGSEL_KEY_STORE_M 0x00000001
+#define CRYPTO_ALGSEL_KEY_STORE_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_DMAPROTCTL
+//
+//*****************************************************************************
+// Field: [0] PROT_EN
+//
+// Select AHB transfer protection control for DMA transfers using the key store
+// area as destination.
+// 0 : transfers use 'USER' type access.
+// 1 : transfers use 'PRIVILEGED' type access.
+#define CRYPTO_DMAPROTCTL_PROT_EN 0x00000001
+#define CRYPTO_DMAPROTCTL_PROT_EN_BITN 0
+#define CRYPTO_DMAPROTCTL_PROT_EN_M 0x00000001
+#define CRYPTO_DMAPROTCTL_PROT_EN_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_SWRESET
+//
+//*****************************************************************************
+// Field: [0] SW_RESET
+//
+// If this bit is set to 1, the following modules are reset:
+// - Master control internal state is reset. That includes interrupt, error
+// status register, and result available interrupt generation FSM.
+// - Key store module state is reset. That includes clearing the written area
+// flags; therefore, the keys must be reloaded to the key store module.
+// Writing 0 has no effect.
+// The bit is self cleared after executing the reset.
+#define CRYPTO_SWRESET_SW_RESET 0x00000001
+#define CRYPTO_SWRESET_SW_RESET_BITN 0
+#define CRYPTO_SWRESET_SW_RESET_M 0x00000001
+#define CRYPTO_SWRESET_SW_RESET_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_IRQTYPE
+//
+//*****************************************************************************
+// Field: [0] LEVEL
+//
+// If this bit is 0, the interrupt output is a pulse.
+// If this bit is set to 1, the interrupt is a level interrupt that must be
+// cleared by writing the interrupt clear register.
+// This bit is applicable for both interrupt output signals.
+#define CRYPTO_IRQTYPE_LEVEL 0x00000001
+#define CRYPTO_IRQTYPE_LEVEL_BITN 0
+#define CRYPTO_IRQTYPE_LEVEL_M 0x00000001
+#define CRYPTO_IRQTYPE_LEVEL_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_IRQEN
+//
+//*****************************************************************************
+// Field: [1] DMA_IN_DONE
+//
+// If this bit is set to 0, the DMA input done (irq_dma_in_done) interrupt
+// output is disabled and remains 0.
+// If this bit is set to 1, the DMA input done interrupt output is enabled.
+#define CRYPTO_IRQEN_DMA_IN_DONE 0x00000002
+#define CRYPTO_IRQEN_DMA_IN_DONE_BITN 1
+#define CRYPTO_IRQEN_DMA_IN_DONE_M 0x00000002
+#define CRYPTO_IRQEN_DMA_IN_DONE_S 1
+
+// Field: [0] RESULT_AVAIL
+//
+// If this bit is set to 0, the result available (irq_result_av) interrupt
+// output is disabled and remains 0.
+// If this bit is set to 1, the result available interrupt output is enabled.
+#define CRYPTO_IRQEN_RESULT_AVAIL 0x00000001
+#define CRYPTO_IRQEN_RESULT_AVAIL_BITN 0
+#define CRYPTO_IRQEN_RESULT_AVAIL_M 0x00000001
+#define CRYPTO_IRQEN_RESULT_AVAIL_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_IRQCLR
+//
+//*****************************************************************************
+// Field: [31] DMA_BUS_ERR
+//
+// If 1 is written to this bit, the DMA bus error status is cleared.
+// Writing 0 has no effect.
+#define CRYPTO_IRQCLR_DMA_BUS_ERR 0x80000000
+#define CRYPTO_IRQCLR_DMA_BUS_ERR_BITN 31
+#define CRYPTO_IRQCLR_DMA_BUS_ERR_M 0x80000000
+#define CRYPTO_IRQCLR_DMA_BUS_ERR_S 31
+
+// Field: [30] KEY_ST_WR_ERR
+//
+// If 1 is written to this bit, the key store write error status is cleared.
+// Writing 0 has no effect.
+#define CRYPTO_IRQCLR_KEY_ST_WR_ERR 0x40000000
+#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_BITN 30
+#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_M 0x40000000
+#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_S 30
+
+// Field: [29] KEY_ST_RD_ERR
+//
+// If 1 is written to this bit, the key store read error status is cleared.
+// Writing 0 has no effect.
+#define CRYPTO_IRQCLR_KEY_ST_RD_ERR 0x20000000
+#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_BITN 29
+#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_M 0x20000000
+#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_S 29
+
+// Field: [1] DMA_IN_DONE
+//
+// If 1 is written to this bit, the DMA in done (irq_dma_in_done) interrupt
+// output is cleared.
+// Writing 0 has no effect.
+// Note that clearing an interrupt makes sense only if the interrupt output is
+// programmed as level (refer to IRQTYPE).
+#define CRYPTO_IRQCLR_DMA_IN_DONE 0x00000002
+#define CRYPTO_IRQCLR_DMA_IN_DONE_BITN 1
+#define CRYPTO_IRQCLR_DMA_IN_DONE_M 0x00000002
+#define CRYPTO_IRQCLR_DMA_IN_DONE_S 1
+
+// Field: [0] RESULT_AVAIL
+//
+// If 1 is written to this bit, the result available (irq_result_av) interrupt
+// output is cleared.
+// Writing 0 has no effect.
+// Note that clearing an interrupt makes sense only if the interrupt output is
+// programmed as level (refer to IRQTYPE).
+#define CRYPTO_IRQCLR_RESULT_AVAIL 0x00000001
+#define CRYPTO_IRQCLR_RESULT_AVAIL_BITN 0
+#define CRYPTO_IRQCLR_RESULT_AVAIL_M 0x00000001
+#define CRYPTO_IRQCLR_RESULT_AVAIL_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_IRQSET
+//
+//*****************************************************************************
+// Field: [1] DMA_IN_DONE
+//
+// If 1 is written to this bit, the DMA data in done (irq_dma_in_done)
+// interrupt output is set to one.
+// Writing 0 has no effect.
+// If the interrupt configuration register is programmed to pulse, clearing the
+// DMA data in done (irq_dma_in_done) interrupt is not needed. If it is
+// programmed to level, clearing the interrupt output should be done by writing
+// the interrupt clear register (IRQCLR.DMA_IN_DONE).
+#define CRYPTO_IRQSET_DMA_IN_DONE 0x00000002
+#define CRYPTO_IRQSET_DMA_IN_DONE_BITN 1
+#define CRYPTO_IRQSET_DMA_IN_DONE_M 0x00000002
+#define CRYPTO_IRQSET_DMA_IN_DONE_S 1
+
+// Field: [0] RESULT_AVAIL
+//
+// If 1 is written to this bit, the result available (irq_result_av) interrupt
+// output is set to one.
+// Writing 0 has no effect.
+// If the interrupt configuration register is programmed to pulse, clearing the
+// result available (irq_result_av) interrupt is not needed. If it is
+// programmed to level, clearing the interrupt output should be done by writing
+// the interrupt clear register (IRQCLR.RESULT_AVAIL).
+#define CRYPTO_IRQSET_RESULT_AVAIL 0x00000001
+#define CRYPTO_IRQSET_RESULT_AVAIL_BITN 0
+#define CRYPTO_IRQSET_RESULT_AVAIL_M 0x00000001
+#define CRYPTO_IRQSET_RESULT_AVAIL_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_IRQSTAT
+//
+//*****************************************************************************
+// Field: [31] DMA_BUS_ERR
+//
+// This bit is set when a DMA bus error is detected during a DMA operation. The
+// value of this register is held until it is cleared through the
+// IRQCLR.DMA_BUS_ERR
+// Note: This error is asserted if an error is detected on the AHB master
+// interface during a DMA operation.
+#define CRYPTO_IRQSTAT_DMA_BUS_ERR 0x80000000
+#define CRYPTO_IRQSTAT_DMA_BUS_ERR_BITN 31
+#define CRYPTO_IRQSTAT_DMA_BUS_ERR_M 0x80000000
+#define CRYPTO_IRQSTAT_DMA_BUS_ERR_S 31
+
+// Field: [30] KEY_ST_WR_ERR
+//
+// This bit is set when a write error is detected during the DMA write
+// operation to the key store memory. The value of this register is held until
+// it is cleared through the IRQCLR.KEY_ST_WR_ERR register.
+// Note: This error is asserted if a DMA operation does not cover a full key
+// area or more areas are written than expected.
+#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR 0x40000000
+#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_BITN 30
+#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M 0x40000000
+#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_S 30
+
+// Field: [29] KEY_ST_RD_ERR
+//
+// This bit is set when a read error is detected during the read of a key from
+// the key store, while copying it to the AES core. The value of this register
+// is held until it is cleared through the IRQCLR.KEY_ST_RD_ERR register.
+// Note: This error is asserted if a key location is selected in the key store
+// that is not available.
+#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR 0x20000000
+#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_BITN 29
+#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_M 0x20000000
+#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_S 29
+
+// Field: [1] DMA_IN_DONE
+//
+// This read only bit returns the actual DMA data in done (irq_data_in_done)
+// interrupt status of the DMA data in done interrupt output pin
+// (irq_data_in_done).
+#define CRYPTO_IRQSTAT_DMA_IN_DONE 0x00000002
+#define CRYPTO_IRQSTAT_DMA_IN_DONE_BITN 1
+#define CRYPTO_IRQSTAT_DMA_IN_DONE_M 0x00000002
+#define CRYPTO_IRQSTAT_DMA_IN_DONE_S 1
+
+// Field: [0] RESULT_AVAIL
+//
+// This read only bit returns the actual result available (irq_result_av)
+// interrupt status of the result available interrupt output pin
+// (irq_result_av).
+#define CRYPTO_IRQSTAT_RESULT_AVAIL 0x00000001
+#define CRYPTO_IRQSTAT_RESULT_AVAIL_BITN 0
+#define CRYPTO_IRQSTAT_RESULT_AVAIL_M 0x00000001
+#define CRYPTO_IRQSTAT_RESULT_AVAIL_S 0
+
+//*****************************************************************************
+//
+// Register: CRYPTO_O_HWVER
+//
+//*****************************************************************************
+// Field: [27:24] HW_MAJOR_VER
+//
+// Major version number
+#define CRYPTO_HWVER_HW_MAJOR_VER_W 4
+#define CRYPTO_HWVER_HW_MAJOR_VER_M 0x0F000000
+#define CRYPTO_HWVER_HW_MAJOR_VER_S 24
+
+// Field: [23:20] HW_MINOR_VER
+//
+// Minor version number
+#define CRYPTO_HWVER_HW_MINOR_VER_W 4
+#define CRYPTO_HWVER_HW_MINOR_VER_M 0x00F00000
+#define CRYPTO_HWVER_HW_MINOR_VER_S 20
+
+// Field: [19:16] HW_PATCH_LVL
+//
+// Patch level
+// Starts at 0 at first delivery of this version
+#define CRYPTO_HWVER_HW_PATCH_LVL_W 4
+#define CRYPTO_HWVER_HW_PATCH_LVL_M 0x000F0000
+#define CRYPTO_HWVER_HW_PATCH_LVL_S 16
+
+// Field: [15:8] VER_NUM_COMPL
+//
+// These bits simply contain the complement of bits [7:0] (0x87), used by a
+// driver to ascertain that the EIP-120t register is indeed read.
+#define CRYPTO_HWVER_VER_NUM_COMPL_W 8
+#define CRYPTO_HWVER_VER_NUM_COMPL_M 0x0000FF00
+#define CRYPTO_HWVER_VER_NUM_COMPL_S 8
+
+// Field: [7:0] VER_NUM
+//
+// These bits encode the EIP number for the EIP-120t, this field contains the
+// value 120 (decimal) or 0x78.
+#define CRYPTO_HWVER_VER_NUM_W 8
+#define CRYPTO_HWVER_VER_NUM_M 0x000000FF
+#define CRYPTO_HWVER_VER_NUM_S 0
+
+
+#endif // __CRYPTO__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ddi.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ddi.h
new file mode 100644
index 0000000..fc93c11
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ddi.h
@@ -0,0 +1,197 @@
+/******************************************************************************
+* Filename: hw_ddi.h
+* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017)
+* Revision: 49096
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_DDI_H__
+#define __HW_DDI_H__
+
+//*****************************************************************************
+//
+// This file contains macros for controlling the DDI master and
+// accessing DDI Slave registers via the DDI Master.
+// There are 3 categories of macros in this file:
+// - macros that provide an offset to a register
+// located within the DDI Master itself.
+// - macros that define bits or bitfields
+// within the DDI Master Registers.
+// - macros that provide an "instruction offset"
+// that are used when accessing a DDI Slave.
+//
+// The macros that that provide DDI Master register offsets and
+// define bits and bitfields for those registers are the typical
+// macros that appear in most hw_<module>.h header files. In
+// the following example DDI_O_CFG is a macro for a
+// register offset and DDI_CFG_WAITFORACK is a macro for
+// a bit in that register. This example code will set the WAITFORACK
+// bit in register DDI_O_CFG of the DDI Master. (Note: this
+// access the Master not the Slave).
+//
+// HWREG(AUX_OSCDDI_BASE + DDI_O_CFG) |= DDI_CFG_WAITFORACK;
+//
+//
+// The "instruction offset" macros are used to pass an instruction to
+// the DDI Master when accessing DDI slave registers. These macros are
+// only used when accessing DDI Slave Registers. (Remember DDI
+// Master Registers are accessed normally).
+//
+// The instructions supported when accessing a DDI Slave Regsiter follow:
+// - Direct Access to a DDI Slave register. I.e. read or
+// write the register.
+// - Set the specified bits in a DDI Slave register.
+// - Clear the specified bits in a DDI Slave register.
+// - Mask write of 4 bits to the a DDI Slave register.
+// - Mask write of 8 bits to the a DDI Slave register.
+// - Mask write of 16 bits to the a DDI Slave register.
+//
+// Note: only the "Direct Access" offset should be used when reading
+// a DDI Slave register. Only 8- and 16-bit reads are supported.
+//
+// The generic format of using this marcos for a read follows:
+// // read low 16-bits in DDI_SLAVE_OFF
+// myushortvar = HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR);
+//
+// // read high 16-bits in DDI_SLAVE_OFF
+// // add 2 for data[31:16]
+// myushortvar = HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + 2 + DDI_O_DIR);
+
+// // read data[31:24] byte in DDI_SLAVE_OFF
+// // add 3 for data[31:24]
+// myuchar = HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + 3 + DDI_O_DIR);
+//
+// Notes: In the above example:
+// - DDI_MASTER_BASE is the base address of the DDI Master defined
+// in the hw_memmap.h header file.
+// - DDI_SLAVE_OFF is the DDI Slave offset defined in the
+// hw_<ddi_slave>.h header file (e.g. hw_osc_top.h for the oscsc
+// oscillator modules.
+// - DDI_O_DIR is the "instruction offset" macro defined in this
+// file that specifies the Direct Access instruction.
+//
+// Writes can use any of the "instruction macros".
+// The following examples do a "direct write" to DDI Slave register
+// DDI_SLAVE_OFF using different size operands:
+//
+// // ---------- DIRECT WRITES ----------
+// // Write 32-bits aligned
+// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR) = 0x12345678;
+
+// // Write 16-bits aligned to high 16-bits then low 16-bits
+// // Add 2 to get to high 16-bits.
+// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 2) = 0xabcd;
+// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR) = 0xef01;
+//
+// // Write each byte at DDI_SLAVE_OFF, one at a time.
+// // Add 1,2,or 3 to get to bytes 1,2, or 3.
+// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR) = 0x33;
+// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 1) = 0x44;
+// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 2) = 0x55;
+// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 3) = 0x66;
+//
+// // ---------- SET/CLR ----------
+// The set and clear functions behave similarly to eachother. Each
+// can be performed on an 8-, 16-, or 32-bit operand.
+// Examples follow:
+// // Set all odd bits in a 32-bit words
+// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_SET) = 0xaaaaaaaa;
+//
+// // Clear all bits in byte 2 (data[23:16]) using 32-bit operand
+// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_CLR) = 0x00ff0000;
+//
+// // Set even bits in byte 2 (data[23:16]) using 8-bit operand
+// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + 2 + DDI_O_CLR) = 0x55;
+//
+// // ---------- MASKED WRITES ----------
+// The mask writes are a bit different. They operate on nibbles,
+// bytes, and 16-bit elements. Two operands are required; a 'mask'
+// and 'data'; The operands are concatenated and written to the master.
+// e.g. the mask and data are combined as follows for a 16 bit masked
+// write:
+// (mask << 16) | data;
+// Examples follow:
+//
+// // Write 5555 to low 16-bits of DDI_SLAVE_OFF register
+// // a long write is needed (32-bits).
+// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B) = 0xffff5555;
+
+// // Write 1AA to data bits 24:16 in high 16-bits of DDI_SLAVE_OFF register
+// // Note add 4 for high 16-bits at DDI_SLAVE_OFF; mask is 1ff!
+// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 4) = 0x01ff01aa;
+//
+// // Do an 8 bit masked write of 00 to low byte of register (data[7:0]).
+// // a short write is needed (16-bits).
+// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B) = 0xff00;
+//
+// // Do an 8 bit masked write of 11 to byte 1 of register (data[15:8]).
+// // add 2 to get to byte 1.
+// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 2) = 0xff11;
+//
+// // Do an 8 bit masked write of 33 to high byte of register (data[31:24]).
+// // add 6 to get to byte 3.
+// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 6) = 0xff33;
+//
+// // Do an 4 bit masked write (Nibble) of 7 to data[3:0]).
+// // Byte write is needed.
+// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B) = 0xf7;
+//
+// // Do an 4 bit masked write of 4 to data[7:4]).
+// // Add 1 for next nibble
+// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 1) = 0xf4;
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// The following are defines for the DDI master instruction offsets.
+//
+//*****************************************************************************
+#define DDI_O_DIR 0x00000000 // Offset for the direct access instruction
+#define DDI_O_SET 0x00000080 // Offset for 'Set' instruction.
+#define DDI_O_CLR 0x00000100 // Offset for 'Clear' instruction.
+#define DDI_O_MASK4B 0x00000200 // Offset for 4-bit masked access.
+ // Data bit[n] is written if mask bit[n] is set ('1').
+ // Bits 7:4 are mask. Bits 3:0 are data.
+ // Requires 'byte' write.
+#define DDI_O_MASK8B 0x00000300 // Offset for 8-bit masked access.
+ // Data bit[n] is written if mask bit[n] is set ('1').
+ // Bits 15:8 are mask. Bits 7:0 are data.
+ // Requires 'short' write.
+#define DDI_O_MASK16B 0x00000400 // Offset for 16-bit masked access.
+ // Data bit[n] is written if mask bit[n] is set ('1').
+ // Bits 31:16 are mask. Bits 15:0 are data.
+ // Requires 'long' write.
+
+
+
+#endif // __HW_DDI_H__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ddi_0_osc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ddi_0_osc.h
new file mode 100644
index 0000000..ee49e27
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ddi_0_osc.h
@@ -0,0 +1,1153 @@
+/******************************************************************************
+* Filename: hw_ddi_0_osc_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_DDI_0_OSC_H__
+#define __HW_DDI_0_OSC_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// DDI_0_OSC component
+//
+//*****************************************************************************
+// Control 0
+#define DDI_0_OSC_O_CTL0 0x00000000
+
+// Control 1
+#define DDI_0_OSC_O_CTL1 0x00000004
+
+// RADC External Configuration
+#define DDI_0_OSC_O_RADCEXTCFG 0x00000008
+
+// Amplitude Compensation Control
+#define DDI_0_OSC_O_AMPCOMPCTL 0x0000000C
+
+// Amplitude Compensation Threshold 1
+#define DDI_0_OSC_O_AMPCOMPTH1 0x00000010
+
+// Amplitude Compensation Threshold 2
+#define DDI_0_OSC_O_AMPCOMPTH2 0x00000014
+
+// Analog Bypass Values 1
+#define DDI_0_OSC_O_ANABYPASSVAL1 0x00000018
+
+// Internal
+#define DDI_0_OSC_O_ANABYPASSVAL2 0x0000001C
+
+// Analog Test Control
+#define DDI_0_OSC_O_ATESTCTL 0x00000020
+
+// ADC Doubler Nanoamp Control
+#define DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL 0x00000024
+
+// XOSCHF Control
+#define DDI_0_OSC_O_XOSCHFCTL 0x00000028
+
+// Low Frequency Oscillator Control
+#define DDI_0_OSC_O_LFOSCCTL 0x0000002C
+
+// RCOSCHF Control
+#define DDI_0_OSC_O_RCOSCHFCTL 0x00000030
+
+// RCOSC_MF Control
+#define DDI_0_OSC_O_RCOSCMFCTL 0x00000034
+
+// Status 0
+#define DDI_0_OSC_O_STAT0 0x0000003C
+
+// Status 1
+#define DDI_0_OSC_O_STAT1 0x00000040
+
+// Status 2
+#define DDI_0_OSC_O_STAT2 0x00000044
+
+//*****************************************************************************
+//
+// Register: DDI_0_OSC_O_CTL0
+//
+//*****************************************************************************
+// Field: [31] XTAL_IS_24M
+//
+// Set based on the accurate high frequency XTAL.
+// ENUMs:
+// 24M Internal. Only to be used through TI provided API.
+// 48M Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_CTL0_XTAL_IS_24M 0x80000000
+#define DDI_0_OSC_CTL0_XTAL_IS_24M_M 0x80000000
+#define DDI_0_OSC_CTL0_XTAL_IS_24M_S 31
+#define DDI_0_OSC_CTL0_XTAL_IS_24M_24M 0x80000000
+#define DDI_0_OSC_CTL0_XTAL_IS_24M_48M 0x00000000
+
+// Field: [29] BYPASS_XOSC_LF_CLK_QUAL
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL 0x20000000
+#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_M 0x20000000
+#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_S 29
+
+// Field: [28] BYPASS_RCOSC_LF_CLK_QUAL
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL 0x10000000
+#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_M 0x10000000
+#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_S 28
+
+// Field: [27:26] DOUBLER_START_DURATION
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_W 2
+#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_M 0x0C000000
+#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_S 26
+
+// Field: [25] DOUBLER_RESET_DURATION
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION 0x02000000
+#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION_M 0x02000000
+#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION_S 25
+
+// Field: [24] CLK_DCDC_SRC_SEL
+//
+// Select DCDC clock source.
+//
+// 0: CLK_DCDC is 48 MHz clock from RCOSC or XOSC / HPOSC
+// 1: CLK_DCDC is always 48 MHz clock from RCOSC
+#define DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL 0x01000000
+#define DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M 0x01000000
+#define DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_S 24
+
+// Field: [14] HPOSC_MODE_EN
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_CTL0_HPOSC_MODE_EN 0x00004000
+#define DDI_0_OSC_CTL0_HPOSC_MODE_EN_M 0x00004000
+#define DDI_0_OSC_CTL0_HPOSC_MODE_EN_S 14
+
+// Field: [12] RCOSC_LF_TRIMMED
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED 0x00001000
+#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED_M 0x00001000
+#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED_S 12
+
+// Field: [11] XOSC_HF_POWER_MODE
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE 0x00000800
+#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE_M 0x00000800
+#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE_S 11
+
+// Field: [10] XOSC_LF_DIG_BYPASS
+//
+// Bypass XOSC_LF and use the digital input clock from AON for the xosc_lf
+// clock.
+//
+// 0: Use 32kHz XOSC as xosc_lf clock source
+// 1: Use digital input (from AON) as xosc_lf clock source.
+//
+// This bit will only have effect when SCLK_LF_SRC_SEL is selecting the xosc_lf
+// as the sclk_lf source. The muxing performed by this bit is not glitch free.
+// The following procedure must be followed when changing this field to avoid
+// glitches on sclk_lf.
+//
+// 1) Set SCLK_LF_SRC_SEL to select any source other than the xosc_lf clock
+// source.
+// 2) Set or clear this bit to bypass or not bypass the xosc_lf.
+// 3) Set SCLK_LF_SRC_SEL to use xosc_lf.
+//
+// It is recommended that either the rcosc_hf or xosc_hf (whichever is
+// currently active) be selected as the source in step 1 above. This provides a
+// faster clock change.
+#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS 0x00000400
+#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS_M 0x00000400
+#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS_S 10
+
+// Field: [9] CLK_LOSS_EN
+//
+// Enable clock loss detection and hence the indicators to the system
+// controller. Checks both SCLK_HF, SCLK_MF and SCLK_LF clock loss indicators.
+//
+// 0: Disable
+// 1: Enable
+//
+// Clock loss detection must be disabled when changing the sclk_lf source.
+// STAT0.SCLK_LF_SRC can be polled to determine when a change to a new sclk_lf
+// source has completed.
+#define DDI_0_OSC_CTL0_CLK_LOSS_EN 0x00000200
+#define DDI_0_OSC_CTL0_CLK_LOSS_EN_M 0x00000200
+#define DDI_0_OSC_CTL0_CLK_LOSS_EN_S 9
+
+// Field: [8:7] ACLK_TDC_SRC_SEL
+//
+// Source select for aclk_tdc.
+//
+// 00: RCOSC_HF (48MHz)
+// 01: RCOSC_HF (24MHz)
+// 10: XOSC_HF (24MHz)
+// 11: Not used
+#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_W 2
+#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_M 0x00000180
+#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_S 7
+
+// Field: [6:4] ACLK_REF_SRC_SEL
+//
+// Source select for aclk_ref
+//
+// 000: RCOSC_HF derived (31.25kHz)
+// 001: XOSC_HF derived (31.25kHz)
+// 010: RCOSC_LF (32kHz)
+// 011: XOSC_LF (32.768kHz)
+// 100: RCOSC_MF (2MHz)
+// 101-111: Not used
+#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_W 3
+#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_M 0x00000070
+#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_S 4
+
+// Field: [3:2] SCLK_LF_SRC_SEL
+//
+// Source select for sclk_lf
+// ENUMs:
+// XOSCLF Low frequency XOSC
+// RCOSCLF Low frequency RCOSC
+// XOSCHFDLF Low frequency clock derived from High Frequency
+// XOSC
+// RCOSCHFDLF Low frequency clock derived from High Frequency
+// RCOSC
+#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_W 2
+#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_M 0x0000000C
+#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_S 2
+#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCLF 0x0000000C
+#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCLF 0x00000008
+#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCHFDLF 0x00000004
+#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCHFDLF 0x00000000
+
+// Field: [0] SCLK_HF_SRC_SEL
+//
+// Source select for sclk_hf.
+// ENUMs:
+// XOSC High frequency XOSC clock
+// RCOSC High frequency RCOSC clock
+#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL 0x00000001
+#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_M 0x00000001
+#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_S 0
+#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_XOSC 0x00000001
+#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_RCOSC 0x00000000
+
+//*****************************************************************************
+//
+// Register: DDI_0_OSC_O_CTL1
+//
+//*****************************************************************************
+// Field: [22:18] RCOSCHFCTRIMFRACT
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_W 5
+#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_M 0x007C0000
+#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_S 18
+
+// Field: [17] RCOSCHFCTRIMFRACT_EN
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN 0x00020000
+#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_M 0x00020000
+#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_S 17
+
+// Field: [1:0] XOSC_HF_FAST_START
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_W 2
+#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_M 0x00000003
+#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_S 0
+
+//*****************************************************************************
+//
+// Register: DDI_0_OSC_O_RADCEXTCFG
+//
+//*****************************************************************************
+// Field: [31:22] HPM_IBIAS_WAIT_CNT
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_W 10
+#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_M 0xFFC00000
+#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_S 22
+
+// Field: [21:16] LPM_IBIAS_WAIT_CNT
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_W 6
+#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_M 0x003F0000
+#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_S 16
+
+// Field: [15:12] IDAC_STEP
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_W 4
+#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_M 0x0000F000
+#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_S 12
+
+// Field: [11:6] RADC_DAC_TH
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_W 6
+#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_M 0x00000FC0
+#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_S 6
+
+// Field: [5] RADC_MODE_IS_SAR
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR 0x00000020
+#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR_M 0x00000020
+#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR_S 5
+
+//*****************************************************************************
+//
+// Register: DDI_0_OSC_O_AMPCOMPCTL
+//
+//*****************************************************************************
+// Field: [30] AMPCOMP_REQ_MODE
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE 0x40000000
+#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_M 0x40000000
+#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_S 30
+
+// Field: [29:28] AMPCOMP_FSM_UPDATE_RATE
+//
+// Internal. Only to be used through TI provided API.
+// ENUMs:
+// 250KHZ Internal. Only to be used through TI provided API.
+// 500KHZ Internal. Only to be used through TI provided API.
+// 1MHZ Internal. Only to be used through TI provided API.
+// 2MHZ Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_W 2
+#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_M 0x30000000
+#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_S 28
+#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_250KHZ 0x30000000
+#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_500KHZ 0x20000000
+#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_1MHZ 0x10000000
+#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_2MHZ 0x00000000
+
+// Field: [27] AMPCOMP_SW_CTRL
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL 0x08000000
+#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL_M 0x08000000
+#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL_S 27
+
+// Field: [26] AMPCOMP_SW_EN
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN 0x04000000
+#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN_M 0x04000000
+#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN_S 26
+
+// Field: [23:20] IBIAS_OFFSET
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_W 4
+#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M 0x00F00000
+#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S 20
+
+// Field: [19:16] IBIAS_INIT
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_W 4
+#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M 0x000F0000
+#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S 16
+
+// Field: [15:8] LPM_IBIAS_WAIT_CNT_FINAL
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_W 8
+#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_M 0x0000FF00
+#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_S 8
+
+// Field: [7:4] CAP_STEP
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_W 4
+#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_M 0x000000F0
+#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_S 4
+
+// Field: [3:0] IBIASCAP_HPTOLP_OL_CNT
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_W 4
+#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_M 0x0000000F
+#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_S 0
+
+//*****************************************************************************
+//
+// Register: DDI_0_OSC_O_AMPCOMPTH1
+//
+//*****************************************************************************
+// Field: [23:18] HPMRAMP3_LTH
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_W 6
+#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_M 0x00FC0000
+#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_S 18
+
+// Field: [15:10] HPMRAMP3_HTH
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_W 6
+#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_M 0x0000FC00
+#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_S 10
+
+// Field: [9:6] IBIASCAP_LPTOHP_OL_CNT
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_W 4
+#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_M 0x000003C0
+#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_S 6
+
+// Field: [5:0] HPMRAMP1_TH
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_W 6
+#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_M 0x0000003F
+#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_S 0
+
+//*****************************************************************************
+//
+// Register: DDI_0_OSC_O_AMPCOMPTH2
+//
+//*****************************************************************************
+// Field: [31:26] LPMUPDATE_LTH
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_W 6
+#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_M 0xFC000000
+#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_S 26
+
+// Field: [23:18] LPMUPDATE_HTH
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_W 6
+#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_M 0x00FC0000
+#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_S 18
+
+// Field: [15:10] ADC_COMP_AMPTH_LPM
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_W 6
+#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_M 0x0000FC00
+#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_S 10
+
+// Field: [7:2] ADC_COMP_AMPTH_HPM
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_W 6
+#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_M 0x000000FC
+#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_S 2
+
+//*****************************************************************************
+//
+// Register: DDI_0_OSC_O_ANABYPASSVAL1
+//
+//*****************************************************************************
+// Field: [19:16] XOSC_HF_ROW_Q12
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_W 4
+#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_M 0x000F0000
+#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_S 16
+
+// Field: [15:0] XOSC_HF_COLUMN_Q12
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_W 16
+#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_M 0x0000FFFF
+#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_S 0
+
+//*****************************************************************************
+//
+// Register: DDI_0_OSC_O_ANABYPASSVAL2
+//
+//*****************************************************************************
+// Field: [13:0] XOSC_HF_IBIASTHERM
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_W 14
+#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_M 0x00003FFF
+#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_S 0
+
+//*****************************************************************************
+//
+// Register: DDI_0_OSC_O_ATESTCTL
+//
+//*****************************************************************************
+// Field: [31] SCLK_LF_AUX_EN
+//
+// Enable 32 kHz clock to AUX_COMPB.
+#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN 0x80000000
+#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN_M 0x80000000
+#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN_S 31
+
+// Field: [15:14] TEST_RCOSCMF
+//
+// Test mode control for RCOSC_MF
+//
+// 0x0: test modes disabled
+// 0x1: boosted bias current into self biased inverter
+// 0x2: clock qualification disabled
+// 0x3: boosted bias current into self biased inverter + clock qualification
+// disabled
+#define DDI_0_OSC_ATESTCTL_TEST_RCOSCMF_W 2
+#define DDI_0_OSC_ATESTCTL_TEST_RCOSCMF_M 0x0000C000
+#define DDI_0_OSC_ATESTCTL_TEST_RCOSCMF_S 14
+
+// Field: [13:12] ATEST_RCOSCMF
+//
+// ATEST control for RCOSC_MF
+//
+// 0x0: ATEST disabled
+// 0x1: ATEST enabled, VDD_LOCAL connected, ATEST internal to **RCOSC_MF*
+// enabled to send out 2MHz clock.
+// 0x2: ATEST disabled
+// 0x3: ATEST enabled, bias current connected, ATEST internal to **RCOSC_MF*
+// enabled to send out 2MHz clock.
+#define DDI_0_OSC_ATESTCTL_ATEST_RCOSCMF_W 2
+#define DDI_0_OSC_ATESTCTL_ATEST_RCOSCMF_M 0x00003000
+#define DDI_0_OSC_ATESTCTL_ATEST_RCOSCMF_S 12
+
+//*****************************************************************************
+//
+// Register: DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL
+//
+//*****************************************************************************
+// Field: [24] NANOAMP_BIAS_ENABLE
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE 0x01000000
+#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE_M 0x01000000
+#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE_S 24
+
+// Field: [23] SPARE23
+//
+// Software should not rely on the value of a reserved. Writing any other value
+// than the reset value may result in undefined behavior
+#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23 0x00800000
+#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23_M 0x00800000
+#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23_S 23
+
+// Field: [5] ADC_SH_MODE_EN
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN 0x00000020
+#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN_M 0x00000020
+#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN_S 5
+
+// Field: [4] ADC_SH_VBUF_EN
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN 0x00000010
+#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN_M 0x00000010
+#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN_S 4
+
+// Field: [1:0] ADC_IREF_CTRL
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_W 2
+#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_M 0x00000003
+#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_S 0
+
+//*****************************************************************************
+//
+// Register: DDI_0_OSC_O_XOSCHFCTL
+//
+//*****************************************************************************
+// Field: [13] TCXO_MODE_XOSC_HF_EN
+//
+// If this register is 1 when TCXO_MODE is 1, then the XOSC_HF is enabled,
+// turning on the XOSC_HF bias current allowing a DC bias point to be provided
+// to the clipped-sine wave clock signal on external input.
+#define DDI_0_OSC_XOSCHFCTL_TCXO_MODE_XOSC_HF_EN 0x00002000
+#define DDI_0_OSC_XOSCHFCTL_TCXO_MODE_XOSC_HF_EN_M 0x00002000
+#define DDI_0_OSC_XOSCHFCTL_TCXO_MODE_XOSC_HF_EN_S 13
+
+// Field: [12] TCXO_MODE
+//
+// If this register is 1 when BYPASS is 1, this will enable clock
+// qualification on the TCXO clock on external input. This register has no
+// effect when BYPASS is 0.
+#define DDI_0_OSC_XOSCHFCTL_TCXO_MODE 0x00001000
+#define DDI_0_OSC_XOSCHFCTL_TCXO_MODE_M 0x00001000
+#define DDI_0_OSC_XOSCHFCTL_TCXO_MODE_S 12
+
+// Field: [9:8] PEAK_DET_ITRIM
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_W 2
+#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_M 0x00000300
+#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_S 8
+
+// Field: [6] BYPASS
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_XOSCHFCTL_BYPASS 0x00000040
+#define DDI_0_OSC_XOSCHFCTL_BYPASS_M 0x00000040
+#define DDI_0_OSC_XOSCHFCTL_BYPASS_S 6
+
+// Field: [4:2] HP_BUF_ITRIM
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_W 3
+#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_M 0x0000001C
+#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_S 2
+
+// Field: [1:0] LP_BUF_ITRIM
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_W 2
+#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_M 0x00000003
+#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_S 0
+
+//*****************************************************************************
+//
+// Register: DDI_0_OSC_O_LFOSCCTL
+//
+//*****************************************************************************
+// Field: [23:22] XOSCLF_REGULATOR_TRIM
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_W 2
+#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_M 0x00C00000
+#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_S 22
+
+// Field: [21:18] XOSCLF_CMIRRWR_RATIO
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_W 4
+#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_M 0x003C0000
+#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_S 18
+
+// Field: [9:8] RCOSCLF_RTUNE_TRIM
+//
+// Internal. Only to be used through TI provided API.
+// ENUMs:
+// 6P0MEG Internal. Only to be used through TI provided API.
+// 6P5MEG Internal. Only to be used through TI provided API.
+// 7P0MEG Internal. Only to be used through TI provided API.
+// 7P5MEG Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_W 2
+#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_M 0x00000300
+#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_S 8
+#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_6P0MEG 0x00000300
+#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_6P5MEG 0x00000200
+#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_7P0MEG 0x00000100
+#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_7P5MEG 0x00000000
+
+// Field: [7:0] RCOSCLF_CTUNE_TRIM
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_W 8
+#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_M 0x000000FF
+#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S 0
+
+//*****************************************************************************
+//
+// Register: DDI_0_OSC_O_RCOSCHFCTL
+//
+//*****************************************************************************
+// Field: [15:8] RCOSCHF_CTRIM
+//
+// Internal. Only to be used through TI provided API.
+#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_W 8
+#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_M 0x0000FF00
+#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_S 8
+
+//*****************************************************************************
+//
+// Register: DDI_0_OSC_O_RCOSCMFCTL
+//
+//*****************************************************************************
+// Field: [15:9] RCOSC_MF_CAP_ARRAY
+//
+// Adjust RCOSC_MF capacitor array.
+//
+// 0x0: nominal frequency, 0.625pF
+// 0x40: highest frequency, 0.125pF
+// 0x3F: lowest frequency, 1.125pF
+#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_CAP_ARRAY_W 7
+#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_CAP_ARRAY_M 0x0000FE00
+#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_CAP_ARRAY_S 9
+
+// Field: [8] RCOSC_MF_REG_SEL
+//
+// Choose regulator type.
+//
+// 0: default
+// 1: alternate
+#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_REG_SEL 0x00000100
+#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_REG_SEL_M 0x00000100
+#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_REG_SEL_S 8
+
+// Field: [7:6] RCOSC_MF_RES_COARSE
+//
+// Select coarse resistor for frequency adjustment.
+//
+// 0x0: 400kohms, default
+// 0x1: 300kohms, min
+// 0x2: 600kohms, max
+// 0x3: 500kohms
+#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_W 2
+#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_M 0x000000C0
+#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_S 6
+
+// Field: [5:4] RCOSC_MF_RES_FINE
+//
+// Select fine resistor for frequency adjustment.
+//
+// 0x0: 11kohms, minimum resistance, max freq
+// 0x1: 13kohms
+// 0x2: 16kohms
+// 0x3: 20kohms, max resistance, min freq
+#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_W 2
+#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_M 0x00000030
+#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_S 4
+
+// Field: [3:0] RCOSC_MF_BIAS_ADJ
+//
+// Adjusts bias current to RCOSC_MF.
+//
+// 0x8 minimum current
+// 0x0 default current
+// 0x7 maximum current
+#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_BIAS_ADJ_W 4
+#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_BIAS_ADJ_M 0x0000000F
+#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_BIAS_ADJ_S 0
+
+//*****************************************************************************
+//
+// Register: DDI_0_OSC_O_STAT0
+//
+//*****************************************************************************
+// Field: [30:29] SCLK_LF_SRC
+//
+// Indicates source for the sclk_lf
+// ENUMs:
+// XOSCLF Low frequency XOSC
+// RCOSCLF Low frequency RCOSC
+// XOSCHFDLF Low frequency clock derived from High Frequency
+// XOSC
+// RCOSCHFDLF Low frequency clock derived from High Frequency
+// RCOSC
+#define DDI_0_OSC_STAT0_SCLK_LF_SRC_W 2
+#define DDI_0_OSC_STAT0_SCLK_LF_SRC_M 0x60000000
+#define DDI_0_OSC_STAT0_SCLK_LF_SRC_S 29
+#define DDI_0_OSC_STAT0_SCLK_LF_SRC_XOSCLF 0x60000000
+#define DDI_0_OSC_STAT0_SCLK_LF_SRC_RCOSCLF 0x40000000
+#define DDI_0_OSC_STAT0_SCLK_LF_SRC_XOSCHFDLF 0x20000000
+#define DDI_0_OSC_STAT0_SCLK_LF_SRC_RCOSCHFDLF 0x00000000
+
+// Field: [28] SCLK_HF_SRC
+//
+// Indicates source for the sclk_hf
+// ENUMs:
+// XOSC High frequency XOSC
+// RCOSC High frequency RCOSC clock
+#define DDI_0_OSC_STAT0_SCLK_HF_SRC 0x10000000
+#define DDI_0_OSC_STAT0_SCLK_HF_SRC_M 0x10000000
+#define DDI_0_OSC_STAT0_SCLK_HF_SRC_S 28
+#define DDI_0_OSC_STAT0_SCLK_HF_SRC_XOSC 0x10000000
+#define DDI_0_OSC_STAT0_SCLK_HF_SRC_RCOSC 0x00000000
+
+// Field: [22] RCOSC_HF_EN
+//
+// RCOSC_HF_EN
+#define DDI_0_OSC_STAT0_RCOSC_HF_EN 0x00400000
+#define DDI_0_OSC_STAT0_RCOSC_HF_EN_M 0x00400000
+#define DDI_0_OSC_STAT0_RCOSC_HF_EN_S 22
+
+// Field: [21] RCOSC_LF_EN
+//
+// RCOSC_LF_EN
+#define DDI_0_OSC_STAT0_RCOSC_LF_EN 0x00200000
+#define DDI_0_OSC_STAT0_RCOSC_LF_EN_M 0x00200000
+#define DDI_0_OSC_STAT0_RCOSC_LF_EN_S 21
+
+// Field: [20] XOSC_LF_EN
+//
+// XOSC_LF_EN
+#define DDI_0_OSC_STAT0_XOSC_LF_EN 0x00100000
+#define DDI_0_OSC_STAT0_XOSC_LF_EN_M 0x00100000
+#define DDI_0_OSC_STAT0_XOSC_LF_EN_S 20
+
+// Field: [19] CLK_DCDC_RDY
+//
+// CLK_DCDC_RDY
+#define DDI_0_OSC_STAT0_CLK_DCDC_RDY 0x00080000
+#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_M 0x00080000
+#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_S 19
+
+// Field: [18] CLK_DCDC_RDY_ACK
+//
+// CLK_DCDC_RDY_ACK
+#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK 0x00040000
+#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK_M 0x00040000
+#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK_S 18
+
+// Field: [17] SCLK_HF_LOSS
+//
+// Indicates sclk_hf is lost
+#define DDI_0_OSC_STAT0_SCLK_HF_LOSS 0x00020000
+#define DDI_0_OSC_STAT0_SCLK_HF_LOSS_M 0x00020000
+#define DDI_0_OSC_STAT0_SCLK_HF_LOSS_S 17
+
+// Field: [16] SCLK_LF_LOSS
+//
+// Indicates sclk_lf is lost
+#define DDI_0_OSC_STAT0_SCLK_LF_LOSS 0x00010000
+#define DDI_0_OSC_STAT0_SCLK_LF_LOSS_M 0x00010000
+#define DDI_0_OSC_STAT0_SCLK_LF_LOSS_S 16
+
+// Field: [15] XOSC_HF_EN
+//
+// Indicates that XOSC_HF is enabled.
+#define DDI_0_OSC_STAT0_XOSC_HF_EN 0x00008000
+#define DDI_0_OSC_STAT0_XOSC_HF_EN_M 0x00008000
+#define DDI_0_OSC_STAT0_XOSC_HF_EN_S 15
+
+// Field: [13] XB_48M_CLK_EN
+//
+// Indicates that the 48MHz clock from the DOUBLER is enabled.
+//
+// It will be enabled if 24 or 48 MHz crystal is used (enabled in doubler
+// bypass for the 48MHz crystal).
+#define DDI_0_OSC_STAT0_XB_48M_CLK_EN 0x00002000
+#define DDI_0_OSC_STAT0_XB_48M_CLK_EN_M 0x00002000
+#define DDI_0_OSC_STAT0_XB_48M_CLK_EN_S 13
+
+// Field: [11] XOSC_HF_LP_BUF_EN
+//
+// XOSC_HF_LP_BUF_EN
+#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN 0x00000800
+#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN_M 0x00000800
+#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN_S 11
+
+// Field: [10] XOSC_HF_HP_BUF_EN
+//
+// XOSC_HF_HP_BUF_EN
+#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN 0x00000400
+#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN_M 0x00000400
+#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN_S 10
+
+// Field: [8] ADC_THMET
+//
+// ADC_THMET
+#define DDI_0_OSC_STAT0_ADC_THMET 0x00000100
+#define DDI_0_OSC_STAT0_ADC_THMET_M 0x00000100
+#define DDI_0_OSC_STAT0_ADC_THMET_S 8
+
+// Field: [7] ADC_DATA_READY
+//
+// indicates when adc_data is ready.
+#define DDI_0_OSC_STAT0_ADC_DATA_READY 0x00000080
+#define DDI_0_OSC_STAT0_ADC_DATA_READY_M 0x00000080
+#define DDI_0_OSC_STAT0_ADC_DATA_READY_S 7
+
+// Field: [6:1] ADC_DATA
+//
+// adc_data
+#define DDI_0_OSC_STAT0_ADC_DATA_W 6
+#define DDI_0_OSC_STAT0_ADC_DATA_M 0x0000007E
+#define DDI_0_OSC_STAT0_ADC_DATA_S 1
+
+// Field: [0] PENDINGSCLKHFSWITCHING
+//
+// Indicates when SCLK_HF clock source is ready to be switched
+#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING 0x00000001
+#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_M 0x00000001
+#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_S 0
+
+//*****************************************************************************
+//
+// Register: DDI_0_OSC_O_STAT1
+//
+//*****************************************************************************
+// Field: [31:28] RAMPSTATE
+//
+// AMPCOMP FSM State
+// ENUMs:
+// FAST_START_SETTLE FAST_START_SETTLE
+// FAST_START FAST_START
+// DUMMY_TO_INIT_1 DUMMY_TO_INIT_1
+// IDAC_DEC_W_MEASURE IDAC_DECREMENT_WITH_MEASURE
+// IBIAS_INC IBIAS_INCREMENT
+// LPM_UPDATE LPM_UPDATE
+// IBIAS_DEC_W_MEASURE IBIAS_DECREMENT_WITH_MEASURE
+// IBIAS_CAP_UPDATE IBIAS_CAP_UPDATE
+// IDAC_INCREMENT IDAC_INCREMENT
+// HPM_UPDATE HPM_UPDATE
+// HPM_RAMP3 HPM_RAMP3
+// HPM_RAMP2 HPM_RAMP2
+// HPM_RAMP1 HPM_RAMP1
+// INITIALIZATION INITIALIZATION
+// RESET RESET
+#define DDI_0_OSC_STAT1_RAMPSTATE_W 4
+#define DDI_0_OSC_STAT1_RAMPSTATE_M 0xF0000000
+#define DDI_0_OSC_STAT1_RAMPSTATE_S 28
+#define DDI_0_OSC_STAT1_RAMPSTATE_FAST_START_SETTLE 0xE0000000
+#define DDI_0_OSC_STAT1_RAMPSTATE_FAST_START 0xD0000000
+#define DDI_0_OSC_STAT1_RAMPSTATE_DUMMY_TO_INIT_1 0xC0000000
+#define DDI_0_OSC_STAT1_RAMPSTATE_IDAC_DEC_W_MEASURE 0xB0000000
+#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_INC 0xA0000000
+#define DDI_0_OSC_STAT1_RAMPSTATE_LPM_UPDATE 0x90000000
+#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_DEC_W_MEASURE 0x80000000
+#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_CAP_UPDATE 0x70000000
+#define DDI_0_OSC_STAT1_RAMPSTATE_IDAC_INCREMENT 0x60000000
+#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_UPDATE 0x50000000
+#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP3 0x40000000
+#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP2 0x30000000
+#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP1 0x20000000
+#define DDI_0_OSC_STAT1_RAMPSTATE_INITIALIZATION 0x10000000
+#define DDI_0_OSC_STAT1_RAMPSTATE_RESET 0x00000000
+
+// Field: [27:22] HPM_UPDATE_AMP
+//
+// XOSC_HF amplitude during HPM_UPDATE state.
+// When amplitude compensation of XOSC_HF is enabled in high performance mode,
+// this value is the amplitude of the crystal oscillations measured by the
+// on-chip oscillator ADC, divided by 15 mV. For example, a value of 0x20
+// would indicate that the amplitude of the crystal is approximately 480 mV.
+// To enable amplitude compensation, AON_WUC OSCCFG must be set to a non-zero
+// value.
+#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_W 6
+#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_M 0x0FC00000
+#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_S 22
+
+// Field: [21:16] LPM_UPDATE_AMP
+//
+// XOSC_HF amplitude during LPM_UPDATE state
+// When amplitude compensation of XOSC_HF is enabled in low power mode, this
+// value is the amplitude of the crystal oscillations measured by the on-chip
+// oscillator ADC, divided by 15 mV. For example, a value of 0x20 would
+// indicate that the amplitude of the crystal is approximately 480 mV. To
+// enable amplitude compensation, AON_WUC OSCCFG must be set to a non-zero
+// value.
+#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_W 6
+#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_M 0x003F0000
+#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_S 16
+
+// Field: [15] FORCE_RCOSC_HF
+//
+// force_rcosc_hf
+#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF 0x00008000
+#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF_M 0x00008000
+#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF_S 15
+
+// Field: [14] SCLK_HF_EN
+//
+// SCLK_HF_EN
+#define DDI_0_OSC_STAT1_SCLK_HF_EN 0x00004000
+#define DDI_0_OSC_STAT1_SCLK_HF_EN_M 0x00004000
+#define DDI_0_OSC_STAT1_SCLK_HF_EN_S 14
+
+// Field: [13] SCLK_MF_EN
+//
+// SCLK_MF_EN
+#define DDI_0_OSC_STAT1_SCLK_MF_EN 0x00002000
+#define DDI_0_OSC_STAT1_SCLK_MF_EN_M 0x00002000
+#define DDI_0_OSC_STAT1_SCLK_MF_EN_S 13
+
+// Field: [12] ACLK_ADC_EN
+//
+// ACLK_ADC_EN
+#define DDI_0_OSC_STAT1_ACLK_ADC_EN 0x00001000
+#define DDI_0_OSC_STAT1_ACLK_ADC_EN_M 0x00001000
+#define DDI_0_OSC_STAT1_ACLK_ADC_EN_S 12
+
+// Field: [11] ACLK_TDC_EN
+//
+// ACLK_TDC_EN
+#define DDI_0_OSC_STAT1_ACLK_TDC_EN 0x00000800
+#define DDI_0_OSC_STAT1_ACLK_TDC_EN_M 0x00000800
+#define DDI_0_OSC_STAT1_ACLK_TDC_EN_S 11
+
+// Field: [10] ACLK_REF_EN
+//
+// ACLK_REF_EN
+#define DDI_0_OSC_STAT1_ACLK_REF_EN 0x00000400
+#define DDI_0_OSC_STAT1_ACLK_REF_EN_M 0x00000400
+#define DDI_0_OSC_STAT1_ACLK_REF_EN_S 10
+
+// Field: [9] CLK_CHP_EN
+//
+// CLK_CHP_EN
+#define DDI_0_OSC_STAT1_CLK_CHP_EN 0x00000200
+#define DDI_0_OSC_STAT1_CLK_CHP_EN_M 0x00000200
+#define DDI_0_OSC_STAT1_CLK_CHP_EN_S 9
+
+// Field: [8] CLK_DCDC_EN
+//
+// CLK_DCDC_EN
+#define DDI_0_OSC_STAT1_CLK_DCDC_EN 0x00000100
+#define DDI_0_OSC_STAT1_CLK_DCDC_EN_M 0x00000100
+#define DDI_0_OSC_STAT1_CLK_DCDC_EN_S 8
+
+// Field: [7] SCLK_HF_GOOD
+//
+// SCLK_HF_GOOD
+#define DDI_0_OSC_STAT1_SCLK_HF_GOOD 0x00000080
+#define DDI_0_OSC_STAT1_SCLK_HF_GOOD_M 0x00000080
+#define DDI_0_OSC_STAT1_SCLK_HF_GOOD_S 7
+
+// Field: [6] SCLK_MF_GOOD
+//
+// SCLK_MF_GOOD
+#define DDI_0_OSC_STAT1_SCLK_MF_GOOD 0x00000040
+#define DDI_0_OSC_STAT1_SCLK_MF_GOOD_M 0x00000040
+#define DDI_0_OSC_STAT1_SCLK_MF_GOOD_S 6
+
+// Field: [5] SCLK_LF_GOOD
+//
+// SCLK_LF_GOOD
+#define DDI_0_OSC_STAT1_SCLK_LF_GOOD 0x00000020
+#define DDI_0_OSC_STAT1_SCLK_LF_GOOD_M 0x00000020
+#define DDI_0_OSC_STAT1_SCLK_LF_GOOD_S 5
+
+// Field: [4] ACLK_ADC_GOOD
+//
+// ACLK_ADC_GOOD
+#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD 0x00000010
+#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD_M 0x00000010
+#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD_S 4
+
+// Field: [3] ACLK_TDC_GOOD
+//
+// ACLK_TDC_GOOD
+#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD 0x00000008
+#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD_M 0x00000008
+#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD_S 3
+
+// Field: [2] ACLK_REF_GOOD
+//
+// ACLK_REF_GOOD.
+#define DDI_0_OSC_STAT1_ACLK_REF_GOOD 0x00000004
+#define DDI_0_OSC_STAT1_ACLK_REF_GOOD_M 0x00000004
+#define DDI_0_OSC_STAT1_ACLK_REF_GOOD_S 2
+
+// Field: [1] CLK_CHP_GOOD
+//
+// CLK_CHP_GOOD
+#define DDI_0_OSC_STAT1_CLK_CHP_GOOD 0x00000002
+#define DDI_0_OSC_STAT1_CLK_CHP_GOOD_M 0x00000002
+#define DDI_0_OSC_STAT1_CLK_CHP_GOOD_S 1
+
+// Field: [0] CLK_DCDC_GOOD
+//
+// CLK_DCDC_GOOD
+#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD 0x00000001
+#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD_M 0x00000001
+#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD_S 0
+
+//*****************************************************************************
+//
+// Register: DDI_0_OSC_O_STAT2
+//
+//*****************************************************************************
+// Field: [31:26] ADC_DCBIAS
+//
+// DC Bias read by RADC during SAR mode
+// The value is an unsigned integer. It is used for debug only.
+#define DDI_0_OSC_STAT2_ADC_DCBIAS_W 6
+#define DDI_0_OSC_STAT2_ADC_DCBIAS_M 0xFC000000
+#define DDI_0_OSC_STAT2_ADC_DCBIAS_S 26
+
+// Field: [25] HPM_RAMP1_THMET
+//
+// Indication of threshold is met for hpm_ramp1
+#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET 0x02000000
+#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET_M 0x02000000
+#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET_S 25
+
+// Field: [24] HPM_RAMP2_THMET
+//
+// Indication of threshold is met for hpm_ramp2
+#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET 0x01000000
+#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET_M 0x01000000
+#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET_S 24
+
+// Field: [23] HPM_RAMP3_THMET
+//
+// Indication of threshold is met for hpm_ramp3
+#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET 0x00800000
+#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET_M 0x00800000
+#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET_S 23
+
+// Field: [15:12] RAMPSTATE
+//
+// xosc_hf amplitude compensation FSM
+//
+// This is identical to STAT1.RAMPSTATE. See that description for encoding.
+#define DDI_0_OSC_STAT2_RAMPSTATE_W 4
+#define DDI_0_OSC_STAT2_RAMPSTATE_M 0x0000F000
+#define DDI_0_OSC_STAT2_RAMPSTATE_S 12
+
+// Field: [3] AMPCOMP_REQ
+//
+// ampcomp_req
+#define DDI_0_OSC_STAT2_AMPCOMP_REQ 0x00000008
+#define DDI_0_OSC_STAT2_AMPCOMP_REQ_M 0x00000008
+#define DDI_0_OSC_STAT2_AMPCOMP_REQ_S 3
+
+// Field: [2] XOSC_HF_AMPGOOD
+//
+// amplitude of xosc_hf is within the required threshold (set by DDI). Not used
+// for anything just for debug/status
+#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD 0x00000004
+#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD_M 0x00000004
+#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD_S 2
+
+// Field: [1] XOSC_HF_FREQGOOD
+//
+// frequency of xosc_hf is good to use for the digital clocks
+#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD 0x00000002
+#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD_M 0x00000002
+#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD_S 1
+
+// Field: [0] XOSC_HF_RF_FREQGOOD
+//
+// frequency of xosc_hf is within +/- 20 ppm and xosc_hf is good for radio
+// operations. Used for SW to start synthesizer.
+#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD 0x00000001
+#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD_M 0x00000001
+#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD_S 0
+
+
+#endif // __DDI_0_OSC__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_event.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_event.h
new file mode 100644
index 0000000..754774f
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_event.h
@@ -0,0 +1,3688 @@
+/******************************************************************************
+* Filename: hw_event_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_EVENT_H__
+#define __HW_EVENT_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// EVENT component
+//
+//*****************************************************************************
+// Output Selection for CPU Interrupt 0
+#define EVENT_O_CPUIRQSEL0 0x00000000
+
+// Output Selection for CPU Interrupt 1
+#define EVENT_O_CPUIRQSEL1 0x00000004
+
+// Output Selection for CPU Interrupt 2
+#define EVENT_O_CPUIRQSEL2 0x00000008
+
+// Output Selection for CPU Interrupt 3
+#define EVENT_O_CPUIRQSEL3 0x0000000C
+
+// Output Selection for CPU Interrupt 4
+#define EVENT_O_CPUIRQSEL4 0x00000010
+
+// Output Selection for CPU Interrupt 5
+#define EVENT_O_CPUIRQSEL5 0x00000014
+
+// Output Selection for CPU Interrupt 6
+#define EVENT_O_CPUIRQSEL6 0x00000018
+
+// Output Selection for CPU Interrupt 7
+#define EVENT_O_CPUIRQSEL7 0x0000001C
+
+// Output Selection for CPU Interrupt 8
+#define EVENT_O_CPUIRQSEL8 0x00000020
+
+// Output Selection for CPU Interrupt 9
+#define EVENT_O_CPUIRQSEL9 0x00000024
+
+// Output Selection for CPU Interrupt 10
+#define EVENT_O_CPUIRQSEL10 0x00000028
+
+// Output Selection for CPU Interrupt 11
+#define EVENT_O_CPUIRQSEL11 0x0000002C
+
+// Output Selection for CPU Interrupt 12
+#define EVENT_O_CPUIRQSEL12 0x00000030
+
+// Output Selection for CPU Interrupt 13
+#define EVENT_O_CPUIRQSEL13 0x00000034
+
+// Output Selection for CPU Interrupt 14
+#define EVENT_O_CPUIRQSEL14 0x00000038
+
+// Output Selection for CPU Interrupt 15
+#define EVENT_O_CPUIRQSEL15 0x0000003C
+
+// Output Selection for CPU Interrupt 16
+#define EVENT_O_CPUIRQSEL16 0x00000040
+
+// Output Selection for CPU Interrupt 17
+#define EVENT_O_CPUIRQSEL17 0x00000044
+
+// Output Selection for CPU Interrupt 18
+#define EVENT_O_CPUIRQSEL18 0x00000048
+
+// Output Selection for CPU Interrupt 19
+#define EVENT_O_CPUIRQSEL19 0x0000004C
+
+// Output Selection for CPU Interrupt 20
+#define EVENT_O_CPUIRQSEL20 0x00000050
+
+// Output Selection for CPU Interrupt 21
+#define EVENT_O_CPUIRQSEL21 0x00000054
+
+// Output Selection for CPU Interrupt 22
+#define EVENT_O_CPUIRQSEL22 0x00000058
+
+// Output Selection for CPU Interrupt 23
+#define EVENT_O_CPUIRQSEL23 0x0000005C
+
+// Output Selection for CPU Interrupt 24
+#define EVENT_O_CPUIRQSEL24 0x00000060
+
+// Output Selection for CPU Interrupt 25
+#define EVENT_O_CPUIRQSEL25 0x00000064
+
+// Output Selection for CPU Interrupt 26
+#define EVENT_O_CPUIRQSEL26 0x00000068
+
+// Output Selection for CPU Interrupt 27
+#define EVENT_O_CPUIRQSEL27 0x0000006C
+
+// Output Selection for CPU Interrupt 28
+#define EVENT_O_CPUIRQSEL28 0x00000070
+
+// Output Selection for CPU Interrupt 29
+#define EVENT_O_CPUIRQSEL29 0x00000074
+
+// Output Selection for CPU Interrupt 30
+#define EVENT_O_CPUIRQSEL30 0x00000078
+
+// Output Selection for CPU Interrupt 31
+#define EVENT_O_CPUIRQSEL31 0x0000007C
+
+// Output Selection for CPU Interrupt 32
+#define EVENT_O_CPUIRQSEL32 0x00000080
+
+// Output Selection for CPU Interrupt 33
+#define EVENT_O_CPUIRQSEL33 0x00000084
+
+// Output Selection for CPU Interrupt 34
+#define EVENT_O_CPUIRQSEL34 0x00000088
+
+// Output Selection for CPU Interrupt 35
+#define EVENT_O_CPUIRQSEL35 0x0000008C
+
+// Output Selection for CPU Interrupt 36
+#define EVENT_O_CPUIRQSEL36 0x00000090
+
+// Output Selection for CPU Interrupt 37
+#define EVENT_O_CPUIRQSEL37 0x00000094
+
+// Output Selection for RFC Event 0
+#define EVENT_O_RFCSEL0 0x00000100
+
+// Output Selection for RFC Event 1
+#define EVENT_O_RFCSEL1 0x00000104
+
+// Output Selection for RFC Event 2
+#define EVENT_O_RFCSEL2 0x00000108
+
+// Output Selection for RFC Event 3
+#define EVENT_O_RFCSEL3 0x0000010C
+
+// Output Selection for RFC Event 4
+#define EVENT_O_RFCSEL4 0x00000110
+
+// Output Selection for RFC Event 5
+#define EVENT_O_RFCSEL5 0x00000114
+
+// Output Selection for RFC Event 6
+#define EVENT_O_RFCSEL6 0x00000118
+
+// Output Selection for RFC Event 7
+#define EVENT_O_RFCSEL7 0x0000011C
+
+// Output Selection for RFC Event 8
+#define EVENT_O_RFCSEL8 0x00000120
+
+// Output Selection for RFC Event 9
+#define EVENT_O_RFCSEL9 0x00000124
+
+// Output Selection for GPT0 0
+#define EVENT_O_GPT0ACAPTSEL 0x00000200
+
+// Output Selection for GPT0 1
+#define EVENT_O_GPT0BCAPTSEL 0x00000204
+
+// Output Selection for GPT1 0
+#define EVENT_O_GPT1ACAPTSEL 0x00000300
+
+// Output Selection for GPT1 1
+#define EVENT_O_GPT1BCAPTSEL 0x00000304
+
+// Output Selection for GPT2 0
+#define EVENT_O_GPT2ACAPTSEL 0x00000400
+
+// Output Selection for GPT2 1
+#define EVENT_O_GPT2BCAPTSEL 0x00000404
+
+// Output Selection for DMA Channel 1 SREQ
+#define EVENT_O_UDMACH1SSEL 0x00000508
+
+// Output Selection for DMA Channel 1 REQ
+#define EVENT_O_UDMACH1BSEL 0x0000050C
+
+// Output Selection for DMA Channel 2 SREQ
+#define EVENT_O_UDMACH2SSEL 0x00000510
+
+// Output Selection for DMA Channel 2 REQ
+#define EVENT_O_UDMACH2BSEL 0x00000514
+
+// Output Selection for DMA Channel 3 SREQ
+#define EVENT_O_UDMACH3SSEL 0x00000518
+
+// Output Selection for DMA Channel 3 REQ
+#define EVENT_O_UDMACH3BSEL 0x0000051C
+
+// Output Selection for DMA Channel 4 SREQ
+#define EVENT_O_UDMACH4SSEL 0x00000520
+
+// Output Selection for DMA Channel 4 REQ
+#define EVENT_O_UDMACH4BSEL 0x00000524
+
+// Output Selection for DMA Channel 5 SREQ
+#define EVENT_O_UDMACH5SSEL 0x00000528
+
+// Output Selection for DMA Channel 5 REQ
+#define EVENT_O_UDMACH5BSEL 0x0000052C
+
+// Output Selection for DMA Channel 6 SREQ
+#define EVENT_O_UDMACH6SSEL 0x00000530
+
+// Output Selection for DMA Channel 6 REQ
+#define EVENT_O_UDMACH6BSEL 0x00000534
+
+// Output Selection for DMA Channel 7 SREQ
+#define EVENT_O_UDMACH7SSEL 0x00000538
+
+// Output Selection for DMA Channel 7 REQ
+#define EVENT_O_UDMACH7BSEL 0x0000053C
+
+// Output Selection for DMA Channel 8 SREQ
+#define EVENT_O_UDMACH8SSEL 0x00000540
+
+// Output Selection for DMA Channel 8 REQ
+#define EVENT_O_UDMACH8BSEL 0x00000544
+
+// Output Selection for DMA Channel 9 SREQ
+#define EVENT_O_UDMACH9SSEL 0x00000548
+
+// Output Selection for DMA Channel 9 REQ
+#define EVENT_O_UDMACH9BSEL 0x0000054C
+
+// Output Selection for DMA Channel 10 SREQ
+#define EVENT_O_UDMACH10SSEL 0x00000550
+
+// Output Selection for DMA Channel 10 REQ
+#define EVENT_O_UDMACH10BSEL 0x00000554
+
+// Output Selection for DMA Channel 11 SREQ
+#define EVENT_O_UDMACH11SSEL 0x00000558
+
+// Output Selection for DMA Channel 11 REQ
+#define EVENT_O_UDMACH11BSEL 0x0000055C
+
+// Output Selection for DMA Channel 12 SREQ
+#define EVENT_O_UDMACH12SSEL 0x00000560
+
+// Output Selection for DMA Channel 12 REQ
+#define EVENT_O_UDMACH12BSEL 0x00000564
+
+// Output Selection for DMA Channel 13 REQ
+#define EVENT_O_UDMACH13BSEL 0x0000056C
+
+// Output Selection for DMA Channel 14 REQ
+#define EVENT_O_UDMACH14BSEL 0x00000574
+
+// Output Selection for DMA Channel 15 REQ
+#define EVENT_O_UDMACH15BSEL 0x0000057C
+
+// Output Selection for DMA Channel 16 SREQ
+#define EVENT_O_UDMACH16SSEL 0x00000580
+
+// Output Selection for DMA Channel 16 REQ
+#define EVENT_O_UDMACH16BSEL 0x00000584
+
+// Output Selection for DMA Channel 17 SREQ
+#define EVENT_O_UDMACH17SSEL 0x00000588
+
+// Output Selection for DMA Channel 17 REQ
+#define EVENT_O_UDMACH17BSEL 0x0000058C
+
+// Output Selection for DMA Channel 21 SREQ
+#define EVENT_O_UDMACH21SSEL 0x000005A8
+
+// Output Selection for DMA Channel 21 REQ
+#define EVENT_O_UDMACH21BSEL 0x000005AC
+
+// Output Selection for DMA Channel 22 SREQ
+#define EVENT_O_UDMACH22SSEL 0x000005B0
+
+// Output Selection for DMA Channel 22 REQ
+#define EVENT_O_UDMACH22BSEL 0x000005B4
+
+// Output Selection for DMA Channel 23 SREQ
+#define EVENT_O_UDMACH23SSEL 0x000005B8
+
+// Output Selection for DMA Channel 23 REQ
+#define EVENT_O_UDMACH23BSEL 0x000005BC
+
+// Output Selection for DMA Channel 24 SREQ
+#define EVENT_O_UDMACH24SSEL 0x000005C0
+
+// Output Selection for DMA Channel 24 REQ
+#define EVENT_O_UDMACH24BSEL 0x000005C4
+
+// Output Selection for GPT3 0
+#define EVENT_O_GPT3ACAPTSEL 0x00000600
+
+// Output Selection for GPT3 1
+#define EVENT_O_GPT3BCAPTSEL 0x00000604
+
+// Output Selection for AUX Subscriber 0
+#define EVENT_O_AUXSEL0 0x00000700
+
+// Output Selection for NMI Subscriber 0
+#define EVENT_O_CM3NMISEL0 0x00000800
+
+// Output Selection for I2S Subscriber 0
+#define EVENT_O_I2SSTMPSEL0 0x00000900
+
+// Output Selection for FRZ Subscriber
+#define EVENT_O_FRZSEL0 0x00000A00
+
+// Set or Clear Software Events
+#define EVENT_O_SWEV 0x00000F00
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL0
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the
+// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET
+// settings
+#define EVENT_CPUIRQSEL0_EV_W 7
+#define EVENT_CPUIRQSEL0_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL0_EV_S 0
+#define EVENT_CPUIRQSEL0_EV_AON_GPIO_EDGE 0x00000004
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL1
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// I2C_IRQ Interrupt event from I2C
+#define EVENT_CPUIRQSEL1_EV_W 7
+#define EVENT_CPUIRQSEL1_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL1_EV_S 0
+#define EVENT_CPUIRQSEL1_EV_I2C_IRQ 0x00000009
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL2
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// RFC_CPE_1 Combined Interrupt for CPE Generated events.
+// Corresponding flags are here
+// RFC_DBELL:RFCPEIFG. Only interrupts selected
+// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a
+// RFC_CPE_1 event
+#define EVENT_CPUIRQSEL2_EV_W 7
+#define EVENT_CPUIRQSEL2_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL2_EV_S 0
+#define EVENT_CPUIRQSEL2_EV_RFC_CPE_1 0x0000001E
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL3
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// PKA_IRQ PKA Interrupt event
+#define EVENT_CPUIRQSEL3_EV_W 7
+#define EVENT_CPUIRQSEL3_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL3_EV_S 0
+#define EVENT_CPUIRQSEL3_EV_PKA_IRQ 0x0000001F
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL4
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// AON_RTC_COMB Event from AON_RTC, controlled by the
+// AON_RTC:CTL.COMB_EV_MASK setting
+#define EVENT_CPUIRQSEL4_EV_W 7
+#define EVENT_CPUIRQSEL4_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL4_EV_S 0
+#define EVENT_CPUIRQSEL4_EV_AON_RTC_COMB 0x00000007
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL5
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// UART0_COMB UART0 combined interrupt, interrupt flags are
+// found here UART0:MIS
+#define EVENT_CPUIRQSEL5_EV_W 7
+#define EVENT_CPUIRQSEL5_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL5_EV_S 0
+#define EVENT_CPUIRQSEL5_EV_UART0_COMB 0x00000024
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL6
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// AUX_SWEV0 AUX software event 0, triggered by
+// AUX_EVCTL:SWEVSET.SWEV0, also available as
+// AUX_EVENT0 AON wake up event.
+// MCU domain wakeup control
+// AON_EVENT:MCUWUSEL
+#define EVENT_CPUIRQSEL6_EV_W 7
+#define EVENT_CPUIRQSEL6_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL6_EV_S 0
+#define EVENT_CPUIRQSEL6_EV_AUX_SWEV0 0x0000001C
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL7
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// SSI0_COMB SSI0 combined interrupt, interrupt flags are found
+// here SSI0:MIS
+#define EVENT_CPUIRQSEL7_EV_W 7
+#define EVENT_CPUIRQSEL7_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL7_EV_S 0
+#define EVENT_CPUIRQSEL7_EV_SSI0_COMB 0x00000022
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL8
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// SSI1_COMB SSI1 combined interrupt, interrupt flags are found
+// here SSI1:MIS
+#define EVENT_CPUIRQSEL8_EV_W 7
+#define EVENT_CPUIRQSEL8_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL8_EV_S 0
+#define EVENT_CPUIRQSEL8_EV_SSI1_COMB 0x00000023
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL9
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// RFC_CPE_0 Combined Interrupt for CPE Generated events.
+// Corresponding flags are here
+// RFC_DBELL:RFCPEIFG. Only interrupts selected
+// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a
+// RFC_CPE_0 event
+#define EVENT_CPUIRQSEL9_EV_W 7
+#define EVENT_CPUIRQSEL9_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL9_EV_S 0
+#define EVENT_CPUIRQSEL9_EV_RFC_CPE_0 0x0000001B
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL10
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// RFC_HW_COMB Combined RFC hardware interrupt, corresponding
+// flag is here RFC_DBELL:RFHWIFG
+#define EVENT_CPUIRQSEL10_EV_W 7
+#define EVENT_CPUIRQSEL10_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL10_EV_S 0
+#define EVENT_CPUIRQSEL10_EV_RFC_HW_COMB 0x0000001A
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL11
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt,
+// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG
+#define EVENT_CPUIRQSEL11_EV_W 7
+#define EVENT_CPUIRQSEL11_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL11_EV_S 0
+#define EVENT_CPUIRQSEL11_EV_RFC_CMD_ACK 0x00000019
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL12
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// I2S_IRQ Interrupt event from I2S
+#define EVENT_CPUIRQSEL12_EV_W 7
+#define EVENT_CPUIRQSEL12_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL12_EV_S 0
+#define EVENT_CPUIRQSEL12_EV_I2S_IRQ 0x00000008
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL13
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// AUX_SWEV1 AUX software event 1, triggered by
+// AUX_EVCTL:SWEVSET.SWEV1, also available as
+// AUX_EVENT2 AON wake up event.
+// MCU domain wakeup control
+// AON_EVENT:MCUWUSEL
+#define EVENT_CPUIRQSEL13_EV_W 7
+#define EVENT_CPUIRQSEL13_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL13_EV_S 0
+#define EVENT_CPUIRQSEL13_EV_AUX_SWEV1 0x0000001D
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL14
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// WDT_IRQ Watchdog interrupt event, controlled by
+// WDT:CTL.INTEN
+#define EVENT_CPUIRQSEL14_EV_W 7
+#define EVENT_CPUIRQSEL14_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL14_EV_S 0
+#define EVENT_CPUIRQSEL14_EV_WDT_IRQ 0x00000018
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL15
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// GPT0A GPT0A interrupt event, controlled by GPT0:TAMR
+#define EVENT_CPUIRQSEL15_EV_W 7
+#define EVENT_CPUIRQSEL15_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL15_EV_S 0
+#define EVENT_CPUIRQSEL15_EV_GPT0A 0x00000010
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL16
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// GPT0B GPT0B interrupt event, controlled by GPT0:TBMR
+#define EVENT_CPUIRQSEL16_EV_W 7
+#define EVENT_CPUIRQSEL16_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL16_EV_S 0
+#define EVENT_CPUIRQSEL16_EV_GPT0B 0x00000011
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL17
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// GPT1A GPT1A interrupt event, controlled by GPT1:TAMR
+#define EVENT_CPUIRQSEL17_EV_W 7
+#define EVENT_CPUIRQSEL17_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL17_EV_S 0
+#define EVENT_CPUIRQSEL17_EV_GPT1A 0x00000012
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL18
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// GPT1B GPT1B interrupt event, controlled by GPT1:TBMR
+#define EVENT_CPUIRQSEL18_EV_W 7
+#define EVENT_CPUIRQSEL18_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL18_EV_S 0
+#define EVENT_CPUIRQSEL18_EV_GPT1B 0x00000013
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL19
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// GPT2A GPT2A interrupt event, controlled by GPT2:TAMR
+#define EVENT_CPUIRQSEL19_EV_W 7
+#define EVENT_CPUIRQSEL19_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL19_EV_S 0
+#define EVENT_CPUIRQSEL19_EV_GPT2A 0x0000000C
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL20
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// GPT2B GPT2B interrupt event, controlled by GPT2:TBMR
+#define EVENT_CPUIRQSEL20_EV_W 7
+#define EVENT_CPUIRQSEL20_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL20_EV_S 0
+#define EVENT_CPUIRQSEL20_EV_GPT2B 0x0000000D
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL21
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// GPT3A GPT3A interrupt event, controlled by GPT3:TAMR
+#define EVENT_CPUIRQSEL21_EV_W 7
+#define EVENT_CPUIRQSEL21_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL21_EV_S 0
+#define EVENT_CPUIRQSEL21_EV_GPT3A 0x0000000E
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL22
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// GPT3B GPT3B interrupt event, controlled by GPT3:TBMR
+#define EVENT_CPUIRQSEL22_EV_W 7
+#define EVENT_CPUIRQSEL22_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL22_EV_S 0
+#define EVENT_CPUIRQSEL22_EV_GPT3B 0x0000000F
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL23
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// CRYPTO_RESULT_AVAIL_IRQ CRYPTO result available interupt event, the
+// corresponding flag is found here
+// CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by
+// CRYPTO:IRQSTAT.RESULT_AVAIL
+#define EVENT_CPUIRQSEL23_EV_W 7
+#define EVENT_CPUIRQSEL23_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL23_EV_S 0
+#define EVENT_CPUIRQSEL23_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL24
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// DMA_DONE_COMB Combined DMA done, corresponding flags are here
+// UDMA0:REQDONE
+#define EVENT_CPUIRQSEL24_EV_W 7
+#define EVENT_CPUIRQSEL24_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL24_EV_S 0
+#define EVENT_CPUIRQSEL24_EV_DMA_DONE_COMB 0x00000027
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL25
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// DMA_ERR DMA bus error, corresponds to UDMA0:ERROR.STATUS
+#define EVENT_CPUIRQSEL25_EV_W 7
+#define EVENT_CPUIRQSEL25_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL25_EV_S 0
+#define EVENT_CPUIRQSEL25_EV_DMA_ERR 0x00000026
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL26
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// FLASH FLASH controller error event, the status flags
+// are FLASH:FEDACSTAT.FSM_DONE and
+// FLASH:FEDACSTAT.RVF_INT
+#define EVENT_CPUIRQSEL26_EV_W 7
+#define EVENT_CPUIRQSEL26_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL26_EV_S 0
+#define EVENT_CPUIRQSEL26_EV_FLASH 0x00000015
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL27
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// SWEV0 Software event 0, triggered by SWEV.SWEV0
+#define EVENT_CPUIRQSEL27_EV_W 7
+#define EVENT_CPUIRQSEL27_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL27_EV_S 0
+#define EVENT_CPUIRQSEL27_EV_SWEV0 0x00000064
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL28
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// AUX_COMB AUX combined event, the corresponding flag
+// register is here AUX_EVCTL:EVTOMCUFLAGS
+#define EVENT_CPUIRQSEL28_EV_W 7
+#define EVENT_CPUIRQSEL28_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL28_EV_S 0
+#define EVENT_CPUIRQSEL28_EV_AUX_COMB 0x0000000B
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL29
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// AON_PROG0 AON programmable event 0. Event selected by
+// AON_EVENT MCU event selector,
+// AON_EVENT:EVTOMCUSEL.AON_PROG0_EV
+#define EVENT_CPUIRQSEL29_EV_W 7
+#define EVENT_CPUIRQSEL29_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL29_EV_S 0
+#define EVENT_CPUIRQSEL29_EV_AON_PROG0 0x00000001
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL30
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read/write selection value
+//
+// Writing any other value than values defined by a ENUM may result in
+// undefined behavior.
+// ENUMs:
+// ALWAYS_ACTIVE Always asserted
+// AON_RTC_UPD RTC periodic event controlled by
+// AON_RTC:CTL.RTC_UPD_EN
+// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0
+// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL
+// AUX_ADC_DONE AUX ADC done, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE
+// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by
+// AUX_SMPH:AUTOTAKE
+// AUX_TIMER1_EV AUX timer 1 event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV
+// AUX_TIMER0_EV AUX timer 0 event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV
+// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the
+// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and
+// the AUX_TDC status AUX_TDC:STAT.DONE
+// AUX_COMPB AUX Compare B event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
+// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV
+// CRYPTO_DMA_DONE_IRQ CRYPTO DMA input done event, the correspondingg
+// flag is CRYPTO:IRQSTAT.DMA_IN_DONE. Controlled
+// by CRYPTO:IRQEN.DMA_IN_DONE
+// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE
+// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3
+// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2
+// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1
+// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0
+// DMA_CH18_DONE DMA done for software tiggered UDMA channel 18,
+// see UDMA0:SOFTREQ
+// DMA_CH0_DONE DMA done for software tiggered UDMA channel 0, see
+// UDMA0:SOFTREQ
+// AON_AUX_SWEV0 AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0
+// I2S_IRQ Interrupt event from I2S
+// AON_PROG2 AON programmable event 2. Event selected by
+// AON_EVENT MCU event selector,
+// AON_EVENT:EVTOMCUSEL.AON_PROG2_EV
+// AON_PROG1 AON programmable event 1. Event selected by
+// AON_EVENT MCU event selector,
+// AON_EVENT:EVTOMCUSEL.AON_PROG1_EV
+// NONE Always inactive
+#define EVENT_CPUIRQSEL30_EV_W 7
+#define EVENT_CPUIRQSEL30_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL30_EV_S 0
+#define EVENT_CPUIRQSEL30_EV_ALWAYS_ACTIVE 0x00000079
+#define EVENT_CPUIRQSEL30_EV_AON_RTC_UPD 0x00000077
+#define EVENT_CPUIRQSEL30_EV_AUX_OBSMUX0 0x00000072
+#define EVENT_CPUIRQSEL30_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071
+#define EVENT_CPUIRQSEL30_EV_AUX_ADC_DONE 0x00000070
+#define EVENT_CPUIRQSEL30_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F
+#define EVENT_CPUIRQSEL30_EV_AUX_TIMER1_EV 0x0000006E
+#define EVENT_CPUIRQSEL30_EV_AUX_TIMER0_EV 0x0000006D
+#define EVENT_CPUIRQSEL30_EV_AUX_TDC_DONE 0x0000006C
+#define EVENT_CPUIRQSEL30_EV_AUX_COMPB 0x0000006B
+#define EVENT_CPUIRQSEL30_EV_AUX_AON_WU_EV 0x00000069
+#define EVENT_CPUIRQSEL30_EV_CRYPTO_DMA_DONE_IRQ 0x0000005E
+#define EVENT_CPUIRQSEL30_EV_AUX_TIMER2_PULSE 0x0000003C
+#define EVENT_CPUIRQSEL30_EV_AUX_TIMER2_EV3 0x0000003B
+#define EVENT_CPUIRQSEL30_EV_AUX_TIMER2_EV2 0x0000003A
+#define EVENT_CPUIRQSEL30_EV_AUX_TIMER2_EV1 0x00000039
+#define EVENT_CPUIRQSEL30_EV_AUX_TIMER2_EV0 0x00000038
+#define EVENT_CPUIRQSEL30_EV_DMA_CH18_DONE 0x00000016
+#define EVENT_CPUIRQSEL30_EV_DMA_CH0_DONE 0x00000014
+#define EVENT_CPUIRQSEL30_EV_AON_AUX_SWEV0 0x0000000A
+#define EVENT_CPUIRQSEL30_EV_I2S_IRQ 0x00000008
+#define EVENT_CPUIRQSEL30_EV_AON_PROG2 0x00000003
+#define EVENT_CPUIRQSEL30_EV_AON_PROG1 0x00000002
+#define EVENT_CPUIRQSEL30_EV_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL31
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// AUX_COMPA AUX Compare A event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
+#define EVENT_CPUIRQSEL31_EV_W 7
+#define EVENT_CPUIRQSEL31_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL31_EV_S 0
+#define EVENT_CPUIRQSEL31_EV_AUX_COMPA 0x0000006A
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL32
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status
+// flags are found here AUX_EVCTL:EVTOMCUFLAGS
+#define EVENT_CPUIRQSEL32_EV_W 7
+#define EVENT_CPUIRQSEL32_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL32_EV_S 0
+#define EVENT_CPUIRQSEL32_EV_AUX_ADC_IRQ 0x00000073
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL33
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// TRNG_IRQ TRNG Interrupt event, controlled by TRNG:IRQEN.EN
+#define EVENT_CPUIRQSEL33_EV_W 7
+#define EVENT_CPUIRQSEL33_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL33_EV_S 0
+#define EVENT_CPUIRQSEL33_EV_TRNG_IRQ 0x00000068
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL34
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// OSC_COMB Combined event from Oscillator control
+#define EVENT_CPUIRQSEL34_EV_W 7
+#define EVENT_CPUIRQSEL34_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL34_EV_S 0
+#define EVENT_CPUIRQSEL34_EV_OSC_COMB 0x00000006
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL35
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0
+#define EVENT_CPUIRQSEL35_EV_W 7
+#define EVENT_CPUIRQSEL35_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL35_EV_S 0
+#define EVENT_CPUIRQSEL35_EV_AUX_TIMER2_EV0 0x00000038
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL36
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// UART1_COMB UART1 combined interrupt, interrupt flags are
+// found here UART1:MIS
+#define EVENT_CPUIRQSEL36_EV_W 7
+#define EVENT_CPUIRQSEL36_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL36_EV_S 0
+#define EVENT_CPUIRQSEL36_EV_UART1_COMB 0x00000025
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CPUIRQSEL37
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// BATMON_COMB Combined event from battery monitor
+#define EVENT_CPUIRQSEL37_EV_W 7
+#define EVENT_CPUIRQSEL37_EV_M 0x0000007F
+#define EVENT_CPUIRQSEL37_EV_S 0
+#define EVENT_CPUIRQSEL37_EV_BATMON_COMB 0x00000005
+
+//*****************************************************************************
+//
+// Register: EVENT_O_RFCSEL0
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT
+#define EVENT_RFCSEL0_EV_W 7
+#define EVENT_RFCSEL0_EV_M 0x0000007F
+#define EVENT_RFCSEL0_EV_S 0
+#define EVENT_RFCSEL0_EV_GPT0A_CMP 0x0000003D
+
+//*****************************************************************************
+//
+// Register: EVENT_O_RFCSEL1
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT
+#define EVENT_RFCSEL1_EV_W 7
+#define EVENT_RFCSEL1_EV_M 0x0000007F
+#define EVENT_RFCSEL1_EV_S 0
+#define EVENT_RFCSEL1_EV_GPT0B_CMP 0x0000003E
+
+//*****************************************************************************
+//
+// Register: EVENT_O_RFCSEL2
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT
+#define EVENT_RFCSEL2_EV_W 7
+#define EVENT_RFCSEL2_EV_M 0x0000007F
+#define EVENT_RFCSEL2_EV_S 0
+#define EVENT_RFCSEL2_EV_GPT1A_CMP 0x0000003F
+
+//*****************************************************************************
+//
+// Register: EVENT_O_RFCSEL3
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT
+#define EVENT_RFCSEL3_EV_W 7
+#define EVENT_RFCSEL3_EV_M 0x0000007F
+#define EVENT_RFCSEL3_EV_S 0
+#define EVENT_RFCSEL3_EV_GPT1B_CMP 0x00000040
+
+//*****************************************************************************
+//
+// Register: EVENT_O_RFCSEL4
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT
+#define EVENT_RFCSEL4_EV_W 7
+#define EVENT_RFCSEL4_EV_M 0x0000007F
+#define EVENT_RFCSEL4_EV_S 0
+#define EVENT_RFCSEL4_EV_GPT2A_CMP 0x00000041
+
+//*****************************************************************************
+//
+// Register: EVENT_O_RFCSEL5
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT
+#define EVENT_RFCSEL5_EV_W 7
+#define EVENT_RFCSEL5_EV_M 0x0000007F
+#define EVENT_RFCSEL5_EV_S 0
+#define EVENT_RFCSEL5_EV_GPT2B_CMP 0x00000042
+
+//*****************************************************************************
+//
+// Register: EVENT_O_RFCSEL6
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT
+#define EVENT_RFCSEL6_EV_W 7
+#define EVENT_RFCSEL6_EV_M 0x0000007F
+#define EVENT_RFCSEL6_EV_S 0
+#define EVENT_RFCSEL6_EV_GPT3A_CMP 0x00000043
+
+//*****************************************************************************
+//
+// Register: EVENT_O_RFCSEL7
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT
+#define EVENT_RFCSEL7_EV_W 7
+#define EVENT_RFCSEL7_EV_M 0x0000007F
+#define EVENT_RFCSEL7_EV_S 0
+#define EVENT_RFCSEL7_EV_GPT3B_CMP 0x00000044
+
+//*****************************************************************************
+//
+// Register: EVENT_O_RFCSEL8
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// AON_RTC_UPD RTC periodic event controlled by
+// AON_RTC:CTL.RTC_UPD_EN
+#define EVENT_RFCSEL8_EV_W 7
+#define EVENT_RFCSEL8_EV_M 0x0000007F
+#define EVENT_RFCSEL8_EV_S 0
+#define EVENT_RFCSEL8_EV_AON_RTC_UPD 0x00000077
+
+//*****************************************************************************
+//
+// Register: EVENT_O_RFCSEL9
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read/write selection value
+//
+// Writing any other value than values defined by a ENUM may result in
+// undefined behavior.
+// ENUMs:
+// ALWAYS_ACTIVE Always asserted
+// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status
+// flags are found here AUX_EVCTL:EVTOMCUFLAGS
+// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0
+// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL
+// AUX_ADC_DONE AUX ADC done, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE
+// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by
+// AUX_SMPH:AUTOTAKE
+// AUX_TIMER1_EV AUX timer 1 event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV
+// AUX_TIMER0_EV AUX timer 0 event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV
+// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the
+// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and
+// the AUX_TDC status AUX_TDC:STAT.DONE
+// AUX_COMPB AUX Compare B event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
+// AUX_COMPA AUX Compare A event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
+// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV
+// SWEV1 Software event 1, triggered by SWEV.SWEV1
+// SWEV0 Software event 0, triggered by SWEV.SWEV0
+// CRYPTO_RESULT_AVAIL_IRQ CRYPTO result available interupt event, the
+// corresponding flag is found here
+// CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by
+// CRYPTO:IRQSTAT.RESULT_AVAIL
+// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE
+// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3
+// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2
+// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1
+// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0
+// DMA_DONE_COMB Combined DMA done, corresponding flags are here
+// UDMA0:REQDONE
+// UART1_COMB UART1 combined interrupt, interrupt flags are
+// found here UART1:MIS
+// UART0_COMB UART0 combined interrupt, interrupt flags are
+// found here UART0:MIS
+// SSI1_COMB SSI1 combined interrupt, interrupt flags are found
+// here SSI1:MIS
+// SSI0_COMB SSI0 combined interrupt, interrupt flags are found
+// here SSI0:MIS
+// WDT_IRQ Watchdog interrupt event, controlled by
+// WDT:CTL.INTEN
+// AON_AUX_SWEV0 AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0
+// I2S_IRQ Interrupt event from I2S
+// AON_PROG1 AON programmable event 1. Event selected by
+// AON_EVENT MCU event selector,
+// AON_EVENT:EVTOMCUSEL.AON_PROG1_EV
+// AON_PROG0 AON programmable event 0. Event selected by
+// AON_EVENT MCU event selector,
+// AON_EVENT:EVTOMCUSEL.AON_PROG0_EV
+// NONE Always inactive
+#define EVENT_RFCSEL9_EV_W 7
+#define EVENT_RFCSEL9_EV_M 0x0000007F
+#define EVENT_RFCSEL9_EV_S 0
+#define EVENT_RFCSEL9_EV_ALWAYS_ACTIVE 0x00000079
+#define EVENT_RFCSEL9_EV_AUX_ADC_IRQ 0x00000073
+#define EVENT_RFCSEL9_EV_AUX_OBSMUX0 0x00000072
+#define EVENT_RFCSEL9_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071
+#define EVENT_RFCSEL9_EV_AUX_ADC_DONE 0x00000070
+#define EVENT_RFCSEL9_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F
+#define EVENT_RFCSEL9_EV_AUX_TIMER1_EV 0x0000006E
+#define EVENT_RFCSEL9_EV_AUX_TIMER0_EV 0x0000006D
+#define EVENT_RFCSEL9_EV_AUX_TDC_DONE 0x0000006C
+#define EVENT_RFCSEL9_EV_AUX_COMPB 0x0000006B
+#define EVENT_RFCSEL9_EV_AUX_COMPA 0x0000006A
+#define EVENT_RFCSEL9_EV_AUX_AON_WU_EV 0x00000069
+#define EVENT_RFCSEL9_EV_SWEV1 0x00000065
+#define EVENT_RFCSEL9_EV_SWEV0 0x00000064
+#define EVENT_RFCSEL9_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D
+#define EVENT_RFCSEL9_EV_AUX_TIMER2_PULSE 0x0000003C
+#define EVENT_RFCSEL9_EV_AUX_TIMER2_EV3 0x0000003B
+#define EVENT_RFCSEL9_EV_AUX_TIMER2_EV2 0x0000003A
+#define EVENT_RFCSEL9_EV_AUX_TIMER2_EV1 0x00000039
+#define EVENT_RFCSEL9_EV_AUX_TIMER2_EV0 0x00000038
+#define EVENT_RFCSEL9_EV_DMA_DONE_COMB 0x00000027
+#define EVENT_RFCSEL9_EV_UART1_COMB 0x00000025
+#define EVENT_RFCSEL9_EV_UART0_COMB 0x00000024
+#define EVENT_RFCSEL9_EV_SSI1_COMB 0x00000023
+#define EVENT_RFCSEL9_EV_SSI0_COMB 0x00000022
+#define EVENT_RFCSEL9_EV_WDT_IRQ 0x00000018
+#define EVENT_RFCSEL9_EV_AON_AUX_SWEV0 0x0000000A
+#define EVENT_RFCSEL9_EV_I2S_IRQ 0x00000008
+#define EVENT_RFCSEL9_EV_AON_PROG1 0x00000002
+#define EVENT_RFCSEL9_EV_AON_PROG0 0x00000001
+#define EVENT_RFCSEL9_EV_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Register: EVENT_O_GPT0ACAPTSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read/write selection value
+//
+// Writing any other value than values defined by a ENUM may result in
+// undefined behavior.
+// ENUMs:
+// ALWAYS_ACTIVE Always asserted
+// AON_RTC_UPD RTC periodic event controlled by
+// AON_RTC:CTL.RTC_UPD_EN
+// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status
+// flags are found here AUX_EVCTL:EVTOMCUFLAGS
+// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0
+// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL
+// AUX_ADC_DONE AUX ADC done, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE
+// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by
+// AUX_SMPH:AUTOTAKE
+// AUX_TIMER1_EV AUX timer 1 event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV
+// AUX_TIMER0_EV AUX timer 0 event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV
+// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the
+// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and
+// the AUX_TDC status AUX_TDC:STAT.DONE
+// AUX_COMPB AUX Compare B event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
+// AUX_COMPA AUX Compare A event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
+// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV
+// PORT_EVENT1 Port capture event from IOC, configured by
+// IOC:IOCFGn.PORT_ID. Events on ports configured
+// with ENUM PORT_EVENT1 wil be routed here.
+// PORT_EVENT0 Port capture event from IOC, configured by
+// IOC:IOCFGn.PORT_ID. Events on ports configured
+// with ENUM PORT_EVENT0 wil be routed here.
+// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT
+// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT
+// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT
+// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT
+// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT
+// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT
+// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT
+// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT
+// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE
+// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3
+// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2
+// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1
+// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0
+// UART1_COMB UART1 combined interrupt, interrupt flags are
+// found here UART1:MIS
+// UART0_COMB UART0 combined interrupt, interrupt flags are
+// found here UART0:MIS
+// SSI1_COMB SSI1 combined interrupt, interrupt flags are found
+// here SSI1:MIS
+// SSI0_COMB SSI0 combined interrupt, interrupt flags are found
+// here SSI0:MIS
+// RFC_CPE_1 Combined Interrupt for CPE Generated events.
+// Corresponding flags are here
+// RFC_DBELL:RFCPEIFG. Only interrupts selected
+// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a
+// RFC_CPE_1 event
+// RFC_CPE_0 Combined Interrupt for CPE Generated events.
+// Corresponding flags are here
+// RFC_DBELL:RFCPEIFG. Only interrupts selected
+// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a
+// RFC_CPE_0 event
+// RFC_HW_COMB Combined RFC hardware interrupt, corresponding
+// flag is here RFC_DBELL:RFHWIFG
+// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt,
+// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG
+// FLASH FLASH controller error event, the status flags
+// are FLASH:FEDACSTAT.FSM_DONE and
+// FLASH:FEDACSTAT.RVF_INT
+// AUX_COMB AUX combined event, the corresponding flag
+// register is here AUX_EVCTL:EVTOMCUFLAGS
+// I2C_IRQ Interrupt event from I2C
+// AON_RTC_COMB Event from AON_RTC, controlled by the
+// AON_RTC:CTL.COMB_EV_MASK setting
+// OSC_COMB Combined event from Oscillator control
+// BATMON_COMB Combined event from battery monitor
+// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the
+// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET
+// settings
+// NONE Always inactive
+#define EVENT_GPT0ACAPTSEL_EV_W 7
+#define EVENT_GPT0ACAPTSEL_EV_M 0x0000007F
+#define EVENT_GPT0ACAPTSEL_EV_S 0
+#define EVENT_GPT0ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079
+#define EVENT_GPT0ACAPTSEL_EV_AON_RTC_UPD 0x00000077
+#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073
+#define EVENT_GPT0ACAPTSEL_EV_AUX_OBSMUX0 0x00000072
+#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071
+#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_DONE 0x00000070
+#define EVENT_GPT0ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F
+#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E
+#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D
+#define EVENT_GPT0ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C
+#define EVENT_GPT0ACAPTSEL_EV_AUX_COMPB 0x0000006B
+#define EVENT_GPT0ACAPTSEL_EV_AUX_COMPA 0x0000006A
+#define EVENT_GPT0ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069
+#define EVENT_GPT0ACAPTSEL_EV_PORT_EVENT1 0x00000056
+#define EVENT_GPT0ACAPTSEL_EV_PORT_EVENT0 0x00000055
+#define EVENT_GPT0ACAPTSEL_EV_GPT3B_CMP 0x00000044
+#define EVENT_GPT0ACAPTSEL_EV_GPT3A_CMP 0x00000043
+#define EVENT_GPT0ACAPTSEL_EV_GPT2B_CMP 0x00000042
+#define EVENT_GPT0ACAPTSEL_EV_GPT2A_CMP 0x00000041
+#define EVENT_GPT0ACAPTSEL_EV_GPT1B_CMP 0x00000040
+#define EVENT_GPT0ACAPTSEL_EV_GPT1A_CMP 0x0000003F
+#define EVENT_GPT0ACAPTSEL_EV_GPT0B_CMP 0x0000003E
+#define EVENT_GPT0ACAPTSEL_EV_GPT0A_CMP 0x0000003D
+#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C
+#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B
+#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A
+#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER2_EV1 0x00000039
+#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER2_EV0 0x00000038
+#define EVENT_GPT0ACAPTSEL_EV_UART1_COMB 0x00000025
+#define EVENT_GPT0ACAPTSEL_EV_UART0_COMB 0x00000024
+#define EVENT_GPT0ACAPTSEL_EV_SSI1_COMB 0x00000023
+#define EVENT_GPT0ACAPTSEL_EV_SSI0_COMB 0x00000022
+#define EVENT_GPT0ACAPTSEL_EV_RFC_CPE_1 0x0000001E
+#define EVENT_GPT0ACAPTSEL_EV_RFC_CPE_0 0x0000001B
+#define EVENT_GPT0ACAPTSEL_EV_RFC_HW_COMB 0x0000001A
+#define EVENT_GPT0ACAPTSEL_EV_RFC_CMD_ACK 0x00000019
+#define EVENT_GPT0ACAPTSEL_EV_FLASH 0x00000015
+#define EVENT_GPT0ACAPTSEL_EV_AUX_COMB 0x0000000B
+#define EVENT_GPT0ACAPTSEL_EV_I2C_IRQ 0x00000009
+#define EVENT_GPT0ACAPTSEL_EV_AON_RTC_COMB 0x00000007
+#define EVENT_GPT0ACAPTSEL_EV_OSC_COMB 0x00000006
+#define EVENT_GPT0ACAPTSEL_EV_BATMON_COMB 0x00000005
+#define EVENT_GPT0ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004
+#define EVENT_GPT0ACAPTSEL_EV_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Register: EVENT_O_GPT0BCAPTSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read/write selection value
+//
+// Writing any other value than values defined by a ENUM may result in
+// undefined behavior.
+// ENUMs:
+// ALWAYS_ACTIVE Always asserted
+// AON_RTC_UPD RTC periodic event controlled by
+// AON_RTC:CTL.RTC_UPD_EN
+// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status
+// flags are found here AUX_EVCTL:EVTOMCUFLAGS
+// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0
+// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL
+// AUX_ADC_DONE AUX ADC done, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE
+// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by
+// AUX_SMPH:AUTOTAKE
+// AUX_TIMER1_EV AUX timer 1 event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV
+// AUX_TIMER0_EV AUX timer 0 event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV
+// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the
+// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and
+// the AUX_TDC status AUX_TDC:STAT.DONE
+// AUX_COMPB AUX Compare B event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
+// AUX_COMPA AUX Compare A event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
+// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV
+// PORT_EVENT1 Port capture event from IOC, configured by
+// IOC:IOCFGn.PORT_ID. Events on ports configured
+// with ENUM PORT_EVENT1 wil be routed here.
+// PORT_EVENT0 Port capture event from IOC, configured by
+// IOC:IOCFGn.PORT_ID. Events on ports configured
+// with ENUM PORT_EVENT0 wil be routed here.
+// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT
+// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT
+// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT
+// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT
+// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT
+// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT
+// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT
+// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT
+// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE
+// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3
+// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2
+// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1
+// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0
+// UART1_COMB UART1 combined interrupt, interrupt flags are
+// found here UART1:MIS
+// UART0_COMB UART0 combined interrupt, interrupt flags are
+// found here UART0:MIS
+// SSI1_COMB SSI1 combined interrupt, interrupt flags are found
+// here SSI1:MIS
+// SSI0_COMB SSI0 combined interrupt, interrupt flags are found
+// here SSI0:MIS
+// RFC_CPE_1 Combined Interrupt for CPE Generated events.
+// Corresponding flags are here
+// RFC_DBELL:RFCPEIFG. Only interrupts selected
+// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a
+// RFC_CPE_1 event
+// RFC_CPE_0 Combined Interrupt for CPE Generated events.
+// Corresponding flags are here
+// RFC_DBELL:RFCPEIFG. Only interrupts selected
+// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a
+// RFC_CPE_0 event
+// RFC_HW_COMB Combined RFC hardware interrupt, corresponding
+// flag is here RFC_DBELL:RFHWIFG
+// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt,
+// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG
+// FLASH FLASH controller error event, the status flags
+// are FLASH:FEDACSTAT.FSM_DONE and
+// FLASH:FEDACSTAT.RVF_INT
+// AUX_COMB AUX combined event, the corresponding flag
+// register is here AUX_EVCTL:EVTOMCUFLAGS
+// I2C_IRQ Interrupt event from I2C
+// AON_RTC_COMB Event from AON_RTC, controlled by the
+// AON_RTC:CTL.COMB_EV_MASK setting
+// OSC_COMB Combined event from Oscillator control
+// BATMON_COMB Combined event from battery monitor
+// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the
+// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET
+// settings
+// NONE Always inactive
+#define EVENT_GPT0BCAPTSEL_EV_W 7
+#define EVENT_GPT0BCAPTSEL_EV_M 0x0000007F
+#define EVENT_GPT0BCAPTSEL_EV_S 0
+#define EVENT_GPT0BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079
+#define EVENT_GPT0BCAPTSEL_EV_AON_RTC_UPD 0x00000077
+#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073
+#define EVENT_GPT0BCAPTSEL_EV_AUX_OBSMUX0 0x00000072
+#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071
+#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_DONE 0x00000070
+#define EVENT_GPT0BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F
+#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E
+#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D
+#define EVENT_GPT0BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C
+#define EVENT_GPT0BCAPTSEL_EV_AUX_COMPB 0x0000006B
+#define EVENT_GPT0BCAPTSEL_EV_AUX_COMPA 0x0000006A
+#define EVENT_GPT0BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069
+#define EVENT_GPT0BCAPTSEL_EV_PORT_EVENT1 0x00000056
+#define EVENT_GPT0BCAPTSEL_EV_PORT_EVENT0 0x00000055
+#define EVENT_GPT0BCAPTSEL_EV_GPT3B_CMP 0x00000044
+#define EVENT_GPT0BCAPTSEL_EV_GPT3A_CMP 0x00000043
+#define EVENT_GPT0BCAPTSEL_EV_GPT2B_CMP 0x00000042
+#define EVENT_GPT0BCAPTSEL_EV_GPT2A_CMP 0x00000041
+#define EVENT_GPT0BCAPTSEL_EV_GPT1B_CMP 0x00000040
+#define EVENT_GPT0BCAPTSEL_EV_GPT1A_CMP 0x0000003F
+#define EVENT_GPT0BCAPTSEL_EV_GPT0B_CMP 0x0000003E
+#define EVENT_GPT0BCAPTSEL_EV_GPT0A_CMP 0x0000003D
+#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C
+#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B
+#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A
+#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER2_EV1 0x00000039
+#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER2_EV0 0x00000038
+#define EVENT_GPT0BCAPTSEL_EV_UART1_COMB 0x00000025
+#define EVENT_GPT0BCAPTSEL_EV_UART0_COMB 0x00000024
+#define EVENT_GPT0BCAPTSEL_EV_SSI1_COMB 0x00000023
+#define EVENT_GPT0BCAPTSEL_EV_SSI0_COMB 0x00000022
+#define EVENT_GPT0BCAPTSEL_EV_RFC_CPE_1 0x0000001E
+#define EVENT_GPT0BCAPTSEL_EV_RFC_CPE_0 0x0000001B
+#define EVENT_GPT0BCAPTSEL_EV_RFC_HW_COMB 0x0000001A
+#define EVENT_GPT0BCAPTSEL_EV_RFC_CMD_ACK 0x00000019
+#define EVENT_GPT0BCAPTSEL_EV_FLASH 0x00000015
+#define EVENT_GPT0BCAPTSEL_EV_AUX_COMB 0x0000000B
+#define EVENT_GPT0BCAPTSEL_EV_I2C_IRQ 0x00000009
+#define EVENT_GPT0BCAPTSEL_EV_AON_RTC_COMB 0x00000007
+#define EVENT_GPT0BCAPTSEL_EV_OSC_COMB 0x00000006
+#define EVENT_GPT0BCAPTSEL_EV_BATMON_COMB 0x00000005
+#define EVENT_GPT0BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004
+#define EVENT_GPT0BCAPTSEL_EV_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Register: EVENT_O_GPT1ACAPTSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read/write selection value
+//
+// Writing any other value than values defined by a ENUM may result in
+// undefined behavior.
+// ENUMs:
+// ALWAYS_ACTIVE Always asserted
+// AON_RTC_UPD RTC periodic event controlled by
+// AON_RTC:CTL.RTC_UPD_EN
+// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status
+// flags are found here AUX_EVCTL:EVTOMCUFLAGS
+// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0
+// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL
+// AUX_ADC_DONE AUX ADC done, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE
+// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by
+// AUX_SMPH:AUTOTAKE
+// AUX_TIMER1_EV AUX timer 1 event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV
+// AUX_TIMER0_EV AUX timer 0 event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV
+// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the
+// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and
+// the AUX_TDC status AUX_TDC:STAT.DONE
+// AUX_COMPB AUX Compare B event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
+// AUX_COMPA AUX Compare A event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
+// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV
+// PORT_EVENT3 Port capture event from IOC, configured by
+// IOC:IOCFGn.PORT_ID. Events on ports configured
+// with ENUM PORT_EVENT3 wil be routed here.
+// PORT_EVENT2 Port capture event from IOC, configured by
+// IOC:IOCFGn.PORT_ID. Events on ports configured
+// with ENUM PORT_EVENT2 wil be routed here.
+// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT
+// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT
+// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT
+// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT
+// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT
+// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT
+// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT
+// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT
+// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE
+// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3
+// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2
+// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1
+// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0
+// UART1_COMB UART1 combined interrupt, interrupt flags are
+// found here UART1:MIS
+// UART0_COMB UART0 combined interrupt, interrupt flags are
+// found here UART0:MIS
+// SSI1_COMB SSI1 combined interrupt, interrupt flags are found
+// here SSI1:MIS
+// SSI0_COMB SSI0 combined interrupt, interrupt flags are found
+// here SSI0:MIS
+// RFC_CPE_1 Combined Interrupt for CPE Generated events.
+// Corresponding flags are here
+// RFC_DBELL:RFCPEIFG. Only interrupts selected
+// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a
+// RFC_CPE_1 event
+// RFC_CPE_0 Combined Interrupt for CPE Generated events.
+// Corresponding flags are here
+// RFC_DBELL:RFCPEIFG. Only interrupts selected
+// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a
+// RFC_CPE_0 event
+// RFC_HW_COMB Combined RFC hardware interrupt, corresponding
+// flag is here RFC_DBELL:RFHWIFG
+// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt,
+// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG
+// FLASH FLASH controller error event, the status flags
+// are FLASH:FEDACSTAT.FSM_DONE and
+// FLASH:FEDACSTAT.RVF_INT
+// AUX_COMB AUX combined event, the corresponding flag
+// register is here AUX_EVCTL:EVTOMCUFLAGS
+// I2C_IRQ Interrupt event from I2C
+// AON_RTC_COMB Event from AON_RTC, controlled by the
+// AON_RTC:CTL.COMB_EV_MASK setting
+// OSC_COMB Combined event from Oscillator control
+// BATMON_COMB Combined event from battery monitor
+// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the
+// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET
+// settings
+// NONE Always inactive
+#define EVENT_GPT1ACAPTSEL_EV_W 7
+#define EVENT_GPT1ACAPTSEL_EV_M 0x0000007F
+#define EVENT_GPT1ACAPTSEL_EV_S 0
+#define EVENT_GPT1ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079
+#define EVENT_GPT1ACAPTSEL_EV_AON_RTC_UPD 0x00000077
+#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073
+#define EVENT_GPT1ACAPTSEL_EV_AUX_OBSMUX0 0x00000072
+#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071
+#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_DONE 0x00000070
+#define EVENT_GPT1ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F
+#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E
+#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D
+#define EVENT_GPT1ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C
+#define EVENT_GPT1ACAPTSEL_EV_AUX_COMPB 0x0000006B
+#define EVENT_GPT1ACAPTSEL_EV_AUX_COMPA 0x0000006A
+#define EVENT_GPT1ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069
+#define EVENT_GPT1ACAPTSEL_EV_PORT_EVENT3 0x00000058
+#define EVENT_GPT1ACAPTSEL_EV_PORT_EVENT2 0x00000057
+#define EVENT_GPT1ACAPTSEL_EV_GPT3B_CMP 0x00000044
+#define EVENT_GPT1ACAPTSEL_EV_GPT3A_CMP 0x00000043
+#define EVENT_GPT1ACAPTSEL_EV_GPT2B_CMP 0x00000042
+#define EVENT_GPT1ACAPTSEL_EV_GPT2A_CMP 0x00000041
+#define EVENT_GPT1ACAPTSEL_EV_GPT1B_CMP 0x00000040
+#define EVENT_GPT1ACAPTSEL_EV_GPT1A_CMP 0x0000003F
+#define EVENT_GPT1ACAPTSEL_EV_GPT0B_CMP 0x0000003E
+#define EVENT_GPT1ACAPTSEL_EV_GPT0A_CMP 0x0000003D
+#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C
+#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B
+#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A
+#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER2_EV1 0x00000039
+#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER2_EV0 0x00000038
+#define EVENT_GPT1ACAPTSEL_EV_UART1_COMB 0x00000025
+#define EVENT_GPT1ACAPTSEL_EV_UART0_COMB 0x00000024
+#define EVENT_GPT1ACAPTSEL_EV_SSI1_COMB 0x00000023
+#define EVENT_GPT1ACAPTSEL_EV_SSI0_COMB 0x00000022
+#define EVENT_GPT1ACAPTSEL_EV_RFC_CPE_1 0x0000001E
+#define EVENT_GPT1ACAPTSEL_EV_RFC_CPE_0 0x0000001B
+#define EVENT_GPT1ACAPTSEL_EV_RFC_HW_COMB 0x0000001A
+#define EVENT_GPT1ACAPTSEL_EV_RFC_CMD_ACK 0x00000019
+#define EVENT_GPT1ACAPTSEL_EV_FLASH 0x00000015
+#define EVENT_GPT1ACAPTSEL_EV_AUX_COMB 0x0000000B
+#define EVENT_GPT1ACAPTSEL_EV_I2C_IRQ 0x00000009
+#define EVENT_GPT1ACAPTSEL_EV_AON_RTC_COMB 0x00000007
+#define EVENT_GPT1ACAPTSEL_EV_OSC_COMB 0x00000006
+#define EVENT_GPT1ACAPTSEL_EV_BATMON_COMB 0x00000005
+#define EVENT_GPT1ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004
+#define EVENT_GPT1ACAPTSEL_EV_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Register: EVENT_O_GPT1BCAPTSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read/write selection value
+//
+// Writing any other value than values defined by a ENUM may result in
+// undefined behavior.
+// ENUMs:
+// ALWAYS_ACTIVE Always asserted
+// AON_RTC_UPD RTC periodic event controlled by
+// AON_RTC:CTL.RTC_UPD_EN
+// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status
+// flags are found here AUX_EVCTL:EVTOMCUFLAGS
+// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0
+// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL
+// AUX_ADC_DONE AUX ADC done, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE
+// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by
+// AUX_SMPH:AUTOTAKE
+// AUX_TIMER1_EV AUX timer 1 event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV
+// AUX_TIMER0_EV AUX timer 0 event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV
+// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the
+// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and
+// the AUX_TDC status AUX_TDC:STAT.DONE
+// AUX_COMPB AUX Compare B event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
+// AUX_COMPA AUX Compare A event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
+// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV
+// PORT_EVENT3 Port capture event from IOC, configured by
+// IOC:IOCFGn.PORT_ID. Events on ports configured
+// with ENUM PORT_EVENT3 wil be routed here.
+// PORT_EVENT2 Port capture event from IOC, configured by
+// IOC:IOCFGn.PORT_ID. Events on ports configured
+// with ENUM PORT_EVENT2 wil be routed here.
+// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT
+// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT
+// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT
+// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT
+// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT
+// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT
+// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT
+// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT
+// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE
+// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3
+// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2
+// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1
+// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0
+// UART1_COMB UART1 combined interrupt, interrupt flags are
+// found here UART1:MIS
+// UART0_COMB UART0 combined interrupt, interrupt flags are
+// found here UART0:MIS
+// SSI1_COMB SSI1 combined interrupt, interrupt flags are found
+// here SSI1:MIS
+// SSI0_COMB SSI0 combined interrupt, interrupt flags are found
+// here SSI0:MIS
+// RFC_CPE_1 Combined Interrupt for CPE Generated events.
+// Corresponding flags are here
+// RFC_DBELL:RFCPEIFG. Only interrupts selected
+// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a
+// RFC_CPE_1 event
+// RFC_CPE_0 Combined Interrupt for CPE Generated events.
+// Corresponding flags are here
+// RFC_DBELL:RFCPEIFG. Only interrupts selected
+// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a
+// RFC_CPE_0 event
+// RFC_HW_COMB Combined RFC hardware interrupt, corresponding
+// flag is here RFC_DBELL:RFHWIFG
+// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt,
+// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG
+// FLASH FLASH controller error event, the status flags
+// are FLASH:FEDACSTAT.FSM_DONE and
+// FLASH:FEDACSTAT.RVF_INT
+// AUX_COMB AUX combined event, the corresponding flag
+// register is here AUX_EVCTL:EVTOMCUFLAGS
+// I2C_IRQ Interrupt event from I2C
+// AON_RTC_COMB Event from AON_RTC, controlled by the
+// AON_RTC:CTL.COMB_EV_MASK setting
+// OSC_COMB Combined event from Oscillator control
+// BATMON_COMB Combined event from battery monitor
+// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the
+// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET
+// settings
+// NONE Always inactive
+#define EVENT_GPT1BCAPTSEL_EV_W 7
+#define EVENT_GPT1BCAPTSEL_EV_M 0x0000007F
+#define EVENT_GPT1BCAPTSEL_EV_S 0
+#define EVENT_GPT1BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079
+#define EVENT_GPT1BCAPTSEL_EV_AON_RTC_UPD 0x00000077
+#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073
+#define EVENT_GPT1BCAPTSEL_EV_AUX_OBSMUX0 0x00000072
+#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071
+#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_DONE 0x00000070
+#define EVENT_GPT1BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F
+#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E
+#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D
+#define EVENT_GPT1BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C
+#define EVENT_GPT1BCAPTSEL_EV_AUX_COMPB 0x0000006B
+#define EVENT_GPT1BCAPTSEL_EV_AUX_COMPA 0x0000006A
+#define EVENT_GPT1BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069
+#define EVENT_GPT1BCAPTSEL_EV_PORT_EVENT3 0x00000058
+#define EVENT_GPT1BCAPTSEL_EV_PORT_EVENT2 0x00000057
+#define EVENT_GPT1BCAPTSEL_EV_GPT3B_CMP 0x00000044
+#define EVENT_GPT1BCAPTSEL_EV_GPT3A_CMP 0x00000043
+#define EVENT_GPT1BCAPTSEL_EV_GPT2B_CMP 0x00000042
+#define EVENT_GPT1BCAPTSEL_EV_GPT2A_CMP 0x00000041
+#define EVENT_GPT1BCAPTSEL_EV_GPT1B_CMP 0x00000040
+#define EVENT_GPT1BCAPTSEL_EV_GPT1A_CMP 0x0000003F
+#define EVENT_GPT1BCAPTSEL_EV_GPT0B_CMP 0x0000003E
+#define EVENT_GPT1BCAPTSEL_EV_GPT0A_CMP 0x0000003D
+#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C
+#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B
+#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A
+#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER2_EV1 0x00000039
+#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER2_EV0 0x00000038
+#define EVENT_GPT1BCAPTSEL_EV_UART1_COMB 0x00000025
+#define EVENT_GPT1BCAPTSEL_EV_UART0_COMB 0x00000024
+#define EVENT_GPT1BCAPTSEL_EV_SSI1_COMB 0x00000023
+#define EVENT_GPT1BCAPTSEL_EV_SSI0_COMB 0x00000022
+#define EVENT_GPT1BCAPTSEL_EV_RFC_CPE_1 0x0000001E
+#define EVENT_GPT1BCAPTSEL_EV_RFC_CPE_0 0x0000001B
+#define EVENT_GPT1BCAPTSEL_EV_RFC_HW_COMB 0x0000001A
+#define EVENT_GPT1BCAPTSEL_EV_RFC_CMD_ACK 0x00000019
+#define EVENT_GPT1BCAPTSEL_EV_FLASH 0x00000015
+#define EVENT_GPT1BCAPTSEL_EV_AUX_COMB 0x0000000B
+#define EVENT_GPT1BCAPTSEL_EV_I2C_IRQ 0x00000009
+#define EVENT_GPT1BCAPTSEL_EV_AON_RTC_COMB 0x00000007
+#define EVENT_GPT1BCAPTSEL_EV_OSC_COMB 0x00000006
+#define EVENT_GPT1BCAPTSEL_EV_BATMON_COMB 0x00000005
+#define EVENT_GPT1BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004
+#define EVENT_GPT1BCAPTSEL_EV_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Register: EVENT_O_GPT2ACAPTSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read/write selection value
+//
+// Writing any other value than values defined by a ENUM may result in
+// undefined behavior.
+// ENUMs:
+// ALWAYS_ACTIVE Always asserted
+// AON_RTC_UPD RTC periodic event controlled by
+// AON_RTC:CTL.RTC_UPD_EN
+// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status
+// flags are found here AUX_EVCTL:EVTOMCUFLAGS
+// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0
+// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL
+// AUX_ADC_DONE AUX ADC done, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE
+// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by
+// AUX_SMPH:AUTOTAKE
+// AUX_TIMER1_EV AUX timer 1 event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV
+// AUX_TIMER0_EV AUX timer 0 event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV
+// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the
+// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and
+// the AUX_TDC status AUX_TDC:STAT.DONE
+// AUX_COMPB AUX Compare B event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
+// AUX_COMPA AUX Compare A event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
+// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV
+// PORT_EVENT5 Port capture event from IOC, configured by
+// IOC:IOCFGn.PORT_ID. Events on ports configured
+// with ENUM PORT_EVENT4 wil be routed here.
+// PORT_EVENT4 Port capture event from IOC, configured by
+// IOC:IOCFGn.PORT_ID. Events on ports configured
+// with ENUM PORT_EVENT4 wil be routed here.
+// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT
+// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT
+// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT
+// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT
+// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT
+// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT
+// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT
+// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT
+// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE
+// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3
+// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2
+// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1
+// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0
+// UART1_COMB UART1 combined interrupt, interrupt flags are
+// found here UART1:MIS
+// UART0_COMB UART0 combined interrupt, interrupt flags are
+// found here UART0:MIS
+// SSI1_COMB SSI1 combined interrupt, interrupt flags are found
+// here SSI1:MIS
+// SSI0_COMB SSI0 combined interrupt, interrupt flags are found
+// here SSI0:MIS
+// RFC_CPE_1 Combined Interrupt for CPE Generated events.
+// Corresponding flags are here
+// RFC_DBELL:RFCPEIFG. Only interrupts selected
+// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a
+// RFC_CPE_1 event
+// RFC_CPE_0 Combined Interrupt for CPE Generated events.
+// Corresponding flags are here
+// RFC_DBELL:RFCPEIFG. Only interrupts selected
+// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a
+// RFC_CPE_0 event
+// RFC_HW_COMB Combined RFC hardware interrupt, corresponding
+// flag is here RFC_DBELL:RFHWIFG
+// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt,
+// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG
+// FLASH FLASH controller error event, the status flags
+// are FLASH:FEDACSTAT.FSM_DONE and
+// FLASH:FEDACSTAT.RVF_INT
+// AUX_COMB AUX combined event, the corresponding flag
+// register is here AUX_EVCTL:EVTOMCUFLAGS
+// I2C_IRQ Interrupt event from I2C
+// AON_RTC_COMB Event from AON_RTC, controlled by the
+// AON_RTC:CTL.COMB_EV_MASK setting
+// OSC_COMB Combined event from Oscillator control
+// BATMON_COMB Combined event from battery monitor
+// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the
+// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET
+// settings
+// NONE Always inactive
+#define EVENT_GPT2ACAPTSEL_EV_W 7
+#define EVENT_GPT2ACAPTSEL_EV_M 0x0000007F
+#define EVENT_GPT2ACAPTSEL_EV_S 0
+#define EVENT_GPT2ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079
+#define EVENT_GPT2ACAPTSEL_EV_AON_RTC_UPD 0x00000077
+#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073
+#define EVENT_GPT2ACAPTSEL_EV_AUX_OBSMUX0 0x00000072
+#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071
+#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_DONE 0x00000070
+#define EVENT_GPT2ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F
+#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E
+#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D
+#define EVENT_GPT2ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C
+#define EVENT_GPT2ACAPTSEL_EV_AUX_COMPB 0x0000006B
+#define EVENT_GPT2ACAPTSEL_EV_AUX_COMPA 0x0000006A
+#define EVENT_GPT2ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069
+#define EVENT_GPT2ACAPTSEL_EV_PORT_EVENT5 0x0000005A
+#define EVENT_GPT2ACAPTSEL_EV_PORT_EVENT4 0x00000059
+#define EVENT_GPT2ACAPTSEL_EV_GPT3B_CMP 0x00000044
+#define EVENT_GPT2ACAPTSEL_EV_GPT3A_CMP 0x00000043
+#define EVENT_GPT2ACAPTSEL_EV_GPT2B_CMP 0x00000042
+#define EVENT_GPT2ACAPTSEL_EV_GPT2A_CMP 0x00000041
+#define EVENT_GPT2ACAPTSEL_EV_GPT1B_CMP 0x00000040
+#define EVENT_GPT2ACAPTSEL_EV_GPT1A_CMP 0x0000003F
+#define EVENT_GPT2ACAPTSEL_EV_GPT0B_CMP 0x0000003E
+#define EVENT_GPT2ACAPTSEL_EV_GPT0A_CMP 0x0000003D
+#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C
+#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B
+#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A
+#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER2_EV1 0x00000039
+#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER2_EV0 0x00000038
+#define EVENT_GPT2ACAPTSEL_EV_UART1_COMB 0x00000025
+#define EVENT_GPT2ACAPTSEL_EV_UART0_COMB 0x00000024
+#define EVENT_GPT2ACAPTSEL_EV_SSI1_COMB 0x00000023
+#define EVENT_GPT2ACAPTSEL_EV_SSI0_COMB 0x00000022
+#define EVENT_GPT2ACAPTSEL_EV_RFC_CPE_1 0x0000001E
+#define EVENT_GPT2ACAPTSEL_EV_RFC_CPE_0 0x0000001B
+#define EVENT_GPT2ACAPTSEL_EV_RFC_HW_COMB 0x0000001A
+#define EVENT_GPT2ACAPTSEL_EV_RFC_CMD_ACK 0x00000019
+#define EVENT_GPT2ACAPTSEL_EV_FLASH 0x00000015
+#define EVENT_GPT2ACAPTSEL_EV_AUX_COMB 0x0000000B
+#define EVENT_GPT2ACAPTSEL_EV_I2C_IRQ 0x00000009
+#define EVENT_GPT2ACAPTSEL_EV_AON_RTC_COMB 0x00000007
+#define EVENT_GPT2ACAPTSEL_EV_OSC_COMB 0x00000006
+#define EVENT_GPT2ACAPTSEL_EV_BATMON_COMB 0x00000005
+#define EVENT_GPT2ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004
+#define EVENT_GPT2ACAPTSEL_EV_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Register: EVENT_O_GPT2BCAPTSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read/write selection value
+//
+// Writing any other value than values defined by a ENUM may result in
+// undefined behavior.
+// ENUMs:
+// ALWAYS_ACTIVE Always asserted
+// AON_RTC_UPD RTC periodic event controlled by
+// AON_RTC:CTL.RTC_UPD_EN
+// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status
+// flags are found here AUX_EVCTL:EVTOMCUFLAGS
+// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0
+// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL
+// AUX_ADC_DONE AUX ADC done, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE
+// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by
+// AUX_SMPH:AUTOTAKE
+// AUX_TIMER1_EV AUX timer 1 event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV
+// AUX_TIMER0_EV AUX timer 0 event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV
+// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the
+// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and
+// the AUX_TDC status AUX_TDC:STAT.DONE
+// AUX_COMPB AUX Compare B event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
+// AUX_COMPA AUX Compare A event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
+// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV
+// PORT_EVENT5 Port capture event from IOC, configured by
+// IOC:IOCFGn.PORT_ID. Events on ports configured
+// with ENUM PORT_EVENT4 wil be routed here.
+// PORT_EVENT4 Port capture event from IOC, configured by
+// IOC:IOCFGn.PORT_ID. Events on ports configured
+// with ENUM PORT_EVENT4 wil be routed here.
+// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT
+// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT
+// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT
+// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT
+// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT
+// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT
+// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT
+// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT
+// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE
+// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3
+// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2
+// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1
+// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0
+// UART1_COMB UART1 combined interrupt, interrupt flags are
+// found here UART1:MIS
+// UART0_COMB UART0 combined interrupt, interrupt flags are
+// found here UART0:MIS
+// SSI1_COMB SSI1 combined interrupt, interrupt flags are found
+// here SSI1:MIS
+// SSI0_COMB SSI0 combined interrupt, interrupt flags are found
+// here SSI0:MIS
+// RFC_CPE_1 Combined Interrupt for CPE Generated events.
+// Corresponding flags are here
+// RFC_DBELL:RFCPEIFG. Only interrupts selected
+// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a
+// RFC_CPE_1 event
+// RFC_CPE_0 Combined Interrupt for CPE Generated events.
+// Corresponding flags are here
+// RFC_DBELL:RFCPEIFG. Only interrupts selected
+// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a
+// RFC_CPE_0 event
+// RFC_HW_COMB Combined RFC hardware interrupt, corresponding
+// flag is here RFC_DBELL:RFHWIFG
+// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt,
+// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG
+// FLASH FLASH controller error event, the status flags
+// are FLASH:FEDACSTAT.FSM_DONE and
+// FLASH:FEDACSTAT.RVF_INT
+// AUX_COMB AUX combined event, the corresponding flag
+// register is here AUX_EVCTL:EVTOMCUFLAGS
+// I2C_IRQ Interrupt event from I2C
+// AON_RTC_COMB Event from AON_RTC, controlled by the
+// AON_RTC:CTL.COMB_EV_MASK setting
+// OSC_COMB Combined event from Oscillator control
+// BATMON_COMB Combined event from battery monitor
+// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the
+// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET
+// settings
+// NONE Always inactive
+#define EVENT_GPT2BCAPTSEL_EV_W 7
+#define EVENT_GPT2BCAPTSEL_EV_M 0x0000007F
+#define EVENT_GPT2BCAPTSEL_EV_S 0
+#define EVENT_GPT2BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079
+#define EVENT_GPT2BCAPTSEL_EV_AON_RTC_UPD 0x00000077
+#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073
+#define EVENT_GPT2BCAPTSEL_EV_AUX_OBSMUX0 0x00000072
+#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071
+#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_DONE 0x00000070
+#define EVENT_GPT2BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F
+#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E
+#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D
+#define EVENT_GPT2BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C
+#define EVENT_GPT2BCAPTSEL_EV_AUX_COMPB 0x0000006B
+#define EVENT_GPT2BCAPTSEL_EV_AUX_COMPA 0x0000006A
+#define EVENT_GPT2BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069
+#define EVENT_GPT2BCAPTSEL_EV_PORT_EVENT5 0x0000005A
+#define EVENT_GPT2BCAPTSEL_EV_PORT_EVENT4 0x00000059
+#define EVENT_GPT2BCAPTSEL_EV_GPT3B_CMP 0x00000044
+#define EVENT_GPT2BCAPTSEL_EV_GPT3A_CMP 0x00000043
+#define EVENT_GPT2BCAPTSEL_EV_GPT2B_CMP 0x00000042
+#define EVENT_GPT2BCAPTSEL_EV_GPT2A_CMP 0x00000041
+#define EVENT_GPT2BCAPTSEL_EV_GPT1B_CMP 0x00000040
+#define EVENT_GPT2BCAPTSEL_EV_GPT1A_CMP 0x0000003F
+#define EVENT_GPT2BCAPTSEL_EV_GPT0B_CMP 0x0000003E
+#define EVENT_GPT2BCAPTSEL_EV_GPT0A_CMP 0x0000003D
+#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C
+#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B
+#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A
+#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER2_EV1 0x00000039
+#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER2_EV0 0x00000038
+#define EVENT_GPT2BCAPTSEL_EV_UART1_COMB 0x00000025
+#define EVENT_GPT2BCAPTSEL_EV_UART0_COMB 0x00000024
+#define EVENT_GPT2BCAPTSEL_EV_SSI1_COMB 0x00000023
+#define EVENT_GPT2BCAPTSEL_EV_SSI0_COMB 0x00000022
+#define EVENT_GPT2BCAPTSEL_EV_RFC_CPE_1 0x0000001E
+#define EVENT_GPT2BCAPTSEL_EV_RFC_CPE_0 0x0000001B
+#define EVENT_GPT2BCAPTSEL_EV_RFC_HW_COMB 0x0000001A
+#define EVENT_GPT2BCAPTSEL_EV_RFC_CMD_ACK 0x00000019
+#define EVENT_GPT2BCAPTSEL_EV_FLASH 0x00000015
+#define EVENT_GPT2BCAPTSEL_EV_AUX_COMB 0x0000000B
+#define EVENT_GPT2BCAPTSEL_EV_I2C_IRQ 0x00000009
+#define EVENT_GPT2BCAPTSEL_EV_AON_RTC_COMB 0x00000007
+#define EVENT_GPT2BCAPTSEL_EV_OSC_COMB 0x00000006
+#define EVENT_GPT2BCAPTSEL_EV_BATMON_COMB 0x00000005
+#define EVENT_GPT2BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004
+#define EVENT_GPT2BCAPTSEL_EV_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH1SSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// UART0_RX_DMASREQ UART0 RX DMA single request, controlled by
+// UART0:DMACTL.RXDMAE
+#define EVENT_UDMACH1SSEL_EV_W 7
+#define EVENT_UDMACH1SSEL_EV_M 0x0000007F
+#define EVENT_UDMACH1SSEL_EV_S 0
+#define EVENT_UDMACH1SSEL_EV_UART0_RX_DMASREQ 0x00000031
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH1BSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// UART0_RX_DMABREQ UART0 RX DMA burst request, controlled by
+// UART0:DMACTL.RXDMAE
+#define EVENT_UDMACH1BSEL_EV_W 7
+#define EVENT_UDMACH1BSEL_EV_M 0x0000007F
+#define EVENT_UDMACH1BSEL_EV_S 0
+#define EVENT_UDMACH1BSEL_EV_UART0_RX_DMABREQ 0x00000030
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH2SSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// UART0_TX_DMASREQ UART0 TX DMA single request, controlled by
+// UART0:DMACTL.TXDMAE
+#define EVENT_UDMACH2SSEL_EV_W 7
+#define EVENT_UDMACH2SSEL_EV_M 0x0000007F
+#define EVENT_UDMACH2SSEL_EV_S 0
+#define EVENT_UDMACH2SSEL_EV_UART0_TX_DMASREQ 0x00000033
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH2BSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// UART0_TX_DMABREQ UART0 TX DMA burst request, controlled by
+// UART0:DMACTL.TXDMAE
+#define EVENT_UDMACH2BSEL_EV_W 7
+#define EVENT_UDMACH2BSEL_EV_M 0x0000007F
+#define EVENT_UDMACH2BSEL_EV_S 0
+#define EVENT_UDMACH2BSEL_EV_UART0_TX_DMABREQ 0x00000032
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH3SSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// SSI0_RX_DMASREQ SSI0 RX DMA single request, controlled by
+// SSI0:DMACR.RXDMAE
+#define EVENT_UDMACH3SSEL_EV_W 7
+#define EVENT_UDMACH3SSEL_EV_M 0x0000007F
+#define EVENT_UDMACH3SSEL_EV_S 0
+#define EVENT_UDMACH3SSEL_EV_SSI0_RX_DMASREQ 0x00000029
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH3BSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// SSI0_RX_DMABREQ SSI0 RX DMA burst request , controlled by
+// SSI0:DMACR.RXDMAE
+#define EVENT_UDMACH3BSEL_EV_W 7
+#define EVENT_UDMACH3BSEL_EV_M 0x0000007F
+#define EVENT_UDMACH3BSEL_EV_S 0
+#define EVENT_UDMACH3BSEL_EV_SSI0_RX_DMABREQ 0x00000028
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH4SSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// SSI0_TX_DMASREQ SSI0 TX DMA single request, controlled by
+// SSI0:DMACR.TXDMAE
+#define EVENT_UDMACH4SSEL_EV_W 7
+#define EVENT_UDMACH4SSEL_EV_M 0x0000007F
+#define EVENT_UDMACH4SSEL_EV_S 0
+#define EVENT_UDMACH4SSEL_EV_SSI0_TX_DMASREQ 0x0000002B
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH4BSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// SSI0_TX_DMABREQ SSI0 TX DMA burst request , controlled by
+// SSI0:DMACR.TXDMAE
+#define EVENT_UDMACH4BSEL_EV_W 7
+#define EVENT_UDMACH4BSEL_EV_M 0x0000007F
+#define EVENT_UDMACH4BSEL_EV_S 0
+#define EVENT_UDMACH4BSEL_EV_SSI0_TX_DMABREQ 0x0000002A
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH5SSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// UART1_RX_DMASREQ UART1 RX DMA single request, controlled by
+// UART1:DMACTL.RXDMAE
+#define EVENT_UDMACH5SSEL_EV_W 7
+#define EVENT_UDMACH5SSEL_EV_M 0x0000007F
+#define EVENT_UDMACH5SSEL_EV_S 0
+#define EVENT_UDMACH5SSEL_EV_UART1_RX_DMASREQ 0x00000035
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH5BSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// UART1_RX_DMABREQ UART1 RX DMA burst request, controlled by
+// UART1:DMACTL.RXDMAE
+#define EVENT_UDMACH5BSEL_EV_W 7
+#define EVENT_UDMACH5BSEL_EV_M 0x0000007F
+#define EVENT_UDMACH5BSEL_EV_S 0
+#define EVENT_UDMACH5BSEL_EV_UART1_RX_DMABREQ 0x00000034
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH6SSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// UART1_TX_DMASREQ UART1 TX DMA single request, controlled by
+// UART1:DMACTL.TXDMAE
+#define EVENT_UDMACH6SSEL_EV_W 7
+#define EVENT_UDMACH6SSEL_EV_M 0x0000007F
+#define EVENT_UDMACH6SSEL_EV_S 0
+#define EVENT_UDMACH6SSEL_EV_UART1_TX_DMASREQ 0x00000037
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH6BSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// UART1_TX_DMABREQ UART1 TX DMA burst request, controlled by
+// UART1:DMACTL.TXDMAE
+#define EVENT_UDMACH6BSEL_EV_W 7
+#define EVENT_UDMACH6BSEL_EV_M 0x0000007F
+#define EVENT_UDMACH6BSEL_EV_S 0
+#define EVENT_UDMACH6BSEL_EV_UART1_TX_DMABREQ 0x00000036
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH7SSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// AUX_DMASREQ DMA single request event from AUX, configured by
+// AUX_EVCTL:DMACTL
+#define EVENT_UDMACH7SSEL_EV_W 7
+#define EVENT_UDMACH7SSEL_EV_M 0x0000007F
+#define EVENT_UDMACH7SSEL_EV_S 0
+#define EVENT_UDMACH7SSEL_EV_AUX_DMASREQ 0x00000075
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH7BSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// AUX_DMABREQ DMA burst request event from AUX, configured by
+// AUX_EVCTL:DMACTL
+#define EVENT_UDMACH7BSEL_EV_W 7
+#define EVENT_UDMACH7BSEL_EV_M 0x0000007F
+#define EVENT_UDMACH7BSEL_EV_S 0
+#define EVENT_UDMACH7BSEL_EV_AUX_DMABREQ 0x00000076
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH8SSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// AUX_SW_DMABREQ DMA sofware trigger from AUX, triggered by
+// AUX_EVCTL:DMASWREQ.START
+#define EVENT_UDMACH8SSEL_EV_W 7
+#define EVENT_UDMACH8SSEL_EV_M 0x0000007F
+#define EVENT_UDMACH8SSEL_EV_S 0
+#define EVENT_UDMACH8SSEL_EV_AUX_SW_DMABREQ 0x00000074
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH8BSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// AUX_SW_DMABREQ DMA sofware trigger from AUX, triggered by
+// AUX_EVCTL:DMASWREQ.START
+#define EVENT_UDMACH8BSEL_EV_W 7
+#define EVENT_UDMACH8BSEL_EV_M 0x0000007F
+#define EVENT_UDMACH8BSEL_EV_S 0
+#define EVENT_UDMACH8BSEL_EV_AUX_SW_DMABREQ 0x00000074
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH9SSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read/write selection value
+//
+// Writing any other value than values defined by a ENUM may result in
+// undefined behavior.
+// ENUMs:
+// ALWAYS_ACTIVE Always asserted
+// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV
+// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV
+// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV
+// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV
+// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV
+// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV
+// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV
+// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV
+// TIE_LOW Not used tied to 0
+// NONE Always inactive
+#define EVENT_UDMACH9SSEL_EV_W 7
+#define EVENT_UDMACH9SSEL_EV_M 0x0000007F
+#define EVENT_UDMACH9SSEL_EV_S 0
+#define EVENT_UDMACH9SSEL_EV_ALWAYS_ACTIVE 0x00000079
+#define EVENT_UDMACH9SSEL_EV_GPT3B_DMABREQ 0x00000054
+#define EVENT_UDMACH9SSEL_EV_GPT3A_DMABREQ 0x00000053
+#define EVENT_UDMACH9SSEL_EV_GPT2B_DMABREQ 0x00000052
+#define EVENT_UDMACH9SSEL_EV_GPT2A_DMABREQ 0x00000051
+#define EVENT_UDMACH9SSEL_EV_GPT1B_DMABREQ 0x00000050
+#define EVENT_UDMACH9SSEL_EV_GPT1A_DMABREQ 0x0000004F
+#define EVENT_UDMACH9SSEL_EV_GPT0B_DMABREQ 0x0000004E
+#define EVENT_UDMACH9SSEL_EV_GPT0A_DMABREQ 0x0000004D
+#define EVENT_UDMACH9SSEL_EV_TIE_LOW 0x00000045
+#define EVENT_UDMACH9SSEL_EV_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH9BSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read/write selection value
+//
+// Writing any other value than values defined by a ENUM may result in
+// undefined behavior.
+// ENUMs:
+// ALWAYS_ACTIVE Always asserted
+// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV
+// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV
+// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV
+// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV
+// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV
+// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV
+// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV
+// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV
+// NONE Always inactive
+#define EVENT_UDMACH9BSEL_EV_W 7
+#define EVENT_UDMACH9BSEL_EV_M 0x0000007F
+#define EVENT_UDMACH9BSEL_EV_S 0
+#define EVENT_UDMACH9BSEL_EV_ALWAYS_ACTIVE 0x00000079
+#define EVENT_UDMACH9BSEL_EV_GPT3B_DMABREQ 0x00000054
+#define EVENT_UDMACH9BSEL_EV_GPT3A_DMABREQ 0x00000053
+#define EVENT_UDMACH9BSEL_EV_GPT2B_DMABREQ 0x00000052
+#define EVENT_UDMACH9BSEL_EV_GPT2A_DMABREQ 0x00000051
+#define EVENT_UDMACH9BSEL_EV_GPT1B_DMABREQ 0x00000050
+#define EVENT_UDMACH9BSEL_EV_GPT1A_DMABREQ 0x0000004F
+#define EVENT_UDMACH9BSEL_EV_GPT0B_DMABREQ 0x0000004E
+#define EVENT_UDMACH9BSEL_EV_GPT0A_DMABREQ 0x0000004D
+#define EVENT_UDMACH9BSEL_EV_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH10SSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read/write selection value
+//
+// Writing any other value than values defined by a ENUM may result in
+// undefined behavior.
+// ENUMs:
+// ALWAYS_ACTIVE Always asserted
+// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV
+// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV
+// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV
+// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV
+// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV
+// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV
+// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV
+// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV
+// TIE_LOW Not used tied to 0
+// NONE Always inactive
+#define EVENT_UDMACH10SSEL_EV_W 7
+#define EVENT_UDMACH10SSEL_EV_M 0x0000007F
+#define EVENT_UDMACH10SSEL_EV_S 0
+#define EVENT_UDMACH10SSEL_EV_ALWAYS_ACTIVE 0x00000079
+#define EVENT_UDMACH10SSEL_EV_GPT3B_DMABREQ 0x00000054
+#define EVENT_UDMACH10SSEL_EV_GPT3A_DMABREQ 0x00000053
+#define EVENT_UDMACH10SSEL_EV_GPT2B_DMABREQ 0x00000052
+#define EVENT_UDMACH10SSEL_EV_GPT2A_DMABREQ 0x00000051
+#define EVENT_UDMACH10SSEL_EV_GPT1B_DMABREQ 0x00000050
+#define EVENT_UDMACH10SSEL_EV_GPT1A_DMABREQ 0x0000004F
+#define EVENT_UDMACH10SSEL_EV_GPT0B_DMABREQ 0x0000004E
+#define EVENT_UDMACH10SSEL_EV_GPT0A_DMABREQ 0x0000004D
+#define EVENT_UDMACH10SSEL_EV_TIE_LOW 0x00000046
+#define EVENT_UDMACH10SSEL_EV_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH10BSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read/write selection value
+//
+// Writing any other value than values defined by a ENUM may result in
+// undefined behavior.
+// ENUMs:
+// ALWAYS_ACTIVE Always asserted
+// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV
+// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV
+// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV
+// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV
+// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV
+// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV
+// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV
+// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV
+// NONE Always inactive
+#define EVENT_UDMACH10BSEL_EV_W 7
+#define EVENT_UDMACH10BSEL_EV_M 0x0000007F
+#define EVENT_UDMACH10BSEL_EV_S 0
+#define EVENT_UDMACH10BSEL_EV_ALWAYS_ACTIVE 0x00000079
+#define EVENT_UDMACH10BSEL_EV_GPT3B_DMABREQ 0x00000054
+#define EVENT_UDMACH10BSEL_EV_GPT3A_DMABREQ 0x00000053
+#define EVENT_UDMACH10BSEL_EV_GPT2B_DMABREQ 0x00000052
+#define EVENT_UDMACH10BSEL_EV_GPT2A_DMABREQ 0x00000051
+#define EVENT_UDMACH10BSEL_EV_GPT1B_DMABREQ 0x00000050
+#define EVENT_UDMACH10BSEL_EV_GPT1A_DMABREQ 0x0000004F
+#define EVENT_UDMACH10BSEL_EV_GPT0B_DMABREQ 0x0000004E
+#define EVENT_UDMACH10BSEL_EV_GPT0A_DMABREQ 0x0000004D
+#define EVENT_UDMACH10BSEL_EV_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH11SSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read/write selection value
+//
+// Writing any other value than values defined by a ENUM may result in
+// undefined behavior.
+// ENUMs:
+// ALWAYS_ACTIVE Always asserted
+// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV
+// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV
+// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV
+// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV
+// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV
+// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV
+// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV
+// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV
+// TIE_LOW Not used tied to 0
+// NONE Always inactive
+#define EVENT_UDMACH11SSEL_EV_W 7
+#define EVENT_UDMACH11SSEL_EV_M 0x0000007F
+#define EVENT_UDMACH11SSEL_EV_S 0
+#define EVENT_UDMACH11SSEL_EV_ALWAYS_ACTIVE 0x00000079
+#define EVENT_UDMACH11SSEL_EV_GPT3B_DMABREQ 0x00000054
+#define EVENT_UDMACH11SSEL_EV_GPT3A_DMABREQ 0x00000053
+#define EVENT_UDMACH11SSEL_EV_GPT2B_DMABREQ 0x00000052
+#define EVENT_UDMACH11SSEL_EV_GPT2A_DMABREQ 0x00000051
+#define EVENT_UDMACH11SSEL_EV_GPT1B_DMABREQ 0x00000050
+#define EVENT_UDMACH11SSEL_EV_GPT1A_DMABREQ 0x0000004F
+#define EVENT_UDMACH11SSEL_EV_GPT0B_DMABREQ 0x0000004E
+#define EVENT_UDMACH11SSEL_EV_GPT0A_DMABREQ 0x0000004D
+#define EVENT_UDMACH11SSEL_EV_TIE_LOW 0x00000047
+#define EVENT_UDMACH11SSEL_EV_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH11BSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read/write selection value
+//
+// Writing any other value than values defined by a ENUM may result in
+// undefined behavior.
+// ENUMs:
+// ALWAYS_ACTIVE Always asserted
+// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV
+// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV
+// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV
+// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV
+// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV
+// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV
+// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV
+// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV
+// NONE Always inactive
+#define EVENT_UDMACH11BSEL_EV_W 7
+#define EVENT_UDMACH11BSEL_EV_M 0x0000007F
+#define EVENT_UDMACH11BSEL_EV_S 0
+#define EVENT_UDMACH11BSEL_EV_ALWAYS_ACTIVE 0x00000079
+#define EVENT_UDMACH11BSEL_EV_GPT3B_DMABREQ 0x00000054
+#define EVENT_UDMACH11BSEL_EV_GPT3A_DMABREQ 0x00000053
+#define EVENT_UDMACH11BSEL_EV_GPT2B_DMABREQ 0x00000052
+#define EVENT_UDMACH11BSEL_EV_GPT2A_DMABREQ 0x00000051
+#define EVENT_UDMACH11BSEL_EV_GPT1B_DMABREQ 0x00000050
+#define EVENT_UDMACH11BSEL_EV_GPT1A_DMABREQ 0x0000004F
+#define EVENT_UDMACH11BSEL_EV_GPT0B_DMABREQ 0x0000004E
+#define EVENT_UDMACH11BSEL_EV_GPT0A_DMABREQ 0x0000004D
+#define EVENT_UDMACH11BSEL_EV_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH12SSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read/write selection value
+//
+// Writing any other value than values defined by a ENUM may result in
+// undefined behavior.
+// ENUMs:
+// ALWAYS_ACTIVE Always asserted
+// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV
+// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV
+// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV
+// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV
+// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV
+// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV
+// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV
+// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV
+// TIE_LOW Not used tied to 0
+// NONE Always inactive
+#define EVENT_UDMACH12SSEL_EV_W 7
+#define EVENT_UDMACH12SSEL_EV_M 0x0000007F
+#define EVENT_UDMACH12SSEL_EV_S 0
+#define EVENT_UDMACH12SSEL_EV_ALWAYS_ACTIVE 0x00000079
+#define EVENT_UDMACH12SSEL_EV_GPT3B_DMABREQ 0x00000054
+#define EVENT_UDMACH12SSEL_EV_GPT3A_DMABREQ 0x00000053
+#define EVENT_UDMACH12SSEL_EV_GPT2B_DMABREQ 0x00000052
+#define EVENT_UDMACH12SSEL_EV_GPT2A_DMABREQ 0x00000051
+#define EVENT_UDMACH12SSEL_EV_GPT1B_DMABREQ 0x00000050
+#define EVENT_UDMACH12SSEL_EV_GPT1A_DMABREQ 0x0000004F
+#define EVENT_UDMACH12SSEL_EV_GPT0B_DMABREQ 0x0000004E
+#define EVENT_UDMACH12SSEL_EV_GPT0A_DMABREQ 0x0000004D
+#define EVENT_UDMACH12SSEL_EV_TIE_LOW 0x00000048
+#define EVENT_UDMACH12SSEL_EV_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH12BSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read/write selection value
+//
+// Writing any other value than values defined by a ENUM may result in
+// undefined behavior.
+// ENUMs:
+// ALWAYS_ACTIVE Always asserted
+// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV
+// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV
+// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV
+// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV
+// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV
+// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV
+// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV
+// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV
+// NONE Always inactive
+#define EVENT_UDMACH12BSEL_EV_W 7
+#define EVENT_UDMACH12BSEL_EV_M 0x0000007F
+#define EVENT_UDMACH12BSEL_EV_S 0
+#define EVENT_UDMACH12BSEL_EV_ALWAYS_ACTIVE 0x00000079
+#define EVENT_UDMACH12BSEL_EV_GPT3B_DMABREQ 0x00000054
+#define EVENT_UDMACH12BSEL_EV_GPT3A_DMABREQ 0x00000053
+#define EVENT_UDMACH12BSEL_EV_GPT2B_DMABREQ 0x00000052
+#define EVENT_UDMACH12BSEL_EV_GPT2A_DMABREQ 0x00000051
+#define EVENT_UDMACH12BSEL_EV_GPT1B_DMABREQ 0x00000050
+#define EVENT_UDMACH12BSEL_EV_GPT1A_DMABREQ 0x0000004F
+#define EVENT_UDMACH12BSEL_EV_GPT0B_DMABREQ 0x0000004E
+#define EVENT_UDMACH12BSEL_EV_GPT0A_DMABREQ 0x0000004D
+#define EVENT_UDMACH12BSEL_EV_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH13BSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// AON_PROG2 AON programmable event 2. Event selected by
+// AON_EVENT MCU event selector,
+// AON_EVENT:EVTOMCUSEL.AON_PROG2_EV
+#define EVENT_UDMACH13BSEL_EV_W 7
+#define EVENT_UDMACH13BSEL_EV_M 0x0000007F
+#define EVENT_UDMACH13BSEL_EV_S 0
+#define EVENT_UDMACH13BSEL_EV_AON_PROG2 0x00000003
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH14BSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read/write selection value
+//
+// Writing any other value than values defined by a ENUM may result in
+// undefined behavior.
+// ENUMs:
+// ALWAYS_ACTIVE Always asserted
+// CPU_HALTED CPU halted
+// AON_RTC_UPD RTC periodic event controlled by
+// AON_RTC:CTL.RTC_UPD_EN
+// AUX_DMABREQ DMA burst request event from AUX, configured by
+// AUX_EVCTL:DMACTL
+// AUX_DMASREQ DMA single request event from AUX, configured by
+// AUX_EVCTL:DMACTL
+// AUX_SW_DMABREQ DMA sofware trigger from AUX, triggered by
+// AUX_EVCTL:DMASWREQ.START
+// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status
+// flags are found here AUX_EVCTL:EVTOMCUFLAGS
+// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0
+// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL
+// AUX_ADC_DONE AUX ADC done, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE
+// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by
+// AUX_SMPH:AUTOTAKE
+// AUX_TIMER1_EV AUX timer 1 event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV
+// AUX_TIMER0_EV AUX timer 0 event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV
+// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the
+// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and
+// the AUX_TDC status AUX_TDC:STAT.DONE
+// AUX_COMPB AUX Compare B event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
+// AUX_COMPA AUX Compare A event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
+// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV
+// TRNG_IRQ TRNG Interrupt event, controlled by TRNG:IRQEN.EN
+// SWEV3 Software event 3, triggered by SWEV.SWEV3
+// SWEV2 Software event 2, triggered by SWEV.SWEV2
+// SWEV1 Software event 1, triggered by SWEV.SWEV1
+// SWEV0 Software event 0, triggered by SWEV.SWEV0
+// WDT_NMI Watchdog non maskable interrupt event, controlled
+// by WDT:CTL.INTTYPE
+// CRYPTO_DMA_DONE_IRQ CRYPTO DMA input done event, the correspondingg
+// flag is CRYPTO:IRQSTAT.DMA_IN_DONE. Controlled
+// by CRYPTO:IRQEN.DMA_IN_DONE
+// CRYPTO_RESULT_AVAIL_IRQ CRYPTO result available interupt event, the
+// corresponding flag is found here
+// CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by
+// CRYPTO:IRQSTAT.RESULT_AVAIL
+// PORT_EVENT7 Port capture event from IOC, configured by
+// IOC:IOCFGn.PORT_ID. Events on ports configured
+// with ENUM PORT_EVENT7 wil be routed here.
+// PORT_EVENT6 Port capture event from IOC, configured by
+// IOC:IOCFGn.PORT_ID. Events on ports configured
+// with ENUM PORT_EVENT6 wil be routed here.
+// PORT_EVENT5 Port capture event from IOC, configured by
+// IOC:IOCFGn.PORT_ID. Events on ports configured
+// with ENUM PORT_EVENT4 wil be routed here.
+// PORT_EVENT4 Port capture event from IOC, configured by
+// IOC:IOCFGn.PORT_ID. Events on ports configured
+// with ENUM PORT_EVENT4 wil be routed here.
+// PORT_EVENT3 Port capture event from IOC, configured by
+// IOC:IOCFGn.PORT_ID. Events on ports configured
+// with ENUM PORT_EVENT3 wil be routed here.
+// PORT_EVENT2 Port capture event from IOC, configured by
+// IOC:IOCFGn.PORT_ID. Events on ports configured
+// with ENUM PORT_EVENT2 wil be routed here.
+// PORT_EVENT1 Port capture event from IOC, configured by
+// IOC:IOCFGn.PORT_ID. Events on ports configured
+// with ENUM PORT_EVENT1 wil be routed here.
+// PORT_EVENT0 Port capture event from IOC, configured by
+// IOC:IOCFGn.PORT_ID. Events on ports configured
+// with ENUM PORT_EVENT0 wil be routed here.
+// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV
+// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV
+// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV
+// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV
+// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV
+// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV
+// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV
+// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV
+// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT
+// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT
+// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT
+// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT
+// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT
+// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT
+// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT
+// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT
+// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE
+// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3
+// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2
+// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1
+// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0
+// UART1_TX_DMASREQ UART1 TX DMA single request, controlled by
+// UART1:DMACTL.TXDMAE
+// UART1_TX_DMABREQ UART1 TX DMA burst request, controlled by
+// UART1:DMACTL.TXDMAE
+// UART1_RX_DMASREQ UART1 RX DMA single request, controlled by
+// UART1:DMACTL.RXDMAE
+// UART1_RX_DMABREQ UART1 RX DMA burst request, controlled by
+// UART1:DMACTL.RXDMAE
+// UART0_TX_DMASREQ UART0 TX DMA single request, controlled by
+// UART0:DMACTL.TXDMAE
+// UART0_TX_DMABREQ UART0 TX DMA burst request, controlled by
+// UART0:DMACTL.TXDMAE
+// UART0_RX_DMASREQ UART0 RX DMA single request, controlled by
+// UART0:DMACTL.RXDMAE
+// UART0_RX_DMABREQ UART0 RX DMA burst request, controlled by
+// UART0:DMACTL.RXDMAE
+// SSI1_TX_DMASREQ SSI1 TX DMA single request, controlled by
+// SSI0:DMACR.TXDMAE
+// SSI1_TX_DMABREQ SSI1 TX DMA burst request , controlled by
+// SSI0:DMACR.TXDMAE
+// SSI1_RX_DMASREQ SSI1 RX DMA single request, controlled by
+// SSI0:DMACR.RXDMAE
+// SSI1_RX_DMABREQ SSI1 RX DMA burst request , controlled by
+// SSI0:DMACR.RXDMAE
+// SSI0_TX_DMASREQ SSI0 TX DMA single request, controlled by
+// SSI0:DMACR.TXDMAE
+// SSI0_TX_DMABREQ SSI0 TX DMA burst request , controlled by
+// SSI0:DMACR.TXDMAE
+// SSI0_RX_DMASREQ SSI0 RX DMA single request, controlled by
+// SSI0:DMACR.RXDMAE
+// SSI0_RX_DMABREQ SSI0 RX DMA burst request , controlled by
+// SSI0:DMACR.RXDMAE
+// DMA_DONE_COMB Combined DMA done, corresponding flags are here
+// UDMA0:REQDONE
+// DMA_ERR DMA bus error, corresponds to UDMA0:ERROR.STATUS
+// UART1_COMB UART1 combined interrupt, interrupt flags are
+// found here UART1:MIS
+// UART0_COMB UART0 combined interrupt, interrupt flags are
+// found here UART0:MIS
+// SSI1_COMB SSI1 combined interrupt, interrupt flags are found
+// here SSI1:MIS
+// SSI0_COMB SSI0 combined interrupt, interrupt flags are found
+// here SSI0:MIS
+// PKA_IRQ PKA Interrupt event
+// RFC_CPE_1 Combined Interrupt for CPE Generated events.
+// Corresponding flags are here
+// RFC_DBELL:RFCPEIFG. Only interrupts selected
+// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a
+// RFC_CPE_1 event
+// AUX_SWEV1 AUX software event 1, triggered by
+// AUX_EVCTL:SWEVSET.SWEV1, also available as
+// AUX_EVENT2 AON wake up event.
+// MCU domain wakeup control
+// AON_EVENT:MCUWUSEL
+// RFC_CPE_0 Combined Interrupt for CPE Generated events.
+// Corresponding flags are here
+// RFC_DBELL:RFCPEIFG. Only interrupts selected
+// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a
+// RFC_CPE_0 event
+// RFC_HW_COMB Combined RFC hardware interrupt, corresponding
+// flag is here RFC_DBELL:RFHWIFG
+// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt,
+// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG
+// WDT_IRQ Watchdog interrupt event, controlled by
+// WDT:CTL.INTEN
+// DMA_CH18_DONE DMA done for software tiggered UDMA channel 18,
+// see UDMA0:SOFTREQ
+// FLASH FLASH controller error event, the status flags
+// are FLASH:FEDACSTAT.FSM_DONE and
+// FLASH:FEDACSTAT.RVF_INT
+// DMA_CH0_DONE DMA done for software tiggered UDMA channel 0, see
+// UDMA0:SOFTREQ
+// GPT1B GPT1B interrupt event, controlled by GPT1:TBMR
+// GPT1A GPT1A interrupt event, controlled by GPT1:TAMR
+// GPT0B GPT0B interrupt event, controlled by GPT0:TBMR
+// GPT0A GPT0A interrupt event, controlled by GPT0:TAMR
+// GPT3B GPT3B interrupt event, controlled by GPT3:TBMR
+// GPT3A GPT3A interrupt event, controlled by GPT3:TAMR
+// GPT2B GPT2B interrupt event, controlled by GPT2:TBMR
+// GPT2A GPT2A interrupt event, controlled by GPT2:TAMR
+// AUX_COMB AUX combined event, the corresponding flag
+// register is here AUX_EVCTL:EVTOMCUFLAGS
+// AON_AUX_SWEV0 AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0
+// I2C_IRQ Interrupt event from I2C
+// I2S_IRQ Interrupt event from I2S
+// AON_RTC_COMB Event from AON_RTC, controlled by the
+// AON_RTC:CTL.COMB_EV_MASK setting
+// OSC_COMB Combined event from Oscillator control
+// BATMON_COMB Combined event from battery monitor
+// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the
+// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET
+// settings
+// AON_PROG2 AON programmable event 2. Event selected by
+// AON_EVENT MCU event selector,
+// AON_EVENT:EVTOMCUSEL.AON_PROG2_EV
+// AON_PROG1 AON programmable event 1. Event selected by
+// AON_EVENT MCU event selector,
+// AON_EVENT:EVTOMCUSEL.AON_PROG1_EV
+// AON_PROG0 AON programmable event 0. Event selected by
+// AON_EVENT MCU event selector,
+// AON_EVENT:EVTOMCUSEL.AON_PROG0_EV
+// NONE Always inactive
+#define EVENT_UDMACH14BSEL_EV_W 7
+#define EVENT_UDMACH14BSEL_EV_M 0x0000007F
+#define EVENT_UDMACH14BSEL_EV_S 0
+#define EVENT_UDMACH14BSEL_EV_ALWAYS_ACTIVE 0x00000079
+#define EVENT_UDMACH14BSEL_EV_CPU_HALTED 0x00000078
+#define EVENT_UDMACH14BSEL_EV_AON_RTC_UPD 0x00000077
+#define EVENT_UDMACH14BSEL_EV_AUX_DMABREQ 0x00000076
+#define EVENT_UDMACH14BSEL_EV_AUX_DMASREQ 0x00000075
+#define EVENT_UDMACH14BSEL_EV_AUX_SW_DMABREQ 0x00000074
+#define EVENT_UDMACH14BSEL_EV_AUX_ADC_IRQ 0x00000073
+#define EVENT_UDMACH14BSEL_EV_AUX_OBSMUX0 0x00000072
+#define EVENT_UDMACH14BSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071
+#define EVENT_UDMACH14BSEL_EV_AUX_ADC_DONE 0x00000070
+#define EVENT_UDMACH14BSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F
+#define EVENT_UDMACH14BSEL_EV_AUX_TIMER1_EV 0x0000006E
+#define EVENT_UDMACH14BSEL_EV_AUX_TIMER0_EV 0x0000006D
+#define EVENT_UDMACH14BSEL_EV_AUX_TDC_DONE 0x0000006C
+#define EVENT_UDMACH14BSEL_EV_AUX_COMPB 0x0000006B
+#define EVENT_UDMACH14BSEL_EV_AUX_COMPA 0x0000006A
+#define EVENT_UDMACH14BSEL_EV_AUX_AON_WU_EV 0x00000069
+#define EVENT_UDMACH14BSEL_EV_TRNG_IRQ 0x00000068
+#define EVENT_UDMACH14BSEL_EV_SWEV3 0x00000067
+#define EVENT_UDMACH14BSEL_EV_SWEV2 0x00000066
+#define EVENT_UDMACH14BSEL_EV_SWEV1 0x00000065
+#define EVENT_UDMACH14BSEL_EV_SWEV0 0x00000064
+#define EVENT_UDMACH14BSEL_EV_WDT_NMI 0x00000063
+#define EVENT_UDMACH14BSEL_EV_CRYPTO_DMA_DONE_IRQ 0x0000005E
+#define EVENT_UDMACH14BSEL_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D
+#define EVENT_UDMACH14BSEL_EV_PORT_EVENT7 0x0000005C
+#define EVENT_UDMACH14BSEL_EV_PORT_EVENT6 0x0000005B
+#define EVENT_UDMACH14BSEL_EV_PORT_EVENT5 0x0000005A
+#define EVENT_UDMACH14BSEL_EV_PORT_EVENT4 0x00000059
+#define EVENT_UDMACH14BSEL_EV_PORT_EVENT3 0x00000058
+#define EVENT_UDMACH14BSEL_EV_PORT_EVENT2 0x00000057
+#define EVENT_UDMACH14BSEL_EV_PORT_EVENT1 0x00000056
+#define EVENT_UDMACH14BSEL_EV_PORT_EVENT0 0x00000055
+#define EVENT_UDMACH14BSEL_EV_GPT3B_DMABREQ 0x00000054
+#define EVENT_UDMACH14BSEL_EV_GPT3A_DMABREQ 0x00000053
+#define EVENT_UDMACH14BSEL_EV_GPT2B_DMABREQ 0x00000052
+#define EVENT_UDMACH14BSEL_EV_GPT2A_DMABREQ 0x00000051
+#define EVENT_UDMACH14BSEL_EV_GPT1B_DMABREQ 0x00000050
+#define EVENT_UDMACH14BSEL_EV_GPT1A_DMABREQ 0x0000004F
+#define EVENT_UDMACH14BSEL_EV_GPT0B_DMABREQ 0x0000004E
+#define EVENT_UDMACH14BSEL_EV_GPT0A_DMABREQ 0x0000004D
+#define EVENT_UDMACH14BSEL_EV_GPT3B_CMP 0x00000044
+#define EVENT_UDMACH14BSEL_EV_GPT3A_CMP 0x00000043
+#define EVENT_UDMACH14BSEL_EV_GPT2B_CMP 0x00000042
+#define EVENT_UDMACH14BSEL_EV_GPT2A_CMP 0x00000041
+#define EVENT_UDMACH14BSEL_EV_GPT1B_CMP 0x00000040
+#define EVENT_UDMACH14BSEL_EV_GPT1A_CMP 0x0000003F
+#define EVENT_UDMACH14BSEL_EV_GPT0B_CMP 0x0000003E
+#define EVENT_UDMACH14BSEL_EV_GPT0A_CMP 0x0000003D
+#define EVENT_UDMACH14BSEL_EV_AUX_TIMER2_PULSE 0x0000003C
+#define EVENT_UDMACH14BSEL_EV_AUX_TIMER2_EV3 0x0000003B
+#define EVENT_UDMACH14BSEL_EV_AUX_TIMER2_EV2 0x0000003A
+#define EVENT_UDMACH14BSEL_EV_AUX_TIMER2_EV1 0x00000039
+#define EVENT_UDMACH14BSEL_EV_AUX_TIMER2_EV0 0x00000038
+#define EVENT_UDMACH14BSEL_EV_UART1_TX_DMASREQ 0x00000037
+#define EVENT_UDMACH14BSEL_EV_UART1_TX_DMABREQ 0x00000036
+#define EVENT_UDMACH14BSEL_EV_UART1_RX_DMASREQ 0x00000035
+#define EVENT_UDMACH14BSEL_EV_UART1_RX_DMABREQ 0x00000034
+#define EVENT_UDMACH14BSEL_EV_UART0_TX_DMASREQ 0x00000033
+#define EVENT_UDMACH14BSEL_EV_UART0_TX_DMABREQ 0x00000032
+#define EVENT_UDMACH14BSEL_EV_UART0_RX_DMASREQ 0x00000031
+#define EVENT_UDMACH14BSEL_EV_UART0_RX_DMABREQ 0x00000030
+#define EVENT_UDMACH14BSEL_EV_SSI1_TX_DMASREQ 0x0000002F
+#define EVENT_UDMACH14BSEL_EV_SSI1_TX_DMABREQ 0x0000002E
+#define EVENT_UDMACH14BSEL_EV_SSI1_RX_DMASREQ 0x0000002D
+#define EVENT_UDMACH14BSEL_EV_SSI1_RX_DMABREQ 0x0000002C
+#define EVENT_UDMACH14BSEL_EV_SSI0_TX_DMASREQ 0x0000002B
+#define EVENT_UDMACH14BSEL_EV_SSI0_TX_DMABREQ 0x0000002A
+#define EVENT_UDMACH14BSEL_EV_SSI0_RX_DMASREQ 0x00000029
+#define EVENT_UDMACH14BSEL_EV_SSI0_RX_DMABREQ 0x00000028
+#define EVENT_UDMACH14BSEL_EV_DMA_DONE_COMB 0x00000027
+#define EVENT_UDMACH14BSEL_EV_DMA_ERR 0x00000026
+#define EVENT_UDMACH14BSEL_EV_UART1_COMB 0x00000025
+#define EVENT_UDMACH14BSEL_EV_UART0_COMB 0x00000024
+#define EVENT_UDMACH14BSEL_EV_SSI1_COMB 0x00000023
+#define EVENT_UDMACH14BSEL_EV_SSI0_COMB 0x00000022
+#define EVENT_UDMACH14BSEL_EV_PKA_IRQ 0x0000001F
+#define EVENT_UDMACH14BSEL_EV_RFC_CPE_1 0x0000001E
+#define EVENT_UDMACH14BSEL_EV_AUX_SWEV1 0x0000001D
+#define EVENT_UDMACH14BSEL_EV_RFC_CPE_0 0x0000001B
+#define EVENT_UDMACH14BSEL_EV_RFC_HW_COMB 0x0000001A
+#define EVENT_UDMACH14BSEL_EV_RFC_CMD_ACK 0x00000019
+#define EVENT_UDMACH14BSEL_EV_WDT_IRQ 0x00000018
+#define EVENT_UDMACH14BSEL_EV_DMA_CH18_DONE 0x00000016
+#define EVENT_UDMACH14BSEL_EV_FLASH 0x00000015
+#define EVENT_UDMACH14BSEL_EV_DMA_CH0_DONE 0x00000014
+#define EVENT_UDMACH14BSEL_EV_GPT1B 0x00000013
+#define EVENT_UDMACH14BSEL_EV_GPT1A 0x00000012
+#define EVENT_UDMACH14BSEL_EV_GPT0B 0x00000011
+#define EVENT_UDMACH14BSEL_EV_GPT0A 0x00000010
+#define EVENT_UDMACH14BSEL_EV_GPT3B 0x0000000F
+#define EVENT_UDMACH14BSEL_EV_GPT3A 0x0000000E
+#define EVENT_UDMACH14BSEL_EV_GPT2B 0x0000000D
+#define EVENT_UDMACH14BSEL_EV_GPT2A 0x0000000C
+#define EVENT_UDMACH14BSEL_EV_AUX_COMB 0x0000000B
+#define EVENT_UDMACH14BSEL_EV_AON_AUX_SWEV0 0x0000000A
+#define EVENT_UDMACH14BSEL_EV_I2C_IRQ 0x00000009
+#define EVENT_UDMACH14BSEL_EV_I2S_IRQ 0x00000008
+#define EVENT_UDMACH14BSEL_EV_AON_RTC_COMB 0x00000007
+#define EVENT_UDMACH14BSEL_EV_OSC_COMB 0x00000006
+#define EVENT_UDMACH14BSEL_EV_BATMON_COMB 0x00000005
+#define EVENT_UDMACH14BSEL_EV_AON_GPIO_EDGE 0x00000004
+#define EVENT_UDMACH14BSEL_EV_AON_PROG2 0x00000003
+#define EVENT_UDMACH14BSEL_EV_AON_PROG1 0x00000002
+#define EVENT_UDMACH14BSEL_EV_AON_PROG0 0x00000001
+#define EVENT_UDMACH14BSEL_EV_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH15BSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// AON_RTC_COMB Event from AON_RTC, controlled by the
+// AON_RTC:CTL.COMB_EV_MASK setting
+#define EVENT_UDMACH15BSEL_EV_W 7
+#define EVENT_UDMACH15BSEL_EV_M 0x0000007F
+#define EVENT_UDMACH15BSEL_EV_S 0
+#define EVENT_UDMACH15BSEL_EV_AON_RTC_COMB 0x00000007
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH16SSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// SSI1_RX_DMASREQ SSI1 RX DMA single request, controlled by
+// SSI0:DMACR.RXDMAE
+#define EVENT_UDMACH16SSEL_EV_W 7
+#define EVENT_UDMACH16SSEL_EV_M 0x0000007F
+#define EVENT_UDMACH16SSEL_EV_S 0
+#define EVENT_UDMACH16SSEL_EV_SSI1_RX_DMASREQ 0x0000002D
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH16BSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// SSI1_RX_DMABREQ SSI1 RX DMA burst request , controlled by
+// SSI0:DMACR.RXDMAE
+#define EVENT_UDMACH16BSEL_EV_W 7
+#define EVENT_UDMACH16BSEL_EV_M 0x0000007F
+#define EVENT_UDMACH16BSEL_EV_S 0
+#define EVENT_UDMACH16BSEL_EV_SSI1_RX_DMABREQ 0x0000002C
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH17SSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// SSI1_TX_DMASREQ SSI1 TX DMA single request, controlled by
+// SSI0:DMACR.TXDMAE
+#define EVENT_UDMACH17SSEL_EV_W 7
+#define EVENT_UDMACH17SSEL_EV_M 0x0000007F
+#define EVENT_UDMACH17SSEL_EV_S 0
+#define EVENT_UDMACH17SSEL_EV_SSI1_TX_DMASREQ 0x0000002F
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH17BSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// SSI1_TX_DMABREQ SSI1 TX DMA burst request , controlled by
+// SSI0:DMACR.TXDMAE
+#define EVENT_UDMACH17BSEL_EV_W 7
+#define EVENT_UDMACH17BSEL_EV_M 0x0000007F
+#define EVENT_UDMACH17BSEL_EV_S 0
+#define EVENT_UDMACH17BSEL_EV_SSI1_TX_DMABREQ 0x0000002E
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH21SSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// SWEV0 Software event 0, triggered by SWEV.SWEV0
+#define EVENT_UDMACH21SSEL_EV_W 7
+#define EVENT_UDMACH21SSEL_EV_M 0x0000007F
+#define EVENT_UDMACH21SSEL_EV_S 0
+#define EVENT_UDMACH21SSEL_EV_SWEV0 0x00000064
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH21BSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// SWEV0 Software event 0, triggered by SWEV.SWEV0
+#define EVENT_UDMACH21BSEL_EV_W 7
+#define EVENT_UDMACH21BSEL_EV_M 0x0000007F
+#define EVENT_UDMACH21BSEL_EV_S 0
+#define EVENT_UDMACH21BSEL_EV_SWEV0 0x00000064
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH22SSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// SWEV1 Software event 1, triggered by SWEV.SWEV1
+#define EVENT_UDMACH22SSEL_EV_W 7
+#define EVENT_UDMACH22SSEL_EV_M 0x0000007F
+#define EVENT_UDMACH22SSEL_EV_S 0
+#define EVENT_UDMACH22SSEL_EV_SWEV1 0x00000065
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH22BSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// SWEV1 Software event 1, triggered by SWEV.SWEV1
+#define EVENT_UDMACH22BSEL_EV_W 7
+#define EVENT_UDMACH22BSEL_EV_M 0x0000007F
+#define EVENT_UDMACH22BSEL_EV_S 0
+#define EVENT_UDMACH22BSEL_EV_SWEV1 0x00000065
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH23SSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// SWEV2 Software event 2, triggered by SWEV.SWEV2
+#define EVENT_UDMACH23SSEL_EV_W 7
+#define EVENT_UDMACH23SSEL_EV_M 0x0000007F
+#define EVENT_UDMACH23SSEL_EV_S 0
+#define EVENT_UDMACH23SSEL_EV_SWEV2 0x00000066
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH23BSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// SWEV2 Software event 2, triggered by SWEV.SWEV2
+#define EVENT_UDMACH23BSEL_EV_W 7
+#define EVENT_UDMACH23BSEL_EV_M 0x0000007F
+#define EVENT_UDMACH23BSEL_EV_S 0
+#define EVENT_UDMACH23BSEL_EV_SWEV2 0x00000066
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH24SSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// SWEV3 Software event 3, triggered by SWEV.SWEV3
+#define EVENT_UDMACH24SSEL_EV_W 7
+#define EVENT_UDMACH24SSEL_EV_M 0x0000007F
+#define EVENT_UDMACH24SSEL_EV_S 0
+#define EVENT_UDMACH24SSEL_EV_SWEV3 0x00000067
+
+//*****************************************************************************
+//
+// Register: EVENT_O_UDMACH24BSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// SWEV3 Software event 3, triggered by SWEV.SWEV3
+#define EVENT_UDMACH24BSEL_EV_W 7
+#define EVENT_UDMACH24BSEL_EV_M 0x0000007F
+#define EVENT_UDMACH24BSEL_EV_S 0
+#define EVENT_UDMACH24BSEL_EV_SWEV3 0x00000067
+
+//*****************************************************************************
+//
+// Register: EVENT_O_GPT3ACAPTSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read/write selection value
+//
+// Writing any other value than values defined by a ENUM may result in
+// undefined behavior.
+// ENUMs:
+// ALWAYS_ACTIVE Always asserted
+// AON_RTC_UPD RTC periodic event controlled by
+// AON_RTC:CTL.RTC_UPD_EN
+// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status
+// flags are found here AUX_EVCTL:EVTOMCUFLAGS
+// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0
+// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL
+// AUX_ADC_DONE AUX ADC done, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE
+// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by
+// AUX_SMPH:AUTOTAKE
+// AUX_TIMER1_EV AUX timer 1 event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV
+// AUX_TIMER0_EV AUX timer 0 event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV
+// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the
+// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and
+// the AUX_TDC status AUX_TDC:STAT.DONE
+// AUX_COMPB AUX Compare B event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
+// AUX_COMPA AUX Compare A event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
+// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV
+// PORT_EVENT7 Port capture event from IOC, configured by
+// IOC:IOCFGn.PORT_ID. Events on ports configured
+// with ENUM PORT_EVENT7 wil be routed here.
+// PORT_EVENT6 Port capture event from IOC, configured by
+// IOC:IOCFGn.PORT_ID. Events on ports configured
+// with ENUM PORT_EVENT6 wil be routed here.
+// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT
+// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT
+// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT
+// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT
+// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT
+// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT
+// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT
+// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT
+// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE
+// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3
+// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2
+// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1
+// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0
+// UART1_COMB UART1 combined interrupt, interrupt flags are
+// found here UART1:MIS
+// UART0_COMB UART0 combined interrupt, interrupt flags are
+// found here UART0:MIS
+// SSI1_COMB SSI1 combined interrupt, interrupt flags are found
+// here SSI1:MIS
+// SSI0_COMB SSI0 combined interrupt, interrupt flags are found
+// here SSI0:MIS
+// RFC_CPE_1 Combined Interrupt for CPE Generated events.
+// Corresponding flags are here
+// RFC_DBELL:RFCPEIFG. Only interrupts selected
+// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a
+// RFC_CPE_1 event
+// RFC_CPE_0 Combined Interrupt for CPE Generated events.
+// Corresponding flags are here
+// RFC_DBELL:RFCPEIFG. Only interrupts selected
+// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a
+// RFC_CPE_0 event
+// RFC_HW_COMB Combined RFC hardware interrupt, corresponding
+// flag is here RFC_DBELL:RFHWIFG
+// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt,
+// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG
+// FLASH FLASH controller error event, the status flags
+// are FLASH:FEDACSTAT.FSM_DONE and
+// FLASH:FEDACSTAT.RVF_INT
+// AUX_COMB AUX combined event, the corresponding flag
+// register is here AUX_EVCTL:EVTOMCUFLAGS
+// I2C_IRQ Interrupt event from I2C
+// AON_RTC_COMB Event from AON_RTC, controlled by the
+// AON_RTC:CTL.COMB_EV_MASK setting
+// OSC_COMB Combined event from Oscillator control
+// BATMON_COMB Combined event from battery monitor
+// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the
+// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET
+// settings
+// NONE Always inactive
+#define EVENT_GPT3ACAPTSEL_EV_W 7
+#define EVENT_GPT3ACAPTSEL_EV_M 0x0000007F
+#define EVENT_GPT3ACAPTSEL_EV_S 0
+#define EVENT_GPT3ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079
+#define EVENT_GPT3ACAPTSEL_EV_AON_RTC_UPD 0x00000077
+#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073
+#define EVENT_GPT3ACAPTSEL_EV_AUX_OBSMUX0 0x00000072
+#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071
+#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_DONE 0x00000070
+#define EVENT_GPT3ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F
+#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E
+#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D
+#define EVENT_GPT3ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C
+#define EVENT_GPT3ACAPTSEL_EV_AUX_COMPB 0x0000006B
+#define EVENT_GPT3ACAPTSEL_EV_AUX_COMPA 0x0000006A
+#define EVENT_GPT3ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069
+#define EVENT_GPT3ACAPTSEL_EV_PORT_EVENT7 0x0000005C
+#define EVENT_GPT3ACAPTSEL_EV_PORT_EVENT6 0x0000005B
+#define EVENT_GPT3ACAPTSEL_EV_GPT3B_CMP 0x00000044
+#define EVENT_GPT3ACAPTSEL_EV_GPT3A_CMP 0x00000043
+#define EVENT_GPT3ACAPTSEL_EV_GPT2B_CMP 0x00000042
+#define EVENT_GPT3ACAPTSEL_EV_GPT2A_CMP 0x00000041
+#define EVENT_GPT3ACAPTSEL_EV_GPT1B_CMP 0x00000040
+#define EVENT_GPT3ACAPTSEL_EV_GPT1A_CMP 0x0000003F
+#define EVENT_GPT3ACAPTSEL_EV_GPT0B_CMP 0x0000003E
+#define EVENT_GPT3ACAPTSEL_EV_GPT0A_CMP 0x0000003D
+#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C
+#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B
+#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A
+#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER2_EV1 0x00000039
+#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER2_EV0 0x00000038
+#define EVENT_GPT3ACAPTSEL_EV_UART1_COMB 0x00000025
+#define EVENT_GPT3ACAPTSEL_EV_UART0_COMB 0x00000024
+#define EVENT_GPT3ACAPTSEL_EV_SSI1_COMB 0x00000023
+#define EVENT_GPT3ACAPTSEL_EV_SSI0_COMB 0x00000022
+#define EVENT_GPT3ACAPTSEL_EV_RFC_CPE_1 0x0000001E
+#define EVENT_GPT3ACAPTSEL_EV_RFC_CPE_0 0x0000001B
+#define EVENT_GPT3ACAPTSEL_EV_RFC_HW_COMB 0x0000001A
+#define EVENT_GPT3ACAPTSEL_EV_RFC_CMD_ACK 0x00000019
+#define EVENT_GPT3ACAPTSEL_EV_FLASH 0x00000015
+#define EVENT_GPT3ACAPTSEL_EV_AUX_COMB 0x0000000B
+#define EVENT_GPT3ACAPTSEL_EV_I2C_IRQ 0x00000009
+#define EVENT_GPT3ACAPTSEL_EV_AON_RTC_COMB 0x00000007
+#define EVENT_GPT3ACAPTSEL_EV_OSC_COMB 0x00000006
+#define EVENT_GPT3ACAPTSEL_EV_BATMON_COMB 0x00000005
+#define EVENT_GPT3ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004
+#define EVENT_GPT3ACAPTSEL_EV_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Register: EVENT_O_GPT3BCAPTSEL
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read/write selection value
+//
+// Writing any other value than values defined by a ENUM may result in
+// undefined behavior.
+// ENUMs:
+// ALWAYS_ACTIVE Always asserted
+// AON_RTC_UPD RTC periodic event controlled by
+// AON_RTC:CTL.RTC_UPD_EN
+// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status
+// flags are found here AUX_EVCTL:EVTOMCUFLAGS
+// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0
+// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL
+// AUX_ADC_DONE AUX ADC done, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE
+// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by
+// AUX_SMPH:AUTOTAKE
+// AUX_TIMER1_EV AUX timer 1 event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV
+// AUX_TIMER0_EV AUX timer 0 event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV
+// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the
+// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and
+// the AUX_TDC status AUX_TDC:STAT.DONE
+// AUX_COMPB AUX Compare B event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB
+// AUX_COMPA AUX Compare A event, corresponds to
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA
+// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV
+// PORT_EVENT7 Port capture event from IOC, configured by
+// IOC:IOCFGn.PORT_ID. Events on ports configured
+// with ENUM PORT_EVENT7 wil be routed here.
+// PORT_EVENT6 Port capture event from IOC, configured by
+// IOC:IOCFGn.PORT_ID. Events on ports configured
+// with ENUM PORT_EVENT6 wil be routed here.
+// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT
+// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT
+// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT
+// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT
+// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT
+// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT
+// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT
+// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT
+// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE
+// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3
+// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2
+// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1
+// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag
+// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0
+// UART1_COMB UART1 combined interrupt, interrupt flags are
+// found here UART1:MIS
+// UART0_COMB UART0 combined interrupt, interrupt flags are
+// found here UART0:MIS
+// SSI1_COMB SSI1 combined interrupt, interrupt flags are found
+// here SSI1:MIS
+// SSI0_COMB SSI0 combined interrupt, interrupt flags are found
+// here SSI0:MIS
+// RFC_CPE_1 Combined Interrupt for CPE Generated events.
+// Corresponding flags are here
+// RFC_DBELL:RFCPEIFG. Only interrupts selected
+// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a
+// RFC_CPE_1 event
+// RFC_CPE_0 Combined Interrupt for CPE Generated events.
+// Corresponding flags are here
+// RFC_DBELL:RFCPEIFG. Only interrupts selected
+// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a
+// RFC_CPE_0 event
+// RFC_HW_COMB Combined RFC hardware interrupt, corresponding
+// flag is here RFC_DBELL:RFHWIFG
+// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt,
+// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG
+// FLASH FLASH controller error event, the status flags
+// are FLASH:FEDACSTAT.FSM_DONE and
+// FLASH:FEDACSTAT.RVF_INT
+// AUX_COMB AUX combined event, the corresponding flag
+// register is here AUX_EVCTL:EVTOMCUFLAGS
+// I2C_IRQ Interrupt event from I2C
+// AON_RTC_COMB Event from AON_RTC, controlled by the
+// AON_RTC:CTL.COMB_EV_MASK setting
+// OSC_COMB Combined event from Oscillator control
+// BATMON_COMB Combined event from battery monitor
+// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the
+// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET
+// settings
+// NONE Always inactive
+#define EVENT_GPT3BCAPTSEL_EV_W 7
+#define EVENT_GPT3BCAPTSEL_EV_M 0x0000007F
+#define EVENT_GPT3BCAPTSEL_EV_S 0
+#define EVENT_GPT3BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079
+#define EVENT_GPT3BCAPTSEL_EV_AON_RTC_UPD 0x00000077
+#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073
+#define EVENT_GPT3BCAPTSEL_EV_AUX_OBSMUX0 0x00000072
+#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071
+#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_DONE 0x00000070
+#define EVENT_GPT3BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F
+#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E
+#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D
+#define EVENT_GPT3BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C
+#define EVENT_GPT3BCAPTSEL_EV_AUX_COMPB 0x0000006B
+#define EVENT_GPT3BCAPTSEL_EV_AUX_COMPA 0x0000006A
+#define EVENT_GPT3BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069
+#define EVENT_GPT3BCAPTSEL_EV_PORT_EVENT7 0x0000005C
+#define EVENT_GPT3BCAPTSEL_EV_PORT_EVENT6 0x0000005B
+#define EVENT_GPT3BCAPTSEL_EV_GPT3B_CMP 0x00000044
+#define EVENT_GPT3BCAPTSEL_EV_GPT3A_CMP 0x00000043
+#define EVENT_GPT3BCAPTSEL_EV_GPT2B_CMP 0x00000042
+#define EVENT_GPT3BCAPTSEL_EV_GPT2A_CMP 0x00000041
+#define EVENT_GPT3BCAPTSEL_EV_GPT1B_CMP 0x00000040
+#define EVENT_GPT3BCAPTSEL_EV_GPT1A_CMP 0x0000003F
+#define EVENT_GPT3BCAPTSEL_EV_GPT0B_CMP 0x0000003E
+#define EVENT_GPT3BCAPTSEL_EV_GPT0A_CMP 0x0000003D
+#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C
+#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B
+#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A
+#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER2_EV1 0x00000039
+#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER2_EV0 0x00000038
+#define EVENT_GPT3BCAPTSEL_EV_UART1_COMB 0x00000025
+#define EVENT_GPT3BCAPTSEL_EV_UART0_COMB 0x00000024
+#define EVENT_GPT3BCAPTSEL_EV_SSI1_COMB 0x00000023
+#define EVENT_GPT3BCAPTSEL_EV_SSI0_COMB 0x00000022
+#define EVENT_GPT3BCAPTSEL_EV_RFC_CPE_1 0x0000001E
+#define EVENT_GPT3BCAPTSEL_EV_RFC_CPE_0 0x0000001B
+#define EVENT_GPT3BCAPTSEL_EV_RFC_HW_COMB 0x0000001A
+#define EVENT_GPT3BCAPTSEL_EV_RFC_CMD_ACK 0x00000019
+#define EVENT_GPT3BCAPTSEL_EV_FLASH 0x00000015
+#define EVENT_GPT3BCAPTSEL_EV_AUX_COMB 0x0000000B
+#define EVENT_GPT3BCAPTSEL_EV_I2C_IRQ 0x00000009
+#define EVENT_GPT3BCAPTSEL_EV_AON_RTC_COMB 0x00000007
+#define EVENT_GPT3BCAPTSEL_EV_OSC_COMB 0x00000006
+#define EVENT_GPT3BCAPTSEL_EV_BATMON_COMB 0x00000005
+#define EVENT_GPT3BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004
+#define EVENT_GPT3BCAPTSEL_EV_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Register: EVENT_O_AUXSEL0
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read/write selection value
+//
+// Writing any other value than values defined by a ENUM may result in
+// undefined behavior.
+// ENUMs:
+// ALWAYS_ACTIVE Always asserted
+// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT
+// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT
+// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT
+// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT
+// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT
+// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT
+// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT
+// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT
+// GPT1B GPT1B interrupt event, controlled by GPT1:TBMR
+// GPT1A GPT1A interrupt event, controlled by GPT1:TAMR
+// GPT0B GPT0B interrupt event, controlled by GPT0:TBMR
+// GPT0A GPT0A interrupt event, controlled by GPT0:TAMR
+// GPT3B GPT3B interrupt event, controlled by GPT3:TBMR
+// GPT3A GPT3A interrupt event, controlled by GPT3:TAMR
+// GPT2B GPT2B interrupt event, controlled by GPT2:TBMR
+// GPT2A GPT2A interrupt event, controlled by GPT2:TAMR
+// NONE Always inactive
+#define EVENT_AUXSEL0_EV_W 7
+#define EVENT_AUXSEL0_EV_M 0x0000007F
+#define EVENT_AUXSEL0_EV_S 0
+#define EVENT_AUXSEL0_EV_ALWAYS_ACTIVE 0x00000079
+#define EVENT_AUXSEL0_EV_GPT3B_CMP 0x00000044
+#define EVENT_AUXSEL0_EV_GPT3A_CMP 0x00000043
+#define EVENT_AUXSEL0_EV_GPT2B_CMP 0x00000042
+#define EVENT_AUXSEL0_EV_GPT2A_CMP 0x00000041
+#define EVENT_AUXSEL0_EV_GPT1B_CMP 0x00000040
+#define EVENT_AUXSEL0_EV_GPT1A_CMP 0x0000003F
+#define EVENT_AUXSEL0_EV_GPT0B_CMP 0x0000003E
+#define EVENT_AUXSEL0_EV_GPT0A_CMP 0x0000003D
+#define EVENT_AUXSEL0_EV_GPT1B 0x00000013
+#define EVENT_AUXSEL0_EV_GPT1A 0x00000012
+#define EVENT_AUXSEL0_EV_GPT0B 0x00000011
+#define EVENT_AUXSEL0_EV_GPT0A 0x00000010
+#define EVENT_AUXSEL0_EV_GPT3B 0x0000000F
+#define EVENT_AUXSEL0_EV_GPT3A 0x0000000E
+#define EVENT_AUXSEL0_EV_GPT2B 0x0000000D
+#define EVENT_AUXSEL0_EV_GPT2A 0x0000000C
+#define EVENT_AUXSEL0_EV_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Register: EVENT_O_CM3NMISEL0
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read only selection value
+// ENUMs:
+// WDT_NMI Watchdog non maskable interrupt event, controlled
+// by WDT:CTL.INTTYPE
+#define EVENT_CM3NMISEL0_EV_W 7
+#define EVENT_CM3NMISEL0_EV_M 0x0000007F
+#define EVENT_CM3NMISEL0_EV_S 0
+#define EVENT_CM3NMISEL0_EV_WDT_NMI 0x00000063
+
+//*****************************************************************************
+//
+// Register: EVENT_O_I2SSTMPSEL0
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read/write selection value
+//
+// Writing any other value than values defined by a ENUM may result in
+// undefined behavior.
+// ENUMs:
+// ALWAYS_ACTIVE Always asserted
+// NONE Always inactive
+#define EVENT_I2SSTMPSEL0_EV_W 7
+#define EVENT_I2SSTMPSEL0_EV_M 0x0000007F
+#define EVENT_I2SSTMPSEL0_EV_S 0
+#define EVENT_I2SSTMPSEL0_EV_ALWAYS_ACTIVE 0x00000079
+#define EVENT_I2SSTMPSEL0_EV_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Register: EVENT_O_FRZSEL0
+//
+//*****************************************************************************
+// Field: [6:0] EV
+//
+// Read/write selection value
+//
+// Writing any other value than values defined by a ENUM may result in
+// undefined behavior.
+// ENUMs:
+// ALWAYS_ACTIVE Always asserted
+// CPU_HALTED CPU halted
+// NONE Always inactive
+#define EVENT_FRZSEL0_EV_W 7
+#define EVENT_FRZSEL0_EV_M 0x0000007F
+#define EVENT_FRZSEL0_EV_S 0
+#define EVENT_FRZSEL0_EV_ALWAYS_ACTIVE 0x00000079
+#define EVENT_FRZSEL0_EV_CPU_HALTED 0x00000078
+#define EVENT_FRZSEL0_EV_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Register: EVENT_O_SWEV
+//
+//*****************************************************************************
+// Field: [24] SWEV3
+//
+// Writing "1" to this bit when the value is "0" triggers the Software 3 event.
+#define EVENT_SWEV_SWEV3 0x01000000
+#define EVENT_SWEV_SWEV3_BITN 24
+#define EVENT_SWEV_SWEV3_M 0x01000000
+#define EVENT_SWEV_SWEV3_S 24
+
+// Field: [16] SWEV2
+//
+// Writing "1" to this bit when the value is "0" triggers the Software 2 event.
+#define EVENT_SWEV_SWEV2 0x00010000
+#define EVENT_SWEV_SWEV2_BITN 16
+#define EVENT_SWEV_SWEV2_M 0x00010000
+#define EVENT_SWEV_SWEV2_S 16
+
+// Field: [8] SWEV1
+//
+// Writing "1" to this bit when the value is "0" triggers the Software 1 event.
+#define EVENT_SWEV_SWEV1 0x00000100
+#define EVENT_SWEV_SWEV1_BITN 8
+#define EVENT_SWEV_SWEV1_M 0x00000100
+#define EVENT_SWEV_SWEV1_S 8
+
+// Field: [0] SWEV0
+//
+// Writing "1" to this bit when the value is "0" triggers the Software 0 event.
+#define EVENT_SWEV_SWEV0 0x00000001
+#define EVENT_SWEV_SWEV0_BITN 0
+#define EVENT_SWEV_SWEV0_M 0x00000001
+#define EVENT_SWEV_SWEV0_S 0
+
+
+#endif // __EVENT__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_fcfg1.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_fcfg1.h
new file mode 100644
index 0000000..cd6cb57
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_fcfg1.h
@@ -0,0 +1,2904 @@
+/******************************************************************************
+* Filename: hw_fcfg1_h
+* Revised: 2018-11-06 14:08:24 +0100 (Tue, 06 Nov 2018)
+* Revision: 53237
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_FCFG1_H__
+#define __HW_FCFG1_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// FCFG1 component
+//
+//*****************************************************************************
+// Misc configurations
+#define FCFG1_O_MISC_CONF_1 0x000000A0
+
+// Internal
+#define FCFG1_O_MISC_CONF_2 0x000000A4
+
+// Internal
+#define FCFG1_O_HPOSC_MEAS_5 0x000000B0
+
+// Internal
+#define FCFG1_O_HPOSC_MEAS_4 0x000000B4
+
+// Internal
+#define FCFG1_O_HPOSC_MEAS_3 0x000000B8
+
+// Internal
+#define FCFG1_O_HPOSC_MEAS_2 0x000000BC
+
+// Internal
+#define FCFG1_O_HPOSC_MEAS_1 0x000000C0
+
+// Internal
+#define FCFG1_O_CONFIG_CC26_FE 0x000000C4
+
+// Internal
+#define FCFG1_O_CONFIG_CC13_FE 0x000000C8
+
+// Internal
+#define FCFG1_O_CONFIG_RF_COMMON 0x000000CC
+
+// Internal
+#define FCFG1_O_CONFIG_SYNTH_DIV2_CC26_2G4 0x000000D0
+
+// Internal
+#define FCFG1_O_CONFIG_SYNTH_DIV2_CC13_2G4 0x000000D4
+
+// Internal
+#define FCFG1_O_CONFIG_SYNTH_DIV2_CC26_1G 0x000000D8
+
+// Internal
+#define FCFG1_O_CONFIG_SYNTH_DIV2_CC13_1G 0x000000DC
+
+// Internal
+#define FCFG1_O_CONFIG_SYNTH_DIV4_CC26 0x000000E0
+
+// Internal
+#define FCFG1_O_CONFIG_SYNTH_DIV4_CC13 0x000000E4
+
+// Internal
+#define FCFG1_O_CONFIG_SYNTH_DIV5 0x000000E8
+
+// Internal
+#define FCFG1_O_CONFIG_SYNTH_DIV6_CC26 0x000000EC
+
+// Internal
+#define FCFG1_O_CONFIG_SYNTH_DIV6_CC13 0x000000F0
+
+// Internal
+#define FCFG1_O_CONFIG_SYNTH_DIV10 0x000000F4
+
+// Internal
+#define FCFG1_O_CONFIG_SYNTH_DIV12_CC26 0x000000F8
+
+// Internal
+#define FCFG1_O_CONFIG_SYNTH_DIV12_CC13 0x000000FC
+
+// Internal
+#define FCFG1_O_CONFIG_SYNTH_DIV15 0x00000100
+
+// Internal
+#define FCFG1_O_CONFIG_SYNTH_DIV30 0x00000104
+
+// Flash information
+#define FCFG1_O_FLASH_NUMBER 0x00000164
+
+// Flash information
+#define FCFG1_O_FLASH_COORDINATE 0x0000016C
+
+// Internal
+#define FCFG1_O_FLASH_E_P 0x00000170
+
+// Internal
+#define FCFG1_O_FLASH_C_E_P_R 0x00000174
+
+// Internal
+#define FCFG1_O_FLASH_P_R_PV 0x00000178
+
+// Internal
+#define FCFG1_O_FLASH_EH_SEQ 0x0000017C
+
+// Internal
+#define FCFG1_O_FLASH_VHV_E 0x00000180
+
+// Internal
+#define FCFG1_O_FLASH_PP 0x00000184
+
+// Internal
+#define FCFG1_O_FLASH_PROG_EP 0x00000188
+
+// Internal
+#define FCFG1_O_FLASH_ERA_PW 0x0000018C
+
+// Internal
+#define FCFG1_O_FLASH_VHV 0x00000190
+
+// Internal
+#define FCFG1_O_FLASH_VHV_PV 0x00000194
+
+// Internal
+#define FCFG1_O_FLASH_V 0x00000198
+
+// User Identification.
+#define FCFG1_O_USER_ID 0x00000294
+
+// Internal
+#define FCFG1_O_FLASH_OTP_DATA3 0x000002B0
+
+// Internal
+#define FCFG1_O_ANA2_TRIM 0x000002B4
+
+// Internal
+#define FCFG1_O_LDO_TRIM 0x000002B8
+
+// MAC BLE Address 0
+#define FCFG1_O_MAC_BLE_0 0x000002E8
+
+// MAC BLE Address 1
+#define FCFG1_O_MAC_BLE_1 0x000002EC
+
+// MAC IEEE 802.15.4 Address 0
+#define FCFG1_O_MAC_15_4_0 0x000002F0
+
+// MAC IEEE 802.15.4 Address 1
+#define FCFG1_O_MAC_15_4_1 0x000002F4
+
+// Internal
+#define FCFG1_O_FLASH_OTP_DATA4 0x00000308
+
+// Miscellaneous Trim Parameters
+#define FCFG1_O_MISC_TRIM 0x0000030C
+
+// Internal
+#define FCFG1_O_RCOSC_HF_TEMPCOMP 0x00000310
+
+// IcePick Device Identification
+#define FCFG1_O_ICEPICK_DEVICE_ID 0x00000318
+
+// Factory Configuration (FCFG1) Revision
+#define FCFG1_O_FCFG1_REVISION 0x0000031C
+
+// Misc OTP Data
+#define FCFG1_O_MISC_OTP_DATA 0x00000320
+
+// IO Configuration
+#define FCFG1_O_IOCONF 0x00000344
+
+// Internal
+#define FCFG1_O_CONFIG_IF_ADC 0x0000034C
+
+// Internal
+#define FCFG1_O_CONFIG_OSC_TOP 0x00000350
+
+// AUX_ADC Gain in Absolute Reference Mode
+#define FCFG1_O_SOC_ADC_ABS_GAIN 0x0000035C
+
+// AUX_ADC Gain in Relative Reference Mode
+#define FCFG1_O_SOC_ADC_REL_GAIN 0x00000360
+
+// AUX_ADC Temperature Offsets in Absolute Reference Mode
+#define FCFG1_O_SOC_ADC_OFFSET_INT 0x00000368
+
+// Internal
+#define FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT 0x0000036C
+
+// Internal
+#define FCFG1_O_AMPCOMP_TH1 0x00000370
+
+// Internal
+#define FCFG1_O_AMPCOMP_TH2 0x00000374
+
+// Internal
+#define FCFG1_O_AMPCOMP_CTRL1 0x00000378
+
+// Internal
+#define FCFG1_O_ANABYPASS_VALUE2 0x0000037C
+
+// Internal
+#define FCFG1_O_VOLT_TRIM 0x00000388
+
+// OSC Configuration
+#define FCFG1_O_OSC_CONF 0x0000038C
+
+// Internal
+#define FCFG1_O_FREQ_OFFSET 0x00000390
+
+// Internal
+#define FCFG1_O_MISC_OTP_DATA_1 0x00000398
+
+// Shadow of EFUSE:DIE_ID_0 register
+#define FCFG1_O_SHDW_DIE_ID_0 0x000003D0
+
+// Shadow of EFUSE:DIE_ID_1 register
+#define FCFG1_O_SHDW_DIE_ID_1 0x000003D4
+
+// Shadow of EFUSE:DIE_ID_2 register
+#define FCFG1_O_SHDW_DIE_ID_2 0x000003D8
+
+// Shadow of EFUSE:DIE_ID_3 register
+#define FCFG1_O_SHDW_DIE_ID_3 0x000003DC
+
+// Internal
+#define FCFG1_O_SHDW_OSC_BIAS_LDO_TRIM 0x000003F8
+
+// Internal
+#define FCFG1_O_SHDW_ANA_TRIM 0x000003FC
+
+// Internal
+#define FCFG1_O_DAC_BIAS_CNF 0x0000040C
+
+// Internal
+#define FCFG1_O_TFW_PROBE 0x00000418
+
+// Internal
+#define FCFG1_O_TFW_FT 0x0000041C
+
+// Internal
+#define FCFG1_O_DAC_CAL0 0x00000420
+
+// Internal
+#define FCFG1_O_DAC_CAL1 0x00000424
+
+// Internal
+#define FCFG1_O_DAC_CAL2 0x00000428
+
+// Internal
+#define FCFG1_O_DAC_CAL3 0x0000042C
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_MISC_CONF_1
+//
+//*****************************************************************************
+// Field: [7:0] DEVICE_MINOR_REV
+//
+// HW minor revision number (a value of 0xFF shall be treated equally to 0x00).
+// Any test of this field by SW should be implemented as a 'greater or equal'
+// comparison as signed integer.
+// Value may change without warning.
+#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_W 8
+#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_M 0x000000FF
+#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_MISC_CONF_2
+//
+//*****************************************************************************
+// Field: [7:0] HPOSC_COMP_P3
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_W 8
+#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_M 0x000000FF
+#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_HPOSC_MEAS_5
+//
+//*****************************************************************************
+// Field: [31:16] HPOSC_D5
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_HPOSC_MEAS_5_HPOSC_D5_W 16
+#define FCFG1_HPOSC_MEAS_5_HPOSC_D5_M 0xFFFF0000
+#define FCFG1_HPOSC_MEAS_5_HPOSC_D5_S 16
+
+// Field: [15:8] HPOSC_T5
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_HPOSC_MEAS_5_HPOSC_T5_W 8
+#define FCFG1_HPOSC_MEAS_5_HPOSC_T5_M 0x0000FF00
+#define FCFG1_HPOSC_MEAS_5_HPOSC_T5_S 8
+
+// Field: [7:0] HPOSC_DT5
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_HPOSC_MEAS_5_HPOSC_DT5_W 8
+#define FCFG1_HPOSC_MEAS_5_HPOSC_DT5_M 0x000000FF
+#define FCFG1_HPOSC_MEAS_5_HPOSC_DT5_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_HPOSC_MEAS_4
+//
+//*****************************************************************************
+// Field: [31:16] HPOSC_D4
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_HPOSC_MEAS_4_HPOSC_D4_W 16
+#define FCFG1_HPOSC_MEAS_4_HPOSC_D4_M 0xFFFF0000
+#define FCFG1_HPOSC_MEAS_4_HPOSC_D4_S 16
+
+// Field: [15:8] HPOSC_T4
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_HPOSC_MEAS_4_HPOSC_T4_W 8
+#define FCFG1_HPOSC_MEAS_4_HPOSC_T4_M 0x0000FF00
+#define FCFG1_HPOSC_MEAS_4_HPOSC_T4_S 8
+
+// Field: [7:0] HPOSC_DT4
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_HPOSC_MEAS_4_HPOSC_DT4_W 8
+#define FCFG1_HPOSC_MEAS_4_HPOSC_DT4_M 0x000000FF
+#define FCFG1_HPOSC_MEAS_4_HPOSC_DT4_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_HPOSC_MEAS_3
+//
+//*****************************************************************************
+// Field: [31:16] HPOSC_D3
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_HPOSC_MEAS_3_HPOSC_D3_W 16
+#define FCFG1_HPOSC_MEAS_3_HPOSC_D3_M 0xFFFF0000
+#define FCFG1_HPOSC_MEAS_3_HPOSC_D3_S 16
+
+// Field: [15:8] HPOSC_T3
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_HPOSC_MEAS_3_HPOSC_T3_W 8
+#define FCFG1_HPOSC_MEAS_3_HPOSC_T3_M 0x0000FF00
+#define FCFG1_HPOSC_MEAS_3_HPOSC_T3_S 8
+
+// Field: [7:0] HPOSC_DT3
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_HPOSC_MEAS_3_HPOSC_DT3_W 8
+#define FCFG1_HPOSC_MEAS_3_HPOSC_DT3_M 0x000000FF
+#define FCFG1_HPOSC_MEAS_3_HPOSC_DT3_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_HPOSC_MEAS_2
+//
+//*****************************************************************************
+// Field: [31:16] HPOSC_D2
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_HPOSC_MEAS_2_HPOSC_D2_W 16
+#define FCFG1_HPOSC_MEAS_2_HPOSC_D2_M 0xFFFF0000
+#define FCFG1_HPOSC_MEAS_2_HPOSC_D2_S 16
+
+// Field: [15:8] HPOSC_T2
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_HPOSC_MEAS_2_HPOSC_T2_W 8
+#define FCFG1_HPOSC_MEAS_2_HPOSC_T2_M 0x0000FF00
+#define FCFG1_HPOSC_MEAS_2_HPOSC_T2_S 8
+
+// Field: [7:0] HPOSC_DT2
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_HPOSC_MEAS_2_HPOSC_DT2_W 8
+#define FCFG1_HPOSC_MEAS_2_HPOSC_DT2_M 0x000000FF
+#define FCFG1_HPOSC_MEAS_2_HPOSC_DT2_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_HPOSC_MEAS_1
+//
+//*****************************************************************************
+// Field: [31:16] HPOSC_D1
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_HPOSC_MEAS_1_HPOSC_D1_W 16
+#define FCFG1_HPOSC_MEAS_1_HPOSC_D1_M 0xFFFF0000
+#define FCFG1_HPOSC_MEAS_1_HPOSC_D1_S 16
+
+// Field: [15:8] HPOSC_T1
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_HPOSC_MEAS_1_HPOSC_T1_W 8
+#define FCFG1_HPOSC_MEAS_1_HPOSC_T1_M 0x0000FF00
+#define FCFG1_HPOSC_MEAS_1_HPOSC_T1_S 8
+
+// Field: [7:0] HPOSC_DT1
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_HPOSC_MEAS_1_HPOSC_DT1_W 8
+#define FCFG1_HPOSC_MEAS_1_HPOSC_DT1_M 0x000000FF
+#define FCFG1_HPOSC_MEAS_1_HPOSC_DT1_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_CONFIG_CC26_FE
+//
+//*****************************************************************************
+// Field: [31:28] IFAMP_IB
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_CC26_FE_IFAMP_IB_W 4
+#define FCFG1_CONFIG_CC26_FE_IFAMP_IB_M 0xF0000000
+#define FCFG1_CONFIG_CC26_FE_IFAMP_IB_S 28
+
+// Field: [27:24] LNA_IB
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_CC26_FE_LNA_IB_W 4
+#define FCFG1_CONFIG_CC26_FE_LNA_IB_M 0x0F000000
+#define FCFG1_CONFIG_CC26_FE_LNA_IB_S 24
+
+// Field: [23:19] IFAMP_TRIM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_CC26_FE_IFAMP_TRIM_W 5
+#define FCFG1_CONFIG_CC26_FE_IFAMP_TRIM_M 0x00F80000
+#define FCFG1_CONFIG_CC26_FE_IFAMP_TRIM_S 19
+
+// Field: [18:14] CTL_PA0_TRIM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_CC26_FE_CTL_PA0_TRIM_W 5
+#define FCFG1_CONFIG_CC26_FE_CTL_PA0_TRIM_M 0x0007C000
+#define FCFG1_CONFIG_CC26_FE_CTL_PA0_TRIM_S 14
+
+// Field: [13] PATRIMCOMPLETE_N
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_CC26_FE_PATRIMCOMPLETE_N 0x00002000
+#define FCFG1_CONFIG_CC26_FE_PATRIMCOMPLETE_N_BITN 13
+#define FCFG1_CONFIG_CC26_FE_PATRIMCOMPLETE_N_M 0x00002000
+#define FCFG1_CONFIG_CC26_FE_PATRIMCOMPLETE_N_S 13
+
+// Field: [12] RSSITRIMCOMPLETE_N
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_CC26_FE_RSSITRIMCOMPLETE_N 0x00001000
+#define FCFG1_CONFIG_CC26_FE_RSSITRIMCOMPLETE_N_BITN 12
+#define FCFG1_CONFIG_CC26_FE_RSSITRIMCOMPLETE_N_M 0x00001000
+#define FCFG1_CONFIG_CC26_FE_RSSITRIMCOMPLETE_N_S 12
+
+// Field: [7:0] RSSI_OFFSET
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_CC26_FE_RSSI_OFFSET_W 8
+#define FCFG1_CONFIG_CC26_FE_RSSI_OFFSET_M 0x000000FF
+#define FCFG1_CONFIG_CC26_FE_RSSI_OFFSET_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_CONFIG_CC13_FE
+//
+//*****************************************************************************
+// Field: [31:28] IFAMP_IB
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_CC13_FE_IFAMP_IB_W 4
+#define FCFG1_CONFIG_CC13_FE_IFAMP_IB_M 0xF0000000
+#define FCFG1_CONFIG_CC13_FE_IFAMP_IB_S 28
+
+// Field: [27:24] LNA_IB
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_CC13_FE_LNA_IB_W 4
+#define FCFG1_CONFIG_CC13_FE_LNA_IB_M 0x0F000000
+#define FCFG1_CONFIG_CC13_FE_LNA_IB_S 24
+
+// Field: [23:19] IFAMP_TRIM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_CC13_FE_IFAMP_TRIM_W 5
+#define FCFG1_CONFIG_CC13_FE_IFAMP_TRIM_M 0x00F80000
+#define FCFG1_CONFIG_CC13_FE_IFAMP_TRIM_S 19
+
+// Field: [18:14] CTL_PA0_TRIM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_CC13_FE_CTL_PA0_TRIM_W 5
+#define FCFG1_CONFIG_CC13_FE_CTL_PA0_TRIM_M 0x0007C000
+#define FCFG1_CONFIG_CC13_FE_CTL_PA0_TRIM_S 14
+
+// Field: [13] PATRIMCOMPLETE_N
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_CC13_FE_PATRIMCOMPLETE_N 0x00002000
+#define FCFG1_CONFIG_CC13_FE_PATRIMCOMPLETE_N_BITN 13
+#define FCFG1_CONFIG_CC13_FE_PATRIMCOMPLETE_N_M 0x00002000
+#define FCFG1_CONFIG_CC13_FE_PATRIMCOMPLETE_N_S 13
+
+// Field: [12] RSSITRIMCOMPLETE_N
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_CC13_FE_RSSITRIMCOMPLETE_N 0x00001000
+#define FCFG1_CONFIG_CC13_FE_RSSITRIMCOMPLETE_N_BITN 12
+#define FCFG1_CONFIG_CC13_FE_RSSITRIMCOMPLETE_N_M 0x00001000
+#define FCFG1_CONFIG_CC13_FE_RSSITRIMCOMPLETE_N_S 12
+
+// Field: [7:0] RSSI_OFFSET
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_CC13_FE_RSSI_OFFSET_W 8
+#define FCFG1_CONFIG_CC13_FE_RSSI_OFFSET_M 0x000000FF
+#define FCFG1_CONFIG_CC13_FE_RSSI_OFFSET_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_CONFIG_RF_COMMON
+//
+//*****************************************************************************
+// Field: [31] DISABLE_CORNER_CAP
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_RF_COMMON_DISABLE_CORNER_CAP 0x80000000
+#define FCFG1_CONFIG_RF_COMMON_DISABLE_CORNER_CAP_BITN 31
+#define FCFG1_CONFIG_RF_COMMON_DISABLE_CORNER_CAP_M 0x80000000
+#define FCFG1_CONFIG_RF_COMMON_DISABLE_CORNER_CAP_S 31
+
+// Field: [30:25] SLDO_TRIM_OUTPUT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_RF_COMMON_SLDO_TRIM_OUTPUT_W 6
+#define FCFG1_CONFIG_RF_COMMON_SLDO_TRIM_OUTPUT_M 0x7E000000
+#define FCFG1_CONFIG_RF_COMMON_SLDO_TRIM_OUTPUT_S 25
+
+// Field: [21] PA20DBMTRIMCOMPLETE_N
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_RF_COMMON_PA20DBMTRIMCOMPLETE_N 0x00200000
+#define FCFG1_CONFIG_RF_COMMON_PA20DBMTRIMCOMPLETE_N_BITN 21
+#define FCFG1_CONFIG_RF_COMMON_PA20DBMTRIMCOMPLETE_N_M 0x00200000
+#define FCFG1_CONFIG_RF_COMMON_PA20DBMTRIMCOMPLETE_N_S 21
+
+// Field: [20:16] CTL_PA_20DBM_TRIM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_RF_COMMON_CTL_PA_20DBM_TRIM_W 5
+#define FCFG1_CONFIG_RF_COMMON_CTL_PA_20DBM_TRIM_M 0x001F0000
+#define FCFG1_CONFIG_RF_COMMON_CTL_PA_20DBM_TRIM_S 16
+
+// Field: [15:9] RFLDO_TRIM_OUTPUT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_RF_COMMON_RFLDO_TRIM_OUTPUT_W 7
+#define FCFG1_CONFIG_RF_COMMON_RFLDO_TRIM_OUTPUT_M 0x0000FE00
+#define FCFG1_CONFIG_RF_COMMON_RFLDO_TRIM_OUTPUT_S 9
+
+// Field: [8:6] QUANTCTLTHRES
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_RF_COMMON_QUANTCTLTHRES_W 3
+#define FCFG1_CONFIG_RF_COMMON_QUANTCTLTHRES_M 0x000001C0
+#define FCFG1_CONFIG_RF_COMMON_QUANTCTLTHRES_S 6
+
+// Field: [5:0] DACTRIM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_RF_COMMON_DACTRIM_W 6
+#define FCFG1_CONFIG_RF_COMMON_DACTRIM_M 0x0000003F
+#define FCFG1_CONFIG_RF_COMMON_DACTRIM_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_CONFIG_SYNTH_DIV2_CC26_2G4
+//
+//*****************************************************************************
+// Field: [31:28] MIN_ALLOWED_RTRIM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_MIN_ALLOWED_RTRIM_W 4
+#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_MIN_ALLOWED_RTRIM_M 0xF0000000
+#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_MIN_ALLOWED_RTRIM_S 28
+
+// Field: [27:12] RFC_MDM_DEMIQMC0
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_W 16
+#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_M 0x0FFFF000
+#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_S 12
+
+// Field: [11:6] LDOVCO_TRIM_OUTPUT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_LDOVCO_TRIM_OUTPUT_W 6
+#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_LDOVCO_TRIM_OUTPUT_M 0x00000FC0
+#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_LDOVCO_TRIM_OUTPUT_S 6
+
+// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \
+ 0x00000020
+#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \
+ 5
+#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \
+ 0x00000020
+#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \
+ 5
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_CONFIG_SYNTH_DIV2_CC13_2G4
+//
+//*****************************************************************************
+// Field: [31:28] MIN_ALLOWED_RTRIM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_MIN_ALLOWED_RTRIM_W 4
+#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_MIN_ALLOWED_RTRIM_M 0xF0000000
+#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_MIN_ALLOWED_RTRIM_S 28
+
+// Field: [27:12] RFC_MDM_DEMIQMC0
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_W 16
+#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_M 0x0FFFF000
+#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_S 12
+
+// Field: [11:6] LDOVCO_TRIM_OUTPUT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_LDOVCO_TRIM_OUTPUT_W 6
+#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_LDOVCO_TRIM_OUTPUT_M 0x00000FC0
+#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_LDOVCO_TRIM_OUTPUT_S 6
+
+// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \
+ 0x00000020
+#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \
+ 5
+#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \
+ 0x00000020
+#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \
+ 5
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_CONFIG_SYNTH_DIV2_CC26_1G
+//
+//*****************************************************************************
+// Field: [31:28] MIN_ALLOWED_RTRIM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_MIN_ALLOWED_RTRIM_W 4
+#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_MIN_ALLOWED_RTRIM_M 0xF0000000
+#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_MIN_ALLOWED_RTRIM_S 28
+
+// Field: [27:12] RFC_MDM_DEMIQMC0
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_W 16
+#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_M 0x0FFFF000
+#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_S 12
+
+// Field: [11:6] LDOVCO_TRIM_OUTPUT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_LDOVCO_TRIM_OUTPUT_W 6
+#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_LDOVCO_TRIM_OUTPUT_M 0x00000FC0
+#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_LDOVCO_TRIM_OUTPUT_S 6
+
+// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \
+ 0x00000020
+#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \
+ 5
+#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \
+ 0x00000020
+#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \
+ 5
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_CONFIG_SYNTH_DIV2_CC13_1G
+//
+//*****************************************************************************
+// Field: [31:28] MIN_ALLOWED_RTRIM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_MIN_ALLOWED_RTRIM_W 4
+#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_MIN_ALLOWED_RTRIM_M 0xF0000000
+#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_MIN_ALLOWED_RTRIM_S 28
+
+// Field: [27:12] RFC_MDM_DEMIQMC0
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_W 16
+#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_M 0x0FFFF000
+#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_S 12
+
+// Field: [11:6] LDOVCO_TRIM_OUTPUT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_LDOVCO_TRIM_OUTPUT_W 6
+#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_LDOVCO_TRIM_OUTPUT_M 0x00000FC0
+#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_LDOVCO_TRIM_OUTPUT_S 6
+
+// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \
+ 0x00000020
+#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \
+ 5
+#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \
+ 0x00000020
+#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \
+ 5
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_CONFIG_SYNTH_DIV4_CC26
+//
+//*****************************************************************************
+// Field: [31:28] MIN_ALLOWED_RTRIM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV4_CC26_MIN_ALLOWED_RTRIM_W 4
+#define FCFG1_CONFIG_SYNTH_DIV4_CC26_MIN_ALLOWED_RTRIM_M 0xF0000000
+#define FCFG1_CONFIG_SYNTH_DIV4_CC26_MIN_ALLOWED_RTRIM_S 28
+
+// Field: [27:12] RFC_MDM_DEMIQMC0
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_W 16
+#define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_M 0x0FFFF000
+#define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_S 12
+
+// Field: [11:6] LDOVCO_TRIM_OUTPUT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV4_CC26_LDOVCO_TRIM_OUTPUT_W 6
+#define FCFG1_CONFIG_SYNTH_DIV4_CC26_LDOVCO_TRIM_OUTPUT_M 0x00000FC0
+#define FCFG1_CONFIG_SYNTH_DIV4_CC26_LDOVCO_TRIM_OUTPUT_S 6
+
+// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \
+ 0x00000020
+#define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \
+ 5
+#define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \
+ 0x00000020
+#define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \
+ 5
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_CONFIG_SYNTH_DIV4_CC13
+//
+//*****************************************************************************
+// Field: [31:28] MIN_ALLOWED_RTRIM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV4_CC13_MIN_ALLOWED_RTRIM_W 4
+#define FCFG1_CONFIG_SYNTH_DIV4_CC13_MIN_ALLOWED_RTRIM_M 0xF0000000
+#define FCFG1_CONFIG_SYNTH_DIV4_CC13_MIN_ALLOWED_RTRIM_S 28
+
+// Field: [27:12] RFC_MDM_DEMIQMC0
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_W 16
+#define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_M 0x0FFFF000
+#define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_S 12
+
+// Field: [11:6] LDOVCO_TRIM_OUTPUT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV4_CC13_LDOVCO_TRIM_OUTPUT_W 6
+#define FCFG1_CONFIG_SYNTH_DIV4_CC13_LDOVCO_TRIM_OUTPUT_M 0x00000FC0
+#define FCFG1_CONFIG_SYNTH_DIV4_CC13_LDOVCO_TRIM_OUTPUT_S 6
+
+// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \
+ 0x00000020
+#define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \
+ 5
+#define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \
+ 0x00000020
+#define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \
+ 5
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_CONFIG_SYNTH_DIV5
+//
+//*****************************************************************************
+// Field: [31:28] MIN_ALLOWED_RTRIM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV5_MIN_ALLOWED_RTRIM_W 4
+#define FCFG1_CONFIG_SYNTH_DIV5_MIN_ALLOWED_RTRIM_M 0xF0000000
+#define FCFG1_CONFIG_SYNTH_DIV5_MIN_ALLOWED_RTRIM_S 28
+
+// Field: [27:12] RFC_MDM_DEMIQMC0
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_W 16
+#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_M 0x0FFFF000
+#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_S 12
+
+// Field: [11:6] LDOVCO_TRIM_OUTPUT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_W 6
+#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_M 0x00000FC0
+#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_S 6
+
+// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N 0x00000020
+#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \
+ 5
+#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \
+ 0x00000020
+#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \
+ 5
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_CONFIG_SYNTH_DIV6_CC26
+//
+//*****************************************************************************
+// Field: [31:28] MIN_ALLOWED_RTRIM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV6_CC26_MIN_ALLOWED_RTRIM_W 4
+#define FCFG1_CONFIG_SYNTH_DIV6_CC26_MIN_ALLOWED_RTRIM_M 0xF0000000
+#define FCFG1_CONFIG_SYNTH_DIV6_CC26_MIN_ALLOWED_RTRIM_S 28
+
+// Field: [27:12] RFC_MDM_DEMIQMC0
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_W 16
+#define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_M 0x0FFFF000
+#define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_S 12
+
+// Field: [11:6] LDOVCO_TRIM_OUTPUT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV6_CC26_LDOVCO_TRIM_OUTPUT_W 6
+#define FCFG1_CONFIG_SYNTH_DIV6_CC26_LDOVCO_TRIM_OUTPUT_M 0x00000FC0
+#define FCFG1_CONFIG_SYNTH_DIV6_CC26_LDOVCO_TRIM_OUTPUT_S 6
+
+// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \
+ 0x00000020
+#define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \
+ 5
+#define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \
+ 0x00000020
+#define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \
+ 5
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_CONFIG_SYNTH_DIV6_CC13
+//
+//*****************************************************************************
+// Field: [31:28] MIN_ALLOWED_RTRIM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV6_CC13_MIN_ALLOWED_RTRIM_W 4
+#define FCFG1_CONFIG_SYNTH_DIV6_CC13_MIN_ALLOWED_RTRIM_M 0xF0000000
+#define FCFG1_CONFIG_SYNTH_DIV6_CC13_MIN_ALLOWED_RTRIM_S 28
+
+// Field: [27:12] RFC_MDM_DEMIQMC0
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_W 16
+#define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_M 0x0FFFF000
+#define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_S 12
+
+// Field: [11:6] LDOVCO_TRIM_OUTPUT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV6_CC13_LDOVCO_TRIM_OUTPUT_W 6
+#define FCFG1_CONFIG_SYNTH_DIV6_CC13_LDOVCO_TRIM_OUTPUT_M 0x00000FC0
+#define FCFG1_CONFIG_SYNTH_DIV6_CC13_LDOVCO_TRIM_OUTPUT_S 6
+
+// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \
+ 0x00000020
+#define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \
+ 5
+#define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \
+ 0x00000020
+#define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \
+ 5
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_CONFIG_SYNTH_DIV10
+//
+//*****************************************************************************
+// Field: [31:28] MIN_ALLOWED_RTRIM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV10_MIN_ALLOWED_RTRIM_W 4
+#define FCFG1_CONFIG_SYNTH_DIV10_MIN_ALLOWED_RTRIM_M 0xF0000000
+#define FCFG1_CONFIG_SYNTH_DIV10_MIN_ALLOWED_RTRIM_S 28
+
+// Field: [27:12] RFC_MDM_DEMIQMC0
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_W 16
+#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_M 0x0FFFF000
+#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_S 12
+
+// Field: [11:6] LDOVCO_TRIM_OUTPUT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_W 6
+#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_M 0x00000FC0
+#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_S 6
+
+// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \
+ 0x00000020
+#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \
+ 5
+#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \
+ 0x00000020
+#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \
+ 5
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_CONFIG_SYNTH_DIV12_CC26
+//
+//*****************************************************************************
+// Field: [31:28] MIN_ALLOWED_RTRIM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV12_CC26_MIN_ALLOWED_RTRIM_W 4
+#define FCFG1_CONFIG_SYNTH_DIV12_CC26_MIN_ALLOWED_RTRIM_M 0xF0000000
+#define FCFG1_CONFIG_SYNTH_DIV12_CC26_MIN_ALLOWED_RTRIM_S 28
+
+// Field: [27:12] RFC_MDM_DEMIQMC0
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_W 16
+#define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_M 0x0FFFF000
+#define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_S 12
+
+// Field: [11:6] LDOVCO_TRIM_OUTPUT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV12_CC26_LDOVCO_TRIM_OUTPUT_W 6
+#define FCFG1_CONFIG_SYNTH_DIV12_CC26_LDOVCO_TRIM_OUTPUT_M 0x00000FC0
+#define FCFG1_CONFIG_SYNTH_DIV12_CC26_LDOVCO_TRIM_OUTPUT_S 6
+
+// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \
+ 0x00000020
+#define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \
+ 5
+#define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \
+ 0x00000020
+#define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \
+ 5
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_CONFIG_SYNTH_DIV12_CC13
+//
+//*****************************************************************************
+// Field: [31:28] MIN_ALLOWED_RTRIM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV12_CC13_MIN_ALLOWED_RTRIM_W 4
+#define FCFG1_CONFIG_SYNTH_DIV12_CC13_MIN_ALLOWED_RTRIM_M 0xF0000000
+#define FCFG1_CONFIG_SYNTH_DIV12_CC13_MIN_ALLOWED_RTRIM_S 28
+
+// Field: [27:12] RFC_MDM_DEMIQMC0
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_W 16
+#define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_M 0x0FFFF000
+#define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_S 12
+
+// Field: [11:6] LDOVCO_TRIM_OUTPUT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV12_CC13_LDOVCO_TRIM_OUTPUT_W 6
+#define FCFG1_CONFIG_SYNTH_DIV12_CC13_LDOVCO_TRIM_OUTPUT_M 0x00000FC0
+#define FCFG1_CONFIG_SYNTH_DIV12_CC13_LDOVCO_TRIM_OUTPUT_S 6
+
+// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \
+ 0x00000020
+#define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \
+ 5
+#define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \
+ 0x00000020
+#define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \
+ 5
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_CONFIG_SYNTH_DIV15
+//
+//*****************************************************************************
+// Field: [31:28] MIN_ALLOWED_RTRIM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV15_MIN_ALLOWED_RTRIM_W 4
+#define FCFG1_CONFIG_SYNTH_DIV15_MIN_ALLOWED_RTRIM_M 0xF0000000
+#define FCFG1_CONFIG_SYNTH_DIV15_MIN_ALLOWED_RTRIM_S 28
+
+// Field: [27:12] RFC_MDM_DEMIQMC0
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_W 16
+#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_M 0x0FFFF000
+#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_S 12
+
+// Field: [11:6] LDOVCO_TRIM_OUTPUT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_W 6
+#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_M 0x00000FC0
+#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_S 6
+
+// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \
+ 0x00000020
+#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \
+ 5
+#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \
+ 0x00000020
+#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \
+ 5
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_CONFIG_SYNTH_DIV30
+//
+//*****************************************************************************
+// Field: [31:28] MIN_ALLOWED_RTRIM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV30_MIN_ALLOWED_RTRIM_W 4
+#define FCFG1_CONFIG_SYNTH_DIV30_MIN_ALLOWED_RTRIM_M 0xF0000000
+#define FCFG1_CONFIG_SYNTH_DIV30_MIN_ALLOWED_RTRIM_S 28
+
+// Field: [27:12] RFC_MDM_DEMIQMC0
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_W 16
+#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_M 0x0FFFF000
+#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_S 12
+
+// Field: [11:6] LDOVCO_TRIM_OUTPUT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_W 6
+#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_M 0x00000FC0
+#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_S 6
+
+// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \
+ 0x00000020
+#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \
+ 5
+#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \
+ 0x00000020
+#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \
+ 5
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_FLASH_NUMBER
+//
+//*****************************************************************************
+// Field: [31:0] LOT_NUMBER
+//
+// Number of the manufacturing lot that produced this unit.
+#define FCFG1_FLASH_NUMBER_LOT_NUMBER_W 32
+#define FCFG1_FLASH_NUMBER_LOT_NUMBER_M 0xFFFFFFFF
+#define FCFG1_FLASH_NUMBER_LOT_NUMBER_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_FLASH_COORDINATE
+//
+//*****************************************************************************
+// Field: [31:16] XCOORDINATE
+//
+// X coordinate of this unit on the wafer.
+#define FCFG1_FLASH_COORDINATE_XCOORDINATE_W 16
+#define FCFG1_FLASH_COORDINATE_XCOORDINATE_M 0xFFFF0000
+#define FCFG1_FLASH_COORDINATE_XCOORDINATE_S 16
+
+// Field: [15:0] YCOORDINATE
+//
+// Y coordinate of this unit on the wafer.
+#define FCFG1_FLASH_COORDINATE_YCOORDINATE_W 16
+#define FCFG1_FLASH_COORDINATE_YCOORDINATE_M 0x0000FFFF
+#define FCFG1_FLASH_COORDINATE_YCOORDINATE_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_FLASH_E_P
+//
+//*****************************************************************************
+// Field: [31:24] PSU
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_E_P_PSU_W 8
+#define FCFG1_FLASH_E_P_PSU_M 0xFF000000
+#define FCFG1_FLASH_E_P_PSU_S 24
+
+// Field: [23:16] ESU
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_E_P_ESU_W 8
+#define FCFG1_FLASH_E_P_ESU_M 0x00FF0000
+#define FCFG1_FLASH_E_P_ESU_S 16
+
+// Field: [15:8] PVSU
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_E_P_PVSU_W 8
+#define FCFG1_FLASH_E_P_PVSU_M 0x0000FF00
+#define FCFG1_FLASH_E_P_PVSU_S 8
+
+// Field: [7:0] EVSU
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_E_P_EVSU_W 8
+#define FCFG1_FLASH_E_P_EVSU_M 0x000000FF
+#define FCFG1_FLASH_E_P_EVSU_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_FLASH_C_E_P_R
+//
+//*****************************************************************************
+// Field: [31:24] RVSU
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_C_E_P_R_RVSU_W 8
+#define FCFG1_FLASH_C_E_P_R_RVSU_M 0xFF000000
+#define FCFG1_FLASH_C_E_P_R_RVSU_S 24
+
+// Field: [23:16] PV_ACCESS
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_W 8
+#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_M 0x00FF0000
+#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_S 16
+
+// Field: [15:12] A_EXEZ_SETUP
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_W 4
+#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_M 0x0000F000
+#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_S 12
+
+// Field: [11:0] CVSU
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_C_E_P_R_CVSU_W 12
+#define FCFG1_FLASH_C_E_P_R_CVSU_M 0x00000FFF
+#define FCFG1_FLASH_C_E_P_R_CVSU_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_FLASH_P_R_PV
+//
+//*****************************************************************************
+// Field: [31:24] PH
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_P_R_PV_PH_W 8
+#define FCFG1_FLASH_P_R_PV_PH_M 0xFF000000
+#define FCFG1_FLASH_P_R_PV_PH_S 24
+
+// Field: [23:16] RH
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_P_R_PV_RH_W 8
+#define FCFG1_FLASH_P_R_PV_RH_M 0x00FF0000
+#define FCFG1_FLASH_P_R_PV_RH_S 16
+
+// Field: [15:8] PVH
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_P_R_PV_PVH_W 8
+#define FCFG1_FLASH_P_R_PV_PVH_M 0x0000FF00
+#define FCFG1_FLASH_P_R_PV_PVH_S 8
+
+// Field: [7:0] PVH2
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_P_R_PV_PVH2_W 8
+#define FCFG1_FLASH_P_R_PV_PVH2_M 0x000000FF
+#define FCFG1_FLASH_P_R_PV_PVH2_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_FLASH_EH_SEQ
+//
+//*****************************************************************************
+// Field: [31:24] EH
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_EH_SEQ_EH_W 8
+#define FCFG1_FLASH_EH_SEQ_EH_M 0xFF000000
+#define FCFG1_FLASH_EH_SEQ_EH_S 24
+
+// Field: [23:16] SEQ
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_EH_SEQ_SEQ_W 8
+#define FCFG1_FLASH_EH_SEQ_SEQ_M 0x00FF0000
+#define FCFG1_FLASH_EH_SEQ_SEQ_S 16
+
+// Field: [15:12] VSTAT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_EH_SEQ_VSTAT_W 4
+#define FCFG1_FLASH_EH_SEQ_VSTAT_M 0x0000F000
+#define FCFG1_FLASH_EH_SEQ_VSTAT_S 12
+
+// Field: [11:0] SM_FREQUENCY
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_W 12
+#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_M 0x00000FFF
+#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_FLASH_VHV_E
+//
+//*****************************************************************************
+// Field: [31:16] VHV_E_START
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_VHV_E_VHV_E_START_W 16
+#define FCFG1_FLASH_VHV_E_VHV_E_START_M 0xFFFF0000
+#define FCFG1_FLASH_VHV_E_VHV_E_START_S 16
+
+// Field: [15:0] VHV_E_STEP_HIGHT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_W 16
+#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_M 0x0000FFFF
+#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_FLASH_PP
+//
+//*****************************************************************************
+// Field: [31:24] PUMP_SU
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_PP_PUMP_SU_W 8
+#define FCFG1_FLASH_PP_PUMP_SU_M 0xFF000000
+#define FCFG1_FLASH_PP_PUMP_SU_S 24
+
+// Field: [23:16] TRIM3P4
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_PP_TRIM3P4_W 8
+#define FCFG1_FLASH_PP_TRIM3P4_M 0x00FF0000
+#define FCFG1_FLASH_PP_TRIM3P4_S 16
+
+// Field: [15:0] MAX_PP
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_PP_MAX_PP_W 16
+#define FCFG1_FLASH_PP_MAX_PP_M 0x0000FFFF
+#define FCFG1_FLASH_PP_MAX_PP_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_FLASH_PROG_EP
+//
+//*****************************************************************************
+// Field: [31:16] MAX_EP
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_PROG_EP_MAX_EP_W 16
+#define FCFG1_FLASH_PROG_EP_MAX_EP_M 0xFFFF0000
+#define FCFG1_FLASH_PROG_EP_MAX_EP_S 16
+
+// Field: [15:0] PROGRAM_PW
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_W 16
+#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_M 0x0000FFFF
+#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_FLASH_ERA_PW
+//
+//*****************************************************************************
+// Field: [31:0] ERASE_PW
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_ERA_PW_ERASE_PW_W 32
+#define FCFG1_FLASH_ERA_PW_ERASE_PW_M 0xFFFFFFFF
+#define FCFG1_FLASH_ERA_PW_ERASE_PW_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_FLASH_VHV
+//
+//*****************************************************************************
+// Field: [27:24] TRIM13_P
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_VHV_TRIM13_P_W 4
+#define FCFG1_FLASH_VHV_TRIM13_P_M 0x0F000000
+#define FCFG1_FLASH_VHV_TRIM13_P_S 24
+
+// Field: [19:16] VHV_P
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_VHV_VHV_P_W 4
+#define FCFG1_FLASH_VHV_VHV_P_M 0x000F0000
+#define FCFG1_FLASH_VHV_VHV_P_S 16
+
+// Field: [11:8] TRIM13_E
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_VHV_TRIM13_E_W 4
+#define FCFG1_FLASH_VHV_TRIM13_E_M 0x00000F00
+#define FCFG1_FLASH_VHV_TRIM13_E_S 8
+
+// Field: [3:0] VHV_E
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_VHV_VHV_E_W 4
+#define FCFG1_FLASH_VHV_VHV_E_M 0x0000000F
+#define FCFG1_FLASH_VHV_VHV_E_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_FLASH_VHV_PV
+//
+//*****************************************************************************
+// Field: [27:24] TRIM13_PV
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_VHV_PV_TRIM13_PV_W 4
+#define FCFG1_FLASH_VHV_PV_TRIM13_PV_M 0x0F000000
+#define FCFG1_FLASH_VHV_PV_TRIM13_PV_S 24
+
+// Field: [19:16] VHV_PV
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_VHV_PV_VHV_PV_W 4
+#define FCFG1_FLASH_VHV_PV_VHV_PV_M 0x000F0000
+#define FCFG1_FLASH_VHV_PV_VHV_PV_S 16
+
+// Field: [15:8] VCG2P5
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_VHV_PV_VCG2P5_W 8
+#define FCFG1_FLASH_VHV_PV_VCG2P5_M 0x0000FF00
+#define FCFG1_FLASH_VHV_PV_VCG2P5_S 8
+
+// Field: [7:0] VINH
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_VHV_PV_VINH_W 8
+#define FCFG1_FLASH_VHV_PV_VINH_M 0x000000FF
+#define FCFG1_FLASH_VHV_PV_VINH_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_FLASH_V
+//
+//*****************************************************************************
+// Field: [31:24] VSL_P
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_V_VSL_P_W 8
+#define FCFG1_FLASH_V_VSL_P_M 0xFF000000
+#define FCFG1_FLASH_V_VSL_P_S 24
+
+// Field: [23:16] VWL_P
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_V_VWL_P_W 8
+#define FCFG1_FLASH_V_VWL_P_M 0x00FF0000
+#define FCFG1_FLASH_V_VWL_P_S 16
+
+// Field: [15:8] V_READ
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_V_V_READ_W 8
+#define FCFG1_FLASH_V_V_READ_M 0x0000FF00
+#define FCFG1_FLASH_V_V_READ_S 8
+
+// Field: [7:0] TRIM0P8
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_V_TRIM0P8_W 8
+#define FCFG1_FLASH_V_TRIM0P8_M 0x000000FF
+#define FCFG1_FLASH_V_TRIM0P8_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_USER_ID
+//
+//*****************************************************************************
+// Field: [31:28] PG_REV
+//
+// Field used to distinguish revisions of the device
+#define FCFG1_USER_ID_PG_REV_W 4
+#define FCFG1_USER_ID_PG_REV_M 0xF0000000
+#define FCFG1_USER_ID_PG_REV_S 28
+
+// Field: [27:26] VER
+//
+// Version number.
+//
+// 0x0: Bits [25:12] of this register has the stated meaning.
+//
+// Any other setting indicate a different encoding of these bits.
+#define FCFG1_USER_ID_VER_W 2
+#define FCFG1_USER_ID_VER_M 0x0C000000
+#define FCFG1_USER_ID_VER_S 26
+
+// Field: [25] PA
+//
+// 0: Does not support 20dBm PA
+// 1: Supports 20dBM PA
+#define FCFG1_USER_ID_PA 0x02000000
+#define FCFG1_USER_ID_PA_BITN 25
+#define FCFG1_USER_ID_PA_M 0x02000000
+#define FCFG1_USER_ID_PA_S 25
+
+// Field: [23] CC13
+//
+// 0: CC26xx device type
+// 1: CC13xx device type
+#define FCFG1_USER_ID_CC13 0x00800000
+#define FCFG1_USER_ID_CC13_BITN 23
+#define FCFG1_USER_ID_CC13_M 0x00800000
+#define FCFG1_USER_ID_CC13_S 23
+
+// Field: [22:19] SEQUENCE
+//
+// Sequence.
+//
+// Used to differentiate between marketing/orderable product where other fields
+// of this register are the same (temp range, flash size, voltage range etc)
+#define FCFG1_USER_ID_SEQUENCE_W 4
+#define FCFG1_USER_ID_SEQUENCE_M 0x00780000
+#define FCFG1_USER_ID_SEQUENCE_S 19
+
+// Field: [18:16] PKG
+//
+// Package type.
+//
+// 0x0: 4x4mm QFN (RHB) package
+// 0x1: 5x5mm QFN (RSM) package
+// 0x2: 7x7mm QFN (RGZ) package
+// 0x3: Wafer sale package (naked die)
+// 0x4: WCSP (YFV)
+// 0x5: 7x7mm QFN package with Wettable Flanks
+//
+// Other values are reserved for future use.
+// Packages available for a specific device are shown in the device datasheet.
+#define FCFG1_USER_ID_PKG_W 3
+#define FCFG1_USER_ID_PKG_M 0x00070000
+#define FCFG1_USER_ID_PKG_S 16
+
+// Field: [15:12] PROTOCOL
+//
+// Protocols supported.
+//
+// 0x1: BLE
+// 0x2: RF4CE
+// 0x4: Zigbee/6lowpan
+// 0x8: Proprietary
+//
+// More than one protocol can be supported on same device - values above are
+// then combined.
+#define FCFG1_USER_ID_PROTOCOL_W 4
+#define FCFG1_USER_ID_PROTOCOL_M 0x0000F000
+#define FCFG1_USER_ID_PROTOCOL_S 12
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_FLASH_OTP_DATA3
+//
+//*****************************************************************************
+// Field: [31:23] EC_STEP_SIZE
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_W 9
+#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_M 0xFF800000
+#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_S 23
+
+// Field: [22] DO_PRECOND
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND 0x00400000
+#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_BITN 22
+#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_M 0x00400000
+#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_S 22
+
+// Field: [21:18] MAX_EC_LEVEL
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_W 4
+#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_M 0x003C0000
+#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_S 18
+
+// Field: [17:16] TRIM_1P7
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_W 2
+#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_M 0x00030000
+#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_S 16
+
+// Field: [15:8] FLASH_SIZE
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_W 8
+#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_M 0x0000FF00
+#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_S 8
+
+// Field: [7:0] WAIT_SYSCODE
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_W 8
+#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_M 0x000000FF
+#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_ANA2_TRIM
+//
+//*****************************************************************************
+// Field: [31] RCOSCHFCTRIMFRACT_EN
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN 0x80000000
+#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_BITN 31
+#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_M 0x80000000
+#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_S 31
+
+// Field: [30:26] RCOSCHFCTRIMFRACT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_W 5
+#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_M 0x7C000000
+#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_S 26
+
+// Field: [24:23] SET_RCOSC_HF_FINE_RESISTOR
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_W 2
+#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_M 0x01800000
+#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_S 23
+
+// Field: [22] ATESTLF_UDIGLDO_IBIAS_TRIM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM 0x00400000
+#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_BITN 22
+#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_M 0x00400000
+#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_S 22
+
+// Field: [21:15] NANOAMP_RES_TRIM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_W 7
+#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_M 0x003F8000
+#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_S 15
+
+// Field: [11] DITHER_EN
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_ANA2_TRIM_DITHER_EN 0x00000800
+#define FCFG1_ANA2_TRIM_DITHER_EN_BITN 11
+#define FCFG1_ANA2_TRIM_DITHER_EN_M 0x00000800
+#define FCFG1_ANA2_TRIM_DITHER_EN_S 11
+
+// Field: [10:8] DCDC_IPEAK
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_ANA2_TRIM_DCDC_IPEAK_W 3
+#define FCFG1_ANA2_TRIM_DCDC_IPEAK_M 0x00000700
+#define FCFG1_ANA2_TRIM_DCDC_IPEAK_S 8
+
+// Field: [7:6] DEAD_TIME_TRIM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_W 2
+#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_M 0x000000C0
+#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_S 6
+
+// Field: [5:3] DCDC_LOW_EN_SEL
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_W 3
+#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_M 0x00000038
+#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_S 3
+
+// Field: [2:0] DCDC_HIGH_EN_SEL
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_W 3
+#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_M 0x00000007
+#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_LDO_TRIM
+//
+//*****************************************************************************
+// Field: [28:24] VDDR_TRIM_SLEEP
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_W 5
+#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_M 0x1F000000
+#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_S 24
+
+// Field: [18:16] GLDO_CURSRC
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_LDO_TRIM_GLDO_CURSRC_W 3
+#define FCFG1_LDO_TRIM_GLDO_CURSRC_M 0x00070000
+#define FCFG1_LDO_TRIM_GLDO_CURSRC_S 16
+
+// Field: [12:11] ITRIM_DIGLDO_LOAD
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_W 2
+#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_M 0x00001800
+#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_S 11
+
+// Field: [10:8] ITRIM_UDIGLDO
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_W 3
+#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_M 0x00000700
+#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_S 8
+
+// Field: [2:0] VTRIM_DELTA
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_LDO_TRIM_VTRIM_DELTA_W 3
+#define FCFG1_LDO_TRIM_VTRIM_DELTA_M 0x00000007
+#define FCFG1_LDO_TRIM_VTRIM_DELTA_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_MAC_BLE_0
+//
+//*****************************************************************************
+// Field: [31:0] ADDR_0_31
+//
+// The first 32-bits of the 64-bit MAC BLE address
+#define FCFG1_MAC_BLE_0_ADDR_0_31_W 32
+#define FCFG1_MAC_BLE_0_ADDR_0_31_M 0xFFFFFFFF
+#define FCFG1_MAC_BLE_0_ADDR_0_31_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_MAC_BLE_1
+//
+//*****************************************************************************
+// Field: [31:0] ADDR_32_63
+//
+// The last 32-bits of the 64-bit MAC BLE address
+#define FCFG1_MAC_BLE_1_ADDR_32_63_W 32
+#define FCFG1_MAC_BLE_1_ADDR_32_63_M 0xFFFFFFFF
+#define FCFG1_MAC_BLE_1_ADDR_32_63_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_MAC_15_4_0
+//
+//*****************************************************************************
+// Field: [31:0] ADDR_0_31
+//
+// The first 32-bits of the 64-bit MAC 15.4 address
+#define FCFG1_MAC_15_4_0_ADDR_0_31_W 32
+#define FCFG1_MAC_15_4_0_ADDR_0_31_M 0xFFFFFFFF
+#define FCFG1_MAC_15_4_0_ADDR_0_31_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_MAC_15_4_1
+//
+//*****************************************************************************
+// Field: [31:0] ADDR_32_63
+//
+// The last 32-bits of the 64-bit MAC 15.4 address
+#define FCFG1_MAC_15_4_1_ADDR_32_63_W 32
+#define FCFG1_MAC_15_4_1_ADDR_32_63_M 0xFFFFFFFF
+#define FCFG1_MAC_15_4_1_ADDR_32_63_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_FLASH_OTP_DATA4
+//
+//*****************************************************************************
+// Field: [31] STANDBY_MODE_SEL_INT_WRT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT 0x80000000
+#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_BITN 31
+#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_M 0x80000000
+#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_S 31
+
+// Field: [30:29] STANDBY_PW_SEL_INT_WRT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_W 2
+#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_M 0x60000000
+#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_S 29
+
+// Field: [28] DIS_STANDBY_INT_WRT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT 0x10000000
+#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_BITN 28
+#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_M 0x10000000
+#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_S 28
+
+// Field: [27] DIS_IDLE_INT_WRT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT 0x08000000
+#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_BITN 27
+#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_M 0x08000000
+#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_S 27
+
+// Field: [26:24] VIN_AT_X_INT_WRT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_W 3
+#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_M 0x07000000
+#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_S 24
+
+// Field: [23] STANDBY_MODE_SEL_EXT_WRT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT 0x00800000
+#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_BITN 23
+#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_M 0x00800000
+#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_S 23
+
+// Field: [22:21] STANDBY_PW_SEL_EXT_WRT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_W 2
+#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_M 0x00600000
+#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_S 21
+
+// Field: [20] DIS_STANDBY_EXT_WRT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT 0x00100000
+#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_BITN 20
+#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_M 0x00100000
+#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_S 20
+
+// Field: [19] DIS_IDLE_EXT_WRT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT 0x00080000
+#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_BITN 19
+#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_M 0x00080000
+#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_S 19
+
+// Field: [18:16] VIN_AT_X_EXT_WRT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_W 3
+#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_M 0x00070000
+#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_S 16
+
+// Field: [15] STANDBY_MODE_SEL_INT_RD
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD 0x00008000
+#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_BITN 15
+#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M 0x00008000
+#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S 15
+
+// Field: [14:13] STANDBY_PW_SEL_INT_RD
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_W 2
+#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M 0x00006000
+#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S 13
+
+// Field: [12] DIS_STANDBY_INT_RD
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD 0x00001000
+#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_BITN 12
+#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M 0x00001000
+#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_S 12
+
+// Field: [11] DIS_IDLE_INT_RD
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD 0x00000800
+#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_BITN 11
+#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M 0x00000800
+#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S 11
+
+// Field: [10:8] VIN_AT_X_INT_RD
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_W 3
+#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M 0x00000700
+#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S 8
+
+// Field: [7] STANDBY_MODE_SEL_EXT_RD
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD 0x00000080
+#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_BITN 7
+#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M 0x00000080
+#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S 7
+
+// Field: [6:5] STANDBY_PW_SEL_EXT_RD
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_W 2
+#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M 0x00000060
+#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S 5
+
+// Field: [4] DIS_STANDBY_EXT_RD
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD 0x00000010
+#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_BITN 4
+#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M 0x00000010
+#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_S 4
+
+// Field: [3] DIS_IDLE_EXT_RD
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD 0x00000008
+#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_BITN 3
+#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M 0x00000008
+#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S 3
+
+// Field: [2:0] VIN_AT_X_EXT_RD
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_W 3
+#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M 0x00000007
+#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_MISC_TRIM
+//
+//*****************************************************************************
+// Field: [16:12] TRIM_RECHARGE_COMP_OFFSET
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_OFFSET_W 5
+#define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_OFFSET_M 0x0001F000
+#define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_OFFSET_S 12
+
+// Field: [11:8] TRIM_RECHARGE_COMP_REFLEVEL
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_REFLEVEL_W 4
+#define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_REFLEVEL_M 0x00000F00
+#define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_REFLEVEL_S 8
+
+// Field: [7:0] TEMPVSLOPE
+//
+// Signed byte value representing the TEMP slope with battery voltage, in
+// degrees C / V, with four fractional bits.
+#define FCFG1_MISC_TRIM_TEMPVSLOPE_W 8
+#define FCFG1_MISC_TRIM_TEMPVSLOPE_M 0x000000FF
+#define FCFG1_MISC_TRIM_TEMPVSLOPE_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_RCOSC_HF_TEMPCOMP
+//
+//*****************************************************************************
+// Field: [31:24] FINE_RESISTOR
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_W 8
+#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_M 0xFF000000
+#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_S 24
+
+// Field: [23:16] CTRIM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_W 8
+#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_M 0x00FF0000
+#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_S 16
+
+// Field: [15:8] CTRIMFRACT_QUAD
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_W 8
+#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_M 0x0000FF00
+#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_S 8
+
+// Field: [7:0] CTRIMFRACT_SLOPE
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_W 8
+#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_M 0x000000FF
+#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_ICEPICK_DEVICE_ID
+//
+//*****************************************************************************
+// Field: [31:28] PG_REV
+//
+// Field used to distinguish revisions of the device.
+#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_W 4
+#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_M 0xF0000000
+#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_S 28
+
+// Field: [27:12] WAFER_ID
+//
+// Field used to identify silicon die.
+#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_W 16
+#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_M 0x0FFFF000
+#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_S 12
+
+// Field: [11:0] MANUFACTURER_ID
+//
+// Manufacturer code.
+//
+// 0x02F: Texas Instruments
+#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_W 12
+#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_M 0x00000FFF
+#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_FCFG1_REVISION
+//
+//*****************************************************************************
+// Field: [31:0] REV
+//
+// The revision number of the FCFG1 layout. This value will be read by
+// application SW in order to determine which FCFG1 parameters that have valid
+// values. This revision number must be incremented by 1 before any devices are
+// to be produced if the FCFG1 layout has changed since the previous production
+// of devices.
+// Value migth change without warning.
+#define FCFG1_FCFG1_REVISION_REV_W 32
+#define FCFG1_FCFG1_REVISION_REV_M 0xFFFFFFFF
+#define FCFG1_FCFG1_REVISION_REV_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_MISC_OTP_DATA
+//
+//*****************************************************************************
+// Field: [31:28] RCOSC_HF_ITUNE
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_W 4
+#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_M 0xF0000000
+#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_S 28
+
+// Field: [27:20] RCOSC_HF_CRIM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_W 8
+#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_M 0x0FF00000
+#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_S 20
+
+// Field: [19:15] PER_M
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_MISC_OTP_DATA_PER_M_W 5
+#define FCFG1_MISC_OTP_DATA_PER_M_M 0x000F8000
+#define FCFG1_MISC_OTP_DATA_PER_M_S 15
+
+// Field: [14:12] PER_E
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_MISC_OTP_DATA_PER_E_W 3
+#define FCFG1_MISC_OTP_DATA_PER_E_M 0x00007000
+#define FCFG1_MISC_OTP_DATA_PER_E_S 12
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_IOCONF
+//
+//*****************************************************************************
+// Field: [6:0] GPIO_CNT
+//
+// Number of available DIOs.
+#define FCFG1_IOCONF_GPIO_CNT_W 7
+#define FCFG1_IOCONF_GPIO_CNT_M 0x0000007F
+#define FCFG1_IOCONF_GPIO_CNT_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_CONFIG_IF_ADC
+//
+//*****************************************************************************
+// Field: [31:28] FF2ADJ
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_IF_ADC_FF2ADJ_W 4
+#define FCFG1_CONFIG_IF_ADC_FF2ADJ_M 0xF0000000
+#define FCFG1_CONFIG_IF_ADC_FF2ADJ_S 28
+
+// Field: [27:24] FF3ADJ
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_IF_ADC_FF3ADJ_W 4
+#define FCFG1_CONFIG_IF_ADC_FF3ADJ_M 0x0F000000
+#define FCFG1_CONFIG_IF_ADC_FF3ADJ_S 24
+
+// Field: [23:20] INT3ADJ
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_IF_ADC_INT3ADJ_W 4
+#define FCFG1_CONFIG_IF_ADC_INT3ADJ_M 0x00F00000
+#define FCFG1_CONFIG_IF_ADC_INT3ADJ_S 20
+
+// Field: [19:16] FF1ADJ
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_IF_ADC_FF1ADJ_W 4
+#define FCFG1_CONFIG_IF_ADC_FF1ADJ_M 0x000F0000
+#define FCFG1_CONFIG_IF_ADC_FF1ADJ_S 16
+
+// Field: [15:14] AAFCAP
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_IF_ADC_AAFCAP_W 2
+#define FCFG1_CONFIG_IF_ADC_AAFCAP_M 0x0000C000
+#define FCFG1_CONFIG_IF_ADC_AAFCAP_S 14
+
+// Field: [13:10] INT2ADJ
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_IF_ADC_INT2ADJ_W 4
+#define FCFG1_CONFIG_IF_ADC_INT2ADJ_M 0x00003C00
+#define FCFG1_CONFIG_IF_ADC_INT2ADJ_S 10
+
+// Field: [9:5] IFDIGLDO_TRIM_OUTPUT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_W 5
+#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_M 0x000003E0
+#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_S 5
+
+// Field: [4:0] IFANALDO_TRIM_OUTPUT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_W 5
+#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_M 0x0000001F
+#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_CONFIG_OSC_TOP
+//
+//*****************************************************************************
+// Field: [29:26] XOSC_HF_ROW_Q12
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_W 4
+#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_M 0x3C000000
+#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_S 26
+
+// Field: [25:10] XOSC_HF_COLUMN_Q12
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_W 16
+#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_M 0x03FFFC00
+#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_S 10
+
+// Field: [9:2] RCOSCLF_CTUNE_TRIM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_W 8
+#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_M 0x000003FC
+#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_S 2
+
+// Field: [1:0] RCOSCLF_RTUNE_TRIM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_W 2
+#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_M 0x00000003
+#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_SOC_ADC_ABS_GAIN
+//
+//*****************************************************************************
+// Field: [15:0] SOC_ADC_ABS_GAIN_TEMP1
+//
+// SOC_ADC gain in absolute reference mode at temperature 1 (30C). Calculated
+// in production test..
+#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_W 16
+#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_M 0x0000FFFF
+#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_SOC_ADC_REL_GAIN
+//
+//*****************************************************************************
+// Field: [15:0] SOC_ADC_REL_GAIN_TEMP1
+//
+// SOC_ADC gain in relative reference mode at temperature 1 (30C). Calculated
+// in production test..
+#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_W 16
+#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_M 0x0000FFFF
+#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_SOC_ADC_OFFSET_INT
+//
+//*****************************************************************************
+// Field: [23:16] SOC_ADC_REL_OFFSET_TEMP1
+//
+// SOC_ADC offset in relative reference mode at temperature 1 (30C). Signed
+// 8-bit number. Calculated in production test..
+#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_W 8
+#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_M 0x00FF0000
+#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_S 16
+
+// Field: [7:0] SOC_ADC_ABS_OFFSET_TEMP1
+//
+// SOC_ADC offset in absolute reference mode at temperature 1 (30C). Signed
+// 8-bit number. Calculated in production test..
+#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_W 8
+#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_M 0x000000FF
+#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT
+//
+//*****************************************************************************
+// Field: [5:0] SOC_ADC_REF_VOLTAGE_TRIM_TEMP1
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_W \
+ 6
+#define FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_M \
+ 0x0000003F
+#define FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_S \
+ 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_AMPCOMP_TH1
+//
+//*****************************************************************************
+// Field: [23:18] HPMRAMP3_LTH
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_W 6
+#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_M 0x00FC0000
+#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_S 18
+
+// Field: [15:10] HPMRAMP3_HTH
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_W 6
+#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_M 0x0000FC00
+#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_S 10
+
+// Field: [9:6] IBIASCAP_LPTOHP_OL_CNT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_W 4
+#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_M 0x000003C0
+#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_S 6
+
+// Field: [5:0] HPMRAMP1_TH
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_W 6
+#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_M 0x0000003F
+#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_AMPCOMP_TH2
+//
+//*****************************************************************************
+// Field: [31:26] LPMUPDATE_LTH
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_W 6
+#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_M 0xFC000000
+#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_S 26
+
+// Field: [23:18] LPMUPDATE_HTM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_W 6
+#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_M 0x00FC0000
+#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_S 18
+
+// Field: [15:10] ADC_COMP_AMPTH_LPM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_W 6
+#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_M 0x0000FC00
+#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_S 10
+
+// Field: [7:2] ADC_COMP_AMPTH_HPM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_W 6
+#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_M 0x000000FC
+#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_S 2
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_AMPCOMP_CTRL1
+//
+//*****************************************************************************
+// Field: [30] AMPCOMP_REQ_MODE
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE 0x40000000
+#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_BITN 30
+#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_M 0x40000000
+#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_S 30
+
+// Field: [23:20] IBIAS_OFFSET
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_W 4
+#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_M 0x00F00000
+#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_S 20
+
+// Field: [19:16] IBIAS_INIT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_W 4
+#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_M 0x000F0000
+#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_S 16
+
+// Field: [15:8] LPM_IBIAS_WAIT_CNT_FINAL
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_W 8
+#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_M 0x0000FF00
+#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_S 8
+
+// Field: [7:4] CAP_STEP
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_W 4
+#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_M 0x000000F0
+#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_S 4
+
+// Field: [3:0] IBIASCAP_HPTOLP_OL_CNT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_W 4
+#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_M 0x0000000F
+#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_ANABYPASS_VALUE2
+//
+//*****************************************************************************
+// Field: [13:0] XOSC_HF_IBIASTHERM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_W 14
+#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_M 0x00003FFF
+#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_VOLT_TRIM
+//
+//*****************************************************************************
+// Field: [28:24] VDDR_TRIM_HH
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_W 5
+#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_M 0x1F000000
+#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_S 24
+
+// Field: [20:16] VDDR_TRIM_H
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_W 5
+#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_M 0x001F0000
+#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_S 16
+
+// Field: [12:8] VDDR_TRIM_SLEEP_H
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_W 5
+#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_M 0x00001F00
+#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_S 8
+
+// Field: [4:0] TRIMBOD_H
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_VOLT_TRIM_TRIMBOD_H_W 5
+#define FCFG1_VOLT_TRIM_TRIMBOD_H_M 0x0000001F
+#define FCFG1_VOLT_TRIM_TRIMBOD_H_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_OSC_CONF
+//
+//*****************************************************************************
+// Field: [29] ADC_SH_VBUF_EN
+//
+// Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_VBUF_EN.
+#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN 0x20000000
+#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_BITN 29
+#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_M 0x20000000
+#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_S 29
+
+// Field: [28] ADC_SH_MODE_EN
+//
+// Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_MODE_EN.
+#define FCFG1_OSC_CONF_ADC_SH_MODE_EN 0x10000000
+#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_BITN 28
+#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_M 0x10000000
+#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_S 28
+
+// Field: [27] ATESTLF_RCOSCLF_IBIAS_TRIM
+//
+// Trim value for DDI_0_OSC:ATESTCTL.ATESTLF_RCOSCLF_IBIAS_TRIM.
+#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM 0x08000000
+#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_BITN 27
+#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_M 0x08000000
+#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_S 27
+
+// Field: [26:25] XOSCLF_REGULATOR_TRIM
+//
+// Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_REGULATOR_TRIM.
+#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_W 2
+#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_M 0x06000000
+#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_S 25
+
+// Field: [24:21] XOSCLF_CMIRRWR_RATIO
+//
+// Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_CMIRRWR_RATIO.
+#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_W 4
+#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_M 0x01E00000
+#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_S 21
+
+// Field: [20:19] XOSC_HF_FAST_START
+//
+// Trim value for DDI_0_OSC:CTL1.XOSC_HF_FAST_START.
+#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_W 2
+#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_M 0x00180000
+#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_S 19
+
+// Field: [18] XOSC_OPTION
+//
+// 0: XOSC_HF unavailable (may not be bonded out)
+// 1: XOSC_HF available (default)
+#define FCFG1_OSC_CONF_XOSC_OPTION 0x00040000
+#define FCFG1_OSC_CONF_XOSC_OPTION_BITN 18
+#define FCFG1_OSC_CONF_XOSC_OPTION_M 0x00040000
+#define FCFG1_OSC_CONF_XOSC_OPTION_S 18
+
+// Field: [17] HPOSC_OPTION
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_OSC_CONF_HPOSC_OPTION 0x00020000
+#define FCFG1_OSC_CONF_HPOSC_OPTION_BITN 17
+#define FCFG1_OSC_CONF_HPOSC_OPTION_M 0x00020000
+#define FCFG1_OSC_CONF_HPOSC_OPTION_S 17
+
+// Field: [16] HPOSC_BIAS_HOLD_MODE_EN
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN 0x00010000
+#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_BITN 16
+#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_M 0x00010000
+#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_S 16
+
+// Field: [15:12] HPOSC_CURRMIRR_RATIO
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_W 4
+#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_M 0x0000F000
+#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_S 12
+
+// Field: [11:8] HPOSC_BIAS_RES_SET
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_W 4
+#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_M 0x00000F00
+#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_S 8
+
+// Field: [7] HPOSC_FILTER_EN
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_OSC_CONF_HPOSC_FILTER_EN 0x00000080
+#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_BITN 7
+#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_M 0x00000080
+#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_S 7
+
+// Field: [6:5] HPOSC_BIAS_RECHARGE_DELAY
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_W 2
+#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_M 0x00000060
+#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_S 5
+
+// Field: [2:1] HPOSC_SERIES_CAP
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_W 2
+#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_M 0x00000006
+#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_S 1
+
+// Field: [0] HPOSC_DIV3_BYPASS
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS 0x00000001
+#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_BITN 0
+#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_M 0x00000001
+#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_FREQ_OFFSET
+//
+//*****************************************************************************
+// Field: [31:16] HPOSC_COMP_P0
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_W 16
+#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_M 0xFFFF0000
+#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_S 16
+
+// Field: [15:8] HPOSC_COMP_P1
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_W 8
+#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_M 0x0000FF00
+#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_S 8
+
+// Field: [7:0] HPOSC_COMP_P2
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_W 8
+#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_M 0x000000FF
+#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_MISC_OTP_DATA_1
+//
+//*****************************************************************************
+// Field: [28:27] PEAK_DET_ITRIM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_W 2
+#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_M 0x18000000
+#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_S 27
+
+// Field: [26:24] HP_BUF_ITRIM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_W 3
+#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_M 0x07000000
+#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_S 24
+
+// Field: [23:22] LP_BUF_ITRIM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_W 2
+#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_M 0x00C00000
+#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_S 22
+
+// Field: [21:20] DBLR_LOOP_FILTER_RESET_VOLTAGE
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_W 2
+#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_M 0x00300000
+#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_S 20
+
+// Field: [19:10] HPM_IBIAS_WAIT_CNT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_W 10
+#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_M 0x000FFC00
+#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_S 10
+
+// Field: [9:4] LPM_IBIAS_WAIT_CNT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_W 6
+#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_M 0x000003F0
+#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_S 4
+
+// Field: [3:0] IDAC_STEP
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_W 4
+#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_M 0x0000000F
+#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_SHDW_DIE_ID_0
+//
+//*****************************************************************************
+// Field: [31:0] ID_31_0
+//
+// Shadow of DIE_ID_0 register in eFuse row number 5
+#define FCFG1_SHDW_DIE_ID_0_ID_31_0_W 32
+#define FCFG1_SHDW_DIE_ID_0_ID_31_0_M 0xFFFFFFFF
+#define FCFG1_SHDW_DIE_ID_0_ID_31_0_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_SHDW_DIE_ID_1
+//
+//*****************************************************************************
+// Field: [31:0] ID_63_32
+//
+// Shadow of DIE_ID_1 register in eFuse row number 6
+#define FCFG1_SHDW_DIE_ID_1_ID_63_32_W 32
+#define FCFG1_SHDW_DIE_ID_1_ID_63_32_M 0xFFFFFFFF
+#define FCFG1_SHDW_DIE_ID_1_ID_63_32_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_SHDW_DIE_ID_2
+//
+//*****************************************************************************
+// Field: [31:0] ID_95_64
+//
+// Shadow of DIE_ID_2 register in eFuse row number 7
+#define FCFG1_SHDW_DIE_ID_2_ID_95_64_W 32
+#define FCFG1_SHDW_DIE_ID_2_ID_95_64_M 0xFFFFFFFF
+#define FCFG1_SHDW_DIE_ID_2_ID_95_64_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_SHDW_DIE_ID_3
+//
+//*****************************************************************************
+// Field: [31:0] ID_127_96
+//
+// Shadow of DIE_ID_3 register in eFuse row number 8
+#define FCFG1_SHDW_DIE_ID_3_ID_127_96_W 32
+#define FCFG1_SHDW_DIE_ID_3_ID_127_96_M 0xFFFFFFFF
+#define FCFG1_SHDW_DIE_ID_3_ID_127_96_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_SHDW_OSC_BIAS_LDO_TRIM
+//
+//*****************************************************************************
+// Field: [26:23] TRIMMAG
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_W 4
+#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_M 0x07800000
+#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_S 23
+
+// Field: [22:18] TRIMIREF
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_W 5
+#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_M 0x007C0000
+#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_S 18
+
+// Field: [17:16] ITRIM_DIG_LDO
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_W 2
+#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_M 0x00030000
+#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_S 16
+
+// Field: [15:12] VTRIM_DIG
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_W 4
+#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_M 0x0000F000
+#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_S 12
+
+// Field: [11:8] VTRIM_COARSE
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_W 4
+#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_M 0x00000F00
+#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_S 8
+
+// Field: [7:0] RCOSCHF_CTRIM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_W 8
+#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_M 0x000000FF
+#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_SHDW_ANA_TRIM
+//
+//*****************************************************************************
+// Field: [30] ALT_VDDR_TRIM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM 0x40000000
+#define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM_BITN 30
+#define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM_M 0x40000000
+#define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM_S 30
+
+// Field: [29] DET_LOGIC_DIS
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS 0x20000000
+#define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS_BITN 29
+#define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS_M 0x20000000
+#define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS_S 29
+
+// Field: [28:27] BOD_BANDGAP_TRIM_CNF_EXT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_EXT_W 2
+#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_EXT_M 0x18000000
+#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_EXT_S 27
+
+// Field: [26:25] BOD_BANDGAP_TRIM_CNF
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_W 2
+#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_M 0x06000000
+#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_S 25
+
+// Field: [24] VDDR_ENABLE_PG1
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1 0x01000000
+#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_BITN 24
+#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_M 0x01000000
+#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_S 24
+
+// Field: [23] VDDR_OK_HYS
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS 0x00800000
+#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_BITN 23
+#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_M 0x00800000
+#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_S 23
+
+// Field: [22:21] IPTAT_TRIM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_W 2
+#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_M 0x00600000
+#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_S 21
+
+// Field: [20:16] VDDR_TRIM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_W 5
+#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_M 0x001F0000
+#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_S 16
+
+// Field: [15:11] TRIMBOD_INTMODE
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_W 5
+#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_M 0x0000F800
+#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_S 11
+
+// Field: [10:6] TRIMBOD_EXTMODE
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_W 5
+#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_M 0x000007C0
+#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_S 6
+
+// Field: [5:0] TRIMTEMP
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_W 6
+#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_M 0x0000003F
+#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_DAC_BIAS_CNF
+//
+//*****************************************************************************
+// Field: [17:12] LPM_TRIM_IOUT
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_W 6
+#define FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_M 0x0003F000
+#define FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_S 12
+
+// Field: [11:9] LPM_BIAS_WIDTH_TRIM
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_W 3
+#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_M 0x00000E00
+#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_S 9
+
+// Field: [8] LPM_BIAS_BACKUP_EN
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN 0x00000100
+#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN_BITN 8
+#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN_M 0x00000100
+#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN_S 8
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_TFW_PROBE
+//
+//*****************************************************************************
+// Field: [31:0] REV
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_TFW_PROBE_REV_W 32
+#define FCFG1_TFW_PROBE_REV_M 0xFFFFFFFF
+#define FCFG1_TFW_PROBE_REV_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_TFW_FT
+//
+//*****************************************************************************
+// Field: [31:0] REV
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_TFW_FT_REV_W 32
+#define FCFG1_TFW_FT_REV_M 0xFFFFFFFF
+#define FCFG1_TFW_FT_REV_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_DAC_CAL0
+//
+//*****************************************************************************
+// Field: [31:16] SOC_DAC_VOUT_CAL_DECOUPLE_C2
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C2_W 16
+#define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C2_M 0xFFFF0000
+#define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C2_S 16
+
+// Field: [15:0] SOC_DAC_VOUT_CAL_DECOUPLE_C1
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C1_W 16
+#define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C1_M 0x0000FFFF
+#define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C1_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_DAC_CAL1
+//
+//*****************************************************************************
+// Field: [31:16] SOC_DAC_VOUT_CAL_PRECH_C2
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C2_W 16
+#define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C2_M 0xFFFF0000
+#define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C2_S 16
+
+// Field: [15:0] SOC_DAC_VOUT_CAL_PRECH_C1
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C1_W 16
+#define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C1_M 0x0000FFFF
+#define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C1_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_DAC_CAL2
+//
+//*****************************************************************************
+// Field: [31:16] SOC_DAC_VOUT_CAL_ADCREF_C2
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C2_W 16
+#define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C2_M 0xFFFF0000
+#define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C2_S 16
+
+// Field: [15:0] SOC_DAC_VOUT_CAL_ADCREF_C1
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C1_W 16
+#define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C1_M 0x0000FFFF
+#define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C1_S 0
+
+//*****************************************************************************
+//
+// Register: FCFG1_O_DAC_CAL3
+//
+//*****************************************************************************
+// Field: [31:16] SOC_DAC_VOUT_CAL_VDDS_C2
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C2_W 16
+#define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C2_M 0xFFFF0000
+#define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C2_S 16
+
+// Field: [15:0] SOC_DAC_VOUT_CAL_VDDS_C1
+//
+// Internal. Only to be used through TI provided API.
+#define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C1_W 16
+#define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C1_M 0x0000FFFF
+#define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C1_S 0
+
+
+#endif // __FCFG1__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_flash.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_flash.h
new file mode 100644
index 0000000..d7e03e7
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_flash.h
@@ -0,0 +1,3498 @@
+/******************************************************************************
+* Filename: hw_flash_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_FLASH_H__
+#define __HW_FLASH_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// FLASH component
+//
+//*****************************************************************************
+// FMC and Efuse Status
+#define FLASH_O_STAT 0x0000001C
+
+// Internal
+#define FLASH_O_CFG 0x00000024
+
+// Internal
+#define FLASH_O_SYSCODE_START 0x00000028
+
+// Internal
+#define FLASH_O_FLASH_SIZE 0x0000002C
+
+// Internal
+#define FLASH_O_FWLOCK 0x0000003C
+
+// Internal
+#define FLASH_O_FWFLAG 0x00000040
+
+// Internal
+#define FLASH_O_EFUSE 0x00001000
+
+// Internal
+#define FLASH_O_EFUSEADDR 0x00001004
+
+// Internal
+#define FLASH_O_DATAUPPER 0x00001008
+
+// Internal
+#define FLASH_O_DATALOWER 0x0000100C
+
+// Internal
+#define FLASH_O_EFUSECFG 0x00001010
+
+// Internal
+#define FLASH_O_EFUSESTAT 0x00001014
+
+// Internal
+#define FLASH_O_ACC 0x00001018
+
+// Internal
+#define FLASH_O_BOUNDARY 0x0000101C
+
+// Internal
+#define FLASH_O_EFUSEFLAG 0x00001020
+
+// Internal
+#define FLASH_O_EFUSEKEY 0x00001024
+
+// Internal
+#define FLASH_O_EFUSERELEASE 0x00001028
+
+// Internal
+#define FLASH_O_EFUSEPINS 0x0000102C
+
+// Internal
+#define FLASH_O_EFUSECRA 0x00001030
+
+// Internal
+#define FLASH_O_EFUSEREAD 0x00001034
+
+// Internal
+#define FLASH_O_EFUSEPROGRAM 0x00001038
+
+// Internal
+#define FLASH_O_EFUSEERROR 0x0000103C
+
+// Internal
+#define FLASH_O_SINGLEBIT 0x00001040
+
+// Internal
+#define FLASH_O_TWOBIT 0x00001044
+
+// Internal
+#define FLASH_O_SELFTESTCYC 0x00001048
+
+// Internal
+#define FLASH_O_SELFTESTSIGN 0x0000104C
+
+// Internal
+#define FLASH_O_FRDCTL 0x00002000
+
+// Internal
+#define FLASH_O_FSPRD 0x00002004
+
+// Internal
+#define FLASH_O_FEDACCTL1 0x00002008
+
+// Internal
+#define FLASH_O_FEDACSTAT 0x0000201C
+
+// Internal
+#define FLASH_O_FBPROT 0x00002030
+
+// Internal
+#define FLASH_O_FBSE 0x00002034
+
+// Internal
+#define FLASH_O_FBBUSY 0x00002038
+
+// Internal
+#define FLASH_O_FBAC 0x0000203C
+
+// Internal
+#define FLASH_O_FBFALLBACK 0x00002040
+
+// Internal
+#define FLASH_O_FBPRDY 0x00002044
+
+// Internal
+#define FLASH_O_FPAC1 0x00002048
+
+// Internal
+#define FLASH_O_FPAC2 0x0000204C
+
+// Internal
+#define FLASH_O_FMAC 0x00002050
+
+// Internal
+#define FLASH_O_FMSTAT 0x00002054
+
+// Internal
+#define FLASH_O_FLOCK 0x00002064
+
+// Internal
+#define FLASH_O_FVREADCT 0x00002080
+
+// Internal
+#define FLASH_O_FVHVCT1 0x00002084
+
+// Internal
+#define FLASH_O_FVHVCT2 0x00002088
+
+// Internal
+#define FLASH_O_FVHVCT3 0x0000208C
+
+// Internal
+#define FLASH_O_FVNVCT 0x00002090
+
+// Internal
+#define FLASH_O_FVSLP 0x00002094
+
+// Internal
+#define FLASH_O_FVWLCT 0x00002098
+
+// Internal
+#define FLASH_O_FEFUSECTL 0x0000209C
+
+// Internal
+#define FLASH_O_FEFUSESTAT 0x000020A0
+
+// Internal
+#define FLASH_O_FEFUSEDATA 0x000020A4
+
+// Internal
+#define FLASH_O_FSEQPMP 0x000020A8
+
+// Internal
+#define FLASH_O_FBSTROBES 0x00002100
+
+// Internal
+#define FLASH_O_FPSTROBES 0x00002104
+
+// Internal
+#define FLASH_O_FBMODE 0x00002108
+
+// Internal
+#define FLASH_O_FTCR 0x0000210C
+
+// Internal
+#define FLASH_O_FADDR 0x00002110
+
+// Internal
+#define FLASH_O_FTCTL 0x0000211C
+
+// Internal
+#define FLASH_O_FWPWRITE0 0x00002120
+
+// Internal
+#define FLASH_O_FWPWRITE1 0x00002124
+
+// Internal
+#define FLASH_O_FWPWRITE2 0x00002128
+
+// Internal
+#define FLASH_O_FWPWRITE3 0x0000212C
+
+// Internal
+#define FLASH_O_FWPWRITE4 0x00002130
+
+// Internal
+#define FLASH_O_FWPWRITE5 0x00002134
+
+// Internal
+#define FLASH_O_FWPWRITE6 0x00002138
+
+// Internal
+#define FLASH_O_FWPWRITE7 0x0000213C
+
+// Internal
+#define FLASH_O_FWPWRITE_ECC 0x00002140
+
+// Internal
+#define FLASH_O_FSWSTAT 0x00002144
+
+// Internal
+#define FLASH_O_FSM_GLBCTL 0x00002200
+
+// Internal
+#define FLASH_O_FSM_STATE 0x00002204
+
+// Internal
+#define FLASH_O_FSM_STAT 0x00002208
+
+// Internal
+#define FLASH_O_FSM_CMD 0x0000220C
+
+// Internal
+#define FLASH_O_FSM_PE_OSU 0x00002210
+
+// Internal
+#define FLASH_O_FSM_VSTAT 0x00002214
+
+// Internal
+#define FLASH_O_FSM_PE_VSU 0x00002218
+
+// Internal
+#define FLASH_O_FSM_CMP_VSU 0x0000221C
+
+// Internal
+#define FLASH_O_FSM_EX_VAL 0x00002220
+
+// Internal
+#define FLASH_O_FSM_RD_H 0x00002224
+
+// Internal
+#define FLASH_O_FSM_P_OH 0x00002228
+
+// Internal
+#define FLASH_O_FSM_ERA_OH 0x0000222C
+
+// Internal
+#define FLASH_O_FSM_SAV_PPUL 0x00002230
+
+// Internal
+#define FLASH_O_FSM_PE_VH 0x00002234
+
+// Internal
+#define FLASH_O_FSM_PRG_PW 0x00002240
+
+// Internal
+#define FLASH_O_FSM_ERA_PW 0x00002244
+
+// Internal
+#define FLASH_O_FSM_SAV_ERA_PUL 0x00002254
+
+// Internal
+#define FLASH_O_FSM_TIMER 0x00002258
+
+// Internal
+#define FLASH_O_FSM_MODE 0x0000225C
+
+// Internal
+#define FLASH_O_FSM_PGM 0x00002260
+
+// Internal
+#define FLASH_O_FSM_ERA 0x00002264
+
+// Internal
+#define FLASH_O_FSM_PRG_PUL 0x00002268
+
+// Internal
+#define FLASH_O_FSM_ERA_PUL 0x0000226C
+
+// Internal
+#define FLASH_O_FSM_STEP_SIZE 0x00002270
+
+// Internal
+#define FLASH_O_FSM_PUL_CNTR 0x00002274
+
+// Internal
+#define FLASH_O_FSM_EC_STEP_HEIGHT 0x00002278
+
+// Internal
+#define FLASH_O_FSM_ST_MACHINE 0x0000227C
+
+// Internal
+#define FLASH_O_FSM_FLES 0x00002280
+
+// Internal
+#define FLASH_O_FSM_WR_ENA 0x00002288
+
+// Internal
+#define FLASH_O_FSM_ACC_PP 0x0000228C
+
+// Internal
+#define FLASH_O_FSM_ACC_EP 0x00002290
+
+// Internal
+#define FLASH_O_FSM_ADDR 0x000022A0
+
+// Internal
+#define FLASH_O_FSM_SECTOR 0x000022A4
+
+// Internal
+#define FLASH_O_FMC_REV_ID 0x000022A8
+
+// Internal
+#define FLASH_O_FSM_ERR_ADDR 0x000022AC
+
+// Internal
+#define FLASH_O_FSM_PGM_MAXPUL 0x000022B0
+
+// Internal
+#define FLASH_O_FSM_EXECUTE 0x000022B4
+
+// Internal
+#define FLASH_O_FSM_SECTOR1 0x000022C0
+
+// Internal
+#define FLASH_O_FSM_SECTOR2 0x000022C4
+
+// Internal
+#define FLASH_O_FSM_BSLE0 0x000022E0
+
+// Internal
+#define FLASH_O_FSM_BSLE1 0x000022E4
+
+// Internal
+#define FLASH_O_FSM_BSLP0 0x000022F0
+
+// Internal
+#define FLASH_O_FSM_BSLP1 0x000022F4
+
+// FMC FSM Enable 128-bit Wide Programming
+#define FLASH_O_FSM_PGM128 0x000022F8
+
+// Internal
+#define FLASH_O_FCFG_BANK 0x00002400
+
+// Internal
+#define FLASH_O_FCFG_WRAPPER 0x00002404
+
+// Internal
+#define FLASH_O_FCFG_BNK_TYPE 0x00002408
+
+// Internal
+#define FLASH_O_FCFG_B0_START 0x00002410
+
+// Internal
+#define FLASH_O_FCFG_B1_START 0x00002414
+
+// Internal
+#define FLASH_O_FCFG_B2_START 0x00002418
+
+// Internal
+#define FLASH_O_FCFG_B3_START 0x0000241C
+
+// Internal
+#define FLASH_O_FCFG_B4_START 0x00002420
+
+// Internal
+#define FLASH_O_FCFG_B5_START 0x00002424
+
+// Internal
+#define FLASH_O_FCFG_B6_START 0x00002428
+
+// Internal
+#define FLASH_O_FCFG_B7_START 0x0000242C
+
+// Internal
+#define FLASH_O_FCFG_B0_SSIZE0 0x00002430
+
+//*****************************************************************************
+//
+// Register: FLASH_O_STAT
+//
+//*****************************************************************************
+// Field: [15] EFUSE_BLANK
+//
+// Efuse scanning detected if fuse ROM is blank:
+// 0 : Not blank
+// 1 : Blank
+#define FLASH_STAT_EFUSE_BLANK 0x00008000
+#define FLASH_STAT_EFUSE_BLANK_BITN 15
+#define FLASH_STAT_EFUSE_BLANK_M 0x00008000
+#define FLASH_STAT_EFUSE_BLANK_S 15
+
+// Field: [14] EFUSE_TIMEOUT
+//
+// Efuse scanning resulted in timeout error.
+// 0 : No Timeout error
+// 1 : Timeout Error
+#define FLASH_STAT_EFUSE_TIMEOUT 0x00004000
+#define FLASH_STAT_EFUSE_TIMEOUT_BITN 14
+#define FLASH_STAT_EFUSE_TIMEOUT_M 0x00004000
+#define FLASH_STAT_EFUSE_TIMEOUT_S 14
+
+// Field: [13] SPRS_BYTE_NOT_OK
+//
+// Efuse scanning resulted in scan chain Sparse byte error.
+// 0 : No Sparse error
+// 1 : Sparse Error
+#define FLASH_STAT_SPRS_BYTE_NOT_OK 0x00002000
+#define FLASH_STAT_SPRS_BYTE_NOT_OK_BITN 13
+#define FLASH_STAT_SPRS_BYTE_NOT_OK_M 0x00002000
+#define FLASH_STAT_SPRS_BYTE_NOT_OK_S 13
+
+// Field: [12:8] EFUSE_ERRCODE
+//
+// Same as EFUSEERROR.CODE
+#define FLASH_STAT_EFUSE_ERRCODE_W 5
+#define FLASH_STAT_EFUSE_ERRCODE_M 0x00001F00
+#define FLASH_STAT_EFUSE_ERRCODE_S 8
+
+// Field: [2] SAMHOLD_DIS
+//
+// Status indicator of flash sample and hold sequencing logic. This bit will go
+// to 1 some delay after CFG.DIS_IDLE is set to 1.
+// 0: Not disabled
+// 1: Sample and hold disabled and stable
+#define FLASH_STAT_SAMHOLD_DIS 0x00000004
+#define FLASH_STAT_SAMHOLD_DIS_BITN 2
+#define FLASH_STAT_SAMHOLD_DIS_M 0x00000004
+#define FLASH_STAT_SAMHOLD_DIS_S 2
+
+// Field: [1] BUSY
+//
+// Fast version of the FMC FMSTAT.BUSY bit.
+// This flag is valid immediately after the operation setting it (FMSTAT.BUSY
+// is delayed some cycles)
+// 0 : Not busy
+// 1 : Busy
+#define FLASH_STAT_BUSY 0x00000002
+#define FLASH_STAT_BUSY_BITN 1
+#define FLASH_STAT_BUSY_M 0x00000002
+#define FLASH_STAT_BUSY_S 1
+
+// Field: [0] POWER_MODE
+//
+// Power state of the flash sub-system.
+// 0 : Active
+// 1 : Low power
+#define FLASH_STAT_POWER_MODE 0x00000001
+#define FLASH_STAT_POWER_MODE_BITN 0
+#define FLASH_STAT_POWER_MODE_M 0x00000001
+#define FLASH_STAT_POWER_MODE_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_CFG
+//
+//*****************************************************************************
+// Field: [8] STANDBY_MODE_SEL
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_CFG_STANDBY_MODE_SEL 0x00000100
+#define FLASH_CFG_STANDBY_MODE_SEL_BITN 8
+#define FLASH_CFG_STANDBY_MODE_SEL_M 0x00000100
+#define FLASH_CFG_STANDBY_MODE_SEL_S 8
+
+// Field: [7:6] STANDBY_PW_SEL
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_CFG_STANDBY_PW_SEL_W 2
+#define FLASH_CFG_STANDBY_PW_SEL_M 0x000000C0
+#define FLASH_CFG_STANDBY_PW_SEL_S 6
+
+// Field: [5] DIS_EFUSECLK
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_CFG_DIS_EFUSECLK 0x00000020
+#define FLASH_CFG_DIS_EFUSECLK_BITN 5
+#define FLASH_CFG_DIS_EFUSECLK_M 0x00000020
+#define FLASH_CFG_DIS_EFUSECLK_S 5
+
+// Field: [4] DIS_READACCESS
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_CFG_DIS_READACCESS 0x00000010
+#define FLASH_CFG_DIS_READACCESS_BITN 4
+#define FLASH_CFG_DIS_READACCESS_M 0x00000010
+#define FLASH_CFG_DIS_READACCESS_S 4
+
+// Field: [3] ENABLE_SWINTF
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_CFG_ENABLE_SWINTF 0x00000008
+#define FLASH_CFG_ENABLE_SWINTF_BITN 3
+#define FLASH_CFG_ENABLE_SWINTF_M 0x00000008
+#define FLASH_CFG_ENABLE_SWINTF_S 3
+
+// Field: [1] DIS_STANDBY
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_CFG_DIS_STANDBY 0x00000002
+#define FLASH_CFG_DIS_STANDBY_BITN 1
+#define FLASH_CFG_DIS_STANDBY_M 0x00000002
+#define FLASH_CFG_DIS_STANDBY_S 1
+
+// Field: [0] DIS_IDLE
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_CFG_DIS_IDLE 0x00000001
+#define FLASH_CFG_DIS_IDLE_BITN 0
+#define FLASH_CFG_DIS_IDLE_M 0x00000001
+#define FLASH_CFG_DIS_IDLE_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_SYSCODE_START
+//
+//*****************************************************************************
+// Field: [5:0] SYSCODE_START
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_SYSCODE_START_SYSCODE_START_W 6
+#define FLASH_SYSCODE_START_SYSCODE_START_M 0x0000003F
+#define FLASH_SYSCODE_START_SYSCODE_START_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FLASH_SIZE
+//
+//*****************************************************************************
+// Field: [7:0] SECTORS
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FLASH_SIZE_SECTORS_W 8
+#define FLASH_FLASH_SIZE_SECTORS_M 0x000000FF
+#define FLASH_FLASH_SIZE_SECTORS_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FWLOCK
+//
+//*****************************************************************************
+// Field: [2:0] FWLOCK
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FWLOCK_FWLOCK_W 3
+#define FLASH_FWLOCK_FWLOCK_M 0x00000007
+#define FLASH_FWLOCK_FWLOCK_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FWFLAG
+//
+//*****************************************************************************
+// Field: [2:0] FWFLAG
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FWFLAG_FWFLAG_W 3
+#define FLASH_FWFLAG_FWFLAG_M 0x00000007
+#define FLASH_FWFLAG_FWFLAG_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_EFUSE
+//
+//*****************************************************************************
+// Field: [28:24] INSTRUCTION
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSE_INSTRUCTION_W 5
+#define FLASH_EFUSE_INSTRUCTION_M 0x1F000000
+#define FLASH_EFUSE_INSTRUCTION_S 24
+
+// Field: [15:0] DUMPWORD
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSE_DUMPWORD_W 16
+#define FLASH_EFUSE_DUMPWORD_M 0x0000FFFF
+#define FLASH_EFUSE_DUMPWORD_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_EFUSEADDR
+//
+//*****************************************************************************
+// Field: [15:11] BLOCK
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSEADDR_BLOCK_W 5
+#define FLASH_EFUSEADDR_BLOCK_M 0x0000F800
+#define FLASH_EFUSEADDR_BLOCK_S 11
+
+// Field: [10:0] ROW
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSEADDR_ROW_W 11
+#define FLASH_EFUSEADDR_ROW_M 0x000007FF
+#define FLASH_EFUSEADDR_ROW_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_DATAUPPER
+//
+//*****************************************************************************
+// Field: [7:3] SPARE
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_DATAUPPER_SPARE_W 5
+#define FLASH_DATAUPPER_SPARE_M 0x000000F8
+#define FLASH_DATAUPPER_SPARE_S 3
+
+// Field: [2] P
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_DATAUPPER_P 0x00000004
+#define FLASH_DATAUPPER_P_BITN 2
+#define FLASH_DATAUPPER_P_M 0x00000004
+#define FLASH_DATAUPPER_P_S 2
+
+// Field: [1] R
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_DATAUPPER_R 0x00000002
+#define FLASH_DATAUPPER_R_BITN 1
+#define FLASH_DATAUPPER_R_M 0x00000002
+#define FLASH_DATAUPPER_R_S 1
+
+// Field: [0] EEN
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_DATAUPPER_EEN 0x00000001
+#define FLASH_DATAUPPER_EEN_BITN 0
+#define FLASH_DATAUPPER_EEN_M 0x00000001
+#define FLASH_DATAUPPER_EEN_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_DATALOWER
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_DATALOWER_DATA_W 32
+#define FLASH_DATALOWER_DATA_M 0xFFFFFFFF
+#define FLASH_DATALOWER_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_EFUSECFG
+//
+//*****************************************************************************
+// Field: [8] IDLEGATING
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSECFG_IDLEGATING 0x00000100
+#define FLASH_EFUSECFG_IDLEGATING_BITN 8
+#define FLASH_EFUSECFG_IDLEGATING_M 0x00000100
+#define FLASH_EFUSECFG_IDLEGATING_S 8
+
+// Field: [4:3] SLAVEPOWER
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSECFG_SLAVEPOWER_W 2
+#define FLASH_EFUSECFG_SLAVEPOWER_M 0x00000018
+#define FLASH_EFUSECFG_SLAVEPOWER_S 3
+
+// Field: [0] GATING
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSECFG_GATING 0x00000001
+#define FLASH_EFUSECFG_GATING_BITN 0
+#define FLASH_EFUSECFG_GATING_M 0x00000001
+#define FLASH_EFUSECFG_GATING_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_EFUSESTAT
+//
+//*****************************************************************************
+// Field: [0] RESETDONE
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSESTAT_RESETDONE 0x00000001
+#define FLASH_EFUSESTAT_RESETDONE_BITN 0
+#define FLASH_EFUSESTAT_RESETDONE_M 0x00000001
+#define FLASH_EFUSESTAT_RESETDONE_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_ACC
+//
+//*****************************************************************************
+// Field: [23:0] ACCUMULATOR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_ACC_ACCUMULATOR_W 24
+#define FLASH_ACC_ACCUMULATOR_M 0x00FFFFFF
+#define FLASH_ACC_ACCUMULATOR_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_BOUNDARY
+//
+//*****************************************************************************
+// Field: [23] DISROW0
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_BOUNDARY_DISROW0 0x00800000
+#define FLASH_BOUNDARY_DISROW0_BITN 23
+#define FLASH_BOUNDARY_DISROW0_M 0x00800000
+#define FLASH_BOUNDARY_DISROW0_S 23
+
+// Field: [22] SPARE
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_BOUNDARY_SPARE 0x00400000
+#define FLASH_BOUNDARY_SPARE_BITN 22
+#define FLASH_BOUNDARY_SPARE_M 0x00400000
+#define FLASH_BOUNDARY_SPARE_S 22
+
+// Field: [21] EFC_SELF_TEST_ERROR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR 0x00200000
+#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_BITN 21
+#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_M 0x00200000
+#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_S 21
+
+// Field: [20] EFC_INSTRUCTION_INFO
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO 0x00100000
+#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_BITN 20
+#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_M 0x00100000
+#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_S 20
+
+// Field: [19] EFC_INSTRUCTION_ERROR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR 0x00080000
+#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_BITN 19
+#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_M 0x00080000
+#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_S 19
+
+// Field: [18] EFC_AUTOLOAD_ERROR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR 0x00040000
+#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_BITN 18
+#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_M 0x00040000
+#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_S 18
+
+// Field: [17:14] OUTPUTENABLE
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_BOUNDARY_OUTPUTENABLE_W 4
+#define FLASH_BOUNDARY_OUTPUTENABLE_M 0x0003C000
+#define FLASH_BOUNDARY_OUTPUTENABLE_S 14
+
+// Field: [13] SYS_ECC_SELF_TEST_EN
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN 0x00002000
+#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_BITN 13
+#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_M 0x00002000
+#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_S 13
+
+// Field: [12] SYS_ECC_OVERRIDE_EN
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN 0x00001000
+#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_BITN 12
+#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_M 0x00001000
+#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_S 12
+
+// Field: [11] EFC_FDI
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_BOUNDARY_EFC_FDI 0x00000800
+#define FLASH_BOUNDARY_EFC_FDI_BITN 11
+#define FLASH_BOUNDARY_EFC_FDI_M 0x00000800
+#define FLASH_BOUNDARY_EFC_FDI_S 11
+
+// Field: [10] SYS_DIEID_AUTOLOAD_EN
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN 0x00000400
+#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_BITN 10
+#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_M 0x00000400
+#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_S 10
+
+// Field: [9:8] SYS_REPAIR_EN
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_BOUNDARY_SYS_REPAIR_EN_W 2
+#define FLASH_BOUNDARY_SYS_REPAIR_EN_M 0x00000300
+#define FLASH_BOUNDARY_SYS_REPAIR_EN_S 8
+
+// Field: [7:4] SYS_WS_READ_STATES
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_BOUNDARY_SYS_WS_READ_STATES_W 4
+#define FLASH_BOUNDARY_SYS_WS_READ_STATES_M 0x000000F0
+#define FLASH_BOUNDARY_SYS_WS_READ_STATES_S 4
+
+// Field: [3:0] INPUTENABLE
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_BOUNDARY_INPUTENABLE_W 4
+#define FLASH_BOUNDARY_INPUTENABLE_M 0x0000000F
+#define FLASH_BOUNDARY_INPUTENABLE_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_EFUSEFLAG
+//
+//*****************************************************************************
+// Field: [0] KEY
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSEFLAG_KEY 0x00000001
+#define FLASH_EFUSEFLAG_KEY_BITN 0
+#define FLASH_EFUSEFLAG_KEY_M 0x00000001
+#define FLASH_EFUSEFLAG_KEY_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_EFUSEKEY
+//
+//*****************************************************************************
+// Field: [31:0] CODE
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSEKEY_CODE_W 32
+#define FLASH_EFUSEKEY_CODE_M 0xFFFFFFFF
+#define FLASH_EFUSEKEY_CODE_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_EFUSERELEASE
+//
+//*****************************************************************************
+// Field: [31:25] ODPYEAR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSERELEASE_ODPYEAR_W 7
+#define FLASH_EFUSERELEASE_ODPYEAR_M 0xFE000000
+#define FLASH_EFUSERELEASE_ODPYEAR_S 25
+
+// Field: [24:21] ODPMONTH
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSERELEASE_ODPMONTH_W 4
+#define FLASH_EFUSERELEASE_ODPMONTH_M 0x01E00000
+#define FLASH_EFUSERELEASE_ODPMONTH_S 21
+
+// Field: [20:16] ODPDAY
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSERELEASE_ODPDAY_W 5
+#define FLASH_EFUSERELEASE_ODPDAY_M 0x001F0000
+#define FLASH_EFUSERELEASE_ODPDAY_S 16
+
+// Field: [15:9] EFUSEYEAR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSERELEASE_EFUSEYEAR_W 7
+#define FLASH_EFUSERELEASE_EFUSEYEAR_M 0x0000FE00
+#define FLASH_EFUSERELEASE_EFUSEYEAR_S 9
+
+// Field: [8:5] EFUSEMONTH
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSERELEASE_EFUSEMONTH_W 4
+#define FLASH_EFUSERELEASE_EFUSEMONTH_M 0x000001E0
+#define FLASH_EFUSERELEASE_EFUSEMONTH_S 5
+
+// Field: [4:0] EFUSEDAY
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSERELEASE_EFUSEDAY_W 5
+#define FLASH_EFUSERELEASE_EFUSEDAY_M 0x0000001F
+#define FLASH_EFUSERELEASE_EFUSEDAY_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_EFUSEPINS
+//
+//*****************************************************************************
+// Field: [15] EFC_SELF_TEST_DONE
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE 0x00008000
+#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_BITN 15
+#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_M 0x00008000
+#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_S 15
+
+// Field: [14] EFC_SELF_TEST_ERROR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR 0x00004000
+#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_BITN 14
+#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_M 0x00004000
+#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_S 14
+
+// Field: [13] SYS_ECC_SELF_TEST_EN
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN 0x00002000
+#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_BITN 13
+#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_M 0x00002000
+#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_S 13
+
+// Field: [12] EFC_INSTRUCTION_INFO
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO 0x00001000
+#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_BITN 12
+#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_M 0x00001000
+#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_S 12
+
+// Field: [11] EFC_INSTRUCTION_ERROR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR 0x00000800
+#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_BITN 11
+#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_M 0x00000800
+#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_S 11
+
+// Field: [10] EFC_AUTOLOAD_ERROR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR 0x00000400
+#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_BITN 10
+#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_M 0x00000400
+#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_S 10
+
+// Field: [9] SYS_ECC_OVERRIDE_EN
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN 0x00000200
+#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_BITN 9
+#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_M 0x00000200
+#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_S 9
+
+// Field: [8] EFC_READY
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSEPINS_EFC_READY 0x00000100
+#define FLASH_EFUSEPINS_EFC_READY_BITN 8
+#define FLASH_EFUSEPINS_EFC_READY_M 0x00000100
+#define FLASH_EFUSEPINS_EFC_READY_S 8
+
+// Field: [7] EFC_FCLRZ
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSEPINS_EFC_FCLRZ 0x00000080
+#define FLASH_EFUSEPINS_EFC_FCLRZ_BITN 7
+#define FLASH_EFUSEPINS_EFC_FCLRZ_M 0x00000080
+#define FLASH_EFUSEPINS_EFC_FCLRZ_S 7
+
+// Field: [6] SYS_DIEID_AUTOLOAD_EN
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN 0x00000040
+#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_BITN 6
+#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_M 0x00000040
+#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_S 6
+
+// Field: [5:4] SYS_REPAIR_EN
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSEPINS_SYS_REPAIR_EN_W 2
+#define FLASH_EFUSEPINS_SYS_REPAIR_EN_M 0x00000030
+#define FLASH_EFUSEPINS_SYS_REPAIR_EN_S 4
+
+// Field: [3:0] SYS_WS_READ_STATES
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_W 4
+#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_M 0x0000000F
+#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_EFUSECRA
+//
+//*****************************************************************************
+// Field: [5:0] DATA
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSECRA_DATA_W 6
+#define FLASH_EFUSECRA_DATA_M 0x0000003F
+#define FLASH_EFUSECRA_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_EFUSEREAD
+//
+//*****************************************************************************
+// Field: [9:8] DATABIT
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSEREAD_DATABIT_W 2
+#define FLASH_EFUSEREAD_DATABIT_M 0x00000300
+#define FLASH_EFUSEREAD_DATABIT_S 8
+
+// Field: [7:4] READCLOCK
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSEREAD_READCLOCK_W 4
+#define FLASH_EFUSEREAD_READCLOCK_M 0x000000F0
+#define FLASH_EFUSEREAD_READCLOCK_S 4
+
+// Field: [3] DEBUG
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSEREAD_DEBUG 0x00000008
+#define FLASH_EFUSEREAD_DEBUG_BITN 3
+#define FLASH_EFUSEREAD_DEBUG_M 0x00000008
+#define FLASH_EFUSEREAD_DEBUG_S 3
+
+// Field: [2] SPARE
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSEREAD_SPARE 0x00000004
+#define FLASH_EFUSEREAD_SPARE_BITN 2
+#define FLASH_EFUSEREAD_SPARE_M 0x00000004
+#define FLASH_EFUSEREAD_SPARE_S 2
+
+// Field: [1:0] MARGIN
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSEREAD_MARGIN_W 2
+#define FLASH_EFUSEREAD_MARGIN_M 0x00000003
+#define FLASH_EFUSEREAD_MARGIN_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_EFUSEPROGRAM
+//
+//*****************************************************************************
+// Field: [30] COMPAREDISABLE
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSEPROGRAM_COMPAREDISABLE 0x40000000
+#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_BITN 30
+#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_M 0x40000000
+#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_S 30
+
+// Field: [29:14] CLOCKSTALL
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSEPROGRAM_CLOCKSTALL_W 16
+#define FLASH_EFUSEPROGRAM_CLOCKSTALL_M 0x3FFFC000
+#define FLASH_EFUSEPROGRAM_CLOCKSTALL_S 14
+
+// Field: [13] VPPTOVDD
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSEPROGRAM_VPPTOVDD 0x00002000
+#define FLASH_EFUSEPROGRAM_VPPTOVDD_BITN 13
+#define FLASH_EFUSEPROGRAM_VPPTOVDD_M 0x00002000
+#define FLASH_EFUSEPROGRAM_VPPTOVDD_S 13
+
+// Field: [12:9] ITERATIONS
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSEPROGRAM_ITERATIONS_W 4
+#define FLASH_EFUSEPROGRAM_ITERATIONS_M 0x00001E00
+#define FLASH_EFUSEPROGRAM_ITERATIONS_S 9
+
+// Field: [8:0] WRITECLOCK
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSEPROGRAM_WRITECLOCK_W 9
+#define FLASH_EFUSEPROGRAM_WRITECLOCK_M 0x000001FF
+#define FLASH_EFUSEPROGRAM_WRITECLOCK_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_EFUSEERROR
+//
+//*****************************************************************************
+// Field: [5] DONE
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSEERROR_DONE 0x00000020
+#define FLASH_EFUSEERROR_DONE_BITN 5
+#define FLASH_EFUSEERROR_DONE_M 0x00000020
+#define FLASH_EFUSEERROR_DONE_S 5
+
+// Field: [4:0] CODE
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_EFUSEERROR_CODE_W 5
+#define FLASH_EFUSEERROR_CODE_M 0x0000001F
+#define FLASH_EFUSEERROR_CODE_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_SINGLEBIT
+//
+//*****************************************************************************
+// Field: [31:1] FROMN
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_SINGLEBIT_FROMN_W 31
+#define FLASH_SINGLEBIT_FROMN_M 0xFFFFFFFE
+#define FLASH_SINGLEBIT_FROMN_S 1
+
+// Field: [0] FROM0
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_SINGLEBIT_FROM0 0x00000001
+#define FLASH_SINGLEBIT_FROM0_BITN 0
+#define FLASH_SINGLEBIT_FROM0_M 0x00000001
+#define FLASH_SINGLEBIT_FROM0_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_TWOBIT
+//
+//*****************************************************************************
+// Field: [31:1] FROMN
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_TWOBIT_FROMN_W 31
+#define FLASH_TWOBIT_FROMN_M 0xFFFFFFFE
+#define FLASH_TWOBIT_FROMN_S 1
+
+// Field: [0] FROM0
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_TWOBIT_FROM0 0x00000001
+#define FLASH_TWOBIT_FROM0_BITN 0
+#define FLASH_TWOBIT_FROM0_M 0x00000001
+#define FLASH_TWOBIT_FROM0_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_SELFTESTCYC
+//
+//*****************************************************************************
+// Field: [31:0] CYCLES
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_SELFTESTCYC_CYCLES_W 32
+#define FLASH_SELFTESTCYC_CYCLES_M 0xFFFFFFFF
+#define FLASH_SELFTESTCYC_CYCLES_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_SELFTESTSIGN
+//
+//*****************************************************************************
+// Field: [31:0] SIGNATURE
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_SELFTESTSIGN_SIGNATURE_W 32
+#define FLASH_SELFTESTSIGN_SIGNATURE_M 0xFFFFFFFF
+#define FLASH_SELFTESTSIGN_SIGNATURE_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FRDCTL
+//
+//*****************************************************************************
+// Field: [11:8] RWAIT
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FRDCTL_RWAIT_W 4
+#define FLASH_FRDCTL_RWAIT_M 0x00000F00
+#define FLASH_FRDCTL_RWAIT_S 8
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSPRD
+//
+//*****************************************************************************
+// Field: [15:8] RMBSEM
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSPRD_RMBSEM_W 8
+#define FLASH_FSPRD_RMBSEM_M 0x0000FF00
+#define FLASH_FSPRD_RMBSEM_S 8
+
+// Field: [1] RM1
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSPRD_RM1 0x00000002
+#define FLASH_FSPRD_RM1_BITN 1
+#define FLASH_FSPRD_RM1_M 0x00000002
+#define FLASH_FSPRD_RM1_S 1
+
+// Field: [0] RM0
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSPRD_RM0 0x00000001
+#define FLASH_FSPRD_RM0_BITN 0
+#define FLASH_FSPRD_RM0_M 0x00000001
+#define FLASH_FSPRD_RM0_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FEDACCTL1
+//
+//*****************************************************************************
+// Field: [24] SUSP_IGNR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FEDACCTL1_SUSP_IGNR 0x01000000
+#define FLASH_FEDACCTL1_SUSP_IGNR_BITN 24
+#define FLASH_FEDACCTL1_SUSP_IGNR_M 0x01000000
+#define FLASH_FEDACCTL1_SUSP_IGNR_S 24
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FEDACSTAT
+//
+//*****************************************************************************
+// Field: [25] RVF_INT
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FEDACSTAT_RVF_INT 0x02000000
+#define FLASH_FEDACSTAT_RVF_INT_BITN 25
+#define FLASH_FEDACSTAT_RVF_INT_M 0x02000000
+#define FLASH_FEDACSTAT_RVF_INT_S 25
+
+// Field: [24] FSM_DONE
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FEDACSTAT_FSM_DONE 0x01000000
+#define FLASH_FEDACSTAT_FSM_DONE_BITN 24
+#define FLASH_FEDACSTAT_FSM_DONE_M 0x01000000
+#define FLASH_FEDACSTAT_FSM_DONE_S 24
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FBPROT
+//
+//*****************************************************************************
+// Field: [0] PROTL1DIS
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FBPROT_PROTL1DIS 0x00000001
+#define FLASH_FBPROT_PROTL1DIS_BITN 0
+#define FLASH_FBPROT_PROTL1DIS_M 0x00000001
+#define FLASH_FBPROT_PROTL1DIS_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FBSE
+//
+//*****************************************************************************
+// Field: [15:0] BSE
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FBSE_BSE_W 16
+#define FLASH_FBSE_BSE_M 0x0000FFFF
+#define FLASH_FBSE_BSE_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FBBUSY
+//
+//*****************************************************************************
+// Field: [7:0] BUSY
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FBBUSY_BUSY_W 8
+#define FLASH_FBBUSY_BUSY_M 0x000000FF
+#define FLASH_FBBUSY_BUSY_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FBAC
+//
+//*****************************************************************************
+// Field: [16] OTPPROTDIS
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FBAC_OTPPROTDIS 0x00010000
+#define FLASH_FBAC_OTPPROTDIS_BITN 16
+#define FLASH_FBAC_OTPPROTDIS_M 0x00010000
+#define FLASH_FBAC_OTPPROTDIS_S 16
+
+// Field: [15:8] BAGP
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FBAC_BAGP_W 8
+#define FLASH_FBAC_BAGP_M 0x0000FF00
+#define FLASH_FBAC_BAGP_S 8
+
+// Field: [7:0] VREADS
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FBAC_VREADS_W 8
+#define FLASH_FBAC_VREADS_M 0x000000FF
+#define FLASH_FBAC_VREADS_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FBFALLBACK
+//
+//*****************************************************************************
+// Field: [27:24] FSM_PWRSAV
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FBFALLBACK_FSM_PWRSAV_W 4
+#define FLASH_FBFALLBACK_FSM_PWRSAV_M 0x0F000000
+#define FLASH_FBFALLBACK_FSM_PWRSAV_S 24
+
+// Field: [19:16] REG_PWRSAV
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FBFALLBACK_REG_PWRSAV_W 4
+#define FLASH_FBFALLBACK_REG_PWRSAV_M 0x000F0000
+#define FLASH_FBFALLBACK_REG_PWRSAV_S 16
+
+// Field: [15:14] BANKPWR7
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FBFALLBACK_BANKPWR7_W 2
+#define FLASH_FBFALLBACK_BANKPWR7_M 0x0000C000
+#define FLASH_FBFALLBACK_BANKPWR7_S 14
+
+// Field: [13:12] BANKPWR6
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FBFALLBACK_BANKPWR6_W 2
+#define FLASH_FBFALLBACK_BANKPWR6_M 0x00003000
+#define FLASH_FBFALLBACK_BANKPWR6_S 12
+
+// Field: [11:10] BANKPWR5
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FBFALLBACK_BANKPWR5_W 2
+#define FLASH_FBFALLBACK_BANKPWR5_M 0x00000C00
+#define FLASH_FBFALLBACK_BANKPWR5_S 10
+
+// Field: [9:8] BANKPWR4
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FBFALLBACK_BANKPWR4_W 2
+#define FLASH_FBFALLBACK_BANKPWR4_M 0x00000300
+#define FLASH_FBFALLBACK_BANKPWR4_S 8
+
+// Field: [7:6] BANKPWR3
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FBFALLBACK_BANKPWR3_W 2
+#define FLASH_FBFALLBACK_BANKPWR3_M 0x000000C0
+#define FLASH_FBFALLBACK_BANKPWR3_S 6
+
+// Field: [5:4] BANKPWR2
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FBFALLBACK_BANKPWR2_W 2
+#define FLASH_FBFALLBACK_BANKPWR2_M 0x00000030
+#define FLASH_FBFALLBACK_BANKPWR2_S 4
+
+// Field: [3:2] BANKPWR1
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FBFALLBACK_BANKPWR1_W 2
+#define FLASH_FBFALLBACK_BANKPWR1_M 0x0000000C
+#define FLASH_FBFALLBACK_BANKPWR1_S 2
+
+// Field: [1:0] BANKPWR0
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FBFALLBACK_BANKPWR0_W 2
+#define FLASH_FBFALLBACK_BANKPWR0_M 0x00000003
+#define FLASH_FBFALLBACK_BANKPWR0_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FBPRDY
+//
+//*****************************************************************************
+// Field: [16] BANKBUSY
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FBPRDY_BANKBUSY 0x00010000
+#define FLASH_FBPRDY_BANKBUSY_BITN 16
+#define FLASH_FBPRDY_BANKBUSY_M 0x00010000
+#define FLASH_FBPRDY_BANKBUSY_S 16
+
+// Field: [15] PUMPRDY
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FBPRDY_PUMPRDY 0x00008000
+#define FLASH_FBPRDY_PUMPRDY_BITN 15
+#define FLASH_FBPRDY_PUMPRDY_M 0x00008000
+#define FLASH_FBPRDY_PUMPRDY_S 15
+
+// Field: [0] BANKRDY
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FBPRDY_BANKRDY 0x00000001
+#define FLASH_FBPRDY_BANKRDY_BITN 0
+#define FLASH_FBPRDY_BANKRDY_M 0x00000001
+#define FLASH_FBPRDY_BANKRDY_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FPAC1
+//
+//*****************************************************************************
+// Field: [27:16] PSLEEPTDIS
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FPAC1_PSLEEPTDIS_W 12
+#define FLASH_FPAC1_PSLEEPTDIS_M 0x0FFF0000
+#define FLASH_FPAC1_PSLEEPTDIS_S 16
+
+// Field: [15:4] PUMPRESET_PW
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FPAC1_PUMPRESET_PW_W 12
+#define FLASH_FPAC1_PUMPRESET_PW_M 0x0000FFF0
+#define FLASH_FPAC1_PUMPRESET_PW_S 4
+
+// Field: [1:0] PUMPPWR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FPAC1_PUMPPWR_W 2
+#define FLASH_FPAC1_PUMPPWR_M 0x00000003
+#define FLASH_FPAC1_PUMPPWR_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FPAC2
+//
+//*****************************************************************************
+// Field: [15:0] PAGP
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FPAC2_PAGP_W 16
+#define FLASH_FPAC2_PAGP_M 0x0000FFFF
+#define FLASH_FPAC2_PAGP_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FMAC
+//
+//*****************************************************************************
+// Field: [2:0] BANK
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FMAC_BANK_W 3
+#define FLASH_FMAC_BANK_M 0x00000007
+#define FLASH_FMAC_BANK_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FMSTAT
+//
+//*****************************************************************************
+// Field: [17] RVSUSP
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FMSTAT_RVSUSP 0x00020000
+#define FLASH_FMSTAT_RVSUSP_BITN 17
+#define FLASH_FMSTAT_RVSUSP_M 0x00020000
+#define FLASH_FMSTAT_RVSUSP_S 17
+
+// Field: [16] RDVER
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FMSTAT_RDVER 0x00010000
+#define FLASH_FMSTAT_RDVER_BITN 16
+#define FLASH_FMSTAT_RDVER_M 0x00010000
+#define FLASH_FMSTAT_RDVER_S 16
+
+// Field: [15] RVF
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FMSTAT_RVF 0x00008000
+#define FLASH_FMSTAT_RVF_BITN 15
+#define FLASH_FMSTAT_RVF_M 0x00008000
+#define FLASH_FMSTAT_RVF_S 15
+
+// Field: [14] ILA
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FMSTAT_ILA 0x00004000
+#define FLASH_FMSTAT_ILA_BITN 14
+#define FLASH_FMSTAT_ILA_M 0x00004000
+#define FLASH_FMSTAT_ILA_S 14
+
+// Field: [13] DBF
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FMSTAT_DBF 0x00002000
+#define FLASH_FMSTAT_DBF_BITN 13
+#define FLASH_FMSTAT_DBF_M 0x00002000
+#define FLASH_FMSTAT_DBF_S 13
+
+// Field: [12] PGV
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FMSTAT_PGV 0x00001000
+#define FLASH_FMSTAT_PGV_BITN 12
+#define FLASH_FMSTAT_PGV_M 0x00001000
+#define FLASH_FMSTAT_PGV_S 12
+
+// Field: [11] PCV
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FMSTAT_PCV 0x00000800
+#define FLASH_FMSTAT_PCV_BITN 11
+#define FLASH_FMSTAT_PCV_M 0x00000800
+#define FLASH_FMSTAT_PCV_S 11
+
+// Field: [10] EV
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FMSTAT_EV 0x00000400
+#define FLASH_FMSTAT_EV_BITN 10
+#define FLASH_FMSTAT_EV_M 0x00000400
+#define FLASH_FMSTAT_EV_S 10
+
+// Field: [9] CV
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FMSTAT_CV 0x00000200
+#define FLASH_FMSTAT_CV_BITN 9
+#define FLASH_FMSTAT_CV_M 0x00000200
+#define FLASH_FMSTAT_CV_S 9
+
+// Field: [8] BUSY
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FMSTAT_BUSY 0x00000100
+#define FLASH_FMSTAT_BUSY_BITN 8
+#define FLASH_FMSTAT_BUSY_M 0x00000100
+#define FLASH_FMSTAT_BUSY_S 8
+
+// Field: [7] ERS
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FMSTAT_ERS 0x00000080
+#define FLASH_FMSTAT_ERS_BITN 7
+#define FLASH_FMSTAT_ERS_M 0x00000080
+#define FLASH_FMSTAT_ERS_S 7
+
+// Field: [6] PGM
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FMSTAT_PGM 0x00000040
+#define FLASH_FMSTAT_PGM_BITN 6
+#define FLASH_FMSTAT_PGM_M 0x00000040
+#define FLASH_FMSTAT_PGM_S 6
+
+// Field: [5] INVDAT
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FMSTAT_INVDAT 0x00000020
+#define FLASH_FMSTAT_INVDAT_BITN 5
+#define FLASH_FMSTAT_INVDAT_M 0x00000020
+#define FLASH_FMSTAT_INVDAT_S 5
+
+// Field: [4] CSTAT
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FMSTAT_CSTAT 0x00000010
+#define FLASH_FMSTAT_CSTAT_BITN 4
+#define FLASH_FMSTAT_CSTAT_M 0x00000010
+#define FLASH_FMSTAT_CSTAT_S 4
+
+// Field: [3] VOLSTAT
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FMSTAT_VOLSTAT 0x00000008
+#define FLASH_FMSTAT_VOLSTAT_BITN 3
+#define FLASH_FMSTAT_VOLSTAT_M 0x00000008
+#define FLASH_FMSTAT_VOLSTAT_S 3
+
+// Field: [2] ESUSP
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FMSTAT_ESUSP 0x00000004
+#define FLASH_FMSTAT_ESUSP_BITN 2
+#define FLASH_FMSTAT_ESUSP_M 0x00000004
+#define FLASH_FMSTAT_ESUSP_S 2
+
+// Field: [1] PSUSP
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FMSTAT_PSUSP 0x00000002
+#define FLASH_FMSTAT_PSUSP_BITN 1
+#define FLASH_FMSTAT_PSUSP_M 0x00000002
+#define FLASH_FMSTAT_PSUSP_S 1
+
+// Field: [0] SLOCK
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FMSTAT_SLOCK 0x00000001
+#define FLASH_FMSTAT_SLOCK_BITN 0
+#define FLASH_FMSTAT_SLOCK_M 0x00000001
+#define FLASH_FMSTAT_SLOCK_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FLOCK
+//
+//*****************************************************************************
+// Field: [15:0] ENCOM
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FLOCK_ENCOM_W 16
+#define FLASH_FLOCK_ENCOM_M 0x0000FFFF
+#define FLASH_FLOCK_ENCOM_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FVREADCT
+//
+//*****************************************************************************
+// Field: [3:0] VREADCT
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FVREADCT_VREADCT_W 4
+#define FLASH_FVREADCT_VREADCT_M 0x0000000F
+#define FLASH_FVREADCT_VREADCT_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FVHVCT1
+//
+//*****************************************************************************
+// Field: [23:20] TRIM13_E
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FVHVCT1_TRIM13_E_W 4
+#define FLASH_FVHVCT1_TRIM13_E_M 0x00F00000
+#define FLASH_FVHVCT1_TRIM13_E_S 20
+
+// Field: [19:16] VHVCT_E
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FVHVCT1_VHVCT_E_W 4
+#define FLASH_FVHVCT1_VHVCT_E_M 0x000F0000
+#define FLASH_FVHVCT1_VHVCT_E_S 16
+
+// Field: [7:4] TRIM13_PV
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FVHVCT1_TRIM13_PV_W 4
+#define FLASH_FVHVCT1_TRIM13_PV_M 0x000000F0
+#define FLASH_FVHVCT1_TRIM13_PV_S 4
+
+// Field: [3:0] VHVCT_PV
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FVHVCT1_VHVCT_PV_W 4
+#define FLASH_FVHVCT1_VHVCT_PV_M 0x0000000F
+#define FLASH_FVHVCT1_VHVCT_PV_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FVHVCT2
+//
+//*****************************************************************************
+// Field: [23:20] TRIM13_P
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FVHVCT2_TRIM13_P_W 4
+#define FLASH_FVHVCT2_TRIM13_P_M 0x00F00000
+#define FLASH_FVHVCT2_TRIM13_P_S 20
+
+// Field: [19:16] VHVCT_P
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FVHVCT2_VHVCT_P_W 4
+#define FLASH_FVHVCT2_VHVCT_P_M 0x000F0000
+#define FLASH_FVHVCT2_VHVCT_P_S 16
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FVHVCT3
+//
+//*****************************************************************************
+// Field: [19:16] WCT
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FVHVCT3_WCT_W 4
+#define FLASH_FVHVCT3_WCT_M 0x000F0000
+#define FLASH_FVHVCT3_WCT_S 16
+
+// Field: [3:0] VHVCT_READ
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FVHVCT3_VHVCT_READ_W 4
+#define FLASH_FVHVCT3_VHVCT_READ_M 0x0000000F
+#define FLASH_FVHVCT3_VHVCT_READ_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FVNVCT
+//
+//*****************************************************************************
+// Field: [12:8] VCG2P5CT
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FVNVCT_VCG2P5CT_W 5
+#define FLASH_FVNVCT_VCG2P5CT_M 0x00001F00
+#define FLASH_FVNVCT_VCG2P5CT_S 8
+
+// Field: [4:0] VIN_CT
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FVNVCT_VIN_CT_W 5
+#define FLASH_FVNVCT_VIN_CT_M 0x0000001F
+#define FLASH_FVNVCT_VIN_CT_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FVSLP
+//
+//*****************************************************************************
+// Field: [15:12] VSL_P
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FVSLP_VSL_P_W 4
+#define FLASH_FVSLP_VSL_P_M 0x0000F000
+#define FLASH_FVSLP_VSL_P_S 12
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FVWLCT
+//
+//*****************************************************************************
+// Field: [4:0] VWLCT_P
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FVWLCT_VWLCT_P_W 5
+#define FLASH_FVWLCT_VWLCT_P_M 0x0000001F
+#define FLASH_FVWLCT_VWLCT_P_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FEFUSECTL
+//
+//*****************************************************************************
+// Field: [26:24] CHAIN_SEL
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FEFUSECTL_CHAIN_SEL_W 3
+#define FLASH_FEFUSECTL_CHAIN_SEL_M 0x07000000
+#define FLASH_FEFUSECTL_CHAIN_SEL_S 24
+
+// Field: [17] WRITE_EN
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FEFUSECTL_WRITE_EN 0x00020000
+#define FLASH_FEFUSECTL_WRITE_EN_BITN 17
+#define FLASH_FEFUSECTL_WRITE_EN_M 0x00020000
+#define FLASH_FEFUSECTL_WRITE_EN_S 17
+
+// Field: [16] BP_SEL
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FEFUSECTL_BP_SEL 0x00010000
+#define FLASH_FEFUSECTL_BP_SEL_BITN 16
+#define FLASH_FEFUSECTL_BP_SEL_M 0x00010000
+#define FLASH_FEFUSECTL_BP_SEL_S 16
+
+// Field: [8] EF_CLRZ
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FEFUSECTL_EF_CLRZ 0x00000100
+#define FLASH_FEFUSECTL_EF_CLRZ_BITN 8
+#define FLASH_FEFUSECTL_EF_CLRZ_M 0x00000100
+#define FLASH_FEFUSECTL_EF_CLRZ_S 8
+
+// Field: [4] EF_TEST
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FEFUSECTL_EF_TEST 0x00000010
+#define FLASH_FEFUSECTL_EF_TEST_BITN 4
+#define FLASH_FEFUSECTL_EF_TEST_M 0x00000010
+#define FLASH_FEFUSECTL_EF_TEST_S 4
+
+// Field: [3:0] EFUSE_EN
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FEFUSECTL_EFUSE_EN_W 4
+#define FLASH_FEFUSECTL_EFUSE_EN_M 0x0000000F
+#define FLASH_FEFUSECTL_EFUSE_EN_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FEFUSESTAT
+//
+//*****************************************************************************
+// Field: [0] SHIFT_DONE
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FEFUSESTAT_SHIFT_DONE 0x00000001
+#define FLASH_FEFUSESTAT_SHIFT_DONE_BITN 0
+#define FLASH_FEFUSESTAT_SHIFT_DONE_M 0x00000001
+#define FLASH_FEFUSESTAT_SHIFT_DONE_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FEFUSEDATA
+//
+//*****************************************************************************
+// Field: [31:0] FEFUSEDATA
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FEFUSEDATA_FEFUSEDATA_W 32
+#define FLASH_FEFUSEDATA_FEFUSEDATA_M 0xFFFFFFFF
+#define FLASH_FEFUSEDATA_FEFUSEDATA_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSEQPMP
+//
+//*****************************************************************************
+// Field: [27:24] TRIM_3P4
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSEQPMP_TRIM_3P4_W 4
+#define FLASH_FSEQPMP_TRIM_3P4_M 0x0F000000
+#define FLASH_FSEQPMP_TRIM_3P4_S 24
+
+// Field: [21:20] TRIM_1P7
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSEQPMP_TRIM_1P7_W 2
+#define FLASH_FSEQPMP_TRIM_1P7_M 0x00300000
+#define FLASH_FSEQPMP_TRIM_1P7_S 20
+
+// Field: [19:16] TRIM_0P8
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSEQPMP_TRIM_0P8_W 4
+#define FLASH_FSEQPMP_TRIM_0P8_M 0x000F0000
+#define FLASH_FSEQPMP_TRIM_0P8_S 16
+
+// Field: [14:12] VIN_AT_X
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSEQPMP_VIN_AT_X_W 3
+#define FLASH_FSEQPMP_VIN_AT_X_M 0x00007000
+#define FLASH_FSEQPMP_VIN_AT_X_S 12
+
+// Field: [8] VIN_BY_PASS
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSEQPMP_VIN_BY_PASS 0x00000100
+#define FLASH_FSEQPMP_VIN_BY_PASS_BITN 8
+#define FLASH_FSEQPMP_VIN_BY_PASS_M 0x00000100
+#define FLASH_FSEQPMP_VIN_BY_PASS_S 8
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FBSTROBES
+//
+//*****************************************************************************
+// Field: [24] ECBIT
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FBSTROBES_ECBIT 0x01000000
+#define FLASH_FBSTROBES_ECBIT_BITN 24
+#define FLASH_FBSTROBES_ECBIT_M 0x01000000
+#define FLASH_FBSTROBES_ECBIT_S 24
+
+// Field: [18] RWAIT2_FLCLK
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FBSTROBES_RWAIT2_FLCLK 0x00040000
+#define FLASH_FBSTROBES_RWAIT2_FLCLK_BITN 18
+#define FLASH_FBSTROBES_RWAIT2_FLCLK_M 0x00040000
+#define FLASH_FBSTROBES_RWAIT2_FLCLK_S 18
+
+// Field: [17] RWAIT_FLCLK
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FBSTROBES_RWAIT_FLCLK 0x00020000
+#define FLASH_FBSTROBES_RWAIT_FLCLK_BITN 17
+#define FLASH_FBSTROBES_RWAIT_FLCLK_M 0x00020000
+#define FLASH_FBSTROBES_RWAIT_FLCLK_S 17
+
+// Field: [16] FLCLKEN
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FBSTROBES_FLCLKEN 0x00010000
+#define FLASH_FBSTROBES_FLCLKEN_BITN 16
+#define FLASH_FBSTROBES_FLCLKEN_M 0x00010000
+#define FLASH_FBSTROBES_FLCLKEN_S 16
+
+// Field: [8] CTRLENZ
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FBSTROBES_CTRLENZ 0x00000100
+#define FLASH_FBSTROBES_CTRLENZ_BITN 8
+#define FLASH_FBSTROBES_CTRLENZ_M 0x00000100
+#define FLASH_FBSTROBES_CTRLENZ_S 8
+
+// Field: [6] NOCOLRED
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FBSTROBES_NOCOLRED 0x00000040
+#define FLASH_FBSTROBES_NOCOLRED_BITN 6
+#define FLASH_FBSTROBES_NOCOLRED_M 0x00000040
+#define FLASH_FBSTROBES_NOCOLRED_S 6
+
+// Field: [5] PRECOL
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FBSTROBES_PRECOL 0x00000020
+#define FLASH_FBSTROBES_PRECOL_BITN 5
+#define FLASH_FBSTROBES_PRECOL_M 0x00000020
+#define FLASH_FBSTROBES_PRECOL_S 5
+
+// Field: [4] TI_OTP
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FBSTROBES_TI_OTP 0x00000010
+#define FLASH_FBSTROBES_TI_OTP_BITN 4
+#define FLASH_FBSTROBES_TI_OTP_M 0x00000010
+#define FLASH_FBSTROBES_TI_OTP_S 4
+
+// Field: [3] OTP
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FBSTROBES_OTP 0x00000008
+#define FLASH_FBSTROBES_OTP_BITN 3
+#define FLASH_FBSTROBES_OTP_M 0x00000008
+#define FLASH_FBSTROBES_OTP_S 3
+
+// Field: [2] TEZ
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FBSTROBES_TEZ 0x00000004
+#define FLASH_FBSTROBES_TEZ_BITN 2
+#define FLASH_FBSTROBES_TEZ_M 0x00000004
+#define FLASH_FBSTROBES_TEZ_S 2
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FPSTROBES
+//
+//*****************************************************************************
+// Field: [8] EXECUTEZ
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FPSTROBES_EXECUTEZ 0x00000100
+#define FLASH_FPSTROBES_EXECUTEZ_BITN 8
+#define FLASH_FPSTROBES_EXECUTEZ_M 0x00000100
+#define FLASH_FPSTROBES_EXECUTEZ_S 8
+
+// Field: [1] V3PWRDNZ
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FPSTROBES_V3PWRDNZ 0x00000002
+#define FLASH_FPSTROBES_V3PWRDNZ_BITN 1
+#define FLASH_FPSTROBES_V3PWRDNZ_M 0x00000002
+#define FLASH_FPSTROBES_V3PWRDNZ_S 1
+
+// Field: [0] V5PWRDNZ
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FPSTROBES_V5PWRDNZ 0x00000001
+#define FLASH_FPSTROBES_V5PWRDNZ_BITN 0
+#define FLASH_FPSTROBES_V5PWRDNZ_M 0x00000001
+#define FLASH_FPSTROBES_V5PWRDNZ_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FBMODE
+//
+//*****************************************************************************
+// Field: [2:0] MODE
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FBMODE_MODE_W 3
+#define FLASH_FBMODE_MODE_M 0x00000007
+#define FLASH_FBMODE_MODE_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FTCR
+//
+//*****************************************************************************
+// Field: [6:0] TCR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FTCR_TCR_W 7
+#define FLASH_FTCR_TCR_M 0x0000007F
+#define FLASH_FTCR_TCR_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FADDR
+//
+//*****************************************************************************
+// Field: [31:0] FADDR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FADDR_FADDR_W 32
+#define FLASH_FADDR_FADDR_M 0xFFFFFFFF
+#define FLASH_FADDR_FADDR_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FTCTL
+//
+//*****************************************************************************
+// Field: [16] WDATA_BLK_CLR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FTCTL_WDATA_BLK_CLR 0x00010000
+#define FLASH_FTCTL_WDATA_BLK_CLR_BITN 16
+#define FLASH_FTCTL_WDATA_BLK_CLR_M 0x00010000
+#define FLASH_FTCTL_WDATA_BLK_CLR_S 16
+
+// Field: [1] TEST_EN
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FTCTL_TEST_EN 0x00000002
+#define FLASH_FTCTL_TEST_EN_BITN 1
+#define FLASH_FTCTL_TEST_EN_M 0x00000002
+#define FLASH_FTCTL_TEST_EN_S 1
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FWPWRITE0
+//
+//*****************************************************************************
+// Field: [31:0] FWPWRITE0
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FWPWRITE0_FWPWRITE0_W 32
+#define FLASH_FWPWRITE0_FWPWRITE0_M 0xFFFFFFFF
+#define FLASH_FWPWRITE0_FWPWRITE0_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FWPWRITE1
+//
+//*****************************************************************************
+// Field: [31:0] FWPWRITE1
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FWPWRITE1_FWPWRITE1_W 32
+#define FLASH_FWPWRITE1_FWPWRITE1_M 0xFFFFFFFF
+#define FLASH_FWPWRITE1_FWPWRITE1_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FWPWRITE2
+//
+//*****************************************************************************
+// Field: [31:0] FWPWRITE2
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FWPWRITE2_FWPWRITE2_W 32
+#define FLASH_FWPWRITE2_FWPWRITE2_M 0xFFFFFFFF
+#define FLASH_FWPWRITE2_FWPWRITE2_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FWPWRITE3
+//
+//*****************************************************************************
+// Field: [31:0] FWPWRITE3
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FWPWRITE3_FWPWRITE3_W 32
+#define FLASH_FWPWRITE3_FWPWRITE3_M 0xFFFFFFFF
+#define FLASH_FWPWRITE3_FWPWRITE3_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FWPWRITE4
+//
+//*****************************************************************************
+// Field: [31:0] FWPWRITE4
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FWPWRITE4_FWPWRITE4_W 32
+#define FLASH_FWPWRITE4_FWPWRITE4_M 0xFFFFFFFF
+#define FLASH_FWPWRITE4_FWPWRITE4_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FWPWRITE5
+//
+//*****************************************************************************
+// Field: [31:0] FWPWRITE5
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FWPWRITE5_FWPWRITE5_W 32
+#define FLASH_FWPWRITE5_FWPWRITE5_M 0xFFFFFFFF
+#define FLASH_FWPWRITE5_FWPWRITE5_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FWPWRITE6
+//
+//*****************************************************************************
+// Field: [31:0] FWPWRITE6
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FWPWRITE6_FWPWRITE6_W 32
+#define FLASH_FWPWRITE6_FWPWRITE6_M 0xFFFFFFFF
+#define FLASH_FWPWRITE6_FWPWRITE6_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FWPWRITE7
+//
+//*****************************************************************************
+// Field: [31:0] FWPWRITE7
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FWPWRITE7_FWPWRITE7_W 32
+#define FLASH_FWPWRITE7_FWPWRITE7_M 0xFFFFFFFF
+#define FLASH_FWPWRITE7_FWPWRITE7_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FWPWRITE_ECC
+//
+//*****************************************************************************
+// Field: [31:24] ECCBYTES07_00
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_W 8
+#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_M 0xFF000000
+#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_S 24
+
+// Field: [23:16] ECCBYTES15_08
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_W 8
+#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_M 0x00FF0000
+#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_S 16
+
+// Field: [15:8] ECCBYTES23_16
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_W 8
+#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_M 0x0000FF00
+#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_S 8
+
+// Field: [7:0] ECCBYTES31_24
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_W 8
+#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_M 0x000000FF
+#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSWSTAT
+//
+//*****************************************************************************
+// Field: [0] SAFELV
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSWSTAT_SAFELV 0x00000001
+#define FLASH_FSWSTAT_SAFELV_BITN 0
+#define FLASH_FSWSTAT_SAFELV_M 0x00000001
+#define FLASH_FSWSTAT_SAFELV_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_GLBCTL
+//
+//*****************************************************************************
+// Field: [0] CLKSEL
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_GLBCTL_CLKSEL 0x00000001
+#define FLASH_FSM_GLBCTL_CLKSEL_BITN 0
+#define FLASH_FSM_GLBCTL_CLKSEL_M 0x00000001
+#define FLASH_FSM_GLBCTL_CLKSEL_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_STATE
+//
+//*****************************************************************************
+// Field: [11] CTRLENZ
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_STATE_CTRLENZ 0x00000800
+#define FLASH_FSM_STATE_CTRLENZ_BITN 11
+#define FLASH_FSM_STATE_CTRLENZ_M 0x00000800
+#define FLASH_FSM_STATE_CTRLENZ_S 11
+
+// Field: [10] EXECUTEZ
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_STATE_EXECUTEZ 0x00000400
+#define FLASH_FSM_STATE_EXECUTEZ_BITN 10
+#define FLASH_FSM_STATE_EXECUTEZ_M 0x00000400
+#define FLASH_FSM_STATE_EXECUTEZ_S 10
+
+// Field: [8] FSM_ACT
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_STATE_FSM_ACT 0x00000100
+#define FLASH_FSM_STATE_FSM_ACT_BITN 8
+#define FLASH_FSM_STATE_FSM_ACT_M 0x00000100
+#define FLASH_FSM_STATE_FSM_ACT_S 8
+
+// Field: [7] TIOTP_ACT
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_STATE_TIOTP_ACT 0x00000080
+#define FLASH_FSM_STATE_TIOTP_ACT_BITN 7
+#define FLASH_FSM_STATE_TIOTP_ACT_M 0x00000080
+#define FLASH_FSM_STATE_TIOTP_ACT_S 7
+
+// Field: [6] OTP_ACT
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_STATE_OTP_ACT 0x00000040
+#define FLASH_FSM_STATE_OTP_ACT_BITN 6
+#define FLASH_FSM_STATE_OTP_ACT_M 0x00000040
+#define FLASH_FSM_STATE_OTP_ACT_S 6
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_STAT
+//
+//*****************************************************************************
+// Field: [2] NON_OP
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_STAT_NON_OP 0x00000004
+#define FLASH_FSM_STAT_NON_OP_BITN 2
+#define FLASH_FSM_STAT_NON_OP_M 0x00000004
+#define FLASH_FSM_STAT_NON_OP_S 2
+
+// Field: [1] OVR_PUL_CNT
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_STAT_OVR_PUL_CNT 0x00000002
+#define FLASH_FSM_STAT_OVR_PUL_CNT_BITN 1
+#define FLASH_FSM_STAT_OVR_PUL_CNT_M 0x00000002
+#define FLASH_FSM_STAT_OVR_PUL_CNT_S 1
+
+// Field: [0] INV_DAT
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_STAT_INV_DAT 0x00000001
+#define FLASH_FSM_STAT_INV_DAT_BITN 0
+#define FLASH_FSM_STAT_INV_DAT_M 0x00000001
+#define FLASH_FSM_STAT_INV_DAT_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_CMD
+//
+//*****************************************************************************
+// Field: [5:0] FSMCMD
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_CMD_FSMCMD_W 6
+#define FLASH_FSM_CMD_FSMCMD_M 0x0000003F
+#define FLASH_FSM_CMD_FSMCMD_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_PE_OSU
+//
+//*****************************************************************************
+// Field: [15:8] PGM_OSU
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_PE_OSU_PGM_OSU_W 8
+#define FLASH_FSM_PE_OSU_PGM_OSU_M 0x0000FF00
+#define FLASH_FSM_PE_OSU_PGM_OSU_S 8
+
+// Field: [7:0] ERA_OSU
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_PE_OSU_ERA_OSU_W 8
+#define FLASH_FSM_PE_OSU_ERA_OSU_M 0x000000FF
+#define FLASH_FSM_PE_OSU_ERA_OSU_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_VSTAT
+//
+//*****************************************************************************
+// Field: [15:12] VSTAT_CNT
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_VSTAT_VSTAT_CNT_W 4
+#define FLASH_FSM_VSTAT_VSTAT_CNT_M 0x0000F000
+#define FLASH_FSM_VSTAT_VSTAT_CNT_S 12
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_PE_VSU
+//
+//*****************************************************************************
+// Field: [15:8] PGM_VSU
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_PE_VSU_PGM_VSU_W 8
+#define FLASH_FSM_PE_VSU_PGM_VSU_M 0x0000FF00
+#define FLASH_FSM_PE_VSU_PGM_VSU_S 8
+
+// Field: [7:0] ERA_VSU
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_PE_VSU_ERA_VSU_W 8
+#define FLASH_FSM_PE_VSU_ERA_VSU_M 0x000000FF
+#define FLASH_FSM_PE_VSU_ERA_VSU_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_CMP_VSU
+//
+//*****************************************************************************
+// Field: [15:12] ADD_EXZ
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_CMP_VSU_ADD_EXZ_W 4
+#define FLASH_FSM_CMP_VSU_ADD_EXZ_M 0x0000F000
+#define FLASH_FSM_CMP_VSU_ADD_EXZ_S 12
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_EX_VAL
+//
+//*****************************************************************************
+// Field: [15:8] REP_VSU
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_EX_VAL_REP_VSU_W 8
+#define FLASH_FSM_EX_VAL_REP_VSU_M 0x0000FF00
+#define FLASH_FSM_EX_VAL_REP_VSU_S 8
+
+// Field: [7:0] EXE_VALD
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_EX_VAL_EXE_VALD_W 8
+#define FLASH_FSM_EX_VAL_EXE_VALD_M 0x000000FF
+#define FLASH_FSM_EX_VAL_EXE_VALD_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_RD_H
+//
+//*****************************************************************************
+// Field: [7:0] RD_H
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_RD_H_RD_H_W 8
+#define FLASH_FSM_RD_H_RD_H_M 0x000000FF
+#define FLASH_FSM_RD_H_RD_H_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_P_OH
+//
+//*****************************************************************************
+// Field: [15:8] PGM_OH
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_P_OH_PGM_OH_W 8
+#define FLASH_FSM_P_OH_PGM_OH_M 0x0000FF00
+#define FLASH_FSM_P_OH_PGM_OH_S 8
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_ERA_OH
+//
+//*****************************************************************************
+// Field: [15:0] ERA_OH
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_ERA_OH_ERA_OH_W 16
+#define FLASH_FSM_ERA_OH_ERA_OH_M 0x0000FFFF
+#define FLASH_FSM_ERA_OH_ERA_OH_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_SAV_PPUL
+//
+//*****************************************************************************
+// Field: [11:0] SAV_P_PUL
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_W 12
+#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_M 0x00000FFF
+#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_PE_VH
+//
+//*****************************************************************************
+// Field: [15:8] PGM_VH
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_PE_VH_PGM_VH_W 8
+#define FLASH_FSM_PE_VH_PGM_VH_M 0x0000FF00
+#define FLASH_FSM_PE_VH_PGM_VH_S 8
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_PRG_PW
+//
+//*****************************************************************************
+// Field: [15:0] PROG_PUL_WIDTH
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_W 16
+#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_M 0x0000FFFF
+#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_ERA_PW
+//
+//*****************************************************************************
+// Field: [31:0] FSM_ERA_PW
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_ERA_PW_FSM_ERA_PW_W 32
+#define FLASH_FSM_ERA_PW_FSM_ERA_PW_M 0xFFFFFFFF
+#define FLASH_FSM_ERA_PW_FSM_ERA_PW_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_SAV_ERA_PUL
+//
+//*****************************************************************************
+// Field: [11:0] SAV_ERA_PUL
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_W 12
+#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_M 0x00000FFF
+#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_TIMER
+//
+//*****************************************************************************
+// Field: [31:0] FSM_TIMER
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_TIMER_FSM_TIMER_W 32
+#define FLASH_FSM_TIMER_FSM_TIMER_M 0xFFFFFFFF
+#define FLASH_FSM_TIMER_FSM_TIMER_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_MODE
+//
+//*****************************************************************************
+// Field: [19:18] RDV_SUBMODE
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_MODE_RDV_SUBMODE_W 2
+#define FLASH_FSM_MODE_RDV_SUBMODE_M 0x000C0000
+#define FLASH_FSM_MODE_RDV_SUBMODE_S 18
+
+// Field: [17:16] PGM_SUBMODE
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_MODE_PGM_SUBMODE_W 2
+#define FLASH_FSM_MODE_PGM_SUBMODE_M 0x00030000
+#define FLASH_FSM_MODE_PGM_SUBMODE_S 16
+
+// Field: [15:14] ERA_SUBMODE
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_MODE_ERA_SUBMODE_W 2
+#define FLASH_FSM_MODE_ERA_SUBMODE_M 0x0000C000
+#define FLASH_FSM_MODE_ERA_SUBMODE_S 14
+
+// Field: [13:12] SUBMODE
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_MODE_SUBMODE_W 2
+#define FLASH_FSM_MODE_SUBMODE_M 0x00003000
+#define FLASH_FSM_MODE_SUBMODE_S 12
+
+// Field: [11:9] SAV_PGM_CMD
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_MODE_SAV_PGM_CMD_W 3
+#define FLASH_FSM_MODE_SAV_PGM_CMD_M 0x00000E00
+#define FLASH_FSM_MODE_SAV_PGM_CMD_S 9
+
+// Field: [8:6] SAV_ERA_MODE
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_MODE_SAV_ERA_MODE_W 3
+#define FLASH_FSM_MODE_SAV_ERA_MODE_M 0x000001C0
+#define FLASH_FSM_MODE_SAV_ERA_MODE_S 6
+
+// Field: [5:3] MODE
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_MODE_MODE_W 3
+#define FLASH_FSM_MODE_MODE_M 0x00000038
+#define FLASH_FSM_MODE_MODE_S 3
+
+// Field: [2:0] CMD
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_MODE_CMD_W 3
+#define FLASH_FSM_MODE_CMD_M 0x00000007
+#define FLASH_FSM_MODE_CMD_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_PGM
+//
+//*****************************************************************************
+// Field: [25:23] PGM_BANK
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_PGM_PGM_BANK_W 3
+#define FLASH_FSM_PGM_PGM_BANK_M 0x03800000
+#define FLASH_FSM_PGM_PGM_BANK_S 23
+
+// Field: [22:0] PGM_ADDR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_PGM_PGM_ADDR_W 23
+#define FLASH_FSM_PGM_PGM_ADDR_M 0x007FFFFF
+#define FLASH_FSM_PGM_PGM_ADDR_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_ERA
+//
+//*****************************************************************************
+// Field: [25:23] ERA_BANK
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_ERA_ERA_BANK_W 3
+#define FLASH_FSM_ERA_ERA_BANK_M 0x03800000
+#define FLASH_FSM_ERA_ERA_BANK_S 23
+
+// Field: [22:0] ERA_ADDR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_ERA_ERA_ADDR_W 23
+#define FLASH_FSM_ERA_ERA_ADDR_M 0x007FFFFF
+#define FLASH_FSM_ERA_ERA_ADDR_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_PRG_PUL
+//
+//*****************************************************************************
+// Field: [19:16] BEG_EC_LEVEL
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_W 4
+#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_M 0x000F0000
+#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_S 16
+
+// Field: [11:0] MAX_PRG_PUL
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_W 12
+#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_M 0x00000FFF
+#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_ERA_PUL
+//
+//*****************************************************************************
+// Field: [19:16] MAX_EC_LEVEL
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_W 4
+#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_M 0x000F0000
+#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_S 16
+
+// Field: [11:0] MAX_ERA_PUL
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_W 12
+#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_M 0x00000FFF
+#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_STEP_SIZE
+//
+//*****************************************************************************
+// Field: [24:16] EC_STEP_SIZE
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_W 9
+#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_M 0x01FF0000
+#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_S 16
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_PUL_CNTR
+//
+//*****************************************************************************
+// Field: [24:16] CUR_EC_LEVEL
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_W 9
+#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_M 0x01FF0000
+#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_S 16
+
+// Field: [11:0] PUL_CNTR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_PUL_CNTR_PUL_CNTR_W 12
+#define FLASH_FSM_PUL_CNTR_PUL_CNTR_M 0x00000FFF
+#define FLASH_FSM_PUL_CNTR_PUL_CNTR_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_EC_STEP_HEIGHT
+//
+//*****************************************************************************
+// Field: [3:0] EC_STEP_HEIGHT
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_W 4
+#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_M 0x0000000F
+#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_ST_MACHINE
+//
+//*****************************************************************************
+// Field: [23] DO_PRECOND
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_ST_MACHINE_DO_PRECOND 0x00800000
+#define FLASH_FSM_ST_MACHINE_DO_PRECOND_BITN 23
+#define FLASH_FSM_ST_MACHINE_DO_PRECOND_M 0x00800000
+#define FLASH_FSM_ST_MACHINE_DO_PRECOND_S 23
+
+// Field: [22] FSM_INT_EN
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_ST_MACHINE_FSM_INT_EN 0x00400000
+#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_BITN 22
+#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_M 0x00400000
+#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_S 22
+
+// Field: [21] ALL_BANKS
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_ST_MACHINE_ALL_BANKS 0x00200000
+#define FLASH_FSM_ST_MACHINE_ALL_BANKS_BITN 21
+#define FLASH_FSM_ST_MACHINE_ALL_BANKS_M 0x00200000
+#define FLASH_FSM_ST_MACHINE_ALL_BANKS_S 21
+
+// Field: [20] CMPV_ALLOWED
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED 0x00100000
+#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_BITN 20
+#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_M 0x00100000
+#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_S 20
+
+// Field: [19] RANDOM
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_ST_MACHINE_RANDOM 0x00080000
+#define FLASH_FSM_ST_MACHINE_RANDOM_BITN 19
+#define FLASH_FSM_ST_MACHINE_RANDOM_M 0x00080000
+#define FLASH_FSM_ST_MACHINE_RANDOM_S 19
+
+// Field: [18] RV_SEC_EN
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_ST_MACHINE_RV_SEC_EN 0x00040000
+#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_BITN 18
+#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_M 0x00040000
+#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_S 18
+
+// Field: [17] RV_RES
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_ST_MACHINE_RV_RES 0x00020000
+#define FLASH_FSM_ST_MACHINE_RV_RES_BITN 17
+#define FLASH_FSM_ST_MACHINE_RV_RES_M 0x00020000
+#define FLASH_FSM_ST_MACHINE_RV_RES_S 17
+
+// Field: [16] RV_INT_EN
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_ST_MACHINE_RV_INT_EN 0x00010000
+#define FLASH_FSM_ST_MACHINE_RV_INT_EN_BITN 16
+#define FLASH_FSM_ST_MACHINE_RV_INT_EN_M 0x00010000
+#define FLASH_FSM_ST_MACHINE_RV_INT_EN_S 16
+
+// Field: [14] ONE_TIME_GOOD
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD 0x00004000
+#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_BITN 14
+#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_M 0x00004000
+#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_S 14
+
+// Field: [11] DO_REDU_COL
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_ST_MACHINE_DO_REDU_COL 0x00000800
+#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_BITN 11
+#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_M 0x00000800
+#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_S 11
+
+// Field: [10:7] DBG_SHORT_ROW
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_W 4
+#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_M 0x00000780
+#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_S 7
+
+// Field: [5] PGM_SEC_COF_EN
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN 0x00000020
+#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_BITN 5
+#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_M 0x00000020
+#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_S 5
+
+// Field: [4] PREC_STOP_EN
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN 0x00000010
+#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_BITN 4
+#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_M 0x00000010
+#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_S 4
+
+// Field: [3] DIS_TST_EN
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_ST_MACHINE_DIS_TST_EN 0x00000008
+#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_BITN 3
+#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_M 0x00000008
+#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_S 3
+
+// Field: [2] CMD_EN
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_ST_MACHINE_CMD_EN 0x00000004
+#define FLASH_FSM_ST_MACHINE_CMD_EN_BITN 2
+#define FLASH_FSM_ST_MACHINE_CMD_EN_M 0x00000004
+#define FLASH_FSM_ST_MACHINE_CMD_EN_S 2
+
+// Field: [1] INV_DATA
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_ST_MACHINE_INV_DATA 0x00000002
+#define FLASH_FSM_ST_MACHINE_INV_DATA_BITN 1
+#define FLASH_FSM_ST_MACHINE_INV_DATA_M 0x00000002
+#define FLASH_FSM_ST_MACHINE_INV_DATA_S 1
+
+// Field: [0] OVERRIDE
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_ST_MACHINE_OVERRIDE 0x00000001
+#define FLASH_FSM_ST_MACHINE_OVERRIDE_BITN 0
+#define FLASH_FSM_ST_MACHINE_OVERRIDE_M 0x00000001
+#define FLASH_FSM_ST_MACHINE_OVERRIDE_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_FLES
+//
+//*****************************************************************************
+// Field: [11:8] BLK_TIOTP
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_FLES_BLK_TIOTP_W 4
+#define FLASH_FSM_FLES_BLK_TIOTP_M 0x00000F00
+#define FLASH_FSM_FLES_BLK_TIOTP_S 8
+
+// Field: [7:0] BLK_OTP
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_FLES_BLK_OTP_W 8
+#define FLASH_FSM_FLES_BLK_OTP_M 0x000000FF
+#define FLASH_FSM_FLES_BLK_OTP_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_WR_ENA
+//
+//*****************************************************************************
+// Field: [2:0] WR_ENA
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_WR_ENA_WR_ENA_W 3
+#define FLASH_FSM_WR_ENA_WR_ENA_M 0x00000007
+#define FLASH_FSM_WR_ENA_WR_ENA_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_ACC_PP
+//
+//*****************************************************************************
+// Field: [31:0] FSM_ACC_PP
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_ACC_PP_FSM_ACC_PP_W 32
+#define FLASH_FSM_ACC_PP_FSM_ACC_PP_M 0xFFFFFFFF
+#define FLASH_FSM_ACC_PP_FSM_ACC_PP_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_ACC_EP
+//
+//*****************************************************************************
+// Field: [15:0] ACC_EP
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_ACC_EP_ACC_EP_W 16
+#define FLASH_FSM_ACC_EP_ACC_EP_M 0x0000FFFF
+#define FLASH_FSM_ACC_EP_ACC_EP_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_ADDR
+//
+//*****************************************************************************
+// Field: [30:28] BANK
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_ADDR_BANK_W 3
+#define FLASH_FSM_ADDR_BANK_M 0x70000000
+#define FLASH_FSM_ADDR_BANK_S 28
+
+// Field: [27:0] CUR_ADDR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_ADDR_CUR_ADDR_W 28
+#define FLASH_FSM_ADDR_CUR_ADDR_M 0x0FFFFFFF
+#define FLASH_FSM_ADDR_CUR_ADDR_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_SECTOR
+//
+//*****************************************************************************
+// Field: [31:16] SECT_ERASED
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_SECTOR_SECT_ERASED_W 16
+#define FLASH_FSM_SECTOR_SECT_ERASED_M 0xFFFF0000
+#define FLASH_FSM_SECTOR_SECT_ERASED_S 16
+
+// Field: [15:8] FSM_SECTOR_EXTENSION
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_W 8
+#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_M 0x0000FF00
+#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_S 8
+
+// Field: [7:4] SECTOR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_SECTOR_SECTOR_W 4
+#define FLASH_FSM_SECTOR_SECTOR_M 0x000000F0
+#define FLASH_FSM_SECTOR_SECTOR_S 4
+
+// Field: [3:0] SEC_OUT
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_SECTOR_SEC_OUT_W 4
+#define FLASH_FSM_SECTOR_SEC_OUT_M 0x0000000F
+#define FLASH_FSM_SECTOR_SEC_OUT_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FMC_REV_ID
+//
+//*****************************************************************************
+// Field: [31:12] MOD_VERSION
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FMC_REV_ID_MOD_VERSION_W 20
+#define FLASH_FMC_REV_ID_MOD_VERSION_M 0xFFFFF000
+#define FLASH_FMC_REV_ID_MOD_VERSION_S 12
+
+// Field: [11:0] CONFIG_CRC
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FMC_REV_ID_CONFIG_CRC_W 12
+#define FLASH_FMC_REV_ID_CONFIG_CRC_M 0x00000FFF
+#define FLASH_FMC_REV_ID_CONFIG_CRC_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_ERR_ADDR
+//
+//*****************************************************************************
+// Field: [31:8] FSM_ERR_ADDR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_W 24
+#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_M 0xFFFFFF00
+#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_S 8
+
+// Field: [3:0] FSM_ERR_BANK
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_W 4
+#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_M 0x0000000F
+#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_PGM_MAXPUL
+//
+//*****************************************************************************
+// Field: [11:0] FSM_PGM_MAXPUL
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_W 12
+#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_M 0x00000FFF
+#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_EXECUTE
+//
+//*****************************************************************************
+// Field: [19:16] SUSPEND_NOW
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_EXECUTE_SUSPEND_NOW_W 4
+#define FLASH_FSM_EXECUTE_SUSPEND_NOW_M 0x000F0000
+#define FLASH_FSM_EXECUTE_SUSPEND_NOW_S 16
+
+// Field: [4:0] FSMEXECUTE
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_EXECUTE_FSMEXECUTE_W 5
+#define FLASH_FSM_EXECUTE_FSMEXECUTE_M 0x0000001F
+#define FLASH_FSM_EXECUTE_FSMEXECUTE_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_SECTOR1
+//
+//*****************************************************************************
+// Field: [31:0] FSM_SECTOR1
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_SECTOR1_FSM_SECTOR1_W 32
+#define FLASH_FSM_SECTOR1_FSM_SECTOR1_M 0xFFFFFFFF
+#define FLASH_FSM_SECTOR1_FSM_SECTOR1_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_SECTOR2
+//
+//*****************************************************************************
+// Field: [31:0] FSM_SECTOR2
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_SECTOR2_FSM_SECTOR2_W 32
+#define FLASH_FSM_SECTOR2_FSM_SECTOR2_M 0xFFFFFFFF
+#define FLASH_FSM_SECTOR2_FSM_SECTOR2_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_BSLE0
+//
+//*****************************************************************************
+// Field: [31:0] FSM_BSLE0
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_BSLE0_FSM_BSLE0_W 32
+#define FLASH_FSM_BSLE0_FSM_BSLE0_M 0xFFFFFFFF
+#define FLASH_FSM_BSLE0_FSM_BSLE0_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_BSLE1
+//
+//*****************************************************************************
+// Field: [31:0] FSM_BSL1
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_BSLE1_FSM_BSL1_W 32
+#define FLASH_FSM_BSLE1_FSM_BSL1_M 0xFFFFFFFF
+#define FLASH_FSM_BSLE1_FSM_BSL1_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_BSLP0
+//
+//*****************************************************************************
+// Field: [31:0] FSM_BSLP0
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_BSLP0_FSM_BSLP0_W 32
+#define FLASH_FSM_BSLP0_FSM_BSLP0_M 0xFFFFFFFF
+#define FLASH_FSM_BSLP0_FSM_BSLP0_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_BSLP1
+//
+//*****************************************************************************
+// Field: [31:0] FSM_BSL1
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FSM_BSLP1_FSM_BSL1_W 32
+#define FLASH_FSM_BSLP1_FSM_BSL1_M 0xFFFFFFFF
+#define FLASH_FSM_BSLP1_FSM_BSL1_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FSM_PGM128
+//
+//*****************************************************************************
+// Field: [0] EN_PGM128
+//
+// 1: Enables 128-bit wide programming. This mode requires programming supply
+// voltage to be greater than 2.5v at the Flash Pump. The primary use case for
+// this mode is manufacturing test for test time reduction.
+//
+// 0: 64-bit wide programming. Valid at any programming voltage. A 128-bit
+// word is divided into two 64-bit words for programming. [default]
+//
+// This register is write protected with the FSM_WR_ENA register.
+#define FLASH_FSM_PGM128_EN_PGM128 0x00000001
+#define FLASH_FSM_PGM128_EN_PGM128_BITN 0
+#define FLASH_FSM_PGM128_EN_PGM128_M 0x00000001
+#define FLASH_FSM_PGM128_EN_PGM128_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FCFG_BANK
+//
+//*****************************************************************************
+// Field: [31:20] EE_BANK_WIDTH
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_BANK_EE_BANK_WIDTH_W 12
+#define FLASH_FCFG_BANK_EE_BANK_WIDTH_M 0xFFF00000
+#define FLASH_FCFG_BANK_EE_BANK_WIDTH_S 20
+
+// Field: [19:16] EE_NUM_BANK
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_BANK_EE_NUM_BANK_W 4
+#define FLASH_FCFG_BANK_EE_NUM_BANK_M 0x000F0000
+#define FLASH_FCFG_BANK_EE_NUM_BANK_S 16
+
+// Field: [15:4] MAIN_BANK_WIDTH
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_W 12
+#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M 0x0000FFF0
+#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S 4
+
+// Field: [3:0] MAIN_NUM_BANK
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_BANK_MAIN_NUM_BANK_W 4
+#define FLASH_FCFG_BANK_MAIN_NUM_BANK_M 0x0000000F
+#define FLASH_FCFG_BANK_MAIN_NUM_BANK_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FCFG_WRAPPER
+//
+//*****************************************************************************
+// Field: [31:24] FAMILY_TYPE
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_W 8
+#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_M 0xFF000000
+#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_S 24
+
+// Field: [20] MEM_MAP
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_WRAPPER_MEM_MAP 0x00100000
+#define FLASH_FCFG_WRAPPER_MEM_MAP_BITN 20
+#define FLASH_FCFG_WRAPPER_MEM_MAP_M 0x00100000
+#define FLASH_FCFG_WRAPPER_MEM_MAP_S 20
+
+// Field: [19:16] CPU2
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_WRAPPER_CPU2_W 4
+#define FLASH_FCFG_WRAPPER_CPU2_M 0x000F0000
+#define FLASH_FCFG_WRAPPER_CPU2_S 16
+
+// Field: [15:12] EE_IN_MAIN
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_W 4
+#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_M 0x0000F000
+#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_S 12
+
+// Field: [11] ROM
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_WRAPPER_ROM 0x00000800
+#define FLASH_FCFG_WRAPPER_ROM_BITN 11
+#define FLASH_FCFG_WRAPPER_ROM_M 0x00000800
+#define FLASH_FCFG_WRAPPER_ROM_S 11
+
+// Field: [10] IFLUSH
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_WRAPPER_IFLUSH 0x00000400
+#define FLASH_FCFG_WRAPPER_IFLUSH_BITN 10
+#define FLASH_FCFG_WRAPPER_IFLUSH_M 0x00000400
+#define FLASH_FCFG_WRAPPER_IFLUSH_S 10
+
+// Field: [9] SIL3
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_WRAPPER_SIL3 0x00000200
+#define FLASH_FCFG_WRAPPER_SIL3_BITN 9
+#define FLASH_FCFG_WRAPPER_SIL3_M 0x00000200
+#define FLASH_FCFG_WRAPPER_SIL3_S 9
+
+// Field: [8] ECCA
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_WRAPPER_ECCA 0x00000100
+#define FLASH_FCFG_WRAPPER_ECCA_BITN 8
+#define FLASH_FCFG_WRAPPER_ECCA_M 0x00000100
+#define FLASH_FCFG_WRAPPER_ECCA_S 8
+
+// Field: [7:6] AUTO_SUSP
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_WRAPPER_AUTO_SUSP_W 2
+#define FLASH_FCFG_WRAPPER_AUTO_SUSP_M 0x000000C0
+#define FLASH_FCFG_WRAPPER_AUTO_SUSP_S 6
+
+// Field: [5:4] UERR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_WRAPPER_UERR_W 2
+#define FLASH_FCFG_WRAPPER_UERR_M 0x00000030
+#define FLASH_FCFG_WRAPPER_UERR_S 4
+
+// Field: [3:0] CPU_TYPE1
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_WRAPPER_CPU_TYPE1_W 4
+#define FLASH_FCFG_WRAPPER_CPU_TYPE1_M 0x0000000F
+#define FLASH_FCFG_WRAPPER_CPU_TYPE1_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FCFG_BNK_TYPE
+//
+//*****************************************************************************
+// Field: [31:28] B7_TYPE
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_BNK_TYPE_B7_TYPE_W 4
+#define FLASH_FCFG_BNK_TYPE_B7_TYPE_M 0xF0000000
+#define FLASH_FCFG_BNK_TYPE_B7_TYPE_S 28
+
+// Field: [27:24] B6_TYPE
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_BNK_TYPE_B6_TYPE_W 4
+#define FLASH_FCFG_BNK_TYPE_B6_TYPE_M 0x0F000000
+#define FLASH_FCFG_BNK_TYPE_B6_TYPE_S 24
+
+// Field: [23:20] B5_TYPE
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_BNK_TYPE_B5_TYPE_W 4
+#define FLASH_FCFG_BNK_TYPE_B5_TYPE_M 0x00F00000
+#define FLASH_FCFG_BNK_TYPE_B5_TYPE_S 20
+
+// Field: [19:16] B4_TYPE
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_BNK_TYPE_B4_TYPE_W 4
+#define FLASH_FCFG_BNK_TYPE_B4_TYPE_M 0x000F0000
+#define FLASH_FCFG_BNK_TYPE_B4_TYPE_S 16
+
+// Field: [15:12] B3_TYPE
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_BNK_TYPE_B3_TYPE_W 4
+#define FLASH_FCFG_BNK_TYPE_B3_TYPE_M 0x0000F000
+#define FLASH_FCFG_BNK_TYPE_B3_TYPE_S 12
+
+// Field: [11:8] B2_TYPE
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_BNK_TYPE_B2_TYPE_W 4
+#define FLASH_FCFG_BNK_TYPE_B2_TYPE_M 0x00000F00
+#define FLASH_FCFG_BNK_TYPE_B2_TYPE_S 8
+
+// Field: [7:4] B1_TYPE
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_BNK_TYPE_B1_TYPE_W 4
+#define FLASH_FCFG_BNK_TYPE_B1_TYPE_M 0x000000F0
+#define FLASH_FCFG_BNK_TYPE_B1_TYPE_S 4
+
+// Field: [3:0] B0_TYPE
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_BNK_TYPE_B0_TYPE_W 4
+#define FLASH_FCFG_BNK_TYPE_B0_TYPE_M 0x0000000F
+#define FLASH_FCFG_BNK_TYPE_B0_TYPE_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FCFG_B0_START
+//
+//*****************************************************************************
+// Field: [31:28] B0_MAX_SECTOR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_W 4
+#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_M 0xF0000000
+#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_S 28
+
+// Field: [27:24] B0_MUX_FACTOR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_W 4
+#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_M 0x0F000000
+#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_S 24
+
+// Field: [23:0] B0_START_ADDR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_B0_START_B0_START_ADDR_W 24
+#define FLASH_FCFG_B0_START_B0_START_ADDR_M 0x00FFFFFF
+#define FLASH_FCFG_B0_START_B0_START_ADDR_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FCFG_B1_START
+//
+//*****************************************************************************
+// Field: [31:28] B1_MAX_SECTOR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_W 4
+#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_M 0xF0000000
+#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_S 28
+
+// Field: [27:24] B1_MUX_FACTOR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_W 4
+#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_M 0x0F000000
+#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_S 24
+
+// Field: [23:0] B1_START_ADDR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_B1_START_B1_START_ADDR_W 24
+#define FLASH_FCFG_B1_START_B1_START_ADDR_M 0x00FFFFFF
+#define FLASH_FCFG_B1_START_B1_START_ADDR_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FCFG_B2_START
+//
+//*****************************************************************************
+// Field: [31:28] B2_MAX_SECTOR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_W 4
+#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_M 0xF0000000
+#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_S 28
+
+// Field: [27:24] B2_MUX_FACTOR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_W 4
+#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_M 0x0F000000
+#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_S 24
+
+// Field: [23:0] B2_START_ADDR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_B2_START_B2_START_ADDR_W 24
+#define FLASH_FCFG_B2_START_B2_START_ADDR_M 0x00FFFFFF
+#define FLASH_FCFG_B2_START_B2_START_ADDR_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FCFG_B3_START
+//
+//*****************************************************************************
+// Field: [31:28] B3_MAX_SECTOR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_W 4
+#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_M 0xF0000000
+#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_S 28
+
+// Field: [27:24] B3_MUX_FACTOR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_W 4
+#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_M 0x0F000000
+#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_S 24
+
+// Field: [23:0] B3_START_ADDR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_B3_START_B3_START_ADDR_W 24
+#define FLASH_FCFG_B3_START_B3_START_ADDR_M 0x00FFFFFF
+#define FLASH_FCFG_B3_START_B3_START_ADDR_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FCFG_B4_START
+//
+//*****************************************************************************
+// Field: [31:28] B4_MAX_SECTOR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_W 4
+#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_M 0xF0000000
+#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_S 28
+
+// Field: [27:24] B4_MUX_FACTOR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_W 4
+#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_M 0x0F000000
+#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_S 24
+
+// Field: [23:0] B4_START_ADDR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_B4_START_B4_START_ADDR_W 24
+#define FLASH_FCFG_B4_START_B4_START_ADDR_M 0x00FFFFFF
+#define FLASH_FCFG_B4_START_B4_START_ADDR_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FCFG_B5_START
+//
+//*****************************************************************************
+// Field: [31:28] B5_MAX_SECTOR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_W 4
+#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_M 0xF0000000
+#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_S 28
+
+// Field: [27:24] B5_MUX_FACTOR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_W 4
+#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_M 0x0F000000
+#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_S 24
+
+// Field: [23:0] B5_START_ADDR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_B5_START_B5_START_ADDR_W 24
+#define FLASH_FCFG_B5_START_B5_START_ADDR_M 0x00FFFFFF
+#define FLASH_FCFG_B5_START_B5_START_ADDR_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FCFG_B6_START
+//
+//*****************************************************************************
+// Field: [31:28] B6_MAX_SECTOR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_W 4
+#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_M 0xF0000000
+#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_S 28
+
+// Field: [27:24] B6_MUX_FACTOR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_W 4
+#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_M 0x0F000000
+#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_S 24
+
+// Field: [23:0] B6_START_ADDR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_B6_START_B6_START_ADDR_W 24
+#define FLASH_FCFG_B6_START_B6_START_ADDR_M 0x00FFFFFF
+#define FLASH_FCFG_B6_START_B6_START_ADDR_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FCFG_B7_START
+//
+//*****************************************************************************
+// Field: [31:28] B7_MAX_SECTOR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_W 4
+#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_M 0xF0000000
+#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_S 28
+
+// Field: [27:24] B7_MUX_FACTOR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_W 4
+#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_M 0x0F000000
+#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_S 24
+
+// Field: [23:0] B7_START_ADDR
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_B7_START_B7_START_ADDR_W 24
+#define FLASH_FCFG_B7_START_B7_START_ADDR_M 0x00FFFFFF
+#define FLASH_FCFG_B7_START_B7_START_ADDR_S 0
+
+//*****************************************************************************
+//
+// Register: FLASH_O_FCFG_B0_SSIZE0
+//
+//*****************************************************************************
+// Field: [27:16] B0_NUM_SECTORS
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_W 12
+#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_M 0x0FFF0000
+#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_S 16
+
+// Field: [3:0] B0_SECT_SIZE
+//
+// Internal. Only to be used through TI provided API.
+#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_W 4
+#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_M 0x0000000F
+#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_S 0
+
+
+#endif // __FLASH__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_gpio.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_gpio.h
new file mode 100644
index 0000000..8ec4bfb
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_gpio.h
@@ -0,0 +1,2247 @@
+/******************************************************************************
+* Filename: hw_gpio_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_GPIO_H__
+#define __HW_GPIO_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// GPIO component
+//
+//*****************************************************************************
+// Data Out 0 to 3
+#define GPIO_O_DOUT3_0 0x00000000
+
+// Data Out 4 to 7
+#define GPIO_O_DOUT7_4 0x00000004
+
+// Data Out 8 to 11
+#define GPIO_O_DOUT11_8 0x00000008
+
+// Data Out 12 to 15
+#define GPIO_O_DOUT15_12 0x0000000C
+
+// Data Out 16 to 19
+#define GPIO_O_DOUT19_16 0x00000010
+
+// Data Out 20 to 23
+#define GPIO_O_DOUT23_20 0x00000014
+
+// Data Out 24 to 27
+#define GPIO_O_DOUT27_24 0x00000018
+
+// Data Out 28 to 31
+#define GPIO_O_DOUT31_28 0x0000001C
+
+// Data Output for DIO 0 to 31
+#define GPIO_O_DOUT31_0 0x00000080
+
+// Data Out Set
+#define GPIO_O_DOUTSET31_0 0x00000090
+
+// Data Out Clear
+#define GPIO_O_DOUTCLR31_0 0x000000A0
+
+// Data Out Toggle
+#define GPIO_O_DOUTTGL31_0 0x000000B0
+
+// Data Input from DIO 0 to 31
+#define GPIO_O_DIN31_0 0x000000C0
+
+// Data Output Enable for DIO 0 to 31
+#define GPIO_O_DOE31_0 0x000000D0
+
+// Event Register for DIO 0 to 31
+#define GPIO_O_EVFLAGS31_0 0x000000E0
+
+//*****************************************************************************
+//
+// Register: GPIO_O_DOUT3_0
+//
+//*****************************************************************************
+// Field: [24] DIO3
+//
+// Sets the state of the pin that is configured as DIO#3, if the corresponding
+// DOE31_0 bitfield is set.
+#define GPIO_DOUT3_0_DIO3 0x01000000
+#define GPIO_DOUT3_0_DIO3_BITN 24
+#define GPIO_DOUT3_0_DIO3_M 0x01000000
+#define GPIO_DOUT3_0_DIO3_S 24
+
+// Field: [16] DIO2
+//
+// Sets the state of the pin that is configured as DIO#2, if the corresponding
+// DOE31_0 bitfield is set.
+#define GPIO_DOUT3_0_DIO2 0x00010000
+#define GPIO_DOUT3_0_DIO2_BITN 16
+#define GPIO_DOUT3_0_DIO2_M 0x00010000
+#define GPIO_DOUT3_0_DIO2_S 16
+
+// Field: [8] DIO1
+//
+// Sets the state of the pin that is configured as DIO#1, if the corresponding
+// DOE31_0 bitfield is set.
+#define GPIO_DOUT3_0_DIO1 0x00000100
+#define GPIO_DOUT3_0_DIO1_BITN 8
+#define GPIO_DOUT3_0_DIO1_M 0x00000100
+#define GPIO_DOUT3_0_DIO1_S 8
+
+// Field: [0] DIO0
+//
+// Sets the state of the pin that is configured as DIO#0, if the corresponding
+// DOE31_0 bitfield is set.
+#define GPIO_DOUT3_0_DIO0 0x00000001
+#define GPIO_DOUT3_0_DIO0_BITN 0
+#define GPIO_DOUT3_0_DIO0_M 0x00000001
+#define GPIO_DOUT3_0_DIO0_S 0
+
+//*****************************************************************************
+//
+// Register: GPIO_O_DOUT7_4
+//
+//*****************************************************************************
+// Field: [24] DIO7
+//
+// Sets the state of the pin that is configured as DIO#7, if the corresponding
+// DOE31_0 bitfield is set.
+#define GPIO_DOUT7_4_DIO7 0x01000000
+#define GPIO_DOUT7_4_DIO7_BITN 24
+#define GPIO_DOUT7_4_DIO7_M 0x01000000
+#define GPIO_DOUT7_4_DIO7_S 24
+
+// Field: [16] DIO6
+//
+// Sets the state of the pin that is configured as DIO#6, if the corresponding
+// DOE31_0 bitfield is set.
+#define GPIO_DOUT7_4_DIO6 0x00010000
+#define GPIO_DOUT7_4_DIO6_BITN 16
+#define GPIO_DOUT7_4_DIO6_M 0x00010000
+#define GPIO_DOUT7_4_DIO6_S 16
+
+// Field: [8] DIO5
+//
+// Sets the state of the pin that is configured as DIO#5, if the corresponding
+// DOE31_0 bitfield is set.
+#define GPIO_DOUT7_4_DIO5 0x00000100
+#define GPIO_DOUT7_4_DIO5_BITN 8
+#define GPIO_DOUT7_4_DIO5_M 0x00000100
+#define GPIO_DOUT7_4_DIO5_S 8
+
+// Field: [0] DIO4
+//
+// Sets the state of the pin that is configured as DIO#4, if the corresponding
+// DOE31_0 bitfield is set.
+#define GPIO_DOUT7_4_DIO4 0x00000001
+#define GPIO_DOUT7_4_DIO4_BITN 0
+#define GPIO_DOUT7_4_DIO4_M 0x00000001
+#define GPIO_DOUT7_4_DIO4_S 0
+
+//*****************************************************************************
+//
+// Register: GPIO_O_DOUT11_8
+//
+//*****************************************************************************
+// Field: [24] DIO11
+//
+// Sets the state of the pin that is configured as DIO#11, if the corresponding
+// DOE31_0 bitfield is set.
+#define GPIO_DOUT11_8_DIO11 0x01000000
+#define GPIO_DOUT11_8_DIO11_BITN 24
+#define GPIO_DOUT11_8_DIO11_M 0x01000000
+#define GPIO_DOUT11_8_DIO11_S 24
+
+// Field: [16] DIO10
+//
+// Sets the state of the pin that is configured as DIO#10, if the corresponding
+// DOE31_0 bitfield is set.
+#define GPIO_DOUT11_8_DIO10 0x00010000
+#define GPIO_DOUT11_8_DIO10_BITN 16
+#define GPIO_DOUT11_8_DIO10_M 0x00010000
+#define GPIO_DOUT11_8_DIO10_S 16
+
+// Field: [8] DIO9
+//
+// Sets the state of the pin that is configured as DIO#9, if the corresponding
+// DOE31_0 bitfield is set.
+#define GPIO_DOUT11_8_DIO9 0x00000100
+#define GPIO_DOUT11_8_DIO9_BITN 8
+#define GPIO_DOUT11_8_DIO9_M 0x00000100
+#define GPIO_DOUT11_8_DIO9_S 8
+
+// Field: [0] DIO8
+//
+// Sets the state of the pin that is configured as DIO#8, if the corresponding
+// DOE31_0 bitfield is set.
+#define GPIO_DOUT11_8_DIO8 0x00000001
+#define GPIO_DOUT11_8_DIO8_BITN 0
+#define GPIO_DOUT11_8_DIO8_M 0x00000001
+#define GPIO_DOUT11_8_DIO8_S 0
+
+//*****************************************************************************
+//
+// Register: GPIO_O_DOUT15_12
+//
+//*****************************************************************************
+// Field: [24] DIO15
+//
+// Sets the state of the pin that is configured as DIO#15, if the corresponding
+// DOE31_0 bitfield is set.
+#define GPIO_DOUT15_12_DIO15 0x01000000
+#define GPIO_DOUT15_12_DIO15_BITN 24
+#define GPIO_DOUT15_12_DIO15_M 0x01000000
+#define GPIO_DOUT15_12_DIO15_S 24
+
+// Field: [16] DIO14
+//
+// Sets the state of the pin that is configured as DIO#14, if the corresponding
+// DOE31_0 bitfield is set.
+#define GPIO_DOUT15_12_DIO14 0x00010000
+#define GPIO_DOUT15_12_DIO14_BITN 16
+#define GPIO_DOUT15_12_DIO14_M 0x00010000
+#define GPIO_DOUT15_12_DIO14_S 16
+
+// Field: [8] DIO13
+//
+// Sets the state of the pin that is configured as DIO#13, if the corresponding
+// DOE31_0 bitfield is set.
+#define GPIO_DOUT15_12_DIO13 0x00000100
+#define GPIO_DOUT15_12_DIO13_BITN 8
+#define GPIO_DOUT15_12_DIO13_M 0x00000100
+#define GPIO_DOUT15_12_DIO13_S 8
+
+// Field: [0] DIO12
+//
+// Sets the state of the pin that is configured as DIO#12, if the corresponding
+// DOE31_0 bitfield is set.
+#define GPIO_DOUT15_12_DIO12 0x00000001
+#define GPIO_DOUT15_12_DIO12_BITN 0
+#define GPIO_DOUT15_12_DIO12_M 0x00000001
+#define GPIO_DOUT15_12_DIO12_S 0
+
+//*****************************************************************************
+//
+// Register: GPIO_O_DOUT19_16
+//
+//*****************************************************************************
+// Field: [24] DIO19
+//
+// Sets the state of the pin that is configured as DIO#19, if the corresponding
+// DOE31_0 bitfield is set.
+#define GPIO_DOUT19_16_DIO19 0x01000000
+#define GPIO_DOUT19_16_DIO19_BITN 24
+#define GPIO_DOUT19_16_DIO19_M 0x01000000
+#define GPIO_DOUT19_16_DIO19_S 24
+
+// Field: [16] DIO18
+//
+// Sets the state of the pin that is configured as DIO#18, if the corresponding
+// DOE31_0 bitfield is set.
+#define GPIO_DOUT19_16_DIO18 0x00010000
+#define GPIO_DOUT19_16_DIO18_BITN 16
+#define GPIO_DOUT19_16_DIO18_M 0x00010000
+#define GPIO_DOUT19_16_DIO18_S 16
+
+// Field: [8] DIO17
+//
+// Sets the state of the pin that is configured as DIO#17, if the corresponding
+// DOE31_0 bitfield is set.
+#define GPIO_DOUT19_16_DIO17 0x00000100
+#define GPIO_DOUT19_16_DIO17_BITN 8
+#define GPIO_DOUT19_16_DIO17_M 0x00000100
+#define GPIO_DOUT19_16_DIO17_S 8
+
+// Field: [0] DIO16
+//
+// Sets the state of the pin that is configured as DIO#16, if the corresponding
+// DOE31_0 bitfield is set.
+#define GPIO_DOUT19_16_DIO16 0x00000001
+#define GPIO_DOUT19_16_DIO16_BITN 0
+#define GPIO_DOUT19_16_DIO16_M 0x00000001
+#define GPIO_DOUT19_16_DIO16_S 0
+
+//*****************************************************************************
+//
+// Register: GPIO_O_DOUT23_20
+//
+//*****************************************************************************
+// Field: [24] DIO23
+//
+// Sets the state of the pin that is configured as DIO#23, if the corresponding
+// DOE31_0 bitfield is set.
+#define GPIO_DOUT23_20_DIO23 0x01000000
+#define GPIO_DOUT23_20_DIO23_BITN 24
+#define GPIO_DOUT23_20_DIO23_M 0x01000000
+#define GPIO_DOUT23_20_DIO23_S 24
+
+// Field: [16] DIO22
+//
+// Sets the state of the pin that is configured as DIO#22, if the corresponding
+// DOE31_0 bitfield is set.
+#define GPIO_DOUT23_20_DIO22 0x00010000
+#define GPIO_DOUT23_20_DIO22_BITN 16
+#define GPIO_DOUT23_20_DIO22_M 0x00010000
+#define GPIO_DOUT23_20_DIO22_S 16
+
+// Field: [8] DIO21
+//
+// Sets the state of the pin that is configured as DIO#21, if the corresponding
+// DOE31_0 bitfield is set.
+#define GPIO_DOUT23_20_DIO21 0x00000100
+#define GPIO_DOUT23_20_DIO21_BITN 8
+#define GPIO_DOUT23_20_DIO21_M 0x00000100
+#define GPIO_DOUT23_20_DIO21_S 8
+
+// Field: [0] DIO20
+//
+// Sets the state of the pin that is configured as DIO#20, if the corresponding
+// DOE31_0 bitfield is set.
+#define GPIO_DOUT23_20_DIO20 0x00000001
+#define GPIO_DOUT23_20_DIO20_BITN 0
+#define GPIO_DOUT23_20_DIO20_M 0x00000001
+#define GPIO_DOUT23_20_DIO20_S 0
+
+//*****************************************************************************
+//
+// Register: GPIO_O_DOUT27_24
+//
+//*****************************************************************************
+// Field: [24] DIO27
+//
+// Sets the state of the pin that is configured as DIO#27, if the corresponding
+// DOE31_0 bitfield is set.
+#define GPIO_DOUT27_24_DIO27 0x01000000
+#define GPIO_DOUT27_24_DIO27_BITN 24
+#define GPIO_DOUT27_24_DIO27_M 0x01000000
+#define GPIO_DOUT27_24_DIO27_S 24
+
+// Field: [16] DIO26
+//
+// Sets the state of the pin that is configured as DIO#26, if the corresponding
+// DOE31_0 bitfield is set.
+#define GPIO_DOUT27_24_DIO26 0x00010000
+#define GPIO_DOUT27_24_DIO26_BITN 16
+#define GPIO_DOUT27_24_DIO26_M 0x00010000
+#define GPIO_DOUT27_24_DIO26_S 16
+
+// Field: [8] DIO25
+//
+// Sets the state of the pin that is configured as DIO#25, if the corresponding
+// DOE31_0 bitfield is set.
+#define GPIO_DOUT27_24_DIO25 0x00000100
+#define GPIO_DOUT27_24_DIO25_BITN 8
+#define GPIO_DOUT27_24_DIO25_M 0x00000100
+#define GPIO_DOUT27_24_DIO25_S 8
+
+// Field: [0] DIO24
+//
+// Sets the state of the pin that is configured as DIO#24, if the corresponding
+// DOE31_0 bitfield is set.
+#define GPIO_DOUT27_24_DIO24 0x00000001
+#define GPIO_DOUT27_24_DIO24_BITN 0
+#define GPIO_DOUT27_24_DIO24_M 0x00000001
+#define GPIO_DOUT27_24_DIO24_S 0
+
+//*****************************************************************************
+//
+// Register: GPIO_O_DOUT31_28
+//
+//*****************************************************************************
+// Field: [24] DIO31
+//
+// Sets the state of the pin that is configured as DIO#31, if the corresponding
+// DOE31_0 bitfield is set.
+#define GPIO_DOUT31_28_DIO31 0x01000000
+#define GPIO_DOUT31_28_DIO31_BITN 24
+#define GPIO_DOUT31_28_DIO31_M 0x01000000
+#define GPIO_DOUT31_28_DIO31_S 24
+
+// Field: [16] DIO30
+//
+// Sets the state of the pin that is configured as DIO#30, if the corresponding
+// DOE31_0 bitfield is set.
+#define GPIO_DOUT31_28_DIO30 0x00010000
+#define GPIO_DOUT31_28_DIO30_BITN 16
+#define GPIO_DOUT31_28_DIO30_M 0x00010000
+#define GPIO_DOUT31_28_DIO30_S 16
+
+// Field: [8] DIO29
+//
+// Sets the state of the pin that is configured as DIO#29, if the corresponding
+// DOE31_0 bitfield is set.
+#define GPIO_DOUT31_28_DIO29 0x00000100
+#define GPIO_DOUT31_28_DIO29_BITN 8
+#define GPIO_DOUT31_28_DIO29_M 0x00000100
+#define GPIO_DOUT31_28_DIO29_S 8
+
+// Field: [0] DIO28
+//
+// Sets the state of the pin that is configured as DIO#28, if the corresponding
+// DOE31_0 bitfield is set.
+#define GPIO_DOUT31_28_DIO28 0x00000001
+#define GPIO_DOUT31_28_DIO28_BITN 0
+#define GPIO_DOUT31_28_DIO28_M 0x00000001
+#define GPIO_DOUT31_28_DIO28_S 0
+
+//*****************************************************************************
+//
+// Register: GPIO_O_DOUT31_0
+//
+//*****************************************************************************
+// Field: [31] DIO31
+//
+// Data output for DIO 31
+#define GPIO_DOUT31_0_DIO31 0x80000000
+#define GPIO_DOUT31_0_DIO31_BITN 31
+#define GPIO_DOUT31_0_DIO31_M 0x80000000
+#define GPIO_DOUT31_0_DIO31_S 31
+
+// Field: [30] DIO30
+//
+// Data output for DIO 30
+#define GPIO_DOUT31_0_DIO30 0x40000000
+#define GPIO_DOUT31_0_DIO30_BITN 30
+#define GPIO_DOUT31_0_DIO30_M 0x40000000
+#define GPIO_DOUT31_0_DIO30_S 30
+
+// Field: [29] DIO29
+//
+// Data output for DIO 29
+#define GPIO_DOUT31_0_DIO29 0x20000000
+#define GPIO_DOUT31_0_DIO29_BITN 29
+#define GPIO_DOUT31_0_DIO29_M 0x20000000
+#define GPIO_DOUT31_0_DIO29_S 29
+
+// Field: [28] DIO28
+//
+// Data output for DIO 28
+#define GPIO_DOUT31_0_DIO28 0x10000000
+#define GPIO_DOUT31_0_DIO28_BITN 28
+#define GPIO_DOUT31_0_DIO28_M 0x10000000
+#define GPIO_DOUT31_0_DIO28_S 28
+
+// Field: [27] DIO27
+//
+// Data output for DIO 27
+#define GPIO_DOUT31_0_DIO27 0x08000000
+#define GPIO_DOUT31_0_DIO27_BITN 27
+#define GPIO_DOUT31_0_DIO27_M 0x08000000
+#define GPIO_DOUT31_0_DIO27_S 27
+
+// Field: [26] DIO26
+//
+// Data output for DIO 26
+#define GPIO_DOUT31_0_DIO26 0x04000000
+#define GPIO_DOUT31_0_DIO26_BITN 26
+#define GPIO_DOUT31_0_DIO26_M 0x04000000
+#define GPIO_DOUT31_0_DIO26_S 26
+
+// Field: [25] DIO25
+//
+// Data output for DIO 25
+#define GPIO_DOUT31_0_DIO25 0x02000000
+#define GPIO_DOUT31_0_DIO25_BITN 25
+#define GPIO_DOUT31_0_DIO25_M 0x02000000
+#define GPIO_DOUT31_0_DIO25_S 25
+
+// Field: [24] DIO24
+//
+// Data output for DIO 24
+#define GPIO_DOUT31_0_DIO24 0x01000000
+#define GPIO_DOUT31_0_DIO24_BITN 24
+#define GPIO_DOUT31_0_DIO24_M 0x01000000
+#define GPIO_DOUT31_0_DIO24_S 24
+
+// Field: [23] DIO23
+//
+// Data output for DIO 23
+#define GPIO_DOUT31_0_DIO23 0x00800000
+#define GPIO_DOUT31_0_DIO23_BITN 23
+#define GPIO_DOUT31_0_DIO23_M 0x00800000
+#define GPIO_DOUT31_0_DIO23_S 23
+
+// Field: [22] DIO22
+//
+// Data output for DIO 22
+#define GPIO_DOUT31_0_DIO22 0x00400000
+#define GPIO_DOUT31_0_DIO22_BITN 22
+#define GPIO_DOUT31_0_DIO22_M 0x00400000
+#define GPIO_DOUT31_0_DIO22_S 22
+
+// Field: [21] DIO21
+//
+// Data output for DIO 21
+#define GPIO_DOUT31_0_DIO21 0x00200000
+#define GPIO_DOUT31_0_DIO21_BITN 21
+#define GPIO_DOUT31_0_DIO21_M 0x00200000
+#define GPIO_DOUT31_0_DIO21_S 21
+
+// Field: [20] DIO20
+//
+// Data output for DIO 20
+#define GPIO_DOUT31_0_DIO20 0x00100000
+#define GPIO_DOUT31_0_DIO20_BITN 20
+#define GPIO_DOUT31_0_DIO20_M 0x00100000
+#define GPIO_DOUT31_0_DIO20_S 20
+
+// Field: [19] DIO19
+//
+// Data output for DIO 19
+#define GPIO_DOUT31_0_DIO19 0x00080000
+#define GPIO_DOUT31_0_DIO19_BITN 19
+#define GPIO_DOUT31_0_DIO19_M 0x00080000
+#define GPIO_DOUT31_0_DIO19_S 19
+
+// Field: [18] DIO18
+//
+// Data output for DIO 18
+#define GPIO_DOUT31_0_DIO18 0x00040000
+#define GPIO_DOUT31_0_DIO18_BITN 18
+#define GPIO_DOUT31_0_DIO18_M 0x00040000
+#define GPIO_DOUT31_0_DIO18_S 18
+
+// Field: [17] DIO17
+//
+// Data output for DIO 17
+#define GPIO_DOUT31_0_DIO17 0x00020000
+#define GPIO_DOUT31_0_DIO17_BITN 17
+#define GPIO_DOUT31_0_DIO17_M 0x00020000
+#define GPIO_DOUT31_0_DIO17_S 17
+
+// Field: [16] DIO16
+//
+// Data output for DIO 16
+#define GPIO_DOUT31_0_DIO16 0x00010000
+#define GPIO_DOUT31_0_DIO16_BITN 16
+#define GPIO_DOUT31_0_DIO16_M 0x00010000
+#define GPIO_DOUT31_0_DIO16_S 16
+
+// Field: [15] DIO15
+//
+// Data output for DIO 15
+#define GPIO_DOUT31_0_DIO15 0x00008000
+#define GPIO_DOUT31_0_DIO15_BITN 15
+#define GPIO_DOUT31_0_DIO15_M 0x00008000
+#define GPIO_DOUT31_0_DIO15_S 15
+
+// Field: [14] DIO14
+//
+// Data output for DIO 14
+#define GPIO_DOUT31_0_DIO14 0x00004000
+#define GPIO_DOUT31_0_DIO14_BITN 14
+#define GPIO_DOUT31_0_DIO14_M 0x00004000
+#define GPIO_DOUT31_0_DIO14_S 14
+
+// Field: [13] DIO13
+//
+// Data output for DIO 13
+#define GPIO_DOUT31_0_DIO13 0x00002000
+#define GPIO_DOUT31_0_DIO13_BITN 13
+#define GPIO_DOUT31_0_DIO13_M 0x00002000
+#define GPIO_DOUT31_0_DIO13_S 13
+
+// Field: [12] DIO12
+//
+// Data output for DIO 12
+#define GPIO_DOUT31_0_DIO12 0x00001000
+#define GPIO_DOUT31_0_DIO12_BITN 12
+#define GPIO_DOUT31_0_DIO12_M 0x00001000
+#define GPIO_DOUT31_0_DIO12_S 12
+
+// Field: [11] DIO11
+//
+// Data output for DIO 11
+#define GPIO_DOUT31_0_DIO11 0x00000800
+#define GPIO_DOUT31_0_DIO11_BITN 11
+#define GPIO_DOUT31_0_DIO11_M 0x00000800
+#define GPIO_DOUT31_0_DIO11_S 11
+
+// Field: [10] DIO10
+//
+// Data output for DIO 10
+#define GPIO_DOUT31_0_DIO10 0x00000400
+#define GPIO_DOUT31_0_DIO10_BITN 10
+#define GPIO_DOUT31_0_DIO10_M 0x00000400
+#define GPIO_DOUT31_0_DIO10_S 10
+
+// Field: [9] DIO9
+//
+// Data output for DIO 9
+#define GPIO_DOUT31_0_DIO9 0x00000200
+#define GPIO_DOUT31_0_DIO9_BITN 9
+#define GPIO_DOUT31_0_DIO9_M 0x00000200
+#define GPIO_DOUT31_0_DIO9_S 9
+
+// Field: [8] DIO8
+//
+// Data output for DIO 8
+#define GPIO_DOUT31_0_DIO8 0x00000100
+#define GPIO_DOUT31_0_DIO8_BITN 8
+#define GPIO_DOUT31_0_DIO8_M 0x00000100
+#define GPIO_DOUT31_0_DIO8_S 8
+
+// Field: [7] DIO7
+//
+// Data output for DIO 7
+#define GPIO_DOUT31_0_DIO7 0x00000080
+#define GPIO_DOUT31_0_DIO7_BITN 7
+#define GPIO_DOUT31_0_DIO7_M 0x00000080
+#define GPIO_DOUT31_0_DIO7_S 7
+
+// Field: [6] DIO6
+//
+// Data output for DIO 6
+#define GPIO_DOUT31_0_DIO6 0x00000040
+#define GPIO_DOUT31_0_DIO6_BITN 6
+#define GPIO_DOUT31_0_DIO6_M 0x00000040
+#define GPIO_DOUT31_0_DIO6_S 6
+
+// Field: [5] DIO5
+//
+// Data output for DIO 5
+#define GPIO_DOUT31_0_DIO5 0x00000020
+#define GPIO_DOUT31_0_DIO5_BITN 5
+#define GPIO_DOUT31_0_DIO5_M 0x00000020
+#define GPIO_DOUT31_0_DIO5_S 5
+
+// Field: [4] DIO4
+//
+// Data output for DIO 4
+#define GPIO_DOUT31_0_DIO4 0x00000010
+#define GPIO_DOUT31_0_DIO4_BITN 4
+#define GPIO_DOUT31_0_DIO4_M 0x00000010
+#define GPIO_DOUT31_0_DIO4_S 4
+
+// Field: [3] DIO3
+//
+// Data output for DIO 3
+#define GPIO_DOUT31_0_DIO3 0x00000008
+#define GPIO_DOUT31_0_DIO3_BITN 3
+#define GPIO_DOUT31_0_DIO3_M 0x00000008
+#define GPIO_DOUT31_0_DIO3_S 3
+
+// Field: [2] DIO2
+//
+// Data output for DIO 2
+#define GPIO_DOUT31_0_DIO2 0x00000004
+#define GPIO_DOUT31_0_DIO2_BITN 2
+#define GPIO_DOUT31_0_DIO2_M 0x00000004
+#define GPIO_DOUT31_0_DIO2_S 2
+
+// Field: [1] DIO1
+//
+// Data output for DIO 1
+#define GPIO_DOUT31_0_DIO1 0x00000002
+#define GPIO_DOUT31_0_DIO1_BITN 1
+#define GPIO_DOUT31_0_DIO1_M 0x00000002
+#define GPIO_DOUT31_0_DIO1_S 1
+
+// Field: [0] DIO0
+//
+// Data output for DIO 0
+#define GPIO_DOUT31_0_DIO0 0x00000001
+#define GPIO_DOUT31_0_DIO0_BITN 0
+#define GPIO_DOUT31_0_DIO0_M 0x00000001
+#define GPIO_DOUT31_0_DIO0_S 0
+
+//*****************************************************************************
+//
+// Register: GPIO_O_DOUTSET31_0
+//
+//*****************************************************************************
+// Field: [31] DIO31
+//
+// Set bit 31
+#define GPIO_DOUTSET31_0_DIO31 0x80000000
+#define GPIO_DOUTSET31_0_DIO31_BITN 31
+#define GPIO_DOUTSET31_0_DIO31_M 0x80000000
+#define GPIO_DOUTSET31_0_DIO31_S 31
+
+// Field: [30] DIO30
+//
+// Set bit 30
+#define GPIO_DOUTSET31_0_DIO30 0x40000000
+#define GPIO_DOUTSET31_0_DIO30_BITN 30
+#define GPIO_DOUTSET31_0_DIO30_M 0x40000000
+#define GPIO_DOUTSET31_0_DIO30_S 30
+
+// Field: [29] DIO29
+//
+// Set bit 29
+#define GPIO_DOUTSET31_0_DIO29 0x20000000
+#define GPIO_DOUTSET31_0_DIO29_BITN 29
+#define GPIO_DOUTSET31_0_DIO29_M 0x20000000
+#define GPIO_DOUTSET31_0_DIO29_S 29
+
+// Field: [28] DIO28
+//
+// Set bit 28
+#define GPIO_DOUTSET31_0_DIO28 0x10000000
+#define GPIO_DOUTSET31_0_DIO28_BITN 28
+#define GPIO_DOUTSET31_0_DIO28_M 0x10000000
+#define GPIO_DOUTSET31_0_DIO28_S 28
+
+// Field: [27] DIO27
+//
+// Set bit 27
+#define GPIO_DOUTSET31_0_DIO27 0x08000000
+#define GPIO_DOUTSET31_0_DIO27_BITN 27
+#define GPIO_DOUTSET31_0_DIO27_M 0x08000000
+#define GPIO_DOUTSET31_0_DIO27_S 27
+
+// Field: [26] DIO26
+//
+// Set bit 26
+#define GPIO_DOUTSET31_0_DIO26 0x04000000
+#define GPIO_DOUTSET31_0_DIO26_BITN 26
+#define GPIO_DOUTSET31_0_DIO26_M 0x04000000
+#define GPIO_DOUTSET31_0_DIO26_S 26
+
+// Field: [25] DIO25
+//
+// Set bit 25
+#define GPIO_DOUTSET31_0_DIO25 0x02000000
+#define GPIO_DOUTSET31_0_DIO25_BITN 25
+#define GPIO_DOUTSET31_0_DIO25_M 0x02000000
+#define GPIO_DOUTSET31_0_DIO25_S 25
+
+// Field: [24] DIO24
+//
+// Set bit 24
+#define GPIO_DOUTSET31_0_DIO24 0x01000000
+#define GPIO_DOUTSET31_0_DIO24_BITN 24
+#define GPIO_DOUTSET31_0_DIO24_M 0x01000000
+#define GPIO_DOUTSET31_0_DIO24_S 24
+
+// Field: [23] DIO23
+//
+// Set bit 23
+#define GPIO_DOUTSET31_0_DIO23 0x00800000
+#define GPIO_DOUTSET31_0_DIO23_BITN 23
+#define GPIO_DOUTSET31_0_DIO23_M 0x00800000
+#define GPIO_DOUTSET31_0_DIO23_S 23
+
+// Field: [22] DIO22
+//
+// Set bit 22
+#define GPIO_DOUTSET31_0_DIO22 0x00400000
+#define GPIO_DOUTSET31_0_DIO22_BITN 22
+#define GPIO_DOUTSET31_0_DIO22_M 0x00400000
+#define GPIO_DOUTSET31_0_DIO22_S 22
+
+// Field: [21] DIO21
+//
+// Set bit 21
+#define GPIO_DOUTSET31_0_DIO21 0x00200000
+#define GPIO_DOUTSET31_0_DIO21_BITN 21
+#define GPIO_DOUTSET31_0_DIO21_M 0x00200000
+#define GPIO_DOUTSET31_0_DIO21_S 21
+
+// Field: [20] DIO20
+//
+// Set bit 20
+#define GPIO_DOUTSET31_0_DIO20 0x00100000
+#define GPIO_DOUTSET31_0_DIO20_BITN 20
+#define GPIO_DOUTSET31_0_DIO20_M 0x00100000
+#define GPIO_DOUTSET31_0_DIO20_S 20
+
+// Field: [19] DIO19
+//
+// Set bit 19
+#define GPIO_DOUTSET31_0_DIO19 0x00080000
+#define GPIO_DOUTSET31_0_DIO19_BITN 19
+#define GPIO_DOUTSET31_0_DIO19_M 0x00080000
+#define GPIO_DOUTSET31_0_DIO19_S 19
+
+// Field: [18] DIO18
+//
+// Set bit 18
+#define GPIO_DOUTSET31_0_DIO18 0x00040000
+#define GPIO_DOUTSET31_0_DIO18_BITN 18
+#define GPIO_DOUTSET31_0_DIO18_M 0x00040000
+#define GPIO_DOUTSET31_0_DIO18_S 18
+
+// Field: [17] DIO17
+//
+// Set bit 17
+#define GPIO_DOUTSET31_0_DIO17 0x00020000
+#define GPIO_DOUTSET31_0_DIO17_BITN 17
+#define GPIO_DOUTSET31_0_DIO17_M 0x00020000
+#define GPIO_DOUTSET31_0_DIO17_S 17
+
+// Field: [16] DIO16
+//
+// Set bit 16
+#define GPIO_DOUTSET31_0_DIO16 0x00010000
+#define GPIO_DOUTSET31_0_DIO16_BITN 16
+#define GPIO_DOUTSET31_0_DIO16_M 0x00010000
+#define GPIO_DOUTSET31_0_DIO16_S 16
+
+// Field: [15] DIO15
+//
+// Set bit 15
+#define GPIO_DOUTSET31_0_DIO15 0x00008000
+#define GPIO_DOUTSET31_0_DIO15_BITN 15
+#define GPIO_DOUTSET31_0_DIO15_M 0x00008000
+#define GPIO_DOUTSET31_0_DIO15_S 15
+
+// Field: [14] DIO14
+//
+// Set bit 14
+#define GPIO_DOUTSET31_0_DIO14 0x00004000
+#define GPIO_DOUTSET31_0_DIO14_BITN 14
+#define GPIO_DOUTSET31_0_DIO14_M 0x00004000
+#define GPIO_DOUTSET31_0_DIO14_S 14
+
+// Field: [13] DIO13
+//
+// Set bit 13
+#define GPIO_DOUTSET31_0_DIO13 0x00002000
+#define GPIO_DOUTSET31_0_DIO13_BITN 13
+#define GPIO_DOUTSET31_0_DIO13_M 0x00002000
+#define GPIO_DOUTSET31_0_DIO13_S 13
+
+// Field: [12] DIO12
+//
+// Set bit 12
+#define GPIO_DOUTSET31_0_DIO12 0x00001000
+#define GPIO_DOUTSET31_0_DIO12_BITN 12
+#define GPIO_DOUTSET31_0_DIO12_M 0x00001000
+#define GPIO_DOUTSET31_0_DIO12_S 12
+
+// Field: [11] DIO11
+//
+// Set bit 11
+#define GPIO_DOUTSET31_0_DIO11 0x00000800
+#define GPIO_DOUTSET31_0_DIO11_BITN 11
+#define GPIO_DOUTSET31_0_DIO11_M 0x00000800
+#define GPIO_DOUTSET31_0_DIO11_S 11
+
+// Field: [10] DIO10
+//
+// Set bit 10
+#define GPIO_DOUTSET31_0_DIO10 0x00000400
+#define GPIO_DOUTSET31_0_DIO10_BITN 10
+#define GPIO_DOUTSET31_0_DIO10_M 0x00000400
+#define GPIO_DOUTSET31_0_DIO10_S 10
+
+// Field: [9] DIO9
+//
+// Set bit 9
+#define GPIO_DOUTSET31_0_DIO9 0x00000200
+#define GPIO_DOUTSET31_0_DIO9_BITN 9
+#define GPIO_DOUTSET31_0_DIO9_M 0x00000200
+#define GPIO_DOUTSET31_0_DIO9_S 9
+
+// Field: [8] DIO8
+//
+// Set bit 8
+#define GPIO_DOUTSET31_0_DIO8 0x00000100
+#define GPIO_DOUTSET31_0_DIO8_BITN 8
+#define GPIO_DOUTSET31_0_DIO8_M 0x00000100
+#define GPIO_DOUTSET31_0_DIO8_S 8
+
+// Field: [7] DIO7
+//
+// Set bit 7
+#define GPIO_DOUTSET31_0_DIO7 0x00000080
+#define GPIO_DOUTSET31_0_DIO7_BITN 7
+#define GPIO_DOUTSET31_0_DIO7_M 0x00000080
+#define GPIO_DOUTSET31_0_DIO7_S 7
+
+// Field: [6] DIO6
+//
+// Set bit 6
+#define GPIO_DOUTSET31_0_DIO6 0x00000040
+#define GPIO_DOUTSET31_0_DIO6_BITN 6
+#define GPIO_DOUTSET31_0_DIO6_M 0x00000040
+#define GPIO_DOUTSET31_0_DIO6_S 6
+
+// Field: [5] DIO5
+//
+// Set bit 5
+#define GPIO_DOUTSET31_0_DIO5 0x00000020
+#define GPIO_DOUTSET31_0_DIO5_BITN 5
+#define GPIO_DOUTSET31_0_DIO5_M 0x00000020
+#define GPIO_DOUTSET31_0_DIO5_S 5
+
+// Field: [4] DIO4
+//
+// Set bit 4
+#define GPIO_DOUTSET31_0_DIO4 0x00000010
+#define GPIO_DOUTSET31_0_DIO4_BITN 4
+#define GPIO_DOUTSET31_0_DIO4_M 0x00000010
+#define GPIO_DOUTSET31_0_DIO4_S 4
+
+// Field: [3] DIO3
+//
+// Set bit 3
+#define GPIO_DOUTSET31_0_DIO3 0x00000008
+#define GPIO_DOUTSET31_0_DIO3_BITN 3
+#define GPIO_DOUTSET31_0_DIO3_M 0x00000008
+#define GPIO_DOUTSET31_0_DIO3_S 3
+
+// Field: [2] DIO2
+//
+// Set bit 2
+#define GPIO_DOUTSET31_0_DIO2 0x00000004
+#define GPIO_DOUTSET31_0_DIO2_BITN 2
+#define GPIO_DOUTSET31_0_DIO2_M 0x00000004
+#define GPIO_DOUTSET31_0_DIO2_S 2
+
+// Field: [1] DIO1
+//
+// Set bit 1
+#define GPIO_DOUTSET31_0_DIO1 0x00000002
+#define GPIO_DOUTSET31_0_DIO1_BITN 1
+#define GPIO_DOUTSET31_0_DIO1_M 0x00000002
+#define GPIO_DOUTSET31_0_DIO1_S 1
+
+// Field: [0] DIO0
+//
+// Set bit 0
+#define GPIO_DOUTSET31_0_DIO0 0x00000001
+#define GPIO_DOUTSET31_0_DIO0_BITN 0
+#define GPIO_DOUTSET31_0_DIO0_M 0x00000001
+#define GPIO_DOUTSET31_0_DIO0_S 0
+
+//*****************************************************************************
+//
+// Register: GPIO_O_DOUTCLR31_0
+//
+//*****************************************************************************
+// Field: [31] DIO31
+//
+// Clears bit 31
+#define GPIO_DOUTCLR31_0_DIO31 0x80000000
+#define GPIO_DOUTCLR31_0_DIO31_BITN 31
+#define GPIO_DOUTCLR31_0_DIO31_M 0x80000000
+#define GPIO_DOUTCLR31_0_DIO31_S 31
+
+// Field: [30] DIO30
+//
+// Clears bit 30
+#define GPIO_DOUTCLR31_0_DIO30 0x40000000
+#define GPIO_DOUTCLR31_0_DIO30_BITN 30
+#define GPIO_DOUTCLR31_0_DIO30_M 0x40000000
+#define GPIO_DOUTCLR31_0_DIO30_S 30
+
+// Field: [29] DIO29
+//
+// Clears bit 29
+#define GPIO_DOUTCLR31_0_DIO29 0x20000000
+#define GPIO_DOUTCLR31_0_DIO29_BITN 29
+#define GPIO_DOUTCLR31_0_DIO29_M 0x20000000
+#define GPIO_DOUTCLR31_0_DIO29_S 29
+
+// Field: [28] DIO28
+//
+// Clears bit 28
+#define GPIO_DOUTCLR31_0_DIO28 0x10000000
+#define GPIO_DOUTCLR31_0_DIO28_BITN 28
+#define GPIO_DOUTCLR31_0_DIO28_M 0x10000000
+#define GPIO_DOUTCLR31_0_DIO28_S 28
+
+// Field: [27] DIO27
+//
+// Clears bit 27
+#define GPIO_DOUTCLR31_0_DIO27 0x08000000
+#define GPIO_DOUTCLR31_0_DIO27_BITN 27
+#define GPIO_DOUTCLR31_0_DIO27_M 0x08000000
+#define GPIO_DOUTCLR31_0_DIO27_S 27
+
+// Field: [26] DIO26
+//
+// Clears bit 26
+#define GPIO_DOUTCLR31_0_DIO26 0x04000000
+#define GPIO_DOUTCLR31_0_DIO26_BITN 26
+#define GPIO_DOUTCLR31_0_DIO26_M 0x04000000
+#define GPIO_DOUTCLR31_0_DIO26_S 26
+
+// Field: [25] DIO25
+//
+// Clears bit 25
+#define GPIO_DOUTCLR31_0_DIO25 0x02000000
+#define GPIO_DOUTCLR31_0_DIO25_BITN 25
+#define GPIO_DOUTCLR31_0_DIO25_M 0x02000000
+#define GPIO_DOUTCLR31_0_DIO25_S 25
+
+// Field: [24] DIO24
+//
+// Clears bit 24
+#define GPIO_DOUTCLR31_0_DIO24 0x01000000
+#define GPIO_DOUTCLR31_0_DIO24_BITN 24
+#define GPIO_DOUTCLR31_0_DIO24_M 0x01000000
+#define GPIO_DOUTCLR31_0_DIO24_S 24
+
+// Field: [23] DIO23
+//
+// Clears bit 23
+#define GPIO_DOUTCLR31_0_DIO23 0x00800000
+#define GPIO_DOUTCLR31_0_DIO23_BITN 23
+#define GPIO_DOUTCLR31_0_DIO23_M 0x00800000
+#define GPIO_DOUTCLR31_0_DIO23_S 23
+
+// Field: [22] DIO22
+//
+// Clears bit 22
+#define GPIO_DOUTCLR31_0_DIO22 0x00400000
+#define GPIO_DOUTCLR31_0_DIO22_BITN 22
+#define GPIO_DOUTCLR31_0_DIO22_M 0x00400000
+#define GPIO_DOUTCLR31_0_DIO22_S 22
+
+// Field: [21] DIO21
+//
+// Clears bit 21
+#define GPIO_DOUTCLR31_0_DIO21 0x00200000
+#define GPIO_DOUTCLR31_0_DIO21_BITN 21
+#define GPIO_DOUTCLR31_0_DIO21_M 0x00200000
+#define GPIO_DOUTCLR31_0_DIO21_S 21
+
+// Field: [20] DIO20
+//
+// Clears bit 20
+#define GPIO_DOUTCLR31_0_DIO20 0x00100000
+#define GPIO_DOUTCLR31_0_DIO20_BITN 20
+#define GPIO_DOUTCLR31_0_DIO20_M 0x00100000
+#define GPIO_DOUTCLR31_0_DIO20_S 20
+
+// Field: [19] DIO19
+//
+// Clears bit 19
+#define GPIO_DOUTCLR31_0_DIO19 0x00080000
+#define GPIO_DOUTCLR31_0_DIO19_BITN 19
+#define GPIO_DOUTCLR31_0_DIO19_M 0x00080000
+#define GPIO_DOUTCLR31_0_DIO19_S 19
+
+// Field: [18] DIO18
+//
+// Clears bit 18
+#define GPIO_DOUTCLR31_0_DIO18 0x00040000
+#define GPIO_DOUTCLR31_0_DIO18_BITN 18
+#define GPIO_DOUTCLR31_0_DIO18_M 0x00040000
+#define GPIO_DOUTCLR31_0_DIO18_S 18
+
+// Field: [17] DIO17
+//
+// Clears bit 17
+#define GPIO_DOUTCLR31_0_DIO17 0x00020000
+#define GPIO_DOUTCLR31_0_DIO17_BITN 17
+#define GPIO_DOUTCLR31_0_DIO17_M 0x00020000
+#define GPIO_DOUTCLR31_0_DIO17_S 17
+
+// Field: [16] DIO16
+//
+// Clears bit 16
+#define GPIO_DOUTCLR31_0_DIO16 0x00010000
+#define GPIO_DOUTCLR31_0_DIO16_BITN 16
+#define GPIO_DOUTCLR31_0_DIO16_M 0x00010000
+#define GPIO_DOUTCLR31_0_DIO16_S 16
+
+// Field: [15] DIO15
+//
+// Clears bit 15
+#define GPIO_DOUTCLR31_0_DIO15 0x00008000
+#define GPIO_DOUTCLR31_0_DIO15_BITN 15
+#define GPIO_DOUTCLR31_0_DIO15_M 0x00008000
+#define GPIO_DOUTCLR31_0_DIO15_S 15
+
+// Field: [14] DIO14
+//
+// Clears bit 14
+#define GPIO_DOUTCLR31_0_DIO14 0x00004000
+#define GPIO_DOUTCLR31_0_DIO14_BITN 14
+#define GPIO_DOUTCLR31_0_DIO14_M 0x00004000
+#define GPIO_DOUTCLR31_0_DIO14_S 14
+
+// Field: [13] DIO13
+//
+// Clears bit 13
+#define GPIO_DOUTCLR31_0_DIO13 0x00002000
+#define GPIO_DOUTCLR31_0_DIO13_BITN 13
+#define GPIO_DOUTCLR31_0_DIO13_M 0x00002000
+#define GPIO_DOUTCLR31_0_DIO13_S 13
+
+// Field: [12] DIO12
+//
+// Clears bit 12
+#define GPIO_DOUTCLR31_0_DIO12 0x00001000
+#define GPIO_DOUTCLR31_0_DIO12_BITN 12
+#define GPIO_DOUTCLR31_0_DIO12_M 0x00001000
+#define GPIO_DOUTCLR31_0_DIO12_S 12
+
+// Field: [11] DIO11
+//
+// Clears bit 11
+#define GPIO_DOUTCLR31_0_DIO11 0x00000800
+#define GPIO_DOUTCLR31_0_DIO11_BITN 11
+#define GPIO_DOUTCLR31_0_DIO11_M 0x00000800
+#define GPIO_DOUTCLR31_0_DIO11_S 11
+
+// Field: [10] DIO10
+//
+// Clears bit 10
+#define GPIO_DOUTCLR31_0_DIO10 0x00000400
+#define GPIO_DOUTCLR31_0_DIO10_BITN 10
+#define GPIO_DOUTCLR31_0_DIO10_M 0x00000400
+#define GPIO_DOUTCLR31_0_DIO10_S 10
+
+// Field: [9] DIO9
+//
+// Clears bit 9
+#define GPIO_DOUTCLR31_0_DIO9 0x00000200
+#define GPIO_DOUTCLR31_0_DIO9_BITN 9
+#define GPIO_DOUTCLR31_0_DIO9_M 0x00000200
+#define GPIO_DOUTCLR31_0_DIO9_S 9
+
+// Field: [8] DIO8
+//
+// Clears bit 8
+#define GPIO_DOUTCLR31_0_DIO8 0x00000100
+#define GPIO_DOUTCLR31_0_DIO8_BITN 8
+#define GPIO_DOUTCLR31_0_DIO8_M 0x00000100
+#define GPIO_DOUTCLR31_0_DIO8_S 8
+
+// Field: [7] DIO7
+//
+// Clears bit 7
+#define GPIO_DOUTCLR31_0_DIO7 0x00000080
+#define GPIO_DOUTCLR31_0_DIO7_BITN 7
+#define GPIO_DOUTCLR31_0_DIO7_M 0x00000080
+#define GPIO_DOUTCLR31_0_DIO7_S 7
+
+// Field: [6] DIO6
+//
+// Clears bit 6
+#define GPIO_DOUTCLR31_0_DIO6 0x00000040
+#define GPIO_DOUTCLR31_0_DIO6_BITN 6
+#define GPIO_DOUTCLR31_0_DIO6_M 0x00000040
+#define GPIO_DOUTCLR31_0_DIO6_S 6
+
+// Field: [5] DIO5
+//
+// Clears bit 5
+#define GPIO_DOUTCLR31_0_DIO5 0x00000020
+#define GPIO_DOUTCLR31_0_DIO5_BITN 5
+#define GPIO_DOUTCLR31_0_DIO5_M 0x00000020
+#define GPIO_DOUTCLR31_0_DIO5_S 5
+
+// Field: [4] DIO4
+//
+// Clears bit 4
+#define GPIO_DOUTCLR31_0_DIO4 0x00000010
+#define GPIO_DOUTCLR31_0_DIO4_BITN 4
+#define GPIO_DOUTCLR31_0_DIO4_M 0x00000010
+#define GPIO_DOUTCLR31_0_DIO4_S 4
+
+// Field: [3] DIO3
+//
+// Clears bit 3
+#define GPIO_DOUTCLR31_0_DIO3 0x00000008
+#define GPIO_DOUTCLR31_0_DIO3_BITN 3
+#define GPIO_DOUTCLR31_0_DIO3_M 0x00000008
+#define GPIO_DOUTCLR31_0_DIO3_S 3
+
+// Field: [2] DIO2
+//
+// Clears bit 2
+#define GPIO_DOUTCLR31_0_DIO2 0x00000004
+#define GPIO_DOUTCLR31_0_DIO2_BITN 2
+#define GPIO_DOUTCLR31_0_DIO2_M 0x00000004
+#define GPIO_DOUTCLR31_0_DIO2_S 2
+
+// Field: [1] DIO1
+//
+// Clears bit 1
+#define GPIO_DOUTCLR31_0_DIO1 0x00000002
+#define GPIO_DOUTCLR31_0_DIO1_BITN 1
+#define GPIO_DOUTCLR31_0_DIO1_M 0x00000002
+#define GPIO_DOUTCLR31_0_DIO1_S 1
+
+// Field: [0] DIO0
+//
+// Clears bit 0
+#define GPIO_DOUTCLR31_0_DIO0 0x00000001
+#define GPIO_DOUTCLR31_0_DIO0_BITN 0
+#define GPIO_DOUTCLR31_0_DIO0_M 0x00000001
+#define GPIO_DOUTCLR31_0_DIO0_S 0
+
+//*****************************************************************************
+//
+// Register: GPIO_O_DOUTTGL31_0
+//
+//*****************************************************************************
+// Field: [31] DIO31
+//
+// Toggles bit 31
+#define GPIO_DOUTTGL31_0_DIO31 0x80000000
+#define GPIO_DOUTTGL31_0_DIO31_BITN 31
+#define GPIO_DOUTTGL31_0_DIO31_M 0x80000000
+#define GPIO_DOUTTGL31_0_DIO31_S 31
+
+// Field: [30] DIO30
+//
+// Toggles bit 30
+#define GPIO_DOUTTGL31_0_DIO30 0x40000000
+#define GPIO_DOUTTGL31_0_DIO30_BITN 30
+#define GPIO_DOUTTGL31_0_DIO30_M 0x40000000
+#define GPIO_DOUTTGL31_0_DIO30_S 30
+
+// Field: [29] DIO29
+//
+// Toggles bit 29
+#define GPIO_DOUTTGL31_0_DIO29 0x20000000
+#define GPIO_DOUTTGL31_0_DIO29_BITN 29
+#define GPIO_DOUTTGL31_0_DIO29_M 0x20000000
+#define GPIO_DOUTTGL31_0_DIO29_S 29
+
+// Field: [28] DIO28
+//
+// Toggles bit 28
+#define GPIO_DOUTTGL31_0_DIO28 0x10000000
+#define GPIO_DOUTTGL31_0_DIO28_BITN 28
+#define GPIO_DOUTTGL31_0_DIO28_M 0x10000000
+#define GPIO_DOUTTGL31_0_DIO28_S 28
+
+// Field: [27] DIO27
+//
+// Toggles bit 27
+#define GPIO_DOUTTGL31_0_DIO27 0x08000000
+#define GPIO_DOUTTGL31_0_DIO27_BITN 27
+#define GPIO_DOUTTGL31_0_DIO27_M 0x08000000
+#define GPIO_DOUTTGL31_0_DIO27_S 27
+
+// Field: [26] DIO26
+//
+// Toggles bit 26
+#define GPIO_DOUTTGL31_0_DIO26 0x04000000
+#define GPIO_DOUTTGL31_0_DIO26_BITN 26
+#define GPIO_DOUTTGL31_0_DIO26_M 0x04000000
+#define GPIO_DOUTTGL31_0_DIO26_S 26
+
+// Field: [25] DIO25
+//
+// Toggles bit 25
+#define GPIO_DOUTTGL31_0_DIO25 0x02000000
+#define GPIO_DOUTTGL31_0_DIO25_BITN 25
+#define GPIO_DOUTTGL31_0_DIO25_M 0x02000000
+#define GPIO_DOUTTGL31_0_DIO25_S 25
+
+// Field: [24] DIO24
+//
+// Toggles bit 24
+#define GPIO_DOUTTGL31_0_DIO24 0x01000000
+#define GPIO_DOUTTGL31_0_DIO24_BITN 24
+#define GPIO_DOUTTGL31_0_DIO24_M 0x01000000
+#define GPIO_DOUTTGL31_0_DIO24_S 24
+
+// Field: [23] DIO23
+//
+// Toggles bit 23
+#define GPIO_DOUTTGL31_0_DIO23 0x00800000
+#define GPIO_DOUTTGL31_0_DIO23_BITN 23
+#define GPIO_DOUTTGL31_0_DIO23_M 0x00800000
+#define GPIO_DOUTTGL31_0_DIO23_S 23
+
+// Field: [22] DIO22
+//
+// Toggles bit 22
+#define GPIO_DOUTTGL31_0_DIO22 0x00400000
+#define GPIO_DOUTTGL31_0_DIO22_BITN 22
+#define GPIO_DOUTTGL31_0_DIO22_M 0x00400000
+#define GPIO_DOUTTGL31_0_DIO22_S 22
+
+// Field: [21] DIO21
+//
+// Toggles bit 21
+#define GPIO_DOUTTGL31_0_DIO21 0x00200000
+#define GPIO_DOUTTGL31_0_DIO21_BITN 21
+#define GPIO_DOUTTGL31_0_DIO21_M 0x00200000
+#define GPIO_DOUTTGL31_0_DIO21_S 21
+
+// Field: [20] DIO20
+//
+// Toggles bit 20
+#define GPIO_DOUTTGL31_0_DIO20 0x00100000
+#define GPIO_DOUTTGL31_0_DIO20_BITN 20
+#define GPIO_DOUTTGL31_0_DIO20_M 0x00100000
+#define GPIO_DOUTTGL31_0_DIO20_S 20
+
+// Field: [19] DIO19
+//
+// Toggles bit 19
+#define GPIO_DOUTTGL31_0_DIO19 0x00080000
+#define GPIO_DOUTTGL31_0_DIO19_BITN 19
+#define GPIO_DOUTTGL31_0_DIO19_M 0x00080000
+#define GPIO_DOUTTGL31_0_DIO19_S 19
+
+// Field: [18] DIO18
+//
+// Toggles bit 18
+#define GPIO_DOUTTGL31_0_DIO18 0x00040000
+#define GPIO_DOUTTGL31_0_DIO18_BITN 18
+#define GPIO_DOUTTGL31_0_DIO18_M 0x00040000
+#define GPIO_DOUTTGL31_0_DIO18_S 18
+
+// Field: [17] DIO17
+//
+// Toggles bit 17
+#define GPIO_DOUTTGL31_0_DIO17 0x00020000
+#define GPIO_DOUTTGL31_0_DIO17_BITN 17
+#define GPIO_DOUTTGL31_0_DIO17_M 0x00020000
+#define GPIO_DOUTTGL31_0_DIO17_S 17
+
+// Field: [16] DIO16
+//
+// Toggles bit 16
+#define GPIO_DOUTTGL31_0_DIO16 0x00010000
+#define GPIO_DOUTTGL31_0_DIO16_BITN 16
+#define GPIO_DOUTTGL31_0_DIO16_M 0x00010000
+#define GPIO_DOUTTGL31_0_DIO16_S 16
+
+// Field: [15] DIO15
+//
+// Toggles bit 15
+#define GPIO_DOUTTGL31_0_DIO15 0x00008000
+#define GPIO_DOUTTGL31_0_DIO15_BITN 15
+#define GPIO_DOUTTGL31_0_DIO15_M 0x00008000
+#define GPIO_DOUTTGL31_0_DIO15_S 15
+
+// Field: [14] DIO14
+//
+// Toggles bit 14
+#define GPIO_DOUTTGL31_0_DIO14 0x00004000
+#define GPIO_DOUTTGL31_0_DIO14_BITN 14
+#define GPIO_DOUTTGL31_0_DIO14_M 0x00004000
+#define GPIO_DOUTTGL31_0_DIO14_S 14
+
+// Field: [13] DIO13
+//
+// Toggles bit 13
+#define GPIO_DOUTTGL31_0_DIO13 0x00002000
+#define GPIO_DOUTTGL31_0_DIO13_BITN 13
+#define GPIO_DOUTTGL31_0_DIO13_M 0x00002000
+#define GPIO_DOUTTGL31_0_DIO13_S 13
+
+// Field: [12] DIO12
+//
+// Toggles bit 12
+#define GPIO_DOUTTGL31_0_DIO12 0x00001000
+#define GPIO_DOUTTGL31_0_DIO12_BITN 12
+#define GPIO_DOUTTGL31_0_DIO12_M 0x00001000
+#define GPIO_DOUTTGL31_0_DIO12_S 12
+
+// Field: [11] DIO11
+//
+// Toggles bit 11
+#define GPIO_DOUTTGL31_0_DIO11 0x00000800
+#define GPIO_DOUTTGL31_0_DIO11_BITN 11
+#define GPIO_DOUTTGL31_0_DIO11_M 0x00000800
+#define GPIO_DOUTTGL31_0_DIO11_S 11
+
+// Field: [10] DIO10
+//
+// Toggles bit 10
+#define GPIO_DOUTTGL31_0_DIO10 0x00000400
+#define GPIO_DOUTTGL31_0_DIO10_BITN 10
+#define GPIO_DOUTTGL31_0_DIO10_M 0x00000400
+#define GPIO_DOUTTGL31_0_DIO10_S 10
+
+// Field: [9] DIO9
+//
+// Toggles bit 9
+#define GPIO_DOUTTGL31_0_DIO9 0x00000200
+#define GPIO_DOUTTGL31_0_DIO9_BITN 9
+#define GPIO_DOUTTGL31_0_DIO9_M 0x00000200
+#define GPIO_DOUTTGL31_0_DIO9_S 9
+
+// Field: [8] DIO8
+//
+// Toggles bit 8
+#define GPIO_DOUTTGL31_0_DIO8 0x00000100
+#define GPIO_DOUTTGL31_0_DIO8_BITN 8
+#define GPIO_DOUTTGL31_0_DIO8_M 0x00000100
+#define GPIO_DOUTTGL31_0_DIO8_S 8
+
+// Field: [7] DIO7
+//
+// Toggles bit 7
+#define GPIO_DOUTTGL31_0_DIO7 0x00000080
+#define GPIO_DOUTTGL31_0_DIO7_BITN 7
+#define GPIO_DOUTTGL31_0_DIO7_M 0x00000080
+#define GPIO_DOUTTGL31_0_DIO7_S 7
+
+// Field: [6] DIO6
+//
+// Toggles bit 6
+#define GPIO_DOUTTGL31_0_DIO6 0x00000040
+#define GPIO_DOUTTGL31_0_DIO6_BITN 6
+#define GPIO_DOUTTGL31_0_DIO6_M 0x00000040
+#define GPIO_DOUTTGL31_0_DIO6_S 6
+
+// Field: [5] DIO5
+//
+// Toggles bit 5
+#define GPIO_DOUTTGL31_0_DIO5 0x00000020
+#define GPIO_DOUTTGL31_0_DIO5_BITN 5
+#define GPIO_DOUTTGL31_0_DIO5_M 0x00000020
+#define GPIO_DOUTTGL31_0_DIO5_S 5
+
+// Field: [4] DIO4
+//
+// Toggles bit 4
+#define GPIO_DOUTTGL31_0_DIO4 0x00000010
+#define GPIO_DOUTTGL31_0_DIO4_BITN 4
+#define GPIO_DOUTTGL31_0_DIO4_M 0x00000010
+#define GPIO_DOUTTGL31_0_DIO4_S 4
+
+// Field: [3] DIO3
+//
+// Toggles bit 3
+#define GPIO_DOUTTGL31_0_DIO3 0x00000008
+#define GPIO_DOUTTGL31_0_DIO3_BITN 3
+#define GPIO_DOUTTGL31_0_DIO3_M 0x00000008
+#define GPIO_DOUTTGL31_0_DIO3_S 3
+
+// Field: [2] DIO2
+//
+// Toggles bit 2
+#define GPIO_DOUTTGL31_0_DIO2 0x00000004
+#define GPIO_DOUTTGL31_0_DIO2_BITN 2
+#define GPIO_DOUTTGL31_0_DIO2_M 0x00000004
+#define GPIO_DOUTTGL31_0_DIO2_S 2
+
+// Field: [1] DIO1
+//
+// Toggles bit 1
+#define GPIO_DOUTTGL31_0_DIO1 0x00000002
+#define GPIO_DOUTTGL31_0_DIO1_BITN 1
+#define GPIO_DOUTTGL31_0_DIO1_M 0x00000002
+#define GPIO_DOUTTGL31_0_DIO1_S 1
+
+// Field: [0] DIO0
+//
+// Toggles bit 0
+#define GPIO_DOUTTGL31_0_DIO0 0x00000001
+#define GPIO_DOUTTGL31_0_DIO0_BITN 0
+#define GPIO_DOUTTGL31_0_DIO0_M 0x00000001
+#define GPIO_DOUTTGL31_0_DIO0_S 0
+
+//*****************************************************************************
+//
+// Register: GPIO_O_DIN31_0
+//
+//*****************************************************************************
+// Field: [31] DIO31
+//
+// Data input from DIO 31
+#define GPIO_DIN31_0_DIO31 0x80000000
+#define GPIO_DIN31_0_DIO31_BITN 31
+#define GPIO_DIN31_0_DIO31_M 0x80000000
+#define GPIO_DIN31_0_DIO31_S 31
+
+// Field: [30] DIO30
+//
+// Data input from DIO 30
+#define GPIO_DIN31_0_DIO30 0x40000000
+#define GPIO_DIN31_0_DIO30_BITN 30
+#define GPIO_DIN31_0_DIO30_M 0x40000000
+#define GPIO_DIN31_0_DIO30_S 30
+
+// Field: [29] DIO29
+//
+// Data input from DIO 29
+#define GPIO_DIN31_0_DIO29 0x20000000
+#define GPIO_DIN31_0_DIO29_BITN 29
+#define GPIO_DIN31_0_DIO29_M 0x20000000
+#define GPIO_DIN31_0_DIO29_S 29
+
+// Field: [28] DIO28
+//
+// Data input from DIO 28
+#define GPIO_DIN31_0_DIO28 0x10000000
+#define GPIO_DIN31_0_DIO28_BITN 28
+#define GPIO_DIN31_0_DIO28_M 0x10000000
+#define GPIO_DIN31_0_DIO28_S 28
+
+// Field: [27] DIO27
+//
+// Data input from DIO 27
+#define GPIO_DIN31_0_DIO27 0x08000000
+#define GPIO_DIN31_0_DIO27_BITN 27
+#define GPIO_DIN31_0_DIO27_M 0x08000000
+#define GPIO_DIN31_0_DIO27_S 27
+
+// Field: [26] DIO26
+//
+// Data input from DIO 26
+#define GPIO_DIN31_0_DIO26 0x04000000
+#define GPIO_DIN31_0_DIO26_BITN 26
+#define GPIO_DIN31_0_DIO26_M 0x04000000
+#define GPIO_DIN31_0_DIO26_S 26
+
+// Field: [25] DIO25
+//
+// Data input from DIO 25
+#define GPIO_DIN31_0_DIO25 0x02000000
+#define GPIO_DIN31_0_DIO25_BITN 25
+#define GPIO_DIN31_0_DIO25_M 0x02000000
+#define GPIO_DIN31_0_DIO25_S 25
+
+// Field: [24] DIO24
+//
+// Data input from DIO 24
+#define GPIO_DIN31_0_DIO24 0x01000000
+#define GPIO_DIN31_0_DIO24_BITN 24
+#define GPIO_DIN31_0_DIO24_M 0x01000000
+#define GPIO_DIN31_0_DIO24_S 24
+
+// Field: [23] DIO23
+//
+// Data input from DIO 23
+#define GPIO_DIN31_0_DIO23 0x00800000
+#define GPIO_DIN31_0_DIO23_BITN 23
+#define GPIO_DIN31_0_DIO23_M 0x00800000
+#define GPIO_DIN31_0_DIO23_S 23
+
+// Field: [22] DIO22
+//
+// Data input from DIO 22
+#define GPIO_DIN31_0_DIO22 0x00400000
+#define GPIO_DIN31_0_DIO22_BITN 22
+#define GPIO_DIN31_0_DIO22_M 0x00400000
+#define GPIO_DIN31_0_DIO22_S 22
+
+// Field: [21] DIO21
+//
+// Data input from DIO 21
+#define GPIO_DIN31_0_DIO21 0x00200000
+#define GPIO_DIN31_0_DIO21_BITN 21
+#define GPIO_DIN31_0_DIO21_M 0x00200000
+#define GPIO_DIN31_0_DIO21_S 21
+
+// Field: [20] DIO20
+//
+// Data input from DIO 20
+#define GPIO_DIN31_0_DIO20 0x00100000
+#define GPIO_DIN31_0_DIO20_BITN 20
+#define GPIO_DIN31_0_DIO20_M 0x00100000
+#define GPIO_DIN31_0_DIO20_S 20
+
+// Field: [19] DIO19
+//
+// Data input from DIO 19
+#define GPIO_DIN31_0_DIO19 0x00080000
+#define GPIO_DIN31_0_DIO19_BITN 19
+#define GPIO_DIN31_0_DIO19_M 0x00080000
+#define GPIO_DIN31_0_DIO19_S 19
+
+// Field: [18] DIO18
+//
+// Data input from DIO 18
+#define GPIO_DIN31_0_DIO18 0x00040000
+#define GPIO_DIN31_0_DIO18_BITN 18
+#define GPIO_DIN31_0_DIO18_M 0x00040000
+#define GPIO_DIN31_0_DIO18_S 18
+
+// Field: [17] DIO17
+//
+// Data input from DIO 17
+#define GPIO_DIN31_0_DIO17 0x00020000
+#define GPIO_DIN31_0_DIO17_BITN 17
+#define GPIO_DIN31_0_DIO17_M 0x00020000
+#define GPIO_DIN31_0_DIO17_S 17
+
+// Field: [16] DIO16
+//
+// Data input from DIO 16
+#define GPIO_DIN31_0_DIO16 0x00010000
+#define GPIO_DIN31_0_DIO16_BITN 16
+#define GPIO_DIN31_0_DIO16_M 0x00010000
+#define GPIO_DIN31_0_DIO16_S 16
+
+// Field: [15] DIO15
+//
+// Data input from DIO 15
+#define GPIO_DIN31_0_DIO15 0x00008000
+#define GPIO_DIN31_0_DIO15_BITN 15
+#define GPIO_DIN31_0_DIO15_M 0x00008000
+#define GPIO_DIN31_0_DIO15_S 15
+
+// Field: [14] DIO14
+//
+// Data input from DIO 14
+#define GPIO_DIN31_0_DIO14 0x00004000
+#define GPIO_DIN31_0_DIO14_BITN 14
+#define GPIO_DIN31_0_DIO14_M 0x00004000
+#define GPIO_DIN31_0_DIO14_S 14
+
+// Field: [13] DIO13
+//
+// Data input from DIO 13
+#define GPIO_DIN31_0_DIO13 0x00002000
+#define GPIO_DIN31_0_DIO13_BITN 13
+#define GPIO_DIN31_0_DIO13_M 0x00002000
+#define GPIO_DIN31_0_DIO13_S 13
+
+// Field: [12] DIO12
+//
+// Data input from DIO 12
+#define GPIO_DIN31_0_DIO12 0x00001000
+#define GPIO_DIN31_0_DIO12_BITN 12
+#define GPIO_DIN31_0_DIO12_M 0x00001000
+#define GPIO_DIN31_0_DIO12_S 12
+
+// Field: [11] DIO11
+//
+// Data input from DIO 11
+#define GPIO_DIN31_0_DIO11 0x00000800
+#define GPIO_DIN31_0_DIO11_BITN 11
+#define GPIO_DIN31_0_DIO11_M 0x00000800
+#define GPIO_DIN31_0_DIO11_S 11
+
+// Field: [10] DIO10
+//
+// Data input from DIO 10
+#define GPIO_DIN31_0_DIO10 0x00000400
+#define GPIO_DIN31_0_DIO10_BITN 10
+#define GPIO_DIN31_0_DIO10_M 0x00000400
+#define GPIO_DIN31_0_DIO10_S 10
+
+// Field: [9] DIO9
+//
+// Data input from DIO 9
+#define GPIO_DIN31_0_DIO9 0x00000200
+#define GPIO_DIN31_0_DIO9_BITN 9
+#define GPIO_DIN31_0_DIO9_M 0x00000200
+#define GPIO_DIN31_0_DIO9_S 9
+
+// Field: [8] DIO8
+//
+// Data input from DIO 8
+#define GPIO_DIN31_0_DIO8 0x00000100
+#define GPIO_DIN31_0_DIO8_BITN 8
+#define GPIO_DIN31_0_DIO8_M 0x00000100
+#define GPIO_DIN31_0_DIO8_S 8
+
+// Field: [7] DIO7
+//
+// Data input from DIO 7
+#define GPIO_DIN31_0_DIO7 0x00000080
+#define GPIO_DIN31_0_DIO7_BITN 7
+#define GPIO_DIN31_0_DIO7_M 0x00000080
+#define GPIO_DIN31_0_DIO7_S 7
+
+// Field: [6] DIO6
+//
+// Data input from DIO 6
+#define GPIO_DIN31_0_DIO6 0x00000040
+#define GPIO_DIN31_0_DIO6_BITN 6
+#define GPIO_DIN31_0_DIO6_M 0x00000040
+#define GPIO_DIN31_0_DIO6_S 6
+
+// Field: [5] DIO5
+//
+// Data input from DIO 5
+#define GPIO_DIN31_0_DIO5 0x00000020
+#define GPIO_DIN31_0_DIO5_BITN 5
+#define GPIO_DIN31_0_DIO5_M 0x00000020
+#define GPIO_DIN31_0_DIO5_S 5
+
+// Field: [4] DIO4
+//
+// Data input from DIO 4
+#define GPIO_DIN31_0_DIO4 0x00000010
+#define GPIO_DIN31_0_DIO4_BITN 4
+#define GPIO_DIN31_0_DIO4_M 0x00000010
+#define GPIO_DIN31_0_DIO4_S 4
+
+// Field: [3] DIO3
+//
+// Data input from DIO 3
+#define GPIO_DIN31_0_DIO3 0x00000008
+#define GPIO_DIN31_0_DIO3_BITN 3
+#define GPIO_DIN31_0_DIO3_M 0x00000008
+#define GPIO_DIN31_0_DIO3_S 3
+
+// Field: [2] DIO2
+//
+// Data input from DIO 2
+#define GPIO_DIN31_0_DIO2 0x00000004
+#define GPIO_DIN31_0_DIO2_BITN 2
+#define GPIO_DIN31_0_DIO2_M 0x00000004
+#define GPIO_DIN31_0_DIO2_S 2
+
+// Field: [1] DIO1
+//
+// Data input from DIO 1
+#define GPIO_DIN31_0_DIO1 0x00000002
+#define GPIO_DIN31_0_DIO1_BITN 1
+#define GPIO_DIN31_0_DIO1_M 0x00000002
+#define GPIO_DIN31_0_DIO1_S 1
+
+// Field: [0] DIO0
+//
+// Data input from DIO 0
+#define GPIO_DIN31_0_DIO0 0x00000001
+#define GPIO_DIN31_0_DIO0_BITN 0
+#define GPIO_DIN31_0_DIO0_M 0x00000001
+#define GPIO_DIN31_0_DIO0_S 0
+
+//*****************************************************************************
+//
+// Register: GPIO_O_DOE31_0
+//
+//*****************************************************************************
+// Field: [31] DIO31
+//
+// Data output enable for DIO 31
+#define GPIO_DOE31_0_DIO31 0x80000000
+#define GPIO_DOE31_0_DIO31_BITN 31
+#define GPIO_DOE31_0_DIO31_M 0x80000000
+#define GPIO_DOE31_0_DIO31_S 31
+
+// Field: [30] DIO30
+//
+// Data output enable for DIO 30
+#define GPIO_DOE31_0_DIO30 0x40000000
+#define GPIO_DOE31_0_DIO30_BITN 30
+#define GPIO_DOE31_0_DIO30_M 0x40000000
+#define GPIO_DOE31_0_DIO30_S 30
+
+// Field: [29] DIO29
+//
+// Data output enable for DIO 29
+#define GPIO_DOE31_0_DIO29 0x20000000
+#define GPIO_DOE31_0_DIO29_BITN 29
+#define GPIO_DOE31_0_DIO29_M 0x20000000
+#define GPIO_DOE31_0_DIO29_S 29
+
+// Field: [28] DIO28
+//
+// Data output enable for DIO 28
+#define GPIO_DOE31_0_DIO28 0x10000000
+#define GPIO_DOE31_0_DIO28_BITN 28
+#define GPIO_DOE31_0_DIO28_M 0x10000000
+#define GPIO_DOE31_0_DIO28_S 28
+
+// Field: [27] DIO27
+//
+// Data output enable for DIO 27
+#define GPIO_DOE31_0_DIO27 0x08000000
+#define GPIO_DOE31_0_DIO27_BITN 27
+#define GPIO_DOE31_0_DIO27_M 0x08000000
+#define GPIO_DOE31_0_DIO27_S 27
+
+// Field: [26] DIO26
+//
+// Data output enable for DIO 26
+#define GPIO_DOE31_0_DIO26 0x04000000
+#define GPIO_DOE31_0_DIO26_BITN 26
+#define GPIO_DOE31_0_DIO26_M 0x04000000
+#define GPIO_DOE31_0_DIO26_S 26
+
+// Field: [25] DIO25
+//
+// Data output enable for DIO 25
+#define GPIO_DOE31_0_DIO25 0x02000000
+#define GPIO_DOE31_0_DIO25_BITN 25
+#define GPIO_DOE31_0_DIO25_M 0x02000000
+#define GPIO_DOE31_0_DIO25_S 25
+
+// Field: [24] DIO24
+//
+// Data output enable for DIO 24
+#define GPIO_DOE31_0_DIO24 0x01000000
+#define GPIO_DOE31_0_DIO24_BITN 24
+#define GPIO_DOE31_0_DIO24_M 0x01000000
+#define GPIO_DOE31_0_DIO24_S 24
+
+// Field: [23] DIO23
+//
+// Data output enable for DIO 23
+#define GPIO_DOE31_0_DIO23 0x00800000
+#define GPIO_DOE31_0_DIO23_BITN 23
+#define GPIO_DOE31_0_DIO23_M 0x00800000
+#define GPIO_DOE31_0_DIO23_S 23
+
+// Field: [22] DIO22
+//
+// Data output enable for DIO 22
+#define GPIO_DOE31_0_DIO22 0x00400000
+#define GPIO_DOE31_0_DIO22_BITN 22
+#define GPIO_DOE31_0_DIO22_M 0x00400000
+#define GPIO_DOE31_0_DIO22_S 22
+
+// Field: [21] DIO21
+//
+// Data output enable for DIO 21
+#define GPIO_DOE31_0_DIO21 0x00200000
+#define GPIO_DOE31_0_DIO21_BITN 21
+#define GPIO_DOE31_0_DIO21_M 0x00200000
+#define GPIO_DOE31_0_DIO21_S 21
+
+// Field: [20] DIO20
+//
+// Data output enable for DIO 20
+#define GPIO_DOE31_0_DIO20 0x00100000
+#define GPIO_DOE31_0_DIO20_BITN 20
+#define GPIO_DOE31_0_DIO20_M 0x00100000
+#define GPIO_DOE31_0_DIO20_S 20
+
+// Field: [19] DIO19
+//
+// Data output enable for DIO 19
+#define GPIO_DOE31_0_DIO19 0x00080000
+#define GPIO_DOE31_0_DIO19_BITN 19
+#define GPIO_DOE31_0_DIO19_M 0x00080000
+#define GPIO_DOE31_0_DIO19_S 19
+
+// Field: [18] DIO18
+//
+// Data output enable for DIO 18
+#define GPIO_DOE31_0_DIO18 0x00040000
+#define GPIO_DOE31_0_DIO18_BITN 18
+#define GPIO_DOE31_0_DIO18_M 0x00040000
+#define GPIO_DOE31_0_DIO18_S 18
+
+// Field: [17] DIO17
+//
+// Data output enable for DIO 17
+#define GPIO_DOE31_0_DIO17 0x00020000
+#define GPIO_DOE31_0_DIO17_BITN 17
+#define GPIO_DOE31_0_DIO17_M 0x00020000
+#define GPIO_DOE31_0_DIO17_S 17
+
+// Field: [16] DIO16
+//
+// Data output enable for DIO 16
+#define GPIO_DOE31_0_DIO16 0x00010000
+#define GPIO_DOE31_0_DIO16_BITN 16
+#define GPIO_DOE31_0_DIO16_M 0x00010000
+#define GPIO_DOE31_0_DIO16_S 16
+
+// Field: [15] DIO15
+//
+// Data output enable for DIO 15
+#define GPIO_DOE31_0_DIO15 0x00008000
+#define GPIO_DOE31_0_DIO15_BITN 15
+#define GPIO_DOE31_0_DIO15_M 0x00008000
+#define GPIO_DOE31_0_DIO15_S 15
+
+// Field: [14] DIO14
+//
+// Data output enable for DIO 14
+#define GPIO_DOE31_0_DIO14 0x00004000
+#define GPIO_DOE31_0_DIO14_BITN 14
+#define GPIO_DOE31_0_DIO14_M 0x00004000
+#define GPIO_DOE31_0_DIO14_S 14
+
+// Field: [13] DIO13
+//
+// Data output enable for DIO 13
+#define GPIO_DOE31_0_DIO13 0x00002000
+#define GPIO_DOE31_0_DIO13_BITN 13
+#define GPIO_DOE31_0_DIO13_M 0x00002000
+#define GPIO_DOE31_0_DIO13_S 13
+
+// Field: [12] DIO12
+//
+// Data output enable for DIO 12
+#define GPIO_DOE31_0_DIO12 0x00001000
+#define GPIO_DOE31_0_DIO12_BITN 12
+#define GPIO_DOE31_0_DIO12_M 0x00001000
+#define GPIO_DOE31_0_DIO12_S 12
+
+// Field: [11] DIO11
+//
+// Data output enable for DIO 11
+#define GPIO_DOE31_0_DIO11 0x00000800
+#define GPIO_DOE31_0_DIO11_BITN 11
+#define GPIO_DOE31_0_DIO11_M 0x00000800
+#define GPIO_DOE31_0_DIO11_S 11
+
+// Field: [10] DIO10
+//
+// Data output enable for DIO 10
+#define GPIO_DOE31_0_DIO10 0x00000400
+#define GPIO_DOE31_0_DIO10_BITN 10
+#define GPIO_DOE31_0_DIO10_M 0x00000400
+#define GPIO_DOE31_0_DIO10_S 10
+
+// Field: [9] DIO9
+//
+// Data output enable for DIO 9
+#define GPIO_DOE31_0_DIO9 0x00000200
+#define GPIO_DOE31_0_DIO9_BITN 9
+#define GPIO_DOE31_0_DIO9_M 0x00000200
+#define GPIO_DOE31_0_DIO9_S 9
+
+// Field: [8] DIO8
+//
+// Data output enable for DIO 8
+#define GPIO_DOE31_0_DIO8 0x00000100
+#define GPIO_DOE31_0_DIO8_BITN 8
+#define GPIO_DOE31_0_DIO8_M 0x00000100
+#define GPIO_DOE31_0_DIO8_S 8
+
+// Field: [7] DIO7
+//
+// Data output enable for DIO 7
+#define GPIO_DOE31_0_DIO7 0x00000080
+#define GPIO_DOE31_0_DIO7_BITN 7
+#define GPIO_DOE31_0_DIO7_M 0x00000080
+#define GPIO_DOE31_0_DIO7_S 7
+
+// Field: [6] DIO6
+//
+// Data output enable for DIO 6
+#define GPIO_DOE31_0_DIO6 0x00000040
+#define GPIO_DOE31_0_DIO6_BITN 6
+#define GPIO_DOE31_0_DIO6_M 0x00000040
+#define GPIO_DOE31_0_DIO6_S 6
+
+// Field: [5] DIO5
+//
+// Data output enable for DIO 5
+#define GPIO_DOE31_0_DIO5 0x00000020
+#define GPIO_DOE31_0_DIO5_BITN 5
+#define GPIO_DOE31_0_DIO5_M 0x00000020
+#define GPIO_DOE31_0_DIO5_S 5
+
+// Field: [4] DIO4
+//
+// Data output enable for DIO 4
+#define GPIO_DOE31_0_DIO4 0x00000010
+#define GPIO_DOE31_0_DIO4_BITN 4
+#define GPIO_DOE31_0_DIO4_M 0x00000010
+#define GPIO_DOE31_0_DIO4_S 4
+
+// Field: [3] DIO3
+//
+// Data output enable for DIO 3
+#define GPIO_DOE31_0_DIO3 0x00000008
+#define GPIO_DOE31_0_DIO3_BITN 3
+#define GPIO_DOE31_0_DIO3_M 0x00000008
+#define GPIO_DOE31_0_DIO3_S 3
+
+// Field: [2] DIO2
+//
+// Data output enable for DIO 2
+#define GPIO_DOE31_0_DIO2 0x00000004
+#define GPIO_DOE31_0_DIO2_BITN 2
+#define GPIO_DOE31_0_DIO2_M 0x00000004
+#define GPIO_DOE31_0_DIO2_S 2
+
+// Field: [1] DIO1
+//
+// Data output enable for DIO 1
+#define GPIO_DOE31_0_DIO1 0x00000002
+#define GPIO_DOE31_0_DIO1_BITN 1
+#define GPIO_DOE31_0_DIO1_M 0x00000002
+#define GPIO_DOE31_0_DIO1_S 1
+
+// Field: [0] DIO0
+//
+// Data output enable for DIO 0
+#define GPIO_DOE31_0_DIO0 0x00000001
+#define GPIO_DOE31_0_DIO0_BITN 0
+#define GPIO_DOE31_0_DIO0_M 0x00000001
+#define GPIO_DOE31_0_DIO0_S 0
+
+//*****************************************************************************
+//
+// Register: GPIO_O_EVFLAGS31_0
+//
+//*****************************************************************************
+// Field: [31] DIO31
+//
+// Event for DIO 31
+#define GPIO_EVFLAGS31_0_DIO31 0x80000000
+#define GPIO_EVFLAGS31_0_DIO31_BITN 31
+#define GPIO_EVFLAGS31_0_DIO31_M 0x80000000
+#define GPIO_EVFLAGS31_0_DIO31_S 31
+
+// Field: [30] DIO30
+//
+// Event for DIO 30
+#define GPIO_EVFLAGS31_0_DIO30 0x40000000
+#define GPIO_EVFLAGS31_0_DIO30_BITN 30
+#define GPIO_EVFLAGS31_0_DIO30_M 0x40000000
+#define GPIO_EVFLAGS31_0_DIO30_S 30
+
+// Field: [29] DIO29
+//
+// Event for DIO 29
+#define GPIO_EVFLAGS31_0_DIO29 0x20000000
+#define GPIO_EVFLAGS31_0_DIO29_BITN 29
+#define GPIO_EVFLAGS31_0_DIO29_M 0x20000000
+#define GPIO_EVFLAGS31_0_DIO29_S 29
+
+// Field: [28] DIO28
+//
+// Event for DIO 28
+#define GPIO_EVFLAGS31_0_DIO28 0x10000000
+#define GPIO_EVFLAGS31_0_DIO28_BITN 28
+#define GPIO_EVFLAGS31_0_DIO28_M 0x10000000
+#define GPIO_EVFLAGS31_0_DIO28_S 28
+
+// Field: [27] DIO27
+//
+// Event for DIO 27
+#define GPIO_EVFLAGS31_0_DIO27 0x08000000
+#define GPIO_EVFLAGS31_0_DIO27_BITN 27
+#define GPIO_EVFLAGS31_0_DIO27_M 0x08000000
+#define GPIO_EVFLAGS31_0_DIO27_S 27
+
+// Field: [26] DIO26
+//
+// Event for DIO 26
+#define GPIO_EVFLAGS31_0_DIO26 0x04000000
+#define GPIO_EVFLAGS31_0_DIO26_BITN 26
+#define GPIO_EVFLAGS31_0_DIO26_M 0x04000000
+#define GPIO_EVFLAGS31_0_DIO26_S 26
+
+// Field: [25] DIO25
+//
+// Event for DIO 25
+#define GPIO_EVFLAGS31_0_DIO25 0x02000000
+#define GPIO_EVFLAGS31_0_DIO25_BITN 25
+#define GPIO_EVFLAGS31_0_DIO25_M 0x02000000
+#define GPIO_EVFLAGS31_0_DIO25_S 25
+
+// Field: [24] DIO24
+//
+// Event for DIO 24
+#define GPIO_EVFLAGS31_0_DIO24 0x01000000
+#define GPIO_EVFLAGS31_0_DIO24_BITN 24
+#define GPIO_EVFLAGS31_0_DIO24_M 0x01000000
+#define GPIO_EVFLAGS31_0_DIO24_S 24
+
+// Field: [23] DIO23
+//
+// Event for DIO 23
+#define GPIO_EVFLAGS31_0_DIO23 0x00800000
+#define GPIO_EVFLAGS31_0_DIO23_BITN 23
+#define GPIO_EVFLAGS31_0_DIO23_M 0x00800000
+#define GPIO_EVFLAGS31_0_DIO23_S 23
+
+// Field: [22] DIO22
+//
+// Event for DIO 22
+#define GPIO_EVFLAGS31_0_DIO22 0x00400000
+#define GPIO_EVFLAGS31_0_DIO22_BITN 22
+#define GPIO_EVFLAGS31_0_DIO22_M 0x00400000
+#define GPIO_EVFLAGS31_0_DIO22_S 22
+
+// Field: [21] DIO21
+//
+// Event for DIO 21
+#define GPIO_EVFLAGS31_0_DIO21 0x00200000
+#define GPIO_EVFLAGS31_0_DIO21_BITN 21
+#define GPIO_EVFLAGS31_0_DIO21_M 0x00200000
+#define GPIO_EVFLAGS31_0_DIO21_S 21
+
+// Field: [20] DIO20
+//
+// Event for DIO 20
+#define GPIO_EVFLAGS31_0_DIO20 0x00100000
+#define GPIO_EVFLAGS31_0_DIO20_BITN 20
+#define GPIO_EVFLAGS31_0_DIO20_M 0x00100000
+#define GPIO_EVFLAGS31_0_DIO20_S 20
+
+// Field: [19] DIO19
+//
+// Event for DIO 19
+#define GPIO_EVFLAGS31_0_DIO19 0x00080000
+#define GPIO_EVFLAGS31_0_DIO19_BITN 19
+#define GPIO_EVFLAGS31_0_DIO19_M 0x00080000
+#define GPIO_EVFLAGS31_0_DIO19_S 19
+
+// Field: [18] DIO18
+//
+// Event for DIO 18
+#define GPIO_EVFLAGS31_0_DIO18 0x00040000
+#define GPIO_EVFLAGS31_0_DIO18_BITN 18
+#define GPIO_EVFLAGS31_0_DIO18_M 0x00040000
+#define GPIO_EVFLAGS31_0_DIO18_S 18
+
+// Field: [17] DIO17
+//
+// Event for DIO 17
+#define GPIO_EVFLAGS31_0_DIO17 0x00020000
+#define GPIO_EVFLAGS31_0_DIO17_BITN 17
+#define GPIO_EVFLAGS31_0_DIO17_M 0x00020000
+#define GPIO_EVFLAGS31_0_DIO17_S 17
+
+// Field: [16] DIO16
+//
+// Event for DIO 16
+#define GPIO_EVFLAGS31_0_DIO16 0x00010000
+#define GPIO_EVFLAGS31_0_DIO16_BITN 16
+#define GPIO_EVFLAGS31_0_DIO16_M 0x00010000
+#define GPIO_EVFLAGS31_0_DIO16_S 16
+
+// Field: [15] DIO15
+//
+// Event for DIO 15
+#define GPIO_EVFLAGS31_0_DIO15 0x00008000
+#define GPIO_EVFLAGS31_0_DIO15_BITN 15
+#define GPIO_EVFLAGS31_0_DIO15_M 0x00008000
+#define GPIO_EVFLAGS31_0_DIO15_S 15
+
+// Field: [14] DIO14
+//
+// Event for DIO 14
+#define GPIO_EVFLAGS31_0_DIO14 0x00004000
+#define GPIO_EVFLAGS31_0_DIO14_BITN 14
+#define GPIO_EVFLAGS31_0_DIO14_M 0x00004000
+#define GPIO_EVFLAGS31_0_DIO14_S 14
+
+// Field: [13] DIO13
+//
+// Event for DIO 13
+#define GPIO_EVFLAGS31_0_DIO13 0x00002000
+#define GPIO_EVFLAGS31_0_DIO13_BITN 13
+#define GPIO_EVFLAGS31_0_DIO13_M 0x00002000
+#define GPIO_EVFLAGS31_0_DIO13_S 13
+
+// Field: [12] DIO12
+//
+// Event for DIO 12
+#define GPIO_EVFLAGS31_0_DIO12 0x00001000
+#define GPIO_EVFLAGS31_0_DIO12_BITN 12
+#define GPIO_EVFLAGS31_0_DIO12_M 0x00001000
+#define GPIO_EVFLAGS31_0_DIO12_S 12
+
+// Field: [11] DIO11
+//
+// Event for DIO 11
+#define GPIO_EVFLAGS31_0_DIO11 0x00000800
+#define GPIO_EVFLAGS31_0_DIO11_BITN 11
+#define GPIO_EVFLAGS31_0_DIO11_M 0x00000800
+#define GPIO_EVFLAGS31_0_DIO11_S 11
+
+// Field: [10] DIO10
+//
+// Event for DIO 10
+#define GPIO_EVFLAGS31_0_DIO10 0x00000400
+#define GPIO_EVFLAGS31_0_DIO10_BITN 10
+#define GPIO_EVFLAGS31_0_DIO10_M 0x00000400
+#define GPIO_EVFLAGS31_0_DIO10_S 10
+
+// Field: [9] DIO9
+//
+// Event for DIO 9
+#define GPIO_EVFLAGS31_0_DIO9 0x00000200
+#define GPIO_EVFLAGS31_0_DIO9_BITN 9
+#define GPIO_EVFLAGS31_0_DIO9_M 0x00000200
+#define GPIO_EVFLAGS31_0_DIO9_S 9
+
+// Field: [8] DIO8
+//
+// Event for DIO 8
+#define GPIO_EVFLAGS31_0_DIO8 0x00000100
+#define GPIO_EVFLAGS31_0_DIO8_BITN 8
+#define GPIO_EVFLAGS31_0_DIO8_M 0x00000100
+#define GPIO_EVFLAGS31_0_DIO8_S 8
+
+// Field: [7] DIO7
+//
+// Event for DIO 7
+#define GPIO_EVFLAGS31_0_DIO7 0x00000080
+#define GPIO_EVFLAGS31_0_DIO7_BITN 7
+#define GPIO_EVFLAGS31_0_DIO7_M 0x00000080
+#define GPIO_EVFLAGS31_0_DIO7_S 7
+
+// Field: [6] DIO6
+//
+// Event for DIO 6
+#define GPIO_EVFLAGS31_0_DIO6 0x00000040
+#define GPIO_EVFLAGS31_0_DIO6_BITN 6
+#define GPIO_EVFLAGS31_0_DIO6_M 0x00000040
+#define GPIO_EVFLAGS31_0_DIO6_S 6
+
+// Field: [5] DIO5
+//
+// Event for DIO 5
+#define GPIO_EVFLAGS31_0_DIO5 0x00000020
+#define GPIO_EVFLAGS31_0_DIO5_BITN 5
+#define GPIO_EVFLAGS31_0_DIO5_M 0x00000020
+#define GPIO_EVFLAGS31_0_DIO5_S 5
+
+// Field: [4] DIO4
+//
+// Event for DIO 4
+#define GPIO_EVFLAGS31_0_DIO4 0x00000010
+#define GPIO_EVFLAGS31_0_DIO4_BITN 4
+#define GPIO_EVFLAGS31_0_DIO4_M 0x00000010
+#define GPIO_EVFLAGS31_0_DIO4_S 4
+
+// Field: [3] DIO3
+//
+// Event for DIO 3
+#define GPIO_EVFLAGS31_0_DIO3 0x00000008
+#define GPIO_EVFLAGS31_0_DIO3_BITN 3
+#define GPIO_EVFLAGS31_0_DIO3_M 0x00000008
+#define GPIO_EVFLAGS31_0_DIO3_S 3
+
+// Field: [2] DIO2
+//
+// Event for DIO 2
+#define GPIO_EVFLAGS31_0_DIO2 0x00000004
+#define GPIO_EVFLAGS31_0_DIO2_BITN 2
+#define GPIO_EVFLAGS31_0_DIO2_M 0x00000004
+#define GPIO_EVFLAGS31_0_DIO2_S 2
+
+// Field: [1] DIO1
+//
+// Event for DIO 1
+#define GPIO_EVFLAGS31_0_DIO1 0x00000002
+#define GPIO_EVFLAGS31_0_DIO1_BITN 1
+#define GPIO_EVFLAGS31_0_DIO1_M 0x00000002
+#define GPIO_EVFLAGS31_0_DIO1_S 1
+
+// Field: [0] DIO0
+//
+// Event for DIO 0
+#define GPIO_EVFLAGS31_0_DIO0 0x00000001
+#define GPIO_EVFLAGS31_0_DIO0_BITN 0
+#define GPIO_EVFLAGS31_0_DIO0_M 0x00000001
+#define GPIO_EVFLAGS31_0_DIO0_S 0
+
+
+#endif // __GPIO__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_gpram.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_gpram.h
new file mode 100644
index 0000000..1042a0f
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_gpram.h
@@ -0,0 +1,48 @@
+/******************************************************************************
+* Filename: hw_gpram_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_GPRAM_H__
+#define __HW_GPRAM_H__
+
+
+#define GPRAM_O_BANK0 0x00000000
+#define GPRAM_BANK0_BYTE_SIZE 8192
+
+#define GPRAM_TOT_BYTE_SIZE 8192
+
+
+
+#endif // __HW_GPRAM__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_gpt.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_gpt.h
new file mode 100644
index 0000000..5cf056e
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_gpt.h
@@ -0,0 +1,1697 @@
+/******************************************************************************
+* Filename: hw_gpt_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_GPT_H__
+#define __HW_GPT_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// GPT component
+//
+//*****************************************************************************
+// Configuration
+#define GPT_O_CFG 0x00000000
+
+// Timer A Mode
+#define GPT_O_TAMR 0x00000004
+
+// Timer B Mode
+#define GPT_O_TBMR 0x00000008
+
+// Control
+#define GPT_O_CTL 0x0000000C
+
+// Synch Register
+#define GPT_O_SYNC 0x00000010
+
+// Interrupt Mask
+#define GPT_O_IMR 0x00000018
+
+// Raw Interrupt Status
+#define GPT_O_RIS 0x0000001C
+
+// Masked Interrupt Status
+#define GPT_O_MIS 0x00000020
+
+// Interrupt Clear
+#define GPT_O_ICLR 0x00000024
+
+// Timer A Interval Load Register
+#define GPT_O_TAILR 0x00000028
+
+// Timer B Interval Load Register
+#define GPT_O_TBILR 0x0000002C
+
+// Timer A Match Register
+#define GPT_O_TAMATCHR 0x00000030
+
+// Timer B Match Register
+#define GPT_O_TBMATCHR 0x00000034
+
+// Timer A Pre-scale
+#define GPT_O_TAPR 0x00000038
+
+// Timer B Pre-scale
+#define GPT_O_TBPR 0x0000003C
+
+// Timer A Pre-scale Match
+#define GPT_O_TAPMR 0x00000040
+
+// Timer B Pre-scale Match
+#define GPT_O_TBPMR 0x00000044
+
+// Timer A Register
+#define GPT_O_TAR 0x00000048
+
+// Timer B Register
+#define GPT_O_TBR 0x0000004C
+
+// Timer A Value
+#define GPT_O_TAV 0x00000050
+
+// Timer B Value
+#define GPT_O_TBV 0x00000054
+
+// Timer A Pre-scale Snap-shot
+#define GPT_O_TAPS 0x0000005C
+
+// Timer B Pre-scale Snap-shot
+#define GPT_O_TBPS 0x00000060
+
+// Timer A Pre-scale Value
+#define GPT_O_TAPV 0x00000064
+
+// Timer B Pre-scale Value
+#define GPT_O_TBPV 0x00000068
+
+// DMA Event
+#define GPT_O_DMAEV 0x0000006C
+
+// Peripheral Version
+#define GPT_O_VERSION 0x00000FB0
+
+// Combined CCP Output
+#define GPT_O_ANDCCP 0x00000FB4
+
+//*****************************************************************************
+//
+// Register: GPT_O_CFG
+//
+//*****************************************************************************
+// Field: [2:0] CFG
+//
+// GPT Configuration
+// 0x2- 0x3 - Reserved
+// 0x5- 0x7 - Reserved
+// ENUMs:
+// 16BIT_TIMER 16-bit timer configuration.
+// Configure for two 16-bit
+// timers.
+// Also see TAMR.TAMR and
+// TBMR.TBMR.
+// 32BIT_TIMER 32-bit timer configuration
+#define GPT_CFG_CFG_W 3
+#define GPT_CFG_CFG_M 0x00000007
+#define GPT_CFG_CFG_S 0
+#define GPT_CFG_CFG_16BIT_TIMER 0x00000004
+#define GPT_CFG_CFG_32BIT_TIMER 0x00000000
+
+//*****************************************************************************
+//
+// Register: GPT_O_TAMR
+//
+//*****************************************************************************
+// Field: [15:13] TCACT
+//
+// Timer Compare Action Select
+// ENUMs:
+// CLRSET_ON_TO Clear CCP output pin immediately and set on
+// Time-Out
+// SETCLR_ON_TO Set CCP output pin immediately and clear on
+// Time-Out
+// CLRTOG_ON_TO Clear CCP output pin immediately and toggle on
+// Time-Out
+// SETTOG_ON_TO Set CCP output pin immediately and toggle on
+// Time-Out
+// SET_ON_TO Set CCP output pin on Time-Out
+// CLR_ON_TO Clear CCP output pin on Time-Out
+// TOG_ON_TO Toggle State on Time-Out
+// DIS_CMP Disable compare operations
+#define GPT_TAMR_TCACT_W 3
+#define GPT_TAMR_TCACT_M 0x0000E000
+#define GPT_TAMR_TCACT_S 13
+#define GPT_TAMR_TCACT_CLRSET_ON_TO 0x0000E000
+#define GPT_TAMR_TCACT_SETCLR_ON_TO 0x0000C000
+#define GPT_TAMR_TCACT_CLRTOG_ON_TO 0x0000A000
+#define GPT_TAMR_TCACT_SETTOG_ON_TO 0x00008000
+#define GPT_TAMR_TCACT_SET_ON_TO 0x00006000
+#define GPT_TAMR_TCACT_CLR_ON_TO 0x00004000
+#define GPT_TAMR_TCACT_TOG_ON_TO 0x00002000
+#define GPT_TAMR_TCACT_DIS_CMP 0x00000000
+
+// Field: [12] TACINTD
+//
+// One-Shot/Periodic Interrupt Disable
+// ENUMs:
+// DIS_TO_INTR Time-out interrupt are disabled
+// EN_TO_INTR Time-out interrupt function as normal
+#define GPT_TAMR_TACINTD 0x00001000
+#define GPT_TAMR_TACINTD_BITN 12
+#define GPT_TAMR_TACINTD_M 0x00001000
+#define GPT_TAMR_TACINTD_S 12
+#define GPT_TAMR_TACINTD_DIS_TO_INTR 0x00001000
+#define GPT_TAMR_TACINTD_EN_TO_INTR 0x00000000
+
+// Field: [11] TAPLO
+//
+// GPTM Timer A PWM Legacy Operation
+//
+// 0 Legacy operation with CCP pin driven Low when the TAILR
+// register is reloaded after the timer reaches 0.
+//
+// 1 CCP is driven High when the TAILR register is reloaded after the timer
+// reaches 0.
+//
+// This bit is only valid in PWM mode.
+// ENUMs:
+// CCP_ON_TO CCP output pin is set to 1 on time-out
+// LEGACY Legacy operation
+#define GPT_TAMR_TAPLO 0x00000800
+#define GPT_TAMR_TAPLO_BITN 11
+#define GPT_TAMR_TAPLO_M 0x00000800
+#define GPT_TAMR_TAPLO_S 11
+#define GPT_TAMR_TAPLO_CCP_ON_TO 0x00000800
+#define GPT_TAMR_TAPLO_LEGACY 0x00000000
+
+// Field: [10] TAMRSU
+//
+// Timer A Match Register Update mode
+//
+// This bit defines when the TAMATCHR and TAPR registers are updated.
+//
+// If the timer is disabled (CTL.TAEN = 0) when this bit is set, TAMATCHR and
+// TAPR are updated when the timer is enabled.
+// If the timer is stalled (CTL.TASTALL = 1) when this bit is set, TAMATCHR and
+// TAPR are updated according to the configuration of this bit.
+// ENUMs:
+// TOUPDATE Update TAMATCHR and TAPR, if used, on the next
+// time-out.
+// CYCLEUPDATE Update TAMATCHR and TAPR, if used, on the next
+// cycle.
+#define GPT_TAMR_TAMRSU 0x00000400
+#define GPT_TAMR_TAMRSU_BITN 10
+#define GPT_TAMR_TAMRSU_M 0x00000400
+#define GPT_TAMR_TAMRSU_S 10
+#define GPT_TAMR_TAMRSU_TOUPDATE 0x00000400
+#define GPT_TAMR_TAMRSU_CYCLEUPDATE 0x00000000
+
+// Field: [9] TAPWMIE
+//
+// GPTM Timer A PWM Interrupt Enable
+// This bit enables interrupts in PWM mode on rising, falling, or both edges of
+// the CCP output, as defined by the CTL.TAEVENT
+// In addition, when this bit is set and a capture event occurs, Timer A
+// automatically generates triggers to the DMA if the trigger capability is
+// enabled by setting the CTL.TAOTE bit and the DMAEV.CAEDMAEN bit
+// respectively.
+//
+// 0 Capture event interrupt is disabled.
+// 1 Capture event interrupt is enabled.
+// This bit is only valid in PWM mode.
+// ENUMs:
+// EN Interrupt is enabled. This bit is only valid in
+// PWM mode.
+// DIS Interrupt is disabled.
+#define GPT_TAMR_TAPWMIE 0x00000200
+#define GPT_TAMR_TAPWMIE_BITN 9
+#define GPT_TAMR_TAPWMIE_M 0x00000200
+#define GPT_TAMR_TAPWMIE_S 9
+#define GPT_TAMR_TAPWMIE_EN 0x00000200
+#define GPT_TAMR_TAPWMIE_DIS 0x00000000
+
+// Field: [8] TAILD
+//
+// GPT Timer A PWM Interval Load Write
+// ENUMs:
+// TOUPDATE Update the TAR register with the value in the
+// TAILR register on the next timeout. If the
+// prescaler is used, update the TAPS register
+// with the value in the TAPR register on the next
+// timeout.
+// CYCLEUPDATE Update the TAR register with the value in the
+// TAILR register on the next clock cycle. If the
+// pre-scaler is used, update the TAPS register
+// with the value in the TAPR register on the next
+// clock cycle.
+#define GPT_TAMR_TAILD 0x00000100
+#define GPT_TAMR_TAILD_BITN 8
+#define GPT_TAMR_TAILD_M 0x00000100
+#define GPT_TAMR_TAILD_S 8
+#define GPT_TAMR_TAILD_TOUPDATE 0x00000100
+#define GPT_TAMR_TAILD_CYCLEUPDATE 0x00000000
+
+// Field: [7] TASNAPS
+//
+// GPT Timer A Snap-Shot Mode
+// ENUMs:
+// EN If Timer A is configured in the periodic mode, the
+// actual free-running value of Timer A is loaded
+// at the time-out event into the GPT Timer A
+// (TAR) register.
+// DIS Snap-shot mode is disabled.
+#define GPT_TAMR_TASNAPS 0x00000080
+#define GPT_TAMR_TASNAPS_BITN 7
+#define GPT_TAMR_TASNAPS_M 0x00000080
+#define GPT_TAMR_TASNAPS_S 7
+#define GPT_TAMR_TASNAPS_EN 0x00000080
+#define GPT_TAMR_TASNAPS_DIS 0x00000000
+
+// Field: [6] TAWOT
+//
+// GPT Timer A Wait-On-Trigger
+// ENUMs:
+// WAIT If Timer A is enabled (CTL.TAEN = 1), Timer A does
+// not begin counting until it receives a trigger
+// from the timer in the previous position in the
+// daisy chain. This bit must be clear for GPT
+// Module 0, Timer A. This function is valid for
+// one-shot, periodic, and PWM modes
+// NOWAIT Timer A begins counting as soon as it is enabled.
+#define GPT_TAMR_TAWOT 0x00000040
+#define GPT_TAMR_TAWOT_BITN 6
+#define GPT_TAMR_TAWOT_M 0x00000040
+#define GPT_TAMR_TAWOT_S 6
+#define GPT_TAMR_TAWOT_WAIT 0x00000040
+#define GPT_TAMR_TAWOT_NOWAIT 0x00000000
+
+// Field: [5] TAMIE
+//
+// GPT Timer A Match Interrupt Enable
+// ENUMs:
+// EN An interrupt is generated when the match value in
+// TAMATCHR is reached in the one-shot and
+// periodic modes.
+// DIS The match interrupt is disabled for match events.
+// Additionally, output triggers on match events
+// are prevented.
+#define GPT_TAMR_TAMIE 0x00000020
+#define GPT_TAMR_TAMIE_BITN 5
+#define GPT_TAMR_TAMIE_M 0x00000020
+#define GPT_TAMR_TAMIE_S 5
+#define GPT_TAMR_TAMIE_EN 0x00000020
+#define GPT_TAMR_TAMIE_DIS 0x00000000
+
+// Field: [4] TACDIR
+//
+// GPT Timer A Count Direction
+// ENUMs:
+// UP The timer counts up. When counting up, the timer
+// starts from a value of 0x0.
+// DOWN The timer counts down.
+#define GPT_TAMR_TACDIR 0x00000010
+#define GPT_TAMR_TACDIR_BITN 4
+#define GPT_TAMR_TACDIR_M 0x00000010
+#define GPT_TAMR_TACDIR_S 4
+#define GPT_TAMR_TACDIR_UP 0x00000010
+#define GPT_TAMR_TACDIR_DOWN 0x00000000
+
+// Field: [3] TAAMS
+//
+// GPT Timer A Alternate Mode
+//
+// Note: To enable PWM mode, you must also clear TACM and then configure TAMR
+// field to 0x2.
+// ENUMs:
+// PWM PWM mode is enabled
+// CAP_COMP Capture/Compare mode is enabled.
+#define GPT_TAMR_TAAMS 0x00000008
+#define GPT_TAMR_TAAMS_BITN 3
+#define GPT_TAMR_TAAMS_M 0x00000008
+#define GPT_TAMR_TAAMS_S 3
+#define GPT_TAMR_TAAMS_PWM 0x00000008
+#define GPT_TAMR_TAAMS_CAP_COMP 0x00000000
+
+// Field: [2] TACM
+//
+// GPT Timer A Capture Mode
+// ENUMs:
+// EDGTIME Edge-Time mode
+// EDGCNT Edge-Count mode
+#define GPT_TAMR_TACM 0x00000004
+#define GPT_TAMR_TACM_BITN 2
+#define GPT_TAMR_TACM_M 0x00000004
+#define GPT_TAMR_TACM_S 2
+#define GPT_TAMR_TACM_EDGTIME 0x00000004
+#define GPT_TAMR_TACM_EDGCNT 0x00000000
+
+// Field: [1:0] TAMR
+//
+// GPT Timer A Mode
+//
+// 0x0 Reserved
+// 0x1 One-Shot Timer mode
+// 0x2 Periodic Timer mode
+// 0x3 Capture mode
+// The Timer mode is based on the timer configuration defined by bits 2:0 in
+// the CFG register
+// ENUMs:
+// CAPTURE Capture mode
+// PERIODIC Periodic Timer mode
+// ONE_SHOT One-Shot Timer mode
+#define GPT_TAMR_TAMR_W 2
+#define GPT_TAMR_TAMR_M 0x00000003
+#define GPT_TAMR_TAMR_S 0
+#define GPT_TAMR_TAMR_CAPTURE 0x00000003
+#define GPT_TAMR_TAMR_PERIODIC 0x00000002
+#define GPT_TAMR_TAMR_ONE_SHOT 0x00000001
+
+//*****************************************************************************
+//
+// Register: GPT_O_TBMR
+//
+//*****************************************************************************
+// Field: [15:13] TCACT
+//
+// Timer Compare Action Select
+// ENUMs:
+// CLRSET_ON_TO Clear CCP output pin immediately and set on
+// Time-Out
+// SETCLR_ON_TO Set CCP output pin immediately and clear on
+// Time-Out
+// CLRTOG_ON_TO Clear CCP output pin immediately and toggle on
+// Time-Out
+// SETTOG_ON_TO Set CCP output pin immediately and toggle on
+// Time-Out
+// SET_ON_TO Set CCP output pin on Time-Out
+// CLR_ON_TO Clear CCP output pin on Time-Out
+// TOG_ON_TO Toggle State on Time-Out
+// DIS_CMP Disable compare operations
+#define GPT_TBMR_TCACT_W 3
+#define GPT_TBMR_TCACT_M 0x0000E000
+#define GPT_TBMR_TCACT_S 13
+#define GPT_TBMR_TCACT_CLRSET_ON_TO 0x0000E000
+#define GPT_TBMR_TCACT_SETCLR_ON_TO 0x0000C000
+#define GPT_TBMR_TCACT_CLRTOG_ON_TO 0x0000A000
+#define GPT_TBMR_TCACT_SETTOG_ON_TO 0x00008000
+#define GPT_TBMR_TCACT_SET_ON_TO 0x00006000
+#define GPT_TBMR_TCACT_CLR_ON_TO 0x00004000
+#define GPT_TBMR_TCACT_TOG_ON_TO 0x00002000
+#define GPT_TBMR_TCACT_DIS_CMP 0x00000000
+
+// Field: [12] TBCINTD
+//
+// One-Shot/Periodic Interrupt Mode
+// ENUMs:
+// DIS_TO_INTR Mask Time-Out Interrupt
+// EN_TO_INTR Normal Time-Out Interrupt
+#define GPT_TBMR_TBCINTD 0x00001000
+#define GPT_TBMR_TBCINTD_BITN 12
+#define GPT_TBMR_TBCINTD_M 0x00001000
+#define GPT_TBMR_TBCINTD_S 12
+#define GPT_TBMR_TBCINTD_DIS_TO_INTR 0x00001000
+#define GPT_TBMR_TBCINTD_EN_TO_INTR 0x00000000
+
+// Field: [11] TBPLO
+//
+// GPTM Timer B PWM Legacy Operation
+//
+// 0 Legacy operation with CCP pin driven Low when the TBILR
+// register is reloaded after the timer reaches 0.
+//
+// 1 CCP is driven High when the TBILR register is reloaded after the timer
+// reaches 0.
+//
+// This bit is only valid in PWM mode.
+// ENUMs:
+// CCP_ON_TO CCP output pin is set to 1 on time-out
+// LEGACY Legacy operation
+#define GPT_TBMR_TBPLO 0x00000800
+#define GPT_TBMR_TBPLO_BITN 11
+#define GPT_TBMR_TBPLO_M 0x00000800
+#define GPT_TBMR_TBPLO_S 11
+#define GPT_TBMR_TBPLO_CCP_ON_TO 0x00000800
+#define GPT_TBMR_TBPLO_LEGACY 0x00000000
+
+// Field: [10] TBMRSU
+//
+// Timer B Match Register Update mode
+//
+// This bit defines when the TBMATCHR and TBPR registers are updated
+//
+// If the timer is disabled (CTL.TBEN is clear) when this bit is set, TBMATCHR
+// and TBPR are updated when the timer is enabled.
+// If the timer is stalled (CTL.TBSTALL is set) when this bit is set, TBMATCHR
+// and TBPR are updated according to the configuration of this bit.
+// ENUMs:
+// TOUPDATE Update TBMATCHR and TBPR, if used, on the next
+// time-out.
+// CYCLEUPDATE Update TBMATCHR and TBPR, if used, on the next
+// cycle.
+#define GPT_TBMR_TBMRSU 0x00000400
+#define GPT_TBMR_TBMRSU_BITN 10
+#define GPT_TBMR_TBMRSU_M 0x00000400
+#define GPT_TBMR_TBMRSU_S 10
+#define GPT_TBMR_TBMRSU_TOUPDATE 0x00000400
+#define GPT_TBMR_TBMRSU_CYCLEUPDATE 0x00000000
+
+// Field: [9] TBPWMIE
+//
+// GPTM Timer B PWM Interrupt Enable
+// This bit enables interrupts in PWM mode on rising, falling, or both edges of
+// the CCP output, as defined by the CTL.TBEVENT
+// In addition, when this bit is set and a capture event occurs, Timer A
+// automatically generates triggers to the DMA if the trigger capability is
+// enabled by setting the CTL.TBOTE bit and the DMAEV.CBEDMAEN bit
+// respectively.
+//
+// 0 Capture event interrupt is disabled.
+// 1 Capture event interrupt is enabled.
+// This bit is only valid in PWM mode.
+// ENUMs:
+// EN Interrupt is enabled. This bit is only valid in
+// PWM mode.
+// DIS Interrupt is disabled.
+#define GPT_TBMR_TBPWMIE 0x00000200
+#define GPT_TBMR_TBPWMIE_BITN 9
+#define GPT_TBMR_TBPWMIE_M 0x00000200
+#define GPT_TBMR_TBPWMIE_S 9
+#define GPT_TBMR_TBPWMIE_EN 0x00000200
+#define GPT_TBMR_TBPWMIE_DIS 0x00000000
+
+// Field: [8] TBILD
+//
+// GPT Timer B PWM Interval Load Write
+// ENUMs:
+// TOUPDATE Update the TBR register with the value in the
+// TBILR register on the next timeout. If the
+// prescaler is used, update the TBPS register
+// with the value in the TBPR register on the next
+// timeout.
+// CYCLEUPDATE Update the TBR register with the value in the
+// TBILR register on the next clock cycle. If the
+// pre-scaler is used, update the TBPS register
+// with the value in the TBPR register on the next
+// clock cycle.
+#define GPT_TBMR_TBILD 0x00000100
+#define GPT_TBMR_TBILD_BITN 8
+#define GPT_TBMR_TBILD_M 0x00000100
+#define GPT_TBMR_TBILD_S 8
+#define GPT_TBMR_TBILD_TOUPDATE 0x00000100
+#define GPT_TBMR_TBILD_CYCLEUPDATE 0x00000000
+
+// Field: [7] TBSNAPS
+//
+// GPT Timer B Snap-Shot Mode
+// ENUMs:
+// EN If Timer B is configured in the periodic mode
+// DIS Snap-shot mode is disabled.
+#define GPT_TBMR_TBSNAPS 0x00000080
+#define GPT_TBMR_TBSNAPS_BITN 7
+#define GPT_TBMR_TBSNAPS_M 0x00000080
+#define GPT_TBMR_TBSNAPS_S 7
+#define GPT_TBMR_TBSNAPS_EN 0x00000080
+#define GPT_TBMR_TBSNAPS_DIS 0x00000000
+
+// Field: [6] TBWOT
+//
+// GPT Timer B Wait-On-Trigger
+// ENUMs:
+// WAIT If Timer B is enabled (CTL.TBEN is set), Timer B
+// does not begin counting until it receives a
+// trigger from the timer in the previous position
+// in the daisy chain. This function is valid for
+// one-shot, periodic, and PWM modes
+// NOWAIT Timer B begins counting as soon as it is enabled.
+#define GPT_TBMR_TBWOT 0x00000040
+#define GPT_TBMR_TBWOT_BITN 6
+#define GPT_TBMR_TBWOT_M 0x00000040
+#define GPT_TBMR_TBWOT_S 6
+#define GPT_TBMR_TBWOT_WAIT 0x00000040
+#define GPT_TBMR_TBWOT_NOWAIT 0x00000000
+
+// Field: [5] TBMIE
+//
+// GPT Timer B Match Interrupt Enable.
+// ENUMs:
+// EN An interrupt is generated when the match value in
+// the TBMATCHR register is reached in the
+// one-shot and periodic modes.
+// DIS The match interrupt is disabled for match events.
+// Additionally, output triggers on match events
+// are prevented.
+#define GPT_TBMR_TBMIE 0x00000020
+#define GPT_TBMR_TBMIE_BITN 5
+#define GPT_TBMR_TBMIE_M 0x00000020
+#define GPT_TBMR_TBMIE_S 5
+#define GPT_TBMR_TBMIE_EN 0x00000020
+#define GPT_TBMR_TBMIE_DIS 0x00000000
+
+// Field: [4] TBCDIR
+//
+// GPT Timer B Count Direction
+// ENUMs:
+// UP The timer counts up. When counting up, the timer
+// starts from a value of 0x0.
+// DOWN The timer counts down.
+#define GPT_TBMR_TBCDIR 0x00000010
+#define GPT_TBMR_TBCDIR_BITN 4
+#define GPT_TBMR_TBCDIR_M 0x00000010
+#define GPT_TBMR_TBCDIR_S 4
+#define GPT_TBMR_TBCDIR_UP 0x00000010
+#define GPT_TBMR_TBCDIR_DOWN 0x00000000
+
+// Field: [3] TBAMS
+//
+// GPT Timer B Alternate Mode
+//
+// Note: To enable PWM mode, you must also clear TBCM bit and configure TBMR
+// field to 0x2.
+// ENUMs:
+// PWM PWM mode is enabled
+// CAP_COMP Capture/Compare mode is enabled.
+#define GPT_TBMR_TBAMS 0x00000008
+#define GPT_TBMR_TBAMS_BITN 3
+#define GPT_TBMR_TBAMS_M 0x00000008
+#define GPT_TBMR_TBAMS_S 3
+#define GPT_TBMR_TBAMS_PWM 0x00000008
+#define GPT_TBMR_TBAMS_CAP_COMP 0x00000000
+
+// Field: [2] TBCM
+//
+// GPT Timer B Capture Mode
+// ENUMs:
+// EDGTIME Edge-Time mode
+// EDGCNT Edge-Count mode
+#define GPT_TBMR_TBCM 0x00000004
+#define GPT_TBMR_TBCM_BITN 2
+#define GPT_TBMR_TBCM_M 0x00000004
+#define GPT_TBMR_TBCM_S 2
+#define GPT_TBMR_TBCM_EDGTIME 0x00000004
+#define GPT_TBMR_TBCM_EDGCNT 0x00000000
+
+// Field: [1:0] TBMR
+//
+// GPT Timer B Mode
+//
+// 0x0 Reserved
+// 0x1 One-Shot Timer mode
+// 0x2 Periodic Timer mode
+// 0x3 Capture mode
+// The Timer mode is based on the timer configuration defined by bits 2:0 in
+// the CFG register
+// ENUMs:
+// CAPTURE Capture mode
+// PERIODIC Periodic Timer mode
+// ONE_SHOT One-Shot Timer mode
+#define GPT_TBMR_TBMR_W 2
+#define GPT_TBMR_TBMR_M 0x00000003
+#define GPT_TBMR_TBMR_S 0
+#define GPT_TBMR_TBMR_CAPTURE 0x00000003
+#define GPT_TBMR_TBMR_PERIODIC 0x00000002
+#define GPT_TBMR_TBMR_ONE_SHOT 0x00000001
+
+//*****************************************************************************
+//
+// Register: GPT_O_CTL
+//
+//*****************************************************************************
+// Field: [14] TBPWML
+//
+// GPT Timer B PWM Output Level
+//
+// 0: Output is unaffected.
+// 1: Output is inverted.
+// ENUMs:
+// INVERTED Inverted
+// NORMAL Not inverted
+#define GPT_CTL_TBPWML 0x00004000
+#define GPT_CTL_TBPWML_BITN 14
+#define GPT_CTL_TBPWML_M 0x00004000
+#define GPT_CTL_TBPWML_S 14
+#define GPT_CTL_TBPWML_INVERTED 0x00004000
+#define GPT_CTL_TBPWML_NORMAL 0x00000000
+
+// Field: [11:10] TBEVENT
+//
+// GPT Timer B Event Mode
+//
+// The values in this register are defined as follows:
+// Value Description
+// 0x0 Positive edge
+// 0x1 Negative edge
+// 0x2 Reserved
+// 0x3 Both edges
+// Note: If PWM output inversion is enabled, edge detection interrupt
+// behavior is reversed. Thus, if a positive-edge interrupt trigger
+// has been set and the PWM inversion generates a postive
+// edge, no event-trigger interrupt asserts. Instead, the interrupt
+// is generated on the negative edge of the PWM signal.
+// ENUMs:
+// BOTH Both edges
+// NEG Negative edge
+// POS Positive edge
+#define GPT_CTL_TBEVENT_W 2
+#define GPT_CTL_TBEVENT_M 0x00000C00
+#define GPT_CTL_TBEVENT_S 10
+#define GPT_CTL_TBEVENT_BOTH 0x00000C00
+#define GPT_CTL_TBEVENT_NEG 0x00000400
+#define GPT_CTL_TBEVENT_POS 0x00000000
+
+// Field: [9] TBSTALL
+//
+// GPT Timer B Stall Enable
+// ENUMs:
+// EN Timer B freezes counting while the processor is
+// halted by the debugger.
+// DIS Timer B continues counting while the processor is
+// halted by the debugger.
+#define GPT_CTL_TBSTALL 0x00000200
+#define GPT_CTL_TBSTALL_BITN 9
+#define GPT_CTL_TBSTALL_M 0x00000200
+#define GPT_CTL_TBSTALL_S 9
+#define GPT_CTL_TBSTALL_EN 0x00000200
+#define GPT_CTL_TBSTALL_DIS 0x00000000
+
+// Field: [8] TBEN
+//
+// GPT Timer B Enable
+// ENUMs:
+// EN Timer B is enabled and begins counting or the
+// capture logic is enabled based on CFG register.
+// DIS Timer B is disabled.
+#define GPT_CTL_TBEN 0x00000100
+#define GPT_CTL_TBEN_BITN 8
+#define GPT_CTL_TBEN_M 0x00000100
+#define GPT_CTL_TBEN_S 8
+#define GPT_CTL_TBEN_EN 0x00000100
+#define GPT_CTL_TBEN_DIS 0x00000000
+
+// Field: [6] TAPWML
+//
+// GPT Timer A PWM Output Level
+// ENUMs:
+// INVERTED Inverted
+// NORMAL Not inverted
+#define GPT_CTL_TAPWML 0x00000040
+#define GPT_CTL_TAPWML_BITN 6
+#define GPT_CTL_TAPWML_M 0x00000040
+#define GPT_CTL_TAPWML_S 6
+#define GPT_CTL_TAPWML_INVERTED 0x00000040
+#define GPT_CTL_TAPWML_NORMAL 0x00000000
+
+// Field: [3:2] TAEVENT
+//
+// GPT Timer A Event Mode
+//
+// The values in this register are defined as follows:
+// Value Description
+// 0x0 Positive edge
+// 0x1 Negative edge
+// 0x2 Reserved
+// 0x3 Both edges
+// Note: If PWM output inversion is enabled, edge detection interrupt
+// behavior is reversed. Thus, if a positive-edge interrupt trigger
+// has been set and the PWM inversion generates a postive
+// edge, no event-trigger interrupt asserts. Instead, the interrupt
+// is generated on the negative edge of the PWM signal.
+// ENUMs:
+// BOTH Both edges
+// NEG Negative edge
+// POS Positive edge
+#define GPT_CTL_TAEVENT_W 2
+#define GPT_CTL_TAEVENT_M 0x0000000C
+#define GPT_CTL_TAEVENT_S 2
+#define GPT_CTL_TAEVENT_BOTH 0x0000000C
+#define GPT_CTL_TAEVENT_NEG 0x00000004
+#define GPT_CTL_TAEVENT_POS 0x00000000
+
+// Field: [1] TASTALL
+//
+// GPT Timer A Stall Enable
+// ENUMs:
+// EN Timer A freezes counting while the processor is
+// halted by the debugger.
+// DIS Timer A continues counting while the processor is
+// halted by the debugger.
+#define GPT_CTL_TASTALL 0x00000002
+#define GPT_CTL_TASTALL_BITN 1
+#define GPT_CTL_TASTALL_M 0x00000002
+#define GPT_CTL_TASTALL_S 1
+#define GPT_CTL_TASTALL_EN 0x00000002
+#define GPT_CTL_TASTALL_DIS 0x00000000
+
+// Field: [0] TAEN
+//
+// GPT Timer A Enable
+// ENUMs:
+// EN Timer A is enabled and begins counting or the
+// capture logic is enabled based on the CFG
+// register.
+// DIS Timer A is disabled.
+#define GPT_CTL_TAEN 0x00000001
+#define GPT_CTL_TAEN_BITN 0
+#define GPT_CTL_TAEN_M 0x00000001
+#define GPT_CTL_TAEN_S 0
+#define GPT_CTL_TAEN_EN 0x00000001
+#define GPT_CTL_TAEN_DIS 0x00000000
+
+//*****************************************************************************
+//
+// Register: GPT_O_SYNC
+//
+//*****************************************************************************
+// Field: [7:6] SYNC3
+//
+// Synchronize GPT Timer 3.
+// ENUMs:
+// BOTH A timeout event for both Timer A and Timer B of
+// GPT3 is triggered
+// TIMERB A timeout event for Timer B of GPT3 is triggered
+// TIMERA A timeout event for Timer A of GPT3 is triggered
+// NOSYNC No Sync. GPT3 is not affected.
+#define GPT_SYNC_SYNC3_W 2
+#define GPT_SYNC_SYNC3_M 0x000000C0
+#define GPT_SYNC_SYNC3_S 6
+#define GPT_SYNC_SYNC3_BOTH 0x000000C0
+#define GPT_SYNC_SYNC3_TIMERB 0x00000080
+#define GPT_SYNC_SYNC3_TIMERA 0x00000040
+#define GPT_SYNC_SYNC3_NOSYNC 0x00000000
+
+// Field: [5:4] SYNC2
+//
+// Synchronize GPT Timer 2.
+// ENUMs:
+// BOTH A timeout event for both Timer A and Timer B of
+// GPT2 is triggered
+// TIMERB A timeout event for Timer B of GPT2 is triggered
+// TIMERA A timeout event for Timer A of GPT2 is triggered
+// NOSYNC No Sync. GPT2 is not affected.
+#define GPT_SYNC_SYNC2_W 2
+#define GPT_SYNC_SYNC2_M 0x00000030
+#define GPT_SYNC_SYNC2_S 4
+#define GPT_SYNC_SYNC2_BOTH 0x00000030
+#define GPT_SYNC_SYNC2_TIMERB 0x00000020
+#define GPT_SYNC_SYNC2_TIMERA 0x00000010
+#define GPT_SYNC_SYNC2_NOSYNC 0x00000000
+
+// Field: [3:2] SYNC1
+//
+// Synchronize GPT Timer 1
+// ENUMs:
+// BOTH A timeout event for both Timer A and Timer B of
+// GPT1 is triggered
+// TIMERB A timeout event for Timer B of GPT1 is triggered
+// TIMERA A timeout event for Timer A of GPT1 is triggered
+// NOSYNC No Sync. GPT1 is not affected.
+#define GPT_SYNC_SYNC1_W 2
+#define GPT_SYNC_SYNC1_M 0x0000000C
+#define GPT_SYNC_SYNC1_S 2
+#define GPT_SYNC_SYNC1_BOTH 0x0000000C
+#define GPT_SYNC_SYNC1_TIMERB 0x00000008
+#define GPT_SYNC_SYNC1_TIMERA 0x00000004
+#define GPT_SYNC_SYNC1_NOSYNC 0x00000000
+
+// Field: [1:0] SYNC0
+//
+// Synchronize GPT Timer 0
+// ENUMs:
+// BOTH A timeout event for both Timer A and Timer B of
+// GPT0 is triggered
+// TIMERB A timeout event for Timer B of GPT0 is triggered
+// TIMERA A timeout event for Timer A of GPT0 is triggered
+// NOSYNC No Sync. GPT0 is not affected.
+#define GPT_SYNC_SYNC0_W 2
+#define GPT_SYNC_SYNC0_M 0x00000003
+#define GPT_SYNC_SYNC0_S 0
+#define GPT_SYNC_SYNC0_BOTH 0x00000003
+#define GPT_SYNC_SYNC0_TIMERB 0x00000002
+#define GPT_SYNC_SYNC0_TIMERA 0x00000001
+#define GPT_SYNC_SYNC0_NOSYNC 0x00000000
+
+//*****************************************************************************
+//
+// Register: GPT_O_IMR
+//
+//*****************************************************************************
+// Field: [13] DMABIM
+//
+// Enabling this bit will make the RIS.DMABRIS interrupt propagate to
+// MIS.DMABMIS
+// ENUMs:
+// EN Enable Interrupt
+// DIS Disable Interrupt
+#define GPT_IMR_DMABIM 0x00002000
+#define GPT_IMR_DMABIM_BITN 13
+#define GPT_IMR_DMABIM_M 0x00002000
+#define GPT_IMR_DMABIM_S 13
+#define GPT_IMR_DMABIM_EN 0x00002000
+#define GPT_IMR_DMABIM_DIS 0x00000000
+
+// Field: [11] TBMIM
+//
+// Enabling this bit will make the RIS.TBMRIS interrupt propagate to MIS.TBMMIS
+// ENUMs:
+// EN Enable Interrupt
+// DIS Disable Interrupt
+#define GPT_IMR_TBMIM 0x00000800
+#define GPT_IMR_TBMIM_BITN 11
+#define GPT_IMR_TBMIM_M 0x00000800
+#define GPT_IMR_TBMIM_S 11
+#define GPT_IMR_TBMIM_EN 0x00000800
+#define GPT_IMR_TBMIM_DIS 0x00000000
+
+// Field: [10] CBEIM
+//
+// Enabling this bit will make the RIS.CBERIS interrupt propagate to MIS.CBEMIS
+// ENUMs:
+// EN Enable Interrupt
+// DIS Disable Interrupt
+#define GPT_IMR_CBEIM 0x00000400
+#define GPT_IMR_CBEIM_BITN 10
+#define GPT_IMR_CBEIM_M 0x00000400
+#define GPT_IMR_CBEIM_S 10
+#define GPT_IMR_CBEIM_EN 0x00000400
+#define GPT_IMR_CBEIM_DIS 0x00000000
+
+// Field: [9] CBMIM
+//
+// Enabling this bit will make the RIS.CBMRIS interrupt propagate to MIS.CBMMIS
+// ENUMs:
+// EN Enable Interrupt
+// DIS Disable Interrupt
+#define GPT_IMR_CBMIM 0x00000200
+#define GPT_IMR_CBMIM_BITN 9
+#define GPT_IMR_CBMIM_M 0x00000200
+#define GPT_IMR_CBMIM_S 9
+#define GPT_IMR_CBMIM_EN 0x00000200
+#define GPT_IMR_CBMIM_DIS 0x00000000
+
+// Field: [8] TBTOIM
+//
+// Enabling this bit will make the RIS.TBTORIS interrupt propagate to
+// MIS.TBTOMIS
+// ENUMs:
+// EN Enable Interrupt
+// DIS Disable Interrupt
+#define GPT_IMR_TBTOIM 0x00000100
+#define GPT_IMR_TBTOIM_BITN 8
+#define GPT_IMR_TBTOIM_M 0x00000100
+#define GPT_IMR_TBTOIM_S 8
+#define GPT_IMR_TBTOIM_EN 0x00000100
+#define GPT_IMR_TBTOIM_DIS 0x00000000
+
+// Field: [5] DMAAIM
+//
+// Enabling this bit will make the RIS.DMAARIS interrupt propagate to
+// MIS.DMAAMIS
+// ENUMs:
+// EN Enable Interrupt
+// DIS Disable Interrupt
+#define GPT_IMR_DMAAIM 0x00000020
+#define GPT_IMR_DMAAIM_BITN 5
+#define GPT_IMR_DMAAIM_M 0x00000020
+#define GPT_IMR_DMAAIM_S 5
+#define GPT_IMR_DMAAIM_EN 0x00000020
+#define GPT_IMR_DMAAIM_DIS 0x00000000
+
+// Field: [4] TAMIM
+//
+// Enabling this bit will make the RIS.TAMRIS interrupt propagate to MIS.TAMMIS
+// ENUMs:
+// EN Enable Interrupt
+// DIS Disable Interrupt
+#define GPT_IMR_TAMIM 0x00000010
+#define GPT_IMR_TAMIM_BITN 4
+#define GPT_IMR_TAMIM_M 0x00000010
+#define GPT_IMR_TAMIM_S 4
+#define GPT_IMR_TAMIM_EN 0x00000010
+#define GPT_IMR_TAMIM_DIS 0x00000000
+
+// Field: [2] CAEIM
+//
+// Enabling this bit will make the RIS.CAERIS interrupt propagate to MIS.CAEMIS
+// ENUMs:
+// EN Enable Interrupt
+// DIS Disable Interrupt
+#define GPT_IMR_CAEIM 0x00000004
+#define GPT_IMR_CAEIM_BITN 2
+#define GPT_IMR_CAEIM_M 0x00000004
+#define GPT_IMR_CAEIM_S 2
+#define GPT_IMR_CAEIM_EN 0x00000004
+#define GPT_IMR_CAEIM_DIS 0x00000000
+
+// Field: [1] CAMIM
+//
+// Enabling this bit will make the RIS.CAMRIS interrupt propagate to MIS.CAMMIS
+// ENUMs:
+// EN Enable Interrupt
+// DIS Disable Interrupt
+#define GPT_IMR_CAMIM 0x00000002
+#define GPT_IMR_CAMIM_BITN 1
+#define GPT_IMR_CAMIM_M 0x00000002
+#define GPT_IMR_CAMIM_S 1
+#define GPT_IMR_CAMIM_EN 0x00000002
+#define GPT_IMR_CAMIM_DIS 0x00000000
+
+// Field: [0] TATOIM
+//
+// Enabling this bit will make the RIS.TATORIS interrupt propagate to
+// MIS.TATOMIS
+// ENUMs:
+// EN Enable Interrupt
+// DIS Disable Interrupt
+#define GPT_IMR_TATOIM 0x00000001
+#define GPT_IMR_TATOIM_BITN 0
+#define GPT_IMR_TATOIM_M 0x00000001
+#define GPT_IMR_TATOIM_S 0
+#define GPT_IMR_TATOIM_EN 0x00000001
+#define GPT_IMR_TATOIM_DIS 0x00000000
+
+//*****************************************************************************
+//
+// Register: GPT_O_RIS
+//
+//*****************************************************************************
+// Field: [13] DMABRIS
+//
+// GPT Timer B DMA Done Raw Interrupt Status
+//
+// 0: Transfer has not completed
+// 1: Transfer has completed
+#define GPT_RIS_DMABRIS 0x00002000
+#define GPT_RIS_DMABRIS_BITN 13
+#define GPT_RIS_DMABRIS_M 0x00002000
+#define GPT_RIS_DMABRIS_S 13
+
+// Field: [11] TBMRIS
+//
+// GPT Timer B Match Raw Interrupt
+//
+// 0: The match value has not been reached
+// 1: The match value is reached.
+//
+// TBMR.TBMIE is set, and the match values in TBMATCHR and optionally TBPMR
+// have been reached when configured in one-shot or periodic mode.
+#define GPT_RIS_TBMRIS 0x00000800
+#define GPT_RIS_TBMRIS_BITN 11
+#define GPT_RIS_TBMRIS_M 0x00000800
+#define GPT_RIS_TBMRIS_S 11
+
+// Field: [10] CBERIS
+//
+// GPT Timer B Capture Mode Event Raw Interrupt
+//
+// 0: The event has not occured.
+// 1: The event has occured.
+//
+// This interrupt asserts when the subtimer is configured in Input Edge-Time
+// mode
+#define GPT_RIS_CBERIS 0x00000400
+#define GPT_RIS_CBERIS_BITN 10
+#define GPT_RIS_CBERIS_M 0x00000400
+#define GPT_RIS_CBERIS_S 10
+
+// Field: [9] CBMRIS
+//
+// GPT Timer B Capture Mode Match Raw Interrupt
+//
+// 0: The capture mode match for Timer B has not occurred.
+// 1: A capture mode match has occurred for Timer B. This interrupt
+// asserts when the values in the TBR and TBPR
+// match the values in the TBMATCHR and TBPMR
+// when configured in Input Edge-Time mode.
+//
+// This bit is cleared by writing a 1 to the ICLR.CBMCINT bit.
+#define GPT_RIS_CBMRIS 0x00000200
+#define GPT_RIS_CBMRIS_BITN 9
+#define GPT_RIS_CBMRIS_M 0x00000200
+#define GPT_RIS_CBMRIS_S 9
+
+// Field: [8] TBTORIS
+//
+// GPT Timer B Time-out Raw Interrupt
+//
+// 0: Timer B has not timed out
+// 1: Timer B has timed out.
+//
+// This interrupt is asserted when a one-shot or periodic mode timer reaches
+// its count limit. The count limit is 0 or the value loaded into TBILR,
+// depending on the count direction.
+#define GPT_RIS_TBTORIS 0x00000100
+#define GPT_RIS_TBTORIS_BITN 8
+#define GPT_RIS_TBTORIS_M 0x00000100
+#define GPT_RIS_TBTORIS_S 8
+
+// Field: [5] DMAARIS
+//
+// GPT Timer A DMA Done Raw Interrupt Status
+//
+// 0: Transfer has not completed
+// 1: Transfer has completed
+#define GPT_RIS_DMAARIS 0x00000020
+#define GPT_RIS_DMAARIS_BITN 5
+#define GPT_RIS_DMAARIS_M 0x00000020
+#define GPT_RIS_DMAARIS_S 5
+
+// Field: [4] TAMRIS
+//
+// GPT Timer A Match Raw Interrupt
+//
+// 0: The match value has not been reached
+// 1: The match value is reached.
+//
+// TAMR.TAMIE is set, and the match values in TAMATCHR and optionally TAPMR
+// have been reached when configured in one-shot or periodic mode.
+#define GPT_RIS_TAMRIS 0x00000010
+#define GPT_RIS_TAMRIS_BITN 4
+#define GPT_RIS_TAMRIS_M 0x00000010
+#define GPT_RIS_TAMRIS_S 4
+
+// Field: [2] CAERIS
+//
+// GPT Timer A Capture Mode Event Raw Interrupt
+//
+// 0: The event has not occured.
+// 1: The event has occured.
+//
+// This interrupt asserts when the subtimer is configured in Input Edge-Time
+// mode
+#define GPT_RIS_CAERIS 0x00000004
+#define GPT_RIS_CAERIS_BITN 2
+#define GPT_RIS_CAERIS_M 0x00000004
+#define GPT_RIS_CAERIS_S 2
+
+// Field: [1] CAMRIS
+//
+// GPT Timer A Capture Mode Match Raw Interrupt
+//
+// 0: The capture mode match for Timer A has not occurred.
+// 1: A capture mode match has occurred for Timer A. This interrupt
+// asserts when the values in the TAR and TAPR
+// match the values in the TAMATCHR and TAPMR
+// when configured in Input Edge-Time mode.
+//
+// This bit is cleared by writing a 1 to the ICLR.CAMCINT bit.
+#define GPT_RIS_CAMRIS 0x00000002
+#define GPT_RIS_CAMRIS_BITN 1
+#define GPT_RIS_CAMRIS_M 0x00000002
+#define GPT_RIS_CAMRIS_S 1
+
+// Field: [0] TATORIS
+//
+// GPT Timer A Time-out Raw Interrupt
+//
+// 0: Timer A has not timed out
+// 1: Timer A has timed out.
+//
+// This interrupt is asserted when a one-shot or periodic mode timer reaches
+// its count limit. The count limit is 0 or the value loaded into TAILR,
+// depending on the count direction.
+#define GPT_RIS_TATORIS 0x00000001
+#define GPT_RIS_TATORIS_BITN 0
+#define GPT_RIS_TATORIS_M 0x00000001
+#define GPT_RIS_TATORIS_S 0
+
+//*****************************************************************************
+//
+// Register: GPT_O_MIS
+//
+//*****************************************************************************
+// Field: [13] DMABMIS
+//
+// 0: No interrupt or interrupt not enabled
+// 1: RIS.DMABRIS = 1 && IMR.DMABIM = 1
+#define GPT_MIS_DMABMIS 0x00002000
+#define GPT_MIS_DMABMIS_BITN 13
+#define GPT_MIS_DMABMIS_M 0x00002000
+#define GPT_MIS_DMABMIS_S 13
+
+// Field: [11] TBMMIS
+//
+// 0: No interrupt or interrupt not enabled
+// 1: RIS.TBMRIS = 1 && IMR.TBMIM = 1
+#define GPT_MIS_TBMMIS 0x00000800
+#define GPT_MIS_TBMMIS_BITN 11
+#define GPT_MIS_TBMMIS_M 0x00000800
+#define GPT_MIS_TBMMIS_S 11
+
+// Field: [10] CBEMIS
+//
+// 0: No interrupt or interrupt not enabled
+// 1: RIS.CBERIS = 1 && IMR.CBEIM = 1
+#define GPT_MIS_CBEMIS 0x00000400
+#define GPT_MIS_CBEMIS_BITN 10
+#define GPT_MIS_CBEMIS_M 0x00000400
+#define GPT_MIS_CBEMIS_S 10
+
+// Field: [9] CBMMIS
+//
+// 0: No interrupt or interrupt not enabled
+// 1: RIS.CBMRIS = 1 && IMR.CBMIM = 1
+#define GPT_MIS_CBMMIS 0x00000200
+#define GPT_MIS_CBMMIS_BITN 9
+#define GPT_MIS_CBMMIS_M 0x00000200
+#define GPT_MIS_CBMMIS_S 9
+
+// Field: [8] TBTOMIS
+//
+// 0: No interrupt or interrupt not enabled
+// 1: RIS.TBTORIS = 1 && IMR.TBTOIM = 1
+#define GPT_MIS_TBTOMIS 0x00000100
+#define GPT_MIS_TBTOMIS_BITN 8
+#define GPT_MIS_TBTOMIS_M 0x00000100
+#define GPT_MIS_TBTOMIS_S 8
+
+// Field: [5] DMAAMIS
+//
+// 0: No interrupt or interrupt not enabled
+// 1: RIS.DMAARIS = 1 && IMR.DMAAIM = 1
+#define GPT_MIS_DMAAMIS 0x00000020
+#define GPT_MIS_DMAAMIS_BITN 5
+#define GPT_MIS_DMAAMIS_M 0x00000020
+#define GPT_MIS_DMAAMIS_S 5
+
+// Field: [4] TAMMIS
+//
+// 0: No interrupt or interrupt not enabled
+// 1: RIS.TAMRIS = 1 && IMR.TAMIM = 1
+#define GPT_MIS_TAMMIS 0x00000010
+#define GPT_MIS_TAMMIS_BITN 4
+#define GPT_MIS_TAMMIS_M 0x00000010
+#define GPT_MIS_TAMMIS_S 4
+
+// Field: [2] CAEMIS
+//
+// 0: No interrupt or interrupt not enabled
+// 1: RIS.CAERIS = 1 && IMR.CAEIM = 1
+#define GPT_MIS_CAEMIS 0x00000004
+#define GPT_MIS_CAEMIS_BITN 2
+#define GPT_MIS_CAEMIS_M 0x00000004
+#define GPT_MIS_CAEMIS_S 2
+
+// Field: [1] CAMMIS
+//
+// 0: No interrupt or interrupt not enabled
+// 1: RIS.CAMRIS = 1 && IMR.CAMIM = 1
+#define GPT_MIS_CAMMIS 0x00000002
+#define GPT_MIS_CAMMIS_BITN 1
+#define GPT_MIS_CAMMIS_M 0x00000002
+#define GPT_MIS_CAMMIS_S 1
+
+// Field: [0] TATOMIS
+//
+// 0: No interrupt or interrupt not enabled
+// 1: RIS.TATORIS = 1 && IMR.TATOIM = 1
+#define GPT_MIS_TATOMIS 0x00000001
+#define GPT_MIS_TATOMIS_BITN 0
+#define GPT_MIS_TATOMIS_M 0x00000001
+#define GPT_MIS_TATOMIS_S 0
+
+//*****************************************************************************
+//
+// Register: GPT_O_ICLR
+//
+//*****************************************************************************
+// Field: [13] DMABINT
+//
+// 0: Do nothing.
+// 1: Clear RIS.DMABRIS and MIS.DMABMIS
+#define GPT_ICLR_DMABINT 0x00002000
+#define GPT_ICLR_DMABINT_BITN 13
+#define GPT_ICLR_DMABINT_M 0x00002000
+#define GPT_ICLR_DMABINT_S 13
+
+// Field: [11] TBMCINT
+//
+// 0: Do nothing.
+// 1: Clear RIS.TBMRIS and MIS.TBMMIS
+#define GPT_ICLR_TBMCINT 0x00000800
+#define GPT_ICLR_TBMCINT_BITN 11
+#define GPT_ICLR_TBMCINT_M 0x00000800
+#define GPT_ICLR_TBMCINT_S 11
+
+// Field: [10] CBECINT
+//
+// 0: Do nothing.
+// 1: Clear RIS.CBERIS and MIS.CBEMIS
+#define GPT_ICLR_CBECINT 0x00000400
+#define GPT_ICLR_CBECINT_BITN 10
+#define GPT_ICLR_CBECINT_M 0x00000400
+#define GPT_ICLR_CBECINT_S 10
+
+// Field: [9] CBMCINT
+//
+// 0: Do nothing.
+// 1: Clear RIS.CBMRIS and MIS.CBMMIS
+#define GPT_ICLR_CBMCINT 0x00000200
+#define GPT_ICLR_CBMCINT_BITN 9
+#define GPT_ICLR_CBMCINT_M 0x00000200
+#define GPT_ICLR_CBMCINT_S 9
+
+// Field: [8] TBTOCINT
+//
+// 0: Do nothing.
+// 1: Clear RIS.TBTORIS and MIS.TBTOMIS
+#define GPT_ICLR_TBTOCINT 0x00000100
+#define GPT_ICLR_TBTOCINT_BITN 8
+#define GPT_ICLR_TBTOCINT_M 0x00000100
+#define GPT_ICLR_TBTOCINT_S 8
+
+// Field: [5] DMAAINT
+//
+// 0: Do nothing.
+// 1: Clear RIS.DMAARIS and MIS.DMAAMIS
+#define GPT_ICLR_DMAAINT 0x00000020
+#define GPT_ICLR_DMAAINT_BITN 5
+#define GPT_ICLR_DMAAINT_M 0x00000020
+#define GPT_ICLR_DMAAINT_S 5
+
+// Field: [4] TAMCINT
+//
+// 0: Do nothing.
+// 1: Clear RIS.TAMRIS and MIS.TAMMIS
+#define GPT_ICLR_TAMCINT 0x00000010
+#define GPT_ICLR_TAMCINT_BITN 4
+#define GPT_ICLR_TAMCINT_M 0x00000010
+#define GPT_ICLR_TAMCINT_S 4
+
+// Field: [2] CAECINT
+//
+// 0: Do nothing.
+// 1: Clear RIS.CAERIS and MIS.CAEMIS
+#define GPT_ICLR_CAECINT 0x00000004
+#define GPT_ICLR_CAECINT_BITN 2
+#define GPT_ICLR_CAECINT_M 0x00000004
+#define GPT_ICLR_CAECINT_S 2
+
+// Field: [1] CAMCINT
+//
+// 0: Do nothing.
+// 1: Clear RIS.CAMRIS and MIS.CAMMIS
+#define GPT_ICLR_CAMCINT 0x00000002
+#define GPT_ICLR_CAMCINT_BITN 1
+#define GPT_ICLR_CAMCINT_M 0x00000002
+#define GPT_ICLR_CAMCINT_S 1
+
+// Field: [0] TATOCINT
+//
+// 0: Do nothing.
+// 1: Clear RIS.TATORIS and MIS.TATOMIS
+#define GPT_ICLR_TATOCINT 0x00000001
+#define GPT_ICLR_TATOCINT_BITN 0
+#define GPT_ICLR_TATOCINT_M 0x00000001
+#define GPT_ICLR_TATOCINT_S 0
+
+//*****************************************************************************
+//
+// Register: GPT_O_TAILR
+//
+//*****************************************************************************
+// Field: [31:0] TAILR
+//
+// GPT Timer A Interval Load Register
+//
+// Writing this field loads the counter for Timer A. A read returns the current
+// value of TAILR.
+#define GPT_TAILR_TAILR_W 32
+#define GPT_TAILR_TAILR_M 0xFFFFFFFF
+#define GPT_TAILR_TAILR_S 0
+
+//*****************************************************************************
+//
+// Register: GPT_O_TBILR
+//
+//*****************************************************************************
+// Field: [31:0] TBILR
+//
+// GPT Timer B Interval Load Register
+//
+// Writing this field loads the counter for Timer B. A read returns the current
+// value of TBILR.
+#define GPT_TBILR_TBILR_W 32
+#define GPT_TBILR_TBILR_M 0xFFFFFFFF
+#define GPT_TBILR_TBILR_S 0
+
+//*****************************************************************************
+//
+// Register: GPT_O_TAMATCHR
+//
+//*****************************************************************************
+// Field: [31:0] TAMATCHR
+//
+// GPT Timer A Match Register
+#define GPT_TAMATCHR_TAMATCHR_W 32
+#define GPT_TAMATCHR_TAMATCHR_M 0xFFFFFFFF
+#define GPT_TAMATCHR_TAMATCHR_S 0
+
+//*****************************************************************************
+//
+// Register: GPT_O_TBMATCHR
+//
+//*****************************************************************************
+// Field: [15:0] TBMATCHR
+//
+// GPT Timer B Match Register
+#define GPT_TBMATCHR_TBMATCHR_W 16
+#define GPT_TBMATCHR_TBMATCHR_M 0x0000FFFF
+#define GPT_TBMATCHR_TBMATCHR_S 0
+
+//*****************************************************************************
+//
+// Register: GPT_O_TAPR
+//
+//*****************************************************************************
+// Field: [7:0] TAPSR
+//
+// Timer A Pre-scale.
+//
+// Prescaler ratio in one-shot and periodic count mode is TAPSR + 1, that is:
+//
+// 0: Prescaler ratio = 1
+// 1: Prescaler ratio = 2
+// 2: Prescaler ratio = 3
+// ...
+// 255: Prescaler ratio = 256
+#define GPT_TAPR_TAPSR_W 8
+#define GPT_TAPR_TAPSR_M 0x000000FF
+#define GPT_TAPR_TAPSR_S 0
+
+//*****************************************************************************
+//
+// Register: GPT_O_TBPR
+//
+//*****************************************************************************
+// Field: [7:0] TBPSR
+//
+// Timer B Pre-scale.
+//
+// Prescale ratio in one-shot and periodic count mode is TBPSR + 1, that is:
+//
+// 0: Prescaler ratio = 1
+// 1: Prescaler ratio = 2
+// 2: Prescaler ratio = 3
+// ...
+// 255: Prescaler ratio = 256
+#define GPT_TBPR_TBPSR_W 8
+#define GPT_TBPR_TBPSR_M 0x000000FF
+#define GPT_TBPR_TBPSR_S 0
+
+//*****************************************************************************
+//
+// Register: GPT_O_TAPMR
+//
+//*****************************************************************************
+// Field: [7:0] TAPSMR
+//
+// GPT Timer A Pre-scale Match. In 16 bit mode this field holds bits 23 to 16.
+#define GPT_TAPMR_TAPSMR_W 8
+#define GPT_TAPMR_TAPSMR_M 0x000000FF
+#define GPT_TAPMR_TAPSMR_S 0
+
+//*****************************************************************************
+//
+// Register: GPT_O_TBPMR
+//
+//*****************************************************************************
+// Field: [7:0] TBPSMR
+//
+// GPT Timer B Pre-scale Match Register. In 16 bit mode this field holds bits
+// 23 to 16.
+#define GPT_TBPMR_TBPSMR_W 8
+#define GPT_TBPMR_TBPSMR_M 0x000000FF
+#define GPT_TBPMR_TBPSMR_S 0
+
+//*****************************************************************************
+//
+// Register: GPT_O_TAR
+//
+//*****************************************************************************
+// Field: [31:0] TAR
+//
+// GPT Timer A Register
+//
+// Based on the value in the register field TAMR.TAILD, this register is
+// updated with the value from TAILR register either on the next cycle or on
+// the next timeout.
+//
+// A read returns the current value of the Timer A Count Register, in all cases
+// except for Input Edge count and Timer modes.
+// In the Input Edge Count Mode, this register contains the number of edges
+// that have occurred. In the Input Edge Time mode, this register contains the
+// time at which the last edge event took place.
+#define GPT_TAR_TAR_W 32
+#define GPT_TAR_TAR_M 0xFFFFFFFF
+#define GPT_TAR_TAR_S 0
+
+//*****************************************************************************
+//
+// Register: GPT_O_TBR
+//
+//*****************************************************************************
+// Field: [31:0] TBR
+//
+// GPT Timer B Register
+//
+// Based on the value in the register field TBMR.TBILD, this register is
+// updated with the value from TBILR register either on the next cycle or on
+// the next timeout.
+//
+// A read returns the current value of the Timer B Count Register, in all cases
+// except for Input Edge count and Timer modes.
+// In the Input Edge Count Mode, this register contains the number of edges
+// that have occurred. In the Input Edge Time mode, this register contains the
+// time at which the last edge event took place.
+#define GPT_TBR_TBR_W 32
+#define GPT_TBR_TBR_M 0xFFFFFFFF
+#define GPT_TBR_TBR_S 0
+
+//*****************************************************************************
+//
+// Register: GPT_O_TAV
+//
+//*****************************************************************************
+// Field: [31:0] TAV
+//
+// GPT Timer A Register
+// A read returns the current, free-running value of Timer A in all modes.
+// When written, the value written into this register is loaded into the
+// TAR register on the next clock cycle.
+// Note: In 16-bit mode, only the lower 16-bits of this
+// register can be written with a new value. Writes to the prescaler bits have
+// no effect
+#define GPT_TAV_TAV_W 32
+#define GPT_TAV_TAV_M 0xFFFFFFFF
+#define GPT_TAV_TAV_S 0
+
+//*****************************************************************************
+//
+// Register: GPT_O_TBV
+//
+//*****************************************************************************
+// Field: [31:0] TBV
+//
+// GPT Timer B Register
+// A read returns the current, free-running value of Timer B in all modes.
+// When written, the value written into this register is loaded into the
+// TBR register on the next clock cycle.
+// Note: In 16-bit mode, only the lower 16-bits of this
+// register can be written with a new value. Writes to the prescaler bits have
+// no effect
+#define GPT_TBV_TBV_W 32
+#define GPT_TBV_TBV_M 0xFFFFFFFF
+#define GPT_TBV_TBV_S 0
+
+//*****************************************************************************
+//
+// Register: GPT_O_TAPS
+//
+//*****************************************************************************
+// Field: [7:0] PSS
+//
+// GPT Timer A Pre-scaler
+#define GPT_TAPS_PSS_W 8
+#define GPT_TAPS_PSS_M 0x000000FF
+#define GPT_TAPS_PSS_S 0
+
+//*****************************************************************************
+//
+// Register: GPT_O_TBPS
+//
+//*****************************************************************************
+// Field: [7:0] PSS
+//
+// GPT Timer B Pre-scaler
+#define GPT_TBPS_PSS_W 8
+#define GPT_TBPS_PSS_M 0x000000FF
+#define GPT_TBPS_PSS_S 0
+
+//*****************************************************************************
+//
+// Register: GPT_O_TAPV
+//
+//*****************************************************************************
+// Field: [7:0] PSV
+//
+// GPT Timer A Pre-scaler Value
+#define GPT_TAPV_PSV_W 8
+#define GPT_TAPV_PSV_M 0x000000FF
+#define GPT_TAPV_PSV_S 0
+
+//*****************************************************************************
+//
+// Register: GPT_O_TBPV
+//
+//*****************************************************************************
+// Field: [7:0] PSV
+//
+// GPT Timer B Pre-scaler Value
+#define GPT_TBPV_PSV_W 8
+#define GPT_TBPV_PSV_M 0x000000FF
+#define GPT_TBPV_PSV_S 0
+
+//*****************************************************************************
+//
+// Register: GPT_O_DMAEV
+//
+//*****************************************************************************
+// Field: [11] TBMDMAEN
+//
+// GPT Timer B Match DMA Trigger Enable
+#define GPT_DMAEV_TBMDMAEN 0x00000800
+#define GPT_DMAEV_TBMDMAEN_BITN 11
+#define GPT_DMAEV_TBMDMAEN_M 0x00000800
+#define GPT_DMAEV_TBMDMAEN_S 11
+
+// Field: [10] CBEDMAEN
+//
+// GPT Timer B Capture Event DMA Trigger Enable
+#define GPT_DMAEV_CBEDMAEN 0x00000400
+#define GPT_DMAEV_CBEDMAEN_BITN 10
+#define GPT_DMAEV_CBEDMAEN_M 0x00000400
+#define GPT_DMAEV_CBEDMAEN_S 10
+
+// Field: [9] CBMDMAEN
+//
+// GPT Timer B Capture Match DMA Trigger Enable
+#define GPT_DMAEV_CBMDMAEN 0x00000200
+#define GPT_DMAEV_CBMDMAEN_BITN 9
+#define GPT_DMAEV_CBMDMAEN_M 0x00000200
+#define GPT_DMAEV_CBMDMAEN_S 9
+
+// Field: [8] TBTODMAEN
+//
+// GPT Timer B Time-Out DMA Trigger Enable
+#define GPT_DMAEV_TBTODMAEN 0x00000100
+#define GPT_DMAEV_TBTODMAEN_BITN 8
+#define GPT_DMAEV_TBTODMAEN_M 0x00000100
+#define GPT_DMAEV_TBTODMAEN_S 8
+
+// Field: [4] TAMDMAEN
+//
+// GPT Timer A Match DMA Trigger Enable
+#define GPT_DMAEV_TAMDMAEN 0x00000010
+#define GPT_DMAEV_TAMDMAEN_BITN 4
+#define GPT_DMAEV_TAMDMAEN_M 0x00000010
+#define GPT_DMAEV_TAMDMAEN_S 4
+
+// Field: [2] CAEDMAEN
+//
+// GPT Timer A Capture Event DMA Trigger Enable
+#define GPT_DMAEV_CAEDMAEN 0x00000004
+#define GPT_DMAEV_CAEDMAEN_BITN 2
+#define GPT_DMAEV_CAEDMAEN_M 0x00000004
+#define GPT_DMAEV_CAEDMAEN_S 2
+
+// Field: [1] CAMDMAEN
+//
+// GPT Timer A Capture Match DMA Trigger Enable
+#define GPT_DMAEV_CAMDMAEN 0x00000002
+#define GPT_DMAEV_CAMDMAEN_BITN 1
+#define GPT_DMAEV_CAMDMAEN_M 0x00000002
+#define GPT_DMAEV_CAMDMAEN_S 1
+
+// Field: [0] TATODMAEN
+//
+// GPT Timer A Time-Out DMA Trigger Enable
+#define GPT_DMAEV_TATODMAEN 0x00000001
+#define GPT_DMAEV_TATODMAEN_BITN 0
+#define GPT_DMAEV_TATODMAEN_M 0x00000001
+#define GPT_DMAEV_TATODMAEN_S 0
+
+//*****************************************************************************
+//
+// Register: GPT_O_VERSION
+//
+//*****************************************************************************
+// Field: [31:0] VERSION
+//
+// Timer Revision.
+#define GPT_VERSION_VERSION_W 32
+#define GPT_VERSION_VERSION_M 0xFFFFFFFF
+#define GPT_VERSION_VERSION_S 0
+
+//*****************************************************************************
+//
+// Register: GPT_O_ANDCCP
+//
+//*****************************************************************************
+// Field: [1] LD_TO_EN
+//
+// PWM assertion would happen at timeout
+//
+// 0: PWM assertion happens when counter matches load value
+// 1: PWM assertion happens at timeout of the counter
+#define GPT_ANDCCP_LD_TO_EN 0x00000002
+#define GPT_ANDCCP_LD_TO_EN_BITN 1
+#define GPT_ANDCCP_LD_TO_EN_M 0x00000002
+#define GPT_ANDCCP_LD_TO_EN_S 1
+
+// Field: [0] CCP_AND_EN
+//
+// Enables AND operation of the CCP outputs for timers A and B.
+//
+// 0 : PWM outputs of Timer A and Timer B are the internal generated PWM
+// signals of the respective timers.
+// 1 : PWM output of Timer A is ANDed version of Timer A and Timer B PWM
+// signals and Timer B PWM ouput is Timer B PWM signal only.
+#define GPT_ANDCCP_CCP_AND_EN 0x00000001
+#define GPT_ANDCCP_CCP_AND_EN_BITN 0
+#define GPT_ANDCCP_CCP_AND_EN_M 0x00000001
+#define GPT_ANDCCP_CCP_AND_EN_S 0
+
+
+#endif // __GPT__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_i2c.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_i2c.h
new file mode 100644
index 0000000..7408570
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_i2c.h
@@ -0,0 +1,728 @@
+/******************************************************************************
+* Filename: hw_i2c_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_I2C_H__
+#define __HW_I2C_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// I2C component
+//
+//*****************************************************************************
+// Slave Own Address
+#define I2C_O_SOAR 0x00000000
+
+// Slave Status
+#define I2C_O_SSTAT 0x00000004
+
+// Slave Control
+#define I2C_O_SCTL 0x00000004
+
+// Slave Data
+#define I2C_O_SDR 0x00000008
+
+// Slave Interrupt Mask
+#define I2C_O_SIMR 0x0000000C
+
+// Slave Raw Interrupt Status
+#define I2C_O_SRIS 0x00000010
+
+// Slave Masked Interrupt Status
+#define I2C_O_SMIS 0x00000014
+
+// Slave Interrupt Clear
+#define I2C_O_SICR 0x00000018
+
+// Master Salve Address
+#define I2C_O_MSA 0x00000800
+
+// Master Status
+#define I2C_O_MSTAT 0x00000804
+
+// Master Control
+#define I2C_O_MCTRL 0x00000804
+
+// Master Data
+#define I2C_O_MDR 0x00000808
+
+// I2C Master Timer Period
+#define I2C_O_MTPR 0x0000080C
+
+// Master Interrupt Mask
+#define I2C_O_MIMR 0x00000810
+
+// Master Raw Interrupt Status
+#define I2C_O_MRIS 0x00000814
+
+// Master Masked Interrupt Status
+#define I2C_O_MMIS 0x00000818
+
+// Master Interrupt Clear
+#define I2C_O_MICR 0x0000081C
+
+// Master Configuration
+#define I2C_O_MCR 0x00000820
+
+//*****************************************************************************
+//
+// Register: I2C_O_SOAR
+//
+//*****************************************************************************
+// Field: [6:0] OAR
+//
+// I2C slave own address
+// This field specifies bits a6 through a0 of the slave address.
+#define I2C_SOAR_OAR_W 7
+#define I2C_SOAR_OAR_M 0x0000007F
+#define I2C_SOAR_OAR_S 0
+
+//*****************************************************************************
+//
+// Register: I2C_O_SSTAT
+//
+//*****************************************************************************
+// Field: [2] FBR
+//
+// First byte received
+//
+// 0: The first byte has not been received.
+// 1: The first byte following the slave's own address has been received.
+//
+// This bit is only valid when the RREQ bit is set and is automatically cleared
+// when data has been read from the SDR register.
+// Note: This bit is not used for slave transmit operations.
+#define I2C_SSTAT_FBR 0x00000004
+#define I2C_SSTAT_FBR_BITN 2
+#define I2C_SSTAT_FBR_M 0x00000004
+#define I2C_SSTAT_FBR_S 2
+
+// Field: [1] TREQ
+//
+// Transmit request
+//
+// 0: No outstanding transmit request.
+// 1: The I2C controller has been addressed as a slave transmitter and is using
+// clock stretching to delay the master until data has been written to the SDR
+// register.
+#define I2C_SSTAT_TREQ 0x00000002
+#define I2C_SSTAT_TREQ_BITN 1
+#define I2C_SSTAT_TREQ_M 0x00000002
+#define I2C_SSTAT_TREQ_S 1
+
+// Field: [0] RREQ
+//
+// Receive request
+//
+// 0: No outstanding receive data
+// 1: The I2C controller has outstanding receive data from the I2C master and
+// is using clock stretching to delay the master until data has been read from
+// the SDR register.
+#define I2C_SSTAT_RREQ 0x00000001
+#define I2C_SSTAT_RREQ_BITN 0
+#define I2C_SSTAT_RREQ_M 0x00000001
+#define I2C_SSTAT_RREQ_S 0
+
+//*****************************************************************************
+//
+// Register: I2C_O_SCTL
+//
+//*****************************************************************************
+// Field: [0] DA
+//
+// Device active
+//
+// 0: Disables the I2C slave operation
+// 1: Enables the I2C slave operation
+#define I2C_SCTL_DA 0x00000001
+#define I2C_SCTL_DA_BITN 0
+#define I2C_SCTL_DA_M 0x00000001
+#define I2C_SCTL_DA_S 0
+
+//*****************************************************************************
+//
+// Register: I2C_O_SDR
+//
+//*****************************************************************************
+// Field: [7:0] DATA
+//
+// Data for transfer
+// This field contains the data for transfer during a slave receive or transmit
+// operation. When written the register data is used as transmit data. When
+// read, this register returns the last data received.
+// Data is stored until next update, either by a system write for transmit or
+// by an external master for receive.
+#define I2C_SDR_DATA_W 8
+#define I2C_SDR_DATA_M 0x000000FF
+#define I2C_SDR_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: I2C_O_SIMR
+//
+//*****************************************************************************
+// Field: [2] STOPIM
+//
+// Stop condition interrupt mask
+//
+// 0: The SRIS.STOPRIS interrupt is suppressed and not sent to the interrupt
+// controller.
+// 1: The SRIS.STOPRIS interrupt is enabled and sent to the interrupt
+// controller.
+// ENUMs:
+// EN Enable Interrupt
+// DIS Disable Interrupt
+#define I2C_SIMR_STOPIM 0x00000004
+#define I2C_SIMR_STOPIM_BITN 2
+#define I2C_SIMR_STOPIM_M 0x00000004
+#define I2C_SIMR_STOPIM_S 2
+#define I2C_SIMR_STOPIM_EN 0x00000004
+#define I2C_SIMR_STOPIM_DIS 0x00000000
+
+// Field: [1] STARTIM
+//
+// Start condition interrupt mask
+//
+// 0: The SRIS.STARTRIS interrupt is suppressed and not sent to the interrupt
+// controller.
+// 1: The SRIS.STARTRIS interrupt is enabled and sent to the interrupt
+// controller.
+// ENUMs:
+// EN Enable Interrupt
+// DIS Disable Interrupt
+#define I2C_SIMR_STARTIM 0x00000002
+#define I2C_SIMR_STARTIM_BITN 1
+#define I2C_SIMR_STARTIM_M 0x00000002
+#define I2C_SIMR_STARTIM_S 1
+#define I2C_SIMR_STARTIM_EN 0x00000002
+#define I2C_SIMR_STARTIM_DIS 0x00000000
+
+// Field: [0] DATAIM
+//
+// Data interrupt mask
+//
+// 0: The SRIS.DATARIS interrupt is suppressed and not sent to the interrupt
+// controller.
+// 1: The SRIS.DATARIS interrupt is enabled and sent to the interrupt
+// controller.
+#define I2C_SIMR_DATAIM 0x00000001
+#define I2C_SIMR_DATAIM_BITN 0
+#define I2C_SIMR_DATAIM_M 0x00000001
+#define I2C_SIMR_DATAIM_S 0
+
+//*****************************************************************************
+//
+// Register: I2C_O_SRIS
+//
+//*****************************************************************************
+// Field: [2] STOPRIS
+//
+// Stop condition raw interrupt status
+//
+// 0: No interrupt
+// 1: A Stop condition interrupt is pending.
+//
+// This bit is cleared by writing a 1 to SICR.STOPIC.
+#define I2C_SRIS_STOPRIS 0x00000004
+#define I2C_SRIS_STOPRIS_BITN 2
+#define I2C_SRIS_STOPRIS_M 0x00000004
+#define I2C_SRIS_STOPRIS_S 2
+
+// Field: [1] STARTRIS
+//
+// Start condition raw interrupt status
+//
+// 0: No interrupt
+// 1: A Start condition interrupt is pending.
+//
+// This bit is cleared by writing a 1 to SICR.STARTIC.
+#define I2C_SRIS_STARTRIS 0x00000002
+#define I2C_SRIS_STARTRIS_BITN 1
+#define I2C_SRIS_STARTRIS_M 0x00000002
+#define I2C_SRIS_STARTRIS_S 1
+
+// Field: [0] DATARIS
+//
+// Data raw interrupt status
+//
+// 0: No interrupt
+// 1: A data received or data requested interrupt is pending.
+//
+// This bit is cleared by writing a 1 to the SICR.DATAIC.
+#define I2C_SRIS_DATARIS 0x00000001
+#define I2C_SRIS_DATARIS_BITN 0
+#define I2C_SRIS_DATARIS_M 0x00000001
+#define I2C_SRIS_DATARIS_S 0
+
+//*****************************************************************************
+//
+// Register: I2C_O_SMIS
+//
+//*****************************************************************************
+// Field: [2] STOPMIS
+//
+// Stop condition masked interrupt status
+//
+// 0: An interrupt has not occurred or is masked/disabled.
+// 1: An unmasked Stop condition interrupt is pending.
+//
+// This bit is cleared by writing a 1 to the SICR.STOPIC.
+#define I2C_SMIS_STOPMIS 0x00000004
+#define I2C_SMIS_STOPMIS_BITN 2
+#define I2C_SMIS_STOPMIS_M 0x00000004
+#define I2C_SMIS_STOPMIS_S 2
+
+// Field: [1] STARTMIS
+//
+// Start condition masked interrupt status
+//
+// 0: An interrupt has not occurred or is masked/disabled.
+// 1: An unmasked Start condition interrupt is pending.
+//
+// This bit is cleared by writing a 1 to the SICR.STARTIC.
+#define I2C_SMIS_STARTMIS 0x00000002
+#define I2C_SMIS_STARTMIS_BITN 1
+#define I2C_SMIS_STARTMIS_M 0x00000002
+#define I2C_SMIS_STARTMIS_S 1
+
+// Field: [0] DATAMIS
+//
+// Data masked interrupt status
+//
+// 0: An interrupt has not occurred or is masked/disabled.
+// 1: An unmasked data received or data requested interrupt is pending.
+//
+// This bit is cleared by writing a 1 to the SICR.DATAIC.
+#define I2C_SMIS_DATAMIS 0x00000001
+#define I2C_SMIS_DATAMIS_BITN 0
+#define I2C_SMIS_DATAMIS_M 0x00000001
+#define I2C_SMIS_DATAMIS_S 0
+
+//*****************************************************************************
+//
+// Register: I2C_O_SICR
+//
+//*****************************************************************************
+// Field: [2] STOPIC
+//
+// Stop condition interrupt clear
+//
+// Writing 1 to this bit clears SRIS.STOPRIS and SMIS.STOPMIS.
+#define I2C_SICR_STOPIC 0x00000004
+#define I2C_SICR_STOPIC_BITN 2
+#define I2C_SICR_STOPIC_M 0x00000004
+#define I2C_SICR_STOPIC_S 2
+
+// Field: [1] STARTIC
+//
+// Start condition interrupt clear
+//
+// Writing 1 to this bit clears SRIS.STARTRIS SMIS.STARTMIS.
+#define I2C_SICR_STARTIC 0x00000002
+#define I2C_SICR_STARTIC_BITN 1
+#define I2C_SICR_STARTIC_M 0x00000002
+#define I2C_SICR_STARTIC_S 1
+
+// Field: [0] DATAIC
+//
+// Data interrupt clear
+//
+// Writing 1 to this bit clears SRIS.DATARIS SMIS.DATAMIS.
+#define I2C_SICR_DATAIC 0x00000001
+#define I2C_SICR_DATAIC_BITN 0
+#define I2C_SICR_DATAIC_M 0x00000001
+#define I2C_SICR_DATAIC_S 0
+
+//*****************************************************************************
+//
+// Register: I2C_O_MSA
+//
+//*****************************************************************************
+// Field: [7:1] SA
+//
+// I2C master slave address
+// Defines which slave is addressed for the transaction in master mode
+#define I2C_MSA_SA_W 7
+#define I2C_MSA_SA_M 0x000000FE
+#define I2C_MSA_SA_S 1
+
+// Field: [0] RS
+//
+// Receive or Send
+// This bit-field specifies if the next operation is a receive (high) or a
+// transmit/send (low) from the addressed slave SA.
+// ENUMs:
+// RX Receive data from slave
+// TX Transmit/send data to slave
+#define I2C_MSA_RS 0x00000001
+#define I2C_MSA_RS_BITN 0
+#define I2C_MSA_RS_M 0x00000001
+#define I2C_MSA_RS_S 0
+#define I2C_MSA_RS_RX 0x00000001
+#define I2C_MSA_RS_TX 0x00000000
+
+//*****************************************************************************
+//
+// Register: I2C_O_MSTAT
+//
+//*****************************************************************************
+// Field: [6] BUSBSY
+//
+// Bus busy
+//
+// 0: The I2C bus is idle.
+// 1: The I2C bus is busy.
+//
+// The bit changes based on the MCTRL.START and MCTRL.STOP conditions.
+#define I2C_MSTAT_BUSBSY 0x00000040
+#define I2C_MSTAT_BUSBSY_BITN 6
+#define I2C_MSTAT_BUSBSY_M 0x00000040
+#define I2C_MSTAT_BUSBSY_S 6
+
+// Field: [5] IDLE
+//
+// I2C idle
+//
+// 0: The I2C controller is not idle.
+// 1: The I2C controller is idle.
+#define I2C_MSTAT_IDLE 0x00000020
+#define I2C_MSTAT_IDLE_BITN 5
+#define I2C_MSTAT_IDLE_M 0x00000020
+#define I2C_MSTAT_IDLE_S 5
+
+// Field: [4] ARBLST
+//
+// Arbitration lost
+//
+// 0: The I2C controller won arbitration.
+// 1: The I2C controller lost arbitration.
+#define I2C_MSTAT_ARBLST 0x00000010
+#define I2C_MSTAT_ARBLST_BITN 4
+#define I2C_MSTAT_ARBLST_M 0x00000010
+#define I2C_MSTAT_ARBLST_S 4
+
+// Field: [3] DATACK_N
+//
+// Data Was Not Acknowledge
+//
+// 0: The transmitted data was acknowledged.
+// 1: The transmitted data was not acknowledged.
+#define I2C_MSTAT_DATACK_N 0x00000008
+#define I2C_MSTAT_DATACK_N_BITN 3
+#define I2C_MSTAT_DATACK_N_M 0x00000008
+#define I2C_MSTAT_DATACK_N_S 3
+
+// Field: [2] ADRACK_N
+//
+// Address Was Not Acknowledge
+//
+// 0: The transmitted address was acknowledged.
+// 1: The transmitted address was not acknowledged.
+#define I2C_MSTAT_ADRACK_N 0x00000004
+#define I2C_MSTAT_ADRACK_N_BITN 2
+#define I2C_MSTAT_ADRACK_N_M 0x00000004
+#define I2C_MSTAT_ADRACK_N_S 2
+
+// Field: [1] ERR
+//
+// Error
+//
+// 0: No error was detected on the last operation.
+// 1: An error occurred on the last operation.
+#define I2C_MSTAT_ERR 0x00000002
+#define I2C_MSTAT_ERR_BITN 1
+#define I2C_MSTAT_ERR_M 0x00000002
+#define I2C_MSTAT_ERR_S 1
+
+// Field: [0] BUSY
+//
+// I2C busy
+//
+// 0: The controller is idle.
+// 1: The controller is busy.
+//
+// When this bit-field is set, the other status bits are not valid.
+//
+// Note: The I2C controller requires four SYSBUS clock cycles to assert the
+// BUSY status after I2C master operation has been initiated through MCTRL
+// register.
+// Hence after programming MCTRL register, application is requested to wait for
+// four SYSBUS clock cycles before issuing a controller status inquiry through
+// MSTAT register.
+// Any prior inquiry would result in wrong status being reported.
+#define I2C_MSTAT_BUSY 0x00000001
+#define I2C_MSTAT_BUSY_BITN 0
+#define I2C_MSTAT_BUSY_M 0x00000001
+#define I2C_MSTAT_BUSY_S 0
+
+//*****************************************************************************
+//
+// Register: I2C_O_MCTRL
+//
+//*****************************************************************************
+// Field: [3] ACK
+//
+// Data acknowledge enable
+//
+// 0: The received data byte is not acknowledged automatically by the master.
+// 1: The received data byte is acknowledged automatically by the master.
+//
+// This bit-field must be cleared when the I2C bus controller requires no
+// further data to be transmitted from the slave transmitter.
+// ENUMs:
+// EN Enable acknowledge
+// DIS Disable acknowledge
+#define I2C_MCTRL_ACK 0x00000008
+#define I2C_MCTRL_ACK_BITN 3
+#define I2C_MCTRL_ACK_M 0x00000008
+#define I2C_MCTRL_ACK_S 3
+#define I2C_MCTRL_ACK_EN 0x00000008
+#define I2C_MCTRL_ACK_DIS 0x00000000
+
+// Field: [2] STOP
+//
+// This bit-field determines if the cycle stops at the end of the data cycle or
+// continues on to a repeated START condition.
+//
+// 0: The controller does not generate the Stop condition.
+// 1: The controller generates the Stop condition.
+// ENUMs:
+// EN Enable STOP
+// DIS Disable STOP
+#define I2C_MCTRL_STOP 0x00000004
+#define I2C_MCTRL_STOP_BITN 2
+#define I2C_MCTRL_STOP_M 0x00000004
+#define I2C_MCTRL_STOP_S 2
+#define I2C_MCTRL_STOP_EN 0x00000004
+#define I2C_MCTRL_STOP_DIS 0x00000000
+
+// Field: [1] START
+//
+// This bit-field generates the Start or Repeated Start condition.
+//
+// 0: The controller does not generate the Start condition.
+// 1: The controller generates the Start condition.
+// ENUMs:
+// EN Enable START
+// DIS Disable START
+#define I2C_MCTRL_START 0x00000002
+#define I2C_MCTRL_START_BITN 1
+#define I2C_MCTRL_START_M 0x00000002
+#define I2C_MCTRL_START_S 1
+#define I2C_MCTRL_START_EN 0x00000002
+#define I2C_MCTRL_START_DIS 0x00000000
+
+// Field: [0] RUN
+//
+// I2C master enable
+//
+// 0: The master is disabled.
+// 1: The master is enabled to transmit or receive data.
+// ENUMs:
+// EN Enable Master
+// DIS Disable Master
+#define I2C_MCTRL_RUN 0x00000001
+#define I2C_MCTRL_RUN_BITN 0
+#define I2C_MCTRL_RUN_M 0x00000001
+#define I2C_MCTRL_RUN_S 0
+#define I2C_MCTRL_RUN_EN 0x00000001
+#define I2C_MCTRL_RUN_DIS 0x00000000
+
+//*****************************************************************************
+//
+// Register: I2C_O_MDR
+//
+//*****************************************************************************
+// Field: [7:0] DATA
+//
+// When Read: Last RX Data is returned
+// When Written: Data is transferred during TX transaction
+#define I2C_MDR_DATA_W 8
+#define I2C_MDR_DATA_M 0x000000FF
+#define I2C_MDR_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: I2C_O_MTPR
+//
+//*****************************************************************************
+// Field: [7] TPR_7
+//
+// Must be set to 0 to set TPR. If set to 1, a write to TPR will be ignored.
+#define I2C_MTPR_TPR_7 0x00000080
+#define I2C_MTPR_TPR_7_BITN 7
+#define I2C_MTPR_TPR_7_M 0x00000080
+#define I2C_MTPR_TPR_7_S 7
+
+// Field: [6:0] TPR
+//
+// SCL clock period
+// This field specifies the period of the SCL clock.
+// SCL_PRD = 2*(1+TPR)*(SCL_LP + SCL_HP)*CLK_PRD
+// where:
+// SCL_PRD is the SCL line period (I2C clock).
+// TPR is the timer period register value (range of 1 to 127)
+// SCL_LP is the SCL low period (fixed at 6).
+// SCL_HP is the SCL high period (fixed at 4).
+// CLK_PRD is the system clock period in ns.
+#define I2C_MTPR_TPR_W 7
+#define I2C_MTPR_TPR_M 0x0000007F
+#define I2C_MTPR_TPR_S 0
+
+//*****************************************************************************
+//
+// Register: I2C_O_MIMR
+//
+//*****************************************************************************
+// Field: [0] IM
+//
+// Interrupt mask
+//
+// 0: The MRIS.RIS interrupt is suppressed and not sent to the interrupt
+// controller.
+// 1: The master interrupt is sent to the interrupt controller when the
+// MRIS.RIS is set.
+// ENUMs:
+// EN Enable Interrupt
+// DIS Disable Interrupt
+#define I2C_MIMR_IM 0x00000001
+#define I2C_MIMR_IM_BITN 0
+#define I2C_MIMR_IM_M 0x00000001
+#define I2C_MIMR_IM_S 0
+#define I2C_MIMR_IM_EN 0x00000001
+#define I2C_MIMR_IM_DIS 0x00000000
+
+//*****************************************************************************
+//
+// Register: I2C_O_MRIS
+//
+//*****************************************************************************
+// Field: [0] RIS
+//
+// Raw interrupt status
+//
+// 0: No interrupt
+// 1: A master interrupt is pending.
+//
+// This bit is cleared by writing 1 to the MICR.IC bit .
+#define I2C_MRIS_RIS 0x00000001
+#define I2C_MRIS_RIS_BITN 0
+#define I2C_MRIS_RIS_M 0x00000001
+#define I2C_MRIS_RIS_S 0
+
+//*****************************************************************************
+//
+// Register: I2C_O_MMIS
+//
+//*****************************************************************************
+// Field: [0] MIS
+//
+// Masked interrupt status
+//
+// 0: An interrupt has not occurred or is masked.
+// 1: A master interrupt is pending.
+//
+// This bit is cleared by writing 1 to the MICR.IC bit .
+#define I2C_MMIS_MIS 0x00000001
+#define I2C_MMIS_MIS_BITN 0
+#define I2C_MMIS_MIS_M 0x00000001
+#define I2C_MMIS_MIS_S 0
+
+//*****************************************************************************
+//
+// Register: I2C_O_MICR
+//
+//*****************************************************************************
+// Field: [0] IC
+//
+// Interrupt clear
+// Writing 1 to this bit clears MRIS.RIS and MMIS.MIS .
+//
+// Reading this register returns no meaningful data.
+#define I2C_MICR_IC 0x00000001
+#define I2C_MICR_IC_BITN 0
+#define I2C_MICR_IC_M 0x00000001
+#define I2C_MICR_IC_S 0
+
+//*****************************************************************************
+//
+// Register: I2C_O_MCR
+//
+//*****************************************************************************
+// Field: [5] SFE
+//
+// I2C slave function enable
+// ENUMs:
+// EN Slave mode is enabled.
+// DIS Slave mode is disabled.
+#define I2C_MCR_SFE 0x00000020
+#define I2C_MCR_SFE_BITN 5
+#define I2C_MCR_SFE_M 0x00000020
+#define I2C_MCR_SFE_S 5
+#define I2C_MCR_SFE_EN 0x00000020
+#define I2C_MCR_SFE_DIS 0x00000000
+
+// Field: [4] MFE
+//
+// I2C master function enable
+// ENUMs:
+// EN Master mode is enabled.
+// DIS Master mode is disabled.
+#define I2C_MCR_MFE 0x00000010
+#define I2C_MCR_MFE_BITN 4
+#define I2C_MCR_MFE_M 0x00000010
+#define I2C_MCR_MFE_S 4
+#define I2C_MCR_MFE_EN 0x00000010
+#define I2C_MCR_MFE_DIS 0x00000000
+
+// Field: [0] LPBK
+//
+// I2C loopback
+//
+// 0: Normal operation
+// 1: Loopback operation (test mode)
+// ENUMs:
+// EN Enable Test Mode
+// DIS Disable Test Mode
+#define I2C_MCR_LPBK 0x00000001
+#define I2C_MCR_LPBK_BITN 0
+#define I2C_MCR_LPBK_M 0x00000001
+#define I2C_MCR_LPBK_S 0
+#define I2C_MCR_LPBK_EN 0x00000001
+#define I2C_MCR_LPBK_DIS 0x00000000
+
+
+#endif // __I2C__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_i2s.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_i2s.h
new file mode 100644
index 0000000..c7ed79a
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_i2s.h
@@ -0,0 +1,967 @@
+/******************************************************************************
+* Filename: hw_i2s_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_I2S_H__
+#define __HW_I2S_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// I2S component
+//
+//*****************************************************************************
+// WCLK Source Selection
+#define I2S_O_AIFWCLKSRC 0x00000000
+
+// DMA Buffer Size Configuration
+#define I2S_O_AIFDMACFG 0x00000004
+
+// Pin Direction
+#define I2S_O_AIFDIRCFG 0x00000008
+
+// Serial Interface Format Configuration
+#define I2S_O_AIFFMTCFG 0x0000000C
+
+// Word Selection Bit Mask for Pin 0
+#define I2S_O_AIFWMASK0 0x00000010
+
+// Word Selection Bit Mask for Pin 1
+#define I2S_O_AIFWMASK1 0x00000014
+
+// Audio Interface PWM Debug Value
+#define I2S_O_AIFPWMVALUE 0x0000001C
+
+// DMA Input Buffer Next Pointer
+#define I2S_O_AIFINPTRNEXT 0x00000020
+
+// DMA Input Buffer Current Pointer
+#define I2S_O_AIFINPTR 0x00000024
+
+// DMA Output Buffer Next Pointer
+#define I2S_O_AIFOUTPTRNEXT 0x00000028
+
+// DMA Output Buffer Current Pointer
+#define I2S_O_AIFOUTPTR 0x0000002C
+
+// Samplestamp Generator Control Register
+#define I2S_O_STMPCTL 0x00000034
+
+// Captured XOSC Counter Value, Capture Channel 0
+#define I2S_O_STMPXCNTCAPT0 0x00000038
+
+// XOSC Period Value
+#define I2S_O_STMPXPER 0x0000003C
+
+// Captured WCLK Counter Value, Capture Channel 0
+#define I2S_O_STMPWCNTCAPT0 0x00000040
+
+// WCLK Counter Period Value
+#define I2S_O_STMPWPER 0x00000044
+
+// WCLK Counter Trigger Value for Input Pins
+#define I2S_O_STMPINTRIG 0x00000048
+
+// WCLK Counter Trigger Value for Output Pins
+#define I2S_O_STMPOUTTRIG 0x0000004C
+
+// WCLK Counter Set Operation
+#define I2S_O_STMPWSET 0x00000050
+
+// WCLK Counter Add Operation
+#define I2S_O_STMPWADD 0x00000054
+
+// XOSC Minimum Period Value
+#define I2S_O_STMPXPERMIN 0x00000058
+
+// Current Value of WCNT
+#define I2S_O_STMPWCNT 0x0000005C
+
+// Current Value of XCNT
+#define I2S_O_STMPXCNT 0x00000060
+
+// Internal
+#define I2S_O_STMPXCNTCAPT1 0x00000064
+
+// Internal
+#define I2S_O_STMPWCNTCAPT1 0x00000068
+
+// Interrupt Mask Register
+#define I2S_O_IRQMASK 0x00000070
+
+// Raw Interrupt Status Register
+#define I2S_O_IRQFLAGS 0x00000074
+
+// Interrupt Set Register
+#define I2S_O_IRQSET 0x00000078
+
+// Interrupt Clear Register
+#define I2S_O_IRQCLR 0x0000007C
+
+//*****************************************************************************
+//
+// Register: I2S_O_AIFWCLKSRC
+//
+//*****************************************************************************
+// Field: [2] WCLK_INV
+//
+// Inverts WCLK source (pad or internal) when set.
+//
+// 0: Not inverted
+// 1: Inverted
+#define I2S_AIFWCLKSRC_WCLK_INV 0x00000004
+#define I2S_AIFWCLKSRC_WCLK_INV_BITN 2
+#define I2S_AIFWCLKSRC_WCLK_INV_M 0x00000004
+#define I2S_AIFWCLKSRC_WCLK_INV_S 2
+
+// Field: [1:0] WCLK_SRC
+//
+// Selects WCLK source for AIF (should be the same as the BCLK source). The
+// BCLK source is defined in the PRCM:I2SBCLKSEL.SRC
+// ENUMs:
+// RESERVED Not supported. Will give same WCLK as 'NONE'
+// ('00')
+// INT Internal WCLK generator, from module PRCM
+// EXT External WCLK generator, from pad
+// NONE None ('0')
+#define I2S_AIFWCLKSRC_WCLK_SRC_W 2
+#define I2S_AIFWCLKSRC_WCLK_SRC_M 0x00000003
+#define I2S_AIFWCLKSRC_WCLK_SRC_S 0
+#define I2S_AIFWCLKSRC_WCLK_SRC_RESERVED 0x00000003
+#define I2S_AIFWCLKSRC_WCLK_SRC_INT 0x00000002
+#define I2S_AIFWCLKSRC_WCLK_SRC_EXT 0x00000001
+#define I2S_AIFWCLKSRC_WCLK_SRC_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Register: I2S_O_AIFDMACFG
+//
+//*****************************************************************************
+// Field: [7:0] END_FRAME_IDX
+//
+// Defines the length of the DMA buffer. Writing a non-zero value to this
+// register field enables and initializes AIF. Note that before doing so, all
+// other configuration must have been done, and AIFINPTRNEXT/AIFOUTPTRNEXT must
+// have been loaded.
+#define I2S_AIFDMACFG_END_FRAME_IDX_W 8
+#define I2S_AIFDMACFG_END_FRAME_IDX_M 0x000000FF
+#define I2S_AIFDMACFG_END_FRAME_IDX_S 0
+
+//*****************************************************************************
+//
+// Register: I2S_O_AIFDIRCFG
+//
+//*****************************************************************************
+// Field: [5:4] AD1
+//
+// Configures the AD1 audio data pin usage:
+//
+// 0x3: Reserved
+// ENUMs:
+// OUT Output mode
+// IN Input mode
+// DIS Not in use (disabled)
+#define I2S_AIFDIRCFG_AD1_W 2
+#define I2S_AIFDIRCFG_AD1_M 0x00000030
+#define I2S_AIFDIRCFG_AD1_S 4
+#define I2S_AIFDIRCFG_AD1_OUT 0x00000020
+#define I2S_AIFDIRCFG_AD1_IN 0x00000010
+#define I2S_AIFDIRCFG_AD1_DIS 0x00000000
+
+// Field: [1:0] AD0
+//
+// Configures the AD0 audio data pin usage:
+//
+// 0x3: Reserved
+// ENUMs:
+// OUT Output mode
+// IN Input mode
+// DIS Not in use (disabled)
+#define I2S_AIFDIRCFG_AD0_W 2
+#define I2S_AIFDIRCFG_AD0_M 0x00000003
+#define I2S_AIFDIRCFG_AD0_S 0
+#define I2S_AIFDIRCFG_AD0_OUT 0x00000002
+#define I2S_AIFDIRCFG_AD0_IN 0x00000001
+#define I2S_AIFDIRCFG_AD0_DIS 0x00000000
+
+//*****************************************************************************
+//
+// Register: I2S_O_AIFFMTCFG
+//
+//*****************************************************************************
+// Field: [15:8] DATA_DELAY
+//
+// The number of BCLK periods between a WCLK edge and MSB of the first word in
+// a phase:
+//
+// 0x00: LJF and DSP format
+// 0x01: I2S and DSP format
+// 0x02: RJF format
+// ...
+// 0xFF: RJF format
+//
+// Note: When 0, MSB of the next word will be output in the idle period between
+// LSB of the previous word and the start of the next word. Otherwise logical 0
+// will be output until the data delay has expired.
+#define I2S_AIFFMTCFG_DATA_DELAY_W 8
+#define I2S_AIFFMTCFG_DATA_DELAY_M 0x0000FF00
+#define I2S_AIFFMTCFG_DATA_DELAY_S 8
+
+// Field: [7] MEM_LEN_24
+//
+// The size of each word stored to or loaded from memory:
+// ENUMs:
+// 24BIT 24-bit (one 8 bit and one 16 bit locked access per
+// sample)
+// 16BIT 16-bit (one 16 bit access per sample)
+#define I2S_AIFFMTCFG_MEM_LEN_24 0x00000080
+#define I2S_AIFFMTCFG_MEM_LEN_24_BITN 7
+#define I2S_AIFFMTCFG_MEM_LEN_24_M 0x00000080
+#define I2S_AIFFMTCFG_MEM_LEN_24_S 7
+#define I2S_AIFFMTCFG_MEM_LEN_24_24BIT 0x00000080
+#define I2S_AIFFMTCFG_MEM_LEN_24_16BIT 0x00000000
+
+// Field: [6] SMPL_EDGE
+//
+// On the serial audio interface, data (and wclk) is sampled and clocked out on
+// opposite edges of BCLK.
+// ENUMs:
+// POS Data is sampled on the positive edge and clocked
+// out on the negative edge.
+// NEG Data is sampled on the negative edge and clocked
+// out on the positive edge.
+#define I2S_AIFFMTCFG_SMPL_EDGE 0x00000040
+#define I2S_AIFFMTCFG_SMPL_EDGE_BITN 6
+#define I2S_AIFFMTCFG_SMPL_EDGE_M 0x00000040
+#define I2S_AIFFMTCFG_SMPL_EDGE_S 6
+#define I2S_AIFFMTCFG_SMPL_EDGE_POS 0x00000040
+#define I2S_AIFFMTCFG_SMPL_EDGE_NEG 0x00000000
+
+// Field: [5] DUAL_PHASE
+//
+// Selects dual- or single-phase format.
+//
+// 0: Single-phase: DSP format
+// 1: Dual-phase: I2S, LJF and RJF formats
+#define I2S_AIFFMTCFG_DUAL_PHASE 0x00000020
+#define I2S_AIFFMTCFG_DUAL_PHASE_BITN 5
+#define I2S_AIFFMTCFG_DUAL_PHASE_M 0x00000020
+#define I2S_AIFFMTCFG_DUAL_PHASE_S 5
+
+// Field: [4:0] WORD_LEN
+//
+// Number of bits per word (8-24):
+// In single-phase format, this is the exact number of bits per word.
+// In dual-phase format, this is the maximum number of bits per word.
+//
+// Values below 8 and above 24 give undefined behavior. Data written to memory
+// is always aligned to 16 or 24 bits as defined by MEM_LEN_24. Bit widths that
+// differ from this alignment will either be truncated or zero padded.
+#define I2S_AIFFMTCFG_WORD_LEN_W 5
+#define I2S_AIFFMTCFG_WORD_LEN_M 0x0000001F
+#define I2S_AIFFMTCFG_WORD_LEN_S 0
+
+//*****************************************************************************
+//
+// Register: I2S_O_AIFWMASK0
+//
+//*****************************************************************************
+// Field: [7:0] MASK
+//
+// Bit-mask indicating valid channels in a frame on AD0.
+//
+// In single-phase mode, each bit represents one channel, starting with LSB for
+// the first word in the frame. A frame can contain up to 8 channels. Channels
+// that are not included in the mask will not be sampled and stored in memory,
+// and clocked out as '0'.
+//
+// In dual-phase mode, only the two LSBs are considered. For a stereo
+// configuration, set both bits. For a mono configuration, set bit 0 only. In
+// mono mode, only channel 0 will be sampled and stored to memory, and channel
+// 0 will be repeated when clocked out.
+//
+// In mono mode, only channel 0 will be sampled and stored to memory, and
+// channel 0 will be repeated in the second phase when clocked out.
+//
+// If all bits are zero, no input words will be stored to memory, and the
+// output data lines will be constant '0'. This can be utilized when PWM debug
+// output is desired without any actively used output pins.
+#define I2S_AIFWMASK0_MASK_W 8
+#define I2S_AIFWMASK0_MASK_M 0x000000FF
+#define I2S_AIFWMASK0_MASK_S 0
+
+//*****************************************************************************
+//
+// Register: I2S_O_AIFWMASK1
+//
+//*****************************************************************************
+// Field: [7:0] MASK
+//
+// Bit-mask indicating valid channels in a frame on AD1.
+//
+// In single-phase mode, each bit represents one channel, starting with LSB for
+// the first word in the frame. A frame can contain up to 8 channels. Channels
+// that are not included in the mask will not be sampled and stored in memory,
+// and clocked out as '0'.
+//
+// In dual-phase mode, only the two LSBs are considered. For a stereo
+// configuration, set both bits. For a mono configuration, set bit 0 only. In
+// mono mode, only channel 0 will be sampled and stored to memory, and channel
+// 0 will be repeated when clocked out.
+//
+// In mono mode, only channel 0 will be sampled and stored to memory, and
+// channel 0 will be repeated in the second phase when clocked out.
+//
+// If all bits are zero, no input words will be stored to memory, and the
+// output data lines will be constant '0'. This can be utilized when PWM debug
+// output is desired without any actively used output pins.
+#define I2S_AIFWMASK1_MASK_W 8
+#define I2S_AIFWMASK1_MASK_M 0x000000FF
+#define I2S_AIFWMASK1_MASK_S 0
+
+//*****************************************************************************
+//
+// Register: I2S_O_AIFPWMVALUE
+//
+//*****************************************************************************
+// Field: [15:0] PULSE_WIDTH
+//
+// The value written to this register determines the width of the active high
+// PWM pulse (pwm_debug), which starts together with MSB of the first output
+// word in a DMA buffer:
+//
+// 0x0000: Constant low
+// 0x0001: Width of the pulse (number of BCLK cycles, here 1).
+// ...
+// 0xFFFE: Width of the pulse (number of BCLK cycles, here 65534).
+// 0xFFFF: Constant high
+#define I2S_AIFPWMVALUE_PULSE_WIDTH_W 16
+#define I2S_AIFPWMVALUE_PULSE_WIDTH_M 0x0000FFFF
+#define I2S_AIFPWMVALUE_PULSE_WIDTH_S 0
+
+//*****************************************************************************
+//
+// Register: I2S_O_AIFINPTRNEXT
+//
+//*****************************************************************************
+// Field: [31:0] PTR
+//
+// Pointer to the first byte in the next DMA input buffer.
+//
+// The read value equals the last written value until the currently used DMA
+// input buffer is completed, and then becomes null when the last written value
+// is transferred to the DMA controller to start on the next buffer. This event
+// is signalized by IRQFLAGS.AIF_DMA_IN.
+//
+// At startup, the value must be written once before and once after configuring
+// the DMA buffer size in AIFDMACFG.
+//
+// The next pointer must be written to this register while the DMA function
+// uses the previously written pointer. If not written in time,
+// IRQFLAGS.PTR_ERR will be raised and all input pins will be disabled.
+#define I2S_AIFINPTRNEXT_PTR_W 32
+#define I2S_AIFINPTRNEXT_PTR_M 0xFFFFFFFF
+#define I2S_AIFINPTRNEXT_PTR_S 0
+
+//*****************************************************************************
+//
+// Register: I2S_O_AIFINPTR
+//
+//*****************************************************************************
+// Field: [31:0] PTR
+//
+// Value of the DMA input buffer pointer currently used by the DMA controller.
+// Incremented by 1 (byte) or 2 (word) for each AHB access.
+#define I2S_AIFINPTR_PTR_W 32
+#define I2S_AIFINPTR_PTR_M 0xFFFFFFFF
+#define I2S_AIFINPTR_PTR_S 0
+
+//*****************************************************************************
+//
+// Register: I2S_O_AIFOUTPTRNEXT
+//
+//*****************************************************************************
+// Field: [31:0] PTR
+//
+// Pointer to the first byte in the next DMA output buffer.
+//
+// The read value equals the last written value until the currently used DMA
+// output buffer is completed, and then becomes null when the last written
+// value is transferred to the DMA controller to start on the next buffer. This
+// event is signalized by IRQFLAGS.AIF_DMA_OUT.
+//
+// At startup, the value must be written once before and once after configuring
+// the DMA buffer size in AIFDMACFG. At this time, the first two samples will
+// be fetched from memory.
+//
+// The next pointer must be written to this register while the DMA function
+// uses the previously written pointer. If not written in time,
+// IRQFLAGS.PTR_ERR will be raised and all output pins will be disabled.
+#define I2S_AIFOUTPTRNEXT_PTR_W 32
+#define I2S_AIFOUTPTRNEXT_PTR_M 0xFFFFFFFF
+#define I2S_AIFOUTPTRNEXT_PTR_S 0
+
+//*****************************************************************************
+//
+// Register: I2S_O_AIFOUTPTR
+//
+//*****************************************************************************
+// Field: [31:0] PTR
+//
+// Value of the DMA output buffer pointer currently used by the DMA controller
+// Incremented by 1 (byte) or 2 (word) for each AHB access.
+#define I2S_AIFOUTPTR_PTR_W 32
+#define I2S_AIFOUTPTR_PTR_M 0xFFFFFFFF
+#define I2S_AIFOUTPTR_PTR_S 0
+
+//*****************************************************************************
+//
+// Register: I2S_O_STMPCTL
+//
+//*****************************************************************************
+// Field: [2] OUT_RDY
+//
+// Low until the output pins are ready to be started by the samplestamp
+// generator. When started (that is STMPOUTTRIG equals the WCLK counter) the
+// bit goes back low.
+#define I2S_STMPCTL_OUT_RDY 0x00000004
+#define I2S_STMPCTL_OUT_RDY_BITN 2
+#define I2S_STMPCTL_OUT_RDY_M 0x00000004
+#define I2S_STMPCTL_OUT_RDY_S 2
+
+// Field: [1] IN_RDY
+//
+// Low until the input pins are ready to be started by the samplestamp
+// generator. When started (that is STMPINTRIG equals the WCLK counter) the bit
+// goes back low.
+#define I2S_STMPCTL_IN_RDY 0x00000002
+#define I2S_STMPCTL_IN_RDY_BITN 1
+#define I2S_STMPCTL_IN_RDY_M 0x00000002
+#define I2S_STMPCTL_IN_RDY_S 1
+
+// Field: [0] STMP_EN
+//
+// Enables the samplestamp generator. The samplestamp generator must only be
+// enabled after it has been properly configured.
+// When cleared, all samplestamp generator counters and capture values are
+// cleared.
+#define I2S_STMPCTL_STMP_EN 0x00000001
+#define I2S_STMPCTL_STMP_EN_BITN 0
+#define I2S_STMPCTL_STMP_EN_M 0x00000001
+#define I2S_STMPCTL_STMP_EN_S 0
+
+//*****************************************************************************
+//
+// Register: I2S_O_STMPXCNTCAPT0
+//
+//*****************************************************************************
+// Field: [15:0] CAPT_VALUE
+//
+// The value of the samplestamp XOSC counter (STMPXCNT.CURR_VALUE) last time an
+// event was pulsed (event source selected in [EVENT.I2SSTMPSEL0.EV] for
+// channel 0). This number corresponds to the number of 24 MHz clock cycles
+// since the last positive edge of the selected WCLK.
+// The value is cleared when STMPCTL.STMP_EN = 0.
+// Note: Due to buffering and synchronization, WCLK is delayed by a small
+// number of BCLK periods and clk periods.
+// Note: When calculating the fractional part of the sample stamp, STMPXPER may
+// be less than this bit field.
+#define I2S_STMPXCNTCAPT0_CAPT_VALUE_W 16
+#define I2S_STMPXCNTCAPT0_CAPT_VALUE_M 0x0000FFFF
+#define I2S_STMPXCNTCAPT0_CAPT_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: I2S_O_STMPXPER
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// The number of 24 MHz clock cycles in the previous WCLK period (that is -
+// the next value of the XOSC counter at the positive WCLK edge, had it not
+// been reset to 0).
+// The value is cleared when STMPCTL.STMP_EN = 0.
+#define I2S_STMPXPER_VALUE_W 16
+#define I2S_STMPXPER_VALUE_M 0x0000FFFF
+#define I2S_STMPXPER_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: I2S_O_STMPWCNTCAPT0
+//
+//*****************************************************************************
+// Field: [15:0] CAPT_VALUE
+//
+// The value of the samplestamp WCLK counter (STMPWCNT.CURR_VALUE) last time an
+// event was pulsed (event source selected in EVENT:I2SSTMPSEL0.EV for channel
+// 0). This number corresponds to the number of positive WCLK edges since the
+// samplestamp generator was enabled (not taking modification through
+// STMPWADD/STMPWSET into account).
+// The value is cleared when STMPCTL.STMP_EN = 0.
+#define I2S_STMPWCNTCAPT0_CAPT_VALUE_W 16
+#define I2S_STMPWCNTCAPT0_CAPT_VALUE_M 0x0000FFFF
+#define I2S_STMPWCNTCAPT0_CAPT_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: I2S_O_STMPWPER
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Used to define when STMPWCNT is to be reset so number of WCLK edges are
+// found for the size of the sample buffer. This is thus a modulo value for the
+// WCLK counter. This number must correspond to the size of the sample buffer
+// used by the system (that is the index of the last sample plus 1).
+#define I2S_STMPWPER_VALUE_W 16
+#define I2S_STMPWPER_VALUE_M 0x0000FFFF
+#define I2S_STMPWPER_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: I2S_O_STMPINTRIG
+//
+//*****************************************************************************
+// Field: [15:0] IN_START_WCNT
+//
+// Compare value used to start the incoming audio streams.
+// This bit field shall equal the WCLK counter value during the WCLK period in
+// which the first input word(s) are sampled and stored to memory (that is the
+// sample at the start of the very first DMA input buffer).
+//
+// The value of this register takes effect when the following conditions are
+// met:
+// - One or more pins are configured as inputs in AIFDIRCFG.
+// - AIFDMACFG has been configured for the correct buffer size, and at least 32
+// BCLK cycle ticks have happened.
+//
+// Note: To avoid false triggers, this bit field should be set higher than
+// STMPWPER.VALUE.
+#define I2S_STMPINTRIG_IN_START_WCNT_W 16
+#define I2S_STMPINTRIG_IN_START_WCNT_M 0x0000FFFF
+#define I2S_STMPINTRIG_IN_START_WCNT_S 0
+
+//*****************************************************************************
+//
+// Register: I2S_O_STMPOUTTRIG
+//
+//*****************************************************************************
+// Field: [15:0] OUT_START_WCNT
+//
+// Compare value used to start the outgoing audio streams.
+//
+// This bit field must equal the WCLK counter value during the WCLK period in
+// which the first output word(s) read from memory are clocked out (that is the
+// sample at the start of the very first DMA output buffer).
+//
+// The value of this register takes effect when the following conditions are
+// met:
+// - One or more pins are configured as outputs in AIFDIRCFG.
+// - AIFDMACFG has been configured for the correct buffer size, and 32 BCLK
+// cycle ticks have happened.
+// - 2 samples have been preloaded from memory (examine the AIFOUTPTR register
+// if necessary).
+// Note: The memory read access is only performed when required, that is
+// channels 0/1 must be selected in AIFWMASK0/AIFWMASK1.
+//
+// Note: To avoid false triggers, this bit field should be set higher than
+// STMPWPER.VALUE.
+#define I2S_STMPOUTTRIG_OUT_START_WCNT_W 16
+#define I2S_STMPOUTTRIG_OUT_START_WCNT_M 0x0000FFFF
+#define I2S_STMPOUTTRIG_OUT_START_WCNT_S 0
+
+//*****************************************************************************
+//
+// Register: I2S_O_STMPWSET
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// WCLK counter modification: Sets the running WCLK counter equal to the
+// written value.
+#define I2S_STMPWSET_VALUE_W 16
+#define I2S_STMPWSET_VALUE_M 0x0000FFFF
+#define I2S_STMPWSET_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: I2S_O_STMPWADD
+//
+//*****************************************************************************
+// Field: [15:0] VALUE_INC
+//
+// WCLK counter modification: Adds the written value to the running WCLK
+// counter. If a positive edge of WCLK occurs at the same time as the
+// operation, this will be taken into account.
+// To add a negative value, write "STMPWPER.VALUE - value".
+//
+#define I2S_STMPWADD_VALUE_INC_W 16
+#define I2S_STMPWADD_VALUE_INC_M 0x0000FFFF
+#define I2S_STMPWADD_VALUE_INC_S 0
+
+//*****************************************************************************
+//
+// Register: I2S_O_STMPXPERMIN
+//
+//*****************************************************************************
+// Field: [15:0] VALUE
+//
+// Each time STMPXPER is updated, the value is also loaded into this register,
+// provided that the value is smaller than the current value in this register.
+// When written, the register is reset to 0xFFFF (65535), regardless of the
+// value written.
+// The minimum value can be used to detect extra WCLK pulses (this registers
+// value will be significantly smaller than STMPXPER.VALUE).
+#define I2S_STMPXPERMIN_VALUE_W 16
+#define I2S_STMPXPERMIN_VALUE_M 0x0000FFFF
+#define I2S_STMPXPERMIN_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: I2S_O_STMPWCNT
+//
+//*****************************************************************************
+// Field: [15:0] CURR_VALUE
+//
+// Current value of the WCLK counter
+#define I2S_STMPWCNT_CURR_VALUE_W 16
+#define I2S_STMPWCNT_CURR_VALUE_M 0x0000FFFF
+#define I2S_STMPWCNT_CURR_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: I2S_O_STMPXCNT
+//
+//*****************************************************************************
+// Field: [15:0] CURR_VALUE
+//
+// Current value of the XOSC counter, latched when reading STMPWCNT.
+#define I2S_STMPXCNT_CURR_VALUE_W 16
+#define I2S_STMPXCNT_CURR_VALUE_M 0x0000FFFF
+#define I2S_STMPXCNT_CURR_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: I2S_O_STMPXCNTCAPT1
+//
+//*****************************************************************************
+// Field: [15:0] CAPT_VALUE
+//
+// Internal. Only to be used through TI provided API.
+#define I2S_STMPXCNTCAPT1_CAPT_VALUE_W 16
+#define I2S_STMPXCNTCAPT1_CAPT_VALUE_M 0x0000FFFF
+#define I2S_STMPXCNTCAPT1_CAPT_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: I2S_O_STMPWCNTCAPT1
+//
+//*****************************************************************************
+// Field: [15:0] CAPT_VALUE
+//
+// Internal. Only to be used through TI provided API.
+#define I2S_STMPWCNTCAPT1_CAPT_VALUE_W 16
+#define I2S_STMPWCNTCAPT1_CAPT_VALUE_M 0x0000FFFF
+#define I2S_STMPWCNTCAPT1_CAPT_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: I2S_O_IRQMASK
+//
+//*****************************************************************************
+// Field: [5] AIF_DMA_IN
+//
+// IRQFLAGS.AIF_DMA_IN interrupt mask
+//
+// 0: Disable
+// 1: Enable
+#define I2S_IRQMASK_AIF_DMA_IN 0x00000020
+#define I2S_IRQMASK_AIF_DMA_IN_BITN 5
+#define I2S_IRQMASK_AIF_DMA_IN_M 0x00000020
+#define I2S_IRQMASK_AIF_DMA_IN_S 5
+
+// Field: [4] AIF_DMA_OUT
+//
+// IRQFLAGS.AIF_DMA_OUT interrupt mask
+//
+// 0: Disable
+// 1: Enable
+#define I2S_IRQMASK_AIF_DMA_OUT 0x00000010
+#define I2S_IRQMASK_AIF_DMA_OUT_BITN 4
+#define I2S_IRQMASK_AIF_DMA_OUT_M 0x00000010
+#define I2S_IRQMASK_AIF_DMA_OUT_S 4
+
+// Field: [3] WCLK_TIMEOUT
+//
+// IRQFLAGS.WCLK_TIMEOUT interrupt mask
+//
+// 0: Disable
+// 1: Enable
+#define I2S_IRQMASK_WCLK_TIMEOUT 0x00000008
+#define I2S_IRQMASK_WCLK_TIMEOUT_BITN 3
+#define I2S_IRQMASK_WCLK_TIMEOUT_M 0x00000008
+#define I2S_IRQMASK_WCLK_TIMEOUT_S 3
+
+// Field: [2] BUS_ERR
+//
+// IRQFLAGS.BUS_ERR interrupt mask
+//
+// 0: Disable
+// 1: Enable
+#define I2S_IRQMASK_BUS_ERR 0x00000004
+#define I2S_IRQMASK_BUS_ERR_BITN 2
+#define I2S_IRQMASK_BUS_ERR_M 0x00000004
+#define I2S_IRQMASK_BUS_ERR_S 2
+
+// Field: [1] WCLK_ERR
+//
+// IRQFLAGS.WCLK_ERR interrupt mask
+//
+// 0: Disable
+// 1: Enable
+#define I2S_IRQMASK_WCLK_ERR 0x00000002
+#define I2S_IRQMASK_WCLK_ERR_BITN 1
+#define I2S_IRQMASK_WCLK_ERR_M 0x00000002
+#define I2S_IRQMASK_WCLK_ERR_S 1
+
+// Field: [0] PTR_ERR
+//
+// IRQFLAGS.PTR_ERR interrupt mask.
+//
+// 0: Disable
+// 1: Enable
+#define I2S_IRQMASK_PTR_ERR 0x00000001
+#define I2S_IRQMASK_PTR_ERR_BITN 0
+#define I2S_IRQMASK_PTR_ERR_M 0x00000001
+#define I2S_IRQMASK_PTR_ERR_S 0
+
+//*****************************************************************************
+//
+// Register: I2S_O_IRQFLAGS
+//
+//*****************************************************************************
+// Field: [5] AIF_DMA_IN
+//
+// Set when condition for this bit field event occurs (auto cleared when input
+// pointer is updated - AIFINPTRNEXT), see description of AIFINPTRNEXT register
+// for details.
+#define I2S_IRQFLAGS_AIF_DMA_IN 0x00000020
+#define I2S_IRQFLAGS_AIF_DMA_IN_BITN 5
+#define I2S_IRQFLAGS_AIF_DMA_IN_M 0x00000020
+#define I2S_IRQFLAGS_AIF_DMA_IN_S 5
+
+// Field: [4] AIF_DMA_OUT
+//
+// Set when condition for this bit field event occurs (auto cleared when output
+// pointer is updated - AIFOUTPTRNEXT), see description of AIFOUTPTRNEXT
+// register for details
+#define I2S_IRQFLAGS_AIF_DMA_OUT 0x00000010
+#define I2S_IRQFLAGS_AIF_DMA_OUT_BITN 4
+#define I2S_IRQFLAGS_AIF_DMA_OUT_M 0x00000010
+#define I2S_IRQFLAGS_AIF_DMA_OUT_S 4
+
+// Field: [3] WCLK_TIMEOUT
+//
+// Set when the sample stamp generator does not detect a positive WCLK edge for
+// 65535 clk periods. This signalizes that the internal or external BCLK and
+// WCLK generator source has been disabled.
+//
+// The bit is sticky and may only be cleared by software (by writing '1' to
+// IRQCLR.WCLK_TIMEOUT).
+#define I2S_IRQFLAGS_WCLK_TIMEOUT 0x00000008
+#define I2S_IRQFLAGS_WCLK_TIMEOUT_BITN 3
+#define I2S_IRQFLAGS_WCLK_TIMEOUT_M 0x00000008
+#define I2S_IRQFLAGS_WCLK_TIMEOUT_S 3
+
+// Field: [2] BUS_ERR
+//
+// Set when a DMA operation is not completed in time (that is audio output
+// buffer underflow, or audio input buffer overflow).
+// This error requires a complete restart since word synchronization has been
+// lost. The bit is sticky and may only be cleared by software (by writing '1'
+// to IRQCLR.BUS_ERR).
+//
+// Note that DMA initiated transactions to illegal addresses will not trigger
+// an interrupt. The response to such transactions is undefined.
+#define I2S_IRQFLAGS_BUS_ERR 0x00000004
+#define I2S_IRQFLAGS_BUS_ERR_BITN 2
+#define I2S_IRQFLAGS_BUS_ERR_M 0x00000004
+#define I2S_IRQFLAGS_BUS_ERR_S 2
+
+// Field: [1] WCLK_ERR
+//
+// Set when:
+// - An unexpected WCLK edge occurs during the data delay period of a phase.
+// Note unexpected WCLK edges during the word and idle periods of the phase are
+// not detected.
+// - In dual-phase mode, when two WCLK edges are less than 4 BCLK cycles
+// apart.
+// - In single-phase mode, when a WCLK pulse occurs before the last channel.
+// This error requires a complete restart since word synchronization has been
+// lost. The bit is sticky and may only be cleared by software (by writing '1'
+// to IRQCLR.WCLK_ERR).
+#define I2S_IRQFLAGS_WCLK_ERR 0x00000002
+#define I2S_IRQFLAGS_WCLK_ERR_BITN 1
+#define I2S_IRQFLAGS_WCLK_ERR_M 0x00000002
+#define I2S_IRQFLAGS_WCLK_ERR_S 1
+
+// Field: [0] PTR_ERR
+//
+// Set when AIFINPTRNEXT or AIFOUTPTRNEXT has not been loaded with the next
+// block address in time.
+// This error requires a complete restart since word synchronization has been
+// lost. The bit is sticky and may only be cleared by software (by writing '1'
+// to IRQCLR.PTR_ERR).
+#define I2S_IRQFLAGS_PTR_ERR 0x00000001
+#define I2S_IRQFLAGS_PTR_ERR_BITN 0
+#define I2S_IRQFLAGS_PTR_ERR_M 0x00000001
+#define I2S_IRQFLAGS_PTR_ERR_S 0
+
+//*****************************************************************************
+//
+// Register: I2S_O_IRQSET
+//
+//*****************************************************************************
+// Field: [5] AIF_DMA_IN
+//
+// 1: Sets the interrupt of IRQFLAGS.AIF_DMA_IN (unless a auto clear criteria
+// was given at the same time, in which the set will be ignored)
+#define I2S_IRQSET_AIF_DMA_IN 0x00000020
+#define I2S_IRQSET_AIF_DMA_IN_BITN 5
+#define I2S_IRQSET_AIF_DMA_IN_M 0x00000020
+#define I2S_IRQSET_AIF_DMA_IN_S 5
+
+// Field: [4] AIF_DMA_OUT
+//
+// 1: Sets the interrupt of IRQFLAGS.AIF_DMA_OUT (unless a auto clear criteria
+// was given at the same time, in which the set will be ignored)
+#define I2S_IRQSET_AIF_DMA_OUT 0x00000010
+#define I2S_IRQSET_AIF_DMA_OUT_BITN 4
+#define I2S_IRQSET_AIF_DMA_OUT_M 0x00000010
+#define I2S_IRQSET_AIF_DMA_OUT_S 4
+
+// Field: [3] WCLK_TIMEOUT
+//
+// 1: Sets the interrupt of IRQFLAGS.WCLK_TIMEOUT
+#define I2S_IRQSET_WCLK_TIMEOUT 0x00000008
+#define I2S_IRQSET_WCLK_TIMEOUT_BITN 3
+#define I2S_IRQSET_WCLK_TIMEOUT_M 0x00000008
+#define I2S_IRQSET_WCLK_TIMEOUT_S 3
+
+// Field: [2] BUS_ERR
+//
+// 1: Sets the interrupt of IRQFLAGS.BUS_ERR
+#define I2S_IRQSET_BUS_ERR 0x00000004
+#define I2S_IRQSET_BUS_ERR_BITN 2
+#define I2S_IRQSET_BUS_ERR_M 0x00000004
+#define I2S_IRQSET_BUS_ERR_S 2
+
+// Field: [1] WCLK_ERR
+//
+// 1: Sets the interrupt of IRQFLAGS.WCLK_ERR
+#define I2S_IRQSET_WCLK_ERR 0x00000002
+#define I2S_IRQSET_WCLK_ERR_BITN 1
+#define I2S_IRQSET_WCLK_ERR_M 0x00000002
+#define I2S_IRQSET_WCLK_ERR_S 1
+
+// Field: [0] PTR_ERR
+//
+// 1: Sets the interrupt of IRQFLAGS.PTR_ERR
+#define I2S_IRQSET_PTR_ERR 0x00000001
+#define I2S_IRQSET_PTR_ERR_BITN 0
+#define I2S_IRQSET_PTR_ERR_M 0x00000001
+#define I2S_IRQSET_PTR_ERR_S 0
+
+//*****************************************************************************
+//
+// Register: I2S_O_IRQCLR
+//
+//*****************************************************************************
+// Field: [5] AIF_DMA_IN
+//
+// 1: Clears the interrupt of IRQFLAGS.AIF_DMA_IN (unless a set criteria was
+// given at the same time in which the clear will be ignored)
+#define I2S_IRQCLR_AIF_DMA_IN 0x00000020
+#define I2S_IRQCLR_AIF_DMA_IN_BITN 5
+#define I2S_IRQCLR_AIF_DMA_IN_M 0x00000020
+#define I2S_IRQCLR_AIF_DMA_IN_S 5
+
+// Field: [4] AIF_DMA_OUT
+//
+// 1: Clears the interrupt of IRQFLAGS.AIF_DMA_OUT (unless a set criteria was
+// given at the same time in which the clear will be ignored)
+#define I2S_IRQCLR_AIF_DMA_OUT 0x00000010
+#define I2S_IRQCLR_AIF_DMA_OUT_BITN 4
+#define I2S_IRQCLR_AIF_DMA_OUT_M 0x00000010
+#define I2S_IRQCLR_AIF_DMA_OUT_S 4
+
+// Field: [3] WCLK_TIMEOUT
+//
+// 1: Clears the interrupt of IRQFLAGS.WCLK_TIMEOUT (unless a set criteria was
+// given at the same time in which the clear will be ignored)
+#define I2S_IRQCLR_WCLK_TIMEOUT 0x00000008
+#define I2S_IRQCLR_WCLK_TIMEOUT_BITN 3
+#define I2S_IRQCLR_WCLK_TIMEOUT_M 0x00000008
+#define I2S_IRQCLR_WCLK_TIMEOUT_S 3
+
+// Field: [2] BUS_ERR
+//
+// 1: Clears the interrupt of IRQFLAGS.BUS_ERR (unless a set criteria was given
+// at the same time in which the clear will be ignored)
+#define I2S_IRQCLR_BUS_ERR 0x00000004
+#define I2S_IRQCLR_BUS_ERR_BITN 2
+#define I2S_IRQCLR_BUS_ERR_M 0x00000004
+#define I2S_IRQCLR_BUS_ERR_S 2
+
+// Field: [1] WCLK_ERR
+//
+// 1: Clears the interrupt of IRQFLAGS.WCLK_ERR (unless a set criteria was
+// given at the same time in which the clear will be ignored)
+#define I2S_IRQCLR_WCLK_ERR 0x00000002
+#define I2S_IRQCLR_WCLK_ERR_BITN 1
+#define I2S_IRQCLR_WCLK_ERR_M 0x00000002
+#define I2S_IRQCLR_WCLK_ERR_S 1
+
+// Field: [0] PTR_ERR
+//
+// 1: Clears the interrupt of IRQFLAGS.PTR_ERR (unless a set criteria was given
+// at the same time in which the clear will be ignored)
+#define I2S_IRQCLR_PTR_ERR 0x00000001
+#define I2S_IRQCLR_PTR_ERR_BITN 0
+#define I2S_IRQCLR_PTR_ERR_M 0x00000001
+#define I2S_IRQCLR_PTR_ERR_S 0
+
+
+#endif // __I2S__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ints.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ints.h
new file mode 100644
index 0000000..940695e
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ints.h
@@ -0,0 +1,120 @@
+/******************************************************************************
+* Filename: hw_ints_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_INTS_H__
+#define __HW_INTS_H__
+
+//*****************************************************************************
+//
+// The following are defines for the interrupt assignments.
+//
+//*****************************************************************************
+#define INT_NMI_FAULT 2 // NMI Fault
+#define INT_HARD_FAULT 3 // Hard Fault
+#define INT_MEMMANAGE_FAULT 4 // Memory Management (MemManage)
+ // Fault
+#define INT_BUS_FAULT 5 // Bus Fault
+#define INT_USAGE_FAULT 6 // Usage Fault
+#define INT_SVCALL 11 // Supervisor Call (SVCall)
+#define INT_DEBUG 12 // Debug Monitor
+#define INT_PENDSV 14 // Pending Service Call (PendSV)
+#define INT_SYSTICK 15 // SysTick Interrupt from the
+ // System Timer in NVIC.
+#define INT_AON_GPIO_EDGE 16 // Edge detect event from IOC
+#define INT_I2C_IRQ 17 // Interrupt event from I2C
+#define INT_RFC_CPE_1 18 // Combined Interrupt for CPE
+ // Generated events
+#define INT_PKA_IRQ 19 // PKA Interrupt event
+#define INT_AON_RTC_COMB 20 // Event from AON_RTC
+#define INT_UART0_COMB 21 // UART0 combined interrupt
+#define INT_AUX_SWEV0 22 // AUX software event 0
+#define INT_SSI0_COMB 23 // SSI0 combined interrupt
+#define INT_SSI1_COMB 24 // SSI1 combined interrupt
+#define INT_RFC_CPE_0 25 // Combined Interrupt for CPE
+ // Generated events
+#define INT_RFC_HW_COMB 26 // Combined RFC hardware interrupt
+#define INT_RFC_CMD_ACK 27 // RFC Doorbell Command
+ // Acknowledgement Interrupt
+#define INT_I2S_IRQ 28 // Interrupt event from I2S
+#define INT_AUX_SWEV1 29 // AUX software event 1
+#define INT_WDT_IRQ 30 // Watchdog interrupt event
+#define INT_GPT0A 31 // GPT0A interrupt event
+#define INT_GPT0B 32 // GPT0B interrupt event
+#define INT_GPT1A 33 // GPT1A interrupt event
+#define INT_GPT1B 34 // GPT1B interrupt event
+#define INT_GPT2A 35 // GPT2A interrupt event
+#define INT_GPT2B 36 // GPT2B interrupt event
+#define INT_GPT3A 37 // GPT3A interrupt event
+#define INT_GPT3B 38 // GPT3B interrupt event
+#define INT_CRYPTO_RESULT_AVAIL_IRQ 39 // CRYPTO result available interupt
+ // event
+#define INT_DMA_DONE_COMB 40 // Combined DMA done
+#define INT_DMA_ERR 41 // DMA bus error
+#define INT_FLASH 42 // FLASH controller error event
+#define INT_SWEV0 43 // Software event 0
+#define INT_AUX_COMB 44 // AUX combined event
+#define INT_AON_PROG0 45 // AON programmable event 0
+#define INT_PROG0 46 // Programmable Interrupt 0
+#define INT_AUX_COMPA 47 // AUX Compare A event
+#define INT_AUX_ADC_IRQ 48 // AUX ADC interrupt event
+#define INT_TRNG_IRQ 49 // TRNG Interrupt event
+#define INT_OSC_COMB 50 // Combined event from Oscillator
+ // control
+#define INT_AUX_TIMER2_EV0 51 // AUX Timer2 event 0
+#define INT_UART1_COMB 52 // UART1 combined interrupt
+#define INT_BATMON_COMB 53 // Combined event from battery
+ // monitor
+
+//*****************************************************************************
+//
+// The following are defines for number of interrupts and priority levels.
+//
+//*****************************************************************************
+#define NUM_INTERRUPTS 54 // Number of interrupts
+#define NUM_PRIORITY_BITS 3 // Number of Priority bits
+#define NUM_PRIORITY 8 // Number of priority levels
+
+
+//*****************************************************************************
+//
+// Aliases for backwards compatibility with Sensor Controller Studio 1.1.0
+//
+//*****************************************************************************
+
+#define INT_AON_AUX_SWEV0 INT_AUX_SWEV0
+#define INT_AON_AUX_SWEV1 INT_AUX_SWEV1
+
+#endif
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ioc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ioc.h
new file mode 100644
index 0000000..9e7c982
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ioc.h
@@ -0,0 +1,11887 @@
+/******************************************************************************
+* Filename: hw_ioc_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_IOC_H__
+#define __HW_IOC_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// IOC component
+//
+//*****************************************************************************
+// Configuration of DIO0
+#define IOC_O_IOCFG0 0x00000000
+
+// Configuration of DIO1
+#define IOC_O_IOCFG1 0x00000004
+
+// Configuration of DIO2
+#define IOC_O_IOCFG2 0x00000008
+
+// Configuration of DIO3
+#define IOC_O_IOCFG3 0x0000000C
+
+// Configuration of DIO4
+#define IOC_O_IOCFG4 0x00000010
+
+// Configuration of DIO5
+#define IOC_O_IOCFG5 0x00000014
+
+// Configuration of DIO6
+#define IOC_O_IOCFG6 0x00000018
+
+// Configuration of DIO7
+#define IOC_O_IOCFG7 0x0000001C
+
+// Configuration of DIO8
+#define IOC_O_IOCFG8 0x00000020
+
+// Configuration of DIO9
+#define IOC_O_IOCFG9 0x00000024
+
+// Configuration of DIO10
+#define IOC_O_IOCFG10 0x00000028
+
+// Configuration of DIO11
+#define IOC_O_IOCFG11 0x0000002C
+
+// Configuration of DIO12
+#define IOC_O_IOCFG12 0x00000030
+
+// Configuration of DIO13
+#define IOC_O_IOCFG13 0x00000034
+
+// Configuration of DIO14
+#define IOC_O_IOCFG14 0x00000038
+
+// Configuration of DIO15
+#define IOC_O_IOCFG15 0x0000003C
+
+// Configuration of DIO16
+#define IOC_O_IOCFG16 0x00000040
+
+// Configuration of DIO17
+#define IOC_O_IOCFG17 0x00000044
+
+// Configuration of DIO18
+#define IOC_O_IOCFG18 0x00000048
+
+// Configuration of DIO19
+#define IOC_O_IOCFG19 0x0000004C
+
+// Configuration of DIO20
+#define IOC_O_IOCFG20 0x00000050
+
+// Configuration of DIO21
+#define IOC_O_IOCFG21 0x00000054
+
+// Configuration of DIO22
+#define IOC_O_IOCFG22 0x00000058
+
+// Configuration of DIO23
+#define IOC_O_IOCFG23 0x0000005C
+
+// Configuration of DIO24
+#define IOC_O_IOCFG24 0x00000060
+
+// Configuration of DIO25
+#define IOC_O_IOCFG25 0x00000064
+
+// Configuration of DIO26
+#define IOC_O_IOCFG26 0x00000068
+
+// Configuration of DIO27
+#define IOC_O_IOCFG27 0x0000006C
+
+// Configuration of DIO28
+#define IOC_O_IOCFG28 0x00000070
+
+// Configuration of DIO29
+#define IOC_O_IOCFG29 0x00000074
+
+// Configuration of DIO30
+#define IOC_O_IOCFG30 0x00000078
+
+// Configuration of DIO31
+#define IOC_O_IOCFG31 0x0000007C
+
+//*****************************************************************************
+//
+// Register: IOC_O_IOCFG0
+//
+//*****************************************************************************
+// Field: [30] HYST_EN
+//
+// 0: Input hysteresis disable
+// 1: Input hysteresis enable
+#define IOC_IOCFG0_HYST_EN 0x40000000
+#define IOC_IOCFG0_HYST_EN_BITN 30
+#define IOC_IOCFG0_HYST_EN_M 0x40000000
+#define IOC_IOCFG0_HYST_EN_S 30
+
+// Field: [29] IE
+//
+// 0: Input disabled
+// 1: Input enabled
+//
+// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be
+// ignored.
+#define IOC_IOCFG0_IE 0x20000000
+#define IOC_IOCFG0_IE_BITN 29
+#define IOC_IOCFG0_IE_M 0x20000000
+#define IOC_IOCFG0_IE_S 29
+
+// Field: [28:27] WU_CFG
+//
+// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or
+// >0x08:
+//
+// 00: No wake-up
+// 01: No wake-up
+// 10: Wakes up from shutdown if this pad is going low.
+// 11: Wakes up from shutdown if this pad is going high.
+//
+// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08,
+// this register only sets wakeup enable or not.
+//
+// 00, 01: Wakeup disabled
+// 10, 11: Wakeup enabled
+//
+// Polarity is controlled from AON registers.
+//
+// Note:When the MSB is set, the IOC will deactivate the output enable for the
+// DIO.
+#define IOC_IOCFG0_WU_CFG_W 2
+#define IOC_IOCFG0_WU_CFG_M 0x18000000
+#define IOC_IOCFG0_WU_CFG_S 27
+
+// Field: [26:24] IOMODE
+//
+// IO Mode
+// Not applicable for IO configured for AON periph. signals and AUX PORT_ID
+// 0x01-0x08
+// AUX has its own open_source/drain configuration.
+//
+// 0x2: Reserved. Undefined behavior.
+// 0x3: Reserved. Undefined behavior.
+// ENUMs:
+// OPENSRC_INV Open Source
+// Inverted input/output
+// OPENSRC Open Source
+// Normal input / outut
+// OPENDR_INV Open Drain
+// Inverted input / output
+// OPENDR Open Drain,
+// Normal input / output
+// INV Inverted input / ouput
+// NORMAL Normal input / output
+#define IOC_IOCFG0_IOMODE_W 3
+#define IOC_IOCFG0_IOMODE_M 0x07000000
+#define IOC_IOCFG0_IOMODE_S 24
+#define IOC_IOCFG0_IOMODE_OPENSRC_INV 0x07000000
+#define IOC_IOCFG0_IOMODE_OPENSRC 0x06000000
+#define IOC_IOCFG0_IOMODE_OPENDR_INV 0x05000000
+#define IOC_IOCFG0_IOMODE_OPENDR 0x04000000
+#define IOC_IOCFG0_IOMODE_INV 0x01000000
+#define IOC_IOCFG0_IOMODE_NORMAL 0x00000000
+
+// Field: [23] IOEV_AON_PROG2_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG2 event
+// 1: Input edge detection asserts AON_PROG2 event
+#define IOC_IOCFG0_IOEV_AON_PROG2_EN 0x00800000
+#define IOC_IOCFG0_IOEV_AON_PROG2_EN_BITN 23
+#define IOC_IOCFG0_IOEV_AON_PROG2_EN_M 0x00800000
+#define IOC_IOCFG0_IOEV_AON_PROG2_EN_S 23
+
+// Field: [22] IOEV_AON_PROG1_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG1 event
+// 1: Input edge detection asserts AON_PROG1 event
+#define IOC_IOCFG0_IOEV_AON_PROG1_EN 0x00400000
+#define IOC_IOCFG0_IOEV_AON_PROG1_EN_BITN 22
+#define IOC_IOCFG0_IOEV_AON_PROG1_EN_M 0x00400000
+#define IOC_IOCFG0_IOEV_AON_PROG1_EN_S 22
+
+// Field: [21] IOEV_AON_PROG0_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG0 event
+// 1: Input edge detection asserts AON_PROG0 event
+#define IOC_IOCFG0_IOEV_AON_PROG0_EN 0x00200000
+#define IOC_IOCFG0_IOEV_AON_PROG0_EN_BITN 21
+#define IOC_IOCFG0_IOEV_AON_PROG0_EN_M 0x00200000
+#define IOC_IOCFG0_IOEV_AON_PROG0_EN_S 21
+
+// Field: [18] EDGE_IRQ_EN
+//
+// 0: No interrupt generation
+// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is
+// enabled)
+#define IOC_IOCFG0_EDGE_IRQ_EN 0x00040000
+#define IOC_IOCFG0_EDGE_IRQ_EN_BITN 18
+#define IOC_IOCFG0_EDGE_IRQ_EN_M 0x00040000
+#define IOC_IOCFG0_EDGE_IRQ_EN_S 18
+
+// Field: [17:16] EDGE_DET
+//
+// Enable generation of edge detection events on this IO
+// ENUMs:
+// BOTH Positive and negative edge detection
+// POS Positive edge detection
+// NEG Negative edge detection
+// NONE No edge detection
+#define IOC_IOCFG0_EDGE_DET_W 2
+#define IOC_IOCFG0_EDGE_DET_M 0x00030000
+#define IOC_IOCFG0_EDGE_DET_S 16
+#define IOC_IOCFG0_EDGE_DET_BOTH 0x00030000
+#define IOC_IOCFG0_EDGE_DET_POS 0x00020000
+#define IOC_IOCFG0_EDGE_DET_NEG 0x00010000
+#define IOC_IOCFG0_EDGE_DET_NONE 0x00000000
+
+// Field: [14:13] PULL_CTL
+//
+// Pull control
+// ENUMs:
+// DIS No pull
+// UP Pull up
+// DWN Pull down
+#define IOC_IOCFG0_PULL_CTL_W 2
+#define IOC_IOCFG0_PULL_CTL_M 0x00006000
+#define IOC_IOCFG0_PULL_CTL_S 13
+#define IOC_IOCFG0_PULL_CTL_DIS 0x00006000
+#define IOC_IOCFG0_PULL_CTL_UP 0x00004000
+#define IOC_IOCFG0_PULL_CTL_DWN 0x00002000
+
+// Field: [12] SLEW_RED
+//
+// 0: Normal slew rate
+// 1: Enables reduced slew rate in output driver.
+#define IOC_IOCFG0_SLEW_RED 0x00001000
+#define IOC_IOCFG0_SLEW_RED_BITN 12
+#define IOC_IOCFG0_SLEW_RED_M 0x00001000
+#define IOC_IOCFG0_SLEW_RED_S 12
+
+// Field: [11:10] IOCURR
+//
+// Selects IO current mode of this IO.
+// ENUMs:
+// 4_8MA Extended-Current (EC) mode: Min 8 mA for double
+// drive strength IOs (min 4 mA for normal IOs)
+// when IOSTR is set to AUTO
+// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set
+// to AUTO
+// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set
+// to AUTO
+#define IOC_IOCFG0_IOCURR_W 2
+#define IOC_IOCFG0_IOCURR_M 0x00000C00
+#define IOC_IOCFG0_IOCURR_S 10
+#define IOC_IOCFG0_IOCURR_4_8MA 0x00000800
+#define IOC_IOCFG0_IOCURR_4MA 0x00000400
+#define IOC_IOCFG0_IOCURR_2MA 0x00000000
+
+// Field: [9:8] IOSTR
+//
+// Select source for drive strength control of this IO.
+// This setting controls the drive strength of the Low-Current (LC) mode.
+// Higher drive strength can be selected in IOCURR
+// ENUMs:
+// MAX Maximum drive strength, controlled by
+// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default
+// values)
+// MED Medium drive strength, controlled by
+// AON_IOC:IOSTRMED (min 2 mA @2.5V with default
+// values)
+// MIN Minimum drive strength, controlled by
+// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default
+// values)
+// AUTO Automatic drive strength, controlled by AON BATMON
+// based on battery voltage. (min 2 mA @VDDS)
+#define IOC_IOCFG0_IOSTR_W 2
+#define IOC_IOCFG0_IOSTR_M 0x00000300
+#define IOC_IOCFG0_IOSTR_S 8
+#define IOC_IOCFG0_IOSTR_MAX 0x00000300
+#define IOC_IOCFG0_IOSTR_MED 0x00000200
+#define IOC_IOCFG0_IOSTR_MIN 0x00000100
+#define IOC_IOCFG0_IOSTR_AUTO 0x00000000
+
+// Field: [7] IOEV_RTC_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert RTC event
+// 1: Input edge detection asserts RTC event
+#define IOC_IOCFG0_IOEV_RTC_EN 0x00000080
+#define IOC_IOCFG0_IOEV_RTC_EN_BITN 7
+#define IOC_IOCFG0_IOEV_RTC_EN_M 0x00000080
+#define IOC_IOCFG0_IOEV_RTC_EN_S 7
+
+// Field: [6] IOEV_MCU_WU_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert MCU_WU event
+// 1: Input edge detection asserts MCU_WU event
+#define IOC_IOCFG0_IOEV_MCU_WU_EN 0x00000040
+#define IOC_IOCFG0_IOEV_MCU_WU_EN_BITN 6
+#define IOC_IOCFG0_IOEV_MCU_WU_EN_M 0x00000040
+#define IOC_IOCFG0_IOEV_MCU_WU_EN_S 6
+
+// Field: [5:0] PORT_ID
+//
+// Selects usage for DIO0
+// ENUMs:
+// RFC_SMI_CL_IN RF Core SMI Command Link In
+// RFC_SMI_CL_OUT RF Core SMI Command Link Out
+// RFC_SMI_DL_IN RF Core SMI Data Link In
+// RFC_SMI_DL_OUT RF Core SMI Data Link Out
+// RFC_GPI1 RF Core Data In 1
+// RFC_GPI0 RF Core Data In 0
+// RFC_GPO3 RF Core Data Out 3
+// RFC_GPO2 RF Core Data Out 2
+// RFC_GPO1 RF Core Data Out 1
+// RFC_GPO0 RF Core Data Out 0
+// RFC_TRC RF Core Trace
+// I2S_MCLK I2S MCLK
+// I2S_BCLK I2S BCLK
+// I2S_WCLK I2S WCLK
+// I2S_AD1 I2S Data 1
+// I2S_AD0 I2S Data 0
+// SSI1_CLK SSI1 CLK
+// SSI1_FSS SSI1 FSS
+// SSI1_TX SSI1 TX
+// SSI1_RX SSI1 RX
+// CPU_SWV CPU SWV
+// PORT_EVENT7 PORT EVENT 7
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT6 PORT EVENT 6
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT5 PORT EVENT 5
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT4 PORT EVENT 4
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT3 PORT EVENT 3
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT2 PORT EVENT 2
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT1 PORT EVENT 1
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT0 PORT EVENT 0
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// UART1_RTS UART1 RTS
+// UART1_CTS UART1 CTS
+// UART1_TX UART1 TX
+// UART1_RX UART1 RX
+// UART0_RTS UART0 RTS
+// UART0_CTS UART0 CTS
+// UART0_TX UART0 TX
+// UART0_RX UART0 RX
+// I2C_MSSCL I2C Clock
+// I2C_MSSDA I2C Data
+// SSI0_CLK SSI0 CLK
+// SSI0_FSS SSI0 FSS
+// SSI0_TX SSI0 TX
+// SSI0_RX SSI0 RX
+// AUX_IO AUX IO
+// AON_CLK32K AON 32 KHz clock (SCLK_LF)
+// GPIO General Purpose IO
+#define IOC_IOCFG0_PORT_ID_W 6
+#define IOC_IOCFG0_PORT_ID_M 0x0000003F
+#define IOC_IOCFG0_PORT_ID_S 0
+#define IOC_IOCFG0_PORT_ID_RFC_SMI_CL_IN 0x00000038
+#define IOC_IOCFG0_PORT_ID_RFC_SMI_CL_OUT 0x00000037
+#define IOC_IOCFG0_PORT_ID_RFC_SMI_DL_IN 0x00000036
+#define IOC_IOCFG0_PORT_ID_RFC_SMI_DL_OUT 0x00000035
+#define IOC_IOCFG0_PORT_ID_RFC_GPI1 0x00000034
+#define IOC_IOCFG0_PORT_ID_RFC_GPI0 0x00000033
+#define IOC_IOCFG0_PORT_ID_RFC_GPO3 0x00000032
+#define IOC_IOCFG0_PORT_ID_RFC_GPO2 0x00000031
+#define IOC_IOCFG0_PORT_ID_RFC_GPO1 0x00000030
+#define IOC_IOCFG0_PORT_ID_RFC_GPO0 0x0000002F
+#define IOC_IOCFG0_PORT_ID_RFC_TRC 0x0000002E
+#define IOC_IOCFG0_PORT_ID_I2S_MCLK 0x00000029
+#define IOC_IOCFG0_PORT_ID_I2S_BCLK 0x00000028
+#define IOC_IOCFG0_PORT_ID_I2S_WCLK 0x00000027
+#define IOC_IOCFG0_PORT_ID_I2S_AD1 0x00000026
+#define IOC_IOCFG0_PORT_ID_I2S_AD0 0x00000025
+#define IOC_IOCFG0_PORT_ID_SSI1_CLK 0x00000024
+#define IOC_IOCFG0_PORT_ID_SSI1_FSS 0x00000023
+#define IOC_IOCFG0_PORT_ID_SSI1_TX 0x00000022
+#define IOC_IOCFG0_PORT_ID_SSI1_RX 0x00000021
+#define IOC_IOCFG0_PORT_ID_CPU_SWV 0x00000020
+#define IOC_IOCFG0_PORT_ID_PORT_EVENT7 0x0000001E
+#define IOC_IOCFG0_PORT_ID_PORT_EVENT6 0x0000001D
+#define IOC_IOCFG0_PORT_ID_PORT_EVENT5 0x0000001C
+#define IOC_IOCFG0_PORT_ID_PORT_EVENT4 0x0000001B
+#define IOC_IOCFG0_PORT_ID_PORT_EVENT3 0x0000001A
+#define IOC_IOCFG0_PORT_ID_PORT_EVENT2 0x00000019
+#define IOC_IOCFG0_PORT_ID_PORT_EVENT1 0x00000018
+#define IOC_IOCFG0_PORT_ID_PORT_EVENT0 0x00000017
+#define IOC_IOCFG0_PORT_ID_UART1_RTS 0x00000016
+#define IOC_IOCFG0_PORT_ID_UART1_CTS 0x00000015
+#define IOC_IOCFG0_PORT_ID_UART1_TX 0x00000014
+#define IOC_IOCFG0_PORT_ID_UART1_RX 0x00000013
+#define IOC_IOCFG0_PORT_ID_UART0_RTS 0x00000012
+#define IOC_IOCFG0_PORT_ID_UART0_CTS 0x00000011
+#define IOC_IOCFG0_PORT_ID_UART0_TX 0x00000010
+#define IOC_IOCFG0_PORT_ID_UART0_RX 0x0000000F
+#define IOC_IOCFG0_PORT_ID_I2C_MSSCL 0x0000000E
+#define IOC_IOCFG0_PORT_ID_I2C_MSSDA 0x0000000D
+#define IOC_IOCFG0_PORT_ID_SSI0_CLK 0x0000000C
+#define IOC_IOCFG0_PORT_ID_SSI0_FSS 0x0000000B
+#define IOC_IOCFG0_PORT_ID_SSI0_TX 0x0000000A
+#define IOC_IOCFG0_PORT_ID_SSI0_RX 0x00000009
+#define IOC_IOCFG0_PORT_ID_AUX_IO 0x00000008
+#define IOC_IOCFG0_PORT_ID_AON_CLK32K 0x00000007
+#define IOC_IOCFG0_PORT_ID_GPIO 0x00000000
+
+//*****************************************************************************
+//
+// Register: IOC_O_IOCFG1
+//
+//*****************************************************************************
+// Field: [30] HYST_EN
+//
+// 0: Input hysteresis disable
+// 1: Input hysteresis enable
+#define IOC_IOCFG1_HYST_EN 0x40000000
+#define IOC_IOCFG1_HYST_EN_BITN 30
+#define IOC_IOCFG1_HYST_EN_M 0x40000000
+#define IOC_IOCFG1_HYST_EN_S 30
+
+// Field: [29] IE
+//
+// 0: Input disabled
+// 1: Input enabled
+//
+// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be
+// ignored.
+#define IOC_IOCFG1_IE 0x20000000
+#define IOC_IOCFG1_IE_BITN 29
+#define IOC_IOCFG1_IE_M 0x20000000
+#define IOC_IOCFG1_IE_S 29
+
+// Field: [28:27] WU_CFG
+//
+// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or
+// >0x08:
+//
+// 00: No wake-up
+// 01: No wake-up
+// 10: Wakes up from shutdown if this pad is going low.
+// 11: Wakes up from shutdown if this pad is going high.
+//
+// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08,
+// this register only sets wakeup enable or not.
+//
+// 00, 01: Wakeup disabled
+// 10, 11: Wakeup enabled
+//
+// Polarity is controlled from AON registers.
+//
+// Note:When the MSB is set, the IOC will deactivate the output enable for the
+// DIO.
+#define IOC_IOCFG1_WU_CFG_W 2
+#define IOC_IOCFG1_WU_CFG_M 0x18000000
+#define IOC_IOCFG1_WU_CFG_S 27
+
+// Field: [26:24] IOMODE
+//
+// IO Mode
+// Not applicable for IO configured for AON periph. signals and AUX PORT_ID
+// 0x01-0x08
+// AUX has its own open_source/drain configuration.
+//
+// 0x2: Reserved. Undefined behavior.
+// 0x3: Reserved. Undefined behavior.
+// ENUMs:
+// OPENSRC_INV Open Source
+// Inverted input / output
+// OPENSRC Open Source
+// Normal input / output
+// OPENDR_INV Open Drain
+// Inverted input / output
+// OPENDR Open Drain,
+// Normal input / output
+// INV Inverted input / ouput
+// NORMAL Normal input / output
+#define IOC_IOCFG1_IOMODE_W 3
+#define IOC_IOCFG1_IOMODE_M 0x07000000
+#define IOC_IOCFG1_IOMODE_S 24
+#define IOC_IOCFG1_IOMODE_OPENSRC_INV 0x07000000
+#define IOC_IOCFG1_IOMODE_OPENSRC 0x06000000
+#define IOC_IOCFG1_IOMODE_OPENDR_INV 0x05000000
+#define IOC_IOCFG1_IOMODE_OPENDR 0x04000000
+#define IOC_IOCFG1_IOMODE_INV 0x01000000
+#define IOC_IOCFG1_IOMODE_NORMAL 0x00000000
+
+// Field: [23] IOEV_AON_PROG2_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG2 event
+// 1: Input edge detection asserts AON_PROG2 event
+#define IOC_IOCFG1_IOEV_AON_PROG2_EN 0x00800000
+#define IOC_IOCFG1_IOEV_AON_PROG2_EN_BITN 23
+#define IOC_IOCFG1_IOEV_AON_PROG2_EN_M 0x00800000
+#define IOC_IOCFG1_IOEV_AON_PROG2_EN_S 23
+
+// Field: [22] IOEV_AON_PROG1_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG1 event
+// 1: Input edge detection asserts AON_PROG1 event
+#define IOC_IOCFG1_IOEV_AON_PROG1_EN 0x00400000
+#define IOC_IOCFG1_IOEV_AON_PROG1_EN_BITN 22
+#define IOC_IOCFG1_IOEV_AON_PROG1_EN_M 0x00400000
+#define IOC_IOCFG1_IOEV_AON_PROG1_EN_S 22
+
+// Field: [21] IOEV_AON_PROG0_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG0 event
+// 1: Input edge detection asserts AON_PROG0 event
+#define IOC_IOCFG1_IOEV_AON_PROG0_EN 0x00200000
+#define IOC_IOCFG1_IOEV_AON_PROG0_EN_BITN 21
+#define IOC_IOCFG1_IOEV_AON_PROG0_EN_M 0x00200000
+#define IOC_IOCFG1_IOEV_AON_PROG0_EN_S 21
+
+// Field: [18] EDGE_IRQ_EN
+//
+// 0: No interrupt generation
+// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is
+// enabled)
+#define IOC_IOCFG1_EDGE_IRQ_EN 0x00040000
+#define IOC_IOCFG1_EDGE_IRQ_EN_BITN 18
+#define IOC_IOCFG1_EDGE_IRQ_EN_M 0x00040000
+#define IOC_IOCFG1_EDGE_IRQ_EN_S 18
+
+// Field: [17:16] EDGE_DET
+//
+// Enable generation of edge detection events on this IO
+// ENUMs:
+// BOTH Positive and negative edge detection
+// POS Positive edge detection
+// NEG Negative edge detection
+// NONE No edge detection
+#define IOC_IOCFG1_EDGE_DET_W 2
+#define IOC_IOCFG1_EDGE_DET_M 0x00030000
+#define IOC_IOCFG1_EDGE_DET_S 16
+#define IOC_IOCFG1_EDGE_DET_BOTH 0x00030000
+#define IOC_IOCFG1_EDGE_DET_POS 0x00020000
+#define IOC_IOCFG1_EDGE_DET_NEG 0x00010000
+#define IOC_IOCFG1_EDGE_DET_NONE 0x00000000
+
+// Field: [14:13] PULL_CTL
+//
+// Pull control
+// ENUMs:
+// DIS No pull
+// UP Pull up
+// DWN Pull down
+#define IOC_IOCFG1_PULL_CTL_W 2
+#define IOC_IOCFG1_PULL_CTL_M 0x00006000
+#define IOC_IOCFG1_PULL_CTL_S 13
+#define IOC_IOCFG1_PULL_CTL_DIS 0x00006000
+#define IOC_IOCFG1_PULL_CTL_UP 0x00004000
+#define IOC_IOCFG1_PULL_CTL_DWN 0x00002000
+
+// Field: [12] SLEW_RED
+//
+// 0: Normal slew rate
+// 1: Enables reduced slew rate in output driver.
+#define IOC_IOCFG1_SLEW_RED 0x00001000
+#define IOC_IOCFG1_SLEW_RED_BITN 12
+#define IOC_IOCFG1_SLEW_RED_M 0x00001000
+#define IOC_IOCFG1_SLEW_RED_S 12
+
+// Field: [11:10] IOCURR
+//
+// Selects IO current mode of this IO.
+// ENUMs:
+// 4_8MA Extended-Current (EC) mode: Min 8 mA for double
+// drive strength IOs (min 4 mA for normal IOs)
+// when IOSTR is set to AUTO
+// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set
+// to AUTO
+// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set
+// to AUTO
+#define IOC_IOCFG1_IOCURR_W 2
+#define IOC_IOCFG1_IOCURR_M 0x00000C00
+#define IOC_IOCFG1_IOCURR_S 10
+#define IOC_IOCFG1_IOCURR_4_8MA 0x00000800
+#define IOC_IOCFG1_IOCURR_4MA 0x00000400
+#define IOC_IOCFG1_IOCURR_2MA 0x00000000
+
+// Field: [9:8] IOSTR
+//
+// Select source for drive strength control of this IO.
+// This setting controls the drive strength of the Low-Current (LC) mode.
+// Higher drive strength can be selected in IOCURR
+// ENUMs:
+// MAX Maximum drive strength, controlled by
+// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default
+// values)
+// MED Medium drive strength, controlled by
+// AON_IOC:IOSTRMED (min 2 mA @2.5V with default
+// values)
+// MIN Minimum drive strength, controlled by
+// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default
+// values)
+// AUTO Automatic drive strength, controlled by AON BATMON
+// based on battery voltage. (min 2 mA @VDDS)
+#define IOC_IOCFG1_IOSTR_W 2
+#define IOC_IOCFG1_IOSTR_M 0x00000300
+#define IOC_IOCFG1_IOSTR_S 8
+#define IOC_IOCFG1_IOSTR_MAX 0x00000300
+#define IOC_IOCFG1_IOSTR_MED 0x00000200
+#define IOC_IOCFG1_IOSTR_MIN 0x00000100
+#define IOC_IOCFG1_IOSTR_AUTO 0x00000000
+
+// Field: [7] IOEV_RTC_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert RTC event
+// 1: Input edge detection asserts RTC event
+#define IOC_IOCFG1_IOEV_RTC_EN 0x00000080
+#define IOC_IOCFG1_IOEV_RTC_EN_BITN 7
+#define IOC_IOCFG1_IOEV_RTC_EN_M 0x00000080
+#define IOC_IOCFG1_IOEV_RTC_EN_S 7
+
+// Field: [6] IOEV_MCU_WU_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert MCU_WU event
+// 1: Input edge detection asserts MCU_WU event
+#define IOC_IOCFG1_IOEV_MCU_WU_EN 0x00000040
+#define IOC_IOCFG1_IOEV_MCU_WU_EN_BITN 6
+#define IOC_IOCFG1_IOEV_MCU_WU_EN_M 0x00000040
+#define IOC_IOCFG1_IOEV_MCU_WU_EN_S 6
+
+// Field: [5:0] PORT_ID
+//
+// Selects usage for DIO1
+// ENUMs:
+// RFC_SMI_CL_IN RF Core SMI Command Link In
+// RFC_SMI_CL_OUT RF Core SMI Command Link Out
+// RFC_SMI_DL_IN RF Core SMI Data Link In
+// RFC_SMI_DL_OUT RF Core SMI Data Link Out
+// RFC_GPI1 RF Core Data In 1
+// RFC_GPI0 RF Core Data In 0
+// RFC_GPO3 RF Core Data Out 3
+// RFC_GPO2 RF Core Data Out 2
+// RFC_GPO1 RF Core Data Out 1
+// RFC_GPO0 RF Core Data Out 0
+// RFC_TRC RF Core Trace
+// I2S_MCLK I2S MCLK
+// I2S_BCLK I2S BCLK
+// I2S_WCLK I2S WCLK
+// I2S_AD1 I2S Data 1
+// I2S_AD0 I2S Data 0
+// SSI1_CLK SSI1 CLK
+// SSI1_FSS SSI1 FSS
+// SSI1_TX SSI1 TX
+// SSI1_RX SSI1 RX
+// CPU_SWV CPU SWV
+// PORT_EVENT7 PORT EVENT 7
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT6 PORT EVENT 6
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT5 PORT EVENT 5
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT4 PORT EVENT 4
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT3 PORT EVENT 3
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT2 PORT EVENT 2
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT1 PORT EVENT 1
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT0 PORT EVENT 0
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// UART1_RTS UART1 RTS
+// UART1_CTS UART1 CTS
+// UART1_TX UART1 TX
+// UART1_RX UART1 RX
+// UART0_RTS UART0 RTS
+// UART0_CTS UART0 CTS
+// UART0_TX UART0 TX
+// UART0_RX UART0 RX
+// I2C_MSSCL I2C Clock
+// I2C_MSSDA I2C Data
+// SSI0_CLK SSI0 CLK
+// SSI0_FSS SSI0 FSS
+// SSI0_TX SSI0 TX
+// SSI0_RX SSI0 RX
+// AUX_IO AUX IO
+// AON_CLK32K AON 32 KHz clock (SCLK_LF)
+// GPIO General Purpose IO
+#define IOC_IOCFG1_PORT_ID_W 6
+#define IOC_IOCFG1_PORT_ID_M 0x0000003F
+#define IOC_IOCFG1_PORT_ID_S 0
+#define IOC_IOCFG1_PORT_ID_RFC_SMI_CL_IN 0x00000038
+#define IOC_IOCFG1_PORT_ID_RFC_SMI_CL_OUT 0x00000037
+#define IOC_IOCFG1_PORT_ID_RFC_SMI_DL_IN 0x00000036
+#define IOC_IOCFG1_PORT_ID_RFC_SMI_DL_OUT 0x00000035
+#define IOC_IOCFG1_PORT_ID_RFC_GPI1 0x00000034
+#define IOC_IOCFG1_PORT_ID_RFC_GPI0 0x00000033
+#define IOC_IOCFG1_PORT_ID_RFC_GPO3 0x00000032
+#define IOC_IOCFG1_PORT_ID_RFC_GPO2 0x00000031
+#define IOC_IOCFG1_PORT_ID_RFC_GPO1 0x00000030
+#define IOC_IOCFG1_PORT_ID_RFC_GPO0 0x0000002F
+#define IOC_IOCFG1_PORT_ID_RFC_TRC 0x0000002E
+#define IOC_IOCFG1_PORT_ID_I2S_MCLK 0x00000029
+#define IOC_IOCFG1_PORT_ID_I2S_BCLK 0x00000028
+#define IOC_IOCFG1_PORT_ID_I2S_WCLK 0x00000027
+#define IOC_IOCFG1_PORT_ID_I2S_AD1 0x00000026
+#define IOC_IOCFG1_PORT_ID_I2S_AD0 0x00000025
+#define IOC_IOCFG1_PORT_ID_SSI1_CLK 0x00000024
+#define IOC_IOCFG1_PORT_ID_SSI1_FSS 0x00000023
+#define IOC_IOCFG1_PORT_ID_SSI1_TX 0x00000022
+#define IOC_IOCFG1_PORT_ID_SSI1_RX 0x00000021
+#define IOC_IOCFG1_PORT_ID_CPU_SWV 0x00000020
+#define IOC_IOCFG1_PORT_ID_PORT_EVENT7 0x0000001E
+#define IOC_IOCFG1_PORT_ID_PORT_EVENT6 0x0000001D
+#define IOC_IOCFG1_PORT_ID_PORT_EVENT5 0x0000001C
+#define IOC_IOCFG1_PORT_ID_PORT_EVENT4 0x0000001B
+#define IOC_IOCFG1_PORT_ID_PORT_EVENT3 0x0000001A
+#define IOC_IOCFG1_PORT_ID_PORT_EVENT2 0x00000019
+#define IOC_IOCFG1_PORT_ID_PORT_EVENT1 0x00000018
+#define IOC_IOCFG1_PORT_ID_PORT_EVENT0 0x00000017
+#define IOC_IOCFG1_PORT_ID_UART1_RTS 0x00000016
+#define IOC_IOCFG1_PORT_ID_UART1_CTS 0x00000015
+#define IOC_IOCFG1_PORT_ID_UART1_TX 0x00000014
+#define IOC_IOCFG1_PORT_ID_UART1_RX 0x00000013
+#define IOC_IOCFG1_PORT_ID_UART0_RTS 0x00000012
+#define IOC_IOCFG1_PORT_ID_UART0_CTS 0x00000011
+#define IOC_IOCFG1_PORT_ID_UART0_TX 0x00000010
+#define IOC_IOCFG1_PORT_ID_UART0_RX 0x0000000F
+#define IOC_IOCFG1_PORT_ID_I2C_MSSCL 0x0000000E
+#define IOC_IOCFG1_PORT_ID_I2C_MSSDA 0x0000000D
+#define IOC_IOCFG1_PORT_ID_SSI0_CLK 0x0000000C
+#define IOC_IOCFG1_PORT_ID_SSI0_FSS 0x0000000B
+#define IOC_IOCFG1_PORT_ID_SSI0_TX 0x0000000A
+#define IOC_IOCFG1_PORT_ID_SSI0_RX 0x00000009
+#define IOC_IOCFG1_PORT_ID_AUX_IO 0x00000008
+#define IOC_IOCFG1_PORT_ID_AON_CLK32K 0x00000007
+#define IOC_IOCFG1_PORT_ID_GPIO 0x00000000
+
+//*****************************************************************************
+//
+// Register: IOC_O_IOCFG2
+//
+//*****************************************************************************
+// Field: [30] HYST_EN
+//
+// 0: Input hysteresis disable
+// 1: Input hysteresis enable
+#define IOC_IOCFG2_HYST_EN 0x40000000
+#define IOC_IOCFG2_HYST_EN_BITN 30
+#define IOC_IOCFG2_HYST_EN_M 0x40000000
+#define IOC_IOCFG2_HYST_EN_S 30
+
+// Field: [29] IE
+//
+// 0: Input disabled
+// 1: Input enabled
+//
+// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be
+// ignored.
+#define IOC_IOCFG2_IE 0x20000000
+#define IOC_IOCFG2_IE_BITN 29
+#define IOC_IOCFG2_IE_M 0x20000000
+#define IOC_IOCFG2_IE_S 29
+
+// Field: [28:27] WU_CFG
+//
+// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or
+// >0x08:
+//
+// 00: No wake-up
+// 01: No wake-up
+// 10: Wakes up from shutdown if this pad is going low.
+// 11: Wakes up from shutdown if this pad is going high.
+//
+// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08,
+// this register only sets wakeup enable or not.
+//
+// 00, 01: Wakeup disabled
+// 10, 11: Wakeup enabled
+//
+// Polarity is controlled from AON registers.
+//
+// Note:When the MSB is set, the IOC will deactivate the output enable for the
+// DIO.
+#define IOC_IOCFG2_WU_CFG_W 2
+#define IOC_IOCFG2_WU_CFG_M 0x18000000
+#define IOC_IOCFG2_WU_CFG_S 27
+
+// Field: [26:24] IOMODE
+//
+// IO Mode
+// Not applicable for IO configured for AON periph. signals and AUX PORT_ID
+// 0x01-0x08
+// AUX has its own open_source/drain configuration.
+//
+// 0x2: Reserved. Undefined behavior.
+// 0x3: Reserved. Undefined behavior.
+// ENUMs:
+// OPENSRC_INV Open Source
+// Inverted input / output
+// OPENSRC Open Source
+// Normal input / output
+// OPENDR_INV Open Drain
+// Inverted input / output
+// OPENDR Open Drain,
+// Normal input / output
+// INV Inverted input / ouput
+// NORMAL Normal input / output
+#define IOC_IOCFG2_IOMODE_W 3
+#define IOC_IOCFG2_IOMODE_M 0x07000000
+#define IOC_IOCFG2_IOMODE_S 24
+#define IOC_IOCFG2_IOMODE_OPENSRC_INV 0x07000000
+#define IOC_IOCFG2_IOMODE_OPENSRC 0x06000000
+#define IOC_IOCFG2_IOMODE_OPENDR_INV 0x05000000
+#define IOC_IOCFG2_IOMODE_OPENDR 0x04000000
+#define IOC_IOCFG2_IOMODE_INV 0x01000000
+#define IOC_IOCFG2_IOMODE_NORMAL 0x00000000
+
+// Field: [23] IOEV_AON_PROG2_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG2 event
+// 1: Input edge detection asserts AON_PROG2 event
+#define IOC_IOCFG2_IOEV_AON_PROG2_EN 0x00800000
+#define IOC_IOCFG2_IOEV_AON_PROG2_EN_BITN 23
+#define IOC_IOCFG2_IOEV_AON_PROG2_EN_M 0x00800000
+#define IOC_IOCFG2_IOEV_AON_PROG2_EN_S 23
+
+// Field: [22] IOEV_AON_PROG1_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG1 event
+// 1: Input edge detection asserts AON_PROG1 event
+#define IOC_IOCFG2_IOEV_AON_PROG1_EN 0x00400000
+#define IOC_IOCFG2_IOEV_AON_PROG1_EN_BITN 22
+#define IOC_IOCFG2_IOEV_AON_PROG1_EN_M 0x00400000
+#define IOC_IOCFG2_IOEV_AON_PROG1_EN_S 22
+
+// Field: [21] IOEV_AON_PROG0_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG0 event
+// 1: Input edge detection asserts AON_PROG0 event
+#define IOC_IOCFG2_IOEV_AON_PROG0_EN 0x00200000
+#define IOC_IOCFG2_IOEV_AON_PROG0_EN_BITN 21
+#define IOC_IOCFG2_IOEV_AON_PROG0_EN_M 0x00200000
+#define IOC_IOCFG2_IOEV_AON_PROG0_EN_S 21
+
+// Field: [18] EDGE_IRQ_EN
+//
+// 0: No interrupt generation
+// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is
+// enabled)
+#define IOC_IOCFG2_EDGE_IRQ_EN 0x00040000
+#define IOC_IOCFG2_EDGE_IRQ_EN_BITN 18
+#define IOC_IOCFG2_EDGE_IRQ_EN_M 0x00040000
+#define IOC_IOCFG2_EDGE_IRQ_EN_S 18
+
+// Field: [17:16] EDGE_DET
+//
+// Enable generation of edge detection events on this IO
+// ENUMs:
+// BOTH Positive and negative edge detection
+// POS Positive edge detection
+// NEG Negative edge detection
+// NONE No edge detection
+#define IOC_IOCFG2_EDGE_DET_W 2
+#define IOC_IOCFG2_EDGE_DET_M 0x00030000
+#define IOC_IOCFG2_EDGE_DET_S 16
+#define IOC_IOCFG2_EDGE_DET_BOTH 0x00030000
+#define IOC_IOCFG2_EDGE_DET_POS 0x00020000
+#define IOC_IOCFG2_EDGE_DET_NEG 0x00010000
+#define IOC_IOCFG2_EDGE_DET_NONE 0x00000000
+
+// Field: [14:13] PULL_CTL
+//
+// Pull control
+// ENUMs:
+// DIS No pull
+// UP Pull up
+// DWN Pull down
+#define IOC_IOCFG2_PULL_CTL_W 2
+#define IOC_IOCFG2_PULL_CTL_M 0x00006000
+#define IOC_IOCFG2_PULL_CTL_S 13
+#define IOC_IOCFG2_PULL_CTL_DIS 0x00006000
+#define IOC_IOCFG2_PULL_CTL_UP 0x00004000
+#define IOC_IOCFG2_PULL_CTL_DWN 0x00002000
+
+// Field: [12] SLEW_RED
+//
+// 0: Normal slew rate
+// 1: Enables reduced slew rate in output driver.
+#define IOC_IOCFG2_SLEW_RED 0x00001000
+#define IOC_IOCFG2_SLEW_RED_BITN 12
+#define IOC_IOCFG2_SLEW_RED_M 0x00001000
+#define IOC_IOCFG2_SLEW_RED_S 12
+
+// Field: [11:10] IOCURR
+//
+// Selects IO current mode of this IO.
+// ENUMs:
+// 4_8MA Extended-Current (EC) mode: Min 8 mA for double
+// drive strength IOs (min 4 mA for normal IOs)
+// when IOSTR is set to AUTO
+// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set
+// to AUTO
+// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set
+// to AUTO
+#define IOC_IOCFG2_IOCURR_W 2
+#define IOC_IOCFG2_IOCURR_M 0x00000C00
+#define IOC_IOCFG2_IOCURR_S 10
+#define IOC_IOCFG2_IOCURR_4_8MA 0x00000800
+#define IOC_IOCFG2_IOCURR_4MA 0x00000400
+#define IOC_IOCFG2_IOCURR_2MA 0x00000000
+
+// Field: [9:8] IOSTR
+//
+// Select source for drive strength control of this IO.
+// This setting controls the drive strength of the Low-Current (LC) mode.
+// Higher drive strength can be selected in IOCURR
+// ENUMs:
+// MAX Maximum drive strength, controlled by
+// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default
+// values)
+// MED Medium drive strength, controlled by
+// AON_IOC:IOSTRMED (min 2 mA @2.5V with default
+// values)
+// MIN Minimum drive strength, controlled by
+// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default
+// values)
+// AUTO Automatic drive strength, controlled by AON BATMON
+// based on battery voltage. (min 2 mA @VDDS)
+#define IOC_IOCFG2_IOSTR_W 2
+#define IOC_IOCFG2_IOSTR_M 0x00000300
+#define IOC_IOCFG2_IOSTR_S 8
+#define IOC_IOCFG2_IOSTR_MAX 0x00000300
+#define IOC_IOCFG2_IOSTR_MED 0x00000200
+#define IOC_IOCFG2_IOSTR_MIN 0x00000100
+#define IOC_IOCFG2_IOSTR_AUTO 0x00000000
+
+// Field: [7] IOEV_RTC_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert RTC event
+// 1: Input edge detection asserts RTC event
+#define IOC_IOCFG2_IOEV_RTC_EN 0x00000080
+#define IOC_IOCFG2_IOEV_RTC_EN_BITN 7
+#define IOC_IOCFG2_IOEV_RTC_EN_M 0x00000080
+#define IOC_IOCFG2_IOEV_RTC_EN_S 7
+
+// Field: [6] IOEV_MCU_WU_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert MCU_WU event
+// 1: Input edge detection asserts MCU_WU event
+#define IOC_IOCFG2_IOEV_MCU_WU_EN 0x00000040
+#define IOC_IOCFG2_IOEV_MCU_WU_EN_BITN 6
+#define IOC_IOCFG2_IOEV_MCU_WU_EN_M 0x00000040
+#define IOC_IOCFG2_IOEV_MCU_WU_EN_S 6
+
+// Field: [5:0] PORT_ID
+//
+// Selects usage for DIO2
+// ENUMs:
+// RFC_SMI_CL_IN RF Core SMI Command Link In
+// RFC_SMI_CL_OUT RF Core SMI Command Link Out
+// RFC_SMI_DL_IN RF Core SMI Data Link In
+// RFC_SMI_DL_OUT RF Core SMI Data Link Out
+// RFC_GPI1 RF Core Data In 1
+// RFC_GPI0 RF Core Data In 0
+// RFC_GPO3 RF Core Data Out 3
+// RFC_GPO2 RF Core Data Out 2
+// RFC_GPO1 RF Core Data Out 1
+// RFC_GPO0 RF Core Data Out 0
+// RFC_TRC RF Core Trace
+// I2S_MCLK I2S MCLK
+// I2S_BCLK I2S BCLK
+// I2S_WCLK I2S WCLK
+// I2S_AD1 I2S Data 1
+// I2S_AD0 I2S Data 0
+// SSI1_CLK SSI1 CLK
+// SSI1_FSS SSI1 FSS
+// SSI1_TX SSI1 TX
+// SSI1_RX SSI1 RX
+// CPU_SWV CPU SWV
+// PORT_EVENT7 PORT EVENT 7
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT6 PORT EVENT 6
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT5 PORT EVENT 5
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT4 PORT EVENT 4
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT3 PORT EVENT 3
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT2 PORT EVENT 2
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT1 PORT EVENT 1
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT0 PORT EVENT 0
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// UART1_RTS UART1 RTS
+// UART1_CTS UART1 CTS
+// UART1_TX UART1 TX
+// UART1_RX UART1 RX
+// UART0_RTS UART0 RTS
+// UART0_CTS UART0 CTS
+// UART0_TX UART0 TX
+// UART0_RX UART0 RX
+// I2C_MSSCL I2C Clock
+// I2C_MSSDA I2C Data
+// SSI0_CLK SSI0 CLK
+// SSI0_FSS SSI0 FSS
+// SSI0_TX SSI0 TX
+// SSI0_RX SSI0 RX
+// AUX_IO AUX IO
+// AON_CLK32K AON 32 KHz clock (SCLK_LF)
+// GPIO General Purpose IO
+#define IOC_IOCFG2_PORT_ID_W 6
+#define IOC_IOCFG2_PORT_ID_M 0x0000003F
+#define IOC_IOCFG2_PORT_ID_S 0
+#define IOC_IOCFG2_PORT_ID_RFC_SMI_CL_IN 0x00000038
+#define IOC_IOCFG2_PORT_ID_RFC_SMI_CL_OUT 0x00000037
+#define IOC_IOCFG2_PORT_ID_RFC_SMI_DL_IN 0x00000036
+#define IOC_IOCFG2_PORT_ID_RFC_SMI_DL_OUT 0x00000035
+#define IOC_IOCFG2_PORT_ID_RFC_GPI1 0x00000034
+#define IOC_IOCFG2_PORT_ID_RFC_GPI0 0x00000033
+#define IOC_IOCFG2_PORT_ID_RFC_GPO3 0x00000032
+#define IOC_IOCFG2_PORT_ID_RFC_GPO2 0x00000031
+#define IOC_IOCFG2_PORT_ID_RFC_GPO1 0x00000030
+#define IOC_IOCFG2_PORT_ID_RFC_GPO0 0x0000002F
+#define IOC_IOCFG2_PORT_ID_RFC_TRC 0x0000002E
+#define IOC_IOCFG2_PORT_ID_I2S_MCLK 0x00000029
+#define IOC_IOCFG2_PORT_ID_I2S_BCLK 0x00000028
+#define IOC_IOCFG2_PORT_ID_I2S_WCLK 0x00000027
+#define IOC_IOCFG2_PORT_ID_I2S_AD1 0x00000026
+#define IOC_IOCFG2_PORT_ID_I2S_AD0 0x00000025
+#define IOC_IOCFG2_PORT_ID_SSI1_CLK 0x00000024
+#define IOC_IOCFG2_PORT_ID_SSI1_FSS 0x00000023
+#define IOC_IOCFG2_PORT_ID_SSI1_TX 0x00000022
+#define IOC_IOCFG2_PORT_ID_SSI1_RX 0x00000021
+#define IOC_IOCFG2_PORT_ID_CPU_SWV 0x00000020
+#define IOC_IOCFG2_PORT_ID_PORT_EVENT7 0x0000001E
+#define IOC_IOCFG2_PORT_ID_PORT_EVENT6 0x0000001D
+#define IOC_IOCFG2_PORT_ID_PORT_EVENT5 0x0000001C
+#define IOC_IOCFG2_PORT_ID_PORT_EVENT4 0x0000001B
+#define IOC_IOCFG2_PORT_ID_PORT_EVENT3 0x0000001A
+#define IOC_IOCFG2_PORT_ID_PORT_EVENT2 0x00000019
+#define IOC_IOCFG2_PORT_ID_PORT_EVENT1 0x00000018
+#define IOC_IOCFG2_PORT_ID_PORT_EVENT0 0x00000017
+#define IOC_IOCFG2_PORT_ID_UART1_RTS 0x00000016
+#define IOC_IOCFG2_PORT_ID_UART1_CTS 0x00000015
+#define IOC_IOCFG2_PORT_ID_UART1_TX 0x00000014
+#define IOC_IOCFG2_PORT_ID_UART1_RX 0x00000013
+#define IOC_IOCFG2_PORT_ID_UART0_RTS 0x00000012
+#define IOC_IOCFG2_PORT_ID_UART0_CTS 0x00000011
+#define IOC_IOCFG2_PORT_ID_UART0_TX 0x00000010
+#define IOC_IOCFG2_PORT_ID_UART0_RX 0x0000000F
+#define IOC_IOCFG2_PORT_ID_I2C_MSSCL 0x0000000E
+#define IOC_IOCFG2_PORT_ID_I2C_MSSDA 0x0000000D
+#define IOC_IOCFG2_PORT_ID_SSI0_CLK 0x0000000C
+#define IOC_IOCFG2_PORT_ID_SSI0_FSS 0x0000000B
+#define IOC_IOCFG2_PORT_ID_SSI0_TX 0x0000000A
+#define IOC_IOCFG2_PORT_ID_SSI0_RX 0x00000009
+#define IOC_IOCFG2_PORT_ID_AUX_IO 0x00000008
+#define IOC_IOCFG2_PORT_ID_AON_CLK32K 0x00000007
+#define IOC_IOCFG2_PORT_ID_GPIO 0x00000000
+
+//*****************************************************************************
+//
+// Register: IOC_O_IOCFG3
+//
+//*****************************************************************************
+// Field: [30] HYST_EN
+//
+// 0: Input hysteresis disable
+// 1: Input hysteresis enable
+#define IOC_IOCFG3_HYST_EN 0x40000000
+#define IOC_IOCFG3_HYST_EN_BITN 30
+#define IOC_IOCFG3_HYST_EN_M 0x40000000
+#define IOC_IOCFG3_HYST_EN_S 30
+
+// Field: [29] IE
+//
+// 0: Input disabled
+// 1: Input enabled
+//
+// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be
+// ignored.
+#define IOC_IOCFG3_IE 0x20000000
+#define IOC_IOCFG3_IE_BITN 29
+#define IOC_IOCFG3_IE_M 0x20000000
+#define IOC_IOCFG3_IE_S 29
+
+// Field: [28:27] WU_CFG
+//
+// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or
+// >0x08:
+//
+// 00: No wake-up
+// 01: No wake-up
+// 10: Wakes up from shutdown if this pad is going low.
+// 11: Wakes up from shutdown if this pad is going high.
+//
+// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08,
+// this register only sets wakeup enable or not.
+//
+// 00, 01: Wakeup disabled
+// 10, 11: Wakeup enabled
+//
+// Polarity is controlled from AON registers.
+//
+// Note:When the MSB is set, the IOC will deactivate the output enable for the
+// DIO.
+#define IOC_IOCFG3_WU_CFG_W 2
+#define IOC_IOCFG3_WU_CFG_M 0x18000000
+#define IOC_IOCFG3_WU_CFG_S 27
+
+// Field: [26:24] IOMODE
+//
+// IO Mode
+// Not applicable for IO configured for AON periph. signals and AUX PORT_ID
+// 0x01-0x08
+// AUX has its own open_source/drain configuration.
+//
+// 0x2: Reserved. Undefined behavior.
+// 0x3: Reserved. Undefined behavior.
+// ENUMs:
+// OPENSRC_INV Open Source
+// Inverted input / output
+// OPENSRC Open Source
+// Normal input / output
+// OPENDR_INV Open Drain
+// Inverted input / output
+// OPENDR Open Drain,
+// Normal input / output
+// INV Inverted input / ouput
+// NORMAL Normal input / output
+#define IOC_IOCFG3_IOMODE_W 3
+#define IOC_IOCFG3_IOMODE_M 0x07000000
+#define IOC_IOCFG3_IOMODE_S 24
+#define IOC_IOCFG3_IOMODE_OPENSRC_INV 0x07000000
+#define IOC_IOCFG3_IOMODE_OPENSRC 0x06000000
+#define IOC_IOCFG3_IOMODE_OPENDR_INV 0x05000000
+#define IOC_IOCFG3_IOMODE_OPENDR 0x04000000
+#define IOC_IOCFG3_IOMODE_INV 0x01000000
+#define IOC_IOCFG3_IOMODE_NORMAL 0x00000000
+
+// Field: [23] IOEV_AON_PROG2_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG2 event
+// 1: Input edge detection asserts AON_PROG2 event
+#define IOC_IOCFG3_IOEV_AON_PROG2_EN 0x00800000
+#define IOC_IOCFG3_IOEV_AON_PROG2_EN_BITN 23
+#define IOC_IOCFG3_IOEV_AON_PROG2_EN_M 0x00800000
+#define IOC_IOCFG3_IOEV_AON_PROG2_EN_S 23
+
+// Field: [22] IOEV_AON_PROG1_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG1 event
+// 1: Input edge detection asserts AON_PROG1 event
+#define IOC_IOCFG3_IOEV_AON_PROG1_EN 0x00400000
+#define IOC_IOCFG3_IOEV_AON_PROG1_EN_BITN 22
+#define IOC_IOCFG3_IOEV_AON_PROG1_EN_M 0x00400000
+#define IOC_IOCFG3_IOEV_AON_PROG1_EN_S 22
+
+// Field: [21] IOEV_AON_PROG0_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG0 event
+// 1: Input edge detection asserts AON_PROG0 event
+#define IOC_IOCFG3_IOEV_AON_PROG0_EN 0x00200000
+#define IOC_IOCFG3_IOEV_AON_PROG0_EN_BITN 21
+#define IOC_IOCFG3_IOEV_AON_PROG0_EN_M 0x00200000
+#define IOC_IOCFG3_IOEV_AON_PROG0_EN_S 21
+
+// Field: [18] EDGE_IRQ_EN
+//
+// 0: No interrupt generation
+// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is
+// enabled)
+#define IOC_IOCFG3_EDGE_IRQ_EN 0x00040000
+#define IOC_IOCFG3_EDGE_IRQ_EN_BITN 18
+#define IOC_IOCFG3_EDGE_IRQ_EN_M 0x00040000
+#define IOC_IOCFG3_EDGE_IRQ_EN_S 18
+
+// Field: [17:16] EDGE_DET
+//
+// Enable generation of edge detection events on this IO
+// ENUMs:
+// BOTH Positive and negative edge detection
+// POS Positive edge detection
+// NEG Negative edge detection
+// NONE No edge detection
+#define IOC_IOCFG3_EDGE_DET_W 2
+#define IOC_IOCFG3_EDGE_DET_M 0x00030000
+#define IOC_IOCFG3_EDGE_DET_S 16
+#define IOC_IOCFG3_EDGE_DET_BOTH 0x00030000
+#define IOC_IOCFG3_EDGE_DET_POS 0x00020000
+#define IOC_IOCFG3_EDGE_DET_NEG 0x00010000
+#define IOC_IOCFG3_EDGE_DET_NONE 0x00000000
+
+// Field: [14:13] PULL_CTL
+//
+// Pull control
+// ENUMs:
+// DIS No pull
+// UP Pull up
+// DWN Pull down
+#define IOC_IOCFG3_PULL_CTL_W 2
+#define IOC_IOCFG3_PULL_CTL_M 0x00006000
+#define IOC_IOCFG3_PULL_CTL_S 13
+#define IOC_IOCFG3_PULL_CTL_DIS 0x00006000
+#define IOC_IOCFG3_PULL_CTL_UP 0x00004000
+#define IOC_IOCFG3_PULL_CTL_DWN 0x00002000
+
+// Field: [12] SLEW_RED
+//
+// 0: Normal slew rate
+// 1: Enables reduced slew rate in output driver.
+#define IOC_IOCFG3_SLEW_RED 0x00001000
+#define IOC_IOCFG3_SLEW_RED_BITN 12
+#define IOC_IOCFG3_SLEW_RED_M 0x00001000
+#define IOC_IOCFG3_SLEW_RED_S 12
+
+// Field: [11:10] IOCURR
+//
+// Selects IO current mode of this IO.
+// ENUMs:
+// 4_8MA Extended-Current (EC) mode: Min 8 mA for double
+// drive strength IOs (min 4 mA for normal IOs)
+// when IOSTR is set to AUTO
+// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set
+// to AUTO
+// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set
+// to AUTO
+#define IOC_IOCFG3_IOCURR_W 2
+#define IOC_IOCFG3_IOCURR_M 0x00000C00
+#define IOC_IOCFG3_IOCURR_S 10
+#define IOC_IOCFG3_IOCURR_4_8MA 0x00000800
+#define IOC_IOCFG3_IOCURR_4MA 0x00000400
+#define IOC_IOCFG3_IOCURR_2MA 0x00000000
+
+// Field: [9:8] IOSTR
+//
+// Select source for drive strength control of this IO.
+// This setting controls the drive strength of the Low-Current (LC) mode.
+// Higher drive strength can be selected in IOCURR
+// ENUMs:
+// MAX Maximum drive strength, controlled by
+// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default
+// values)
+// MED Medium drive strength, controlled by
+// AON_IOC:IOSTRMED (min 2 mA @2.5V with default
+// values)
+// MIN Minimum drive strength, controlled by
+// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default
+// values)
+// AUTO Automatic drive strength, controlled by AON BATMON
+// based on battery voltage. (min 2 mA @VDDS)
+#define IOC_IOCFG3_IOSTR_W 2
+#define IOC_IOCFG3_IOSTR_M 0x00000300
+#define IOC_IOCFG3_IOSTR_S 8
+#define IOC_IOCFG3_IOSTR_MAX 0x00000300
+#define IOC_IOCFG3_IOSTR_MED 0x00000200
+#define IOC_IOCFG3_IOSTR_MIN 0x00000100
+#define IOC_IOCFG3_IOSTR_AUTO 0x00000000
+
+// Field: [7] IOEV_RTC_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert RTC event
+// 1: Input edge detection asserts RTC event
+#define IOC_IOCFG3_IOEV_RTC_EN 0x00000080
+#define IOC_IOCFG3_IOEV_RTC_EN_BITN 7
+#define IOC_IOCFG3_IOEV_RTC_EN_M 0x00000080
+#define IOC_IOCFG3_IOEV_RTC_EN_S 7
+
+// Field: [6] IOEV_MCU_WU_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert MCU_WU event
+// 1: Input edge detection asserts MCU_WU event
+#define IOC_IOCFG3_IOEV_MCU_WU_EN 0x00000040
+#define IOC_IOCFG3_IOEV_MCU_WU_EN_BITN 6
+#define IOC_IOCFG3_IOEV_MCU_WU_EN_M 0x00000040
+#define IOC_IOCFG3_IOEV_MCU_WU_EN_S 6
+
+// Field: [5:0] PORT_ID
+//
+// Selects usage for DIO3
+// ENUMs:
+// RFC_SMI_CL_IN RF Core SMI Command Link In
+// RFC_SMI_CL_OUT RF Core SMI Command Link Out
+// RFC_SMI_DL_IN RF Core SMI Data Link In
+// RFC_SMI_DL_OUT RF Core SMI Data Link Out
+// RFC_GPI1 RF Core Data In 1
+// RFC_GPI0 RF Core Data In 0
+// RFC_GPO3 RF Core Data Out 3
+// RFC_GPO2 RF Core Data Out 2
+// RFC_GPO1 RF Core Data Out 1
+// RFC_GPO0 RF Core Data Out 0
+// RFC_TRC RF Core Trace
+// I2S_MCLK I2S MCLK
+// I2S_BCLK I2S BCLK
+// I2S_WCLK I2S WCLK
+// I2S_AD1 I2S Data 1
+// I2S_AD0 I2S Data 0
+// SSI1_CLK SSI1 CLK
+// SSI1_FSS SSI1 FSS
+// SSI1_TX SSI1 TX
+// SSI1_RX SSI1 RX
+// CPU_SWV CPU SWV
+// PORT_EVENT7 PORT EVENT 7
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT6 PORT EVENT 6
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT5 PORT EVENT 5
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT4 PORT EVENT 4
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT3 PORT EVENT 3
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT2 PORT EVENT 2
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT1 PORT EVENT 1
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT0 PORT EVENT 0
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// UART1_RTS UART1 RTS
+// UART1_CTS UART1 CTS
+// UART1_TX UART1 TX
+// UART1_RX UART1 RX
+// UART0_RTS UART0 RTS
+// UART0_CTS UART0 CTS
+// UART0_TX UART0 TX
+// UART0_RX UART0 RX
+// I2C_MSSCL I2C Clock
+// I2C_MSSDA I2C Data
+// SSI0_CLK SSI0 CLK
+// SSI0_FSS SSI0 FSS
+// SSI0_TX SSI0 TX
+// SSI0_RX SSI0 RX
+// AUX_IO AUX IO
+// AON_CLK32K AON 32 KHz clock (SCLK_LF)
+// GPIO General Purpose IO
+#define IOC_IOCFG3_PORT_ID_W 6
+#define IOC_IOCFG3_PORT_ID_M 0x0000003F
+#define IOC_IOCFG3_PORT_ID_S 0
+#define IOC_IOCFG3_PORT_ID_RFC_SMI_CL_IN 0x00000038
+#define IOC_IOCFG3_PORT_ID_RFC_SMI_CL_OUT 0x00000037
+#define IOC_IOCFG3_PORT_ID_RFC_SMI_DL_IN 0x00000036
+#define IOC_IOCFG3_PORT_ID_RFC_SMI_DL_OUT 0x00000035
+#define IOC_IOCFG3_PORT_ID_RFC_GPI1 0x00000034
+#define IOC_IOCFG3_PORT_ID_RFC_GPI0 0x00000033
+#define IOC_IOCFG3_PORT_ID_RFC_GPO3 0x00000032
+#define IOC_IOCFG3_PORT_ID_RFC_GPO2 0x00000031
+#define IOC_IOCFG3_PORT_ID_RFC_GPO1 0x00000030
+#define IOC_IOCFG3_PORT_ID_RFC_GPO0 0x0000002F
+#define IOC_IOCFG3_PORT_ID_RFC_TRC 0x0000002E
+#define IOC_IOCFG3_PORT_ID_I2S_MCLK 0x00000029
+#define IOC_IOCFG3_PORT_ID_I2S_BCLK 0x00000028
+#define IOC_IOCFG3_PORT_ID_I2S_WCLK 0x00000027
+#define IOC_IOCFG3_PORT_ID_I2S_AD1 0x00000026
+#define IOC_IOCFG3_PORT_ID_I2S_AD0 0x00000025
+#define IOC_IOCFG3_PORT_ID_SSI1_CLK 0x00000024
+#define IOC_IOCFG3_PORT_ID_SSI1_FSS 0x00000023
+#define IOC_IOCFG3_PORT_ID_SSI1_TX 0x00000022
+#define IOC_IOCFG3_PORT_ID_SSI1_RX 0x00000021
+#define IOC_IOCFG3_PORT_ID_CPU_SWV 0x00000020
+#define IOC_IOCFG3_PORT_ID_PORT_EVENT7 0x0000001E
+#define IOC_IOCFG3_PORT_ID_PORT_EVENT6 0x0000001D
+#define IOC_IOCFG3_PORT_ID_PORT_EVENT5 0x0000001C
+#define IOC_IOCFG3_PORT_ID_PORT_EVENT4 0x0000001B
+#define IOC_IOCFG3_PORT_ID_PORT_EVENT3 0x0000001A
+#define IOC_IOCFG3_PORT_ID_PORT_EVENT2 0x00000019
+#define IOC_IOCFG3_PORT_ID_PORT_EVENT1 0x00000018
+#define IOC_IOCFG3_PORT_ID_PORT_EVENT0 0x00000017
+#define IOC_IOCFG3_PORT_ID_UART1_RTS 0x00000016
+#define IOC_IOCFG3_PORT_ID_UART1_CTS 0x00000015
+#define IOC_IOCFG3_PORT_ID_UART1_TX 0x00000014
+#define IOC_IOCFG3_PORT_ID_UART1_RX 0x00000013
+#define IOC_IOCFG3_PORT_ID_UART0_RTS 0x00000012
+#define IOC_IOCFG3_PORT_ID_UART0_CTS 0x00000011
+#define IOC_IOCFG3_PORT_ID_UART0_TX 0x00000010
+#define IOC_IOCFG3_PORT_ID_UART0_RX 0x0000000F
+#define IOC_IOCFG3_PORT_ID_I2C_MSSCL 0x0000000E
+#define IOC_IOCFG3_PORT_ID_I2C_MSSDA 0x0000000D
+#define IOC_IOCFG3_PORT_ID_SSI0_CLK 0x0000000C
+#define IOC_IOCFG3_PORT_ID_SSI0_FSS 0x0000000B
+#define IOC_IOCFG3_PORT_ID_SSI0_TX 0x0000000A
+#define IOC_IOCFG3_PORT_ID_SSI0_RX 0x00000009
+#define IOC_IOCFG3_PORT_ID_AUX_IO 0x00000008
+#define IOC_IOCFG3_PORT_ID_AON_CLK32K 0x00000007
+#define IOC_IOCFG3_PORT_ID_GPIO 0x00000000
+
+//*****************************************************************************
+//
+// Register: IOC_O_IOCFG4
+//
+//*****************************************************************************
+// Field: [30] HYST_EN
+//
+// 0: Input hysteresis disable
+// 1: Input hysteresis enable
+#define IOC_IOCFG4_HYST_EN 0x40000000
+#define IOC_IOCFG4_HYST_EN_BITN 30
+#define IOC_IOCFG4_HYST_EN_M 0x40000000
+#define IOC_IOCFG4_HYST_EN_S 30
+
+// Field: [29] IE
+//
+// 0: Input disabled
+// 1: Input enabled
+//
+// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be
+// ignored.
+#define IOC_IOCFG4_IE 0x20000000
+#define IOC_IOCFG4_IE_BITN 29
+#define IOC_IOCFG4_IE_M 0x20000000
+#define IOC_IOCFG4_IE_S 29
+
+// Field: [28:27] WU_CFG
+//
+// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or
+// >0x08:
+//
+// 00: No wake-up
+// 01: No wake-up
+// 10: Wakes up from shutdown if this pad is going low.
+// 11: Wakes up from shutdown if this pad is going high.
+//
+// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08,
+// this register only sets wakeup enable or not.
+//
+// 00, 01: Wakeup disabled
+// 10, 11: Wakeup enabled
+//
+// Polarity is controlled from AON registers.
+//
+// Note:When the MSB is set, the IOC will deactivate the output enable for the
+// DIO.
+#define IOC_IOCFG4_WU_CFG_W 2
+#define IOC_IOCFG4_WU_CFG_M 0x18000000
+#define IOC_IOCFG4_WU_CFG_S 27
+
+// Field: [26:24] IOMODE
+//
+// IO Mode
+// Not applicable for IO configured for AON periph. signals and AUX PORT_ID
+// 0x01-0x08
+// AUX has its own open_source/drain configuration.
+//
+// 0x2: Reserved. Undefined behavior.
+// 0x3: Reserved. Undefined behavior.
+// ENUMs:
+// OPENSRC_INV Open Source
+// Inverted input / output
+// OPENSRC Open Source
+// Normal input / output
+// OPENDR_INV Open Drain
+// Inverted input / output
+// OPENDR Open Drain,
+// Normal input / output
+// INV Inverted input / ouput
+// NORMAL Normal input / output
+#define IOC_IOCFG4_IOMODE_W 3
+#define IOC_IOCFG4_IOMODE_M 0x07000000
+#define IOC_IOCFG4_IOMODE_S 24
+#define IOC_IOCFG4_IOMODE_OPENSRC_INV 0x07000000
+#define IOC_IOCFG4_IOMODE_OPENSRC 0x06000000
+#define IOC_IOCFG4_IOMODE_OPENDR_INV 0x05000000
+#define IOC_IOCFG4_IOMODE_OPENDR 0x04000000
+#define IOC_IOCFG4_IOMODE_INV 0x01000000
+#define IOC_IOCFG4_IOMODE_NORMAL 0x00000000
+
+// Field: [23] IOEV_AON_PROG2_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG2 event
+// 1: Input edge detection asserts AON_PROG2 event
+#define IOC_IOCFG4_IOEV_AON_PROG2_EN 0x00800000
+#define IOC_IOCFG4_IOEV_AON_PROG2_EN_BITN 23
+#define IOC_IOCFG4_IOEV_AON_PROG2_EN_M 0x00800000
+#define IOC_IOCFG4_IOEV_AON_PROG2_EN_S 23
+
+// Field: [22] IOEV_AON_PROG1_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG1 event
+// 1: Input edge detection asserts AON_PROG1 event
+#define IOC_IOCFG4_IOEV_AON_PROG1_EN 0x00400000
+#define IOC_IOCFG4_IOEV_AON_PROG1_EN_BITN 22
+#define IOC_IOCFG4_IOEV_AON_PROG1_EN_M 0x00400000
+#define IOC_IOCFG4_IOEV_AON_PROG1_EN_S 22
+
+// Field: [21] IOEV_AON_PROG0_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG0 event
+// 1: Input edge detection asserts AON_PROG0 event
+#define IOC_IOCFG4_IOEV_AON_PROG0_EN 0x00200000
+#define IOC_IOCFG4_IOEV_AON_PROG0_EN_BITN 21
+#define IOC_IOCFG4_IOEV_AON_PROG0_EN_M 0x00200000
+#define IOC_IOCFG4_IOEV_AON_PROG0_EN_S 21
+
+// Field: [18] EDGE_IRQ_EN
+//
+// 0: No interrupt generation
+// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is
+// enabled)
+#define IOC_IOCFG4_EDGE_IRQ_EN 0x00040000
+#define IOC_IOCFG4_EDGE_IRQ_EN_BITN 18
+#define IOC_IOCFG4_EDGE_IRQ_EN_M 0x00040000
+#define IOC_IOCFG4_EDGE_IRQ_EN_S 18
+
+// Field: [17:16] EDGE_DET
+//
+// Enable generation of edge detection events on this IO
+// ENUMs:
+// BOTH Positive and negative edge detection
+// POS Positive edge detection
+// NEG Negative edge detection
+// NONE No edge detection
+#define IOC_IOCFG4_EDGE_DET_W 2
+#define IOC_IOCFG4_EDGE_DET_M 0x00030000
+#define IOC_IOCFG4_EDGE_DET_S 16
+#define IOC_IOCFG4_EDGE_DET_BOTH 0x00030000
+#define IOC_IOCFG4_EDGE_DET_POS 0x00020000
+#define IOC_IOCFG4_EDGE_DET_NEG 0x00010000
+#define IOC_IOCFG4_EDGE_DET_NONE 0x00000000
+
+// Field: [14:13] PULL_CTL
+//
+// Pull control
+// ENUMs:
+// DIS No pull
+// UP Pull up
+// DWN Pull down
+#define IOC_IOCFG4_PULL_CTL_W 2
+#define IOC_IOCFG4_PULL_CTL_M 0x00006000
+#define IOC_IOCFG4_PULL_CTL_S 13
+#define IOC_IOCFG4_PULL_CTL_DIS 0x00006000
+#define IOC_IOCFG4_PULL_CTL_UP 0x00004000
+#define IOC_IOCFG4_PULL_CTL_DWN 0x00002000
+
+// Field: [12] SLEW_RED
+//
+// 0: Normal slew rate
+// 1: Enables reduced slew rate in output driver.
+#define IOC_IOCFG4_SLEW_RED 0x00001000
+#define IOC_IOCFG4_SLEW_RED_BITN 12
+#define IOC_IOCFG4_SLEW_RED_M 0x00001000
+#define IOC_IOCFG4_SLEW_RED_S 12
+
+// Field: [11:10] IOCURR
+//
+// Selects IO current mode of this IO.
+// ENUMs:
+// 4_8MA Extended-Current (EC) mode: Min 8 mA for double
+// drive strength IOs (min 4 mA for normal IOs)
+// when IOSTR is set to AUTO
+// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set
+// to AUTO
+// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set
+// to AUTO
+#define IOC_IOCFG4_IOCURR_W 2
+#define IOC_IOCFG4_IOCURR_M 0x00000C00
+#define IOC_IOCFG4_IOCURR_S 10
+#define IOC_IOCFG4_IOCURR_4_8MA 0x00000800
+#define IOC_IOCFG4_IOCURR_4MA 0x00000400
+#define IOC_IOCFG4_IOCURR_2MA 0x00000000
+
+// Field: [9:8] IOSTR
+//
+// Select source for drive strength control of this IO.
+// This setting controls the drive strength of the Low-Current (LC) mode.
+// Higher drive strength can be selected in IOCURR
+// ENUMs:
+// MAX Maximum drive strength, controlled by
+// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default
+// values)
+// MED Medium drive strength, controlled by
+// AON_IOC:IOSTRMED (min 2 mA @2.5V with default
+// values)
+// MIN Minimum drive strength, controlled by
+// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default
+// values)
+// AUTO Automatic drive strength, controlled by AON BATMON
+// based on battery voltage. (min 2 mA @VDDS)
+#define IOC_IOCFG4_IOSTR_W 2
+#define IOC_IOCFG4_IOSTR_M 0x00000300
+#define IOC_IOCFG4_IOSTR_S 8
+#define IOC_IOCFG4_IOSTR_MAX 0x00000300
+#define IOC_IOCFG4_IOSTR_MED 0x00000200
+#define IOC_IOCFG4_IOSTR_MIN 0x00000100
+#define IOC_IOCFG4_IOSTR_AUTO 0x00000000
+
+// Field: [7] IOEV_RTC_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert RTC event
+// 1: Input edge detection asserts RTC event
+#define IOC_IOCFG4_IOEV_RTC_EN 0x00000080
+#define IOC_IOCFG4_IOEV_RTC_EN_BITN 7
+#define IOC_IOCFG4_IOEV_RTC_EN_M 0x00000080
+#define IOC_IOCFG4_IOEV_RTC_EN_S 7
+
+// Field: [6] IOEV_MCU_WU_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert MCU_WU event
+// 1: Input edge detection asserts MCU_WU event
+#define IOC_IOCFG4_IOEV_MCU_WU_EN 0x00000040
+#define IOC_IOCFG4_IOEV_MCU_WU_EN_BITN 6
+#define IOC_IOCFG4_IOEV_MCU_WU_EN_M 0x00000040
+#define IOC_IOCFG4_IOEV_MCU_WU_EN_S 6
+
+// Field: [5:0] PORT_ID
+//
+// Selects usage for DIO4
+// ENUMs:
+// RFC_SMI_CL_IN RF Core SMI Command Link In
+// RFC_SMI_CL_OUT RF Core SMI Command Link Out
+// RFC_SMI_DL_IN RF Core SMI Data Link In
+// RFC_SMI_DL_OUT RF Core SMI Data Link Out
+// RFC_GPI1 RF Core Data In 1
+// RFC_GPI0 RF Core Data In 0
+// RFC_GPO3 RF Core Data Out 3
+// RFC_GPO2 RF Core Data Out 2
+// RFC_GPO1 RF Core Data Out 1
+// RFC_GPO0 RF Core Data Out 0
+// RFC_TRC RF Core Trace
+// I2S_MCLK I2S MCLK
+// I2S_BCLK I2S BCLK
+// I2S_WCLK I2S WCLK
+// I2S_AD1 I2S Data 1
+// I2S_AD0 I2S Data 0
+// SSI1_CLK SSI1 CLK
+// SSI1_FSS SSI1 FSS
+// SSI1_TX SSI1 TX
+// SSI1_RX SSI1 RX
+// CPU_SWV CPU SWV
+// PORT_EVENT7 PORT EVENT 7
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT6 PORT EVENT 6
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT5 PORT EVENT 5
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT4 PORT EVENT 4
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT3 PORT EVENT 3
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT2 PORT EVENT 2
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT1 PORT EVENT 1
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT0 PORT EVENT 0
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// UART1_RTS UART1 RTS
+// UART1_CTS UART1 CTS
+// UART1_TX UART1 TX
+// UART1_RX UART1 RX
+// UART0_RTS UART0 RTS
+// UART0_CTS UART0 CTS
+// UART0_TX UART0 TX
+// UART0_RX UART0 RX
+// I2C_MSSCL I2C Clock
+// I2C_MSSDA I2C Data
+// SSI0_CLK SSI0 CLK
+// SSI0_FSS SSI0 FSS
+// SSI0_TX SSI0 TX
+// SSI0_RX SSI0 RX
+// AUX_IO AUX IO
+// AON_CLK32K AON 32 KHz clock (SCLK_LF)
+// GPIO General Purpose IO
+#define IOC_IOCFG4_PORT_ID_W 6
+#define IOC_IOCFG4_PORT_ID_M 0x0000003F
+#define IOC_IOCFG4_PORT_ID_S 0
+#define IOC_IOCFG4_PORT_ID_RFC_SMI_CL_IN 0x00000038
+#define IOC_IOCFG4_PORT_ID_RFC_SMI_CL_OUT 0x00000037
+#define IOC_IOCFG4_PORT_ID_RFC_SMI_DL_IN 0x00000036
+#define IOC_IOCFG4_PORT_ID_RFC_SMI_DL_OUT 0x00000035
+#define IOC_IOCFG4_PORT_ID_RFC_GPI1 0x00000034
+#define IOC_IOCFG4_PORT_ID_RFC_GPI0 0x00000033
+#define IOC_IOCFG4_PORT_ID_RFC_GPO3 0x00000032
+#define IOC_IOCFG4_PORT_ID_RFC_GPO2 0x00000031
+#define IOC_IOCFG4_PORT_ID_RFC_GPO1 0x00000030
+#define IOC_IOCFG4_PORT_ID_RFC_GPO0 0x0000002F
+#define IOC_IOCFG4_PORT_ID_RFC_TRC 0x0000002E
+#define IOC_IOCFG4_PORT_ID_I2S_MCLK 0x00000029
+#define IOC_IOCFG4_PORT_ID_I2S_BCLK 0x00000028
+#define IOC_IOCFG4_PORT_ID_I2S_WCLK 0x00000027
+#define IOC_IOCFG4_PORT_ID_I2S_AD1 0x00000026
+#define IOC_IOCFG4_PORT_ID_I2S_AD0 0x00000025
+#define IOC_IOCFG4_PORT_ID_SSI1_CLK 0x00000024
+#define IOC_IOCFG4_PORT_ID_SSI1_FSS 0x00000023
+#define IOC_IOCFG4_PORT_ID_SSI1_TX 0x00000022
+#define IOC_IOCFG4_PORT_ID_SSI1_RX 0x00000021
+#define IOC_IOCFG4_PORT_ID_CPU_SWV 0x00000020
+#define IOC_IOCFG4_PORT_ID_PORT_EVENT7 0x0000001E
+#define IOC_IOCFG4_PORT_ID_PORT_EVENT6 0x0000001D
+#define IOC_IOCFG4_PORT_ID_PORT_EVENT5 0x0000001C
+#define IOC_IOCFG4_PORT_ID_PORT_EVENT4 0x0000001B
+#define IOC_IOCFG4_PORT_ID_PORT_EVENT3 0x0000001A
+#define IOC_IOCFG4_PORT_ID_PORT_EVENT2 0x00000019
+#define IOC_IOCFG4_PORT_ID_PORT_EVENT1 0x00000018
+#define IOC_IOCFG4_PORT_ID_PORT_EVENT0 0x00000017
+#define IOC_IOCFG4_PORT_ID_UART1_RTS 0x00000016
+#define IOC_IOCFG4_PORT_ID_UART1_CTS 0x00000015
+#define IOC_IOCFG4_PORT_ID_UART1_TX 0x00000014
+#define IOC_IOCFG4_PORT_ID_UART1_RX 0x00000013
+#define IOC_IOCFG4_PORT_ID_UART0_RTS 0x00000012
+#define IOC_IOCFG4_PORT_ID_UART0_CTS 0x00000011
+#define IOC_IOCFG4_PORT_ID_UART0_TX 0x00000010
+#define IOC_IOCFG4_PORT_ID_UART0_RX 0x0000000F
+#define IOC_IOCFG4_PORT_ID_I2C_MSSCL 0x0000000E
+#define IOC_IOCFG4_PORT_ID_I2C_MSSDA 0x0000000D
+#define IOC_IOCFG4_PORT_ID_SSI0_CLK 0x0000000C
+#define IOC_IOCFG4_PORT_ID_SSI0_FSS 0x0000000B
+#define IOC_IOCFG4_PORT_ID_SSI0_TX 0x0000000A
+#define IOC_IOCFG4_PORT_ID_SSI0_RX 0x00000009
+#define IOC_IOCFG4_PORT_ID_AUX_IO 0x00000008
+#define IOC_IOCFG4_PORT_ID_AON_CLK32K 0x00000007
+#define IOC_IOCFG4_PORT_ID_GPIO 0x00000000
+
+//*****************************************************************************
+//
+// Register: IOC_O_IOCFG5
+//
+//*****************************************************************************
+// Field: [30] HYST_EN
+//
+// 0: Input hysteresis disable
+// 1: Input hysteresis enable
+#define IOC_IOCFG5_HYST_EN 0x40000000
+#define IOC_IOCFG5_HYST_EN_BITN 30
+#define IOC_IOCFG5_HYST_EN_M 0x40000000
+#define IOC_IOCFG5_HYST_EN_S 30
+
+// Field: [29] IE
+//
+// 0: Input disabled
+// 1: Input enabled
+//
+// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be
+// ignored.
+#define IOC_IOCFG5_IE 0x20000000
+#define IOC_IOCFG5_IE_BITN 29
+#define IOC_IOCFG5_IE_M 0x20000000
+#define IOC_IOCFG5_IE_S 29
+
+// Field: [28:27] WU_CFG
+//
+// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or
+// >0x08:
+//
+// 00: No wake-up
+// 01: No wake-up
+// 10: Wakes up from shutdown if this pad is going low.
+// 11: Wakes up from shutdown if this pad is going high.
+//
+// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08,
+// this register only sets wakeup enable or not.
+//
+// 00, 01: Wakeup disabled
+// 10, 11: Wakeup enabled
+//
+// Polarity is controlled from AON registers.
+//
+// Note:When the MSB is set, the IOC will deactivate the output enable for the
+// DIO.
+#define IOC_IOCFG5_WU_CFG_W 2
+#define IOC_IOCFG5_WU_CFG_M 0x18000000
+#define IOC_IOCFG5_WU_CFG_S 27
+
+// Field: [26:24] IOMODE
+//
+// IO Mode
+// Not applicable for IO configured for AON periph. signals and AUX PORT_ID
+// 0x01-0x08
+// AUX has its own open_source/drain configuration.
+//
+// 0x2: Reserved. Undefined behavior.
+// 0x3: Reserved. Undefined behavior.
+// ENUMs:
+// OPENSRC_INV Open Source
+// Inverted input / output
+// OPENSRC Open Source
+// Normal input / output
+// OPENDR_INV Open Drain
+// Inverted input / output
+// OPENDR Open Drain,
+// Normal input / output
+// INV Inverted input / ouput
+// NORMAL Normal input / output
+#define IOC_IOCFG5_IOMODE_W 3
+#define IOC_IOCFG5_IOMODE_M 0x07000000
+#define IOC_IOCFG5_IOMODE_S 24
+#define IOC_IOCFG5_IOMODE_OPENSRC_INV 0x07000000
+#define IOC_IOCFG5_IOMODE_OPENSRC 0x06000000
+#define IOC_IOCFG5_IOMODE_OPENDR_INV 0x05000000
+#define IOC_IOCFG5_IOMODE_OPENDR 0x04000000
+#define IOC_IOCFG5_IOMODE_INV 0x01000000
+#define IOC_IOCFG5_IOMODE_NORMAL 0x00000000
+
+// Field: [23] IOEV_AON_PROG2_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG2 event
+// 1: Input edge detection asserts AON_PROG2 event
+#define IOC_IOCFG5_IOEV_AON_PROG2_EN 0x00800000
+#define IOC_IOCFG5_IOEV_AON_PROG2_EN_BITN 23
+#define IOC_IOCFG5_IOEV_AON_PROG2_EN_M 0x00800000
+#define IOC_IOCFG5_IOEV_AON_PROG2_EN_S 23
+
+// Field: [22] IOEV_AON_PROG1_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG1 event
+// 1: Input edge detection asserts AON_PROG1 event
+#define IOC_IOCFG5_IOEV_AON_PROG1_EN 0x00400000
+#define IOC_IOCFG5_IOEV_AON_PROG1_EN_BITN 22
+#define IOC_IOCFG5_IOEV_AON_PROG1_EN_M 0x00400000
+#define IOC_IOCFG5_IOEV_AON_PROG1_EN_S 22
+
+// Field: [21] IOEV_AON_PROG0_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG0 event
+// 1: Input edge detection asserts AON_PROG0 event
+#define IOC_IOCFG5_IOEV_AON_PROG0_EN 0x00200000
+#define IOC_IOCFG5_IOEV_AON_PROG0_EN_BITN 21
+#define IOC_IOCFG5_IOEV_AON_PROG0_EN_M 0x00200000
+#define IOC_IOCFG5_IOEV_AON_PROG0_EN_S 21
+
+// Field: [18] EDGE_IRQ_EN
+//
+// 0: No interrupt generation
+// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is
+// enabled)
+#define IOC_IOCFG5_EDGE_IRQ_EN 0x00040000
+#define IOC_IOCFG5_EDGE_IRQ_EN_BITN 18
+#define IOC_IOCFG5_EDGE_IRQ_EN_M 0x00040000
+#define IOC_IOCFG5_EDGE_IRQ_EN_S 18
+
+// Field: [17:16] EDGE_DET
+//
+// Enable generation of edge detection events on this IO
+// ENUMs:
+// BOTH Positive and negative edge detection
+// POS Positive edge detection
+// NEG Negative edge detection
+// NONE No edge detection
+#define IOC_IOCFG5_EDGE_DET_W 2
+#define IOC_IOCFG5_EDGE_DET_M 0x00030000
+#define IOC_IOCFG5_EDGE_DET_S 16
+#define IOC_IOCFG5_EDGE_DET_BOTH 0x00030000
+#define IOC_IOCFG5_EDGE_DET_POS 0x00020000
+#define IOC_IOCFG5_EDGE_DET_NEG 0x00010000
+#define IOC_IOCFG5_EDGE_DET_NONE 0x00000000
+
+// Field: [14:13] PULL_CTL
+//
+// Pull control
+// ENUMs:
+// DIS No pull
+// UP Pull up
+// DWN Pull down
+#define IOC_IOCFG5_PULL_CTL_W 2
+#define IOC_IOCFG5_PULL_CTL_M 0x00006000
+#define IOC_IOCFG5_PULL_CTL_S 13
+#define IOC_IOCFG5_PULL_CTL_DIS 0x00006000
+#define IOC_IOCFG5_PULL_CTL_UP 0x00004000
+#define IOC_IOCFG5_PULL_CTL_DWN 0x00002000
+
+// Field: [12] SLEW_RED
+//
+// 0: Normal slew rate
+// 1: Enables reduced slew rate in output driver.
+#define IOC_IOCFG5_SLEW_RED 0x00001000
+#define IOC_IOCFG5_SLEW_RED_BITN 12
+#define IOC_IOCFG5_SLEW_RED_M 0x00001000
+#define IOC_IOCFG5_SLEW_RED_S 12
+
+// Field: [11:10] IOCURR
+//
+// Selects IO current mode of this IO.
+// ENUMs:
+// 4_8MA Extended-Current (EC) mode: Min 8 mA for double
+// drive strength IOs (min 4 mA for normal IOs)
+// when IOSTR is set to AUTO
+// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set
+// to AUTO
+// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set
+// to AUTO
+#define IOC_IOCFG5_IOCURR_W 2
+#define IOC_IOCFG5_IOCURR_M 0x00000C00
+#define IOC_IOCFG5_IOCURR_S 10
+#define IOC_IOCFG5_IOCURR_4_8MA 0x00000800
+#define IOC_IOCFG5_IOCURR_4MA 0x00000400
+#define IOC_IOCFG5_IOCURR_2MA 0x00000000
+
+// Field: [9:8] IOSTR
+//
+// Select source for drive strength control of this IO.
+// This setting controls the drive strength of the Low-Current (LC) mode.
+// Higher drive strength can be selected in IOCURR
+// ENUMs:
+// MAX Maximum drive strength, controlled by
+// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default
+// values)
+// MED Medium drive strength, controlled by
+// AON_IOC:IOSTRMED (min 2 mA @2.5V with default
+// values)
+// MIN Minimum drive strength, controlled by
+// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default
+// values)
+// AUTO Automatic drive strength, controlled by AON BATMON
+// based on battery voltage. (min 2 mA @VDDS)
+#define IOC_IOCFG5_IOSTR_W 2
+#define IOC_IOCFG5_IOSTR_M 0x00000300
+#define IOC_IOCFG5_IOSTR_S 8
+#define IOC_IOCFG5_IOSTR_MAX 0x00000300
+#define IOC_IOCFG5_IOSTR_MED 0x00000200
+#define IOC_IOCFG5_IOSTR_MIN 0x00000100
+#define IOC_IOCFG5_IOSTR_AUTO 0x00000000
+
+// Field: [7] IOEV_RTC_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert RTC event
+// 1: Input edge detection asserts RTC event
+#define IOC_IOCFG5_IOEV_RTC_EN 0x00000080
+#define IOC_IOCFG5_IOEV_RTC_EN_BITN 7
+#define IOC_IOCFG5_IOEV_RTC_EN_M 0x00000080
+#define IOC_IOCFG5_IOEV_RTC_EN_S 7
+
+// Field: [6] IOEV_MCU_WU_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert MCU_WU event
+// 1: Input edge detection asserts MCU_WU event
+#define IOC_IOCFG5_IOEV_MCU_WU_EN 0x00000040
+#define IOC_IOCFG5_IOEV_MCU_WU_EN_BITN 6
+#define IOC_IOCFG5_IOEV_MCU_WU_EN_M 0x00000040
+#define IOC_IOCFG5_IOEV_MCU_WU_EN_S 6
+
+// Field: [5:0] PORT_ID
+//
+// Selects usage for DIO5
+// ENUMs:
+// RFC_SMI_CL_IN RF Core SMI Command Link In
+// RFC_SMI_CL_OUT RF Core SMI Command Link Out
+// RFC_SMI_DL_IN RF Core SMI Data Link In
+// RFC_SMI_DL_OUT RF Core SMI Data Link Out
+// RFC_GPI1 RF Core Data In 1
+// RFC_GPI0 RF Core Data In 0
+// RFC_GPO3 RF Core Data Out 3
+// RFC_GPO2 RF Core Data Out 2
+// RFC_GPO1 RF Core Data Out 1
+// RFC_GPO0 RF Core Data Out 0
+// RFC_TRC RF Core Trace
+// I2S_MCLK I2S MCLK
+// I2S_BCLK I2S BCLK
+// I2S_WCLK I2S WCLK
+// I2S_AD1 I2S Data 1
+// I2S_AD0 I2S Data 0
+// SSI1_CLK SSI1 CLK
+// SSI1_FSS SSI1 FSS
+// SSI1_TX SSI1 TX
+// SSI1_RX SSI1 RX
+// CPU_SWV CPU SWV
+// PORT_EVENT7 PORT EVENT 7
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT6 PORT EVENT 6
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT5 PORT EVENT 5
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT4 PORT EVENT 4
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT3 PORT EVENT 3
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT2 PORT EVENT 2
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT1 PORT EVENT 1
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT0 PORT EVENT 0
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// UART1_RTS UART1 RTS
+// UART1_CTS UART1 CTS
+// UART1_TX UART1 TX
+// UART1_RX UART1 RX
+// UART0_RTS UART0 RTS
+// UART0_CTS UART0 CTS
+// UART0_TX UART0 TX
+// UART0_RX UART0 RX
+// I2C_MSSCL I2C Clock
+// I2C_MSSDA I2C Data
+// SSI0_CLK SSI0 CLK
+// SSI0_FSS SSI0 FSS
+// SSI0_TX SSI0 TX
+// SSI0_RX SSI0 RX
+// AUX_IO AUX IO
+// AON_CLK32K AON 32 KHz clock (SCLK_LF)
+// GPIO General Purpose IO
+#define IOC_IOCFG5_PORT_ID_W 6
+#define IOC_IOCFG5_PORT_ID_M 0x0000003F
+#define IOC_IOCFG5_PORT_ID_S 0
+#define IOC_IOCFG5_PORT_ID_RFC_SMI_CL_IN 0x00000038
+#define IOC_IOCFG5_PORT_ID_RFC_SMI_CL_OUT 0x00000037
+#define IOC_IOCFG5_PORT_ID_RFC_SMI_DL_IN 0x00000036
+#define IOC_IOCFG5_PORT_ID_RFC_SMI_DL_OUT 0x00000035
+#define IOC_IOCFG5_PORT_ID_RFC_GPI1 0x00000034
+#define IOC_IOCFG5_PORT_ID_RFC_GPI0 0x00000033
+#define IOC_IOCFG5_PORT_ID_RFC_GPO3 0x00000032
+#define IOC_IOCFG5_PORT_ID_RFC_GPO2 0x00000031
+#define IOC_IOCFG5_PORT_ID_RFC_GPO1 0x00000030
+#define IOC_IOCFG5_PORT_ID_RFC_GPO0 0x0000002F
+#define IOC_IOCFG5_PORT_ID_RFC_TRC 0x0000002E
+#define IOC_IOCFG5_PORT_ID_I2S_MCLK 0x00000029
+#define IOC_IOCFG5_PORT_ID_I2S_BCLK 0x00000028
+#define IOC_IOCFG5_PORT_ID_I2S_WCLK 0x00000027
+#define IOC_IOCFG5_PORT_ID_I2S_AD1 0x00000026
+#define IOC_IOCFG5_PORT_ID_I2S_AD0 0x00000025
+#define IOC_IOCFG5_PORT_ID_SSI1_CLK 0x00000024
+#define IOC_IOCFG5_PORT_ID_SSI1_FSS 0x00000023
+#define IOC_IOCFG5_PORT_ID_SSI1_TX 0x00000022
+#define IOC_IOCFG5_PORT_ID_SSI1_RX 0x00000021
+#define IOC_IOCFG5_PORT_ID_CPU_SWV 0x00000020
+#define IOC_IOCFG5_PORT_ID_PORT_EVENT7 0x0000001E
+#define IOC_IOCFG5_PORT_ID_PORT_EVENT6 0x0000001D
+#define IOC_IOCFG5_PORT_ID_PORT_EVENT5 0x0000001C
+#define IOC_IOCFG5_PORT_ID_PORT_EVENT4 0x0000001B
+#define IOC_IOCFG5_PORT_ID_PORT_EVENT3 0x0000001A
+#define IOC_IOCFG5_PORT_ID_PORT_EVENT2 0x00000019
+#define IOC_IOCFG5_PORT_ID_PORT_EVENT1 0x00000018
+#define IOC_IOCFG5_PORT_ID_PORT_EVENT0 0x00000017
+#define IOC_IOCFG5_PORT_ID_UART1_RTS 0x00000016
+#define IOC_IOCFG5_PORT_ID_UART1_CTS 0x00000015
+#define IOC_IOCFG5_PORT_ID_UART1_TX 0x00000014
+#define IOC_IOCFG5_PORT_ID_UART1_RX 0x00000013
+#define IOC_IOCFG5_PORT_ID_UART0_RTS 0x00000012
+#define IOC_IOCFG5_PORT_ID_UART0_CTS 0x00000011
+#define IOC_IOCFG5_PORT_ID_UART0_TX 0x00000010
+#define IOC_IOCFG5_PORT_ID_UART0_RX 0x0000000F
+#define IOC_IOCFG5_PORT_ID_I2C_MSSCL 0x0000000E
+#define IOC_IOCFG5_PORT_ID_I2C_MSSDA 0x0000000D
+#define IOC_IOCFG5_PORT_ID_SSI0_CLK 0x0000000C
+#define IOC_IOCFG5_PORT_ID_SSI0_FSS 0x0000000B
+#define IOC_IOCFG5_PORT_ID_SSI0_TX 0x0000000A
+#define IOC_IOCFG5_PORT_ID_SSI0_RX 0x00000009
+#define IOC_IOCFG5_PORT_ID_AUX_IO 0x00000008
+#define IOC_IOCFG5_PORT_ID_AON_CLK32K 0x00000007
+#define IOC_IOCFG5_PORT_ID_GPIO 0x00000000
+
+//*****************************************************************************
+//
+// Register: IOC_O_IOCFG6
+//
+//*****************************************************************************
+// Field: [30] HYST_EN
+//
+// 0: Input hysteresis disable
+// 1: Input hysteresis enable
+#define IOC_IOCFG6_HYST_EN 0x40000000
+#define IOC_IOCFG6_HYST_EN_BITN 30
+#define IOC_IOCFG6_HYST_EN_M 0x40000000
+#define IOC_IOCFG6_HYST_EN_S 30
+
+// Field: [29] IE
+//
+// 0: Input disabled
+// 1: Input enabled
+//
+// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be
+// ignored.
+#define IOC_IOCFG6_IE 0x20000000
+#define IOC_IOCFG6_IE_BITN 29
+#define IOC_IOCFG6_IE_M 0x20000000
+#define IOC_IOCFG6_IE_S 29
+
+// Field: [28:27] WU_CFG
+//
+// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or
+// >0x08:
+//
+// 00: No wake-up
+// 01: No wake-up
+// 10: Wakes up from shutdown if this pad is going low.
+// 11: Wakes up from shutdown if this pad is going high.
+//
+// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08,
+// this register only sets wakeup enable or not.
+//
+// 00, 01: Wakeup disabled
+// 10, 11: Wakeup enabled
+//
+// Polarity is controlled from AON registers.
+//
+// Note:When the MSB is set, the IOC will deactivate the output enable for the
+// DIO.
+#define IOC_IOCFG6_WU_CFG_W 2
+#define IOC_IOCFG6_WU_CFG_M 0x18000000
+#define IOC_IOCFG6_WU_CFG_S 27
+
+// Field: [26:24] IOMODE
+//
+// IO Mode
+// Not applicable for IO configured for AON periph. signals and AUX PORT_ID
+// 0x01-0x08
+// AUX has its own open_source/drain configuration.
+//
+// 0x2: Reserved. Undefined behavior.
+// 0x3: Reserved. Undefined behavior.
+// ENUMs:
+// OPENSRC_INV Open Source
+// Inverted input / output
+// OPENSRC Open Source
+// Normal input / output
+// OPENDR_INV Open Drain
+// Inverted input / output
+// OPENDR Open Drain,
+// Normal input / output
+// INV Inverted input / ouput
+// NORMAL Normal input / output
+#define IOC_IOCFG6_IOMODE_W 3
+#define IOC_IOCFG6_IOMODE_M 0x07000000
+#define IOC_IOCFG6_IOMODE_S 24
+#define IOC_IOCFG6_IOMODE_OPENSRC_INV 0x07000000
+#define IOC_IOCFG6_IOMODE_OPENSRC 0x06000000
+#define IOC_IOCFG6_IOMODE_OPENDR_INV 0x05000000
+#define IOC_IOCFG6_IOMODE_OPENDR 0x04000000
+#define IOC_IOCFG6_IOMODE_INV 0x01000000
+#define IOC_IOCFG6_IOMODE_NORMAL 0x00000000
+
+// Field: [23] IOEV_AON_PROG2_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG2 event
+// 1: Input edge detection asserts AON_PROG2 event
+#define IOC_IOCFG6_IOEV_AON_PROG2_EN 0x00800000
+#define IOC_IOCFG6_IOEV_AON_PROG2_EN_BITN 23
+#define IOC_IOCFG6_IOEV_AON_PROG2_EN_M 0x00800000
+#define IOC_IOCFG6_IOEV_AON_PROG2_EN_S 23
+
+// Field: [22] IOEV_AON_PROG1_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG1 event
+// 1: Input edge detection asserts AON_PROG1 event
+#define IOC_IOCFG6_IOEV_AON_PROG1_EN 0x00400000
+#define IOC_IOCFG6_IOEV_AON_PROG1_EN_BITN 22
+#define IOC_IOCFG6_IOEV_AON_PROG1_EN_M 0x00400000
+#define IOC_IOCFG6_IOEV_AON_PROG1_EN_S 22
+
+// Field: [21] IOEV_AON_PROG0_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG0 event
+// 1: Input edge detection asserts AON_PROG0 event
+#define IOC_IOCFG6_IOEV_AON_PROG0_EN 0x00200000
+#define IOC_IOCFG6_IOEV_AON_PROG0_EN_BITN 21
+#define IOC_IOCFG6_IOEV_AON_PROG0_EN_M 0x00200000
+#define IOC_IOCFG6_IOEV_AON_PROG0_EN_S 21
+
+// Field: [18] EDGE_IRQ_EN
+//
+// 0: No interrupt generation
+// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is
+// enabled)
+#define IOC_IOCFG6_EDGE_IRQ_EN 0x00040000
+#define IOC_IOCFG6_EDGE_IRQ_EN_BITN 18
+#define IOC_IOCFG6_EDGE_IRQ_EN_M 0x00040000
+#define IOC_IOCFG6_EDGE_IRQ_EN_S 18
+
+// Field: [17:16] EDGE_DET
+//
+// Enable generation of edge detection events on this IO
+// ENUMs:
+// BOTH Positive and negative edge detection
+// POS Positive edge detection
+// NEG Negative edge detection
+// NONE No edge detection
+#define IOC_IOCFG6_EDGE_DET_W 2
+#define IOC_IOCFG6_EDGE_DET_M 0x00030000
+#define IOC_IOCFG6_EDGE_DET_S 16
+#define IOC_IOCFG6_EDGE_DET_BOTH 0x00030000
+#define IOC_IOCFG6_EDGE_DET_POS 0x00020000
+#define IOC_IOCFG6_EDGE_DET_NEG 0x00010000
+#define IOC_IOCFG6_EDGE_DET_NONE 0x00000000
+
+// Field: [14:13] PULL_CTL
+//
+// Pull control
+// ENUMs:
+// DIS No pull
+// UP Pull up
+// DWN Pull down
+#define IOC_IOCFG6_PULL_CTL_W 2
+#define IOC_IOCFG6_PULL_CTL_M 0x00006000
+#define IOC_IOCFG6_PULL_CTL_S 13
+#define IOC_IOCFG6_PULL_CTL_DIS 0x00006000
+#define IOC_IOCFG6_PULL_CTL_UP 0x00004000
+#define IOC_IOCFG6_PULL_CTL_DWN 0x00002000
+
+// Field: [12] SLEW_RED
+//
+// 0: Normal slew rate
+// 1: Enables reduced slew rate in output driver.
+#define IOC_IOCFG6_SLEW_RED 0x00001000
+#define IOC_IOCFG6_SLEW_RED_BITN 12
+#define IOC_IOCFG6_SLEW_RED_M 0x00001000
+#define IOC_IOCFG6_SLEW_RED_S 12
+
+// Field: [11:10] IOCURR
+//
+// Selects IO current mode of this IO.
+// ENUMs:
+// 4_8MA Extended-Current (EC) mode: Min 8 mA for double
+// drive strength IOs (min 4 mA for normal IOs)
+// when IOSTR is set to AUTO
+// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set
+// to AUTO
+// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set
+// to AUTO
+#define IOC_IOCFG6_IOCURR_W 2
+#define IOC_IOCFG6_IOCURR_M 0x00000C00
+#define IOC_IOCFG6_IOCURR_S 10
+#define IOC_IOCFG6_IOCURR_4_8MA 0x00000800
+#define IOC_IOCFG6_IOCURR_4MA 0x00000400
+#define IOC_IOCFG6_IOCURR_2MA 0x00000000
+
+// Field: [9:8] IOSTR
+//
+// Select source for drive strength control of this IO.
+// This setting controls the drive strength of the Low-Current (LC) mode.
+// Higher drive strength can be selected in IOCURR
+// ENUMs:
+// MAX Maximum drive strength, controlled by
+// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default
+// values)
+// MED Medium drive strength, controlled by
+// AON_IOC:IOSTRMED (min 2 mA @2.5V with default
+// values)
+// MIN Minimum drive strength, controlled by
+// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default
+// values)
+// AUTO Automatic drive strength, controlled by AON BATMON
+// based on battery voltage. (min 2 mA @VDDS)
+#define IOC_IOCFG6_IOSTR_W 2
+#define IOC_IOCFG6_IOSTR_M 0x00000300
+#define IOC_IOCFG6_IOSTR_S 8
+#define IOC_IOCFG6_IOSTR_MAX 0x00000300
+#define IOC_IOCFG6_IOSTR_MED 0x00000200
+#define IOC_IOCFG6_IOSTR_MIN 0x00000100
+#define IOC_IOCFG6_IOSTR_AUTO 0x00000000
+
+// Field: [7] IOEV_RTC_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert RTC event
+// 1: Input edge detection asserts RTC event
+#define IOC_IOCFG6_IOEV_RTC_EN 0x00000080
+#define IOC_IOCFG6_IOEV_RTC_EN_BITN 7
+#define IOC_IOCFG6_IOEV_RTC_EN_M 0x00000080
+#define IOC_IOCFG6_IOEV_RTC_EN_S 7
+
+// Field: [6] IOEV_MCU_WU_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert MCU_WU event
+// 1: Input edge detection asserts MCU_WU event
+#define IOC_IOCFG6_IOEV_MCU_WU_EN 0x00000040
+#define IOC_IOCFG6_IOEV_MCU_WU_EN_BITN 6
+#define IOC_IOCFG6_IOEV_MCU_WU_EN_M 0x00000040
+#define IOC_IOCFG6_IOEV_MCU_WU_EN_S 6
+
+// Field: [5:0] PORT_ID
+//
+// Selects usage for DIO6
+// ENUMs:
+// RFC_SMI_CL_IN RF Core SMI Command Link In
+// RFC_SMI_CL_OUT RF Core SMI Command Link Out
+// RFC_SMI_DL_IN RF Core SMI Data Link In
+// RFC_SMI_DL_OUT RF Core SMI Data Link Out
+// RFC_GPI1 RF Core Data In 1
+// RFC_GPI0 RF Core Data In 0
+// RFC_GPO3 RF Core Data Out 3
+// RFC_GPO2 RF Core Data Out 2
+// RFC_GPO1 RF Core Data Out 1
+// RFC_GPO0 RF Core Data Out 0
+// RFC_TRC RF Core Trace
+// I2S_MCLK I2S MCLK
+// I2S_BCLK I2S BCLK
+// I2S_WCLK I2S WCLK
+// I2S_AD1 I2S Data 1
+// I2S_AD0 I2S Data 0
+// SSI1_CLK SSI1 CLK
+// SSI1_FSS SSI1 FSS
+// SSI1_TX SSI1 TX
+// SSI1_RX SSI1 RX
+// CPU_SWV CPU SWV
+// PORT_EVENT7 PORT EVENT 7
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT6 PORT EVENT 6
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT5 PORT EVENT 5
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT4 PORT EVENT 4
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT3 PORT EVENT 3
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT2 PORT EVENT 2
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT1 PORT EVENT 1
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT0 PORT EVENT 0
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// UART1_RTS UART1 RTS
+// UART1_CTS UART1 CTS
+// UART1_TX UART1 TX
+// UART1_RX UART1 RX
+// UART0_RTS UART0 RTS
+// UART0_CTS UART0 CTS
+// UART0_TX UART0 TX
+// UART0_RX UART0 RX
+// I2C_MSSCL I2C Clock
+// I2C_MSSDA I2C Data
+// SSI0_CLK SSI0 CLK
+// SSI0_FSS SSI0 FSS
+// SSI0_TX SSI0 TX
+// SSI0_RX SSI0 RX
+// AUX_IO AUX IO
+// AON_CLK32K AON 32 KHz clock (SCLK_LF)
+// GPIO General Purpose IO
+#define IOC_IOCFG6_PORT_ID_W 6
+#define IOC_IOCFG6_PORT_ID_M 0x0000003F
+#define IOC_IOCFG6_PORT_ID_S 0
+#define IOC_IOCFG6_PORT_ID_RFC_SMI_CL_IN 0x00000038
+#define IOC_IOCFG6_PORT_ID_RFC_SMI_CL_OUT 0x00000037
+#define IOC_IOCFG6_PORT_ID_RFC_SMI_DL_IN 0x00000036
+#define IOC_IOCFG6_PORT_ID_RFC_SMI_DL_OUT 0x00000035
+#define IOC_IOCFG6_PORT_ID_RFC_GPI1 0x00000034
+#define IOC_IOCFG6_PORT_ID_RFC_GPI0 0x00000033
+#define IOC_IOCFG6_PORT_ID_RFC_GPO3 0x00000032
+#define IOC_IOCFG6_PORT_ID_RFC_GPO2 0x00000031
+#define IOC_IOCFG6_PORT_ID_RFC_GPO1 0x00000030
+#define IOC_IOCFG6_PORT_ID_RFC_GPO0 0x0000002F
+#define IOC_IOCFG6_PORT_ID_RFC_TRC 0x0000002E
+#define IOC_IOCFG6_PORT_ID_I2S_MCLK 0x00000029
+#define IOC_IOCFG6_PORT_ID_I2S_BCLK 0x00000028
+#define IOC_IOCFG6_PORT_ID_I2S_WCLK 0x00000027
+#define IOC_IOCFG6_PORT_ID_I2S_AD1 0x00000026
+#define IOC_IOCFG6_PORT_ID_I2S_AD0 0x00000025
+#define IOC_IOCFG6_PORT_ID_SSI1_CLK 0x00000024
+#define IOC_IOCFG6_PORT_ID_SSI1_FSS 0x00000023
+#define IOC_IOCFG6_PORT_ID_SSI1_TX 0x00000022
+#define IOC_IOCFG6_PORT_ID_SSI1_RX 0x00000021
+#define IOC_IOCFG6_PORT_ID_CPU_SWV 0x00000020
+#define IOC_IOCFG6_PORT_ID_PORT_EVENT7 0x0000001E
+#define IOC_IOCFG6_PORT_ID_PORT_EVENT6 0x0000001D
+#define IOC_IOCFG6_PORT_ID_PORT_EVENT5 0x0000001C
+#define IOC_IOCFG6_PORT_ID_PORT_EVENT4 0x0000001B
+#define IOC_IOCFG6_PORT_ID_PORT_EVENT3 0x0000001A
+#define IOC_IOCFG6_PORT_ID_PORT_EVENT2 0x00000019
+#define IOC_IOCFG6_PORT_ID_PORT_EVENT1 0x00000018
+#define IOC_IOCFG6_PORT_ID_PORT_EVENT0 0x00000017
+#define IOC_IOCFG6_PORT_ID_UART1_RTS 0x00000016
+#define IOC_IOCFG6_PORT_ID_UART1_CTS 0x00000015
+#define IOC_IOCFG6_PORT_ID_UART1_TX 0x00000014
+#define IOC_IOCFG6_PORT_ID_UART1_RX 0x00000013
+#define IOC_IOCFG6_PORT_ID_UART0_RTS 0x00000012
+#define IOC_IOCFG6_PORT_ID_UART0_CTS 0x00000011
+#define IOC_IOCFG6_PORT_ID_UART0_TX 0x00000010
+#define IOC_IOCFG6_PORT_ID_UART0_RX 0x0000000F
+#define IOC_IOCFG6_PORT_ID_I2C_MSSCL 0x0000000E
+#define IOC_IOCFG6_PORT_ID_I2C_MSSDA 0x0000000D
+#define IOC_IOCFG6_PORT_ID_SSI0_CLK 0x0000000C
+#define IOC_IOCFG6_PORT_ID_SSI0_FSS 0x0000000B
+#define IOC_IOCFG6_PORT_ID_SSI0_TX 0x0000000A
+#define IOC_IOCFG6_PORT_ID_SSI0_RX 0x00000009
+#define IOC_IOCFG6_PORT_ID_AUX_IO 0x00000008
+#define IOC_IOCFG6_PORT_ID_AON_CLK32K 0x00000007
+#define IOC_IOCFG6_PORT_ID_GPIO 0x00000000
+
+//*****************************************************************************
+//
+// Register: IOC_O_IOCFG7
+//
+//*****************************************************************************
+// Field: [30] HYST_EN
+//
+// 0: Input hysteresis disable
+// 1: Input hysteresis enable
+#define IOC_IOCFG7_HYST_EN 0x40000000
+#define IOC_IOCFG7_HYST_EN_BITN 30
+#define IOC_IOCFG7_HYST_EN_M 0x40000000
+#define IOC_IOCFG7_HYST_EN_S 30
+
+// Field: [29] IE
+//
+// 0: Input disabled
+// 1: Input enabled
+//
+// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be
+// ignored.
+#define IOC_IOCFG7_IE 0x20000000
+#define IOC_IOCFG7_IE_BITN 29
+#define IOC_IOCFG7_IE_M 0x20000000
+#define IOC_IOCFG7_IE_S 29
+
+// Field: [28:27] WU_CFG
+//
+// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or
+// >0x08:
+//
+// 00: No wake-up
+// 01: No wake-up
+// 10: Wakes up from shutdown if this pad is going low.
+// 11: Wakes up from shutdown if this pad is going high.
+//
+// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08,
+// this register only sets wakeup enable or not.
+//
+// 00, 01: Wakeup disabled
+// 10, 11: Wakeup enabled
+//
+// Polarity is controlled from AON registers.
+//
+// Note:When the MSB is set, the IOC will deactivate the output enable for the
+// DIO.
+#define IOC_IOCFG7_WU_CFG_W 2
+#define IOC_IOCFG7_WU_CFG_M 0x18000000
+#define IOC_IOCFG7_WU_CFG_S 27
+
+// Field: [26:24] IOMODE
+//
+// IO Mode
+// Not applicable for IO configured for AON periph. signals and AUX PORT_ID
+// 0x01-0x08
+// AUX has its own open_source/drain configuration.
+//
+// 0x2: Reserved. Undefined behavior.
+// 0x3: Reserved. Undefined behavior.
+// ENUMs:
+// OPENSRC_INV Open Source
+// Inverted input / output
+// OPENSRC Open Source
+// Normal input / output
+// OPENDR_INV Open Drain
+// Inverted input / output
+// OPENDR Open Drain,
+// Normal input / output
+// INV Inverted input / ouput
+// NORMAL Normal input / output
+#define IOC_IOCFG7_IOMODE_W 3
+#define IOC_IOCFG7_IOMODE_M 0x07000000
+#define IOC_IOCFG7_IOMODE_S 24
+#define IOC_IOCFG7_IOMODE_OPENSRC_INV 0x07000000
+#define IOC_IOCFG7_IOMODE_OPENSRC 0x06000000
+#define IOC_IOCFG7_IOMODE_OPENDR_INV 0x05000000
+#define IOC_IOCFG7_IOMODE_OPENDR 0x04000000
+#define IOC_IOCFG7_IOMODE_INV 0x01000000
+#define IOC_IOCFG7_IOMODE_NORMAL 0x00000000
+
+// Field: [23] IOEV_AON_PROG2_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG2 event
+// 1: Input edge detection asserts AON_PROG2 event
+#define IOC_IOCFG7_IOEV_AON_PROG2_EN 0x00800000
+#define IOC_IOCFG7_IOEV_AON_PROG2_EN_BITN 23
+#define IOC_IOCFG7_IOEV_AON_PROG2_EN_M 0x00800000
+#define IOC_IOCFG7_IOEV_AON_PROG2_EN_S 23
+
+// Field: [22] IOEV_AON_PROG1_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG1 event
+// 1: Input edge detection asserts AON_PROG1 event
+#define IOC_IOCFG7_IOEV_AON_PROG1_EN 0x00400000
+#define IOC_IOCFG7_IOEV_AON_PROG1_EN_BITN 22
+#define IOC_IOCFG7_IOEV_AON_PROG1_EN_M 0x00400000
+#define IOC_IOCFG7_IOEV_AON_PROG1_EN_S 22
+
+// Field: [21] IOEV_AON_PROG0_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG0 event
+// 1: Input edge detection asserts AON_PROG0 event
+#define IOC_IOCFG7_IOEV_AON_PROG0_EN 0x00200000
+#define IOC_IOCFG7_IOEV_AON_PROG0_EN_BITN 21
+#define IOC_IOCFG7_IOEV_AON_PROG0_EN_M 0x00200000
+#define IOC_IOCFG7_IOEV_AON_PROG0_EN_S 21
+
+// Field: [18] EDGE_IRQ_EN
+//
+// 0: No interrupt generation
+// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is
+// enabled)
+#define IOC_IOCFG7_EDGE_IRQ_EN 0x00040000
+#define IOC_IOCFG7_EDGE_IRQ_EN_BITN 18
+#define IOC_IOCFG7_EDGE_IRQ_EN_M 0x00040000
+#define IOC_IOCFG7_EDGE_IRQ_EN_S 18
+
+// Field: [17:16] EDGE_DET
+//
+// Enable generation of edge detection events on this IO
+// ENUMs:
+// BOTH Positive and negative edge detection
+// POS Positive edge detection
+// NEG Negative edge detection
+// NONE No edge detection
+#define IOC_IOCFG7_EDGE_DET_W 2
+#define IOC_IOCFG7_EDGE_DET_M 0x00030000
+#define IOC_IOCFG7_EDGE_DET_S 16
+#define IOC_IOCFG7_EDGE_DET_BOTH 0x00030000
+#define IOC_IOCFG7_EDGE_DET_POS 0x00020000
+#define IOC_IOCFG7_EDGE_DET_NEG 0x00010000
+#define IOC_IOCFG7_EDGE_DET_NONE 0x00000000
+
+// Field: [14:13] PULL_CTL
+//
+// Pull control
+// ENUMs:
+// DIS No pull
+// UP Pull up
+// DWN Pull down
+#define IOC_IOCFG7_PULL_CTL_W 2
+#define IOC_IOCFG7_PULL_CTL_M 0x00006000
+#define IOC_IOCFG7_PULL_CTL_S 13
+#define IOC_IOCFG7_PULL_CTL_DIS 0x00006000
+#define IOC_IOCFG7_PULL_CTL_UP 0x00004000
+#define IOC_IOCFG7_PULL_CTL_DWN 0x00002000
+
+// Field: [12] SLEW_RED
+//
+// 0: Normal slew rate
+// 1: Enables reduced slew rate in output driver.
+#define IOC_IOCFG7_SLEW_RED 0x00001000
+#define IOC_IOCFG7_SLEW_RED_BITN 12
+#define IOC_IOCFG7_SLEW_RED_M 0x00001000
+#define IOC_IOCFG7_SLEW_RED_S 12
+
+// Field: [11:10] IOCURR
+//
+// Selects IO current mode of this IO.
+// ENUMs:
+// 4_8MA Extended-Current (EC) mode: Min 8 mA for double
+// drive strength IOs (min 4 mA for normal IOs)
+// when IOSTR is set to AUTO
+// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set
+// to AUTO
+// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set
+// to AUTO
+#define IOC_IOCFG7_IOCURR_W 2
+#define IOC_IOCFG7_IOCURR_M 0x00000C00
+#define IOC_IOCFG7_IOCURR_S 10
+#define IOC_IOCFG7_IOCURR_4_8MA 0x00000800
+#define IOC_IOCFG7_IOCURR_4MA 0x00000400
+#define IOC_IOCFG7_IOCURR_2MA 0x00000000
+
+// Field: [9:8] IOSTR
+//
+// Select source for drive strength control of this IO.
+// This setting controls the drive strength of the Low-Current (LC) mode.
+// Higher drive strength can be selected in IOCURR
+// ENUMs:
+// MAX Maximum drive strength, controlled by
+// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default
+// values)
+// MED Medium drive strength, controlled by
+// AON_IOC:IOSTRMED (min 2 mA @2.5V with default
+// values)
+// MIN Minimum drive strength, controlled by
+// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default
+// values)
+// AUTO Automatic drive strength, controlled by AON BATMON
+// based on battery voltage. (min 2 mA @VDDS)
+#define IOC_IOCFG7_IOSTR_W 2
+#define IOC_IOCFG7_IOSTR_M 0x00000300
+#define IOC_IOCFG7_IOSTR_S 8
+#define IOC_IOCFG7_IOSTR_MAX 0x00000300
+#define IOC_IOCFG7_IOSTR_MED 0x00000200
+#define IOC_IOCFG7_IOSTR_MIN 0x00000100
+#define IOC_IOCFG7_IOSTR_AUTO 0x00000000
+
+// Field: [7] IOEV_RTC_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert RTC event
+// 1: Input edge detection asserts RTC event
+#define IOC_IOCFG7_IOEV_RTC_EN 0x00000080
+#define IOC_IOCFG7_IOEV_RTC_EN_BITN 7
+#define IOC_IOCFG7_IOEV_RTC_EN_M 0x00000080
+#define IOC_IOCFG7_IOEV_RTC_EN_S 7
+
+// Field: [6] IOEV_MCU_WU_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert MCU_WU event
+// 1: Input edge detection asserts MCU_WU event
+#define IOC_IOCFG7_IOEV_MCU_WU_EN 0x00000040
+#define IOC_IOCFG7_IOEV_MCU_WU_EN_BITN 6
+#define IOC_IOCFG7_IOEV_MCU_WU_EN_M 0x00000040
+#define IOC_IOCFG7_IOEV_MCU_WU_EN_S 6
+
+// Field: [5:0] PORT_ID
+//
+// Selects usage for DIO7
+// ENUMs:
+// RFC_SMI_CL_IN RF Core SMI Command Link In
+// RFC_SMI_CL_OUT RF Core SMI Command Link Out
+// RFC_SMI_DL_IN RF Core SMI Data Link In
+// RFC_SMI_DL_OUT RF Core SMI Data Link Out
+// RFC_GPI1 RF Core Data In 1
+// RFC_GPI0 RF Core Data In 0
+// RFC_GPO3 RF Core Data Out 3
+// RFC_GPO2 RF Core Data Out 2
+// RFC_GPO1 RF Core Data Out 1
+// RFC_GPO0 RF Core Data Out 0
+// RFC_TRC RF Core Trace
+// I2S_MCLK I2S MCLK
+// I2S_BCLK I2S BCLK
+// I2S_WCLK I2S WCLK
+// I2S_AD1 I2S Data 1
+// I2S_AD0 I2S Data 0
+// SSI1_CLK SSI1 CLK
+// SSI1_FSS SSI1 FSS
+// SSI1_TX SSI1 TX
+// SSI1_RX SSI1 RX
+// CPU_SWV CPU SWV
+// PORT_EVENT7 PORT EVENT 7
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT6 PORT EVENT 6
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT5 PORT EVENT 5
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT4 PORT EVENT 4
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT3 PORT EVENT 3
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT2 PORT EVENT 2
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT1 PORT EVENT 1
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT0 PORT EVENT 0
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// UART1_RTS UART1 RTS
+// UART1_CTS UART1 CTS
+// UART1_TX UART1 TX
+// UART1_RX UART1 RX
+// UART0_RTS UART0 RTS
+// UART0_CTS UART0 CTS
+// UART0_TX UART0 TX
+// UART0_RX UART0 RX
+// I2C_MSSCL I2C Clock
+// I2C_MSSDA I2C Data
+// SSI0_CLK SSI0 CLK
+// SSI0_FSS SSI0 FSS
+// SSI0_TX SSI0 TX
+// SSI0_RX SSI0 RX
+// AUX_IO AUX IO
+// AON_CLK32K AON 32 KHz clock (SCLK_LF)
+// GPIO General Purpose IO
+#define IOC_IOCFG7_PORT_ID_W 6
+#define IOC_IOCFG7_PORT_ID_M 0x0000003F
+#define IOC_IOCFG7_PORT_ID_S 0
+#define IOC_IOCFG7_PORT_ID_RFC_SMI_CL_IN 0x00000038
+#define IOC_IOCFG7_PORT_ID_RFC_SMI_CL_OUT 0x00000037
+#define IOC_IOCFG7_PORT_ID_RFC_SMI_DL_IN 0x00000036
+#define IOC_IOCFG7_PORT_ID_RFC_SMI_DL_OUT 0x00000035
+#define IOC_IOCFG7_PORT_ID_RFC_GPI1 0x00000034
+#define IOC_IOCFG7_PORT_ID_RFC_GPI0 0x00000033
+#define IOC_IOCFG7_PORT_ID_RFC_GPO3 0x00000032
+#define IOC_IOCFG7_PORT_ID_RFC_GPO2 0x00000031
+#define IOC_IOCFG7_PORT_ID_RFC_GPO1 0x00000030
+#define IOC_IOCFG7_PORT_ID_RFC_GPO0 0x0000002F
+#define IOC_IOCFG7_PORT_ID_RFC_TRC 0x0000002E
+#define IOC_IOCFG7_PORT_ID_I2S_MCLK 0x00000029
+#define IOC_IOCFG7_PORT_ID_I2S_BCLK 0x00000028
+#define IOC_IOCFG7_PORT_ID_I2S_WCLK 0x00000027
+#define IOC_IOCFG7_PORT_ID_I2S_AD1 0x00000026
+#define IOC_IOCFG7_PORT_ID_I2S_AD0 0x00000025
+#define IOC_IOCFG7_PORT_ID_SSI1_CLK 0x00000024
+#define IOC_IOCFG7_PORT_ID_SSI1_FSS 0x00000023
+#define IOC_IOCFG7_PORT_ID_SSI1_TX 0x00000022
+#define IOC_IOCFG7_PORT_ID_SSI1_RX 0x00000021
+#define IOC_IOCFG7_PORT_ID_CPU_SWV 0x00000020
+#define IOC_IOCFG7_PORT_ID_PORT_EVENT7 0x0000001E
+#define IOC_IOCFG7_PORT_ID_PORT_EVENT6 0x0000001D
+#define IOC_IOCFG7_PORT_ID_PORT_EVENT5 0x0000001C
+#define IOC_IOCFG7_PORT_ID_PORT_EVENT4 0x0000001B
+#define IOC_IOCFG7_PORT_ID_PORT_EVENT3 0x0000001A
+#define IOC_IOCFG7_PORT_ID_PORT_EVENT2 0x00000019
+#define IOC_IOCFG7_PORT_ID_PORT_EVENT1 0x00000018
+#define IOC_IOCFG7_PORT_ID_PORT_EVENT0 0x00000017
+#define IOC_IOCFG7_PORT_ID_UART1_RTS 0x00000016
+#define IOC_IOCFG7_PORT_ID_UART1_CTS 0x00000015
+#define IOC_IOCFG7_PORT_ID_UART1_TX 0x00000014
+#define IOC_IOCFG7_PORT_ID_UART1_RX 0x00000013
+#define IOC_IOCFG7_PORT_ID_UART0_RTS 0x00000012
+#define IOC_IOCFG7_PORT_ID_UART0_CTS 0x00000011
+#define IOC_IOCFG7_PORT_ID_UART0_TX 0x00000010
+#define IOC_IOCFG7_PORT_ID_UART0_RX 0x0000000F
+#define IOC_IOCFG7_PORT_ID_I2C_MSSCL 0x0000000E
+#define IOC_IOCFG7_PORT_ID_I2C_MSSDA 0x0000000D
+#define IOC_IOCFG7_PORT_ID_SSI0_CLK 0x0000000C
+#define IOC_IOCFG7_PORT_ID_SSI0_FSS 0x0000000B
+#define IOC_IOCFG7_PORT_ID_SSI0_TX 0x0000000A
+#define IOC_IOCFG7_PORT_ID_SSI0_RX 0x00000009
+#define IOC_IOCFG7_PORT_ID_AUX_IO 0x00000008
+#define IOC_IOCFG7_PORT_ID_AON_CLK32K 0x00000007
+#define IOC_IOCFG7_PORT_ID_GPIO 0x00000000
+
+//*****************************************************************************
+//
+// Register: IOC_O_IOCFG8
+//
+//*****************************************************************************
+// Field: [30] HYST_EN
+//
+// 0: Input hysteresis disable
+// 1: Input hysteresis enable
+#define IOC_IOCFG8_HYST_EN 0x40000000
+#define IOC_IOCFG8_HYST_EN_BITN 30
+#define IOC_IOCFG8_HYST_EN_M 0x40000000
+#define IOC_IOCFG8_HYST_EN_S 30
+
+// Field: [29] IE
+//
+// 0: Input disabled
+// 1: Input enabled
+//
+// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be
+// ignored.
+#define IOC_IOCFG8_IE 0x20000000
+#define IOC_IOCFG8_IE_BITN 29
+#define IOC_IOCFG8_IE_M 0x20000000
+#define IOC_IOCFG8_IE_S 29
+
+// Field: [28:27] WU_CFG
+//
+// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or
+// >0x08:
+//
+// 00: No wake-up
+// 01: No wake-up
+// 10: Wakes up from shutdown if this pad is going low.
+// 11: Wakes up from shutdown if this pad is going high.
+//
+// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08,
+// this register only sets wakeup enable or not.
+//
+// 00, 01: Wakeup disabled
+// 10, 11: Wakeup enabled
+//
+// Polarity is controlled from AON registers.
+//
+// Note:When the MSB is set, the IOC will deactivate the output enable for the
+// DIO.
+#define IOC_IOCFG8_WU_CFG_W 2
+#define IOC_IOCFG8_WU_CFG_M 0x18000000
+#define IOC_IOCFG8_WU_CFG_S 27
+
+// Field: [26:24] IOMODE
+//
+// IO Mode
+// Not applicable for IO configured for AON periph. signals and AUX PORT_ID
+// 0x01-0x08
+// AUX has its own open_source/drain configuration.
+//
+// 0x2: Reserved. Undefined behavior.
+// 0x3: Reserved. Undefined behavior.
+// ENUMs:
+// OPENSRC_INV Open Source
+// Inverted input / output
+// OPENSRC Open Source
+// Normal input / output
+// OPENDR_INV Open Drain
+// Inverted input / output
+// OPENDR Open Drain,
+// Normal input / output
+// INV Inverted input / ouput
+// NORMAL Normal input / output
+#define IOC_IOCFG8_IOMODE_W 3
+#define IOC_IOCFG8_IOMODE_M 0x07000000
+#define IOC_IOCFG8_IOMODE_S 24
+#define IOC_IOCFG8_IOMODE_OPENSRC_INV 0x07000000
+#define IOC_IOCFG8_IOMODE_OPENSRC 0x06000000
+#define IOC_IOCFG8_IOMODE_OPENDR_INV 0x05000000
+#define IOC_IOCFG8_IOMODE_OPENDR 0x04000000
+#define IOC_IOCFG8_IOMODE_INV 0x01000000
+#define IOC_IOCFG8_IOMODE_NORMAL 0x00000000
+
+// Field: [23] IOEV_AON_PROG2_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG2 event
+// 1: Input edge detection asserts AON_PROG2 event
+#define IOC_IOCFG8_IOEV_AON_PROG2_EN 0x00800000
+#define IOC_IOCFG8_IOEV_AON_PROG2_EN_BITN 23
+#define IOC_IOCFG8_IOEV_AON_PROG2_EN_M 0x00800000
+#define IOC_IOCFG8_IOEV_AON_PROG2_EN_S 23
+
+// Field: [22] IOEV_AON_PROG1_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG1 event
+// 1: Input edge detection asserts AON_PROG1 event
+#define IOC_IOCFG8_IOEV_AON_PROG1_EN 0x00400000
+#define IOC_IOCFG8_IOEV_AON_PROG1_EN_BITN 22
+#define IOC_IOCFG8_IOEV_AON_PROG1_EN_M 0x00400000
+#define IOC_IOCFG8_IOEV_AON_PROG1_EN_S 22
+
+// Field: [21] IOEV_AON_PROG0_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG0 event
+// 1: Input edge detection asserts AON_PROG0 event
+#define IOC_IOCFG8_IOEV_AON_PROG0_EN 0x00200000
+#define IOC_IOCFG8_IOEV_AON_PROG0_EN_BITN 21
+#define IOC_IOCFG8_IOEV_AON_PROG0_EN_M 0x00200000
+#define IOC_IOCFG8_IOEV_AON_PROG0_EN_S 21
+
+// Field: [18] EDGE_IRQ_EN
+//
+// 0: No interrupt generation
+// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is
+// enabled)
+#define IOC_IOCFG8_EDGE_IRQ_EN 0x00040000
+#define IOC_IOCFG8_EDGE_IRQ_EN_BITN 18
+#define IOC_IOCFG8_EDGE_IRQ_EN_M 0x00040000
+#define IOC_IOCFG8_EDGE_IRQ_EN_S 18
+
+// Field: [17:16] EDGE_DET
+//
+// Enable generation of edge detection events on this IO
+// ENUMs:
+// BOTH Positive and negative edge detection
+// POS Positive edge detection
+// NEG Negative edge detection
+// NONE No edge detection
+#define IOC_IOCFG8_EDGE_DET_W 2
+#define IOC_IOCFG8_EDGE_DET_M 0x00030000
+#define IOC_IOCFG8_EDGE_DET_S 16
+#define IOC_IOCFG8_EDGE_DET_BOTH 0x00030000
+#define IOC_IOCFG8_EDGE_DET_POS 0x00020000
+#define IOC_IOCFG8_EDGE_DET_NEG 0x00010000
+#define IOC_IOCFG8_EDGE_DET_NONE 0x00000000
+
+// Field: [14:13] PULL_CTL
+//
+// Pull control
+// ENUMs:
+// DIS No pull
+// UP Pull up
+// DWN Pull down
+#define IOC_IOCFG8_PULL_CTL_W 2
+#define IOC_IOCFG8_PULL_CTL_M 0x00006000
+#define IOC_IOCFG8_PULL_CTL_S 13
+#define IOC_IOCFG8_PULL_CTL_DIS 0x00006000
+#define IOC_IOCFG8_PULL_CTL_UP 0x00004000
+#define IOC_IOCFG8_PULL_CTL_DWN 0x00002000
+
+// Field: [12] SLEW_RED
+//
+// 0: Normal slew rate
+// 1: Enables reduced slew rate in output driver.
+#define IOC_IOCFG8_SLEW_RED 0x00001000
+#define IOC_IOCFG8_SLEW_RED_BITN 12
+#define IOC_IOCFG8_SLEW_RED_M 0x00001000
+#define IOC_IOCFG8_SLEW_RED_S 12
+
+// Field: [11:10] IOCURR
+//
+// Selects IO current mode of this IO.
+// ENUMs:
+// 4_8MA Extended-Current (EC) mode: Min 8 mA for double
+// drive strength IOs (min 4 mA for normal IOs)
+// when IOSTR is set to AUTO
+// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set
+// to AUTO
+// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set
+// to AUTO
+#define IOC_IOCFG8_IOCURR_W 2
+#define IOC_IOCFG8_IOCURR_M 0x00000C00
+#define IOC_IOCFG8_IOCURR_S 10
+#define IOC_IOCFG8_IOCURR_4_8MA 0x00000800
+#define IOC_IOCFG8_IOCURR_4MA 0x00000400
+#define IOC_IOCFG8_IOCURR_2MA 0x00000000
+
+// Field: [9:8] IOSTR
+//
+// Select source for drive strength control of this IO.
+// This setting controls the drive strength of the Low-Current (LC) mode.
+// Higher drive strength can be selected in IOCURR
+// ENUMs:
+// MAX Maximum drive strength, controlled by
+// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default
+// values)
+// MED Medium drive strength, controlled by
+// AON_IOC:IOSTRMED (min 2 mA @2.5V with default
+// values)
+// MIN Minimum drive strength, controlled by
+// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default
+// values)
+// AUTO Automatic drive strength, controlled by AON BATMON
+// based on battery voltage. (min 2 mA @VDDS)
+#define IOC_IOCFG8_IOSTR_W 2
+#define IOC_IOCFG8_IOSTR_M 0x00000300
+#define IOC_IOCFG8_IOSTR_S 8
+#define IOC_IOCFG8_IOSTR_MAX 0x00000300
+#define IOC_IOCFG8_IOSTR_MED 0x00000200
+#define IOC_IOCFG8_IOSTR_MIN 0x00000100
+#define IOC_IOCFG8_IOSTR_AUTO 0x00000000
+
+// Field: [7] IOEV_RTC_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert RTC event
+// 1: Input edge detection asserts RTC event
+#define IOC_IOCFG8_IOEV_RTC_EN 0x00000080
+#define IOC_IOCFG8_IOEV_RTC_EN_BITN 7
+#define IOC_IOCFG8_IOEV_RTC_EN_M 0x00000080
+#define IOC_IOCFG8_IOEV_RTC_EN_S 7
+
+// Field: [6] IOEV_MCU_WU_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert MCU_WU event
+// 1: Input edge detection asserts MCU_WU event
+#define IOC_IOCFG8_IOEV_MCU_WU_EN 0x00000040
+#define IOC_IOCFG8_IOEV_MCU_WU_EN_BITN 6
+#define IOC_IOCFG8_IOEV_MCU_WU_EN_M 0x00000040
+#define IOC_IOCFG8_IOEV_MCU_WU_EN_S 6
+
+// Field: [5:0] PORT_ID
+//
+// Selects usage for DIO8
+// ENUMs:
+// RFC_SMI_CL_IN RF Core SMI Command Link In
+// RFC_SMI_CL_OUT RF Core SMI Command Link Out
+// RFC_SMI_DL_IN RF Core SMI Data Link In
+// RFC_SMI_DL_OUT RF Core SMI Data Link Out
+// RFC_GPI1 RF Core Data In 1
+// RFC_GPI0 RF Core Data In 0
+// RFC_GPO3 RF Core Data Out 3
+// RFC_GPO2 RF Core Data Out 2
+// RFC_GPO1 RF Core Data Out 1
+// RFC_GPO0 RF Core Data Out 0
+// RFC_TRC RF Core Trace
+// I2S_MCLK I2S MCLK
+// I2S_BCLK I2S BCLK
+// I2S_WCLK I2S WCLK
+// I2S_AD1 I2S Data 1
+// I2S_AD0 I2S Data 0
+// SSI1_CLK SSI1 CLK
+// SSI1_FSS SSI1 FSS
+// SSI1_TX SSI1 TX
+// SSI1_RX SSI1 RX
+// CPU_SWV CPU SWV
+// PORT_EVENT7 PORT EVENT 7
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT6 PORT EVENT 6
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT5 PORT EVENT 5
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT4 PORT EVENT 4
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT3 PORT EVENT 3
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT2 PORT EVENT 2
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT1 PORT EVENT 1
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT0 PORT EVENT 0
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// UART1_RTS UART1 RTS
+// UART1_CTS UART1 CTS
+// UART1_TX UART1 TX
+// UART1_RX UART1 RX
+// UART0_RTS UART0 RTS
+// UART0_CTS UART0 CTS
+// UART0_TX UART0 TX
+// UART0_RX UART0 RX
+// I2C_MSSCL I2C Clock
+// I2C_MSSDA I2C Data
+// SSI0_CLK SSI0 CLK
+// SSI0_FSS SSI0 FSS
+// SSI0_TX SSI0 TX
+// SSI0_RX SSI0 RX
+// AUX_IO AUX IO
+// AON_CLK32K AON 32 KHz clock (SCLK_LF)
+// GPIO General Purpose IO
+#define IOC_IOCFG8_PORT_ID_W 6
+#define IOC_IOCFG8_PORT_ID_M 0x0000003F
+#define IOC_IOCFG8_PORT_ID_S 0
+#define IOC_IOCFG8_PORT_ID_RFC_SMI_CL_IN 0x00000038
+#define IOC_IOCFG8_PORT_ID_RFC_SMI_CL_OUT 0x00000037
+#define IOC_IOCFG8_PORT_ID_RFC_SMI_DL_IN 0x00000036
+#define IOC_IOCFG8_PORT_ID_RFC_SMI_DL_OUT 0x00000035
+#define IOC_IOCFG8_PORT_ID_RFC_GPI1 0x00000034
+#define IOC_IOCFG8_PORT_ID_RFC_GPI0 0x00000033
+#define IOC_IOCFG8_PORT_ID_RFC_GPO3 0x00000032
+#define IOC_IOCFG8_PORT_ID_RFC_GPO2 0x00000031
+#define IOC_IOCFG8_PORT_ID_RFC_GPO1 0x00000030
+#define IOC_IOCFG8_PORT_ID_RFC_GPO0 0x0000002F
+#define IOC_IOCFG8_PORT_ID_RFC_TRC 0x0000002E
+#define IOC_IOCFG8_PORT_ID_I2S_MCLK 0x00000029
+#define IOC_IOCFG8_PORT_ID_I2S_BCLK 0x00000028
+#define IOC_IOCFG8_PORT_ID_I2S_WCLK 0x00000027
+#define IOC_IOCFG8_PORT_ID_I2S_AD1 0x00000026
+#define IOC_IOCFG8_PORT_ID_I2S_AD0 0x00000025
+#define IOC_IOCFG8_PORT_ID_SSI1_CLK 0x00000024
+#define IOC_IOCFG8_PORT_ID_SSI1_FSS 0x00000023
+#define IOC_IOCFG8_PORT_ID_SSI1_TX 0x00000022
+#define IOC_IOCFG8_PORT_ID_SSI1_RX 0x00000021
+#define IOC_IOCFG8_PORT_ID_CPU_SWV 0x00000020
+#define IOC_IOCFG8_PORT_ID_PORT_EVENT7 0x0000001E
+#define IOC_IOCFG8_PORT_ID_PORT_EVENT6 0x0000001D
+#define IOC_IOCFG8_PORT_ID_PORT_EVENT5 0x0000001C
+#define IOC_IOCFG8_PORT_ID_PORT_EVENT4 0x0000001B
+#define IOC_IOCFG8_PORT_ID_PORT_EVENT3 0x0000001A
+#define IOC_IOCFG8_PORT_ID_PORT_EVENT2 0x00000019
+#define IOC_IOCFG8_PORT_ID_PORT_EVENT1 0x00000018
+#define IOC_IOCFG8_PORT_ID_PORT_EVENT0 0x00000017
+#define IOC_IOCFG8_PORT_ID_UART1_RTS 0x00000016
+#define IOC_IOCFG8_PORT_ID_UART1_CTS 0x00000015
+#define IOC_IOCFG8_PORT_ID_UART1_TX 0x00000014
+#define IOC_IOCFG8_PORT_ID_UART1_RX 0x00000013
+#define IOC_IOCFG8_PORT_ID_UART0_RTS 0x00000012
+#define IOC_IOCFG8_PORT_ID_UART0_CTS 0x00000011
+#define IOC_IOCFG8_PORT_ID_UART0_TX 0x00000010
+#define IOC_IOCFG8_PORT_ID_UART0_RX 0x0000000F
+#define IOC_IOCFG8_PORT_ID_I2C_MSSCL 0x0000000E
+#define IOC_IOCFG8_PORT_ID_I2C_MSSDA 0x0000000D
+#define IOC_IOCFG8_PORT_ID_SSI0_CLK 0x0000000C
+#define IOC_IOCFG8_PORT_ID_SSI0_FSS 0x0000000B
+#define IOC_IOCFG8_PORT_ID_SSI0_TX 0x0000000A
+#define IOC_IOCFG8_PORT_ID_SSI0_RX 0x00000009
+#define IOC_IOCFG8_PORT_ID_AUX_IO 0x00000008
+#define IOC_IOCFG8_PORT_ID_AON_CLK32K 0x00000007
+#define IOC_IOCFG8_PORT_ID_GPIO 0x00000000
+
+//*****************************************************************************
+//
+// Register: IOC_O_IOCFG9
+//
+//*****************************************************************************
+// Field: [30] HYST_EN
+//
+// 0: Input hysteresis disable
+// 1: Input hysteresis enable
+#define IOC_IOCFG9_HYST_EN 0x40000000
+#define IOC_IOCFG9_HYST_EN_BITN 30
+#define IOC_IOCFG9_HYST_EN_M 0x40000000
+#define IOC_IOCFG9_HYST_EN_S 30
+
+// Field: [29] IE
+//
+// 0: Input disabled
+// 1: Input enabled
+//
+// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be
+// ignored.
+#define IOC_IOCFG9_IE 0x20000000
+#define IOC_IOCFG9_IE_BITN 29
+#define IOC_IOCFG9_IE_M 0x20000000
+#define IOC_IOCFG9_IE_S 29
+
+// Field: [28:27] WU_CFG
+//
+// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or
+// >0x08:
+//
+// 00: No wake-up
+// 01: No wake-up
+// 10: Wakes up from shutdown if this pad is going low.
+// 11: Wakes up from shutdown if this pad is going high.
+//
+// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08,
+// this register only sets wakeup enable or not.
+//
+// 00, 01: Wakeup disabled
+// 10, 11: Wakeup enabled
+//
+// Polarity is controlled from AON registers.
+//
+// Note:When the MSB is set, the IOC will deactivate the output enable for the
+// DIO.
+#define IOC_IOCFG9_WU_CFG_W 2
+#define IOC_IOCFG9_WU_CFG_M 0x18000000
+#define IOC_IOCFG9_WU_CFG_S 27
+
+// Field: [26:24] IOMODE
+//
+// IO Mode
+// Not applicable for IO configured for AON periph. signals and AUX PORT_ID
+// 0x01-0x08
+// AUX has its own open_source/drain configuration.
+//
+// 0x2: Reserved. Undefined behavior.
+// 0x3: Reserved. Undefined behavior.
+// ENUMs:
+// OPENSRC_INV Open Source
+// Inverted input / output
+// OPENSRC Open Source
+// Normal input / output
+// OPENDR_INV Open Drain
+// Inverted input / output
+// OPENDR Open Drain,
+// Normal input / output
+// INV Inverted input / ouput
+// NORMAL Normal input / output
+#define IOC_IOCFG9_IOMODE_W 3
+#define IOC_IOCFG9_IOMODE_M 0x07000000
+#define IOC_IOCFG9_IOMODE_S 24
+#define IOC_IOCFG9_IOMODE_OPENSRC_INV 0x07000000
+#define IOC_IOCFG9_IOMODE_OPENSRC 0x06000000
+#define IOC_IOCFG9_IOMODE_OPENDR_INV 0x05000000
+#define IOC_IOCFG9_IOMODE_OPENDR 0x04000000
+#define IOC_IOCFG9_IOMODE_INV 0x01000000
+#define IOC_IOCFG9_IOMODE_NORMAL 0x00000000
+
+// Field: [23] IOEV_AON_PROG2_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG2 event
+// 1: Input edge detection asserts AON_PROG2 event
+#define IOC_IOCFG9_IOEV_AON_PROG2_EN 0x00800000
+#define IOC_IOCFG9_IOEV_AON_PROG2_EN_BITN 23
+#define IOC_IOCFG9_IOEV_AON_PROG2_EN_M 0x00800000
+#define IOC_IOCFG9_IOEV_AON_PROG2_EN_S 23
+
+// Field: [22] IOEV_AON_PROG1_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG1 event
+// 1: Input edge detection asserts AON_PROG1 event
+#define IOC_IOCFG9_IOEV_AON_PROG1_EN 0x00400000
+#define IOC_IOCFG9_IOEV_AON_PROG1_EN_BITN 22
+#define IOC_IOCFG9_IOEV_AON_PROG1_EN_M 0x00400000
+#define IOC_IOCFG9_IOEV_AON_PROG1_EN_S 22
+
+// Field: [21] IOEV_AON_PROG0_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG0 event
+// 1: Input edge detection asserts AON_PROG0 event
+#define IOC_IOCFG9_IOEV_AON_PROG0_EN 0x00200000
+#define IOC_IOCFG9_IOEV_AON_PROG0_EN_BITN 21
+#define IOC_IOCFG9_IOEV_AON_PROG0_EN_M 0x00200000
+#define IOC_IOCFG9_IOEV_AON_PROG0_EN_S 21
+
+// Field: [18] EDGE_IRQ_EN
+//
+// 0: No interrupt generation
+// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is
+// enabled)
+#define IOC_IOCFG9_EDGE_IRQ_EN 0x00040000
+#define IOC_IOCFG9_EDGE_IRQ_EN_BITN 18
+#define IOC_IOCFG9_EDGE_IRQ_EN_M 0x00040000
+#define IOC_IOCFG9_EDGE_IRQ_EN_S 18
+
+// Field: [17:16] EDGE_DET
+//
+// Enable generation of edge detection events on this IO
+// ENUMs:
+// BOTH Positive and negative edge detection
+// POS Positive edge detection
+// NEG Negative edge detection
+// NONE No edge detection
+#define IOC_IOCFG9_EDGE_DET_W 2
+#define IOC_IOCFG9_EDGE_DET_M 0x00030000
+#define IOC_IOCFG9_EDGE_DET_S 16
+#define IOC_IOCFG9_EDGE_DET_BOTH 0x00030000
+#define IOC_IOCFG9_EDGE_DET_POS 0x00020000
+#define IOC_IOCFG9_EDGE_DET_NEG 0x00010000
+#define IOC_IOCFG9_EDGE_DET_NONE 0x00000000
+
+// Field: [14:13] PULL_CTL
+//
+// Pull control
+// ENUMs:
+// DIS No pull
+// UP Pull up
+// DWN Pull down
+#define IOC_IOCFG9_PULL_CTL_W 2
+#define IOC_IOCFG9_PULL_CTL_M 0x00006000
+#define IOC_IOCFG9_PULL_CTL_S 13
+#define IOC_IOCFG9_PULL_CTL_DIS 0x00006000
+#define IOC_IOCFG9_PULL_CTL_UP 0x00004000
+#define IOC_IOCFG9_PULL_CTL_DWN 0x00002000
+
+// Field: [12] SLEW_RED
+//
+// 0: Normal slew rate
+// 1: Enables reduced slew rate in output driver.
+#define IOC_IOCFG9_SLEW_RED 0x00001000
+#define IOC_IOCFG9_SLEW_RED_BITN 12
+#define IOC_IOCFG9_SLEW_RED_M 0x00001000
+#define IOC_IOCFG9_SLEW_RED_S 12
+
+// Field: [11:10] IOCURR
+//
+// Selects IO current mode of this IO.
+// ENUMs:
+// 4_8MA Extended-Current (EC) mode: Min 8 mA for double
+// drive strength IOs (min 4 mA for normal IOs)
+// when IOSTR is set to AUTO
+// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set
+// to AUTO
+// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set
+// to AUTO
+#define IOC_IOCFG9_IOCURR_W 2
+#define IOC_IOCFG9_IOCURR_M 0x00000C00
+#define IOC_IOCFG9_IOCURR_S 10
+#define IOC_IOCFG9_IOCURR_4_8MA 0x00000800
+#define IOC_IOCFG9_IOCURR_4MA 0x00000400
+#define IOC_IOCFG9_IOCURR_2MA 0x00000000
+
+// Field: [9:8] IOSTR
+//
+// Select source for drive strength control of this IO.
+// This setting controls the drive strength of the Low-Current (LC) mode.
+// Higher drive strength can be selected in IOCURR
+// ENUMs:
+// MAX Maximum drive strength, controlled by
+// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default
+// values)
+// MED Medium drive strength, controlled by
+// AON_IOC:IOSTRMED (min 2 mA @2.5V with default
+// values)
+// MIN Minimum drive strength, controlled by
+// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default
+// values)
+// AUTO Automatic drive strength, controlled by AON BATMON
+// based on battery voltage. (min 2 mA @VDDS)
+#define IOC_IOCFG9_IOSTR_W 2
+#define IOC_IOCFG9_IOSTR_M 0x00000300
+#define IOC_IOCFG9_IOSTR_S 8
+#define IOC_IOCFG9_IOSTR_MAX 0x00000300
+#define IOC_IOCFG9_IOSTR_MED 0x00000200
+#define IOC_IOCFG9_IOSTR_MIN 0x00000100
+#define IOC_IOCFG9_IOSTR_AUTO 0x00000000
+
+// Field: [7] IOEV_RTC_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert RTC event
+// 1: Input edge detection asserts RTC event
+#define IOC_IOCFG9_IOEV_RTC_EN 0x00000080
+#define IOC_IOCFG9_IOEV_RTC_EN_BITN 7
+#define IOC_IOCFG9_IOEV_RTC_EN_M 0x00000080
+#define IOC_IOCFG9_IOEV_RTC_EN_S 7
+
+// Field: [6] IOEV_MCU_WU_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert MCU_WU event
+// 1: Input edge detection asserts MCU_WU event
+#define IOC_IOCFG9_IOEV_MCU_WU_EN 0x00000040
+#define IOC_IOCFG9_IOEV_MCU_WU_EN_BITN 6
+#define IOC_IOCFG9_IOEV_MCU_WU_EN_M 0x00000040
+#define IOC_IOCFG9_IOEV_MCU_WU_EN_S 6
+
+// Field: [5:0] PORT_ID
+//
+// Selects usage for DIO9
+// ENUMs:
+// RFC_SMI_CL_IN RF Core SMI Command Link In
+// RFC_SMI_CL_OUT RF Core SMI Command Link Out
+// RFC_SMI_DL_IN RF Core SMI Data Link In
+// RFC_SMI_DL_OUT RF Core SMI Data Link Out
+// RFC_GPI1 RF Core Data In 1
+// RFC_GPI0 RF Core Data In 0
+// RFC_GPO3 RF Core Data Out 3
+// RFC_GPO2 RF Core Data Out 2
+// RFC_GPO1 RF Core Data Out 1
+// RFC_GPO0 RF Core Data Out 0
+// RFC_TRC RF Core Trace
+// I2S_MCLK I2S MCLK
+// I2S_BCLK I2S BCLK
+// I2S_WCLK I2S WCLK
+// I2S_AD1 I2S Data 1
+// I2S_AD0 I2S Data 0
+// SSI1_CLK SSI1 CLK
+// SSI1_FSS SSI1 FSS
+// SSI1_TX SSI1 TX
+// SSI1_RX SSI1 RX
+// CPU_SWV CPU SWV
+// PORT_EVENT7 PORT EVENT 7
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT6 PORT EVENT 6
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT5 PORT EVENT 5
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT4 PORT EVENT 4
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT3 PORT EVENT 3
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT2 PORT EVENT 2
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT1 PORT EVENT 1
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT0 PORT EVENT 0
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// UART1_RTS UART1 RTS
+// UART1_CTS UART1 CTS
+// UART1_TX UART1 TX
+// UART1_RX UART1 RX
+// UART0_RTS UART0 RTS
+// UART0_CTS UART0 CTS
+// UART0_TX UART0 TX
+// UART0_RX UART0 RX
+// I2C_MSSCL I2C Clock
+// I2C_MSSDA I2C Data
+// SSI0_CLK SSI0 CLK
+// SSI0_FSS SSI0 FSS
+// SSI0_TX SSI0 TX
+// SSI0_RX SSI0 RX
+// AUX_IO AUX IO
+// AON_CLK32K AON 32 KHz clock (SCLK_LF)
+// GPIO General Purpose IO
+#define IOC_IOCFG9_PORT_ID_W 6
+#define IOC_IOCFG9_PORT_ID_M 0x0000003F
+#define IOC_IOCFG9_PORT_ID_S 0
+#define IOC_IOCFG9_PORT_ID_RFC_SMI_CL_IN 0x00000038
+#define IOC_IOCFG9_PORT_ID_RFC_SMI_CL_OUT 0x00000037
+#define IOC_IOCFG9_PORT_ID_RFC_SMI_DL_IN 0x00000036
+#define IOC_IOCFG9_PORT_ID_RFC_SMI_DL_OUT 0x00000035
+#define IOC_IOCFG9_PORT_ID_RFC_GPI1 0x00000034
+#define IOC_IOCFG9_PORT_ID_RFC_GPI0 0x00000033
+#define IOC_IOCFG9_PORT_ID_RFC_GPO3 0x00000032
+#define IOC_IOCFG9_PORT_ID_RFC_GPO2 0x00000031
+#define IOC_IOCFG9_PORT_ID_RFC_GPO1 0x00000030
+#define IOC_IOCFG9_PORT_ID_RFC_GPO0 0x0000002F
+#define IOC_IOCFG9_PORT_ID_RFC_TRC 0x0000002E
+#define IOC_IOCFG9_PORT_ID_I2S_MCLK 0x00000029
+#define IOC_IOCFG9_PORT_ID_I2S_BCLK 0x00000028
+#define IOC_IOCFG9_PORT_ID_I2S_WCLK 0x00000027
+#define IOC_IOCFG9_PORT_ID_I2S_AD1 0x00000026
+#define IOC_IOCFG9_PORT_ID_I2S_AD0 0x00000025
+#define IOC_IOCFG9_PORT_ID_SSI1_CLK 0x00000024
+#define IOC_IOCFG9_PORT_ID_SSI1_FSS 0x00000023
+#define IOC_IOCFG9_PORT_ID_SSI1_TX 0x00000022
+#define IOC_IOCFG9_PORT_ID_SSI1_RX 0x00000021
+#define IOC_IOCFG9_PORT_ID_CPU_SWV 0x00000020
+#define IOC_IOCFG9_PORT_ID_PORT_EVENT7 0x0000001E
+#define IOC_IOCFG9_PORT_ID_PORT_EVENT6 0x0000001D
+#define IOC_IOCFG9_PORT_ID_PORT_EVENT5 0x0000001C
+#define IOC_IOCFG9_PORT_ID_PORT_EVENT4 0x0000001B
+#define IOC_IOCFG9_PORT_ID_PORT_EVENT3 0x0000001A
+#define IOC_IOCFG9_PORT_ID_PORT_EVENT2 0x00000019
+#define IOC_IOCFG9_PORT_ID_PORT_EVENT1 0x00000018
+#define IOC_IOCFG9_PORT_ID_PORT_EVENT0 0x00000017
+#define IOC_IOCFG9_PORT_ID_UART1_RTS 0x00000016
+#define IOC_IOCFG9_PORT_ID_UART1_CTS 0x00000015
+#define IOC_IOCFG9_PORT_ID_UART1_TX 0x00000014
+#define IOC_IOCFG9_PORT_ID_UART1_RX 0x00000013
+#define IOC_IOCFG9_PORT_ID_UART0_RTS 0x00000012
+#define IOC_IOCFG9_PORT_ID_UART0_CTS 0x00000011
+#define IOC_IOCFG9_PORT_ID_UART0_TX 0x00000010
+#define IOC_IOCFG9_PORT_ID_UART0_RX 0x0000000F
+#define IOC_IOCFG9_PORT_ID_I2C_MSSCL 0x0000000E
+#define IOC_IOCFG9_PORT_ID_I2C_MSSDA 0x0000000D
+#define IOC_IOCFG9_PORT_ID_SSI0_CLK 0x0000000C
+#define IOC_IOCFG9_PORT_ID_SSI0_FSS 0x0000000B
+#define IOC_IOCFG9_PORT_ID_SSI0_TX 0x0000000A
+#define IOC_IOCFG9_PORT_ID_SSI0_RX 0x00000009
+#define IOC_IOCFG9_PORT_ID_AUX_IO 0x00000008
+#define IOC_IOCFG9_PORT_ID_AON_CLK32K 0x00000007
+#define IOC_IOCFG9_PORT_ID_GPIO 0x00000000
+
+//*****************************************************************************
+//
+// Register: IOC_O_IOCFG10
+//
+//*****************************************************************************
+// Field: [30] HYST_EN
+//
+// 0: Input hysteresis disable
+// 1: Input hysteresis enable
+#define IOC_IOCFG10_HYST_EN 0x40000000
+#define IOC_IOCFG10_HYST_EN_BITN 30
+#define IOC_IOCFG10_HYST_EN_M 0x40000000
+#define IOC_IOCFG10_HYST_EN_S 30
+
+// Field: [29] IE
+//
+// 0: Input disabled
+// 1: Input enabled
+//
+// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be
+// ignored.
+#define IOC_IOCFG10_IE 0x20000000
+#define IOC_IOCFG10_IE_BITN 29
+#define IOC_IOCFG10_IE_M 0x20000000
+#define IOC_IOCFG10_IE_S 29
+
+// Field: [28:27] WU_CFG
+//
+// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or
+// >0x08:
+//
+// 00: No wake-up
+// 01: No wake-up
+// 10: Wakes up from shutdown if this pad is going low.
+// 11: Wakes up from shutdown if this pad is going high.
+//
+// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08,
+// this register only sets wakeup enable or not.
+//
+// 00, 01: Wakeup disabled
+// 10, 11: Wakeup enabled
+//
+// Polarity is controlled from AON registers.
+//
+// Note:When the MSB is set, the IOC will deactivate the output enable for the
+// DIO.
+#define IOC_IOCFG10_WU_CFG_W 2
+#define IOC_IOCFG10_WU_CFG_M 0x18000000
+#define IOC_IOCFG10_WU_CFG_S 27
+
+// Field: [26:24] IOMODE
+//
+// IO Mode
+// Not applicable for IO configured for AON periph. signals and AUX PORT_ID
+// 0x01-0x08
+// AUX has its own open_source/drain configuration.
+//
+// 0x2: Reserved. Undefined behavior.
+// 0x3: Reserved. Undefined behavior.
+// ENUMs:
+// OPENSRC_INV Open Source
+// Inverted input / output
+// OPENSRC Open Source
+// Normal input / output
+// OPENDR_INV Open Drain
+// Inverted input / output
+// OPENDR Open Drain,
+// Normal input / output
+// INV Inverted input / ouput
+// NORMAL Normal input / output
+#define IOC_IOCFG10_IOMODE_W 3
+#define IOC_IOCFG10_IOMODE_M 0x07000000
+#define IOC_IOCFG10_IOMODE_S 24
+#define IOC_IOCFG10_IOMODE_OPENSRC_INV 0x07000000
+#define IOC_IOCFG10_IOMODE_OPENSRC 0x06000000
+#define IOC_IOCFG10_IOMODE_OPENDR_INV 0x05000000
+#define IOC_IOCFG10_IOMODE_OPENDR 0x04000000
+#define IOC_IOCFG10_IOMODE_INV 0x01000000
+#define IOC_IOCFG10_IOMODE_NORMAL 0x00000000
+
+// Field: [23] IOEV_AON_PROG2_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG2 event
+// 1: Input edge detection asserts AON_PROG2 event
+#define IOC_IOCFG10_IOEV_AON_PROG2_EN 0x00800000
+#define IOC_IOCFG10_IOEV_AON_PROG2_EN_BITN 23
+#define IOC_IOCFG10_IOEV_AON_PROG2_EN_M 0x00800000
+#define IOC_IOCFG10_IOEV_AON_PROG2_EN_S 23
+
+// Field: [22] IOEV_AON_PROG1_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG1 event
+// 1: Input edge detection asserts AON_PROG1 event
+#define IOC_IOCFG10_IOEV_AON_PROG1_EN 0x00400000
+#define IOC_IOCFG10_IOEV_AON_PROG1_EN_BITN 22
+#define IOC_IOCFG10_IOEV_AON_PROG1_EN_M 0x00400000
+#define IOC_IOCFG10_IOEV_AON_PROG1_EN_S 22
+
+// Field: [21] IOEV_AON_PROG0_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG0 event
+// 1: Input edge detection asserts AON_PROG0 event
+#define IOC_IOCFG10_IOEV_AON_PROG0_EN 0x00200000
+#define IOC_IOCFG10_IOEV_AON_PROG0_EN_BITN 21
+#define IOC_IOCFG10_IOEV_AON_PROG0_EN_M 0x00200000
+#define IOC_IOCFG10_IOEV_AON_PROG0_EN_S 21
+
+// Field: [18] EDGE_IRQ_EN
+//
+// 0: No interrupt generation
+// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is
+// enabled)
+#define IOC_IOCFG10_EDGE_IRQ_EN 0x00040000
+#define IOC_IOCFG10_EDGE_IRQ_EN_BITN 18
+#define IOC_IOCFG10_EDGE_IRQ_EN_M 0x00040000
+#define IOC_IOCFG10_EDGE_IRQ_EN_S 18
+
+// Field: [17:16] EDGE_DET
+//
+// Enable generation of edge detection events on this IO
+// ENUMs:
+// BOTH Positive and negative edge detection
+// POS Positive edge detection
+// NEG Negative edge detection
+// NONE No edge detection
+#define IOC_IOCFG10_EDGE_DET_W 2
+#define IOC_IOCFG10_EDGE_DET_M 0x00030000
+#define IOC_IOCFG10_EDGE_DET_S 16
+#define IOC_IOCFG10_EDGE_DET_BOTH 0x00030000
+#define IOC_IOCFG10_EDGE_DET_POS 0x00020000
+#define IOC_IOCFG10_EDGE_DET_NEG 0x00010000
+#define IOC_IOCFG10_EDGE_DET_NONE 0x00000000
+
+// Field: [14:13] PULL_CTL
+//
+// Pull control
+// ENUMs:
+// DIS No pull
+// UP Pull up
+// DWN Pull down
+#define IOC_IOCFG10_PULL_CTL_W 2
+#define IOC_IOCFG10_PULL_CTL_M 0x00006000
+#define IOC_IOCFG10_PULL_CTL_S 13
+#define IOC_IOCFG10_PULL_CTL_DIS 0x00006000
+#define IOC_IOCFG10_PULL_CTL_UP 0x00004000
+#define IOC_IOCFG10_PULL_CTL_DWN 0x00002000
+
+// Field: [12] SLEW_RED
+//
+// 0: Normal slew rate
+// 1: Enables reduced slew rate in output driver.
+#define IOC_IOCFG10_SLEW_RED 0x00001000
+#define IOC_IOCFG10_SLEW_RED_BITN 12
+#define IOC_IOCFG10_SLEW_RED_M 0x00001000
+#define IOC_IOCFG10_SLEW_RED_S 12
+
+// Field: [11:10] IOCURR
+//
+// Selects IO current mode of this IO.
+// ENUMs:
+// 4_8MA Extended-Current (EC) mode: Min 8 mA for double
+// drive strength IOs (min 4 mA for normal IOs)
+// when IOSTR is set to AUTO
+// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set
+// to AUTO
+// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set
+// to AUTO
+#define IOC_IOCFG10_IOCURR_W 2
+#define IOC_IOCFG10_IOCURR_M 0x00000C00
+#define IOC_IOCFG10_IOCURR_S 10
+#define IOC_IOCFG10_IOCURR_4_8MA 0x00000800
+#define IOC_IOCFG10_IOCURR_4MA 0x00000400
+#define IOC_IOCFG10_IOCURR_2MA 0x00000000
+
+// Field: [9:8] IOSTR
+//
+// Select source for drive strength control of this IO.
+// This setting controls the drive strength of the Low-Current (LC) mode.
+// Higher drive strength can be selected in IOCURR
+// ENUMs:
+// MAX Maximum drive strength, controlled by
+// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default
+// values)
+// MED Medium drive strength, controlled by
+// AON_IOC:IOSTRMED (min 2 mA @2.5V with default
+// values)
+// MIN Minimum drive strength, controlled by
+// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default
+// values)
+// AUTO Automatic drive strength, controlled by AON BATMON
+// based on battery voltage. (min 2 mA @VDDS)
+#define IOC_IOCFG10_IOSTR_W 2
+#define IOC_IOCFG10_IOSTR_M 0x00000300
+#define IOC_IOCFG10_IOSTR_S 8
+#define IOC_IOCFG10_IOSTR_MAX 0x00000300
+#define IOC_IOCFG10_IOSTR_MED 0x00000200
+#define IOC_IOCFG10_IOSTR_MIN 0x00000100
+#define IOC_IOCFG10_IOSTR_AUTO 0x00000000
+
+// Field: [7] IOEV_RTC_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert RTC event
+// 1: Input edge detection asserts RTC event
+#define IOC_IOCFG10_IOEV_RTC_EN 0x00000080
+#define IOC_IOCFG10_IOEV_RTC_EN_BITN 7
+#define IOC_IOCFG10_IOEV_RTC_EN_M 0x00000080
+#define IOC_IOCFG10_IOEV_RTC_EN_S 7
+
+// Field: [6] IOEV_MCU_WU_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert MCU_WU event
+// 1: Input edge detection asserts MCU_WU event
+#define IOC_IOCFG10_IOEV_MCU_WU_EN 0x00000040
+#define IOC_IOCFG10_IOEV_MCU_WU_EN_BITN 6
+#define IOC_IOCFG10_IOEV_MCU_WU_EN_M 0x00000040
+#define IOC_IOCFG10_IOEV_MCU_WU_EN_S 6
+
+// Field: [5:0] PORT_ID
+//
+// Selects usage for DIO10
+// ENUMs:
+// RFC_SMI_CL_IN RF Core SMI Command Link In
+// RFC_SMI_CL_OUT RF Core SMI Command Link Out
+// RFC_SMI_DL_IN RF Core SMI Data Link In
+// RFC_SMI_DL_OUT RF Core SMI Data Link Out
+// RFC_GPI1 RF Core Data In 1
+// RFC_GPI0 RF Core Data In 0
+// RFC_GPO3 RF Core Data Out 3
+// RFC_GPO2 RF Core Data Out 2
+// RFC_GPO1 RF Core Data Out 1
+// RFC_GPO0 RF Core Data Out 0
+// RFC_TRC RF Core Trace
+// I2S_MCLK I2S MCLK
+// I2S_BCLK I2S BCLK
+// I2S_WCLK I2S WCLK
+// I2S_AD1 I2S Data 1
+// I2S_AD0 I2S Data 0
+// SSI1_CLK SSI1 CLK
+// SSI1_FSS SSI1 FSS
+// SSI1_TX SSI1 TX
+// SSI1_RX SSI1 RX
+// CPU_SWV CPU SWV
+// PORT_EVENT7 PORT EVENT 7
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT6 PORT EVENT 6
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT5 PORT EVENT 5
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT4 PORT EVENT 4
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT3 PORT EVENT 3
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT2 PORT EVENT 2
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT1 PORT EVENT 1
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT0 PORT EVENT 0
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// UART1_RTS UART1 RTS
+// UART1_CTS UART1 CTS
+// UART1_TX UART1 TX
+// UART1_RX UART1 RX
+// UART0_RTS UART0 RTS
+// UART0_CTS UART0 CTS
+// UART0_TX UART0 TX
+// UART0_RX UART0 RX
+// I2C_MSSCL I2C Clock
+// I2C_MSSDA I2C Data
+// SSI0_CLK SSI0 CLK
+// SSI0_FSS SSI0 FSS
+// SSI0_TX SSI0 TX
+// SSI0_RX SSI0 RX
+// AUX_IO AUX IO
+// AON_CLK32K AON 32 KHz clock (SCLK_LF)
+// GPIO General Purpose IO
+#define IOC_IOCFG10_PORT_ID_W 6
+#define IOC_IOCFG10_PORT_ID_M 0x0000003F
+#define IOC_IOCFG10_PORT_ID_S 0
+#define IOC_IOCFG10_PORT_ID_RFC_SMI_CL_IN 0x00000038
+#define IOC_IOCFG10_PORT_ID_RFC_SMI_CL_OUT 0x00000037
+#define IOC_IOCFG10_PORT_ID_RFC_SMI_DL_IN 0x00000036
+#define IOC_IOCFG10_PORT_ID_RFC_SMI_DL_OUT 0x00000035
+#define IOC_IOCFG10_PORT_ID_RFC_GPI1 0x00000034
+#define IOC_IOCFG10_PORT_ID_RFC_GPI0 0x00000033
+#define IOC_IOCFG10_PORT_ID_RFC_GPO3 0x00000032
+#define IOC_IOCFG10_PORT_ID_RFC_GPO2 0x00000031
+#define IOC_IOCFG10_PORT_ID_RFC_GPO1 0x00000030
+#define IOC_IOCFG10_PORT_ID_RFC_GPO0 0x0000002F
+#define IOC_IOCFG10_PORT_ID_RFC_TRC 0x0000002E
+#define IOC_IOCFG10_PORT_ID_I2S_MCLK 0x00000029
+#define IOC_IOCFG10_PORT_ID_I2S_BCLK 0x00000028
+#define IOC_IOCFG10_PORT_ID_I2S_WCLK 0x00000027
+#define IOC_IOCFG10_PORT_ID_I2S_AD1 0x00000026
+#define IOC_IOCFG10_PORT_ID_I2S_AD0 0x00000025
+#define IOC_IOCFG10_PORT_ID_SSI1_CLK 0x00000024
+#define IOC_IOCFG10_PORT_ID_SSI1_FSS 0x00000023
+#define IOC_IOCFG10_PORT_ID_SSI1_TX 0x00000022
+#define IOC_IOCFG10_PORT_ID_SSI1_RX 0x00000021
+#define IOC_IOCFG10_PORT_ID_CPU_SWV 0x00000020
+#define IOC_IOCFG10_PORT_ID_PORT_EVENT7 0x0000001E
+#define IOC_IOCFG10_PORT_ID_PORT_EVENT6 0x0000001D
+#define IOC_IOCFG10_PORT_ID_PORT_EVENT5 0x0000001C
+#define IOC_IOCFG10_PORT_ID_PORT_EVENT4 0x0000001B
+#define IOC_IOCFG10_PORT_ID_PORT_EVENT3 0x0000001A
+#define IOC_IOCFG10_PORT_ID_PORT_EVENT2 0x00000019
+#define IOC_IOCFG10_PORT_ID_PORT_EVENT1 0x00000018
+#define IOC_IOCFG10_PORT_ID_PORT_EVENT0 0x00000017
+#define IOC_IOCFG10_PORT_ID_UART1_RTS 0x00000016
+#define IOC_IOCFG10_PORT_ID_UART1_CTS 0x00000015
+#define IOC_IOCFG10_PORT_ID_UART1_TX 0x00000014
+#define IOC_IOCFG10_PORT_ID_UART1_RX 0x00000013
+#define IOC_IOCFG10_PORT_ID_UART0_RTS 0x00000012
+#define IOC_IOCFG10_PORT_ID_UART0_CTS 0x00000011
+#define IOC_IOCFG10_PORT_ID_UART0_TX 0x00000010
+#define IOC_IOCFG10_PORT_ID_UART0_RX 0x0000000F
+#define IOC_IOCFG10_PORT_ID_I2C_MSSCL 0x0000000E
+#define IOC_IOCFG10_PORT_ID_I2C_MSSDA 0x0000000D
+#define IOC_IOCFG10_PORT_ID_SSI0_CLK 0x0000000C
+#define IOC_IOCFG10_PORT_ID_SSI0_FSS 0x0000000B
+#define IOC_IOCFG10_PORT_ID_SSI0_TX 0x0000000A
+#define IOC_IOCFG10_PORT_ID_SSI0_RX 0x00000009
+#define IOC_IOCFG10_PORT_ID_AUX_IO 0x00000008
+#define IOC_IOCFG10_PORT_ID_AON_CLK32K 0x00000007
+#define IOC_IOCFG10_PORT_ID_GPIO 0x00000000
+
+//*****************************************************************************
+//
+// Register: IOC_O_IOCFG11
+//
+//*****************************************************************************
+// Field: [30] HYST_EN
+//
+// 0: Input hysteresis disable
+// 1: Input hysteresis enable
+#define IOC_IOCFG11_HYST_EN 0x40000000
+#define IOC_IOCFG11_HYST_EN_BITN 30
+#define IOC_IOCFG11_HYST_EN_M 0x40000000
+#define IOC_IOCFG11_HYST_EN_S 30
+
+// Field: [29] IE
+//
+// 0: Input disabled
+// 1: Input enabled
+//
+// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be
+// ignored.
+#define IOC_IOCFG11_IE 0x20000000
+#define IOC_IOCFG11_IE_BITN 29
+#define IOC_IOCFG11_IE_M 0x20000000
+#define IOC_IOCFG11_IE_S 29
+
+// Field: [28:27] WU_CFG
+//
+// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or
+// >0x08:
+//
+// 00: No wake-up
+// 01: No wake-up
+// 10: Wakes up from shutdown if this pad is going low.
+// 11: Wakes up from shutdown if this pad is going high.
+//
+// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08,
+// this register only sets wakeup enable or not.
+//
+// 00, 01: Wakeup disabled
+// 10, 11: Wakeup enabled
+//
+// Polarity is controlled from AON registers.
+//
+// Note:When the MSB is set, the IOC will deactivate the output enable for the
+// DIO.
+#define IOC_IOCFG11_WU_CFG_W 2
+#define IOC_IOCFG11_WU_CFG_M 0x18000000
+#define IOC_IOCFG11_WU_CFG_S 27
+
+// Field: [26:24] IOMODE
+//
+// IO Mode
+// Not applicable for IO configured for AON periph. signals and AUX PORT_ID
+// 0x01-0x08
+// AUX has its own open_source/drain configuration.
+//
+// 0x2: Reserved. Undefined behavior.
+// 0x3: Reserved. Undefined behavior.
+// ENUMs:
+// OPENSRC_INV Open Source
+// Inverted input / output
+// OPENSRC Open Source
+// Normal input / output
+// OPENDR_INV Open Drain
+// Inverted input / output
+// OPENDR Open Drain,
+// Normal input / output
+// INV Inverted input / ouput
+// NORMAL Normal input / output
+#define IOC_IOCFG11_IOMODE_W 3
+#define IOC_IOCFG11_IOMODE_M 0x07000000
+#define IOC_IOCFG11_IOMODE_S 24
+#define IOC_IOCFG11_IOMODE_OPENSRC_INV 0x07000000
+#define IOC_IOCFG11_IOMODE_OPENSRC 0x06000000
+#define IOC_IOCFG11_IOMODE_OPENDR_INV 0x05000000
+#define IOC_IOCFG11_IOMODE_OPENDR 0x04000000
+#define IOC_IOCFG11_IOMODE_INV 0x01000000
+#define IOC_IOCFG11_IOMODE_NORMAL 0x00000000
+
+// Field: [23] IOEV_AON_PROG2_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG2 event
+// 1: Input edge detection asserts AON_PROG2 event
+#define IOC_IOCFG11_IOEV_AON_PROG2_EN 0x00800000
+#define IOC_IOCFG11_IOEV_AON_PROG2_EN_BITN 23
+#define IOC_IOCFG11_IOEV_AON_PROG2_EN_M 0x00800000
+#define IOC_IOCFG11_IOEV_AON_PROG2_EN_S 23
+
+// Field: [22] IOEV_AON_PROG1_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG1 event
+// 1: Input edge detection asserts AON_PROG1 event
+#define IOC_IOCFG11_IOEV_AON_PROG1_EN 0x00400000
+#define IOC_IOCFG11_IOEV_AON_PROG1_EN_BITN 22
+#define IOC_IOCFG11_IOEV_AON_PROG1_EN_M 0x00400000
+#define IOC_IOCFG11_IOEV_AON_PROG1_EN_S 22
+
+// Field: [21] IOEV_AON_PROG0_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG0 event
+// 1: Input edge detection asserts AON_PROG0 event
+#define IOC_IOCFG11_IOEV_AON_PROG0_EN 0x00200000
+#define IOC_IOCFG11_IOEV_AON_PROG0_EN_BITN 21
+#define IOC_IOCFG11_IOEV_AON_PROG0_EN_M 0x00200000
+#define IOC_IOCFG11_IOEV_AON_PROG0_EN_S 21
+
+// Field: [18] EDGE_IRQ_EN
+//
+// 0: No interrupt generation
+// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is
+// enabled)
+#define IOC_IOCFG11_EDGE_IRQ_EN 0x00040000
+#define IOC_IOCFG11_EDGE_IRQ_EN_BITN 18
+#define IOC_IOCFG11_EDGE_IRQ_EN_M 0x00040000
+#define IOC_IOCFG11_EDGE_IRQ_EN_S 18
+
+// Field: [17:16] EDGE_DET
+//
+// Enable generation of edge detection events on this IO
+// ENUMs:
+// BOTH Positive and negative edge detection
+// POS Positive edge detection
+// NEG Negative edge detection
+// NONE No edge detection
+#define IOC_IOCFG11_EDGE_DET_W 2
+#define IOC_IOCFG11_EDGE_DET_M 0x00030000
+#define IOC_IOCFG11_EDGE_DET_S 16
+#define IOC_IOCFG11_EDGE_DET_BOTH 0x00030000
+#define IOC_IOCFG11_EDGE_DET_POS 0x00020000
+#define IOC_IOCFG11_EDGE_DET_NEG 0x00010000
+#define IOC_IOCFG11_EDGE_DET_NONE 0x00000000
+
+// Field: [14:13] PULL_CTL
+//
+// Pull control
+// ENUMs:
+// DIS No pull
+// UP Pull up
+// DWN Pull down
+#define IOC_IOCFG11_PULL_CTL_W 2
+#define IOC_IOCFG11_PULL_CTL_M 0x00006000
+#define IOC_IOCFG11_PULL_CTL_S 13
+#define IOC_IOCFG11_PULL_CTL_DIS 0x00006000
+#define IOC_IOCFG11_PULL_CTL_UP 0x00004000
+#define IOC_IOCFG11_PULL_CTL_DWN 0x00002000
+
+// Field: [12] SLEW_RED
+//
+// 0: Normal slew rate
+// 1: Enables reduced slew rate in output driver.
+#define IOC_IOCFG11_SLEW_RED 0x00001000
+#define IOC_IOCFG11_SLEW_RED_BITN 12
+#define IOC_IOCFG11_SLEW_RED_M 0x00001000
+#define IOC_IOCFG11_SLEW_RED_S 12
+
+// Field: [11:10] IOCURR
+//
+// Selects IO current mode of this IO.
+// ENUMs:
+// 4_8MA Extended-Current (EC) mode: Min 8 mA for double
+// drive strength IOs (min 4 mA for normal IOs)
+// when IOSTR is set to AUTO
+// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set
+// to AUTO
+// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set
+// to AUTO
+#define IOC_IOCFG11_IOCURR_W 2
+#define IOC_IOCFG11_IOCURR_M 0x00000C00
+#define IOC_IOCFG11_IOCURR_S 10
+#define IOC_IOCFG11_IOCURR_4_8MA 0x00000800
+#define IOC_IOCFG11_IOCURR_4MA 0x00000400
+#define IOC_IOCFG11_IOCURR_2MA 0x00000000
+
+// Field: [9:8] IOSTR
+//
+// Select source for drive strength control of this IO.
+// This setting controls the drive strength of the Low-Current (LC) mode.
+// Higher drive strength can be selected in IOCURR
+// ENUMs:
+// MAX Maximum drive strength, controlled by
+// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default
+// values)
+// MED Medium drive strength, controlled by
+// AON_IOC:IOSTRMED (min 2 mA @2.5V with default
+// values)
+// MIN Minimum drive strength, controlled by
+// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default
+// values)
+// AUTO Automatic drive strength, controlled by AON BATMON
+// based on battery voltage. (min 2 mA @VDDS)
+#define IOC_IOCFG11_IOSTR_W 2
+#define IOC_IOCFG11_IOSTR_M 0x00000300
+#define IOC_IOCFG11_IOSTR_S 8
+#define IOC_IOCFG11_IOSTR_MAX 0x00000300
+#define IOC_IOCFG11_IOSTR_MED 0x00000200
+#define IOC_IOCFG11_IOSTR_MIN 0x00000100
+#define IOC_IOCFG11_IOSTR_AUTO 0x00000000
+
+// Field: [7] IOEV_RTC_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert RTC event
+// 1: Input edge detection asserts RTC event
+#define IOC_IOCFG11_IOEV_RTC_EN 0x00000080
+#define IOC_IOCFG11_IOEV_RTC_EN_BITN 7
+#define IOC_IOCFG11_IOEV_RTC_EN_M 0x00000080
+#define IOC_IOCFG11_IOEV_RTC_EN_S 7
+
+// Field: [6] IOEV_MCU_WU_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert MCU_WU event
+// 1: Input edge detection asserts MCU_WU event
+#define IOC_IOCFG11_IOEV_MCU_WU_EN 0x00000040
+#define IOC_IOCFG11_IOEV_MCU_WU_EN_BITN 6
+#define IOC_IOCFG11_IOEV_MCU_WU_EN_M 0x00000040
+#define IOC_IOCFG11_IOEV_MCU_WU_EN_S 6
+
+// Field: [5:0] PORT_ID
+//
+// Selects usage for DIO11
+// ENUMs:
+// RFC_SMI_CL_IN RF Core SMI Command Link In
+// RFC_SMI_CL_OUT RF Core SMI Command Link Out
+// RFC_SMI_DL_IN RF Core SMI Data Link In
+// RFC_SMI_DL_OUT RF Core SMI Data Link Out
+// RFC_GPI1 RF Core Data In 1
+// RFC_GPI0 RF Core Data In 0
+// RFC_GPO3 RF Core Data Out 3
+// RFC_GPO2 RF Core Data Out 2
+// RFC_GPO1 RF Core Data Out 1
+// RFC_GPO0 RF Core Data Out 0
+// RFC_TRC RF Core Trace
+// I2S_MCLK I2S MCLK
+// I2S_BCLK I2S BCLK
+// I2S_WCLK I2S WCLK
+// I2S_AD1 I2S Data 1
+// I2S_AD0 I2S Data 0
+// SSI1_CLK SSI1 CLK
+// SSI1_FSS SSI1 FSS
+// SSI1_TX SSI1 TX
+// SSI1_RX SSI1 RX
+// CPU_SWV CPU SWV
+// PORT_EVENT7 PORT EVENT 7
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT6 PORT EVENT 6
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT5 PORT EVENT 5
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT4 PORT EVENT 4
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT3 PORT EVENT 3
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT2 PORT EVENT 2
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT1 PORT EVENT 1
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT0 PORT EVENT 0
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// UART1_RTS UART1 RTS
+// UART1_CTS UART1 CTS
+// UART1_TX UART1 TX
+// UART1_RX UART1 RX
+// UART0_RTS UART0 RTS
+// UART0_CTS UART0 CTS
+// UART0_TX UART0 TX
+// UART0_RX UART0 RX
+// I2C_MSSCL I2C Clock
+// I2C_MSSDA I2C Data
+// SSI0_CLK SSI0 CLK
+// SSI0_FSS SSI0 FSS
+// SSI0_TX SSI0 TX
+// SSI0_RX SSI0 RX
+// AUX_IO AUX IO
+// AON_CLK32K AON 32 KHz clock (SCLK_LF)
+// GPIO General Purpose IO
+#define IOC_IOCFG11_PORT_ID_W 6
+#define IOC_IOCFG11_PORT_ID_M 0x0000003F
+#define IOC_IOCFG11_PORT_ID_S 0
+#define IOC_IOCFG11_PORT_ID_RFC_SMI_CL_IN 0x00000038
+#define IOC_IOCFG11_PORT_ID_RFC_SMI_CL_OUT 0x00000037
+#define IOC_IOCFG11_PORT_ID_RFC_SMI_DL_IN 0x00000036
+#define IOC_IOCFG11_PORT_ID_RFC_SMI_DL_OUT 0x00000035
+#define IOC_IOCFG11_PORT_ID_RFC_GPI1 0x00000034
+#define IOC_IOCFG11_PORT_ID_RFC_GPI0 0x00000033
+#define IOC_IOCFG11_PORT_ID_RFC_GPO3 0x00000032
+#define IOC_IOCFG11_PORT_ID_RFC_GPO2 0x00000031
+#define IOC_IOCFG11_PORT_ID_RFC_GPO1 0x00000030
+#define IOC_IOCFG11_PORT_ID_RFC_GPO0 0x0000002F
+#define IOC_IOCFG11_PORT_ID_RFC_TRC 0x0000002E
+#define IOC_IOCFG11_PORT_ID_I2S_MCLK 0x00000029
+#define IOC_IOCFG11_PORT_ID_I2S_BCLK 0x00000028
+#define IOC_IOCFG11_PORT_ID_I2S_WCLK 0x00000027
+#define IOC_IOCFG11_PORT_ID_I2S_AD1 0x00000026
+#define IOC_IOCFG11_PORT_ID_I2S_AD0 0x00000025
+#define IOC_IOCFG11_PORT_ID_SSI1_CLK 0x00000024
+#define IOC_IOCFG11_PORT_ID_SSI1_FSS 0x00000023
+#define IOC_IOCFG11_PORT_ID_SSI1_TX 0x00000022
+#define IOC_IOCFG11_PORT_ID_SSI1_RX 0x00000021
+#define IOC_IOCFG11_PORT_ID_CPU_SWV 0x00000020
+#define IOC_IOCFG11_PORT_ID_PORT_EVENT7 0x0000001E
+#define IOC_IOCFG11_PORT_ID_PORT_EVENT6 0x0000001D
+#define IOC_IOCFG11_PORT_ID_PORT_EVENT5 0x0000001C
+#define IOC_IOCFG11_PORT_ID_PORT_EVENT4 0x0000001B
+#define IOC_IOCFG11_PORT_ID_PORT_EVENT3 0x0000001A
+#define IOC_IOCFG11_PORT_ID_PORT_EVENT2 0x00000019
+#define IOC_IOCFG11_PORT_ID_PORT_EVENT1 0x00000018
+#define IOC_IOCFG11_PORT_ID_PORT_EVENT0 0x00000017
+#define IOC_IOCFG11_PORT_ID_UART1_RTS 0x00000016
+#define IOC_IOCFG11_PORT_ID_UART1_CTS 0x00000015
+#define IOC_IOCFG11_PORT_ID_UART1_TX 0x00000014
+#define IOC_IOCFG11_PORT_ID_UART1_RX 0x00000013
+#define IOC_IOCFG11_PORT_ID_UART0_RTS 0x00000012
+#define IOC_IOCFG11_PORT_ID_UART0_CTS 0x00000011
+#define IOC_IOCFG11_PORT_ID_UART0_TX 0x00000010
+#define IOC_IOCFG11_PORT_ID_UART0_RX 0x0000000F
+#define IOC_IOCFG11_PORT_ID_I2C_MSSCL 0x0000000E
+#define IOC_IOCFG11_PORT_ID_I2C_MSSDA 0x0000000D
+#define IOC_IOCFG11_PORT_ID_SSI0_CLK 0x0000000C
+#define IOC_IOCFG11_PORT_ID_SSI0_FSS 0x0000000B
+#define IOC_IOCFG11_PORT_ID_SSI0_TX 0x0000000A
+#define IOC_IOCFG11_PORT_ID_SSI0_RX 0x00000009
+#define IOC_IOCFG11_PORT_ID_AUX_IO 0x00000008
+#define IOC_IOCFG11_PORT_ID_AON_CLK32K 0x00000007
+#define IOC_IOCFG11_PORT_ID_GPIO 0x00000000
+
+//*****************************************************************************
+//
+// Register: IOC_O_IOCFG12
+//
+//*****************************************************************************
+// Field: [30] HYST_EN
+//
+// 0: Input hysteresis disable
+// 1: Input hysteresis enable
+#define IOC_IOCFG12_HYST_EN 0x40000000
+#define IOC_IOCFG12_HYST_EN_BITN 30
+#define IOC_IOCFG12_HYST_EN_M 0x40000000
+#define IOC_IOCFG12_HYST_EN_S 30
+
+// Field: [29] IE
+//
+// 0: Input disabled
+// 1: Input enabled
+//
+// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be
+// ignored.
+#define IOC_IOCFG12_IE 0x20000000
+#define IOC_IOCFG12_IE_BITN 29
+#define IOC_IOCFG12_IE_M 0x20000000
+#define IOC_IOCFG12_IE_S 29
+
+// Field: [28:27] WU_CFG
+//
+// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or
+// >0x08:
+//
+// 00: No wake-up
+// 01: No wake-up
+// 10: Wakes up from shutdown if this pad is going low.
+// 11: Wakes up from shutdown if this pad is going high.
+//
+// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08,
+// this register only sets wakeup enable or not.
+//
+// 00, 01: Wakeup disabled
+// 10, 11: Wakeup enabled
+//
+// Polarity is controlled from AON registers.
+//
+// Note:When the MSB is set, the IOC will deactivate the output enable for the
+// DIO.
+#define IOC_IOCFG12_WU_CFG_W 2
+#define IOC_IOCFG12_WU_CFG_M 0x18000000
+#define IOC_IOCFG12_WU_CFG_S 27
+
+// Field: [26:24] IOMODE
+//
+// IO Mode
+// Not applicable for IO configured for AON periph. signals and AUX PORT_ID
+// 0x01-0x08
+// AUX has its own open_source/drain configuration.
+//
+// 0x2: Reserved. Undefined behavior.
+// 0x3: Reserved. Undefined behavior.
+// ENUMs:
+// OPENSRC_INV Open Source
+// Inverted input / output
+// OPENSRC Open Source
+// Normal input / output
+// OPENDR_INV Open Drain
+// Inverted input / output
+// OPENDR Open Drain,
+// Normal input / output
+// INV Inverted input / ouput
+// NORMAL Normal input / output
+#define IOC_IOCFG12_IOMODE_W 3
+#define IOC_IOCFG12_IOMODE_M 0x07000000
+#define IOC_IOCFG12_IOMODE_S 24
+#define IOC_IOCFG12_IOMODE_OPENSRC_INV 0x07000000
+#define IOC_IOCFG12_IOMODE_OPENSRC 0x06000000
+#define IOC_IOCFG12_IOMODE_OPENDR_INV 0x05000000
+#define IOC_IOCFG12_IOMODE_OPENDR 0x04000000
+#define IOC_IOCFG12_IOMODE_INV 0x01000000
+#define IOC_IOCFG12_IOMODE_NORMAL 0x00000000
+
+// Field: [23] IOEV_AON_PROG2_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG2 event
+// 1: Input edge detection asserts AON_PROG2 event
+#define IOC_IOCFG12_IOEV_AON_PROG2_EN 0x00800000
+#define IOC_IOCFG12_IOEV_AON_PROG2_EN_BITN 23
+#define IOC_IOCFG12_IOEV_AON_PROG2_EN_M 0x00800000
+#define IOC_IOCFG12_IOEV_AON_PROG2_EN_S 23
+
+// Field: [22] IOEV_AON_PROG1_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG1 event
+// 1: Input edge detection asserts AON_PROG1 event
+#define IOC_IOCFG12_IOEV_AON_PROG1_EN 0x00400000
+#define IOC_IOCFG12_IOEV_AON_PROG1_EN_BITN 22
+#define IOC_IOCFG12_IOEV_AON_PROG1_EN_M 0x00400000
+#define IOC_IOCFG12_IOEV_AON_PROG1_EN_S 22
+
+// Field: [21] IOEV_AON_PROG0_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG0 event
+// 1: Input edge detection asserts AON_PROG0 event
+#define IOC_IOCFG12_IOEV_AON_PROG0_EN 0x00200000
+#define IOC_IOCFG12_IOEV_AON_PROG0_EN_BITN 21
+#define IOC_IOCFG12_IOEV_AON_PROG0_EN_M 0x00200000
+#define IOC_IOCFG12_IOEV_AON_PROG0_EN_S 21
+
+// Field: [18] EDGE_IRQ_EN
+//
+// 0: No interrupt generation
+// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is
+// enabled)
+#define IOC_IOCFG12_EDGE_IRQ_EN 0x00040000
+#define IOC_IOCFG12_EDGE_IRQ_EN_BITN 18
+#define IOC_IOCFG12_EDGE_IRQ_EN_M 0x00040000
+#define IOC_IOCFG12_EDGE_IRQ_EN_S 18
+
+// Field: [17:16] EDGE_DET
+//
+// Enable generation of edge detection events on this IO
+// ENUMs:
+// BOTH Positive and negative edge detection
+// POS Positive edge detection
+// NEG Negative edge detection
+// NONE No edge detection
+#define IOC_IOCFG12_EDGE_DET_W 2
+#define IOC_IOCFG12_EDGE_DET_M 0x00030000
+#define IOC_IOCFG12_EDGE_DET_S 16
+#define IOC_IOCFG12_EDGE_DET_BOTH 0x00030000
+#define IOC_IOCFG12_EDGE_DET_POS 0x00020000
+#define IOC_IOCFG12_EDGE_DET_NEG 0x00010000
+#define IOC_IOCFG12_EDGE_DET_NONE 0x00000000
+
+// Field: [14:13] PULL_CTL
+//
+// Pull control
+// ENUMs:
+// DIS No pull
+// UP Pull up
+// DWN Pull down
+#define IOC_IOCFG12_PULL_CTL_W 2
+#define IOC_IOCFG12_PULL_CTL_M 0x00006000
+#define IOC_IOCFG12_PULL_CTL_S 13
+#define IOC_IOCFG12_PULL_CTL_DIS 0x00006000
+#define IOC_IOCFG12_PULL_CTL_UP 0x00004000
+#define IOC_IOCFG12_PULL_CTL_DWN 0x00002000
+
+// Field: [12] SLEW_RED
+//
+// 0: Normal slew rate
+// 1: Enables reduced slew rate in output driver.
+#define IOC_IOCFG12_SLEW_RED 0x00001000
+#define IOC_IOCFG12_SLEW_RED_BITN 12
+#define IOC_IOCFG12_SLEW_RED_M 0x00001000
+#define IOC_IOCFG12_SLEW_RED_S 12
+
+// Field: [11:10] IOCURR
+//
+// Selects IO current mode of this IO.
+// ENUMs:
+// 4_8MA Extended-Current (EC) mode: Min 8 mA for double
+// drive strength IOs (min 4 mA for normal IOs)
+// when IOSTR is set to AUTO
+// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set
+// to AUTO
+// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set
+// to AUTO
+#define IOC_IOCFG12_IOCURR_W 2
+#define IOC_IOCFG12_IOCURR_M 0x00000C00
+#define IOC_IOCFG12_IOCURR_S 10
+#define IOC_IOCFG12_IOCURR_4_8MA 0x00000800
+#define IOC_IOCFG12_IOCURR_4MA 0x00000400
+#define IOC_IOCFG12_IOCURR_2MA 0x00000000
+
+// Field: [9:8] IOSTR
+//
+// Select source for drive strength control of this IO.
+// This setting controls the drive strength of the Low-Current (LC) mode.
+// Higher drive strength can be selected in IOCURR
+// ENUMs:
+// MAX Maximum drive strength, controlled by
+// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default
+// values)
+// MED Medium drive strength, controlled by
+// AON_IOC:IOSTRMED (min 2 mA @2.5V with default
+// values)
+// MIN Minimum drive strength, controlled by
+// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default
+// values)
+// AUTO Automatic drive strength, controlled by AON BATMON
+// based on battery voltage. (min 2 mA @VDDS)
+#define IOC_IOCFG12_IOSTR_W 2
+#define IOC_IOCFG12_IOSTR_M 0x00000300
+#define IOC_IOCFG12_IOSTR_S 8
+#define IOC_IOCFG12_IOSTR_MAX 0x00000300
+#define IOC_IOCFG12_IOSTR_MED 0x00000200
+#define IOC_IOCFG12_IOSTR_MIN 0x00000100
+#define IOC_IOCFG12_IOSTR_AUTO 0x00000000
+
+// Field: [7] IOEV_RTC_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert RTC event
+// 1: Input edge detection asserts RTC event
+#define IOC_IOCFG12_IOEV_RTC_EN 0x00000080
+#define IOC_IOCFG12_IOEV_RTC_EN_BITN 7
+#define IOC_IOCFG12_IOEV_RTC_EN_M 0x00000080
+#define IOC_IOCFG12_IOEV_RTC_EN_S 7
+
+// Field: [6] IOEV_MCU_WU_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert MCU_WU event
+// 1: Input edge detection asserts MCU_WU event
+#define IOC_IOCFG12_IOEV_MCU_WU_EN 0x00000040
+#define IOC_IOCFG12_IOEV_MCU_WU_EN_BITN 6
+#define IOC_IOCFG12_IOEV_MCU_WU_EN_M 0x00000040
+#define IOC_IOCFG12_IOEV_MCU_WU_EN_S 6
+
+// Field: [5:0] PORT_ID
+//
+// Selects usage for DIO12
+// ENUMs:
+// RFC_SMI_CL_IN RF Core SMI Command Link In
+// RFC_SMI_CL_OUT RF Core SMI Command Link Out
+// RFC_SMI_DL_IN RF Core SMI Data Link In
+// RFC_SMI_DL_OUT RF Core SMI Data Link Out
+// RFC_GPI1 RF Core Data In 1
+// RFC_GPI0 RF Core Data In 0
+// RFC_GPO3 RF Core Data Out 3
+// RFC_GPO2 RF Core Data Out 2
+// RFC_GPO1 RF Core Data Out 1
+// RFC_GPO0 RF Core Data Out 0
+// RFC_TRC RF Core Trace
+// I2S_MCLK I2S MCLK
+// I2S_BCLK I2S BCLK
+// I2S_WCLK I2S WCLK
+// I2S_AD1 I2S Data 1
+// I2S_AD0 I2S Data 0
+// SSI1_CLK SSI1 CLK
+// SSI1_FSS SSI1 FSS
+// SSI1_TX SSI1 TX
+// SSI1_RX SSI1 RX
+// CPU_SWV CPU SWV
+// PORT_EVENT7 PORT EVENT 7
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT6 PORT EVENT 6
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT5 PORT EVENT 5
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT4 PORT EVENT 4
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT3 PORT EVENT 3
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT2 PORT EVENT 2
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT1 PORT EVENT 1
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT0 PORT EVENT 0
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// UART1_RTS UART1 RTS
+// UART1_CTS UART1 CTS
+// UART1_TX UART1 TX
+// UART1_RX UART1 RX
+// UART0_RTS UART0 RTS
+// UART0_CTS UART0 CTS
+// UART0_TX UART0 TX
+// UART0_RX UART0 RX
+// I2C_MSSCL I2C Clock
+// I2C_MSSDA I2C Data
+// SSI0_CLK SSI0 CLK
+// SSI0_FSS SSI0 FSS
+// SSI0_TX SSI0 TX
+// SSI0_RX SSI0 RX
+// AUX_IO AUX IO
+// AON_CLK32K AON 32 KHz clock (SCLK_LF)
+// GPIO General Purpose IO
+#define IOC_IOCFG12_PORT_ID_W 6
+#define IOC_IOCFG12_PORT_ID_M 0x0000003F
+#define IOC_IOCFG12_PORT_ID_S 0
+#define IOC_IOCFG12_PORT_ID_RFC_SMI_CL_IN 0x00000038
+#define IOC_IOCFG12_PORT_ID_RFC_SMI_CL_OUT 0x00000037
+#define IOC_IOCFG12_PORT_ID_RFC_SMI_DL_IN 0x00000036
+#define IOC_IOCFG12_PORT_ID_RFC_SMI_DL_OUT 0x00000035
+#define IOC_IOCFG12_PORT_ID_RFC_GPI1 0x00000034
+#define IOC_IOCFG12_PORT_ID_RFC_GPI0 0x00000033
+#define IOC_IOCFG12_PORT_ID_RFC_GPO3 0x00000032
+#define IOC_IOCFG12_PORT_ID_RFC_GPO2 0x00000031
+#define IOC_IOCFG12_PORT_ID_RFC_GPO1 0x00000030
+#define IOC_IOCFG12_PORT_ID_RFC_GPO0 0x0000002F
+#define IOC_IOCFG12_PORT_ID_RFC_TRC 0x0000002E
+#define IOC_IOCFG12_PORT_ID_I2S_MCLK 0x00000029
+#define IOC_IOCFG12_PORT_ID_I2S_BCLK 0x00000028
+#define IOC_IOCFG12_PORT_ID_I2S_WCLK 0x00000027
+#define IOC_IOCFG12_PORT_ID_I2S_AD1 0x00000026
+#define IOC_IOCFG12_PORT_ID_I2S_AD0 0x00000025
+#define IOC_IOCFG12_PORT_ID_SSI1_CLK 0x00000024
+#define IOC_IOCFG12_PORT_ID_SSI1_FSS 0x00000023
+#define IOC_IOCFG12_PORT_ID_SSI1_TX 0x00000022
+#define IOC_IOCFG12_PORT_ID_SSI1_RX 0x00000021
+#define IOC_IOCFG12_PORT_ID_CPU_SWV 0x00000020
+#define IOC_IOCFG12_PORT_ID_PORT_EVENT7 0x0000001E
+#define IOC_IOCFG12_PORT_ID_PORT_EVENT6 0x0000001D
+#define IOC_IOCFG12_PORT_ID_PORT_EVENT5 0x0000001C
+#define IOC_IOCFG12_PORT_ID_PORT_EVENT4 0x0000001B
+#define IOC_IOCFG12_PORT_ID_PORT_EVENT3 0x0000001A
+#define IOC_IOCFG12_PORT_ID_PORT_EVENT2 0x00000019
+#define IOC_IOCFG12_PORT_ID_PORT_EVENT1 0x00000018
+#define IOC_IOCFG12_PORT_ID_PORT_EVENT0 0x00000017
+#define IOC_IOCFG12_PORT_ID_UART1_RTS 0x00000016
+#define IOC_IOCFG12_PORT_ID_UART1_CTS 0x00000015
+#define IOC_IOCFG12_PORT_ID_UART1_TX 0x00000014
+#define IOC_IOCFG12_PORT_ID_UART1_RX 0x00000013
+#define IOC_IOCFG12_PORT_ID_UART0_RTS 0x00000012
+#define IOC_IOCFG12_PORT_ID_UART0_CTS 0x00000011
+#define IOC_IOCFG12_PORT_ID_UART0_TX 0x00000010
+#define IOC_IOCFG12_PORT_ID_UART0_RX 0x0000000F
+#define IOC_IOCFG12_PORT_ID_I2C_MSSCL 0x0000000E
+#define IOC_IOCFG12_PORT_ID_I2C_MSSDA 0x0000000D
+#define IOC_IOCFG12_PORT_ID_SSI0_CLK 0x0000000C
+#define IOC_IOCFG12_PORT_ID_SSI0_FSS 0x0000000B
+#define IOC_IOCFG12_PORT_ID_SSI0_TX 0x0000000A
+#define IOC_IOCFG12_PORT_ID_SSI0_RX 0x00000009
+#define IOC_IOCFG12_PORT_ID_AUX_IO 0x00000008
+#define IOC_IOCFG12_PORT_ID_AON_CLK32K 0x00000007
+#define IOC_IOCFG12_PORT_ID_GPIO 0x00000000
+
+//*****************************************************************************
+//
+// Register: IOC_O_IOCFG13
+//
+//*****************************************************************************
+// Field: [30] HYST_EN
+//
+// 0: Input hysteresis disable
+// 1: Input hysteresis enable
+#define IOC_IOCFG13_HYST_EN 0x40000000
+#define IOC_IOCFG13_HYST_EN_BITN 30
+#define IOC_IOCFG13_HYST_EN_M 0x40000000
+#define IOC_IOCFG13_HYST_EN_S 30
+
+// Field: [29] IE
+//
+// 0: Input disabled
+// 1: Input enabled
+//
+// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be
+// ignored.
+#define IOC_IOCFG13_IE 0x20000000
+#define IOC_IOCFG13_IE_BITN 29
+#define IOC_IOCFG13_IE_M 0x20000000
+#define IOC_IOCFG13_IE_S 29
+
+// Field: [28:27] WU_CFG
+//
+// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or
+// >0x08:
+//
+// 00: No wake-up
+// 01: No wake-up
+// 10: Wakes up from shutdown if this pad is going low.
+// 11: Wakes up from shutdown if this pad is going high.
+//
+// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08,
+// this register only sets wakeup enable or not.
+//
+// 00, 01: Wakeup disabled
+// 10, 11: Wakeup enabled
+//
+// Polarity is controlled from AON registers.
+//
+// Note:When the MSB is set, the IOC will deactivate the output enable for the
+// DIO.
+#define IOC_IOCFG13_WU_CFG_W 2
+#define IOC_IOCFG13_WU_CFG_M 0x18000000
+#define IOC_IOCFG13_WU_CFG_S 27
+
+// Field: [26:24] IOMODE
+//
+// IO Mode
+// Not applicable for IO configured for AON periph. signals and AUX PORT_ID
+// 0x01-0x08
+// AUX has its own open_source/drain configuration.
+//
+// 0x2: Reserved. Undefined behavior.
+// 0x3: Reserved. Undefined behavior.
+// ENUMs:
+// OPENSRC_INV Open Source
+// Inverted input / output
+// OPENSRC Open Source
+// Normal input / output
+// OPENDR_INV Open Drain
+// Inverted input / output
+// OPENDR Open Drain,
+// Normal input / output
+// INV Inverted input / ouput
+// NORMAL Normal input / output
+#define IOC_IOCFG13_IOMODE_W 3
+#define IOC_IOCFG13_IOMODE_M 0x07000000
+#define IOC_IOCFG13_IOMODE_S 24
+#define IOC_IOCFG13_IOMODE_OPENSRC_INV 0x07000000
+#define IOC_IOCFG13_IOMODE_OPENSRC 0x06000000
+#define IOC_IOCFG13_IOMODE_OPENDR_INV 0x05000000
+#define IOC_IOCFG13_IOMODE_OPENDR 0x04000000
+#define IOC_IOCFG13_IOMODE_INV 0x01000000
+#define IOC_IOCFG13_IOMODE_NORMAL 0x00000000
+
+// Field: [23] IOEV_AON_PROG2_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG2 event
+// 1: Input edge detection asserts AON_PROG2 event
+#define IOC_IOCFG13_IOEV_AON_PROG2_EN 0x00800000
+#define IOC_IOCFG13_IOEV_AON_PROG2_EN_BITN 23
+#define IOC_IOCFG13_IOEV_AON_PROG2_EN_M 0x00800000
+#define IOC_IOCFG13_IOEV_AON_PROG2_EN_S 23
+
+// Field: [22] IOEV_AON_PROG1_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG1 event
+// 1: Input edge detection asserts AON_PROG1 event
+#define IOC_IOCFG13_IOEV_AON_PROG1_EN 0x00400000
+#define IOC_IOCFG13_IOEV_AON_PROG1_EN_BITN 22
+#define IOC_IOCFG13_IOEV_AON_PROG1_EN_M 0x00400000
+#define IOC_IOCFG13_IOEV_AON_PROG1_EN_S 22
+
+// Field: [21] IOEV_AON_PROG0_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG0 event
+// 1: Input edge detection asserts AON_PROG0 event
+#define IOC_IOCFG13_IOEV_AON_PROG0_EN 0x00200000
+#define IOC_IOCFG13_IOEV_AON_PROG0_EN_BITN 21
+#define IOC_IOCFG13_IOEV_AON_PROG0_EN_M 0x00200000
+#define IOC_IOCFG13_IOEV_AON_PROG0_EN_S 21
+
+// Field: [18] EDGE_IRQ_EN
+//
+// 0: No interrupt generation
+// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is
+// enabled)
+#define IOC_IOCFG13_EDGE_IRQ_EN 0x00040000
+#define IOC_IOCFG13_EDGE_IRQ_EN_BITN 18
+#define IOC_IOCFG13_EDGE_IRQ_EN_M 0x00040000
+#define IOC_IOCFG13_EDGE_IRQ_EN_S 18
+
+// Field: [17:16] EDGE_DET
+//
+// Enable generation of edge detection events on this IO
+// ENUMs:
+// BOTH Positive and negative edge detection
+// POS Positive edge detection
+// NEG Negative edge detection
+// NONE No edge detection
+#define IOC_IOCFG13_EDGE_DET_W 2
+#define IOC_IOCFG13_EDGE_DET_M 0x00030000
+#define IOC_IOCFG13_EDGE_DET_S 16
+#define IOC_IOCFG13_EDGE_DET_BOTH 0x00030000
+#define IOC_IOCFG13_EDGE_DET_POS 0x00020000
+#define IOC_IOCFG13_EDGE_DET_NEG 0x00010000
+#define IOC_IOCFG13_EDGE_DET_NONE 0x00000000
+
+// Field: [14:13] PULL_CTL
+//
+// Pull control
+// ENUMs:
+// DIS No pull
+// UP Pull up
+// DWN Pull down
+#define IOC_IOCFG13_PULL_CTL_W 2
+#define IOC_IOCFG13_PULL_CTL_M 0x00006000
+#define IOC_IOCFG13_PULL_CTL_S 13
+#define IOC_IOCFG13_PULL_CTL_DIS 0x00006000
+#define IOC_IOCFG13_PULL_CTL_UP 0x00004000
+#define IOC_IOCFG13_PULL_CTL_DWN 0x00002000
+
+// Field: [12] SLEW_RED
+//
+// 0: Normal slew rate
+// 1: Enables reduced slew rate in output driver.
+#define IOC_IOCFG13_SLEW_RED 0x00001000
+#define IOC_IOCFG13_SLEW_RED_BITN 12
+#define IOC_IOCFG13_SLEW_RED_M 0x00001000
+#define IOC_IOCFG13_SLEW_RED_S 12
+
+// Field: [11:10] IOCURR
+//
+// Selects IO current mode of this IO.
+// ENUMs:
+// 4_8MA Extended-Current (EC) mode: Min 8 mA for double
+// drive strength IOs (min 4 mA for normal IOs)
+// when IOSTR is set to AUTO
+// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set
+// to AUTO
+// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set
+// to AUTO
+#define IOC_IOCFG13_IOCURR_W 2
+#define IOC_IOCFG13_IOCURR_M 0x00000C00
+#define IOC_IOCFG13_IOCURR_S 10
+#define IOC_IOCFG13_IOCURR_4_8MA 0x00000800
+#define IOC_IOCFG13_IOCURR_4MA 0x00000400
+#define IOC_IOCFG13_IOCURR_2MA 0x00000000
+
+// Field: [9:8] IOSTR
+//
+// Select source for drive strength control of this IO.
+// This setting controls the drive strength of the Low-Current (LC) mode.
+// Higher drive strength can be selected in IOCURR
+// ENUMs:
+// MAX Maximum drive strength, controlled by
+// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default
+// values)
+// MED Medium drive strength, controlled by
+// AON_IOC:IOSTRMED (min 2 mA @2.5V with default
+// values)
+// MIN Minimum drive strength, controlled by
+// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default
+// values)
+// AUTO Automatic drive strength, controlled by AON BATMON
+// based on battery voltage. (min 2 mA @VDDS)
+#define IOC_IOCFG13_IOSTR_W 2
+#define IOC_IOCFG13_IOSTR_M 0x00000300
+#define IOC_IOCFG13_IOSTR_S 8
+#define IOC_IOCFG13_IOSTR_MAX 0x00000300
+#define IOC_IOCFG13_IOSTR_MED 0x00000200
+#define IOC_IOCFG13_IOSTR_MIN 0x00000100
+#define IOC_IOCFG13_IOSTR_AUTO 0x00000000
+
+// Field: [7] IOEV_RTC_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert RTC event
+// 1: Input edge detection asserts RTC event
+#define IOC_IOCFG13_IOEV_RTC_EN 0x00000080
+#define IOC_IOCFG13_IOEV_RTC_EN_BITN 7
+#define IOC_IOCFG13_IOEV_RTC_EN_M 0x00000080
+#define IOC_IOCFG13_IOEV_RTC_EN_S 7
+
+// Field: [6] IOEV_MCU_WU_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert MCU_WU event
+// 1: Input edge detection asserts MCU_WU event
+#define IOC_IOCFG13_IOEV_MCU_WU_EN 0x00000040
+#define IOC_IOCFG13_IOEV_MCU_WU_EN_BITN 6
+#define IOC_IOCFG13_IOEV_MCU_WU_EN_M 0x00000040
+#define IOC_IOCFG13_IOEV_MCU_WU_EN_S 6
+
+// Field: [5:0] PORT_ID
+//
+// Selects usage for DIO13
+// ENUMs:
+// RFC_SMI_CL_IN RF Core SMI Command Link In
+// RFC_SMI_CL_OUT RF Core SMI Command Link Out
+// RFC_SMI_DL_IN RF Core SMI Data Link In
+// RFC_SMI_DL_OUT RF Core SMI Data Link Out
+// RFC_GPI1 RF Core Data In 1
+// RFC_GPI0 RF Core Data In 0
+// RFC_GPO3 RF Core Data Out 3
+// RFC_GPO2 RF Core Data Out 2
+// RFC_GPO1 RF Core Data Out 1
+// RFC_GPO0 RF Core Data Out 0
+// RFC_TRC RF Core Trace
+// I2S_MCLK I2S MCLK
+// I2S_BCLK I2S BCLK
+// I2S_WCLK I2S WCLK
+// I2S_AD1 I2S Data 1
+// I2S_AD0 I2S Data 0
+// SSI1_CLK SSI1 CLK
+// SSI1_FSS SSI1 FSS
+// SSI1_TX SSI1 TX
+// SSI1_RX SSI1 RX
+// CPU_SWV CPU SWV
+// PORT_EVENT7 PORT EVENT 7
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT6 PORT EVENT 6
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT5 PORT EVENT 5
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT4 PORT EVENT 4
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT3 PORT EVENT 3
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT2 PORT EVENT 2
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT1 PORT EVENT 1
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT0 PORT EVENT 0
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// UART1_RTS UART1 RTS
+// UART1_CTS UART1 CTS
+// UART1_TX UART1 TX
+// UART1_RX UART1 RX
+// UART0_RTS UART0 RTS
+// UART0_CTS UART0 CTS
+// UART0_TX UART0 TX
+// UART0_RX UART0 RX
+// I2C_MSSCL I2C Clock
+// I2C_MSSDA I2C Data
+// SSI0_CLK SSI0 CLK
+// SSI0_FSS SSI0 FSS
+// SSI0_TX SSI0 TX
+// SSI0_RX SSI0 RX
+// AUX_IO AUX IO
+// AON_CLK32K AON 32 KHz clock (SCLK_LF)
+// GPIO General Purpose IO
+#define IOC_IOCFG13_PORT_ID_W 6
+#define IOC_IOCFG13_PORT_ID_M 0x0000003F
+#define IOC_IOCFG13_PORT_ID_S 0
+#define IOC_IOCFG13_PORT_ID_RFC_SMI_CL_IN 0x00000038
+#define IOC_IOCFG13_PORT_ID_RFC_SMI_CL_OUT 0x00000037
+#define IOC_IOCFG13_PORT_ID_RFC_SMI_DL_IN 0x00000036
+#define IOC_IOCFG13_PORT_ID_RFC_SMI_DL_OUT 0x00000035
+#define IOC_IOCFG13_PORT_ID_RFC_GPI1 0x00000034
+#define IOC_IOCFG13_PORT_ID_RFC_GPI0 0x00000033
+#define IOC_IOCFG13_PORT_ID_RFC_GPO3 0x00000032
+#define IOC_IOCFG13_PORT_ID_RFC_GPO2 0x00000031
+#define IOC_IOCFG13_PORT_ID_RFC_GPO1 0x00000030
+#define IOC_IOCFG13_PORT_ID_RFC_GPO0 0x0000002F
+#define IOC_IOCFG13_PORT_ID_RFC_TRC 0x0000002E
+#define IOC_IOCFG13_PORT_ID_I2S_MCLK 0x00000029
+#define IOC_IOCFG13_PORT_ID_I2S_BCLK 0x00000028
+#define IOC_IOCFG13_PORT_ID_I2S_WCLK 0x00000027
+#define IOC_IOCFG13_PORT_ID_I2S_AD1 0x00000026
+#define IOC_IOCFG13_PORT_ID_I2S_AD0 0x00000025
+#define IOC_IOCFG13_PORT_ID_SSI1_CLK 0x00000024
+#define IOC_IOCFG13_PORT_ID_SSI1_FSS 0x00000023
+#define IOC_IOCFG13_PORT_ID_SSI1_TX 0x00000022
+#define IOC_IOCFG13_PORT_ID_SSI1_RX 0x00000021
+#define IOC_IOCFG13_PORT_ID_CPU_SWV 0x00000020
+#define IOC_IOCFG13_PORT_ID_PORT_EVENT7 0x0000001E
+#define IOC_IOCFG13_PORT_ID_PORT_EVENT6 0x0000001D
+#define IOC_IOCFG13_PORT_ID_PORT_EVENT5 0x0000001C
+#define IOC_IOCFG13_PORT_ID_PORT_EVENT4 0x0000001B
+#define IOC_IOCFG13_PORT_ID_PORT_EVENT3 0x0000001A
+#define IOC_IOCFG13_PORT_ID_PORT_EVENT2 0x00000019
+#define IOC_IOCFG13_PORT_ID_PORT_EVENT1 0x00000018
+#define IOC_IOCFG13_PORT_ID_PORT_EVENT0 0x00000017
+#define IOC_IOCFG13_PORT_ID_UART1_RTS 0x00000016
+#define IOC_IOCFG13_PORT_ID_UART1_CTS 0x00000015
+#define IOC_IOCFG13_PORT_ID_UART1_TX 0x00000014
+#define IOC_IOCFG13_PORT_ID_UART1_RX 0x00000013
+#define IOC_IOCFG13_PORT_ID_UART0_RTS 0x00000012
+#define IOC_IOCFG13_PORT_ID_UART0_CTS 0x00000011
+#define IOC_IOCFG13_PORT_ID_UART0_TX 0x00000010
+#define IOC_IOCFG13_PORT_ID_UART0_RX 0x0000000F
+#define IOC_IOCFG13_PORT_ID_I2C_MSSCL 0x0000000E
+#define IOC_IOCFG13_PORT_ID_I2C_MSSDA 0x0000000D
+#define IOC_IOCFG13_PORT_ID_SSI0_CLK 0x0000000C
+#define IOC_IOCFG13_PORT_ID_SSI0_FSS 0x0000000B
+#define IOC_IOCFG13_PORT_ID_SSI0_TX 0x0000000A
+#define IOC_IOCFG13_PORT_ID_SSI0_RX 0x00000009
+#define IOC_IOCFG13_PORT_ID_AUX_IO 0x00000008
+#define IOC_IOCFG13_PORT_ID_AON_CLK32K 0x00000007
+#define IOC_IOCFG13_PORT_ID_GPIO 0x00000000
+
+//*****************************************************************************
+//
+// Register: IOC_O_IOCFG14
+//
+//*****************************************************************************
+// Field: [30] HYST_EN
+//
+// 0: Input hysteresis disable
+// 1: Input hysteresis enable
+#define IOC_IOCFG14_HYST_EN 0x40000000
+#define IOC_IOCFG14_HYST_EN_BITN 30
+#define IOC_IOCFG14_HYST_EN_M 0x40000000
+#define IOC_IOCFG14_HYST_EN_S 30
+
+// Field: [29] IE
+//
+// 0: Input disabled
+// 1: Input enabled
+//
+// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be
+// ignored.
+#define IOC_IOCFG14_IE 0x20000000
+#define IOC_IOCFG14_IE_BITN 29
+#define IOC_IOCFG14_IE_M 0x20000000
+#define IOC_IOCFG14_IE_S 29
+
+// Field: [28:27] WU_CFG
+//
+// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or
+// >0x08:
+//
+// 00: No wake-up
+// 01: No wake-up
+// 10: Wakes up from shutdown if this pad is going low.
+// 11: Wakes up from shutdown if this pad is going high.
+//
+// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08,
+// this register only sets wakeup enable or not.
+//
+// 00, 01: Wakeup disabled
+// 10, 11: Wakeup enabled
+//
+// Polarity is controlled from AON registers.
+//
+// Note:When the MSB is set, the IOC will deactivate the output enable for the
+// DIO.
+#define IOC_IOCFG14_WU_CFG_W 2
+#define IOC_IOCFG14_WU_CFG_M 0x18000000
+#define IOC_IOCFG14_WU_CFG_S 27
+
+// Field: [26:24] IOMODE
+//
+// IO Mode
+// Not applicable for IO configured for AON periph. signals and AUX PORT_ID
+// 0x01-0x08
+// AUX has its own open_source/drain configuration.
+//
+// 0x2: Reserved. Undefined behavior.
+// 0x3: Reserved. Undefined behavior.
+// ENUMs:
+// OPENSRC_INV Open Source
+// Inverted input / output
+// OPENSRC Open Source
+// Normal input / output
+// OPENDR_INV Open Drain
+// Inverted input / output
+// OPENDR Open Drain,
+// Normal input / output
+// INV Inverted input / ouput
+// NORMAL Normal input / output
+#define IOC_IOCFG14_IOMODE_W 3
+#define IOC_IOCFG14_IOMODE_M 0x07000000
+#define IOC_IOCFG14_IOMODE_S 24
+#define IOC_IOCFG14_IOMODE_OPENSRC_INV 0x07000000
+#define IOC_IOCFG14_IOMODE_OPENSRC 0x06000000
+#define IOC_IOCFG14_IOMODE_OPENDR_INV 0x05000000
+#define IOC_IOCFG14_IOMODE_OPENDR 0x04000000
+#define IOC_IOCFG14_IOMODE_INV 0x01000000
+#define IOC_IOCFG14_IOMODE_NORMAL 0x00000000
+
+// Field: [23] IOEV_AON_PROG2_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG2 event
+// 1: Input edge detection asserts AON_PROG2 event
+#define IOC_IOCFG14_IOEV_AON_PROG2_EN 0x00800000
+#define IOC_IOCFG14_IOEV_AON_PROG2_EN_BITN 23
+#define IOC_IOCFG14_IOEV_AON_PROG2_EN_M 0x00800000
+#define IOC_IOCFG14_IOEV_AON_PROG2_EN_S 23
+
+// Field: [22] IOEV_AON_PROG1_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG1 event
+// 1: Input edge detection asserts AON_PROG1 event
+#define IOC_IOCFG14_IOEV_AON_PROG1_EN 0x00400000
+#define IOC_IOCFG14_IOEV_AON_PROG1_EN_BITN 22
+#define IOC_IOCFG14_IOEV_AON_PROG1_EN_M 0x00400000
+#define IOC_IOCFG14_IOEV_AON_PROG1_EN_S 22
+
+// Field: [21] IOEV_AON_PROG0_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG0 event
+// 1: Input edge detection asserts AON_PROG0 event
+#define IOC_IOCFG14_IOEV_AON_PROG0_EN 0x00200000
+#define IOC_IOCFG14_IOEV_AON_PROG0_EN_BITN 21
+#define IOC_IOCFG14_IOEV_AON_PROG0_EN_M 0x00200000
+#define IOC_IOCFG14_IOEV_AON_PROG0_EN_S 21
+
+// Field: [18] EDGE_IRQ_EN
+//
+// 0: No interrupt generation
+// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is
+// enabled)
+#define IOC_IOCFG14_EDGE_IRQ_EN 0x00040000
+#define IOC_IOCFG14_EDGE_IRQ_EN_BITN 18
+#define IOC_IOCFG14_EDGE_IRQ_EN_M 0x00040000
+#define IOC_IOCFG14_EDGE_IRQ_EN_S 18
+
+// Field: [17:16] EDGE_DET
+//
+// Enable generation of edge detection events on this IO
+// ENUMs:
+// BOTH Positive and negative edge detection
+// POS Positive edge detection
+// NEG Negative edge detection
+// NONE No edge detection
+#define IOC_IOCFG14_EDGE_DET_W 2
+#define IOC_IOCFG14_EDGE_DET_M 0x00030000
+#define IOC_IOCFG14_EDGE_DET_S 16
+#define IOC_IOCFG14_EDGE_DET_BOTH 0x00030000
+#define IOC_IOCFG14_EDGE_DET_POS 0x00020000
+#define IOC_IOCFG14_EDGE_DET_NEG 0x00010000
+#define IOC_IOCFG14_EDGE_DET_NONE 0x00000000
+
+// Field: [14:13] PULL_CTL
+//
+// Pull control
+// ENUMs:
+// DIS No pull
+// UP Pull up
+// DWN Pull down
+#define IOC_IOCFG14_PULL_CTL_W 2
+#define IOC_IOCFG14_PULL_CTL_M 0x00006000
+#define IOC_IOCFG14_PULL_CTL_S 13
+#define IOC_IOCFG14_PULL_CTL_DIS 0x00006000
+#define IOC_IOCFG14_PULL_CTL_UP 0x00004000
+#define IOC_IOCFG14_PULL_CTL_DWN 0x00002000
+
+// Field: [12] SLEW_RED
+//
+// 0: Normal slew rate
+// 1: Enables reduced slew rate in output driver.
+#define IOC_IOCFG14_SLEW_RED 0x00001000
+#define IOC_IOCFG14_SLEW_RED_BITN 12
+#define IOC_IOCFG14_SLEW_RED_M 0x00001000
+#define IOC_IOCFG14_SLEW_RED_S 12
+
+// Field: [11:10] IOCURR
+//
+// Selects IO current mode of this IO.
+// ENUMs:
+// 4_8MA Extended-Current (EC) mode: Min 8 mA for double
+// drive strength IOs (min 4 mA for normal IOs)
+// when IOSTR is set to AUTO
+// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set
+// to AUTO
+// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set
+// to AUTO
+#define IOC_IOCFG14_IOCURR_W 2
+#define IOC_IOCFG14_IOCURR_M 0x00000C00
+#define IOC_IOCFG14_IOCURR_S 10
+#define IOC_IOCFG14_IOCURR_4_8MA 0x00000800
+#define IOC_IOCFG14_IOCURR_4MA 0x00000400
+#define IOC_IOCFG14_IOCURR_2MA 0x00000000
+
+// Field: [9:8] IOSTR
+//
+// Select source for drive strength control of this IO.
+// This setting controls the drive strength of the Low-Current (LC) mode.
+// Higher drive strength can be selected in IOCURR
+// ENUMs:
+// MAX Maximum drive strength, controlled by
+// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default
+// values)
+// MED Medium drive strength, controlled by
+// AON_IOC:IOSTRMED (min 2 mA @2.5V with default
+// values)
+// MIN Minimum drive strength, controlled by
+// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default
+// values)
+// AUTO Automatic drive strength, controlled by AON BATMON
+// based on battery voltage. (min 2 mA @VDDS)
+#define IOC_IOCFG14_IOSTR_W 2
+#define IOC_IOCFG14_IOSTR_M 0x00000300
+#define IOC_IOCFG14_IOSTR_S 8
+#define IOC_IOCFG14_IOSTR_MAX 0x00000300
+#define IOC_IOCFG14_IOSTR_MED 0x00000200
+#define IOC_IOCFG14_IOSTR_MIN 0x00000100
+#define IOC_IOCFG14_IOSTR_AUTO 0x00000000
+
+// Field: [7] IOEV_RTC_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert RTC event
+// 1: Input edge detection asserts RTC event
+#define IOC_IOCFG14_IOEV_RTC_EN 0x00000080
+#define IOC_IOCFG14_IOEV_RTC_EN_BITN 7
+#define IOC_IOCFG14_IOEV_RTC_EN_M 0x00000080
+#define IOC_IOCFG14_IOEV_RTC_EN_S 7
+
+// Field: [6] IOEV_MCU_WU_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert MCU_WU event
+// 1: Input edge detection asserts MCU_WU event
+#define IOC_IOCFG14_IOEV_MCU_WU_EN 0x00000040
+#define IOC_IOCFG14_IOEV_MCU_WU_EN_BITN 6
+#define IOC_IOCFG14_IOEV_MCU_WU_EN_M 0x00000040
+#define IOC_IOCFG14_IOEV_MCU_WU_EN_S 6
+
+// Field: [5:0] PORT_ID
+//
+// Selects usage for DIO14
+// ENUMs:
+// RFC_SMI_CL_IN RF Core SMI Command Link In
+// RFC_SMI_CL_OUT RF Core SMI Command Link Out
+// RFC_SMI_DL_IN RF Core SMI Data Link In
+// RFC_SMI_DL_OUT RF Core SMI Data Link Out
+// RFC_GPI1 RF Core Data In 1
+// RFC_GPI0 RF Core Data In 0
+// RFC_GPO3 RF Core Data Out 3
+// RFC_GPO2 RF Core Data Out 2
+// RFC_GPO1 RF Core Data Out 1
+// RFC_GPO0 RF Core Data Out 0
+// RFC_TRC RF Core Trace
+// I2S_MCLK I2S MCLK
+// I2S_BCLK I2S BCLK
+// I2S_WCLK I2S WCLK
+// I2S_AD1 I2S Data 1
+// I2S_AD0 I2S Data 0
+// SSI1_CLK SSI1 CLK
+// SSI1_FSS SSI1 FSS
+// SSI1_TX SSI1 TX
+// SSI1_RX SSI1 RX
+// CPU_SWV CPU SWV
+// PORT_EVENT7 PORT EVENT 7
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT6 PORT EVENT 6
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT5 PORT EVENT 5
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT4 PORT EVENT 4
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT3 PORT EVENT 3
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT2 PORT EVENT 2
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT1 PORT EVENT 1
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT0 PORT EVENT 0
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// UART1_RTS UART1 RTS
+// UART1_CTS UART1 CTS
+// UART1_TX UART1 TX
+// UART1_RX UART1 RX
+// UART0_RTS UART0 RTS
+// UART0_CTS UART0 CTS
+// UART0_TX UART0 TX
+// UART0_RX UART0 RX
+// I2C_MSSCL I2C Clock
+// I2C_MSSDA I2C Data
+// SSI0_CLK SSI0 CLK
+// SSI0_FSS SSI0 FSS
+// SSI0_TX SSI0 TX
+// SSI0_RX SSI0 RX
+// AUX_IO AUX IO
+// AON_CLK32K AON 32 KHz clock (SCLK_LF)
+// GPIO General Purpose IO
+#define IOC_IOCFG14_PORT_ID_W 6
+#define IOC_IOCFG14_PORT_ID_M 0x0000003F
+#define IOC_IOCFG14_PORT_ID_S 0
+#define IOC_IOCFG14_PORT_ID_RFC_SMI_CL_IN 0x00000038
+#define IOC_IOCFG14_PORT_ID_RFC_SMI_CL_OUT 0x00000037
+#define IOC_IOCFG14_PORT_ID_RFC_SMI_DL_IN 0x00000036
+#define IOC_IOCFG14_PORT_ID_RFC_SMI_DL_OUT 0x00000035
+#define IOC_IOCFG14_PORT_ID_RFC_GPI1 0x00000034
+#define IOC_IOCFG14_PORT_ID_RFC_GPI0 0x00000033
+#define IOC_IOCFG14_PORT_ID_RFC_GPO3 0x00000032
+#define IOC_IOCFG14_PORT_ID_RFC_GPO2 0x00000031
+#define IOC_IOCFG14_PORT_ID_RFC_GPO1 0x00000030
+#define IOC_IOCFG14_PORT_ID_RFC_GPO0 0x0000002F
+#define IOC_IOCFG14_PORT_ID_RFC_TRC 0x0000002E
+#define IOC_IOCFG14_PORT_ID_I2S_MCLK 0x00000029
+#define IOC_IOCFG14_PORT_ID_I2S_BCLK 0x00000028
+#define IOC_IOCFG14_PORT_ID_I2S_WCLK 0x00000027
+#define IOC_IOCFG14_PORT_ID_I2S_AD1 0x00000026
+#define IOC_IOCFG14_PORT_ID_I2S_AD0 0x00000025
+#define IOC_IOCFG14_PORT_ID_SSI1_CLK 0x00000024
+#define IOC_IOCFG14_PORT_ID_SSI1_FSS 0x00000023
+#define IOC_IOCFG14_PORT_ID_SSI1_TX 0x00000022
+#define IOC_IOCFG14_PORT_ID_SSI1_RX 0x00000021
+#define IOC_IOCFG14_PORT_ID_CPU_SWV 0x00000020
+#define IOC_IOCFG14_PORT_ID_PORT_EVENT7 0x0000001E
+#define IOC_IOCFG14_PORT_ID_PORT_EVENT6 0x0000001D
+#define IOC_IOCFG14_PORT_ID_PORT_EVENT5 0x0000001C
+#define IOC_IOCFG14_PORT_ID_PORT_EVENT4 0x0000001B
+#define IOC_IOCFG14_PORT_ID_PORT_EVENT3 0x0000001A
+#define IOC_IOCFG14_PORT_ID_PORT_EVENT2 0x00000019
+#define IOC_IOCFG14_PORT_ID_PORT_EVENT1 0x00000018
+#define IOC_IOCFG14_PORT_ID_PORT_EVENT0 0x00000017
+#define IOC_IOCFG14_PORT_ID_UART1_RTS 0x00000016
+#define IOC_IOCFG14_PORT_ID_UART1_CTS 0x00000015
+#define IOC_IOCFG14_PORT_ID_UART1_TX 0x00000014
+#define IOC_IOCFG14_PORT_ID_UART1_RX 0x00000013
+#define IOC_IOCFG14_PORT_ID_UART0_RTS 0x00000012
+#define IOC_IOCFG14_PORT_ID_UART0_CTS 0x00000011
+#define IOC_IOCFG14_PORT_ID_UART0_TX 0x00000010
+#define IOC_IOCFG14_PORT_ID_UART0_RX 0x0000000F
+#define IOC_IOCFG14_PORT_ID_I2C_MSSCL 0x0000000E
+#define IOC_IOCFG14_PORT_ID_I2C_MSSDA 0x0000000D
+#define IOC_IOCFG14_PORT_ID_SSI0_CLK 0x0000000C
+#define IOC_IOCFG14_PORT_ID_SSI0_FSS 0x0000000B
+#define IOC_IOCFG14_PORT_ID_SSI0_TX 0x0000000A
+#define IOC_IOCFG14_PORT_ID_SSI0_RX 0x00000009
+#define IOC_IOCFG14_PORT_ID_AUX_IO 0x00000008
+#define IOC_IOCFG14_PORT_ID_AON_CLK32K 0x00000007
+#define IOC_IOCFG14_PORT_ID_GPIO 0x00000000
+
+//*****************************************************************************
+//
+// Register: IOC_O_IOCFG15
+//
+//*****************************************************************************
+// Field: [30] HYST_EN
+//
+// 0: Input hysteresis disable
+// 1: Input hysteresis enable
+#define IOC_IOCFG15_HYST_EN 0x40000000
+#define IOC_IOCFG15_HYST_EN_BITN 30
+#define IOC_IOCFG15_HYST_EN_M 0x40000000
+#define IOC_IOCFG15_HYST_EN_S 30
+
+// Field: [29] IE
+//
+// 0: Input disabled
+// 1: Input enabled
+//
+// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be
+// ignored.
+#define IOC_IOCFG15_IE 0x20000000
+#define IOC_IOCFG15_IE_BITN 29
+#define IOC_IOCFG15_IE_M 0x20000000
+#define IOC_IOCFG15_IE_S 29
+
+// Field: [28:27] WU_CFG
+//
+// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or
+// >0x08:
+//
+// 00: No wake-up
+// 01: No wake-up
+// 10: Wakes up from shutdown if this pad is going low.
+// 11: Wakes up from shutdown if this pad is going high.
+//
+// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08,
+// this register only sets wakeup enable or not.
+//
+// 00, 01: Wakeup disabled
+// 10, 11: Wakeup enabled
+//
+// Polarity is controlled from AON registers.
+//
+// Note:When the MSB is set, the IOC will deactivate the output enable for the
+// DIO.
+#define IOC_IOCFG15_WU_CFG_W 2
+#define IOC_IOCFG15_WU_CFG_M 0x18000000
+#define IOC_IOCFG15_WU_CFG_S 27
+
+// Field: [26:24] IOMODE
+//
+// IO Mode
+// Not applicable for IO configured for AON periph. signals and AUX PORT_ID
+// 0x01-0x08
+// AUX has its own open_source/drain configuration.
+//
+// 0x2: Reserved. Undefined behavior.
+// 0x3: Reserved. Undefined behavior.
+// ENUMs:
+// OPENSRC_INV Open Source
+// Inverted input / output
+// OPENSRC Open Source
+// Normal input / output
+// OPENDR_INV Open Drain
+// Inverted input / output
+// OPENDR Open Drain,
+// Normal input / output
+// INV Inverted input / ouput
+// NORMAL Normal input / output
+#define IOC_IOCFG15_IOMODE_W 3
+#define IOC_IOCFG15_IOMODE_M 0x07000000
+#define IOC_IOCFG15_IOMODE_S 24
+#define IOC_IOCFG15_IOMODE_OPENSRC_INV 0x07000000
+#define IOC_IOCFG15_IOMODE_OPENSRC 0x06000000
+#define IOC_IOCFG15_IOMODE_OPENDR_INV 0x05000000
+#define IOC_IOCFG15_IOMODE_OPENDR 0x04000000
+#define IOC_IOCFG15_IOMODE_INV 0x01000000
+#define IOC_IOCFG15_IOMODE_NORMAL 0x00000000
+
+// Field: [23] IOEV_AON_PROG2_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG2 event
+// 1: Input edge detection asserts AON_PROG2 event
+#define IOC_IOCFG15_IOEV_AON_PROG2_EN 0x00800000
+#define IOC_IOCFG15_IOEV_AON_PROG2_EN_BITN 23
+#define IOC_IOCFG15_IOEV_AON_PROG2_EN_M 0x00800000
+#define IOC_IOCFG15_IOEV_AON_PROG2_EN_S 23
+
+// Field: [22] IOEV_AON_PROG1_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG1 event
+// 1: Input edge detection asserts AON_PROG1 event
+#define IOC_IOCFG15_IOEV_AON_PROG1_EN 0x00400000
+#define IOC_IOCFG15_IOEV_AON_PROG1_EN_BITN 22
+#define IOC_IOCFG15_IOEV_AON_PROG1_EN_M 0x00400000
+#define IOC_IOCFG15_IOEV_AON_PROG1_EN_S 22
+
+// Field: [21] IOEV_AON_PROG0_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG0 event
+// 1: Input edge detection asserts AON_PROG0 event
+#define IOC_IOCFG15_IOEV_AON_PROG0_EN 0x00200000
+#define IOC_IOCFG15_IOEV_AON_PROG0_EN_BITN 21
+#define IOC_IOCFG15_IOEV_AON_PROG0_EN_M 0x00200000
+#define IOC_IOCFG15_IOEV_AON_PROG0_EN_S 21
+
+// Field: [18] EDGE_IRQ_EN
+//
+// 0: No interrupt generation
+// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is
+// enabled)
+#define IOC_IOCFG15_EDGE_IRQ_EN 0x00040000
+#define IOC_IOCFG15_EDGE_IRQ_EN_BITN 18
+#define IOC_IOCFG15_EDGE_IRQ_EN_M 0x00040000
+#define IOC_IOCFG15_EDGE_IRQ_EN_S 18
+
+// Field: [17:16] EDGE_DET
+//
+// Enable generation of edge detection events on this IO
+// ENUMs:
+// BOTH Positive and negative edge detection
+// POS Positive edge detection
+// NEG Negative edge detection
+// NONE No edge detection
+#define IOC_IOCFG15_EDGE_DET_W 2
+#define IOC_IOCFG15_EDGE_DET_M 0x00030000
+#define IOC_IOCFG15_EDGE_DET_S 16
+#define IOC_IOCFG15_EDGE_DET_BOTH 0x00030000
+#define IOC_IOCFG15_EDGE_DET_POS 0x00020000
+#define IOC_IOCFG15_EDGE_DET_NEG 0x00010000
+#define IOC_IOCFG15_EDGE_DET_NONE 0x00000000
+
+// Field: [14:13] PULL_CTL
+//
+// Pull control
+// ENUMs:
+// DIS No pull
+// UP Pull up
+// DWN Pull down
+#define IOC_IOCFG15_PULL_CTL_W 2
+#define IOC_IOCFG15_PULL_CTL_M 0x00006000
+#define IOC_IOCFG15_PULL_CTL_S 13
+#define IOC_IOCFG15_PULL_CTL_DIS 0x00006000
+#define IOC_IOCFG15_PULL_CTL_UP 0x00004000
+#define IOC_IOCFG15_PULL_CTL_DWN 0x00002000
+
+// Field: [12] SLEW_RED
+//
+// 0: Normal slew rate
+// 1: Enables reduced slew rate in output driver.
+#define IOC_IOCFG15_SLEW_RED 0x00001000
+#define IOC_IOCFG15_SLEW_RED_BITN 12
+#define IOC_IOCFG15_SLEW_RED_M 0x00001000
+#define IOC_IOCFG15_SLEW_RED_S 12
+
+// Field: [11:10] IOCURR
+//
+// Selects IO current mode of this IO.
+// ENUMs:
+// 4_8MA Extended-Current (EC) mode: Min 8 mA for double
+// drive strength IOs (min 4 mA for normal IOs)
+// when IOSTR is set to AUTO
+// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set
+// to AUTO
+// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set
+// to AUTO
+#define IOC_IOCFG15_IOCURR_W 2
+#define IOC_IOCFG15_IOCURR_M 0x00000C00
+#define IOC_IOCFG15_IOCURR_S 10
+#define IOC_IOCFG15_IOCURR_4_8MA 0x00000800
+#define IOC_IOCFG15_IOCURR_4MA 0x00000400
+#define IOC_IOCFG15_IOCURR_2MA 0x00000000
+
+// Field: [9:8] IOSTR
+//
+// Select source for drive strength control of this IO.
+// This setting controls the drive strength of the Low-Current (LC) mode.
+// Higher drive strength can be selected in IOCURR
+// ENUMs:
+// MAX Maximum drive strength, controlled by
+// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default
+// values)
+// MED Medium drive strength, controlled by
+// AON_IOC:IOSTRMED (min 2 mA @2.5V with default
+// values)
+// MIN Minimum drive strength, controlled by
+// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default
+// values)
+// AUTO Automatic drive strength, controlled by AON BATMON
+// based on battery voltage. (min 2 mA @VDDS)
+#define IOC_IOCFG15_IOSTR_W 2
+#define IOC_IOCFG15_IOSTR_M 0x00000300
+#define IOC_IOCFG15_IOSTR_S 8
+#define IOC_IOCFG15_IOSTR_MAX 0x00000300
+#define IOC_IOCFG15_IOSTR_MED 0x00000200
+#define IOC_IOCFG15_IOSTR_MIN 0x00000100
+#define IOC_IOCFG15_IOSTR_AUTO 0x00000000
+
+// Field: [7] IOEV_RTC_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert RTC event
+// 1: Input edge detection asserts RTC event
+#define IOC_IOCFG15_IOEV_RTC_EN 0x00000080
+#define IOC_IOCFG15_IOEV_RTC_EN_BITN 7
+#define IOC_IOCFG15_IOEV_RTC_EN_M 0x00000080
+#define IOC_IOCFG15_IOEV_RTC_EN_S 7
+
+// Field: [6] IOEV_MCU_WU_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert MCU_WU event
+// 1: Input edge detection asserts MCU_WU event
+#define IOC_IOCFG15_IOEV_MCU_WU_EN 0x00000040
+#define IOC_IOCFG15_IOEV_MCU_WU_EN_BITN 6
+#define IOC_IOCFG15_IOEV_MCU_WU_EN_M 0x00000040
+#define IOC_IOCFG15_IOEV_MCU_WU_EN_S 6
+
+// Field: [5:0] PORT_ID
+//
+// Selects usage for DIO15
+// ENUMs:
+// RFC_SMI_CL_IN RF Core SMI Command Link In
+// RFC_SMI_CL_OUT RF Core SMI Command Link Out
+// RFC_SMI_DL_IN RF Core SMI Data Link In
+// RFC_SMI_DL_OUT RF Core SMI Data Link Out
+// RFC_GPI1 RF Core Data In 1
+// RFC_GPI0 RF Core Data In 0
+// RFC_GPO3 RF Core Data Out 3
+// RFC_GPO2 RF Core Data Out 2
+// RFC_GPO1 RF Core Data Out 1
+// RFC_GPO0 RF Core Data Out 0
+// RFC_TRC RF Core Trace
+// I2S_MCLK I2S MCLK
+// I2S_BCLK I2S BCLK
+// I2S_WCLK I2S WCLK
+// I2S_AD1 I2S Data 1
+// I2S_AD0 I2S Data 0
+// SSI1_CLK SSI1 CLK
+// SSI1_FSS SSI1 FSS
+// SSI1_TX SSI1 TX
+// SSI1_RX SSI1 RX
+// CPU_SWV CPU SWV
+// PORT_EVENT7 PORT EVENT 7
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT6 PORT EVENT 6
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT5 PORT EVENT 5
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT4 PORT EVENT 4
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT3 PORT EVENT 3
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT2 PORT EVENT 2
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT1 PORT EVENT 1
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT0 PORT EVENT 0
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// UART1_RTS UART1 RTS
+// UART1_CTS UART1 CTS
+// UART1_TX UART1 TX
+// UART1_RX UART1 RX
+// UART0_RTS UART0 RTS
+// UART0_CTS UART0 CTS
+// UART0_TX UART0 TX
+// UART0_RX UART0 RX
+// I2C_MSSCL I2C Clock
+// I2C_MSSDA I2C Data
+// SSI0_CLK SSI0 CLK
+// SSI0_FSS SSI0 FSS
+// SSI0_TX SSI0 TX
+// SSI0_RX SSI0 RX
+// AUX_IO AUX IO
+// AON_CLK32K AON 32 KHz clock (SCLK_LF)
+// GPIO General Purpose IO
+#define IOC_IOCFG15_PORT_ID_W 6
+#define IOC_IOCFG15_PORT_ID_M 0x0000003F
+#define IOC_IOCFG15_PORT_ID_S 0
+#define IOC_IOCFG15_PORT_ID_RFC_SMI_CL_IN 0x00000038
+#define IOC_IOCFG15_PORT_ID_RFC_SMI_CL_OUT 0x00000037
+#define IOC_IOCFG15_PORT_ID_RFC_SMI_DL_IN 0x00000036
+#define IOC_IOCFG15_PORT_ID_RFC_SMI_DL_OUT 0x00000035
+#define IOC_IOCFG15_PORT_ID_RFC_GPI1 0x00000034
+#define IOC_IOCFG15_PORT_ID_RFC_GPI0 0x00000033
+#define IOC_IOCFG15_PORT_ID_RFC_GPO3 0x00000032
+#define IOC_IOCFG15_PORT_ID_RFC_GPO2 0x00000031
+#define IOC_IOCFG15_PORT_ID_RFC_GPO1 0x00000030
+#define IOC_IOCFG15_PORT_ID_RFC_GPO0 0x0000002F
+#define IOC_IOCFG15_PORT_ID_RFC_TRC 0x0000002E
+#define IOC_IOCFG15_PORT_ID_I2S_MCLK 0x00000029
+#define IOC_IOCFG15_PORT_ID_I2S_BCLK 0x00000028
+#define IOC_IOCFG15_PORT_ID_I2S_WCLK 0x00000027
+#define IOC_IOCFG15_PORT_ID_I2S_AD1 0x00000026
+#define IOC_IOCFG15_PORT_ID_I2S_AD0 0x00000025
+#define IOC_IOCFG15_PORT_ID_SSI1_CLK 0x00000024
+#define IOC_IOCFG15_PORT_ID_SSI1_FSS 0x00000023
+#define IOC_IOCFG15_PORT_ID_SSI1_TX 0x00000022
+#define IOC_IOCFG15_PORT_ID_SSI1_RX 0x00000021
+#define IOC_IOCFG15_PORT_ID_CPU_SWV 0x00000020
+#define IOC_IOCFG15_PORT_ID_PORT_EVENT7 0x0000001E
+#define IOC_IOCFG15_PORT_ID_PORT_EVENT6 0x0000001D
+#define IOC_IOCFG15_PORT_ID_PORT_EVENT5 0x0000001C
+#define IOC_IOCFG15_PORT_ID_PORT_EVENT4 0x0000001B
+#define IOC_IOCFG15_PORT_ID_PORT_EVENT3 0x0000001A
+#define IOC_IOCFG15_PORT_ID_PORT_EVENT2 0x00000019
+#define IOC_IOCFG15_PORT_ID_PORT_EVENT1 0x00000018
+#define IOC_IOCFG15_PORT_ID_PORT_EVENT0 0x00000017
+#define IOC_IOCFG15_PORT_ID_UART1_RTS 0x00000016
+#define IOC_IOCFG15_PORT_ID_UART1_CTS 0x00000015
+#define IOC_IOCFG15_PORT_ID_UART1_TX 0x00000014
+#define IOC_IOCFG15_PORT_ID_UART1_RX 0x00000013
+#define IOC_IOCFG15_PORT_ID_UART0_RTS 0x00000012
+#define IOC_IOCFG15_PORT_ID_UART0_CTS 0x00000011
+#define IOC_IOCFG15_PORT_ID_UART0_TX 0x00000010
+#define IOC_IOCFG15_PORT_ID_UART0_RX 0x0000000F
+#define IOC_IOCFG15_PORT_ID_I2C_MSSCL 0x0000000E
+#define IOC_IOCFG15_PORT_ID_I2C_MSSDA 0x0000000D
+#define IOC_IOCFG15_PORT_ID_SSI0_CLK 0x0000000C
+#define IOC_IOCFG15_PORT_ID_SSI0_FSS 0x0000000B
+#define IOC_IOCFG15_PORT_ID_SSI0_TX 0x0000000A
+#define IOC_IOCFG15_PORT_ID_SSI0_RX 0x00000009
+#define IOC_IOCFG15_PORT_ID_AUX_IO 0x00000008
+#define IOC_IOCFG15_PORT_ID_AON_CLK32K 0x00000007
+#define IOC_IOCFG15_PORT_ID_GPIO 0x00000000
+
+//*****************************************************************************
+//
+// Register: IOC_O_IOCFG16
+//
+//*****************************************************************************
+// Field: [30] HYST_EN
+//
+// 0: Input hysteresis disable
+// 1: Input hysteresis enable
+#define IOC_IOCFG16_HYST_EN 0x40000000
+#define IOC_IOCFG16_HYST_EN_BITN 30
+#define IOC_IOCFG16_HYST_EN_M 0x40000000
+#define IOC_IOCFG16_HYST_EN_S 30
+
+// Field: [29] IE
+//
+// 0: Input disabled
+// 1: Input enabled
+//
+// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be
+// ignored.
+#define IOC_IOCFG16_IE 0x20000000
+#define IOC_IOCFG16_IE_BITN 29
+#define IOC_IOCFG16_IE_M 0x20000000
+#define IOC_IOCFG16_IE_S 29
+
+// Field: [28:27] WU_CFG
+//
+// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or
+// >0x08:
+//
+// 00: No wake-up
+// 01: No wake-up
+// 10: Wakes up from shutdown if this pad is going low.
+// 11: Wakes up from shutdown if this pad is going high.
+//
+// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08,
+// this register only sets wakeup enable or not.
+//
+// 00, 01: Wakeup disabled
+// 10, 11: Wakeup enabled
+//
+// Polarity is controlled from AON registers.
+//
+// Note:When the MSB is set, the IOC will deactivate the output enable for the
+// DIO.
+#define IOC_IOCFG16_WU_CFG_W 2
+#define IOC_IOCFG16_WU_CFG_M 0x18000000
+#define IOC_IOCFG16_WU_CFG_S 27
+
+// Field: [26:24] IOMODE
+//
+// IO Mode
+// Not applicable for IO configured for AON periph. signals and AUX PORT_ID
+// 0x01-0x08
+// AUX has its own open_source/drain configuration.
+//
+// 0x2: Reserved. Undefined behavior.
+// 0x3: Reserved. Undefined behavior.
+// ENUMs:
+// OPENSRC_INV Open Source
+// Inverted input / output
+// OPENSRC Open Source
+// Normal input / output
+// OPENDR_INV Open Drain
+// Inverted input / output
+// OPENDR Open Drain,
+// Normal input / output
+// INV Inverted input / ouput
+// NORMAL Normal input / output
+#define IOC_IOCFG16_IOMODE_W 3
+#define IOC_IOCFG16_IOMODE_M 0x07000000
+#define IOC_IOCFG16_IOMODE_S 24
+#define IOC_IOCFG16_IOMODE_OPENSRC_INV 0x07000000
+#define IOC_IOCFG16_IOMODE_OPENSRC 0x06000000
+#define IOC_IOCFG16_IOMODE_OPENDR_INV 0x05000000
+#define IOC_IOCFG16_IOMODE_OPENDR 0x04000000
+#define IOC_IOCFG16_IOMODE_INV 0x01000000
+#define IOC_IOCFG16_IOMODE_NORMAL 0x00000000
+
+// Field: [23] IOEV_AON_PROG2_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG2 event
+// 1: Input edge detection asserts AON_PROG2 event
+#define IOC_IOCFG16_IOEV_AON_PROG2_EN 0x00800000
+#define IOC_IOCFG16_IOEV_AON_PROG2_EN_BITN 23
+#define IOC_IOCFG16_IOEV_AON_PROG2_EN_M 0x00800000
+#define IOC_IOCFG16_IOEV_AON_PROG2_EN_S 23
+
+// Field: [22] IOEV_AON_PROG1_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG1 event
+// 1: Input edge detection asserts AON_PROG1 event
+#define IOC_IOCFG16_IOEV_AON_PROG1_EN 0x00400000
+#define IOC_IOCFG16_IOEV_AON_PROG1_EN_BITN 22
+#define IOC_IOCFG16_IOEV_AON_PROG1_EN_M 0x00400000
+#define IOC_IOCFG16_IOEV_AON_PROG1_EN_S 22
+
+// Field: [21] IOEV_AON_PROG0_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG0 event
+// 1: Input edge detection asserts AON_PROG0 event
+#define IOC_IOCFG16_IOEV_AON_PROG0_EN 0x00200000
+#define IOC_IOCFG16_IOEV_AON_PROG0_EN_BITN 21
+#define IOC_IOCFG16_IOEV_AON_PROG0_EN_M 0x00200000
+#define IOC_IOCFG16_IOEV_AON_PROG0_EN_S 21
+
+// Field: [18] EDGE_IRQ_EN
+//
+// 0: No interrupt generation
+// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is
+// enabled)
+#define IOC_IOCFG16_EDGE_IRQ_EN 0x00040000
+#define IOC_IOCFG16_EDGE_IRQ_EN_BITN 18
+#define IOC_IOCFG16_EDGE_IRQ_EN_M 0x00040000
+#define IOC_IOCFG16_EDGE_IRQ_EN_S 18
+
+// Field: [17:16] EDGE_DET
+//
+// Enable generation of edge detection events on this IO
+// ENUMs:
+// BOTH Positive and negative edge detection
+// POS Positive edge detection
+// NEG Negative edge detection
+// NONE No edge detection
+#define IOC_IOCFG16_EDGE_DET_W 2
+#define IOC_IOCFG16_EDGE_DET_M 0x00030000
+#define IOC_IOCFG16_EDGE_DET_S 16
+#define IOC_IOCFG16_EDGE_DET_BOTH 0x00030000
+#define IOC_IOCFG16_EDGE_DET_POS 0x00020000
+#define IOC_IOCFG16_EDGE_DET_NEG 0x00010000
+#define IOC_IOCFG16_EDGE_DET_NONE 0x00000000
+
+// Field: [14:13] PULL_CTL
+//
+// Pull control
+// ENUMs:
+// DIS No pull
+// UP Pull up
+// DWN Pull down
+#define IOC_IOCFG16_PULL_CTL_W 2
+#define IOC_IOCFG16_PULL_CTL_M 0x00006000
+#define IOC_IOCFG16_PULL_CTL_S 13
+#define IOC_IOCFG16_PULL_CTL_DIS 0x00006000
+#define IOC_IOCFG16_PULL_CTL_UP 0x00004000
+#define IOC_IOCFG16_PULL_CTL_DWN 0x00002000
+
+// Field: [12] SLEW_RED
+//
+// 0: Normal slew rate
+// 1: Enables reduced slew rate in output driver.
+#define IOC_IOCFG16_SLEW_RED 0x00001000
+#define IOC_IOCFG16_SLEW_RED_BITN 12
+#define IOC_IOCFG16_SLEW_RED_M 0x00001000
+#define IOC_IOCFG16_SLEW_RED_S 12
+
+// Field: [11:10] IOCURR
+//
+// Selects IO current mode of this IO.
+// ENUMs:
+// 4_8MA Extended-Current (EC) mode: Min 8 mA for double
+// drive strength IOs (min 4 mA for normal IOs)
+// when IOSTR is set to AUTO
+// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set
+// to AUTO
+// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set
+// to AUTO
+#define IOC_IOCFG16_IOCURR_W 2
+#define IOC_IOCFG16_IOCURR_M 0x00000C00
+#define IOC_IOCFG16_IOCURR_S 10
+#define IOC_IOCFG16_IOCURR_4_8MA 0x00000800
+#define IOC_IOCFG16_IOCURR_4MA 0x00000400
+#define IOC_IOCFG16_IOCURR_2MA 0x00000000
+
+// Field: [9:8] IOSTR
+//
+// Select source for drive strength control of this IO.
+// This setting controls the drive strength of the Low-Current (LC) mode.
+// Higher drive strength can be selected in IOCURR
+// ENUMs:
+// MAX Maximum drive strength, controlled by
+// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default
+// values)
+// MED Medium drive strength, controlled by
+// AON_IOC:IOSTRMED (min 2 mA @2.5V with default
+// values)
+// MIN Minimum drive strength, controlled by
+// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default
+// values)
+// AUTO Automatic drive strength, controlled by AON BATMON
+// based on battery voltage. (min 2 mA @VDDS)
+#define IOC_IOCFG16_IOSTR_W 2
+#define IOC_IOCFG16_IOSTR_M 0x00000300
+#define IOC_IOCFG16_IOSTR_S 8
+#define IOC_IOCFG16_IOSTR_MAX 0x00000300
+#define IOC_IOCFG16_IOSTR_MED 0x00000200
+#define IOC_IOCFG16_IOSTR_MIN 0x00000100
+#define IOC_IOCFG16_IOSTR_AUTO 0x00000000
+
+// Field: [7] IOEV_RTC_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert RTC event
+// 1: Input edge detection asserts RTC event
+#define IOC_IOCFG16_IOEV_RTC_EN 0x00000080
+#define IOC_IOCFG16_IOEV_RTC_EN_BITN 7
+#define IOC_IOCFG16_IOEV_RTC_EN_M 0x00000080
+#define IOC_IOCFG16_IOEV_RTC_EN_S 7
+
+// Field: [6] IOEV_MCU_WU_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert MCU_WU event
+// 1: Input edge detection asserts MCU_WU event
+#define IOC_IOCFG16_IOEV_MCU_WU_EN 0x00000040
+#define IOC_IOCFG16_IOEV_MCU_WU_EN_BITN 6
+#define IOC_IOCFG16_IOEV_MCU_WU_EN_M 0x00000040
+#define IOC_IOCFG16_IOEV_MCU_WU_EN_S 6
+
+// Field: [5:0] PORT_ID
+//
+// Selects usage for DIO16
+// ENUMs:
+// RFC_SMI_CL_IN RF Core SMI Command Link In
+// RFC_SMI_CL_OUT RF Core SMI Command Link Out
+// RFC_SMI_DL_IN RF Core SMI Data Link In
+// RFC_SMI_DL_OUT RF Core SMI Data Link Out
+// RFC_GPI1 RF Core Data In 1
+// RFC_GPI0 RF Core Data In 0
+// RFC_GPO3 RF Core Data Out 3
+// RFC_GPO2 RF Core Data Out 2
+// RFC_GPO1 RF Core Data Out 1
+// RFC_GPO0 RF Core Data Out 0
+// RFC_TRC RF Core Trace
+// I2S_MCLK I2S MCLK
+// I2S_BCLK I2S BCLK
+// I2S_WCLK I2S WCLK
+// I2S_AD1 I2S Data 1
+// I2S_AD0 I2S Data 0
+// SSI1_CLK SSI1 CLK
+// SSI1_FSS SSI1 FSS
+// SSI1_TX SSI1 TX
+// SSI1_RX SSI1 RX
+// CPU_SWV CPU SWV
+// PORT_EVENT7 PORT EVENT 7
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT6 PORT EVENT 6
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT5 PORT EVENT 5
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT4 PORT EVENT 4
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT3 PORT EVENT 3
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT2 PORT EVENT 2
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT1 PORT EVENT 1
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT0 PORT EVENT 0
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// UART1_RTS UART1 RTS
+// UART1_CTS UART1 CTS
+// UART1_TX UART1 TX
+// UART1_RX UART1 RX
+// UART0_RTS UART0 RTS
+// UART0_CTS UART0 CTS
+// UART0_TX UART0 TX
+// UART0_RX UART0 RX
+// I2C_MSSCL I2C Clock
+// I2C_MSSDA I2C Data
+// SSI0_CLK SSI0 CLK
+// SSI0_FSS SSI0 FSS
+// SSI0_TX SSI0 TX
+// SSI0_RX SSI0 RX
+// AUX_IO AUX IO
+// AON_CLK32K AON 32 KHz clock (SCLK_LF)
+// GPIO General Purpose IO
+#define IOC_IOCFG16_PORT_ID_W 6
+#define IOC_IOCFG16_PORT_ID_M 0x0000003F
+#define IOC_IOCFG16_PORT_ID_S 0
+#define IOC_IOCFG16_PORT_ID_RFC_SMI_CL_IN 0x00000038
+#define IOC_IOCFG16_PORT_ID_RFC_SMI_CL_OUT 0x00000037
+#define IOC_IOCFG16_PORT_ID_RFC_SMI_DL_IN 0x00000036
+#define IOC_IOCFG16_PORT_ID_RFC_SMI_DL_OUT 0x00000035
+#define IOC_IOCFG16_PORT_ID_RFC_GPI1 0x00000034
+#define IOC_IOCFG16_PORT_ID_RFC_GPI0 0x00000033
+#define IOC_IOCFG16_PORT_ID_RFC_GPO3 0x00000032
+#define IOC_IOCFG16_PORT_ID_RFC_GPO2 0x00000031
+#define IOC_IOCFG16_PORT_ID_RFC_GPO1 0x00000030
+#define IOC_IOCFG16_PORT_ID_RFC_GPO0 0x0000002F
+#define IOC_IOCFG16_PORT_ID_RFC_TRC 0x0000002E
+#define IOC_IOCFG16_PORT_ID_I2S_MCLK 0x00000029
+#define IOC_IOCFG16_PORT_ID_I2S_BCLK 0x00000028
+#define IOC_IOCFG16_PORT_ID_I2S_WCLK 0x00000027
+#define IOC_IOCFG16_PORT_ID_I2S_AD1 0x00000026
+#define IOC_IOCFG16_PORT_ID_I2S_AD0 0x00000025
+#define IOC_IOCFG16_PORT_ID_SSI1_CLK 0x00000024
+#define IOC_IOCFG16_PORT_ID_SSI1_FSS 0x00000023
+#define IOC_IOCFG16_PORT_ID_SSI1_TX 0x00000022
+#define IOC_IOCFG16_PORT_ID_SSI1_RX 0x00000021
+#define IOC_IOCFG16_PORT_ID_CPU_SWV 0x00000020
+#define IOC_IOCFG16_PORT_ID_PORT_EVENT7 0x0000001E
+#define IOC_IOCFG16_PORT_ID_PORT_EVENT6 0x0000001D
+#define IOC_IOCFG16_PORT_ID_PORT_EVENT5 0x0000001C
+#define IOC_IOCFG16_PORT_ID_PORT_EVENT4 0x0000001B
+#define IOC_IOCFG16_PORT_ID_PORT_EVENT3 0x0000001A
+#define IOC_IOCFG16_PORT_ID_PORT_EVENT2 0x00000019
+#define IOC_IOCFG16_PORT_ID_PORT_EVENT1 0x00000018
+#define IOC_IOCFG16_PORT_ID_PORT_EVENT0 0x00000017
+#define IOC_IOCFG16_PORT_ID_UART1_RTS 0x00000016
+#define IOC_IOCFG16_PORT_ID_UART1_CTS 0x00000015
+#define IOC_IOCFG16_PORT_ID_UART1_TX 0x00000014
+#define IOC_IOCFG16_PORT_ID_UART1_RX 0x00000013
+#define IOC_IOCFG16_PORT_ID_UART0_RTS 0x00000012
+#define IOC_IOCFG16_PORT_ID_UART0_CTS 0x00000011
+#define IOC_IOCFG16_PORT_ID_UART0_TX 0x00000010
+#define IOC_IOCFG16_PORT_ID_UART0_RX 0x0000000F
+#define IOC_IOCFG16_PORT_ID_I2C_MSSCL 0x0000000E
+#define IOC_IOCFG16_PORT_ID_I2C_MSSDA 0x0000000D
+#define IOC_IOCFG16_PORT_ID_SSI0_CLK 0x0000000C
+#define IOC_IOCFG16_PORT_ID_SSI0_FSS 0x0000000B
+#define IOC_IOCFG16_PORT_ID_SSI0_TX 0x0000000A
+#define IOC_IOCFG16_PORT_ID_SSI0_RX 0x00000009
+#define IOC_IOCFG16_PORT_ID_AUX_IO 0x00000008
+#define IOC_IOCFG16_PORT_ID_AON_CLK32K 0x00000007
+#define IOC_IOCFG16_PORT_ID_GPIO 0x00000000
+
+//*****************************************************************************
+//
+// Register: IOC_O_IOCFG17
+//
+//*****************************************************************************
+// Field: [30] HYST_EN
+//
+// 0: Input hysteresis disable
+// 1: Input hysteresis enable
+#define IOC_IOCFG17_HYST_EN 0x40000000
+#define IOC_IOCFG17_HYST_EN_BITN 30
+#define IOC_IOCFG17_HYST_EN_M 0x40000000
+#define IOC_IOCFG17_HYST_EN_S 30
+
+// Field: [29] IE
+//
+// 0: Input disabled
+// 1: Input enabled
+//
+// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be
+// ignored.
+#define IOC_IOCFG17_IE 0x20000000
+#define IOC_IOCFG17_IE_BITN 29
+#define IOC_IOCFG17_IE_M 0x20000000
+#define IOC_IOCFG17_IE_S 29
+
+// Field: [28:27] WU_CFG
+//
+// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or
+// >0x08:
+//
+// 00: No wake-up
+// 01: No wake-up
+// 10: Wakes up from shutdown if this pad is going low.
+// 11: Wakes up from shutdown if this pad is going high.
+//
+// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08,
+// this register only sets wakeup enable or not.
+//
+// 00, 01: Wakeup disabled
+// 10, 11: Wakeup enabled
+//
+// Polarity is controlled from AON registers.
+//
+// Note:When the MSB is set, the IOC will deactivate the output enable for the
+// DIO.
+#define IOC_IOCFG17_WU_CFG_W 2
+#define IOC_IOCFG17_WU_CFG_M 0x18000000
+#define IOC_IOCFG17_WU_CFG_S 27
+
+// Field: [26:24] IOMODE
+//
+// IO Mode
+// Not applicable for IO configured for AON periph. signals and AUX PORT_ID
+// 0x01-0x08
+// AUX has its own open_source/drain configuration.
+//
+// 0x2: Reserved. Undefined behavior.
+// 0x3: Reserved. Undefined behavior.
+// ENUMs:
+// OPENSRC_INV Open Source
+// Inverted input / output
+// OPENSRC Open Source
+// Normal input / output
+// OPENDR_INV Open Drain
+// Inverted input / output
+// OPENDR Open Drain,
+// Normal input / output
+// INV Inverted input / ouput
+// NORMAL Normal input / output
+#define IOC_IOCFG17_IOMODE_W 3
+#define IOC_IOCFG17_IOMODE_M 0x07000000
+#define IOC_IOCFG17_IOMODE_S 24
+#define IOC_IOCFG17_IOMODE_OPENSRC_INV 0x07000000
+#define IOC_IOCFG17_IOMODE_OPENSRC 0x06000000
+#define IOC_IOCFG17_IOMODE_OPENDR_INV 0x05000000
+#define IOC_IOCFG17_IOMODE_OPENDR 0x04000000
+#define IOC_IOCFG17_IOMODE_INV 0x01000000
+#define IOC_IOCFG17_IOMODE_NORMAL 0x00000000
+
+// Field: [23] IOEV_AON_PROG2_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG2 event
+// 1: Input edge detection asserts AON_PROG2 event
+#define IOC_IOCFG17_IOEV_AON_PROG2_EN 0x00800000
+#define IOC_IOCFG17_IOEV_AON_PROG2_EN_BITN 23
+#define IOC_IOCFG17_IOEV_AON_PROG2_EN_M 0x00800000
+#define IOC_IOCFG17_IOEV_AON_PROG2_EN_S 23
+
+// Field: [22] IOEV_AON_PROG1_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG1 event
+// 1: Input edge detection asserts AON_PROG1 event
+#define IOC_IOCFG17_IOEV_AON_PROG1_EN 0x00400000
+#define IOC_IOCFG17_IOEV_AON_PROG1_EN_BITN 22
+#define IOC_IOCFG17_IOEV_AON_PROG1_EN_M 0x00400000
+#define IOC_IOCFG17_IOEV_AON_PROG1_EN_S 22
+
+// Field: [21] IOEV_AON_PROG0_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG0 event
+// 1: Input edge detection asserts AON_PROG0 event
+#define IOC_IOCFG17_IOEV_AON_PROG0_EN 0x00200000
+#define IOC_IOCFG17_IOEV_AON_PROG0_EN_BITN 21
+#define IOC_IOCFG17_IOEV_AON_PROG0_EN_M 0x00200000
+#define IOC_IOCFG17_IOEV_AON_PROG0_EN_S 21
+
+// Field: [18] EDGE_IRQ_EN
+//
+// 0: No interrupt generation
+// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is
+// enabled)
+#define IOC_IOCFG17_EDGE_IRQ_EN 0x00040000
+#define IOC_IOCFG17_EDGE_IRQ_EN_BITN 18
+#define IOC_IOCFG17_EDGE_IRQ_EN_M 0x00040000
+#define IOC_IOCFG17_EDGE_IRQ_EN_S 18
+
+// Field: [17:16] EDGE_DET
+//
+// Enable generation of edge detection events on this IO
+// ENUMs:
+// BOTH Positive and negative edge detection
+// POS Positive edge detection
+// NEG Negative edge detection
+// NONE No edge detection
+#define IOC_IOCFG17_EDGE_DET_W 2
+#define IOC_IOCFG17_EDGE_DET_M 0x00030000
+#define IOC_IOCFG17_EDGE_DET_S 16
+#define IOC_IOCFG17_EDGE_DET_BOTH 0x00030000
+#define IOC_IOCFG17_EDGE_DET_POS 0x00020000
+#define IOC_IOCFG17_EDGE_DET_NEG 0x00010000
+#define IOC_IOCFG17_EDGE_DET_NONE 0x00000000
+
+// Field: [14:13] PULL_CTL
+//
+// Pull control
+// ENUMs:
+// DIS No pull
+// UP Pull up
+// DWN Pull down
+#define IOC_IOCFG17_PULL_CTL_W 2
+#define IOC_IOCFG17_PULL_CTL_M 0x00006000
+#define IOC_IOCFG17_PULL_CTL_S 13
+#define IOC_IOCFG17_PULL_CTL_DIS 0x00006000
+#define IOC_IOCFG17_PULL_CTL_UP 0x00004000
+#define IOC_IOCFG17_PULL_CTL_DWN 0x00002000
+
+// Field: [12] SLEW_RED
+//
+// 0: Normal slew rate
+// 1: Enables reduced slew rate in output driver.
+#define IOC_IOCFG17_SLEW_RED 0x00001000
+#define IOC_IOCFG17_SLEW_RED_BITN 12
+#define IOC_IOCFG17_SLEW_RED_M 0x00001000
+#define IOC_IOCFG17_SLEW_RED_S 12
+
+// Field: [11:10] IOCURR
+//
+// Selects IO current mode of this IO.
+// ENUMs:
+// 4_8MA Extended-Current (EC) mode: Min 8 mA for double
+// drive strength IOs (min 4 mA for normal IOs)
+// when IOSTR is set to AUTO
+// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set
+// to AUTO
+// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set
+// to AUTO
+#define IOC_IOCFG17_IOCURR_W 2
+#define IOC_IOCFG17_IOCURR_M 0x00000C00
+#define IOC_IOCFG17_IOCURR_S 10
+#define IOC_IOCFG17_IOCURR_4_8MA 0x00000800
+#define IOC_IOCFG17_IOCURR_4MA 0x00000400
+#define IOC_IOCFG17_IOCURR_2MA 0x00000000
+
+// Field: [9:8] IOSTR
+//
+// Select source for drive strength control of this IO.
+// This setting controls the drive strength of the Low-Current (LC) mode.
+// Higher drive strength can be selected in IOCURR
+// ENUMs:
+// MAX Maximum drive strength, controlled by
+// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default
+// values)
+// MED Medium drive strength, controlled by
+// AON_IOC:IOSTRMED (min 2 mA @2.5V with default
+// values)
+// MIN Minimum drive strength, controlled by
+// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default
+// values)
+// AUTO Automatic drive strength, controlled by AON BATMON
+// based on battery voltage. (min 2 mA @VDDS)
+#define IOC_IOCFG17_IOSTR_W 2
+#define IOC_IOCFG17_IOSTR_M 0x00000300
+#define IOC_IOCFG17_IOSTR_S 8
+#define IOC_IOCFG17_IOSTR_MAX 0x00000300
+#define IOC_IOCFG17_IOSTR_MED 0x00000200
+#define IOC_IOCFG17_IOSTR_MIN 0x00000100
+#define IOC_IOCFG17_IOSTR_AUTO 0x00000000
+
+// Field: [7] IOEV_RTC_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert RTC event
+// 1: Input edge detection asserts RTC event
+#define IOC_IOCFG17_IOEV_RTC_EN 0x00000080
+#define IOC_IOCFG17_IOEV_RTC_EN_BITN 7
+#define IOC_IOCFG17_IOEV_RTC_EN_M 0x00000080
+#define IOC_IOCFG17_IOEV_RTC_EN_S 7
+
+// Field: [6] IOEV_MCU_WU_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert MCU_WU event
+// 1: Input edge detection asserts MCU_WU event
+#define IOC_IOCFG17_IOEV_MCU_WU_EN 0x00000040
+#define IOC_IOCFG17_IOEV_MCU_WU_EN_BITN 6
+#define IOC_IOCFG17_IOEV_MCU_WU_EN_M 0x00000040
+#define IOC_IOCFG17_IOEV_MCU_WU_EN_S 6
+
+// Field: [5:0] PORT_ID
+//
+// Selects usage for DIO17
+// ENUMs:
+// RFC_SMI_CL_IN RF Core SMI Command Link In
+// RFC_SMI_CL_OUT RF Core SMI Command Link Out
+// RFC_SMI_DL_IN RF Core SMI Data Link In
+// RFC_SMI_DL_OUT RF Core SMI Data Link Out
+// RFC_GPI1 RF Core Data In 1
+// RFC_GPI0 RF Core Data In 0
+// RFC_GPO3 RF Core Data Out 3
+// RFC_GPO2 RF Core Data Out 2
+// RFC_GPO1 RF Core Data Out 1
+// RFC_GPO0 RF Core Data Out 0
+// RFC_TRC RF Core Trace
+// I2S_MCLK I2S MCLK
+// I2S_BCLK I2S BCLK
+// I2S_WCLK I2S WCLK
+// I2S_AD1 I2S Data 1
+// I2S_AD0 I2S Data 0
+// SSI1_CLK SSI1 CLK
+// SSI1_FSS SSI1 FSS
+// SSI1_TX SSI1 TX
+// SSI1_RX SSI1 RX
+// CPU_SWV CPU SWV
+// PORT_EVENT7 PORT EVENT 7
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT6 PORT EVENT 6
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT5 PORT EVENT 5
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT4 PORT EVENT 4
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT3 PORT EVENT 3
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT2 PORT EVENT 2
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT1 PORT EVENT 1
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT0 PORT EVENT 0
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// UART1_RTS UART1 RTS
+// UART1_CTS UART1 CTS
+// UART1_TX UART1 TX
+// UART1_RX UART1 RX
+// UART0_RTS UART0 RTS
+// UART0_CTS UART0 CTS
+// UART0_TX UART0 TX
+// UART0_RX UART0 RX
+// I2C_MSSCL I2C Clock
+// I2C_MSSDA I2C Data
+// SSI0_CLK SSI0 CLK
+// SSI0_FSS SSI0 FSS
+// SSI0_TX SSI0 TX
+// SSI0_RX SSI0 RX
+// AUX_IO AUX IO
+// AON_CLK32K AON 32 KHz clock (SCLK_LF)
+// GPIO General Purpose IO
+#define IOC_IOCFG17_PORT_ID_W 6
+#define IOC_IOCFG17_PORT_ID_M 0x0000003F
+#define IOC_IOCFG17_PORT_ID_S 0
+#define IOC_IOCFG17_PORT_ID_RFC_SMI_CL_IN 0x00000038
+#define IOC_IOCFG17_PORT_ID_RFC_SMI_CL_OUT 0x00000037
+#define IOC_IOCFG17_PORT_ID_RFC_SMI_DL_IN 0x00000036
+#define IOC_IOCFG17_PORT_ID_RFC_SMI_DL_OUT 0x00000035
+#define IOC_IOCFG17_PORT_ID_RFC_GPI1 0x00000034
+#define IOC_IOCFG17_PORT_ID_RFC_GPI0 0x00000033
+#define IOC_IOCFG17_PORT_ID_RFC_GPO3 0x00000032
+#define IOC_IOCFG17_PORT_ID_RFC_GPO2 0x00000031
+#define IOC_IOCFG17_PORT_ID_RFC_GPO1 0x00000030
+#define IOC_IOCFG17_PORT_ID_RFC_GPO0 0x0000002F
+#define IOC_IOCFG17_PORT_ID_RFC_TRC 0x0000002E
+#define IOC_IOCFG17_PORT_ID_I2S_MCLK 0x00000029
+#define IOC_IOCFG17_PORT_ID_I2S_BCLK 0x00000028
+#define IOC_IOCFG17_PORT_ID_I2S_WCLK 0x00000027
+#define IOC_IOCFG17_PORT_ID_I2S_AD1 0x00000026
+#define IOC_IOCFG17_PORT_ID_I2S_AD0 0x00000025
+#define IOC_IOCFG17_PORT_ID_SSI1_CLK 0x00000024
+#define IOC_IOCFG17_PORT_ID_SSI1_FSS 0x00000023
+#define IOC_IOCFG17_PORT_ID_SSI1_TX 0x00000022
+#define IOC_IOCFG17_PORT_ID_SSI1_RX 0x00000021
+#define IOC_IOCFG17_PORT_ID_CPU_SWV 0x00000020
+#define IOC_IOCFG17_PORT_ID_PORT_EVENT7 0x0000001E
+#define IOC_IOCFG17_PORT_ID_PORT_EVENT6 0x0000001D
+#define IOC_IOCFG17_PORT_ID_PORT_EVENT5 0x0000001C
+#define IOC_IOCFG17_PORT_ID_PORT_EVENT4 0x0000001B
+#define IOC_IOCFG17_PORT_ID_PORT_EVENT3 0x0000001A
+#define IOC_IOCFG17_PORT_ID_PORT_EVENT2 0x00000019
+#define IOC_IOCFG17_PORT_ID_PORT_EVENT1 0x00000018
+#define IOC_IOCFG17_PORT_ID_PORT_EVENT0 0x00000017
+#define IOC_IOCFG17_PORT_ID_UART1_RTS 0x00000016
+#define IOC_IOCFG17_PORT_ID_UART1_CTS 0x00000015
+#define IOC_IOCFG17_PORT_ID_UART1_TX 0x00000014
+#define IOC_IOCFG17_PORT_ID_UART1_RX 0x00000013
+#define IOC_IOCFG17_PORT_ID_UART0_RTS 0x00000012
+#define IOC_IOCFG17_PORT_ID_UART0_CTS 0x00000011
+#define IOC_IOCFG17_PORT_ID_UART0_TX 0x00000010
+#define IOC_IOCFG17_PORT_ID_UART0_RX 0x0000000F
+#define IOC_IOCFG17_PORT_ID_I2C_MSSCL 0x0000000E
+#define IOC_IOCFG17_PORT_ID_I2C_MSSDA 0x0000000D
+#define IOC_IOCFG17_PORT_ID_SSI0_CLK 0x0000000C
+#define IOC_IOCFG17_PORT_ID_SSI0_FSS 0x0000000B
+#define IOC_IOCFG17_PORT_ID_SSI0_TX 0x0000000A
+#define IOC_IOCFG17_PORT_ID_SSI0_RX 0x00000009
+#define IOC_IOCFG17_PORT_ID_AUX_IO 0x00000008
+#define IOC_IOCFG17_PORT_ID_AON_CLK32K 0x00000007
+#define IOC_IOCFG17_PORT_ID_GPIO 0x00000000
+
+//*****************************************************************************
+//
+// Register: IOC_O_IOCFG18
+//
+//*****************************************************************************
+// Field: [30] HYST_EN
+//
+// 0: Input hysteresis disable
+// 1: Input hysteresis enable
+#define IOC_IOCFG18_HYST_EN 0x40000000
+#define IOC_IOCFG18_HYST_EN_BITN 30
+#define IOC_IOCFG18_HYST_EN_M 0x40000000
+#define IOC_IOCFG18_HYST_EN_S 30
+
+// Field: [29] IE
+//
+// 0: Input disabled
+// 1: Input enabled
+//
+// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be
+// ignored.
+#define IOC_IOCFG18_IE 0x20000000
+#define IOC_IOCFG18_IE_BITN 29
+#define IOC_IOCFG18_IE_M 0x20000000
+#define IOC_IOCFG18_IE_S 29
+
+// Field: [28:27] WU_CFG
+//
+// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or
+// >0x08:
+//
+// 00: No wake-up
+// 01: No wake-up
+// 10: Wakes up from shutdown if this pad is going low.
+// 11: Wakes up from shutdown if this pad is going high.
+//
+// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08,
+// this register only sets wakeup enable or not.
+//
+// 00, 01: Wakeup disabled
+// 10, 11: Wakeup enabled
+//
+// Polarity is controlled from AON registers.
+//
+// Note:When the MSB is set, the IOC will deactivate the output enable for the
+// DIO.
+#define IOC_IOCFG18_WU_CFG_W 2
+#define IOC_IOCFG18_WU_CFG_M 0x18000000
+#define IOC_IOCFG18_WU_CFG_S 27
+
+// Field: [26:24] IOMODE
+//
+// IO Mode
+// Not applicable for IO configured for AON periph. signals and AUX PORT_ID
+// 0x01-0x08
+// AUX has its own open_source/drain configuration.
+//
+// 0x2: Reserved. Undefined behavior.
+// 0x3: Reserved. Undefined behavior.
+// ENUMs:
+// OPENSRC_INV Open Source
+// Inverted input / output
+// OPENSRC Open Source
+// Normal input / output
+// OPENDR_INV Open Drain
+// Inverted input / output
+// OPENDR Open Drain,
+// Normal input / output
+// INV Inverted input / ouput
+// NORMAL Normal input / output
+#define IOC_IOCFG18_IOMODE_W 3
+#define IOC_IOCFG18_IOMODE_M 0x07000000
+#define IOC_IOCFG18_IOMODE_S 24
+#define IOC_IOCFG18_IOMODE_OPENSRC_INV 0x07000000
+#define IOC_IOCFG18_IOMODE_OPENSRC 0x06000000
+#define IOC_IOCFG18_IOMODE_OPENDR_INV 0x05000000
+#define IOC_IOCFG18_IOMODE_OPENDR 0x04000000
+#define IOC_IOCFG18_IOMODE_INV 0x01000000
+#define IOC_IOCFG18_IOMODE_NORMAL 0x00000000
+
+// Field: [23] IOEV_AON_PROG2_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG2 event
+// 1: Input edge detection asserts AON_PROG2 event
+#define IOC_IOCFG18_IOEV_AON_PROG2_EN 0x00800000
+#define IOC_IOCFG18_IOEV_AON_PROG2_EN_BITN 23
+#define IOC_IOCFG18_IOEV_AON_PROG2_EN_M 0x00800000
+#define IOC_IOCFG18_IOEV_AON_PROG2_EN_S 23
+
+// Field: [22] IOEV_AON_PROG1_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG1 event
+// 1: Input edge detection asserts AON_PROG1 event
+#define IOC_IOCFG18_IOEV_AON_PROG1_EN 0x00400000
+#define IOC_IOCFG18_IOEV_AON_PROG1_EN_BITN 22
+#define IOC_IOCFG18_IOEV_AON_PROG1_EN_M 0x00400000
+#define IOC_IOCFG18_IOEV_AON_PROG1_EN_S 22
+
+// Field: [21] IOEV_AON_PROG0_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG0 event
+// 1: Input edge detection asserts AON_PROG0 event
+#define IOC_IOCFG18_IOEV_AON_PROG0_EN 0x00200000
+#define IOC_IOCFG18_IOEV_AON_PROG0_EN_BITN 21
+#define IOC_IOCFG18_IOEV_AON_PROG0_EN_M 0x00200000
+#define IOC_IOCFG18_IOEV_AON_PROG0_EN_S 21
+
+// Field: [18] EDGE_IRQ_EN
+//
+// 0: No interrupt generation
+// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is
+// enabled)
+#define IOC_IOCFG18_EDGE_IRQ_EN 0x00040000
+#define IOC_IOCFG18_EDGE_IRQ_EN_BITN 18
+#define IOC_IOCFG18_EDGE_IRQ_EN_M 0x00040000
+#define IOC_IOCFG18_EDGE_IRQ_EN_S 18
+
+// Field: [17:16] EDGE_DET
+//
+// Enable generation of edge detection events on this IO
+// ENUMs:
+// BOTH Positive and negative edge detection
+// POS Positive edge detection
+// NEG Negative edge detection
+// NONE No edge detection
+#define IOC_IOCFG18_EDGE_DET_W 2
+#define IOC_IOCFG18_EDGE_DET_M 0x00030000
+#define IOC_IOCFG18_EDGE_DET_S 16
+#define IOC_IOCFG18_EDGE_DET_BOTH 0x00030000
+#define IOC_IOCFG18_EDGE_DET_POS 0x00020000
+#define IOC_IOCFG18_EDGE_DET_NEG 0x00010000
+#define IOC_IOCFG18_EDGE_DET_NONE 0x00000000
+
+// Field: [14:13] PULL_CTL
+//
+// Pull control
+// ENUMs:
+// DIS No pull
+// UP Pull up
+// DWN Pull down
+#define IOC_IOCFG18_PULL_CTL_W 2
+#define IOC_IOCFG18_PULL_CTL_M 0x00006000
+#define IOC_IOCFG18_PULL_CTL_S 13
+#define IOC_IOCFG18_PULL_CTL_DIS 0x00006000
+#define IOC_IOCFG18_PULL_CTL_UP 0x00004000
+#define IOC_IOCFG18_PULL_CTL_DWN 0x00002000
+
+// Field: [12] SLEW_RED
+//
+// 0: Normal slew rate
+// 1: Enables reduced slew rate in output driver.
+#define IOC_IOCFG18_SLEW_RED 0x00001000
+#define IOC_IOCFG18_SLEW_RED_BITN 12
+#define IOC_IOCFG18_SLEW_RED_M 0x00001000
+#define IOC_IOCFG18_SLEW_RED_S 12
+
+// Field: [11:10] IOCURR
+//
+// Selects IO current mode of this IO.
+// ENUMs:
+// 4_8MA Extended-Current (EC) mode: Min 8 mA for double
+// drive strength IOs (min 4 mA for normal IOs)
+// when IOSTR is set to AUTO
+// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set
+// to AUTO
+// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set
+// to AUTO
+#define IOC_IOCFG18_IOCURR_W 2
+#define IOC_IOCFG18_IOCURR_M 0x00000C00
+#define IOC_IOCFG18_IOCURR_S 10
+#define IOC_IOCFG18_IOCURR_4_8MA 0x00000800
+#define IOC_IOCFG18_IOCURR_4MA 0x00000400
+#define IOC_IOCFG18_IOCURR_2MA 0x00000000
+
+// Field: [9:8] IOSTR
+//
+// Select source for drive strength control of this IO.
+// This setting controls the drive strength of the Low-Current (LC) mode.
+// Higher drive strength can be selected in IOCURR
+// ENUMs:
+// MAX Maximum drive strength, controlled by
+// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default
+// values)
+// MED Medium drive strength, controlled by
+// AON_IOC:IOSTRMED (min 2 mA @2.5V with default
+// values)
+// MIN Minimum drive strength, controlled by
+// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default
+// values)
+// AUTO Automatic drive strength, controlled by AON BATMON
+// based on battery voltage. (min 2 mA @VDDS)
+#define IOC_IOCFG18_IOSTR_W 2
+#define IOC_IOCFG18_IOSTR_M 0x00000300
+#define IOC_IOCFG18_IOSTR_S 8
+#define IOC_IOCFG18_IOSTR_MAX 0x00000300
+#define IOC_IOCFG18_IOSTR_MED 0x00000200
+#define IOC_IOCFG18_IOSTR_MIN 0x00000100
+#define IOC_IOCFG18_IOSTR_AUTO 0x00000000
+
+// Field: [7] IOEV_RTC_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert RTC event
+// 1: Input edge detection asserts RTC event
+#define IOC_IOCFG18_IOEV_RTC_EN 0x00000080
+#define IOC_IOCFG18_IOEV_RTC_EN_BITN 7
+#define IOC_IOCFG18_IOEV_RTC_EN_M 0x00000080
+#define IOC_IOCFG18_IOEV_RTC_EN_S 7
+
+// Field: [6] IOEV_MCU_WU_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert MCU_WU event
+// 1: Input edge detection asserts MCU_WU event
+#define IOC_IOCFG18_IOEV_MCU_WU_EN 0x00000040
+#define IOC_IOCFG18_IOEV_MCU_WU_EN_BITN 6
+#define IOC_IOCFG18_IOEV_MCU_WU_EN_M 0x00000040
+#define IOC_IOCFG18_IOEV_MCU_WU_EN_S 6
+
+// Field: [5:0] PORT_ID
+//
+// Selects usage for DIO18
+// ENUMs:
+// RFC_SMI_CL_IN RF Core SMI Command Link In
+// RFC_SMI_CL_OUT RF Core SMI Command Link Out
+// RFC_SMI_DL_IN RF Core SMI Data Link In
+// RFC_SMI_DL_OUT RF Core SMI Data Link Out
+// RFC_GPI1 RF Core Data In 1
+// RFC_GPI0 RF Core Data In 0
+// RFC_GPO3 RF Core Data Out 3
+// RFC_GPO2 RF Core Data Out 2
+// RFC_GPO1 RF Core Data Out 1
+// RFC_GPO0 RF Core Data Out 0
+// RFC_TRC RF Core Trace
+// I2S_MCLK I2S MCLK
+// I2S_BCLK I2S BCLK
+// I2S_WCLK I2S WCLK
+// I2S_AD1 I2S Data 1
+// I2S_AD0 I2S Data 0
+// SSI1_CLK SSI1 CLK
+// SSI1_FSS SSI1 FSS
+// SSI1_TX SSI1 TX
+// SSI1_RX SSI1 RX
+// CPU_SWV CPU SWV
+// PORT_EVENT7 PORT EVENT 7
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT6 PORT EVENT 6
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT5 PORT EVENT 5
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT4 PORT EVENT 4
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT3 PORT EVENT 3
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT2 PORT EVENT 2
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT1 PORT EVENT 1
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT0 PORT EVENT 0
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// UART1_RTS UART1 RTS
+// UART1_CTS UART1 CTS
+// UART1_TX UART1 TX
+// UART1_RX UART1 RX
+// UART0_RTS UART0 RTS
+// UART0_CTS UART0 CTS
+// UART0_TX UART0 TX
+// UART0_RX UART0 RX
+// I2C_MSSCL I2C Clock
+// I2C_MSSDA I2C Data
+// SSI0_CLK SSI0 CLK
+// SSI0_FSS SSI0 FSS
+// SSI0_TX SSI0 TX
+// SSI0_RX SSI0 RX
+// AUX_IO AUX IO
+// AON_CLK32K AON 32 KHz clock (SCLK_LF)
+// GPIO General Purpose IO
+#define IOC_IOCFG18_PORT_ID_W 6
+#define IOC_IOCFG18_PORT_ID_M 0x0000003F
+#define IOC_IOCFG18_PORT_ID_S 0
+#define IOC_IOCFG18_PORT_ID_RFC_SMI_CL_IN 0x00000038
+#define IOC_IOCFG18_PORT_ID_RFC_SMI_CL_OUT 0x00000037
+#define IOC_IOCFG18_PORT_ID_RFC_SMI_DL_IN 0x00000036
+#define IOC_IOCFG18_PORT_ID_RFC_SMI_DL_OUT 0x00000035
+#define IOC_IOCFG18_PORT_ID_RFC_GPI1 0x00000034
+#define IOC_IOCFG18_PORT_ID_RFC_GPI0 0x00000033
+#define IOC_IOCFG18_PORT_ID_RFC_GPO3 0x00000032
+#define IOC_IOCFG18_PORT_ID_RFC_GPO2 0x00000031
+#define IOC_IOCFG18_PORT_ID_RFC_GPO1 0x00000030
+#define IOC_IOCFG18_PORT_ID_RFC_GPO0 0x0000002F
+#define IOC_IOCFG18_PORT_ID_RFC_TRC 0x0000002E
+#define IOC_IOCFG18_PORT_ID_I2S_MCLK 0x00000029
+#define IOC_IOCFG18_PORT_ID_I2S_BCLK 0x00000028
+#define IOC_IOCFG18_PORT_ID_I2S_WCLK 0x00000027
+#define IOC_IOCFG18_PORT_ID_I2S_AD1 0x00000026
+#define IOC_IOCFG18_PORT_ID_I2S_AD0 0x00000025
+#define IOC_IOCFG18_PORT_ID_SSI1_CLK 0x00000024
+#define IOC_IOCFG18_PORT_ID_SSI1_FSS 0x00000023
+#define IOC_IOCFG18_PORT_ID_SSI1_TX 0x00000022
+#define IOC_IOCFG18_PORT_ID_SSI1_RX 0x00000021
+#define IOC_IOCFG18_PORT_ID_CPU_SWV 0x00000020
+#define IOC_IOCFG18_PORT_ID_PORT_EVENT7 0x0000001E
+#define IOC_IOCFG18_PORT_ID_PORT_EVENT6 0x0000001D
+#define IOC_IOCFG18_PORT_ID_PORT_EVENT5 0x0000001C
+#define IOC_IOCFG18_PORT_ID_PORT_EVENT4 0x0000001B
+#define IOC_IOCFG18_PORT_ID_PORT_EVENT3 0x0000001A
+#define IOC_IOCFG18_PORT_ID_PORT_EVENT2 0x00000019
+#define IOC_IOCFG18_PORT_ID_PORT_EVENT1 0x00000018
+#define IOC_IOCFG18_PORT_ID_PORT_EVENT0 0x00000017
+#define IOC_IOCFG18_PORT_ID_UART1_RTS 0x00000016
+#define IOC_IOCFG18_PORT_ID_UART1_CTS 0x00000015
+#define IOC_IOCFG18_PORT_ID_UART1_TX 0x00000014
+#define IOC_IOCFG18_PORT_ID_UART1_RX 0x00000013
+#define IOC_IOCFG18_PORT_ID_UART0_RTS 0x00000012
+#define IOC_IOCFG18_PORT_ID_UART0_CTS 0x00000011
+#define IOC_IOCFG18_PORT_ID_UART0_TX 0x00000010
+#define IOC_IOCFG18_PORT_ID_UART0_RX 0x0000000F
+#define IOC_IOCFG18_PORT_ID_I2C_MSSCL 0x0000000E
+#define IOC_IOCFG18_PORT_ID_I2C_MSSDA 0x0000000D
+#define IOC_IOCFG18_PORT_ID_SSI0_CLK 0x0000000C
+#define IOC_IOCFG18_PORT_ID_SSI0_FSS 0x0000000B
+#define IOC_IOCFG18_PORT_ID_SSI0_TX 0x0000000A
+#define IOC_IOCFG18_PORT_ID_SSI0_RX 0x00000009
+#define IOC_IOCFG18_PORT_ID_AUX_IO 0x00000008
+#define IOC_IOCFG18_PORT_ID_AON_CLK32K 0x00000007
+#define IOC_IOCFG18_PORT_ID_GPIO 0x00000000
+
+//*****************************************************************************
+//
+// Register: IOC_O_IOCFG19
+//
+//*****************************************************************************
+// Field: [30] HYST_EN
+//
+// 0: Input hysteresis disable
+// 1: Input hysteresis enable
+#define IOC_IOCFG19_HYST_EN 0x40000000
+#define IOC_IOCFG19_HYST_EN_BITN 30
+#define IOC_IOCFG19_HYST_EN_M 0x40000000
+#define IOC_IOCFG19_HYST_EN_S 30
+
+// Field: [29] IE
+//
+// 0: Input disabled
+// 1: Input enabled
+//
+// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be
+// ignored.
+#define IOC_IOCFG19_IE 0x20000000
+#define IOC_IOCFG19_IE_BITN 29
+#define IOC_IOCFG19_IE_M 0x20000000
+#define IOC_IOCFG19_IE_S 29
+
+// Field: [28:27] WU_CFG
+//
+// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or
+// >0x08:
+//
+// 00: No wake-up
+// 01: No wake-up
+// 10: Wakes up from shutdown if this pad is going low.
+// 11: Wakes up from shutdown if this pad is going high.
+//
+// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08,
+// this register only sets wakeup enable or not.
+//
+// 00, 01: Wakeup disabled
+// 10, 11: Wakeup enabled
+//
+// Polarity is controlled from AON registers.
+//
+// Note:When the MSB is set, the IOC will deactivate the output enable for the
+// DIO.
+#define IOC_IOCFG19_WU_CFG_W 2
+#define IOC_IOCFG19_WU_CFG_M 0x18000000
+#define IOC_IOCFG19_WU_CFG_S 27
+
+// Field: [26:24] IOMODE
+//
+// IO Mode
+// Not applicable for IO configured for AON periph. signals and AUX PORT_ID
+// 0x01-0x08
+// AUX has its own open_source/drain configuration.
+//
+// 0x2: Reserved. Undefined behavior.
+// 0x3: Reserved. Undefined behavior.
+// ENUMs:
+// OPENSRC_INV Open Source
+// Inverted input / output
+// OPENSRC Open Source
+// Normal input / output
+// OPENDR_INV Open Drain
+// Inverted input / output
+// OPENDR Open Drain,
+// Normal input / output
+// INV Inverted input / ouput
+// NORMAL Normal input / output
+#define IOC_IOCFG19_IOMODE_W 3
+#define IOC_IOCFG19_IOMODE_M 0x07000000
+#define IOC_IOCFG19_IOMODE_S 24
+#define IOC_IOCFG19_IOMODE_OPENSRC_INV 0x07000000
+#define IOC_IOCFG19_IOMODE_OPENSRC 0x06000000
+#define IOC_IOCFG19_IOMODE_OPENDR_INV 0x05000000
+#define IOC_IOCFG19_IOMODE_OPENDR 0x04000000
+#define IOC_IOCFG19_IOMODE_INV 0x01000000
+#define IOC_IOCFG19_IOMODE_NORMAL 0x00000000
+
+// Field: [23] IOEV_AON_PROG2_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG2 event
+// 1: Input edge detection asserts AON_PROG2 event
+#define IOC_IOCFG19_IOEV_AON_PROG2_EN 0x00800000
+#define IOC_IOCFG19_IOEV_AON_PROG2_EN_BITN 23
+#define IOC_IOCFG19_IOEV_AON_PROG2_EN_M 0x00800000
+#define IOC_IOCFG19_IOEV_AON_PROG2_EN_S 23
+
+// Field: [22] IOEV_AON_PROG1_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG1 event
+// 1: Input edge detection asserts AON_PROG1 event
+#define IOC_IOCFG19_IOEV_AON_PROG1_EN 0x00400000
+#define IOC_IOCFG19_IOEV_AON_PROG1_EN_BITN 22
+#define IOC_IOCFG19_IOEV_AON_PROG1_EN_M 0x00400000
+#define IOC_IOCFG19_IOEV_AON_PROG1_EN_S 22
+
+// Field: [21] IOEV_AON_PROG0_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG0 event
+// 1: Input edge detection asserts AON_PROG0 event
+#define IOC_IOCFG19_IOEV_AON_PROG0_EN 0x00200000
+#define IOC_IOCFG19_IOEV_AON_PROG0_EN_BITN 21
+#define IOC_IOCFG19_IOEV_AON_PROG0_EN_M 0x00200000
+#define IOC_IOCFG19_IOEV_AON_PROG0_EN_S 21
+
+// Field: [18] EDGE_IRQ_EN
+//
+// 0: No interrupt generation
+// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is
+// enabled)
+#define IOC_IOCFG19_EDGE_IRQ_EN 0x00040000
+#define IOC_IOCFG19_EDGE_IRQ_EN_BITN 18
+#define IOC_IOCFG19_EDGE_IRQ_EN_M 0x00040000
+#define IOC_IOCFG19_EDGE_IRQ_EN_S 18
+
+// Field: [17:16] EDGE_DET
+//
+// Enable generation of edge detection events on this IO
+// ENUMs:
+// BOTH Positive and negative edge detection
+// POS Positive edge detection
+// NEG Negative edge detection
+// NONE No edge detection
+#define IOC_IOCFG19_EDGE_DET_W 2
+#define IOC_IOCFG19_EDGE_DET_M 0x00030000
+#define IOC_IOCFG19_EDGE_DET_S 16
+#define IOC_IOCFG19_EDGE_DET_BOTH 0x00030000
+#define IOC_IOCFG19_EDGE_DET_POS 0x00020000
+#define IOC_IOCFG19_EDGE_DET_NEG 0x00010000
+#define IOC_IOCFG19_EDGE_DET_NONE 0x00000000
+
+// Field: [14:13] PULL_CTL
+//
+// Pull control
+// ENUMs:
+// DIS No pull
+// UP Pull up
+// DWN Pull down
+#define IOC_IOCFG19_PULL_CTL_W 2
+#define IOC_IOCFG19_PULL_CTL_M 0x00006000
+#define IOC_IOCFG19_PULL_CTL_S 13
+#define IOC_IOCFG19_PULL_CTL_DIS 0x00006000
+#define IOC_IOCFG19_PULL_CTL_UP 0x00004000
+#define IOC_IOCFG19_PULL_CTL_DWN 0x00002000
+
+// Field: [12] SLEW_RED
+//
+// 0: Normal slew rate
+// 1: Enables reduced slew rate in output driver.
+#define IOC_IOCFG19_SLEW_RED 0x00001000
+#define IOC_IOCFG19_SLEW_RED_BITN 12
+#define IOC_IOCFG19_SLEW_RED_M 0x00001000
+#define IOC_IOCFG19_SLEW_RED_S 12
+
+// Field: [11:10] IOCURR
+//
+// Selects IO current mode of this IO.
+// ENUMs:
+// 4_8MA Extended-Current (EC) mode: Min 8 mA for double
+// drive strength IOs (min 4 mA for normal IOs)
+// when IOSTR is set to AUTO
+// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set
+// to AUTO
+// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set
+// to AUTO
+#define IOC_IOCFG19_IOCURR_W 2
+#define IOC_IOCFG19_IOCURR_M 0x00000C00
+#define IOC_IOCFG19_IOCURR_S 10
+#define IOC_IOCFG19_IOCURR_4_8MA 0x00000800
+#define IOC_IOCFG19_IOCURR_4MA 0x00000400
+#define IOC_IOCFG19_IOCURR_2MA 0x00000000
+
+// Field: [9:8] IOSTR
+//
+// Select source for drive strength control of this IO.
+// This setting controls the drive strength of the Low-Current (LC) mode.
+// Higher drive strength can be selected in IOCURR
+// ENUMs:
+// MAX Maximum drive strength, controlled by
+// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default
+// values)
+// MED Medium drive strength, controlled by
+// AON_IOC:IOSTRMED (min 2 mA @2.5V with default
+// values)
+// MIN Minimum drive strength, controlled by
+// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default
+// values)
+// AUTO Automatic drive strength, controlled by AON BATMON
+// based on battery voltage. (min 2 mA @VDDS)
+#define IOC_IOCFG19_IOSTR_W 2
+#define IOC_IOCFG19_IOSTR_M 0x00000300
+#define IOC_IOCFG19_IOSTR_S 8
+#define IOC_IOCFG19_IOSTR_MAX 0x00000300
+#define IOC_IOCFG19_IOSTR_MED 0x00000200
+#define IOC_IOCFG19_IOSTR_MIN 0x00000100
+#define IOC_IOCFG19_IOSTR_AUTO 0x00000000
+
+// Field: [7] IOEV_RTC_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert RTC event
+// 1: Input edge detection asserts RTC event
+#define IOC_IOCFG19_IOEV_RTC_EN 0x00000080
+#define IOC_IOCFG19_IOEV_RTC_EN_BITN 7
+#define IOC_IOCFG19_IOEV_RTC_EN_M 0x00000080
+#define IOC_IOCFG19_IOEV_RTC_EN_S 7
+
+// Field: [6] IOEV_MCU_WU_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert MCU_WU event
+// 1: Input edge detection asserts MCU_WU event
+#define IOC_IOCFG19_IOEV_MCU_WU_EN 0x00000040
+#define IOC_IOCFG19_IOEV_MCU_WU_EN_BITN 6
+#define IOC_IOCFG19_IOEV_MCU_WU_EN_M 0x00000040
+#define IOC_IOCFG19_IOEV_MCU_WU_EN_S 6
+
+// Field: [5:0] PORT_ID
+//
+// Selects usage for DIO19
+// ENUMs:
+// RFC_SMI_CL_IN RF Core SMI Command Link In
+// RFC_SMI_CL_OUT RF Core SMI Command Link Out
+// RFC_SMI_DL_IN RF Core SMI Data Link In
+// RFC_SMI_DL_OUT RF Core SMI Data Link Out
+// RFC_GPI1 RF Core Data In 1
+// RFC_GPI0 RF Core Data In 0
+// RFC_GPO3 RF Core Data Out 3
+// RFC_GPO2 RF Core Data Out 2
+// RFC_GPO1 RF Core Data Out 1
+// RFC_GPO0 RF Core Data Out 0
+// RFC_TRC RF Core Trace
+// I2S_MCLK I2S MCLK
+// I2S_BCLK I2S BCLK
+// I2S_WCLK I2S WCLK
+// I2S_AD1 I2S Data 1
+// I2S_AD0 I2S Data 0
+// SSI1_CLK SSI1 CLK
+// SSI1_FSS SSI1 FSS
+// SSI1_TX SSI1 TX
+// SSI1_RX SSI1 RX
+// CPU_SWV CPU SWV
+// PORT_EVENT7 PORT EVENT 7
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT6 PORT EVENT 6
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT5 PORT EVENT 5
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT4 PORT EVENT 4
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT3 PORT EVENT 3
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT2 PORT EVENT 2
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT1 PORT EVENT 1
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT0 PORT EVENT 0
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// UART1_RTS UART1 RTS
+// UART1_CTS UART1 CTS
+// UART1_TX UART1 TX
+// UART1_RX UART1 RX
+// UART0_RTS UART0 RTS
+// UART0_CTS UART0 CTS
+// UART0_TX UART0 TX
+// UART0_RX UART0 RX
+// I2C_MSSCL I2C Clock
+// I2C_MSSDA I2C Data
+// SSI0_CLK SSI0 CLK
+// SSI0_FSS SSI0 FSS
+// SSI0_TX SSI0 TX
+// SSI0_RX SSI0 RX
+// AUX_IO AUX IO
+// AON_CLK32K AON 32 KHz clock (SCLK_LF)
+// GPIO General Purpose IO
+#define IOC_IOCFG19_PORT_ID_W 6
+#define IOC_IOCFG19_PORT_ID_M 0x0000003F
+#define IOC_IOCFG19_PORT_ID_S 0
+#define IOC_IOCFG19_PORT_ID_RFC_SMI_CL_IN 0x00000038
+#define IOC_IOCFG19_PORT_ID_RFC_SMI_CL_OUT 0x00000037
+#define IOC_IOCFG19_PORT_ID_RFC_SMI_DL_IN 0x00000036
+#define IOC_IOCFG19_PORT_ID_RFC_SMI_DL_OUT 0x00000035
+#define IOC_IOCFG19_PORT_ID_RFC_GPI1 0x00000034
+#define IOC_IOCFG19_PORT_ID_RFC_GPI0 0x00000033
+#define IOC_IOCFG19_PORT_ID_RFC_GPO3 0x00000032
+#define IOC_IOCFG19_PORT_ID_RFC_GPO2 0x00000031
+#define IOC_IOCFG19_PORT_ID_RFC_GPO1 0x00000030
+#define IOC_IOCFG19_PORT_ID_RFC_GPO0 0x0000002F
+#define IOC_IOCFG19_PORT_ID_RFC_TRC 0x0000002E
+#define IOC_IOCFG19_PORT_ID_I2S_MCLK 0x00000029
+#define IOC_IOCFG19_PORT_ID_I2S_BCLK 0x00000028
+#define IOC_IOCFG19_PORT_ID_I2S_WCLK 0x00000027
+#define IOC_IOCFG19_PORT_ID_I2S_AD1 0x00000026
+#define IOC_IOCFG19_PORT_ID_I2S_AD0 0x00000025
+#define IOC_IOCFG19_PORT_ID_SSI1_CLK 0x00000024
+#define IOC_IOCFG19_PORT_ID_SSI1_FSS 0x00000023
+#define IOC_IOCFG19_PORT_ID_SSI1_TX 0x00000022
+#define IOC_IOCFG19_PORT_ID_SSI1_RX 0x00000021
+#define IOC_IOCFG19_PORT_ID_CPU_SWV 0x00000020
+#define IOC_IOCFG19_PORT_ID_PORT_EVENT7 0x0000001E
+#define IOC_IOCFG19_PORT_ID_PORT_EVENT6 0x0000001D
+#define IOC_IOCFG19_PORT_ID_PORT_EVENT5 0x0000001C
+#define IOC_IOCFG19_PORT_ID_PORT_EVENT4 0x0000001B
+#define IOC_IOCFG19_PORT_ID_PORT_EVENT3 0x0000001A
+#define IOC_IOCFG19_PORT_ID_PORT_EVENT2 0x00000019
+#define IOC_IOCFG19_PORT_ID_PORT_EVENT1 0x00000018
+#define IOC_IOCFG19_PORT_ID_PORT_EVENT0 0x00000017
+#define IOC_IOCFG19_PORT_ID_UART1_RTS 0x00000016
+#define IOC_IOCFG19_PORT_ID_UART1_CTS 0x00000015
+#define IOC_IOCFG19_PORT_ID_UART1_TX 0x00000014
+#define IOC_IOCFG19_PORT_ID_UART1_RX 0x00000013
+#define IOC_IOCFG19_PORT_ID_UART0_RTS 0x00000012
+#define IOC_IOCFG19_PORT_ID_UART0_CTS 0x00000011
+#define IOC_IOCFG19_PORT_ID_UART0_TX 0x00000010
+#define IOC_IOCFG19_PORT_ID_UART0_RX 0x0000000F
+#define IOC_IOCFG19_PORT_ID_I2C_MSSCL 0x0000000E
+#define IOC_IOCFG19_PORT_ID_I2C_MSSDA 0x0000000D
+#define IOC_IOCFG19_PORT_ID_SSI0_CLK 0x0000000C
+#define IOC_IOCFG19_PORT_ID_SSI0_FSS 0x0000000B
+#define IOC_IOCFG19_PORT_ID_SSI0_TX 0x0000000A
+#define IOC_IOCFG19_PORT_ID_SSI0_RX 0x00000009
+#define IOC_IOCFG19_PORT_ID_AUX_IO 0x00000008
+#define IOC_IOCFG19_PORT_ID_AON_CLK32K 0x00000007
+#define IOC_IOCFG19_PORT_ID_GPIO 0x00000000
+
+//*****************************************************************************
+//
+// Register: IOC_O_IOCFG20
+//
+//*****************************************************************************
+// Field: [30] HYST_EN
+//
+// 0: Input hysteresis disable
+// 1: Input hysteresis enable
+#define IOC_IOCFG20_HYST_EN 0x40000000
+#define IOC_IOCFG20_HYST_EN_BITN 30
+#define IOC_IOCFG20_HYST_EN_M 0x40000000
+#define IOC_IOCFG20_HYST_EN_S 30
+
+// Field: [29] IE
+//
+// 0: Input disabled
+// 1: Input enabled
+//
+// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be
+// ignored.
+#define IOC_IOCFG20_IE 0x20000000
+#define IOC_IOCFG20_IE_BITN 29
+#define IOC_IOCFG20_IE_M 0x20000000
+#define IOC_IOCFG20_IE_S 29
+
+// Field: [28:27] WU_CFG
+//
+// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or
+// >0x08:
+//
+// 00: No wake-up
+// 01: No wake-up
+// 10: Wakes up from shutdown if this pad is going low.
+// 11: Wakes up from shutdown if this pad is going high.
+//
+// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08,
+// this register only sets wakeup enable or not.
+//
+// 00, 01: Wakeup disabled
+// 10, 11: Wakeup enabled
+//
+// Polarity is controlled from AON registers.
+//
+// Note:When the MSB is set, the IOC will deactivate the output enable for the
+// DIO.
+#define IOC_IOCFG20_WU_CFG_W 2
+#define IOC_IOCFG20_WU_CFG_M 0x18000000
+#define IOC_IOCFG20_WU_CFG_S 27
+
+// Field: [26:24] IOMODE
+//
+// IO Mode
+// Not applicable for IO configured for AON periph. signals and AUX PORT_ID
+// 0x01-0x08
+// AUX has its own open_source/drain configuration.
+//
+// 0x2: Reserved. Undefined behavior.
+// 0x3: Reserved. Undefined behavior.
+// ENUMs:
+// OPENSRC_INV Open Source
+// Inverted input / output
+// OPENSRC Open Source
+// Normal input / output
+// OPENDR_INV Open Drain
+// Inverted input / output
+// OPENDR Open Drain,
+// Normal input / output
+// INV Inverted input / ouput
+// NORMAL Normal input / output
+#define IOC_IOCFG20_IOMODE_W 3
+#define IOC_IOCFG20_IOMODE_M 0x07000000
+#define IOC_IOCFG20_IOMODE_S 24
+#define IOC_IOCFG20_IOMODE_OPENSRC_INV 0x07000000
+#define IOC_IOCFG20_IOMODE_OPENSRC 0x06000000
+#define IOC_IOCFG20_IOMODE_OPENDR_INV 0x05000000
+#define IOC_IOCFG20_IOMODE_OPENDR 0x04000000
+#define IOC_IOCFG20_IOMODE_INV 0x01000000
+#define IOC_IOCFG20_IOMODE_NORMAL 0x00000000
+
+// Field: [23] IOEV_AON_PROG2_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG2 event
+// 1: Input edge detection asserts AON_PROG2 event
+#define IOC_IOCFG20_IOEV_AON_PROG2_EN 0x00800000
+#define IOC_IOCFG20_IOEV_AON_PROG2_EN_BITN 23
+#define IOC_IOCFG20_IOEV_AON_PROG2_EN_M 0x00800000
+#define IOC_IOCFG20_IOEV_AON_PROG2_EN_S 23
+
+// Field: [22] IOEV_AON_PROG1_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG1 event
+// 1: Input edge detection asserts AON_PROG1 event
+#define IOC_IOCFG20_IOEV_AON_PROG1_EN 0x00400000
+#define IOC_IOCFG20_IOEV_AON_PROG1_EN_BITN 22
+#define IOC_IOCFG20_IOEV_AON_PROG1_EN_M 0x00400000
+#define IOC_IOCFG20_IOEV_AON_PROG1_EN_S 22
+
+// Field: [21] IOEV_AON_PROG0_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG0 event
+// 1: Input edge detection asserts AON_PROG0 event
+#define IOC_IOCFG20_IOEV_AON_PROG0_EN 0x00200000
+#define IOC_IOCFG20_IOEV_AON_PROG0_EN_BITN 21
+#define IOC_IOCFG20_IOEV_AON_PROG0_EN_M 0x00200000
+#define IOC_IOCFG20_IOEV_AON_PROG0_EN_S 21
+
+// Field: [18] EDGE_IRQ_EN
+//
+// 0: No interrupt generation
+// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is
+// enabled)
+#define IOC_IOCFG20_EDGE_IRQ_EN 0x00040000
+#define IOC_IOCFG20_EDGE_IRQ_EN_BITN 18
+#define IOC_IOCFG20_EDGE_IRQ_EN_M 0x00040000
+#define IOC_IOCFG20_EDGE_IRQ_EN_S 18
+
+// Field: [17:16] EDGE_DET
+//
+// Enable generation of edge detection events on this IO
+// ENUMs:
+// BOTH Positive and negative edge detection
+// POS Positive edge detection
+// NEG Negative edge detection
+// NONE No edge detection
+#define IOC_IOCFG20_EDGE_DET_W 2
+#define IOC_IOCFG20_EDGE_DET_M 0x00030000
+#define IOC_IOCFG20_EDGE_DET_S 16
+#define IOC_IOCFG20_EDGE_DET_BOTH 0x00030000
+#define IOC_IOCFG20_EDGE_DET_POS 0x00020000
+#define IOC_IOCFG20_EDGE_DET_NEG 0x00010000
+#define IOC_IOCFG20_EDGE_DET_NONE 0x00000000
+
+// Field: [14:13] PULL_CTL
+//
+// Pull control
+// ENUMs:
+// DIS No pull
+// UP Pull up
+// DWN Pull down
+#define IOC_IOCFG20_PULL_CTL_W 2
+#define IOC_IOCFG20_PULL_CTL_M 0x00006000
+#define IOC_IOCFG20_PULL_CTL_S 13
+#define IOC_IOCFG20_PULL_CTL_DIS 0x00006000
+#define IOC_IOCFG20_PULL_CTL_UP 0x00004000
+#define IOC_IOCFG20_PULL_CTL_DWN 0x00002000
+
+// Field: [12] SLEW_RED
+//
+// 0: Normal slew rate
+// 1: Enables reduced slew rate in output driver.
+#define IOC_IOCFG20_SLEW_RED 0x00001000
+#define IOC_IOCFG20_SLEW_RED_BITN 12
+#define IOC_IOCFG20_SLEW_RED_M 0x00001000
+#define IOC_IOCFG20_SLEW_RED_S 12
+
+// Field: [11:10] IOCURR
+//
+// Selects IO current mode of this IO.
+// ENUMs:
+// 4_8MA Extended-Current (EC) mode: Min 8 mA for double
+// drive strength IOs (min 4 mA for normal IOs)
+// when IOSTR is set to AUTO
+// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set
+// to AUTO
+// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set
+// to AUTO
+#define IOC_IOCFG20_IOCURR_W 2
+#define IOC_IOCFG20_IOCURR_M 0x00000C00
+#define IOC_IOCFG20_IOCURR_S 10
+#define IOC_IOCFG20_IOCURR_4_8MA 0x00000800
+#define IOC_IOCFG20_IOCURR_4MA 0x00000400
+#define IOC_IOCFG20_IOCURR_2MA 0x00000000
+
+// Field: [9:8] IOSTR
+//
+// Select source for drive strength control of this IO.
+// This setting controls the drive strength of the Low-Current (LC) mode.
+// Higher drive strength can be selected in IOCURR
+// ENUMs:
+// MAX Maximum drive strength, controlled by
+// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default
+// values)
+// MED Medium drive strength, controlled by
+// AON_IOC:IOSTRMED (min 2 mA @2.5V with default
+// values)
+// MIN Minimum drive strength, controlled by
+// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default
+// values)
+// AUTO Automatic drive strength, controlled by AON BATMON
+// based on battery voltage. (min 2 mA @VDDS)
+#define IOC_IOCFG20_IOSTR_W 2
+#define IOC_IOCFG20_IOSTR_M 0x00000300
+#define IOC_IOCFG20_IOSTR_S 8
+#define IOC_IOCFG20_IOSTR_MAX 0x00000300
+#define IOC_IOCFG20_IOSTR_MED 0x00000200
+#define IOC_IOCFG20_IOSTR_MIN 0x00000100
+#define IOC_IOCFG20_IOSTR_AUTO 0x00000000
+
+// Field: [7] IOEV_RTC_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert RTC event
+// 1: Input edge detection asserts RTC event
+#define IOC_IOCFG20_IOEV_RTC_EN 0x00000080
+#define IOC_IOCFG20_IOEV_RTC_EN_BITN 7
+#define IOC_IOCFG20_IOEV_RTC_EN_M 0x00000080
+#define IOC_IOCFG20_IOEV_RTC_EN_S 7
+
+// Field: [6] IOEV_MCU_WU_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert MCU_WU event
+// 1: Input edge detection asserts MCU_WU event
+#define IOC_IOCFG20_IOEV_MCU_WU_EN 0x00000040
+#define IOC_IOCFG20_IOEV_MCU_WU_EN_BITN 6
+#define IOC_IOCFG20_IOEV_MCU_WU_EN_M 0x00000040
+#define IOC_IOCFG20_IOEV_MCU_WU_EN_S 6
+
+// Field: [5:0] PORT_ID
+//
+// Selects usage for DIO20
+// ENUMs:
+// RFC_SMI_CL_IN RF Core SMI Command Link In
+// RFC_SMI_CL_OUT RF Core SMI Command Link Out
+// RFC_SMI_DL_IN RF Core SMI Data Link In
+// RFC_SMI_DL_OUT RF Core SMI Data Link Out
+// RFC_GPI1 RF Core Data In 1
+// RFC_GPI0 RF Core Data In 0
+// RFC_GPO3 RF Core Data Out 3
+// RFC_GPO2 RF Core Data Out 2
+// RFC_GPO1 RF Core Data Out 1
+// RFC_GPO0 RF Core Data Out 0
+// RFC_TRC RF Core Trace
+// I2S_MCLK I2S MCLK
+// I2S_BCLK I2S BCLK
+// I2S_WCLK I2S WCLK
+// I2S_AD1 I2S Data 1
+// I2S_AD0 I2S Data 0
+// SSI1_CLK SSI1 CLK
+// SSI1_FSS SSI1 FSS
+// SSI1_TX SSI1 TX
+// SSI1_RX SSI1 RX
+// CPU_SWV CPU SWV
+// PORT_EVENT7 PORT EVENT 7
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT6 PORT EVENT 6
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT5 PORT EVENT 5
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT4 PORT EVENT 4
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT3 PORT EVENT 3
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT2 PORT EVENT 2
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT1 PORT EVENT 1
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT0 PORT EVENT 0
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// UART1_RTS UART1 RTS
+// UART1_CTS UART1 CTS
+// UART1_TX UART1 TX
+// UART1_RX UART1 RX
+// UART0_RTS UART0 RTS
+// UART0_CTS UART0 CTS
+// UART0_TX UART0 TX
+// UART0_RX UART0 RX
+// I2C_MSSCL I2C Clock
+// I2C_MSSDA I2C Data
+// SSI0_CLK SSI0 CLK
+// SSI0_FSS SSI0 FSS
+// SSI0_TX SSI0 TX
+// SSI0_RX SSI0 RX
+// AUX_IO AUX IO
+// AON_CLK32K AON 32 KHz clock (SCLK_LF)
+// GPIO General Purpose IO
+#define IOC_IOCFG20_PORT_ID_W 6
+#define IOC_IOCFG20_PORT_ID_M 0x0000003F
+#define IOC_IOCFG20_PORT_ID_S 0
+#define IOC_IOCFG20_PORT_ID_RFC_SMI_CL_IN 0x00000038
+#define IOC_IOCFG20_PORT_ID_RFC_SMI_CL_OUT 0x00000037
+#define IOC_IOCFG20_PORT_ID_RFC_SMI_DL_IN 0x00000036
+#define IOC_IOCFG20_PORT_ID_RFC_SMI_DL_OUT 0x00000035
+#define IOC_IOCFG20_PORT_ID_RFC_GPI1 0x00000034
+#define IOC_IOCFG20_PORT_ID_RFC_GPI0 0x00000033
+#define IOC_IOCFG20_PORT_ID_RFC_GPO3 0x00000032
+#define IOC_IOCFG20_PORT_ID_RFC_GPO2 0x00000031
+#define IOC_IOCFG20_PORT_ID_RFC_GPO1 0x00000030
+#define IOC_IOCFG20_PORT_ID_RFC_GPO0 0x0000002F
+#define IOC_IOCFG20_PORT_ID_RFC_TRC 0x0000002E
+#define IOC_IOCFG20_PORT_ID_I2S_MCLK 0x00000029
+#define IOC_IOCFG20_PORT_ID_I2S_BCLK 0x00000028
+#define IOC_IOCFG20_PORT_ID_I2S_WCLK 0x00000027
+#define IOC_IOCFG20_PORT_ID_I2S_AD1 0x00000026
+#define IOC_IOCFG20_PORT_ID_I2S_AD0 0x00000025
+#define IOC_IOCFG20_PORT_ID_SSI1_CLK 0x00000024
+#define IOC_IOCFG20_PORT_ID_SSI1_FSS 0x00000023
+#define IOC_IOCFG20_PORT_ID_SSI1_TX 0x00000022
+#define IOC_IOCFG20_PORT_ID_SSI1_RX 0x00000021
+#define IOC_IOCFG20_PORT_ID_CPU_SWV 0x00000020
+#define IOC_IOCFG20_PORT_ID_PORT_EVENT7 0x0000001E
+#define IOC_IOCFG20_PORT_ID_PORT_EVENT6 0x0000001D
+#define IOC_IOCFG20_PORT_ID_PORT_EVENT5 0x0000001C
+#define IOC_IOCFG20_PORT_ID_PORT_EVENT4 0x0000001B
+#define IOC_IOCFG20_PORT_ID_PORT_EVENT3 0x0000001A
+#define IOC_IOCFG20_PORT_ID_PORT_EVENT2 0x00000019
+#define IOC_IOCFG20_PORT_ID_PORT_EVENT1 0x00000018
+#define IOC_IOCFG20_PORT_ID_PORT_EVENT0 0x00000017
+#define IOC_IOCFG20_PORT_ID_UART1_RTS 0x00000016
+#define IOC_IOCFG20_PORT_ID_UART1_CTS 0x00000015
+#define IOC_IOCFG20_PORT_ID_UART1_TX 0x00000014
+#define IOC_IOCFG20_PORT_ID_UART1_RX 0x00000013
+#define IOC_IOCFG20_PORT_ID_UART0_RTS 0x00000012
+#define IOC_IOCFG20_PORT_ID_UART0_CTS 0x00000011
+#define IOC_IOCFG20_PORT_ID_UART0_TX 0x00000010
+#define IOC_IOCFG20_PORT_ID_UART0_RX 0x0000000F
+#define IOC_IOCFG20_PORT_ID_I2C_MSSCL 0x0000000E
+#define IOC_IOCFG20_PORT_ID_I2C_MSSDA 0x0000000D
+#define IOC_IOCFG20_PORT_ID_SSI0_CLK 0x0000000C
+#define IOC_IOCFG20_PORT_ID_SSI0_FSS 0x0000000B
+#define IOC_IOCFG20_PORT_ID_SSI0_TX 0x0000000A
+#define IOC_IOCFG20_PORT_ID_SSI0_RX 0x00000009
+#define IOC_IOCFG20_PORT_ID_AUX_IO 0x00000008
+#define IOC_IOCFG20_PORT_ID_AON_CLK32K 0x00000007
+#define IOC_IOCFG20_PORT_ID_GPIO 0x00000000
+
+//*****************************************************************************
+//
+// Register: IOC_O_IOCFG21
+//
+//*****************************************************************************
+// Field: [30] HYST_EN
+//
+// 0: Input hysteresis disable
+// 1: Input hysteresis enable
+#define IOC_IOCFG21_HYST_EN 0x40000000
+#define IOC_IOCFG21_HYST_EN_BITN 30
+#define IOC_IOCFG21_HYST_EN_M 0x40000000
+#define IOC_IOCFG21_HYST_EN_S 30
+
+// Field: [29] IE
+//
+// 0: Input disabled
+// 1: Input enabled
+//
+// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be
+// ignored.
+#define IOC_IOCFG21_IE 0x20000000
+#define IOC_IOCFG21_IE_BITN 29
+#define IOC_IOCFG21_IE_M 0x20000000
+#define IOC_IOCFG21_IE_S 29
+
+// Field: [28:27] WU_CFG
+//
+// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or
+// >0x08:
+//
+// 00: No wake-up
+// 01: No wake-up
+// 10: Wakes up from shutdown if this pad is going low.
+// 11: Wakes up from shutdown if this pad is going high.
+//
+// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08,
+// this register only sets wakeup enable or not.
+//
+// 00, 01: Wakeup disabled
+// 10, 11: Wakeup enabled
+//
+// Polarity is controlled from AON registers.
+//
+// Note:When the MSB is set, the IOC will deactivate the output enable for the
+// DIO.
+#define IOC_IOCFG21_WU_CFG_W 2
+#define IOC_IOCFG21_WU_CFG_M 0x18000000
+#define IOC_IOCFG21_WU_CFG_S 27
+
+// Field: [26:24] IOMODE
+//
+// IO Mode
+// Not applicable for IO configured for AON periph. signals and AUX PORT_ID
+// 0x01-0x08
+// AUX has its own open_source/drain configuration.
+//
+// 0x2: Reserved. Undefined behavior.
+// 0x3: Reserved. Undefined behavior.
+// ENUMs:
+// OPENSRC_INV Open Source
+// Inverted input / output
+// OPENSRC Open Source
+// Normal input / output
+// OPENDR_INV Open Drain
+// Inverted input / output
+// OPENDR Open Drain,
+// Normal input / output
+// INV Inverted input / ouput
+// NORMAL Normal input / output
+#define IOC_IOCFG21_IOMODE_W 3
+#define IOC_IOCFG21_IOMODE_M 0x07000000
+#define IOC_IOCFG21_IOMODE_S 24
+#define IOC_IOCFG21_IOMODE_OPENSRC_INV 0x07000000
+#define IOC_IOCFG21_IOMODE_OPENSRC 0x06000000
+#define IOC_IOCFG21_IOMODE_OPENDR_INV 0x05000000
+#define IOC_IOCFG21_IOMODE_OPENDR 0x04000000
+#define IOC_IOCFG21_IOMODE_INV 0x01000000
+#define IOC_IOCFG21_IOMODE_NORMAL 0x00000000
+
+// Field: [23] IOEV_AON_PROG2_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG2 event
+// 1: Input edge detection asserts AON_PROG2 event
+#define IOC_IOCFG21_IOEV_AON_PROG2_EN 0x00800000
+#define IOC_IOCFG21_IOEV_AON_PROG2_EN_BITN 23
+#define IOC_IOCFG21_IOEV_AON_PROG2_EN_M 0x00800000
+#define IOC_IOCFG21_IOEV_AON_PROG2_EN_S 23
+
+// Field: [22] IOEV_AON_PROG1_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG1 event
+// 1: Input edge detection asserts AON_PROG1 event
+#define IOC_IOCFG21_IOEV_AON_PROG1_EN 0x00400000
+#define IOC_IOCFG21_IOEV_AON_PROG1_EN_BITN 22
+#define IOC_IOCFG21_IOEV_AON_PROG1_EN_M 0x00400000
+#define IOC_IOCFG21_IOEV_AON_PROG1_EN_S 22
+
+// Field: [21] IOEV_AON_PROG0_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG0 event
+// 1: Input edge detection asserts AON_PROG0 event
+#define IOC_IOCFG21_IOEV_AON_PROG0_EN 0x00200000
+#define IOC_IOCFG21_IOEV_AON_PROG0_EN_BITN 21
+#define IOC_IOCFG21_IOEV_AON_PROG0_EN_M 0x00200000
+#define IOC_IOCFG21_IOEV_AON_PROG0_EN_S 21
+
+// Field: [18] EDGE_IRQ_EN
+//
+// 0: No interrupt generation
+// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is
+// enabled)
+#define IOC_IOCFG21_EDGE_IRQ_EN 0x00040000
+#define IOC_IOCFG21_EDGE_IRQ_EN_BITN 18
+#define IOC_IOCFG21_EDGE_IRQ_EN_M 0x00040000
+#define IOC_IOCFG21_EDGE_IRQ_EN_S 18
+
+// Field: [17:16] EDGE_DET
+//
+// Enable generation of edge detection events on this IO
+// ENUMs:
+// BOTH Positive and negative edge detection
+// POS Positive edge detection
+// NEG Negative edge detection
+// NONE No edge detection
+#define IOC_IOCFG21_EDGE_DET_W 2
+#define IOC_IOCFG21_EDGE_DET_M 0x00030000
+#define IOC_IOCFG21_EDGE_DET_S 16
+#define IOC_IOCFG21_EDGE_DET_BOTH 0x00030000
+#define IOC_IOCFG21_EDGE_DET_POS 0x00020000
+#define IOC_IOCFG21_EDGE_DET_NEG 0x00010000
+#define IOC_IOCFG21_EDGE_DET_NONE 0x00000000
+
+// Field: [14:13] PULL_CTL
+//
+// Pull control
+// ENUMs:
+// DIS No pull
+// UP Pull up
+// DWN Pull down
+#define IOC_IOCFG21_PULL_CTL_W 2
+#define IOC_IOCFG21_PULL_CTL_M 0x00006000
+#define IOC_IOCFG21_PULL_CTL_S 13
+#define IOC_IOCFG21_PULL_CTL_DIS 0x00006000
+#define IOC_IOCFG21_PULL_CTL_UP 0x00004000
+#define IOC_IOCFG21_PULL_CTL_DWN 0x00002000
+
+// Field: [12] SLEW_RED
+//
+// 0: Normal slew rate
+// 1: Enables reduced slew rate in output driver.
+#define IOC_IOCFG21_SLEW_RED 0x00001000
+#define IOC_IOCFG21_SLEW_RED_BITN 12
+#define IOC_IOCFG21_SLEW_RED_M 0x00001000
+#define IOC_IOCFG21_SLEW_RED_S 12
+
+// Field: [11:10] IOCURR
+//
+// Selects IO current mode of this IO.
+// ENUMs:
+// 4_8MA Extended-Current (EC) mode: Min 8 mA for double
+// drive strength IOs (min 4 mA for normal IOs)
+// when IOSTR is set to AUTO
+// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set
+// to AUTO
+// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set
+// to AUTO
+#define IOC_IOCFG21_IOCURR_W 2
+#define IOC_IOCFG21_IOCURR_M 0x00000C00
+#define IOC_IOCFG21_IOCURR_S 10
+#define IOC_IOCFG21_IOCURR_4_8MA 0x00000800
+#define IOC_IOCFG21_IOCURR_4MA 0x00000400
+#define IOC_IOCFG21_IOCURR_2MA 0x00000000
+
+// Field: [9:8] IOSTR
+//
+// Select source for drive strength control of this IO.
+// This setting controls the drive strength of the Low-Current (LC) mode.
+// Higher drive strength can be selected in IOCURR
+// ENUMs:
+// MAX Maximum drive strength, controlled by
+// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default
+// values)
+// MED Medium drive strength, controlled by
+// AON_IOC:IOSTRMED (min 2 mA @2.5V with default
+// values)
+// MIN Minimum drive strength, controlled by
+// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default
+// values)
+// AUTO Automatic drive strength, controlled by AON BATMON
+// based on battery voltage. (min 2 mA @VDDS)
+#define IOC_IOCFG21_IOSTR_W 2
+#define IOC_IOCFG21_IOSTR_M 0x00000300
+#define IOC_IOCFG21_IOSTR_S 8
+#define IOC_IOCFG21_IOSTR_MAX 0x00000300
+#define IOC_IOCFG21_IOSTR_MED 0x00000200
+#define IOC_IOCFG21_IOSTR_MIN 0x00000100
+#define IOC_IOCFG21_IOSTR_AUTO 0x00000000
+
+// Field: [7] IOEV_RTC_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert RTC event
+// 1: Input edge detection asserts RTC event
+#define IOC_IOCFG21_IOEV_RTC_EN 0x00000080
+#define IOC_IOCFG21_IOEV_RTC_EN_BITN 7
+#define IOC_IOCFG21_IOEV_RTC_EN_M 0x00000080
+#define IOC_IOCFG21_IOEV_RTC_EN_S 7
+
+// Field: [6] IOEV_MCU_WU_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert MCU_WU event
+// 1: Input edge detection asserts MCU_WU event
+#define IOC_IOCFG21_IOEV_MCU_WU_EN 0x00000040
+#define IOC_IOCFG21_IOEV_MCU_WU_EN_BITN 6
+#define IOC_IOCFG21_IOEV_MCU_WU_EN_M 0x00000040
+#define IOC_IOCFG21_IOEV_MCU_WU_EN_S 6
+
+// Field: [5:0] PORT_ID
+//
+// Selects usage for DIO21
+// ENUMs:
+// RFC_SMI_CL_IN RF Core SMI Command Link In
+// RFC_SMI_CL_OUT RF Core SMI Command Link Out
+// RFC_SMI_DL_IN RF Core SMI Data Link In
+// RFC_SMI_DL_OUT RF Core SMI Data Link Out
+// RFC_GPI1 RF Core Data In 1
+// RFC_GPI0 RF Core Data In 0
+// RFC_GPO3 RF Core Data Out 3
+// RFC_GPO2 RF Core Data Out 2
+// RFC_GPO1 RF Core Data Out 1
+// RFC_GPO0 RF Core Data Out 0
+// RFC_TRC RF Core Trace
+// I2S_MCLK I2S MCLK
+// I2S_BCLK I2S BCLK
+// I2S_WCLK I2S WCLK
+// I2S_AD1 I2S Data 1
+// I2S_AD0 I2S Data 0
+// SSI1_CLK SSI1 CLK
+// SSI1_FSS SSI1 FSS
+// SSI1_TX SSI1 TX
+// SSI1_RX SSI1 RX
+// CPU_SWV CPU SWV
+// PORT_EVENT7 PORT EVENT 7
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT6 PORT EVENT 6
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT5 PORT EVENT 5
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT4 PORT EVENT 4
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT3 PORT EVENT 3
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT2 PORT EVENT 2
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT1 PORT EVENT 1
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT0 PORT EVENT 0
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// UART1_RTS UART1 RTS
+// UART1_CTS UART1 CTS
+// UART1_TX UART1 TX
+// UART1_RX UART1 RX
+// UART0_RTS UART0 RTS
+// UART0_CTS UART0 CTS
+// UART0_TX UART0 TX
+// UART0_RX UART0 RX
+// I2C_MSSCL I2C Clock
+// I2C_MSSDA I2C Data
+// SSI0_CLK SSI0 CLK
+// SSI0_FSS SSI0 FSS
+// SSI0_TX SSI0 TX
+// SSI0_RX SSI0 RX
+// AUX_IO AUX IO
+// AON_CLK32K AON 32 KHz clock (SCLK_LF)
+// GPIO General Purpose IO
+#define IOC_IOCFG21_PORT_ID_W 6
+#define IOC_IOCFG21_PORT_ID_M 0x0000003F
+#define IOC_IOCFG21_PORT_ID_S 0
+#define IOC_IOCFG21_PORT_ID_RFC_SMI_CL_IN 0x00000038
+#define IOC_IOCFG21_PORT_ID_RFC_SMI_CL_OUT 0x00000037
+#define IOC_IOCFG21_PORT_ID_RFC_SMI_DL_IN 0x00000036
+#define IOC_IOCFG21_PORT_ID_RFC_SMI_DL_OUT 0x00000035
+#define IOC_IOCFG21_PORT_ID_RFC_GPI1 0x00000034
+#define IOC_IOCFG21_PORT_ID_RFC_GPI0 0x00000033
+#define IOC_IOCFG21_PORT_ID_RFC_GPO3 0x00000032
+#define IOC_IOCFG21_PORT_ID_RFC_GPO2 0x00000031
+#define IOC_IOCFG21_PORT_ID_RFC_GPO1 0x00000030
+#define IOC_IOCFG21_PORT_ID_RFC_GPO0 0x0000002F
+#define IOC_IOCFG21_PORT_ID_RFC_TRC 0x0000002E
+#define IOC_IOCFG21_PORT_ID_I2S_MCLK 0x00000029
+#define IOC_IOCFG21_PORT_ID_I2S_BCLK 0x00000028
+#define IOC_IOCFG21_PORT_ID_I2S_WCLK 0x00000027
+#define IOC_IOCFG21_PORT_ID_I2S_AD1 0x00000026
+#define IOC_IOCFG21_PORT_ID_I2S_AD0 0x00000025
+#define IOC_IOCFG21_PORT_ID_SSI1_CLK 0x00000024
+#define IOC_IOCFG21_PORT_ID_SSI1_FSS 0x00000023
+#define IOC_IOCFG21_PORT_ID_SSI1_TX 0x00000022
+#define IOC_IOCFG21_PORT_ID_SSI1_RX 0x00000021
+#define IOC_IOCFG21_PORT_ID_CPU_SWV 0x00000020
+#define IOC_IOCFG21_PORT_ID_PORT_EVENT7 0x0000001E
+#define IOC_IOCFG21_PORT_ID_PORT_EVENT6 0x0000001D
+#define IOC_IOCFG21_PORT_ID_PORT_EVENT5 0x0000001C
+#define IOC_IOCFG21_PORT_ID_PORT_EVENT4 0x0000001B
+#define IOC_IOCFG21_PORT_ID_PORT_EVENT3 0x0000001A
+#define IOC_IOCFG21_PORT_ID_PORT_EVENT2 0x00000019
+#define IOC_IOCFG21_PORT_ID_PORT_EVENT1 0x00000018
+#define IOC_IOCFG21_PORT_ID_PORT_EVENT0 0x00000017
+#define IOC_IOCFG21_PORT_ID_UART1_RTS 0x00000016
+#define IOC_IOCFG21_PORT_ID_UART1_CTS 0x00000015
+#define IOC_IOCFG21_PORT_ID_UART1_TX 0x00000014
+#define IOC_IOCFG21_PORT_ID_UART1_RX 0x00000013
+#define IOC_IOCFG21_PORT_ID_UART0_RTS 0x00000012
+#define IOC_IOCFG21_PORT_ID_UART0_CTS 0x00000011
+#define IOC_IOCFG21_PORT_ID_UART0_TX 0x00000010
+#define IOC_IOCFG21_PORT_ID_UART0_RX 0x0000000F
+#define IOC_IOCFG21_PORT_ID_I2C_MSSCL 0x0000000E
+#define IOC_IOCFG21_PORT_ID_I2C_MSSDA 0x0000000D
+#define IOC_IOCFG21_PORT_ID_SSI0_CLK 0x0000000C
+#define IOC_IOCFG21_PORT_ID_SSI0_FSS 0x0000000B
+#define IOC_IOCFG21_PORT_ID_SSI0_TX 0x0000000A
+#define IOC_IOCFG21_PORT_ID_SSI0_RX 0x00000009
+#define IOC_IOCFG21_PORT_ID_AUX_IO 0x00000008
+#define IOC_IOCFG21_PORT_ID_AON_CLK32K 0x00000007
+#define IOC_IOCFG21_PORT_ID_GPIO 0x00000000
+
+//*****************************************************************************
+//
+// Register: IOC_O_IOCFG22
+//
+//*****************************************************************************
+// Field: [30] HYST_EN
+//
+// 0: Input hysteresis disable
+// 1: Input hysteresis enable
+#define IOC_IOCFG22_HYST_EN 0x40000000
+#define IOC_IOCFG22_HYST_EN_BITN 30
+#define IOC_IOCFG22_HYST_EN_M 0x40000000
+#define IOC_IOCFG22_HYST_EN_S 30
+
+// Field: [29] IE
+//
+// 0: Input disabled
+// 1: Input enabled
+//
+// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be
+// ignored.
+#define IOC_IOCFG22_IE 0x20000000
+#define IOC_IOCFG22_IE_BITN 29
+#define IOC_IOCFG22_IE_M 0x20000000
+#define IOC_IOCFG22_IE_S 29
+
+// Field: [28:27] WU_CFG
+//
+// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or
+// >0x08:
+//
+// 00: No wake-up
+// 01: No wake-up
+// 10: Wakes up from shutdown if this pad is going low.
+// 11: Wakes up from shutdown if this pad is going high.
+//
+// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08,
+// this register only sets wakeup enable or not.
+//
+// 00, 01: Wakeup disabled
+// 10, 11: Wakeup enabled
+//
+// Polarity is controlled from AON registers.
+//
+// Note:When the MSB is set, the IOC will deactivate the output enable for the
+// DIO.
+#define IOC_IOCFG22_WU_CFG_W 2
+#define IOC_IOCFG22_WU_CFG_M 0x18000000
+#define IOC_IOCFG22_WU_CFG_S 27
+
+// Field: [26:24] IOMODE
+//
+// IO Mode
+// Not applicable for IO configured for AON periph. signals and AUX PORT_ID
+// 0x01-0x08
+// AUX has its own open_source/drain configuration.
+//
+// 0x2: Reserved. Undefined behavior.
+// 0x3: Reserved. Undefined behavior.
+// ENUMs:
+// OPENSRC_INV Open Source
+// Inverted input / output
+// OPENSRC Open Source
+// Normal input / output
+// OPENDR_INV Open Drain
+// Inverted input / output
+// OPENDR Open Drain,
+// Normal input / output
+// INV Inverted input / ouput
+// NORMAL Normal input / output
+#define IOC_IOCFG22_IOMODE_W 3
+#define IOC_IOCFG22_IOMODE_M 0x07000000
+#define IOC_IOCFG22_IOMODE_S 24
+#define IOC_IOCFG22_IOMODE_OPENSRC_INV 0x07000000
+#define IOC_IOCFG22_IOMODE_OPENSRC 0x06000000
+#define IOC_IOCFG22_IOMODE_OPENDR_INV 0x05000000
+#define IOC_IOCFG22_IOMODE_OPENDR 0x04000000
+#define IOC_IOCFG22_IOMODE_INV 0x01000000
+#define IOC_IOCFG22_IOMODE_NORMAL 0x00000000
+
+// Field: [23] IOEV_AON_PROG2_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG2 event
+// 1: Input edge detection asserts AON_PROG2 event
+#define IOC_IOCFG22_IOEV_AON_PROG2_EN 0x00800000
+#define IOC_IOCFG22_IOEV_AON_PROG2_EN_BITN 23
+#define IOC_IOCFG22_IOEV_AON_PROG2_EN_M 0x00800000
+#define IOC_IOCFG22_IOEV_AON_PROG2_EN_S 23
+
+// Field: [22] IOEV_AON_PROG1_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG1 event
+// 1: Input edge detection asserts AON_PROG1 event
+#define IOC_IOCFG22_IOEV_AON_PROG1_EN 0x00400000
+#define IOC_IOCFG22_IOEV_AON_PROG1_EN_BITN 22
+#define IOC_IOCFG22_IOEV_AON_PROG1_EN_M 0x00400000
+#define IOC_IOCFG22_IOEV_AON_PROG1_EN_S 22
+
+// Field: [21] IOEV_AON_PROG0_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG0 event
+// 1: Input edge detection asserts AON_PROG0 event
+#define IOC_IOCFG22_IOEV_AON_PROG0_EN 0x00200000
+#define IOC_IOCFG22_IOEV_AON_PROG0_EN_BITN 21
+#define IOC_IOCFG22_IOEV_AON_PROG0_EN_M 0x00200000
+#define IOC_IOCFG22_IOEV_AON_PROG0_EN_S 21
+
+// Field: [18] EDGE_IRQ_EN
+//
+// 0: No interrupt generation
+// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is
+// enabled)
+#define IOC_IOCFG22_EDGE_IRQ_EN 0x00040000
+#define IOC_IOCFG22_EDGE_IRQ_EN_BITN 18
+#define IOC_IOCFG22_EDGE_IRQ_EN_M 0x00040000
+#define IOC_IOCFG22_EDGE_IRQ_EN_S 18
+
+// Field: [17:16] EDGE_DET
+//
+// Enable generation of edge detection events on this IO
+// ENUMs:
+// BOTH Positive and negative edge detection
+// POS Positive edge detection
+// NEG Negative edge detection
+// NONE No edge detection
+#define IOC_IOCFG22_EDGE_DET_W 2
+#define IOC_IOCFG22_EDGE_DET_M 0x00030000
+#define IOC_IOCFG22_EDGE_DET_S 16
+#define IOC_IOCFG22_EDGE_DET_BOTH 0x00030000
+#define IOC_IOCFG22_EDGE_DET_POS 0x00020000
+#define IOC_IOCFG22_EDGE_DET_NEG 0x00010000
+#define IOC_IOCFG22_EDGE_DET_NONE 0x00000000
+
+// Field: [14:13] PULL_CTL
+//
+// Pull control
+// ENUMs:
+// DIS No pull
+// UP Pull up
+// DWN Pull down
+#define IOC_IOCFG22_PULL_CTL_W 2
+#define IOC_IOCFG22_PULL_CTL_M 0x00006000
+#define IOC_IOCFG22_PULL_CTL_S 13
+#define IOC_IOCFG22_PULL_CTL_DIS 0x00006000
+#define IOC_IOCFG22_PULL_CTL_UP 0x00004000
+#define IOC_IOCFG22_PULL_CTL_DWN 0x00002000
+
+// Field: [12] SLEW_RED
+//
+// 0: Normal slew rate
+// 1: Enables reduced slew rate in output driver.
+#define IOC_IOCFG22_SLEW_RED 0x00001000
+#define IOC_IOCFG22_SLEW_RED_BITN 12
+#define IOC_IOCFG22_SLEW_RED_M 0x00001000
+#define IOC_IOCFG22_SLEW_RED_S 12
+
+// Field: [11:10] IOCURR
+//
+// Selects IO current mode of this IO.
+// ENUMs:
+// 4_8MA Extended-Current (EC) mode: Min 8 mA for double
+// drive strength IOs (min 4 mA for normal IOs)
+// when IOSTR is set to AUTO
+// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set
+// to AUTO
+// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set
+// to AUTO
+#define IOC_IOCFG22_IOCURR_W 2
+#define IOC_IOCFG22_IOCURR_M 0x00000C00
+#define IOC_IOCFG22_IOCURR_S 10
+#define IOC_IOCFG22_IOCURR_4_8MA 0x00000800
+#define IOC_IOCFG22_IOCURR_4MA 0x00000400
+#define IOC_IOCFG22_IOCURR_2MA 0x00000000
+
+// Field: [9:8] IOSTR
+//
+// Select source for drive strength control of this IO.
+// This setting controls the drive strength of the Low-Current (LC) mode.
+// Higher drive strength can be selected in IOCURR
+// ENUMs:
+// MAX Maximum drive strength, controlled by
+// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default
+// values)
+// MED Medium drive strength, controlled by
+// AON_IOC:IOSTRMED (min 2 mA @2.5V with default
+// values)
+// MIN Minimum drive strength, controlled by
+// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default
+// values)
+// AUTO Automatic drive strength, controlled by AON BATMON
+// based on battery voltage. (min 2 mA @VDDS)
+#define IOC_IOCFG22_IOSTR_W 2
+#define IOC_IOCFG22_IOSTR_M 0x00000300
+#define IOC_IOCFG22_IOSTR_S 8
+#define IOC_IOCFG22_IOSTR_MAX 0x00000300
+#define IOC_IOCFG22_IOSTR_MED 0x00000200
+#define IOC_IOCFG22_IOSTR_MIN 0x00000100
+#define IOC_IOCFG22_IOSTR_AUTO 0x00000000
+
+// Field: [7] IOEV_RTC_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert RTC event
+// 1: Input edge detection asserts RTC event
+#define IOC_IOCFG22_IOEV_RTC_EN 0x00000080
+#define IOC_IOCFG22_IOEV_RTC_EN_BITN 7
+#define IOC_IOCFG22_IOEV_RTC_EN_M 0x00000080
+#define IOC_IOCFG22_IOEV_RTC_EN_S 7
+
+// Field: [6] IOEV_MCU_WU_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert MCU_WU event
+// 1: Input edge detection asserts MCU_WU event
+#define IOC_IOCFG22_IOEV_MCU_WU_EN 0x00000040
+#define IOC_IOCFG22_IOEV_MCU_WU_EN_BITN 6
+#define IOC_IOCFG22_IOEV_MCU_WU_EN_M 0x00000040
+#define IOC_IOCFG22_IOEV_MCU_WU_EN_S 6
+
+// Field: [5:0] PORT_ID
+//
+// Selects usage for DIO22
+// ENUMs:
+// RFC_SMI_CL_IN RF Core SMI Command Link In
+// RFC_SMI_CL_OUT RF Core SMI Command Link Out
+// RFC_SMI_DL_IN RF Core SMI Data Link In
+// RFC_SMI_DL_OUT RF Core SMI Data Link Out
+// RFC_GPI1 RF Core Data In 1
+// RFC_GPI0 RF Core Data In 0
+// RFC_GPO3 RF Core Data Out 3
+// RFC_GPO2 RF Core Data Out 2
+// RFC_GPO1 RF Core Data Out 1
+// RFC_GPO0 RF Core Data Out 0
+// RFC_TRC RF Core Trace
+// I2S_MCLK I2S MCLK
+// I2S_BCLK I2S BCLK
+// I2S_WCLK I2S WCLK
+// I2S_AD1 I2S Data 1
+// I2S_AD0 I2S Data 0
+// SSI1_CLK SSI1 CLK
+// SSI1_FSS SSI1 FSS
+// SSI1_TX SSI1 TX
+// SSI1_RX SSI1 RX
+// CPU_SWV CPU SWV
+// PORT_EVENT7 PORT EVENT 7
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT6 PORT EVENT 6
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT5 PORT EVENT 5
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT4 PORT EVENT 4
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT3 PORT EVENT 3
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT2 PORT EVENT 2
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT1 PORT EVENT 1
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT0 PORT EVENT 0
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// UART1_RTS UART1 RTS
+// UART1_CTS UART1 CTS
+// UART1_TX UART1 TX
+// UART1_RX UART1 RX
+// UART0_RTS UART0 RTS
+// UART0_CTS UART0 CTS
+// UART0_TX UART0 TX
+// UART0_RX UART0 RX
+// I2C_MSSCL I2C Clock
+// I2C_MSSDA I2C Data
+// SSI0_CLK SSI0 CLK
+// SSI0_FSS SSI0 FSS
+// SSI0_TX SSI0 TX
+// SSI0_RX SSI0 RX
+// AUX_IO AUX IO
+// AON_CLK32K AON 32 KHz clock (SCLK_LF)
+// GPIO General Purpose IO
+#define IOC_IOCFG22_PORT_ID_W 6
+#define IOC_IOCFG22_PORT_ID_M 0x0000003F
+#define IOC_IOCFG22_PORT_ID_S 0
+#define IOC_IOCFG22_PORT_ID_RFC_SMI_CL_IN 0x00000038
+#define IOC_IOCFG22_PORT_ID_RFC_SMI_CL_OUT 0x00000037
+#define IOC_IOCFG22_PORT_ID_RFC_SMI_DL_IN 0x00000036
+#define IOC_IOCFG22_PORT_ID_RFC_SMI_DL_OUT 0x00000035
+#define IOC_IOCFG22_PORT_ID_RFC_GPI1 0x00000034
+#define IOC_IOCFG22_PORT_ID_RFC_GPI0 0x00000033
+#define IOC_IOCFG22_PORT_ID_RFC_GPO3 0x00000032
+#define IOC_IOCFG22_PORT_ID_RFC_GPO2 0x00000031
+#define IOC_IOCFG22_PORT_ID_RFC_GPO1 0x00000030
+#define IOC_IOCFG22_PORT_ID_RFC_GPO0 0x0000002F
+#define IOC_IOCFG22_PORT_ID_RFC_TRC 0x0000002E
+#define IOC_IOCFG22_PORT_ID_I2S_MCLK 0x00000029
+#define IOC_IOCFG22_PORT_ID_I2S_BCLK 0x00000028
+#define IOC_IOCFG22_PORT_ID_I2S_WCLK 0x00000027
+#define IOC_IOCFG22_PORT_ID_I2S_AD1 0x00000026
+#define IOC_IOCFG22_PORT_ID_I2S_AD0 0x00000025
+#define IOC_IOCFG22_PORT_ID_SSI1_CLK 0x00000024
+#define IOC_IOCFG22_PORT_ID_SSI1_FSS 0x00000023
+#define IOC_IOCFG22_PORT_ID_SSI1_TX 0x00000022
+#define IOC_IOCFG22_PORT_ID_SSI1_RX 0x00000021
+#define IOC_IOCFG22_PORT_ID_CPU_SWV 0x00000020
+#define IOC_IOCFG22_PORT_ID_PORT_EVENT7 0x0000001E
+#define IOC_IOCFG22_PORT_ID_PORT_EVENT6 0x0000001D
+#define IOC_IOCFG22_PORT_ID_PORT_EVENT5 0x0000001C
+#define IOC_IOCFG22_PORT_ID_PORT_EVENT4 0x0000001B
+#define IOC_IOCFG22_PORT_ID_PORT_EVENT3 0x0000001A
+#define IOC_IOCFG22_PORT_ID_PORT_EVENT2 0x00000019
+#define IOC_IOCFG22_PORT_ID_PORT_EVENT1 0x00000018
+#define IOC_IOCFG22_PORT_ID_PORT_EVENT0 0x00000017
+#define IOC_IOCFG22_PORT_ID_UART1_RTS 0x00000016
+#define IOC_IOCFG22_PORT_ID_UART1_CTS 0x00000015
+#define IOC_IOCFG22_PORT_ID_UART1_TX 0x00000014
+#define IOC_IOCFG22_PORT_ID_UART1_RX 0x00000013
+#define IOC_IOCFG22_PORT_ID_UART0_RTS 0x00000012
+#define IOC_IOCFG22_PORT_ID_UART0_CTS 0x00000011
+#define IOC_IOCFG22_PORT_ID_UART0_TX 0x00000010
+#define IOC_IOCFG22_PORT_ID_UART0_RX 0x0000000F
+#define IOC_IOCFG22_PORT_ID_I2C_MSSCL 0x0000000E
+#define IOC_IOCFG22_PORT_ID_I2C_MSSDA 0x0000000D
+#define IOC_IOCFG22_PORT_ID_SSI0_CLK 0x0000000C
+#define IOC_IOCFG22_PORT_ID_SSI0_FSS 0x0000000B
+#define IOC_IOCFG22_PORT_ID_SSI0_TX 0x0000000A
+#define IOC_IOCFG22_PORT_ID_SSI0_RX 0x00000009
+#define IOC_IOCFG22_PORT_ID_AUX_IO 0x00000008
+#define IOC_IOCFG22_PORT_ID_AON_CLK32K 0x00000007
+#define IOC_IOCFG22_PORT_ID_GPIO 0x00000000
+
+//*****************************************************************************
+//
+// Register: IOC_O_IOCFG23
+//
+//*****************************************************************************
+// Field: [30] HYST_EN
+//
+// 0: Input hysteresis disable
+// 1: Input hysteresis enable
+#define IOC_IOCFG23_HYST_EN 0x40000000
+#define IOC_IOCFG23_HYST_EN_BITN 30
+#define IOC_IOCFG23_HYST_EN_M 0x40000000
+#define IOC_IOCFG23_HYST_EN_S 30
+
+// Field: [29] IE
+//
+// 0: Input disabled
+// 1: Input enabled
+//
+// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be
+// ignored.
+#define IOC_IOCFG23_IE 0x20000000
+#define IOC_IOCFG23_IE_BITN 29
+#define IOC_IOCFG23_IE_M 0x20000000
+#define IOC_IOCFG23_IE_S 29
+
+// Field: [28:27] WU_CFG
+//
+// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or
+// >0x08:
+//
+// 00: No wake-up
+// 01: No wake-up
+// 10: Wakes up from shutdown if this pad is going low.
+// 11: Wakes up from shutdown if this pad is going high.
+//
+// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08,
+// this register only sets wakeup enable or not.
+//
+// 00, 01: Wakeup disabled
+// 10, 11: Wakeup enabled
+//
+// Polarity is controlled from AON registers.
+//
+// Note:When the MSB is set, the IOC will deactivate the output enable for the
+// DIO.
+#define IOC_IOCFG23_WU_CFG_W 2
+#define IOC_IOCFG23_WU_CFG_M 0x18000000
+#define IOC_IOCFG23_WU_CFG_S 27
+
+// Field: [26:24] IOMODE
+//
+// IO Mode
+// Not applicable for IO configured for AON periph. signals and AUX PORT_ID
+// 0x01-0x08
+// AUX has its own open_source/drain configuration.
+//
+// 0x2: Reserved. Undefined behavior.
+// 0x3: Reserved. Undefined behavior.
+// ENUMs:
+// OPENSRC_INV Open Source
+// Inverted input / output
+// OPENSRC Open Source
+// Normal input / output
+// OPENDR_INV Open Drain
+// Inverted input / output
+// OPENDR Open Drain,
+// Normal input / output
+// INV Inverted input / ouput
+// NORMAL Normal input / output
+#define IOC_IOCFG23_IOMODE_W 3
+#define IOC_IOCFG23_IOMODE_M 0x07000000
+#define IOC_IOCFG23_IOMODE_S 24
+#define IOC_IOCFG23_IOMODE_OPENSRC_INV 0x07000000
+#define IOC_IOCFG23_IOMODE_OPENSRC 0x06000000
+#define IOC_IOCFG23_IOMODE_OPENDR_INV 0x05000000
+#define IOC_IOCFG23_IOMODE_OPENDR 0x04000000
+#define IOC_IOCFG23_IOMODE_INV 0x01000000
+#define IOC_IOCFG23_IOMODE_NORMAL 0x00000000
+
+// Field: [23] IOEV_AON_PROG2_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG2 event
+// 1: Input edge detection asserts AON_PROG2 event
+#define IOC_IOCFG23_IOEV_AON_PROG2_EN 0x00800000
+#define IOC_IOCFG23_IOEV_AON_PROG2_EN_BITN 23
+#define IOC_IOCFG23_IOEV_AON_PROG2_EN_M 0x00800000
+#define IOC_IOCFG23_IOEV_AON_PROG2_EN_S 23
+
+// Field: [22] IOEV_AON_PROG1_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG1 event
+// 1: Input edge detection asserts AON_PROG1 event
+#define IOC_IOCFG23_IOEV_AON_PROG1_EN 0x00400000
+#define IOC_IOCFG23_IOEV_AON_PROG1_EN_BITN 22
+#define IOC_IOCFG23_IOEV_AON_PROG1_EN_M 0x00400000
+#define IOC_IOCFG23_IOEV_AON_PROG1_EN_S 22
+
+// Field: [21] IOEV_AON_PROG0_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG0 event
+// 1: Input edge detection asserts AON_PROG0 event
+#define IOC_IOCFG23_IOEV_AON_PROG0_EN 0x00200000
+#define IOC_IOCFG23_IOEV_AON_PROG0_EN_BITN 21
+#define IOC_IOCFG23_IOEV_AON_PROG0_EN_M 0x00200000
+#define IOC_IOCFG23_IOEV_AON_PROG0_EN_S 21
+
+// Field: [18] EDGE_IRQ_EN
+//
+// 0: No interrupt generation
+// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is
+// enabled)
+#define IOC_IOCFG23_EDGE_IRQ_EN 0x00040000
+#define IOC_IOCFG23_EDGE_IRQ_EN_BITN 18
+#define IOC_IOCFG23_EDGE_IRQ_EN_M 0x00040000
+#define IOC_IOCFG23_EDGE_IRQ_EN_S 18
+
+// Field: [17:16] EDGE_DET
+//
+// Enable generation of edge detection events on this IO
+// ENUMs:
+// BOTH Positive and negative edge detection
+// POS Positive edge detection
+// NEG Negative edge detection
+// NONE No edge detection
+#define IOC_IOCFG23_EDGE_DET_W 2
+#define IOC_IOCFG23_EDGE_DET_M 0x00030000
+#define IOC_IOCFG23_EDGE_DET_S 16
+#define IOC_IOCFG23_EDGE_DET_BOTH 0x00030000
+#define IOC_IOCFG23_EDGE_DET_POS 0x00020000
+#define IOC_IOCFG23_EDGE_DET_NEG 0x00010000
+#define IOC_IOCFG23_EDGE_DET_NONE 0x00000000
+
+// Field: [14:13] PULL_CTL
+//
+// Pull control
+// ENUMs:
+// DIS No pull
+// UP Pull up
+// DWN Pull down
+#define IOC_IOCFG23_PULL_CTL_W 2
+#define IOC_IOCFG23_PULL_CTL_M 0x00006000
+#define IOC_IOCFG23_PULL_CTL_S 13
+#define IOC_IOCFG23_PULL_CTL_DIS 0x00006000
+#define IOC_IOCFG23_PULL_CTL_UP 0x00004000
+#define IOC_IOCFG23_PULL_CTL_DWN 0x00002000
+
+// Field: [12] SLEW_RED
+//
+// 0: Normal slew rate
+// 1: Enables reduced slew rate in output driver.
+#define IOC_IOCFG23_SLEW_RED 0x00001000
+#define IOC_IOCFG23_SLEW_RED_BITN 12
+#define IOC_IOCFG23_SLEW_RED_M 0x00001000
+#define IOC_IOCFG23_SLEW_RED_S 12
+
+// Field: [11:10] IOCURR
+//
+// Selects IO current mode of this IO.
+// ENUMs:
+// 4_8MA Extended-Current (EC) mode: Min 8 mA for double
+// drive strength IOs (min 4 mA for normal IOs)
+// when IOSTR is set to AUTO
+// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set
+// to AUTO
+// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set
+// to AUTO
+#define IOC_IOCFG23_IOCURR_W 2
+#define IOC_IOCFG23_IOCURR_M 0x00000C00
+#define IOC_IOCFG23_IOCURR_S 10
+#define IOC_IOCFG23_IOCURR_4_8MA 0x00000800
+#define IOC_IOCFG23_IOCURR_4MA 0x00000400
+#define IOC_IOCFG23_IOCURR_2MA 0x00000000
+
+// Field: [9:8] IOSTR
+//
+// Select source for drive strength control of this IO.
+// This setting controls the drive strength of the Low-Current (LC) mode.
+// Higher drive strength can be selected in IOCURR
+// ENUMs:
+// MAX Maximum drive strength, controlled by
+// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default
+// values)
+// MED Medium drive strength, controlled by
+// AON_IOC:IOSTRMED (min 2 mA @2.5V with default
+// values)
+// MIN Minimum drive strength, controlled by
+// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default
+// values)
+// AUTO Automatic drive strength, controlled by AON BATMON
+// based on battery voltage. (min 2 mA @VDDS)
+#define IOC_IOCFG23_IOSTR_W 2
+#define IOC_IOCFG23_IOSTR_M 0x00000300
+#define IOC_IOCFG23_IOSTR_S 8
+#define IOC_IOCFG23_IOSTR_MAX 0x00000300
+#define IOC_IOCFG23_IOSTR_MED 0x00000200
+#define IOC_IOCFG23_IOSTR_MIN 0x00000100
+#define IOC_IOCFG23_IOSTR_AUTO 0x00000000
+
+// Field: [7] IOEV_RTC_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert RTC event
+// 1: Input edge detection asserts RTC event
+#define IOC_IOCFG23_IOEV_RTC_EN 0x00000080
+#define IOC_IOCFG23_IOEV_RTC_EN_BITN 7
+#define IOC_IOCFG23_IOEV_RTC_EN_M 0x00000080
+#define IOC_IOCFG23_IOEV_RTC_EN_S 7
+
+// Field: [6] IOEV_MCU_WU_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert MCU_WU event
+// 1: Input edge detection asserts MCU_WU event
+#define IOC_IOCFG23_IOEV_MCU_WU_EN 0x00000040
+#define IOC_IOCFG23_IOEV_MCU_WU_EN_BITN 6
+#define IOC_IOCFG23_IOEV_MCU_WU_EN_M 0x00000040
+#define IOC_IOCFG23_IOEV_MCU_WU_EN_S 6
+
+// Field: [5:0] PORT_ID
+//
+// Selects usage for DIO23
+// ENUMs:
+// RFC_SMI_CL_IN RF Core SMI Command Link In
+// RFC_SMI_CL_OUT RF Core SMI Command Link Out
+// RFC_SMI_DL_IN RF Core SMI Data Link In
+// RFC_SMI_DL_OUT RF Core SMI Data Link Out
+// RFC_GPI1 RF Core Data In 1
+// RFC_GPI0 RF Core Data In 0
+// RFC_GPO3 RF Core Data Out 3
+// RFC_GPO2 RF Core Data Out 2
+// RFC_GPO1 RF Core Data Out 1
+// RFC_GPO0 RF Core Data Out 0
+// RFC_TRC RF Core Trace
+// I2S_MCLK I2S MCLK
+// I2S_BCLK I2S BCLK
+// I2S_WCLK I2S WCLK
+// I2S_AD1 I2S Data 1
+// I2S_AD0 I2S Data 0
+// SSI1_CLK SSI1 CLK
+// SSI1_FSS SSI1 FSS
+// SSI1_TX SSI1 TX
+// SSI1_RX SSI1 RX
+// CPU_SWV CPU SWV
+// PORT_EVENT7 PORT EVENT 7
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT6 PORT EVENT 6
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT5 PORT EVENT 5
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT4 PORT EVENT 4
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT3 PORT EVENT 3
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT2 PORT EVENT 2
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT1 PORT EVENT 1
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT0 PORT EVENT 0
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// UART1_RTS UART1 RTS
+// UART1_CTS UART1 CTS
+// UART1_TX UART1 TX
+// UART1_RX UART1 RX
+// UART0_RTS UART0 RTS
+// UART0_CTS UART0 CTS
+// UART0_TX UART0 TX
+// UART0_RX UART0 RX
+// I2C_MSSCL I2C Clock
+// I2C_MSSDA I2C Data
+// SSI0_CLK SSI0 CLK
+// SSI0_FSS SSI0 FSS
+// SSI0_TX SSI0 TX
+// SSI0_RX SSI0 RX
+// AUX_IO AUX IO
+// AON_CLK32K AON 32 KHz clock (SCLK_LF)
+// GPIO General Purpose IO
+#define IOC_IOCFG23_PORT_ID_W 6
+#define IOC_IOCFG23_PORT_ID_M 0x0000003F
+#define IOC_IOCFG23_PORT_ID_S 0
+#define IOC_IOCFG23_PORT_ID_RFC_SMI_CL_IN 0x00000038
+#define IOC_IOCFG23_PORT_ID_RFC_SMI_CL_OUT 0x00000037
+#define IOC_IOCFG23_PORT_ID_RFC_SMI_DL_IN 0x00000036
+#define IOC_IOCFG23_PORT_ID_RFC_SMI_DL_OUT 0x00000035
+#define IOC_IOCFG23_PORT_ID_RFC_GPI1 0x00000034
+#define IOC_IOCFG23_PORT_ID_RFC_GPI0 0x00000033
+#define IOC_IOCFG23_PORT_ID_RFC_GPO3 0x00000032
+#define IOC_IOCFG23_PORT_ID_RFC_GPO2 0x00000031
+#define IOC_IOCFG23_PORT_ID_RFC_GPO1 0x00000030
+#define IOC_IOCFG23_PORT_ID_RFC_GPO0 0x0000002F
+#define IOC_IOCFG23_PORT_ID_RFC_TRC 0x0000002E
+#define IOC_IOCFG23_PORT_ID_I2S_MCLK 0x00000029
+#define IOC_IOCFG23_PORT_ID_I2S_BCLK 0x00000028
+#define IOC_IOCFG23_PORT_ID_I2S_WCLK 0x00000027
+#define IOC_IOCFG23_PORT_ID_I2S_AD1 0x00000026
+#define IOC_IOCFG23_PORT_ID_I2S_AD0 0x00000025
+#define IOC_IOCFG23_PORT_ID_SSI1_CLK 0x00000024
+#define IOC_IOCFG23_PORT_ID_SSI1_FSS 0x00000023
+#define IOC_IOCFG23_PORT_ID_SSI1_TX 0x00000022
+#define IOC_IOCFG23_PORT_ID_SSI1_RX 0x00000021
+#define IOC_IOCFG23_PORT_ID_CPU_SWV 0x00000020
+#define IOC_IOCFG23_PORT_ID_PORT_EVENT7 0x0000001E
+#define IOC_IOCFG23_PORT_ID_PORT_EVENT6 0x0000001D
+#define IOC_IOCFG23_PORT_ID_PORT_EVENT5 0x0000001C
+#define IOC_IOCFG23_PORT_ID_PORT_EVENT4 0x0000001B
+#define IOC_IOCFG23_PORT_ID_PORT_EVENT3 0x0000001A
+#define IOC_IOCFG23_PORT_ID_PORT_EVENT2 0x00000019
+#define IOC_IOCFG23_PORT_ID_PORT_EVENT1 0x00000018
+#define IOC_IOCFG23_PORT_ID_PORT_EVENT0 0x00000017
+#define IOC_IOCFG23_PORT_ID_UART1_RTS 0x00000016
+#define IOC_IOCFG23_PORT_ID_UART1_CTS 0x00000015
+#define IOC_IOCFG23_PORT_ID_UART1_TX 0x00000014
+#define IOC_IOCFG23_PORT_ID_UART1_RX 0x00000013
+#define IOC_IOCFG23_PORT_ID_UART0_RTS 0x00000012
+#define IOC_IOCFG23_PORT_ID_UART0_CTS 0x00000011
+#define IOC_IOCFG23_PORT_ID_UART0_TX 0x00000010
+#define IOC_IOCFG23_PORT_ID_UART0_RX 0x0000000F
+#define IOC_IOCFG23_PORT_ID_I2C_MSSCL 0x0000000E
+#define IOC_IOCFG23_PORT_ID_I2C_MSSDA 0x0000000D
+#define IOC_IOCFG23_PORT_ID_SSI0_CLK 0x0000000C
+#define IOC_IOCFG23_PORT_ID_SSI0_FSS 0x0000000B
+#define IOC_IOCFG23_PORT_ID_SSI0_TX 0x0000000A
+#define IOC_IOCFG23_PORT_ID_SSI0_RX 0x00000009
+#define IOC_IOCFG23_PORT_ID_AUX_IO 0x00000008
+#define IOC_IOCFG23_PORT_ID_AON_CLK32K 0x00000007
+#define IOC_IOCFG23_PORT_ID_GPIO 0x00000000
+
+//*****************************************************************************
+//
+// Register: IOC_O_IOCFG24
+//
+//*****************************************************************************
+// Field: [30] HYST_EN
+//
+// 0: Input hysteresis disable
+// 1: Input hysteresis enable
+#define IOC_IOCFG24_HYST_EN 0x40000000
+#define IOC_IOCFG24_HYST_EN_BITN 30
+#define IOC_IOCFG24_HYST_EN_M 0x40000000
+#define IOC_IOCFG24_HYST_EN_S 30
+
+// Field: [29] IE
+//
+// 0: Input disabled
+// 1: Input enabled
+//
+// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be
+// ignored.
+#define IOC_IOCFG24_IE 0x20000000
+#define IOC_IOCFG24_IE_BITN 29
+#define IOC_IOCFG24_IE_M 0x20000000
+#define IOC_IOCFG24_IE_S 29
+
+// Field: [28:27] WU_CFG
+//
+// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or
+// >0x08:
+//
+// 00: No wake-up
+// 01: No wake-up
+// 10: Wakes up from shutdown if this pad is going low.
+// 11: Wakes up from shutdown if this pad is going high.
+//
+// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08,
+// this register only sets wakeup enable or not.
+//
+// 00, 01: Wakeup disabled
+// 10, 11: Wakeup enabled
+//
+// Polarity is controlled from AON registers.
+//
+// Note:When the MSB is set, the IOC will deactivate the output enable for the
+// DIO.
+#define IOC_IOCFG24_WU_CFG_W 2
+#define IOC_IOCFG24_WU_CFG_M 0x18000000
+#define IOC_IOCFG24_WU_CFG_S 27
+
+// Field: [26:24] IOMODE
+//
+// IO Mode
+// Not applicable for IO configured for AON periph. signals and AUX PORT_ID
+// 0x01-0x08
+// AUX has its own open_source/drain configuration.
+//
+// 0x2: Reserved. Undefined behavior.
+// 0x3: Reserved. Undefined behavior.
+// ENUMs:
+// OPENSRC_INV Open Source
+// Inverted input / output
+// OPENSRC Open Source
+// Normal input / output
+// OPENDR_INV Open Drain
+// Inverted input / output
+// OPENDR Open Drain,
+// Normal input / output
+// INV Inverted input / ouput
+// NORMAL Normal input / output
+#define IOC_IOCFG24_IOMODE_W 3
+#define IOC_IOCFG24_IOMODE_M 0x07000000
+#define IOC_IOCFG24_IOMODE_S 24
+#define IOC_IOCFG24_IOMODE_OPENSRC_INV 0x07000000
+#define IOC_IOCFG24_IOMODE_OPENSRC 0x06000000
+#define IOC_IOCFG24_IOMODE_OPENDR_INV 0x05000000
+#define IOC_IOCFG24_IOMODE_OPENDR 0x04000000
+#define IOC_IOCFG24_IOMODE_INV 0x01000000
+#define IOC_IOCFG24_IOMODE_NORMAL 0x00000000
+
+// Field: [23] IOEV_AON_PROG2_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG2 event
+// 1: Input edge detection asserts AON_PROG2 event
+#define IOC_IOCFG24_IOEV_AON_PROG2_EN 0x00800000
+#define IOC_IOCFG24_IOEV_AON_PROG2_EN_BITN 23
+#define IOC_IOCFG24_IOEV_AON_PROG2_EN_M 0x00800000
+#define IOC_IOCFG24_IOEV_AON_PROG2_EN_S 23
+
+// Field: [22] IOEV_AON_PROG1_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG1 event
+// 1: Input edge detection asserts AON_PROG1 event
+#define IOC_IOCFG24_IOEV_AON_PROG1_EN 0x00400000
+#define IOC_IOCFG24_IOEV_AON_PROG1_EN_BITN 22
+#define IOC_IOCFG24_IOEV_AON_PROG1_EN_M 0x00400000
+#define IOC_IOCFG24_IOEV_AON_PROG1_EN_S 22
+
+// Field: [21] IOEV_AON_PROG0_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG0 event
+// 1: Input edge detection asserts AON_PROG0 event
+#define IOC_IOCFG24_IOEV_AON_PROG0_EN 0x00200000
+#define IOC_IOCFG24_IOEV_AON_PROG0_EN_BITN 21
+#define IOC_IOCFG24_IOEV_AON_PROG0_EN_M 0x00200000
+#define IOC_IOCFG24_IOEV_AON_PROG0_EN_S 21
+
+// Field: [18] EDGE_IRQ_EN
+//
+// 0: No interrupt generation
+// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is
+// enabled)
+#define IOC_IOCFG24_EDGE_IRQ_EN 0x00040000
+#define IOC_IOCFG24_EDGE_IRQ_EN_BITN 18
+#define IOC_IOCFG24_EDGE_IRQ_EN_M 0x00040000
+#define IOC_IOCFG24_EDGE_IRQ_EN_S 18
+
+// Field: [17:16] EDGE_DET
+//
+// Enable generation of edge detection events on this IO
+// ENUMs:
+// BOTH Positive and negative edge detection
+// POS Positive edge detection
+// NEG Negative edge detection
+// NONE No edge detection
+#define IOC_IOCFG24_EDGE_DET_W 2
+#define IOC_IOCFG24_EDGE_DET_M 0x00030000
+#define IOC_IOCFG24_EDGE_DET_S 16
+#define IOC_IOCFG24_EDGE_DET_BOTH 0x00030000
+#define IOC_IOCFG24_EDGE_DET_POS 0x00020000
+#define IOC_IOCFG24_EDGE_DET_NEG 0x00010000
+#define IOC_IOCFG24_EDGE_DET_NONE 0x00000000
+
+// Field: [14:13] PULL_CTL
+//
+// Pull control
+// ENUMs:
+// DIS No pull
+// UP Pull up
+// DWN Pull down
+#define IOC_IOCFG24_PULL_CTL_W 2
+#define IOC_IOCFG24_PULL_CTL_M 0x00006000
+#define IOC_IOCFG24_PULL_CTL_S 13
+#define IOC_IOCFG24_PULL_CTL_DIS 0x00006000
+#define IOC_IOCFG24_PULL_CTL_UP 0x00004000
+#define IOC_IOCFG24_PULL_CTL_DWN 0x00002000
+
+// Field: [12] SLEW_RED
+//
+// 0: Normal slew rate
+// 1: Enables reduced slew rate in output driver.
+#define IOC_IOCFG24_SLEW_RED 0x00001000
+#define IOC_IOCFG24_SLEW_RED_BITN 12
+#define IOC_IOCFG24_SLEW_RED_M 0x00001000
+#define IOC_IOCFG24_SLEW_RED_S 12
+
+// Field: [11:10] IOCURR
+//
+// Selects IO current mode of this IO.
+// ENUMs:
+// 4_8MA Extended-Current (EC) mode: Min 8 mA for double
+// drive strength IOs (min 4 mA for normal IOs)
+// when IOSTR is set to AUTO
+// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set
+// to AUTO
+// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set
+// to AUTO
+#define IOC_IOCFG24_IOCURR_W 2
+#define IOC_IOCFG24_IOCURR_M 0x00000C00
+#define IOC_IOCFG24_IOCURR_S 10
+#define IOC_IOCFG24_IOCURR_4_8MA 0x00000800
+#define IOC_IOCFG24_IOCURR_4MA 0x00000400
+#define IOC_IOCFG24_IOCURR_2MA 0x00000000
+
+// Field: [9:8] IOSTR
+//
+// Select source for drive strength control of this IO.
+// This setting controls the drive strength of the Low-Current (LC) mode.
+// Higher drive strength can be selected in IOCURR
+// ENUMs:
+// MAX Maximum drive strength, controlled by
+// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default
+// values)
+// MED Medium drive strength, controlled by
+// AON_IOC:IOSTRMED (min 2 mA @2.5V with default
+// values)
+// MIN Minimum drive strength, controlled by
+// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default
+// values)
+// AUTO Automatic drive strength, controlled by AON BATMON
+// based on battery voltage. (min 2 mA @VDDS)
+#define IOC_IOCFG24_IOSTR_W 2
+#define IOC_IOCFG24_IOSTR_M 0x00000300
+#define IOC_IOCFG24_IOSTR_S 8
+#define IOC_IOCFG24_IOSTR_MAX 0x00000300
+#define IOC_IOCFG24_IOSTR_MED 0x00000200
+#define IOC_IOCFG24_IOSTR_MIN 0x00000100
+#define IOC_IOCFG24_IOSTR_AUTO 0x00000000
+
+// Field: [7] IOEV_RTC_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert RTC event
+// 1: Input edge detection asserts RTC event
+#define IOC_IOCFG24_IOEV_RTC_EN 0x00000080
+#define IOC_IOCFG24_IOEV_RTC_EN_BITN 7
+#define IOC_IOCFG24_IOEV_RTC_EN_M 0x00000080
+#define IOC_IOCFG24_IOEV_RTC_EN_S 7
+
+// Field: [6] IOEV_MCU_WU_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert MCU_WU event
+// 1: Input edge detection asserts MCU_WU event
+#define IOC_IOCFG24_IOEV_MCU_WU_EN 0x00000040
+#define IOC_IOCFG24_IOEV_MCU_WU_EN_BITN 6
+#define IOC_IOCFG24_IOEV_MCU_WU_EN_M 0x00000040
+#define IOC_IOCFG24_IOEV_MCU_WU_EN_S 6
+
+// Field: [5:0] PORT_ID
+//
+// Selects usage for DIO24
+// ENUMs:
+// RFC_SMI_CL_IN RF Core SMI Command Link In
+// RFC_SMI_CL_OUT RF Core SMI Command Link Out
+// RFC_SMI_DL_IN RF Core SMI Data Link In
+// RFC_SMI_DL_OUT RF Core SMI Data Link Out
+// RFC_GPI1 RF Core Data In 1
+// RFC_GPI0 RF Core Data In 0
+// RFC_GPO3 RF Core Data Out 3
+// RFC_GPO2 RF Core Data Out 2
+// RFC_GPO1 RF Core Data Out 1
+// RFC_GPO0 RF Core Data Out 0
+// RFC_TRC RF Core Trace
+// I2S_MCLK I2S MCLK
+// I2S_BCLK I2S BCLK
+// I2S_WCLK I2S WCLK
+// I2S_AD1 I2S Data 1
+// I2S_AD0 I2S Data 0
+// SSI1_CLK SSI1 CLK
+// SSI1_FSS SSI1 FSS
+// SSI1_TX SSI1 TX
+// SSI1_RX SSI1 RX
+// CPU_SWV CPU SWV
+// PORT_EVENT7 PORT EVENT 7
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT6 PORT EVENT 6
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT5 PORT EVENT 5
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT4 PORT EVENT 4
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT3 PORT EVENT 3
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT2 PORT EVENT 2
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT1 PORT EVENT 1
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT0 PORT EVENT 0
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// UART1_RTS UART1 RTS
+// UART1_CTS UART1 CTS
+// UART1_TX UART1 TX
+// UART1_RX UART1 RX
+// UART0_RTS UART0 RTS
+// UART0_CTS UART0 CTS
+// UART0_TX UART0 TX
+// UART0_RX UART0 RX
+// I2C_MSSCL I2C Clock
+// I2C_MSSDA I2C Data
+// SSI0_CLK SSI0 CLK
+// SSI0_FSS SSI0 FSS
+// SSI0_TX SSI0 TX
+// SSI0_RX SSI0 RX
+// AUX_IO AUX IO
+// AON_CLK32K AON 32 KHz clock (SCLK_LF)
+// GPIO General Purpose IO
+#define IOC_IOCFG24_PORT_ID_W 6
+#define IOC_IOCFG24_PORT_ID_M 0x0000003F
+#define IOC_IOCFG24_PORT_ID_S 0
+#define IOC_IOCFG24_PORT_ID_RFC_SMI_CL_IN 0x00000038
+#define IOC_IOCFG24_PORT_ID_RFC_SMI_CL_OUT 0x00000037
+#define IOC_IOCFG24_PORT_ID_RFC_SMI_DL_IN 0x00000036
+#define IOC_IOCFG24_PORT_ID_RFC_SMI_DL_OUT 0x00000035
+#define IOC_IOCFG24_PORT_ID_RFC_GPI1 0x00000034
+#define IOC_IOCFG24_PORT_ID_RFC_GPI0 0x00000033
+#define IOC_IOCFG24_PORT_ID_RFC_GPO3 0x00000032
+#define IOC_IOCFG24_PORT_ID_RFC_GPO2 0x00000031
+#define IOC_IOCFG24_PORT_ID_RFC_GPO1 0x00000030
+#define IOC_IOCFG24_PORT_ID_RFC_GPO0 0x0000002F
+#define IOC_IOCFG24_PORT_ID_RFC_TRC 0x0000002E
+#define IOC_IOCFG24_PORT_ID_I2S_MCLK 0x00000029
+#define IOC_IOCFG24_PORT_ID_I2S_BCLK 0x00000028
+#define IOC_IOCFG24_PORT_ID_I2S_WCLK 0x00000027
+#define IOC_IOCFG24_PORT_ID_I2S_AD1 0x00000026
+#define IOC_IOCFG24_PORT_ID_I2S_AD0 0x00000025
+#define IOC_IOCFG24_PORT_ID_SSI1_CLK 0x00000024
+#define IOC_IOCFG24_PORT_ID_SSI1_FSS 0x00000023
+#define IOC_IOCFG24_PORT_ID_SSI1_TX 0x00000022
+#define IOC_IOCFG24_PORT_ID_SSI1_RX 0x00000021
+#define IOC_IOCFG24_PORT_ID_CPU_SWV 0x00000020
+#define IOC_IOCFG24_PORT_ID_PORT_EVENT7 0x0000001E
+#define IOC_IOCFG24_PORT_ID_PORT_EVENT6 0x0000001D
+#define IOC_IOCFG24_PORT_ID_PORT_EVENT5 0x0000001C
+#define IOC_IOCFG24_PORT_ID_PORT_EVENT4 0x0000001B
+#define IOC_IOCFG24_PORT_ID_PORT_EVENT3 0x0000001A
+#define IOC_IOCFG24_PORT_ID_PORT_EVENT2 0x00000019
+#define IOC_IOCFG24_PORT_ID_PORT_EVENT1 0x00000018
+#define IOC_IOCFG24_PORT_ID_PORT_EVENT0 0x00000017
+#define IOC_IOCFG24_PORT_ID_UART1_RTS 0x00000016
+#define IOC_IOCFG24_PORT_ID_UART1_CTS 0x00000015
+#define IOC_IOCFG24_PORT_ID_UART1_TX 0x00000014
+#define IOC_IOCFG24_PORT_ID_UART1_RX 0x00000013
+#define IOC_IOCFG24_PORT_ID_UART0_RTS 0x00000012
+#define IOC_IOCFG24_PORT_ID_UART0_CTS 0x00000011
+#define IOC_IOCFG24_PORT_ID_UART0_TX 0x00000010
+#define IOC_IOCFG24_PORT_ID_UART0_RX 0x0000000F
+#define IOC_IOCFG24_PORT_ID_I2C_MSSCL 0x0000000E
+#define IOC_IOCFG24_PORT_ID_I2C_MSSDA 0x0000000D
+#define IOC_IOCFG24_PORT_ID_SSI0_CLK 0x0000000C
+#define IOC_IOCFG24_PORT_ID_SSI0_FSS 0x0000000B
+#define IOC_IOCFG24_PORT_ID_SSI0_TX 0x0000000A
+#define IOC_IOCFG24_PORT_ID_SSI0_RX 0x00000009
+#define IOC_IOCFG24_PORT_ID_AUX_IO 0x00000008
+#define IOC_IOCFG24_PORT_ID_AON_CLK32K 0x00000007
+#define IOC_IOCFG24_PORT_ID_GPIO 0x00000000
+
+//*****************************************************************************
+//
+// Register: IOC_O_IOCFG25
+//
+//*****************************************************************************
+// Field: [30] HYST_EN
+//
+// 0: Input hysteresis disable
+// 1: Input hysteresis enable
+#define IOC_IOCFG25_HYST_EN 0x40000000
+#define IOC_IOCFG25_HYST_EN_BITN 30
+#define IOC_IOCFG25_HYST_EN_M 0x40000000
+#define IOC_IOCFG25_HYST_EN_S 30
+
+// Field: [29] IE
+//
+// 0: Input disabled
+// 1: Input enabled
+//
+// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be
+// ignored.
+#define IOC_IOCFG25_IE 0x20000000
+#define IOC_IOCFG25_IE_BITN 29
+#define IOC_IOCFG25_IE_M 0x20000000
+#define IOC_IOCFG25_IE_S 29
+
+// Field: [28:27] WU_CFG
+//
+// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or
+// >0x08:
+//
+// 00: No wake-up
+// 01: No wake-up
+// 10: Wakes up from shutdown if this pad is going low.
+// 11: Wakes up from shutdown if this pad is going high.
+//
+// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08,
+// this register only sets wakeup enable or not.
+//
+// 00, 01: Wakeup disabled
+// 10, 11: Wakeup enabled
+//
+// Polarity is controlled from AON registers.
+//
+// Note:When the MSB is set, the IOC will deactivate the output enable for the
+// DIO.
+#define IOC_IOCFG25_WU_CFG_W 2
+#define IOC_IOCFG25_WU_CFG_M 0x18000000
+#define IOC_IOCFG25_WU_CFG_S 27
+
+// Field: [26:24] IOMODE
+//
+// IO Mode
+// Not applicable for IO configured for AON periph. signals and AUX PORT_ID
+// 0x01-0x08
+// AUX has its own open_source/drain configuration.
+//
+// 0x2: Reserved. Undefined behavior.
+// 0x3: Reserved. Undefined behavior.
+// ENUMs:
+// OPENSRC_INV Open Source
+// Inverted input / output
+// OPENSRC Open Source
+// Normal input / output
+// OPENDR_INV Open Drain
+// Inverted input / output
+// OPENDR Open Drain,
+// Normal input / output
+// INV Inverted input / ouput
+// NORMAL Normal input / output
+#define IOC_IOCFG25_IOMODE_W 3
+#define IOC_IOCFG25_IOMODE_M 0x07000000
+#define IOC_IOCFG25_IOMODE_S 24
+#define IOC_IOCFG25_IOMODE_OPENSRC_INV 0x07000000
+#define IOC_IOCFG25_IOMODE_OPENSRC 0x06000000
+#define IOC_IOCFG25_IOMODE_OPENDR_INV 0x05000000
+#define IOC_IOCFG25_IOMODE_OPENDR 0x04000000
+#define IOC_IOCFG25_IOMODE_INV 0x01000000
+#define IOC_IOCFG25_IOMODE_NORMAL 0x00000000
+
+// Field: [23] IOEV_AON_PROG2_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG2 event
+// 1: Input edge detection asserts AON_PROG2 event
+#define IOC_IOCFG25_IOEV_AON_PROG2_EN 0x00800000
+#define IOC_IOCFG25_IOEV_AON_PROG2_EN_BITN 23
+#define IOC_IOCFG25_IOEV_AON_PROG2_EN_M 0x00800000
+#define IOC_IOCFG25_IOEV_AON_PROG2_EN_S 23
+
+// Field: [22] IOEV_AON_PROG1_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG1 event
+// 1: Input edge detection asserts AON_PROG1 event
+#define IOC_IOCFG25_IOEV_AON_PROG1_EN 0x00400000
+#define IOC_IOCFG25_IOEV_AON_PROG1_EN_BITN 22
+#define IOC_IOCFG25_IOEV_AON_PROG1_EN_M 0x00400000
+#define IOC_IOCFG25_IOEV_AON_PROG1_EN_S 22
+
+// Field: [21] IOEV_AON_PROG0_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG0 event
+// 1: Input edge detection asserts AON_PROG0 event
+#define IOC_IOCFG25_IOEV_AON_PROG0_EN 0x00200000
+#define IOC_IOCFG25_IOEV_AON_PROG0_EN_BITN 21
+#define IOC_IOCFG25_IOEV_AON_PROG0_EN_M 0x00200000
+#define IOC_IOCFG25_IOEV_AON_PROG0_EN_S 21
+
+// Field: [18] EDGE_IRQ_EN
+//
+// 0: No interrupt generation
+// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is
+// enabled)
+#define IOC_IOCFG25_EDGE_IRQ_EN 0x00040000
+#define IOC_IOCFG25_EDGE_IRQ_EN_BITN 18
+#define IOC_IOCFG25_EDGE_IRQ_EN_M 0x00040000
+#define IOC_IOCFG25_EDGE_IRQ_EN_S 18
+
+// Field: [17:16] EDGE_DET
+//
+// Enable generation of edge detection events on this IO
+// ENUMs:
+// BOTH Positive and negative edge detection
+// POS Positive edge detection
+// NEG Negative edge detection
+// NONE No edge detection
+#define IOC_IOCFG25_EDGE_DET_W 2
+#define IOC_IOCFG25_EDGE_DET_M 0x00030000
+#define IOC_IOCFG25_EDGE_DET_S 16
+#define IOC_IOCFG25_EDGE_DET_BOTH 0x00030000
+#define IOC_IOCFG25_EDGE_DET_POS 0x00020000
+#define IOC_IOCFG25_EDGE_DET_NEG 0x00010000
+#define IOC_IOCFG25_EDGE_DET_NONE 0x00000000
+
+// Field: [14:13] PULL_CTL
+//
+// Pull control
+// ENUMs:
+// DIS No pull
+// UP Pull up
+// DWN Pull down
+#define IOC_IOCFG25_PULL_CTL_W 2
+#define IOC_IOCFG25_PULL_CTL_M 0x00006000
+#define IOC_IOCFG25_PULL_CTL_S 13
+#define IOC_IOCFG25_PULL_CTL_DIS 0x00006000
+#define IOC_IOCFG25_PULL_CTL_UP 0x00004000
+#define IOC_IOCFG25_PULL_CTL_DWN 0x00002000
+
+// Field: [12] SLEW_RED
+//
+// 0: Normal slew rate
+// 1: Enables reduced slew rate in output driver.
+#define IOC_IOCFG25_SLEW_RED 0x00001000
+#define IOC_IOCFG25_SLEW_RED_BITN 12
+#define IOC_IOCFG25_SLEW_RED_M 0x00001000
+#define IOC_IOCFG25_SLEW_RED_S 12
+
+// Field: [11:10] IOCURR
+//
+// Selects IO current mode of this IO.
+// ENUMs:
+// 4_8MA Extended-Current (EC) mode: Min 8 mA for double
+// drive strength IOs (min 4 mA for normal IOs)
+// when IOSTR is set to AUTO
+// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set
+// to AUTO
+// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set
+// to AUTO
+#define IOC_IOCFG25_IOCURR_W 2
+#define IOC_IOCFG25_IOCURR_M 0x00000C00
+#define IOC_IOCFG25_IOCURR_S 10
+#define IOC_IOCFG25_IOCURR_4_8MA 0x00000800
+#define IOC_IOCFG25_IOCURR_4MA 0x00000400
+#define IOC_IOCFG25_IOCURR_2MA 0x00000000
+
+// Field: [9:8] IOSTR
+//
+// Select source for drive strength control of this IO.
+// This setting controls the drive strength of the Low-Current (LC) mode.
+// Higher drive strength can be selected in IOCURR
+// ENUMs:
+// MAX Maximum drive strength, controlled by
+// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default
+// values)
+// MED Medium drive strength, controlled by
+// AON_IOC:IOSTRMED (min 2 mA @2.5V with default
+// values)
+// MIN Minimum drive strength, controlled by
+// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default
+// values)
+// AUTO Automatic drive strength, controlled by AON BATMON
+// based on battery voltage. (min 2 mA @VDDS)
+#define IOC_IOCFG25_IOSTR_W 2
+#define IOC_IOCFG25_IOSTR_M 0x00000300
+#define IOC_IOCFG25_IOSTR_S 8
+#define IOC_IOCFG25_IOSTR_MAX 0x00000300
+#define IOC_IOCFG25_IOSTR_MED 0x00000200
+#define IOC_IOCFG25_IOSTR_MIN 0x00000100
+#define IOC_IOCFG25_IOSTR_AUTO 0x00000000
+
+// Field: [7] IOEV_RTC_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert RTC event
+// 1: Input edge detection asserts RTC event
+#define IOC_IOCFG25_IOEV_RTC_EN 0x00000080
+#define IOC_IOCFG25_IOEV_RTC_EN_BITN 7
+#define IOC_IOCFG25_IOEV_RTC_EN_M 0x00000080
+#define IOC_IOCFG25_IOEV_RTC_EN_S 7
+
+// Field: [6] IOEV_MCU_WU_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert MCU_WU event
+// 1: Input edge detection asserts MCU_WU event
+#define IOC_IOCFG25_IOEV_MCU_WU_EN 0x00000040
+#define IOC_IOCFG25_IOEV_MCU_WU_EN_BITN 6
+#define IOC_IOCFG25_IOEV_MCU_WU_EN_M 0x00000040
+#define IOC_IOCFG25_IOEV_MCU_WU_EN_S 6
+
+// Field: [5:0] PORT_ID
+//
+// Selects usage for DIO25
+// ENUMs:
+// RFC_SMI_CL_IN RF Core SMI Command Link In
+// RFC_SMI_CL_OUT RF Core SMI Command Link Out
+// RFC_SMI_DL_IN RF Core SMI Data Link In
+// RFC_SMI_DL_OUT RF Core SMI Data Link Out
+// RFC_GPI1 RF Core Data In 1
+// RFC_GPI0 RF Core Data In 0
+// RFC_GPO3 RF Core Data Out 3
+// RFC_GPO2 RF Core Data Out 2
+// RFC_GPO1 RF Core Data Out 1
+// RFC_GPO0 RF Core Data Out 0
+// RFC_TRC RF Core Trace
+// I2S_MCLK I2S MCLK
+// I2S_BCLK I2S BCLK
+// I2S_WCLK I2S WCLK
+// I2S_AD1 I2S Data 1
+// I2S_AD0 I2S Data 0
+// SSI1_CLK SSI1 CLK
+// SSI1_FSS SSI1 FSS
+// SSI1_TX SSI1 TX
+// SSI1_RX SSI1 RX
+// CPU_SWV CPU SWV
+// PORT_EVENT7 PORT EVENT 7
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT6 PORT EVENT 6
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT5 PORT EVENT 5
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT4 PORT EVENT 4
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT3 PORT EVENT 3
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT2 PORT EVENT 2
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT1 PORT EVENT 1
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT0 PORT EVENT 0
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// UART1_RTS UART1 RTS
+// UART1_CTS UART1 CTS
+// UART1_TX UART1 TX
+// UART1_RX UART1 RX
+// UART0_RTS UART0 RTS
+// UART0_CTS UART0 CTS
+// UART0_TX UART0 TX
+// UART0_RX UART0 RX
+// I2C_MSSCL I2C Clock
+// I2C_MSSDA I2C Data
+// SSI0_CLK SSI0 CLK
+// SSI0_FSS SSI0 FSS
+// SSI0_TX SSI0 TX
+// SSI0_RX SSI0 RX
+// AUX_IO AUX IO
+// AON_CLK32K AON 32 KHz clock (SCLK_LF)
+// GPIO General Purpose IO
+#define IOC_IOCFG25_PORT_ID_W 6
+#define IOC_IOCFG25_PORT_ID_M 0x0000003F
+#define IOC_IOCFG25_PORT_ID_S 0
+#define IOC_IOCFG25_PORT_ID_RFC_SMI_CL_IN 0x00000038
+#define IOC_IOCFG25_PORT_ID_RFC_SMI_CL_OUT 0x00000037
+#define IOC_IOCFG25_PORT_ID_RFC_SMI_DL_IN 0x00000036
+#define IOC_IOCFG25_PORT_ID_RFC_SMI_DL_OUT 0x00000035
+#define IOC_IOCFG25_PORT_ID_RFC_GPI1 0x00000034
+#define IOC_IOCFG25_PORT_ID_RFC_GPI0 0x00000033
+#define IOC_IOCFG25_PORT_ID_RFC_GPO3 0x00000032
+#define IOC_IOCFG25_PORT_ID_RFC_GPO2 0x00000031
+#define IOC_IOCFG25_PORT_ID_RFC_GPO1 0x00000030
+#define IOC_IOCFG25_PORT_ID_RFC_GPO0 0x0000002F
+#define IOC_IOCFG25_PORT_ID_RFC_TRC 0x0000002E
+#define IOC_IOCFG25_PORT_ID_I2S_MCLK 0x00000029
+#define IOC_IOCFG25_PORT_ID_I2S_BCLK 0x00000028
+#define IOC_IOCFG25_PORT_ID_I2S_WCLK 0x00000027
+#define IOC_IOCFG25_PORT_ID_I2S_AD1 0x00000026
+#define IOC_IOCFG25_PORT_ID_I2S_AD0 0x00000025
+#define IOC_IOCFG25_PORT_ID_SSI1_CLK 0x00000024
+#define IOC_IOCFG25_PORT_ID_SSI1_FSS 0x00000023
+#define IOC_IOCFG25_PORT_ID_SSI1_TX 0x00000022
+#define IOC_IOCFG25_PORT_ID_SSI1_RX 0x00000021
+#define IOC_IOCFG25_PORT_ID_CPU_SWV 0x00000020
+#define IOC_IOCFG25_PORT_ID_PORT_EVENT7 0x0000001E
+#define IOC_IOCFG25_PORT_ID_PORT_EVENT6 0x0000001D
+#define IOC_IOCFG25_PORT_ID_PORT_EVENT5 0x0000001C
+#define IOC_IOCFG25_PORT_ID_PORT_EVENT4 0x0000001B
+#define IOC_IOCFG25_PORT_ID_PORT_EVENT3 0x0000001A
+#define IOC_IOCFG25_PORT_ID_PORT_EVENT2 0x00000019
+#define IOC_IOCFG25_PORT_ID_PORT_EVENT1 0x00000018
+#define IOC_IOCFG25_PORT_ID_PORT_EVENT0 0x00000017
+#define IOC_IOCFG25_PORT_ID_UART1_RTS 0x00000016
+#define IOC_IOCFG25_PORT_ID_UART1_CTS 0x00000015
+#define IOC_IOCFG25_PORT_ID_UART1_TX 0x00000014
+#define IOC_IOCFG25_PORT_ID_UART1_RX 0x00000013
+#define IOC_IOCFG25_PORT_ID_UART0_RTS 0x00000012
+#define IOC_IOCFG25_PORT_ID_UART0_CTS 0x00000011
+#define IOC_IOCFG25_PORT_ID_UART0_TX 0x00000010
+#define IOC_IOCFG25_PORT_ID_UART0_RX 0x0000000F
+#define IOC_IOCFG25_PORT_ID_I2C_MSSCL 0x0000000E
+#define IOC_IOCFG25_PORT_ID_I2C_MSSDA 0x0000000D
+#define IOC_IOCFG25_PORT_ID_SSI0_CLK 0x0000000C
+#define IOC_IOCFG25_PORT_ID_SSI0_FSS 0x0000000B
+#define IOC_IOCFG25_PORT_ID_SSI0_TX 0x0000000A
+#define IOC_IOCFG25_PORT_ID_SSI0_RX 0x00000009
+#define IOC_IOCFG25_PORT_ID_AUX_IO 0x00000008
+#define IOC_IOCFG25_PORT_ID_AON_CLK32K 0x00000007
+#define IOC_IOCFG25_PORT_ID_GPIO 0x00000000
+
+//*****************************************************************************
+//
+// Register: IOC_O_IOCFG26
+//
+//*****************************************************************************
+// Field: [30] HYST_EN
+//
+// 0: Input hysteresis disable
+// 1: Input hysteresis enable
+#define IOC_IOCFG26_HYST_EN 0x40000000
+#define IOC_IOCFG26_HYST_EN_BITN 30
+#define IOC_IOCFG26_HYST_EN_M 0x40000000
+#define IOC_IOCFG26_HYST_EN_S 30
+
+// Field: [29] IE
+//
+// 0: Input disabled
+// 1: Input enabled
+//
+// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be
+// ignored.
+#define IOC_IOCFG26_IE 0x20000000
+#define IOC_IOCFG26_IE_BITN 29
+#define IOC_IOCFG26_IE_M 0x20000000
+#define IOC_IOCFG26_IE_S 29
+
+// Field: [28:27] WU_CFG
+//
+// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or
+// >0x08:
+//
+// 00: No wake-up
+// 01: No wake-up
+// 10: Wakes up from shutdown if this pad is going low.
+// 11: Wakes up from shutdown if this pad is going high.
+//
+// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08,
+// this register only sets wakeup enable or not.
+//
+// 00, 01: Wakeup disabled
+// 10, 11: Wakeup enabled
+//
+// Polarity is controlled from AON registers.
+//
+// Note:When the MSB is set, the IOC will deactivate the output enable for the
+// DIO.
+#define IOC_IOCFG26_WU_CFG_W 2
+#define IOC_IOCFG26_WU_CFG_M 0x18000000
+#define IOC_IOCFG26_WU_CFG_S 27
+
+// Field: [26:24] IOMODE
+//
+// IO Mode
+// Not applicable for IO configured for AON periph. signals and AUX PORT_ID
+// 0x01-0x08
+// AUX has its own open_source/drain configuration.
+//
+// 0x2: Reserved. Undefined behavior.
+// 0x3: Reserved. Undefined behavior.
+// ENUMs:
+// OPENSRC_INV Open Source
+// Inverted input / output
+// OPENSRC Open Source
+// Normal input / output
+// OPENDR_INV Open Drain
+// Inverted input / output
+// OPENDR Open Drain,
+// Normal input / output
+// INV Inverted input / ouput
+// NORMAL Normal input / output
+#define IOC_IOCFG26_IOMODE_W 3
+#define IOC_IOCFG26_IOMODE_M 0x07000000
+#define IOC_IOCFG26_IOMODE_S 24
+#define IOC_IOCFG26_IOMODE_OPENSRC_INV 0x07000000
+#define IOC_IOCFG26_IOMODE_OPENSRC 0x06000000
+#define IOC_IOCFG26_IOMODE_OPENDR_INV 0x05000000
+#define IOC_IOCFG26_IOMODE_OPENDR 0x04000000
+#define IOC_IOCFG26_IOMODE_INV 0x01000000
+#define IOC_IOCFG26_IOMODE_NORMAL 0x00000000
+
+// Field: [23] IOEV_AON_PROG2_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG2 event
+// 1: Input edge detection asserts AON_PROG2 event
+#define IOC_IOCFG26_IOEV_AON_PROG2_EN 0x00800000
+#define IOC_IOCFG26_IOEV_AON_PROG2_EN_BITN 23
+#define IOC_IOCFG26_IOEV_AON_PROG2_EN_M 0x00800000
+#define IOC_IOCFG26_IOEV_AON_PROG2_EN_S 23
+
+// Field: [22] IOEV_AON_PROG1_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG1 event
+// 1: Input edge detection asserts AON_PROG1 event
+#define IOC_IOCFG26_IOEV_AON_PROG1_EN 0x00400000
+#define IOC_IOCFG26_IOEV_AON_PROG1_EN_BITN 22
+#define IOC_IOCFG26_IOEV_AON_PROG1_EN_M 0x00400000
+#define IOC_IOCFG26_IOEV_AON_PROG1_EN_S 22
+
+// Field: [21] IOEV_AON_PROG0_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG0 event
+// 1: Input edge detection asserts AON_PROG0 event
+#define IOC_IOCFG26_IOEV_AON_PROG0_EN 0x00200000
+#define IOC_IOCFG26_IOEV_AON_PROG0_EN_BITN 21
+#define IOC_IOCFG26_IOEV_AON_PROG0_EN_M 0x00200000
+#define IOC_IOCFG26_IOEV_AON_PROG0_EN_S 21
+
+// Field: [18] EDGE_IRQ_EN
+//
+// 0: No interrupt generation
+// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is
+// enabled)
+#define IOC_IOCFG26_EDGE_IRQ_EN 0x00040000
+#define IOC_IOCFG26_EDGE_IRQ_EN_BITN 18
+#define IOC_IOCFG26_EDGE_IRQ_EN_M 0x00040000
+#define IOC_IOCFG26_EDGE_IRQ_EN_S 18
+
+// Field: [17:16] EDGE_DET
+//
+// Enable generation of edge detection events on this IO
+// ENUMs:
+// BOTH Positive and negative edge detection
+// POS Positive edge detection
+// NEG Negative edge detection
+// NONE No edge detection
+#define IOC_IOCFG26_EDGE_DET_W 2
+#define IOC_IOCFG26_EDGE_DET_M 0x00030000
+#define IOC_IOCFG26_EDGE_DET_S 16
+#define IOC_IOCFG26_EDGE_DET_BOTH 0x00030000
+#define IOC_IOCFG26_EDGE_DET_POS 0x00020000
+#define IOC_IOCFG26_EDGE_DET_NEG 0x00010000
+#define IOC_IOCFG26_EDGE_DET_NONE 0x00000000
+
+// Field: [14:13] PULL_CTL
+//
+// Pull control
+// ENUMs:
+// DIS No pull
+// UP Pull up
+// DWN Pull down
+#define IOC_IOCFG26_PULL_CTL_W 2
+#define IOC_IOCFG26_PULL_CTL_M 0x00006000
+#define IOC_IOCFG26_PULL_CTL_S 13
+#define IOC_IOCFG26_PULL_CTL_DIS 0x00006000
+#define IOC_IOCFG26_PULL_CTL_UP 0x00004000
+#define IOC_IOCFG26_PULL_CTL_DWN 0x00002000
+
+// Field: [12] SLEW_RED
+//
+// 0: Normal slew rate
+// 1: Enables reduced slew rate in output driver.
+#define IOC_IOCFG26_SLEW_RED 0x00001000
+#define IOC_IOCFG26_SLEW_RED_BITN 12
+#define IOC_IOCFG26_SLEW_RED_M 0x00001000
+#define IOC_IOCFG26_SLEW_RED_S 12
+
+// Field: [11:10] IOCURR
+//
+// Selects IO current mode of this IO.
+// ENUMs:
+// 4_8MA Extended-Current (EC) mode: Min 8 mA for double
+// drive strength IOs (min 4 mA for normal IOs)
+// when IOSTR is set to AUTO
+// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set
+// to AUTO
+// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set
+// to AUTO
+#define IOC_IOCFG26_IOCURR_W 2
+#define IOC_IOCFG26_IOCURR_M 0x00000C00
+#define IOC_IOCFG26_IOCURR_S 10
+#define IOC_IOCFG26_IOCURR_4_8MA 0x00000800
+#define IOC_IOCFG26_IOCURR_4MA 0x00000400
+#define IOC_IOCFG26_IOCURR_2MA 0x00000000
+
+// Field: [9:8] IOSTR
+//
+// Select source for drive strength control of this IO.
+// This setting controls the drive strength of the Low-Current (LC) mode.
+// Higher drive strength can be selected in IOCURR
+// ENUMs:
+// MAX Maximum drive strength, controlled by
+// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default
+// values)
+// MED Medium drive strength, controlled by
+// AON_IOC:IOSTRMED (min 2 mA @2.5V with default
+// values)
+// MIN Minimum drive strength, controlled by
+// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default
+// values)
+// AUTO Automatic drive strength, controlled by AON BATMON
+// based on battery voltage. (min 2 mA @VDDS)
+#define IOC_IOCFG26_IOSTR_W 2
+#define IOC_IOCFG26_IOSTR_M 0x00000300
+#define IOC_IOCFG26_IOSTR_S 8
+#define IOC_IOCFG26_IOSTR_MAX 0x00000300
+#define IOC_IOCFG26_IOSTR_MED 0x00000200
+#define IOC_IOCFG26_IOSTR_MIN 0x00000100
+#define IOC_IOCFG26_IOSTR_AUTO 0x00000000
+
+// Field: [7] IOEV_RTC_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert RTC event
+// 1: Input edge detection asserts RTC event
+#define IOC_IOCFG26_IOEV_RTC_EN 0x00000080
+#define IOC_IOCFG26_IOEV_RTC_EN_BITN 7
+#define IOC_IOCFG26_IOEV_RTC_EN_M 0x00000080
+#define IOC_IOCFG26_IOEV_RTC_EN_S 7
+
+// Field: [6] IOEV_MCU_WU_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert MCU_WU event
+// 1: Input edge detection asserts MCU_WU event
+#define IOC_IOCFG26_IOEV_MCU_WU_EN 0x00000040
+#define IOC_IOCFG26_IOEV_MCU_WU_EN_BITN 6
+#define IOC_IOCFG26_IOEV_MCU_WU_EN_M 0x00000040
+#define IOC_IOCFG26_IOEV_MCU_WU_EN_S 6
+
+// Field: [5:0] PORT_ID
+//
+// Selects usage for DIO26
+// ENUMs:
+// RFC_SMI_CL_IN RF Core SMI Command Link In
+// RFC_SMI_CL_OUT RF Core SMI Command Link Out
+// RFC_SMI_DL_IN RF Core SMI Data Link In
+// RFC_SMI_DL_OUT RF Core SMI Data Link Out
+// RFC_GPI1 RF Core Data In 1
+// RFC_GPI0 RF Core Data In 0
+// RFC_GPO3 RF Core Data Out 3
+// RFC_GPO2 RF Core Data Out 2
+// RFC_GPO1 RF Core Data Out 1
+// RFC_GPO0 RF Core Data Out 0
+// RFC_TRC RF Core Trace
+// I2S_MCLK I2S MCLK
+// I2S_BCLK I2S BCLK
+// I2S_WCLK I2S WCLK
+// I2S_AD1 I2S Data 1
+// I2S_AD0 I2S Data 0
+// SSI1_CLK SSI1 CLK
+// SSI1_FSS SSI1 FSS
+// SSI1_TX SSI1 TX
+// SSI1_RX SSI1 RX
+// CPU_SWV CPU SWV
+// PORT_EVENT7 PORT EVENT 7
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT6 PORT EVENT 6
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT5 PORT EVENT 5
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT4 PORT EVENT 4
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT3 PORT EVENT 3
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT2 PORT EVENT 2
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT1 PORT EVENT 1
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT0 PORT EVENT 0
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// UART1_RTS UART1 RTS
+// UART1_CTS UART1 CTS
+// UART1_TX UART1 TX
+// UART1_RX UART1 RX
+// UART0_RTS UART0 RTS
+// UART0_CTS UART0 CTS
+// UART0_TX UART0 TX
+// UART0_RX UART0 RX
+// I2C_MSSCL I2C Clock
+// I2C_MSSDA I2C Data
+// SSI0_CLK SSI0 CLK
+// SSI0_FSS SSI0 FSS
+// SSI0_TX SSI0 TX
+// SSI0_RX SSI0 RX
+// AUX_IO AUX IO
+// AON_CLK32K AON 32 KHz clock (SCLK_LF)
+// GPIO General Purpose IO
+#define IOC_IOCFG26_PORT_ID_W 6
+#define IOC_IOCFG26_PORT_ID_M 0x0000003F
+#define IOC_IOCFG26_PORT_ID_S 0
+#define IOC_IOCFG26_PORT_ID_RFC_SMI_CL_IN 0x00000038
+#define IOC_IOCFG26_PORT_ID_RFC_SMI_CL_OUT 0x00000037
+#define IOC_IOCFG26_PORT_ID_RFC_SMI_DL_IN 0x00000036
+#define IOC_IOCFG26_PORT_ID_RFC_SMI_DL_OUT 0x00000035
+#define IOC_IOCFG26_PORT_ID_RFC_GPI1 0x00000034
+#define IOC_IOCFG26_PORT_ID_RFC_GPI0 0x00000033
+#define IOC_IOCFG26_PORT_ID_RFC_GPO3 0x00000032
+#define IOC_IOCFG26_PORT_ID_RFC_GPO2 0x00000031
+#define IOC_IOCFG26_PORT_ID_RFC_GPO1 0x00000030
+#define IOC_IOCFG26_PORT_ID_RFC_GPO0 0x0000002F
+#define IOC_IOCFG26_PORT_ID_RFC_TRC 0x0000002E
+#define IOC_IOCFG26_PORT_ID_I2S_MCLK 0x00000029
+#define IOC_IOCFG26_PORT_ID_I2S_BCLK 0x00000028
+#define IOC_IOCFG26_PORT_ID_I2S_WCLK 0x00000027
+#define IOC_IOCFG26_PORT_ID_I2S_AD1 0x00000026
+#define IOC_IOCFG26_PORT_ID_I2S_AD0 0x00000025
+#define IOC_IOCFG26_PORT_ID_SSI1_CLK 0x00000024
+#define IOC_IOCFG26_PORT_ID_SSI1_FSS 0x00000023
+#define IOC_IOCFG26_PORT_ID_SSI1_TX 0x00000022
+#define IOC_IOCFG26_PORT_ID_SSI1_RX 0x00000021
+#define IOC_IOCFG26_PORT_ID_CPU_SWV 0x00000020
+#define IOC_IOCFG26_PORT_ID_PORT_EVENT7 0x0000001E
+#define IOC_IOCFG26_PORT_ID_PORT_EVENT6 0x0000001D
+#define IOC_IOCFG26_PORT_ID_PORT_EVENT5 0x0000001C
+#define IOC_IOCFG26_PORT_ID_PORT_EVENT4 0x0000001B
+#define IOC_IOCFG26_PORT_ID_PORT_EVENT3 0x0000001A
+#define IOC_IOCFG26_PORT_ID_PORT_EVENT2 0x00000019
+#define IOC_IOCFG26_PORT_ID_PORT_EVENT1 0x00000018
+#define IOC_IOCFG26_PORT_ID_PORT_EVENT0 0x00000017
+#define IOC_IOCFG26_PORT_ID_UART1_RTS 0x00000016
+#define IOC_IOCFG26_PORT_ID_UART1_CTS 0x00000015
+#define IOC_IOCFG26_PORT_ID_UART1_TX 0x00000014
+#define IOC_IOCFG26_PORT_ID_UART1_RX 0x00000013
+#define IOC_IOCFG26_PORT_ID_UART0_RTS 0x00000012
+#define IOC_IOCFG26_PORT_ID_UART0_CTS 0x00000011
+#define IOC_IOCFG26_PORT_ID_UART0_TX 0x00000010
+#define IOC_IOCFG26_PORT_ID_UART0_RX 0x0000000F
+#define IOC_IOCFG26_PORT_ID_I2C_MSSCL 0x0000000E
+#define IOC_IOCFG26_PORT_ID_I2C_MSSDA 0x0000000D
+#define IOC_IOCFG26_PORT_ID_SSI0_CLK 0x0000000C
+#define IOC_IOCFG26_PORT_ID_SSI0_FSS 0x0000000B
+#define IOC_IOCFG26_PORT_ID_SSI0_TX 0x0000000A
+#define IOC_IOCFG26_PORT_ID_SSI0_RX 0x00000009
+#define IOC_IOCFG26_PORT_ID_AUX_IO 0x00000008
+#define IOC_IOCFG26_PORT_ID_AON_CLK32K 0x00000007
+#define IOC_IOCFG26_PORT_ID_GPIO 0x00000000
+
+//*****************************************************************************
+//
+// Register: IOC_O_IOCFG27
+//
+//*****************************************************************************
+// Field: [30] HYST_EN
+//
+// 0: Input hysteresis disable
+// 1: Input hysteresis enable
+#define IOC_IOCFG27_HYST_EN 0x40000000
+#define IOC_IOCFG27_HYST_EN_BITN 30
+#define IOC_IOCFG27_HYST_EN_M 0x40000000
+#define IOC_IOCFG27_HYST_EN_S 30
+
+// Field: [29] IE
+//
+// 0: Input disabled
+// 1: Input enabled
+//
+// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be
+// ignored.
+#define IOC_IOCFG27_IE 0x20000000
+#define IOC_IOCFG27_IE_BITN 29
+#define IOC_IOCFG27_IE_M 0x20000000
+#define IOC_IOCFG27_IE_S 29
+
+// Field: [28:27] WU_CFG
+//
+// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or
+// >0x08:
+//
+// 00: No wake-up
+// 01: No wake-up
+// 10: Wakes up from shutdown if this pad is going low.
+// 11: Wakes up from shutdown if this pad is going high.
+//
+// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08,
+// this register only sets wakeup enable or not.
+//
+// 00, 01: Wakeup disabled
+// 10, 11: Wakeup enabled
+//
+// Polarity is controlled from AON registers.
+//
+// Note:When the MSB is set, the IOC will deactivate the output enable for the
+// DIO.
+#define IOC_IOCFG27_WU_CFG_W 2
+#define IOC_IOCFG27_WU_CFG_M 0x18000000
+#define IOC_IOCFG27_WU_CFG_S 27
+
+// Field: [26:24] IOMODE
+//
+// IO Mode
+// Not applicable for IO configured for AON periph. signals and AUX PORT_ID
+// 0x01-0x08
+// AUX has its own open_source/drain configuration.
+//
+// 0x2: Reserved. Undefined behavior.
+// 0x3: Reserved. Undefined behavior.
+// ENUMs:
+// OPENSRC_INV Open Source
+// Inverted input / output
+// OPENSRC Open Source
+// Normal input / output
+// OPENDR_INV Open Drain
+// Inverted input / output
+// OPENDR Open Drain,
+// Normal input / output
+// INV Inverted input / ouput
+// NORMAL Normal input / output
+#define IOC_IOCFG27_IOMODE_W 3
+#define IOC_IOCFG27_IOMODE_M 0x07000000
+#define IOC_IOCFG27_IOMODE_S 24
+#define IOC_IOCFG27_IOMODE_OPENSRC_INV 0x07000000
+#define IOC_IOCFG27_IOMODE_OPENSRC 0x06000000
+#define IOC_IOCFG27_IOMODE_OPENDR_INV 0x05000000
+#define IOC_IOCFG27_IOMODE_OPENDR 0x04000000
+#define IOC_IOCFG27_IOMODE_INV 0x01000000
+#define IOC_IOCFG27_IOMODE_NORMAL 0x00000000
+
+// Field: [23] IOEV_AON_PROG2_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG2 event
+// 1: Input edge detection asserts AON_PROG2 event
+#define IOC_IOCFG27_IOEV_AON_PROG2_EN 0x00800000
+#define IOC_IOCFG27_IOEV_AON_PROG2_EN_BITN 23
+#define IOC_IOCFG27_IOEV_AON_PROG2_EN_M 0x00800000
+#define IOC_IOCFG27_IOEV_AON_PROG2_EN_S 23
+
+// Field: [22] IOEV_AON_PROG1_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG1 event
+// 1: Input edge detection asserts AON_PROG1 event
+#define IOC_IOCFG27_IOEV_AON_PROG1_EN 0x00400000
+#define IOC_IOCFG27_IOEV_AON_PROG1_EN_BITN 22
+#define IOC_IOCFG27_IOEV_AON_PROG1_EN_M 0x00400000
+#define IOC_IOCFG27_IOEV_AON_PROG1_EN_S 22
+
+// Field: [21] IOEV_AON_PROG0_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG0 event
+// 1: Input edge detection asserts AON_PROG0 event
+#define IOC_IOCFG27_IOEV_AON_PROG0_EN 0x00200000
+#define IOC_IOCFG27_IOEV_AON_PROG0_EN_BITN 21
+#define IOC_IOCFG27_IOEV_AON_PROG0_EN_M 0x00200000
+#define IOC_IOCFG27_IOEV_AON_PROG0_EN_S 21
+
+// Field: [18] EDGE_IRQ_EN
+//
+// 0: No interrupt generation
+// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is
+// enabled)
+#define IOC_IOCFG27_EDGE_IRQ_EN 0x00040000
+#define IOC_IOCFG27_EDGE_IRQ_EN_BITN 18
+#define IOC_IOCFG27_EDGE_IRQ_EN_M 0x00040000
+#define IOC_IOCFG27_EDGE_IRQ_EN_S 18
+
+// Field: [17:16] EDGE_DET
+//
+// Enable generation of edge detection events on this IO
+// ENUMs:
+// BOTH Positive and negative edge detection
+// POS Positive edge detection
+// NEG Negative edge detection
+// NONE No edge detection
+#define IOC_IOCFG27_EDGE_DET_W 2
+#define IOC_IOCFG27_EDGE_DET_M 0x00030000
+#define IOC_IOCFG27_EDGE_DET_S 16
+#define IOC_IOCFG27_EDGE_DET_BOTH 0x00030000
+#define IOC_IOCFG27_EDGE_DET_POS 0x00020000
+#define IOC_IOCFG27_EDGE_DET_NEG 0x00010000
+#define IOC_IOCFG27_EDGE_DET_NONE 0x00000000
+
+// Field: [14:13] PULL_CTL
+//
+// Pull control
+// ENUMs:
+// DIS No pull
+// UP Pull up
+// DWN Pull down
+#define IOC_IOCFG27_PULL_CTL_W 2
+#define IOC_IOCFG27_PULL_CTL_M 0x00006000
+#define IOC_IOCFG27_PULL_CTL_S 13
+#define IOC_IOCFG27_PULL_CTL_DIS 0x00006000
+#define IOC_IOCFG27_PULL_CTL_UP 0x00004000
+#define IOC_IOCFG27_PULL_CTL_DWN 0x00002000
+
+// Field: [12] SLEW_RED
+//
+// 0: Normal slew rate
+// 1: Enables reduced slew rate in output driver.
+#define IOC_IOCFG27_SLEW_RED 0x00001000
+#define IOC_IOCFG27_SLEW_RED_BITN 12
+#define IOC_IOCFG27_SLEW_RED_M 0x00001000
+#define IOC_IOCFG27_SLEW_RED_S 12
+
+// Field: [11:10] IOCURR
+//
+// Selects IO current mode of this IO.
+// ENUMs:
+// 4_8MA Extended-Current (EC) mode: Min 8 mA for double
+// drive strength IOs (min 4 mA for normal IOs)
+// when IOSTR is set to AUTO
+// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set
+// to AUTO
+// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set
+// to AUTO
+#define IOC_IOCFG27_IOCURR_W 2
+#define IOC_IOCFG27_IOCURR_M 0x00000C00
+#define IOC_IOCFG27_IOCURR_S 10
+#define IOC_IOCFG27_IOCURR_4_8MA 0x00000800
+#define IOC_IOCFG27_IOCURR_4MA 0x00000400
+#define IOC_IOCFG27_IOCURR_2MA 0x00000000
+
+// Field: [9:8] IOSTR
+//
+// Select source for drive strength control of this IO.
+// This setting controls the drive strength of the Low-Current (LC) mode.
+// Higher drive strength can be selected in IOCURR
+// ENUMs:
+// MAX Maximum drive strength, controlled by
+// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default
+// values)
+// MED Medium drive strength, controlled by
+// AON_IOC:IOSTRMED (min 2 mA @2.5V with default
+// values)
+// MIN Minimum drive strength, controlled by
+// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default
+// values)
+// AUTO Automatic drive strength, controlled by AON BATMON
+// based on battery voltage. (min 2 mA @VDDS)
+#define IOC_IOCFG27_IOSTR_W 2
+#define IOC_IOCFG27_IOSTR_M 0x00000300
+#define IOC_IOCFG27_IOSTR_S 8
+#define IOC_IOCFG27_IOSTR_MAX 0x00000300
+#define IOC_IOCFG27_IOSTR_MED 0x00000200
+#define IOC_IOCFG27_IOSTR_MIN 0x00000100
+#define IOC_IOCFG27_IOSTR_AUTO 0x00000000
+
+// Field: [7] IOEV_RTC_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert RTC event
+// 1: Input edge detection asserts RTC event
+#define IOC_IOCFG27_IOEV_RTC_EN 0x00000080
+#define IOC_IOCFG27_IOEV_RTC_EN_BITN 7
+#define IOC_IOCFG27_IOEV_RTC_EN_M 0x00000080
+#define IOC_IOCFG27_IOEV_RTC_EN_S 7
+
+// Field: [6] IOEV_MCU_WU_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert MCU_WU event
+// 1: Input edge detection asserts MCU_WU event
+#define IOC_IOCFG27_IOEV_MCU_WU_EN 0x00000040
+#define IOC_IOCFG27_IOEV_MCU_WU_EN_BITN 6
+#define IOC_IOCFG27_IOEV_MCU_WU_EN_M 0x00000040
+#define IOC_IOCFG27_IOEV_MCU_WU_EN_S 6
+
+// Field: [5:0] PORT_ID
+//
+// Selects usage for DIO27
+// ENUMs:
+// RFC_SMI_CL_IN RF Core SMI Command Link In
+// RFC_SMI_CL_OUT RF Core SMI Command Link Out
+// RFC_SMI_DL_IN RF Core SMI Data Link In
+// RFC_SMI_DL_OUT RF Core SMI Data Link Out
+// RFC_GPI1 RF Core Data In 1
+// RFC_GPI0 RF Core Data In 0
+// RFC_GPO3 RF Core Data Out 3
+// RFC_GPO2 RF Core Data Out 2
+// RFC_GPO1 RF Core Data Out 1
+// RFC_GPO0 RF Core Data Out 0
+// RFC_TRC RF Core Trace
+// I2S_MCLK I2S MCLK
+// I2S_BCLK I2S BCLK
+// I2S_WCLK I2S WCLK
+// I2S_AD1 I2S Data 1
+// I2S_AD0 I2S Data 0
+// SSI1_CLK SSI1 CLK
+// SSI1_FSS SSI1 FSS
+// SSI1_TX SSI1 TX
+// SSI1_RX SSI1 RX
+// CPU_SWV CPU SWV
+// PORT_EVENT7 PORT EVENT 7
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT6 PORT EVENT 6
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT5 PORT EVENT 5
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT4 PORT EVENT 4
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT3 PORT EVENT 3
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT2 PORT EVENT 2
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT1 PORT EVENT 1
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT0 PORT EVENT 0
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// UART1_RTS UART1 RTS
+// UART1_CTS UART1 CTS
+// UART1_TX UART1 TX
+// UART1_RX UART1 RX
+// UART0_RTS UART0 RTS
+// UART0_CTS UART0 CTS
+// UART0_TX UART0 TX
+// UART0_RX UART0 RX
+// I2C_MSSCL I2C Clock
+// I2C_MSSDA I2C Data
+// SSI0_CLK SSI0 CLK
+// SSI0_FSS SSI0 FSS
+// SSI0_TX SSI0 TX
+// SSI0_RX SSI0 RX
+// AUX_IO AUX IO
+// AON_CLK32K AON 32 KHz clock (SCLK_LF)
+// GPIO General Purpose IO
+#define IOC_IOCFG27_PORT_ID_W 6
+#define IOC_IOCFG27_PORT_ID_M 0x0000003F
+#define IOC_IOCFG27_PORT_ID_S 0
+#define IOC_IOCFG27_PORT_ID_RFC_SMI_CL_IN 0x00000038
+#define IOC_IOCFG27_PORT_ID_RFC_SMI_CL_OUT 0x00000037
+#define IOC_IOCFG27_PORT_ID_RFC_SMI_DL_IN 0x00000036
+#define IOC_IOCFG27_PORT_ID_RFC_SMI_DL_OUT 0x00000035
+#define IOC_IOCFG27_PORT_ID_RFC_GPI1 0x00000034
+#define IOC_IOCFG27_PORT_ID_RFC_GPI0 0x00000033
+#define IOC_IOCFG27_PORT_ID_RFC_GPO3 0x00000032
+#define IOC_IOCFG27_PORT_ID_RFC_GPO2 0x00000031
+#define IOC_IOCFG27_PORT_ID_RFC_GPO1 0x00000030
+#define IOC_IOCFG27_PORT_ID_RFC_GPO0 0x0000002F
+#define IOC_IOCFG27_PORT_ID_RFC_TRC 0x0000002E
+#define IOC_IOCFG27_PORT_ID_I2S_MCLK 0x00000029
+#define IOC_IOCFG27_PORT_ID_I2S_BCLK 0x00000028
+#define IOC_IOCFG27_PORT_ID_I2S_WCLK 0x00000027
+#define IOC_IOCFG27_PORT_ID_I2S_AD1 0x00000026
+#define IOC_IOCFG27_PORT_ID_I2S_AD0 0x00000025
+#define IOC_IOCFG27_PORT_ID_SSI1_CLK 0x00000024
+#define IOC_IOCFG27_PORT_ID_SSI1_FSS 0x00000023
+#define IOC_IOCFG27_PORT_ID_SSI1_TX 0x00000022
+#define IOC_IOCFG27_PORT_ID_SSI1_RX 0x00000021
+#define IOC_IOCFG27_PORT_ID_CPU_SWV 0x00000020
+#define IOC_IOCFG27_PORT_ID_PORT_EVENT7 0x0000001E
+#define IOC_IOCFG27_PORT_ID_PORT_EVENT6 0x0000001D
+#define IOC_IOCFG27_PORT_ID_PORT_EVENT5 0x0000001C
+#define IOC_IOCFG27_PORT_ID_PORT_EVENT4 0x0000001B
+#define IOC_IOCFG27_PORT_ID_PORT_EVENT3 0x0000001A
+#define IOC_IOCFG27_PORT_ID_PORT_EVENT2 0x00000019
+#define IOC_IOCFG27_PORT_ID_PORT_EVENT1 0x00000018
+#define IOC_IOCFG27_PORT_ID_PORT_EVENT0 0x00000017
+#define IOC_IOCFG27_PORT_ID_UART1_RTS 0x00000016
+#define IOC_IOCFG27_PORT_ID_UART1_CTS 0x00000015
+#define IOC_IOCFG27_PORT_ID_UART1_TX 0x00000014
+#define IOC_IOCFG27_PORT_ID_UART1_RX 0x00000013
+#define IOC_IOCFG27_PORT_ID_UART0_RTS 0x00000012
+#define IOC_IOCFG27_PORT_ID_UART0_CTS 0x00000011
+#define IOC_IOCFG27_PORT_ID_UART0_TX 0x00000010
+#define IOC_IOCFG27_PORT_ID_UART0_RX 0x0000000F
+#define IOC_IOCFG27_PORT_ID_I2C_MSSCL 0x0000000E
+#define IOC_IOCFG27_PORT_ID_I2C_MSSDA 0x0000000D
+#define IOC_IOCFG27_PORT_ID_SSI0_CLK 0x0000000C
+#define IOC_IOCFG27_PORT_ID_SSI0_FSS 0x0000000B
+#define IOC_IOCFG27_PORT_ID_SSI0_TX 0x0000000A
+#define IOC_IOCFG27_PORT_ID_SSI0_RX 0x00000009
+#define IOC_IOCFG27_PORT_ID_AUX_IO 0x00000008
+#define IOC_IOCFG27_PORT_ID_AON_CLK32K 0x00000007
+#define IOC_IOCFG27_PORT_ID_GPIO 0x00000000
+
+//*****************************************************************************
+//
+// Register: IOC_O_IOCFG28
+//
+//*****************************************************************************
+// Field: [30] HYST_EN
+//
+// 0: Input hysteresis disable
+// 1: Input hysteresis enable
+#define IOC_IOCFG28_HYST_EN 0x40000000
+#define IOC_IOCFG28_HYST_EN_BITN 30
+#define IOC_IOCFG28_HYST_EN_M 0x40000000
+#define IOC_IOCFG28_HYST_EN_S 30
+
+// Field: [29] IE
+//
+// 0: Input disabled
+// 1: Input enabled
+//
+// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be
+// ignored.
+#define IOC_IOCFG28_IE 0x20000000
+#define IOC_IOCFG28_IE_BITN 29
+#define IOC_IOCFG28_IE_M 0x20000000
+#define IOC_IOCFG28_IE_S 29
+
+// Field: [28:27] WU_CFG
+//
+// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or
+// >0x08:
+//
+// 00: No wake-up
+// 01: No wake-up
+// 10: Wakes up from shutdown if this pad is going low.
+// 11: Wakes up from shutdown if this pad is going high.
+//
+// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08,
+// this register only sets wakeup enable or not.
+//
+// 00, 01: Wakeup disabled
+// 10, 11: Wakeup enabled
+//
+// Polarity is controlled from AON registers.
+//
+// Note:When the MSB is set, the IOC will deactivate the output enable for the
+// DIO.
+#define IOC_IOCFG28_WU_CFG_W 2
+#define IOC_IOCFG28_WU_CFG_M 0x18000000
+#define IOC_IOCFG28_WU_CFG_S 27
+
+// Field: [26:24] IOMODE
+//
+// IO Mode
+// Not applicable for IO configured for AON periph. signals and AUX PORT_ID
+// 0x01-0x08
+// AUX has its own open_source/drain configuration.
+//
+// 0x2: Reserved. Undefined behavior.
+// 0x3: Reserved. Undefined behavior.
+// ENUMs:
+// OPENSRC_INV Open Source
+// Inverted input / output
+// OPENSRC Open Source
+// Normal input / output
+// OPENDR_INV Open Drain
+// Inverted input / output
+// OPENDR Open Drain,
+// Normal input / output
+// INV Inverted input / ouput
+// NORMAL Normal input / output
+#define IOC_IOCFG28_IOMODE_W 3
+#define IOC_IOCFG28_IOMODE_M 0x07000000
+#define IOC_IOCFG28_IOMODE_S 24
+#define IOC_IOCFG28_IOMODE_OPENSRC_INV 0x07000000
+#define IOC_IOCFG28_IOMODE_OPENSRC 0x06000000
+#define IOC_IOCFG28_IOMODE_OPENDR_INV 0x05000000
+#define IOC_IOCFG28_IOMODE_OPENDR 0x04000000
+#define IOC_IOCFG28_IOMODE_INV 0x01000000
+#define IOC_IOCFG28_IOMODE_NORMAL 0x00000000
+
+// Field: [23] IOEV_AON_PROG2_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG2 event
+// 1: Input edge detection asserts AON_PROG2 event
+#define IOC_IOCFG28_IOEV_AON_PROG2_EN 0x00800000
+#define IOC_IOCFG28_IOEV_AON_PROG2_EN_BITN 23
+#define IOC_IOCFG28_IOEV_AON_PROG2_EN_M 0x00800000
+#define IOC_IOCFG28_IOEV_AON_PROG2_EN_S 23
+
+// Field: [22] IOEV_AON_PROG1_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG1 event
+// 1: Input edge detection asserts AON_PROG1 event
+#define IOC_IOCFG28_IOEV_AON_PROG1_EN 0x00400000
+#define IOC_IOCFG28_IOEV_AON_PROG1_EN_BITN 22
+#define IOC_IOCFG28_IOEV_AON_PROG1_EN_M 0x00400000
+#define IOC_IOCFG28_IOEV_AON_PROG1_EN_S 22
+
+// Field: [21] IOEV_AON_PROG0_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG0 event
+// 1: Input edge detection asserts AON_PROG0 event
+#define IOC_IOCFG28_IOEV_AON_PROG0_EN 0x00200000
+#define IOC_IOCFG28_IOEV_AON_PROG0_EN_BITN 21
+#define IOC_IOCFG28_IOEV_AON_PROG0_EN_M 0x00200000
+#define IOC_IOCFG28_IOEV_AON_PROG0_EN_S 21
+
+// Field: [18] EDGE_IRQ_EN
+//
+// 0: No interrupt generation
+// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is
+// enabled)
+#define IOC_IOCFG28_EDGE_IRQ_EN 0x00040000
+#define IOC_IOCFG28_EDGE_IRQ_EN_BITN 18
+#define IOC_IOCFG28_EDGE_IRQ_EN_M 0x00040000
+#define IOC_IOCFG28_EDGE_IRQ_EN_S 18
+
+// Field: [17:16] EDGE_DET
+//
+// Enable generation of edge detection events on this IO
+// ENUMs:
+// BOTH Positive and negative edge detection
+// POS Positive edge detection
+// NEG Negative edge detection
+// NONE No edge detection
+#define IOC_IOCFG28_EDGE_DET_W 2
+#define IOC_IOCFG28_EDGE_DET_M 0x00030000
+#define IOC_IOCFG28_EDGE_DET_S 16
+#define IOC_IOCFG28_EDGE_DET_BOTH 0x00030000
+#define IOC_IOCFG28_EDGE_DET_POS 0x00020000
+#define IOC_IOCFG28_EDGE_DET_NEG 0x00010000
+#define IOC_IOCFG28_EDGE_DET_NONE 0x00000000
+
+// Field: [14:13] PULL_CTL
+//
+// Pull control
+// ENUMs:
+// DIS No pull
+// UP Pull up
+// DWN Pull down
+#define IOC_IOCFG28_PULL_CTL_W 2
+#define IOC_IOCFG28_PULL_CTL_M 0x00006000
+#define IOC_IOCFG28_PULL_CTL_S 13
+#define IOC_IOCFG28_PULL_CTL_DIS 0x00006000
+#define IOC_IOCFG28_PULL_CTL_UP 0x00004000
+#define IOC_IOCFG28_PULL_CTL_DWN 0x00002000
+
+// Field: [12] SLEW_RED
+//
+// 0: Normal slew rate
+// 1: Enables reduced slew rate in output driver.
+#define IOC_IOCFG28_SLEW_RED 0x00001000
+#define IOC_IOCFG28_SLEW_RED_BITN 12
+#define IOC_IOCFG28_SLEW_RED_M 0x00001000
+#define IOC_IOCFG28_SLEW_RED_S 12
+
+// Field: [11:10] IOCURR
+//
+// Selects IO current mode of this IO.
+// ENUMs:
+// 4_8MA Extended-Current (EC) mode: Min 8 mA for double
+// drive strength IOs (min 4 mA for normal IOs)
+// when IOSTR is set to AUTO
+// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set
+// to AUTO
+// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set
+// to AUTO
+#define IOC_IOCFG28_IOCURR_W 2
+#define IOC_IOCFG28_IOCURR_M 0x00000C00
+#define IOC_IOCFG28_IOCURR_S 10
+#define IOC_IOCFG28_IOCURR_4_8MA 0x00000800
+#define IOC_IOCFG28_IOCURR_4MA 0x00000400
+#define IOC_IOCFG28_IOCURR_2MA 0x00000000
+
+// Field: [9:8] IOSTR
+//
+// Select source for drive strength control of this IO.
+// This setting controls the drive strength of the Low-Current (LC) mode.
+// Higher drive strength can be selected in IOCURR
+// ENUMs:
+// MAX Maximum drive strength, controlled by
+// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default
+// values)
+// MED Medium drive strength, controlled by
+// AON_IOC:IOSTRMED (min 2 mA @2.5V with default
+// values)
+// MIN Minimum drive strength, controlled by
+// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default
+// values)
+// AUTO Automatic drive strength, controlled by AON BATMON
+// based on battery voltage. (min 2 mA @VDDS)
+#define IOC_IOCFG28_IOSTR_W 2
+#define IOC_IOCFG28_IOSTR_M 0x00000300
+#define IOC_IOCFG28_IOSTR_S 8
+#define IOC_IOCFG28_IOSTR_MAX 0x00000300
+#define IOC_IOCFG28_IOSTR_MED 0x00000200
+#define IOC_IOCFG28_IOSTR_MIN 0x00000100
+#define IOC_IOCFG28_IOSTR_AUTO 0x00000000
+
+// Field: [7] IOEV_RTC_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert RTC event
+// 1: Input edge detection asserts RTC event
+#define IOC_IOCFG28_IOEV_RTC_EN 0x00000080
+#define IOC_IOCFG28_IOEV_RTC_EN_BITN 7
+#define IOC_IOCFG28_IOEV_RTC_EN_M 0x00000080
+#define IOC_IOCFG28_IOEV_RTC_EN_S 7
+
+// Field: [6] IOEV_MCU_WU_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert MCU_WU event
+// 1: Input edge detection asserts MCU_WU event
+#define IOC_IOCFG28_IOEV_MCU_WU_EN 0x00000040
+#define IOC_IOCFG28_IOEV_MCU_WU_EN_BITN 6
+#define IOC_IOCFG28_IOEV_MCU_WU_EN_M 0x00000040
+#define IOC_IOCFG28_IOEV_MCU_WU_EN_S 6
+
+// Field: [5:0] PORT_ID
+//
+// Selects usage for DIO28
+// ENUMs:
+// RFC_SMI_CL_IN RF Core SMI Command Link In
+// RFC_SMI_CL_OUT RF Core SMI Command Link Out
+// RFC_SMI_DL_IN RF Core SMI Data Link In
+// RFC_SMI_DL_OUT RF Core SMI Data Link Out
+// RFC_GPI1 RF Core Data In 1
+// RFC_GPI0 RF Core Data In 0
+// RFC_GPO3 RF Core Data Out 3
+// RFC_GPO2 RF Core Data Out 2
+// RFC_GPO1 RF Core Data Out 1
+// RFC_GPO0 RF Core Data Out 0
+// RFC_TRC RF Core Trace
+// I2S_MCLK I2S MCLK
+// I2S_BCLK I2S BCLK
+// I2S_WCLK I2S WCLK
+// I2S_AD1 I2S Data 1
+// I2S_AD0 I2S Data 0
+// SSI1_CLK SSI1 CLK
+// SSI1_FSS SSI1 FSS
+// SSI1_TX SSI1 TX
+// SSI1_RX SSI1 RX
+// CPU_SWV CPU SWV
+// PORT_EVENT7 PORT EVENT 7
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT6 PORT EVENT 6
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT5 PORT EVENT 5
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT4 PORT EVENT 4
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT3 PORT EVENT 3
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT2 PORT EVENT 2
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT1 PORT EVENT 1
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT0 PORT EVENT 0
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// UART1_RTS UART1 RTS
+// UART1_CTS UART1 CTS
+// UART1_TX UART1 TX
+// UART1_RX UART1 RX
+// UART0_RTS UART0 RTS
+// UART0_CTS UART0 CTS
+// UART0_TX UART0 TX
+// UART0_RX UART0 RX
+// I2C_MSSCL I2C Clock
+// I2C_MSSDA I2C Data
+// SSI0_CLK SSI0 CLK
+// SSI0_FSS SSI0 FSS
+// SSI0_TX SSI0 TX
+// SSI0_RX SSI0 RX
+// AUX_IO AUX IO
+// AON_CLK32K AON 32 KHz clock (SCLK_LF)
+// GPIO General Purpose IO
+#define IOC_IOCFG28_PORT_ID_W 6
+#define IOC_IOCFG28_PORT_ID_M 0x0000003F
+#define IOC_IOCFG28_PORT_ID_S 0
+#define IOC_IOCFG28_PORT_ID_RFC_SMI_CL_IN 0x00000038
+#define IOC_IOCFG28_PORT_ID_RFC_SMI_CL_OUT 0x00000037
+#define IOC_IOCFG28_PORT_ID_RFC_SMI_DL_IN 0x00000036
+#define IOC_IOCFG28_PORT_ID_RFC_SMI_DL_OUT 0x00000035
+#define IOC_IOCFG28_PORT_ID_RFC_GPI1 0x00000034
+#define IOC_IOCFG28_PORT_ID_RFC_GPI0 0x00000033
+#define IOC_IOCFG28_PORT_ID_RFC_GPO3 0x00000032
+#define IOC_IOCFG28_PORT_ID_RFC_GPO2 0x00000031
+#define IOC_IOCFG28_PORT_ID_RFC_GPO1 0x00000030
+#define IOC_IOCFG28_PORT_ID_RFC_GPO0 0x0000002F
+#define IOC_IOCFG28_PORT_ID_RFC_TRC 0x0000002E
+#define IOC_IOCFG28_PORT_ID_I2S_MCLK 0x00000029
+#define IOC_IOCFG28_PORT_ID_I2S_BCLK 0x00000028
+#define IOC_IOCFG28_PORT_ID_I2S_WCLK 0x00000027
+#define IOC_IOCFG28_PORT_ID_I2S_AD1 0x00000026
+#define IOC_IOCFG28_PORT_ID_I2S_AD0 0x00000025
+#define IOC_IOCFG28_PORT_ID_SSI1_CLK 0x00000024
+#define IOC_IOCFG28_PORT_ID_SSI1_FSS 0x00000023
+#define IOC_IOCFG28_PORT_ID_SSI1_TX 0x00000022
+#define IOC_IOCFG28_PORT_ID_SSI1_RX 0x00000021
+#define IOC_IOCFG28_PORT_ID_CPU_SWV 0x00000020
+#define IOC_IOCFG28_PORT_ID_PORT_EVENT7 0x0000001E
+#define IOC_IOCFG28_PORT_ID_PORT_EVENT6 0x0000001D
+#define IOC_IOCFG28_PORT_ID_PORT_EVENT5 0x0000001C
+#define IOC_IOCFG28_PORT_ID_PORT_EVENT4 0x0000001B
+#define IOC_IOCFG28_PORT_ID_PORT_EVENT3 0x0000001A
+#define IOC_IOCFG28_PORT_ID_PORT_EVENT2 0x00000019
+#define IOC_IOCFG28_PORT_ID_PORT_EVENT1 0x00000018
+#define IOC_IOCFG28_PORT_ID_PORT_EVENT0 0x00000017
+#define IOC_IOCFG28_PORT_ID_UART1_RTS 0x00000016
+#define IOC_IOCFG28_PORT_ID_UART1_CTS 0x00000015
+#define IOC_IOCFG28_PORT_ID_UART1_TX 0x00000014
+#define IOC_IOCFG28_PORT_ID_UART1_RX 0x00000013
+#define IOC_IOCFG28_PORT_ID_UART0_RTS 0x00000012
+#define IOC_IOCFG28_PORT_ID_UART0_CTS 0x00000011
+#define IOC_IOCFG28_PORT_ID_UART0_TX 0x00000010
+#define IOC_IOCFG28_PORT_ID_UART0_RX 0x0000000F
+#define IOC_IOCFG28_PORT_ID_I2C_MSSCL 0x0000000E
+#define IOC_IOCFG28_PORT_ID_I2C_MSSDA 0x0000000D
+#define IOC_IOCFG28_PORT_ID_SSI0_CLK 0x0000000C
+#define IOC_IOCFG28_PORT_ID_SSI0_FSS 0x0000000B
+#define IOC_IOCFG28_PORT_ID_SSI0_TX 0x0000000A
+#define IOC_IOCFG28_PORT_ID_SSI0_RX 0x00000009
+#define IOC_IOCFG28_PORT_ID_AUX_IO 0x00000008
+#define IOC_IOCFG28_PORT_ID_AON_CLK32K 0x00000007
+#define IOC_IOCFG28_PORT_ID_GPIO 0x00000000
+
+//*****************************************************************************
+//
+// Register: IOC_O_IOCFG29
+//
+//*****************************************************************************
+// Field: [30] HYST_EN
+//
+// 0: Input hysteresis disable
+// 1: Input hysteresis enable
+#define IOC_IOCFG29_HYST_EN 0x40000000
+#define IOC_IOCFG29_HYST_EN_BITN 30
+#define IOC_IOCFG29_HYST_EN_M 0x40000000
+#define IOC_IOCFG29_HYST_EN_S 30
+
+// Field: [29] IE
+//
+// 0: Input disabled
+// 1: Input enabled
+//
+// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be
+// ignored.
+#define IOC_IOCFG29_IE 0x20000000
+#define IOC_IOCFG29_IE_BITN 29
+#define IOC_IOCFG29_IE_M 0x20000000
+#define IOC_IOCFG29_IE_S 29
+
+// Field: [28:27] WU_CFG
+//
+// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or
+// >0x08:
+//
+// 00: No wake-up
+// 01: No wake-up
+// 10: Wakes up from shutdown if this pad is going low.
+// 11: Wakes up from shutdown if this pad is going high.
+//
+// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08,
+// this register only sets wakeup enable or not.
+//
+// 00, 01: Wakeup disabled
+// 10, 11: Wakeup enabled
+//
+// Polarity is controlled from AON registers.
+//
+// Note:When the MSB is set, the IOC will deactivate the output enable for the
+// DIO.
+#define IOC_IOCFG29_WU_CFG_W 2
+#define IOC_IOCFG29_WU_CFG_M 0x18000000
+#define IOC_IOCFG29_WU_CFG_S 27
+
+// Field: [26:24] IOMODE
+//
+// IO Mode
+// Not applicable for IO configured for AON periph. signals and AUX PORT_ID
+// 0x01-0x08
+// AUX has its own open_source/drain configuration.
+//
+// 0x2: Reserved. Undefined behavior.
+// 0x3: Reserved. Undefined behavior.
+// ENUMs:
+// OPENSRC_INV Open Source
+// Inverted input / output
+// OPENSRC Open Source
+// Normal input / output
+// OPENDR_INV Open Drain
+// Inverted input / output
+// OPENDR Open Drain,
+// Normal input / output
+// INV Inverted input / ouput
+// NORMAL Normal input / output
+#define IOC_IOCFG29_IOMODE_W 3
+#define IOC_IOCFG29_IOMODE_M 0x07000000
+#define IOC_IOCFG29_IOMODE_S 24
+#define IOC_IOCFG29_IOMODE_OPENSRC_INV 0x07000000
+#define IOC_IOCFG29_IOMODE_OPENSRC 0x06000000
+#define IOC_IOCFG29_IOMODE_OPENDR_INV 0x05000000
+#define IOC_IOCFG29_IOMODE_OPENDR 0x04000000
+#define IOC_IOCFG29_IOMODE_INV 0x01000000
+#define IOC_IOCFG29_IOMODE_NORMAL 0x00000000
+
+// Field: [23] IOEV_AON_PROG2_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG2 event
+// 1: Input edge detection asserts AON_PROG2 event
+#define IOC_IOCFG29_IOEV_AON_PROG2_EN 0x00800000
+#define IOC_IOCFG29_IOEV_AON_PROG2_EN_BITN 23
+#define IOC_IOCFG29_IOEV_AON_PROG2_EN_M 0x00800000
+#define IOC_IOCFG29_IOEV_AON_PROG2_EN_S 23
+
+// Field: [22] IOEV_AON_PROG1_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG1 event
+// 1: Input edge detection asserts AON_PROG1 event
+#define IOC_IOCFG29_IOEV_AON_PROG1_EN 0x00400000
+#define IOC_IOCFG29_IOEV_AON_PROG1_EN_BITN 22
+#define IOC_IOCFG29_IOEV_AON_PROG1_EN_M 0x00400000
+#define IOC_IOCFG29_IOEV_AON_PROG1_EN_S 22
+
+// Field: [21] IOEV_AON_PROG0_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG0 event
+// 1: Input edge detection asserts AON_PROG0 event
+#define IOC_IOCFG29_IOEV_AON_PROG0_EN 0x00200000
+#define IOC_IOCFG29_IOEV_AON_PROG0_EN_BITN 21
+#define IOC_IOCFG29_IOEV_AON_PROG0_EN_M 0x00200000
+#define IOC_IOCFG29_IOEV_AON_PROG0_EN_S 21
+
+// Field: [18] EDGE_IRQ_EN
+//
+// 0: No interrupt generation
+// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is
+// enabled)
+#define IOC_IOCFG29_EDGE_IRQ_EN 0x00040000
+#define IOC_IOCFG29_EDGE_IRQ_EN_BITN 18
+#define IOC_IOCFG29_EDGE_IRQ_EN_M 0x00040000
+#define IOC_IOCFG29_EDGE_IRQ_EN_S 18
+
+// Field: [17:16] EDGE_DET
+//
+// Enable generation of edge detection events on this IO
+// ENUMs:
+// BOTH Positive and negative edge detection
+// POS Positive edge detection
+// NEG Negative edge detection
+// NONE No edge detection
+#define IOC_IOCFG29_EDGE_DET_W 2
+#define IOC_IOCFG29_EDGE_DET_M 0x00030000
+#define IOC_IOCFG29_EDGE_DET_S 16
+#define IOC_IOCFG29_EDGE_DET_BOTH 0x00030000
+#define IOC_IOCFG29_EDGE_DET_POS 0x00020000
+#define IOC_IOCFG29_EDGE_DET_NEG 0x00010000
+#define IOC_IOCFG29_EDGE_DET_NONE 0x00000000
+
+// Field: [14:13] PULL_CTL
+//
+// Pull control
+// ENUMs:
+// DIS No pull
+// UP Pull up
+// DWN Pull down
+#define IOC_IOCFG29_PULL_CTL_W 2
+#define IOC_IOCFG29_PULL_CTL_M 0x00006000
+#define IOC_IOCFG29_PULL_CTL_S 13
+#define IOC_IOCFG29_PULL_CTL_DIS 0x00006000
+#define IOC_IOCFG29_PULL_CTL_UP 0x00004000
+#define IOC_IOCFG29_PULL_CTL_DWN 0x00002000
+
+// Field: [12] SLEW_RED
+//
+// 0: Normal slew rate
+// 1: Enables reduced slew rate in output driver.
+#define IOC_IOCFG29_SLEW_RED 0x00001000
+#define IOC_IOCFG29_SLEW_RED_BITN 12
+#define IOC_IOCFG29_SLEW_RED_M 0x00001000
+#define IOC_IOCFG29_SLEW_RED_S 12
+
+// Field: [11:10] IOCURR
+//
+// Selects IO current mode of this IO.
+// ENUMs:
+// 4_8MA Extended-Current (EC) mode: Min 8 mA for double
+// drive strength IOs (min 4 mA for normal IOs)
+// when IOSTR is set to AUTO
+// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set
+// to AUTO
+// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set
+// to AUTO
+#define IOC_IOCFG29_IOCURR_W 2
+#define IOC_IOCFG29_IOCURR_M 0x00000C00
+#define IOC_IOCFG29_IOCURR_S 10
+#define IOC_IOCFG29_IOCURR_4_8MA 0x00000800
+#define IOC_IOCFG29_IOCURR_4MA 0x00000400
+#define IOC_IOCFG29_IOCURR_2MA 0x00000000
+
+// Field: [9:8] IOSTR
+//
+// Select source for drive strength control of this IO.
+// This setting controls the drive strength of the Low-Current (LC) mode.
+// Higher drive strength can be selected in IOCURR
+// ENUMs:
+// MAX Maximum drive strength, controlled by
+// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default
+// values)
+// MED Medium drive strength, controlled by
+// AON_IOC:IOSTRMED (min 2 mA @2.5V with default
+// values)
+// MIN Minimum drive strength, controlled by
+// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default
+// values)
+// AUTO Automatic drive strength, controlled by AON BATMON
+// based on battery voltage. (min 2 mA @VDDS)
+#define IOC_IOCFG29_IOSTR_W 2
+#define IOC_IOCFG29_IOSTR_M 0x00000300
+#define IOC_IOCFG29_IOSTR_S 8
+#define IOC_IOCFG29_IOSTR_MAX 0x00000300
+#define IOC_IOCFG29_IOSTR_MED 0x00000200
+#define IOC_IOCFG29_IOSTR_MIN 0x00000100
+#define IOC_IOCFG29_IOSTR_AUTO 0x00000000
+
+// Field: [7] IOEV_RTC_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert RTC event
+// 1: Input edge detection asserts RTC event
+#define IOC_IOCFG29_IOEV_RTC_EN 0x00000080
+#define IOC_IOCFG29_IOEV_RTC_EN_BITN 7
+#define IOC_IOCFG29_IOEV_RTC_EN_M 0x00000080
+#define IOC_IOCFG29_IOEV_RTC_EN_S 7
+
+// Field: [6] IOEV_MCU_WU_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert MCU_WU event
+// 1: Input edge detection asserts MCU_WU event
+#define IOC_IOCFG29_IOEV_MCU_WU_EN 0x00000040
+#define IOC_IOCFG29_IOEV_MCU_WU_EN_BITN 6
+#define IOC_IOCFG29_IOEV_MCU_WU_EN_M 0x00000040
+#define IOC_IOCFG29_IOEV_MCU_WU_EN_S 6
+
+// Field: [5:0] PORT_ID
+//
+// Selects usage for DIO29
+// ENUMs:
+// RFC_SMI_CL_IN RF Core SMI Command Link In
+// RFC_SMI_CL_OUT RF Core SMI Command Link Out
+// RFC_SMI_DL_IN RF Core SMI Data Link In
+// RFC_SMI_DL_OUT RF Core SMI Data Link Out
+// RFC_GPI1 RF Core Data In 1
+// RFC_GPI0 RF Core Data In 0
+// RFC_GPO3 RF Core Data Out 3
+// RFC_GPO2 RF Core Data Out 2
+// RFC_GPO1 RF Core Data Out 1
+// RFC_GPO0 RF Core Data Out 0
+// RFC_TRC RF Core Trace
+// I2S_MCLK I2S MCLK
+// I2S_BCLK I2S BCLK
+// I2S_WCLK I2S WCLK
+// I2S_AD1 I2S Data 1
+// I2S_AD0 I2S Data 0
+// SSI1_CLK SSI1 CLK
+// SSI1_FSS SSI1 FSS
+// SSI1_TX SSI1 TX
+// SSI1_RX SSI1 RX
+// CPU_SWV CPU SWV
+// PORT_EVENT7 PORT EVENT 7
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT6 PORT EVENT 6
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT5 PORT EVENT 5
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT4 PORT EVENT 4
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT3 PORT EVENT 3
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT2 PORT EVENT 2
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT1 PORT EVENT 1
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT0 PORT EVENT 0
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// UART1_RTS UART1 RTS
+// UART1_CTS UART1 CTS
+// UART1_TX UART1 TX
+// UART1_RX UART1 RX
+// UART0_RTS UART0 RTS
+// UART0_CTS UART0 CTS
+// UART0_TX UART0 TX
+// UART0_RX UART0 RX
+// I2C_MSSCL I2C Clock
+// I2C_MSSDA I2C Data
+// SSI0_CLK SSI0 CLK
+// SSI0_FSS SSI0 FSS
+// SSI0_TX SSI0 TX
+// SSI0_RX SSI0 RX
+// AUX_IO AUX IO
+// AON_CLK32K AON 32 KHz clock (SCLK_LF)
+// GPIO General Purpose IO
+#define IOC_IOCFG29_PORT_ID_W 6
+#define IOC_IOCFG29_PORT_ID_M 0x0000003F
+#define IOC_IOCFG29_PORT_ID_S 0
+#define IOC_IOCFG29_PORT_ID_RFC_SMI_CL_IN 0x00000038
+#define IOC_IOCFG29_PORT_ID_RFC_SMI_CL_OUT 0x00000037
+#define IOC_IOCFG29_PORT_ID_RFC_SMI_DL_IN 0x00000036
+#define IOC_IOCFG29_PORT_ID_RFC_SMI_DL_OUT 0x00000035
+#define IOC_IOCFG29_PORT_ID_RFC_GPI1 0x00000034
+#define IOC_IOCFG29_PORT_ID_RFC_GPI0 0x00000033
+#define IOC_IOCFG29_PORT_ID_RFC_GPO3 0x00000032
+#define IOC_IOCFG29_PORT_ID_RFC_GPO2 0x00000031
+#define IOC_IOCFG29_PORT_ID_RFC_GPO1 0x00000030
+#define IOC_IOCFG29_PORT_ID_RFC_GPO0 0x0000002F
+#define IOC_IOCFG29_PORT_ID_RFC_TRC 0x0000002E
+#define IOC_IOCFG29_PORT_ID_I2S_MCLK 0x00000029
+#define IOC_IOCFG29_PORT_ID_I2S_BCLK 0x00000028
+#define IOC_IOCFG29_PORT_ID_I2S_WCLK 0x00000027
+#define IOC_IOCFG29_PORT_ID_I2S_AD1 0x00000026
+#define IOC_IOCFG29_PORT_ID_I2S_AD0 0x00000025
+#define IOC_IOCFG29_PORT_ID_SSI1_CLK 0x00000024
+#define IOC_IOCFG29_PORT_ID_SSI1_FSS 0x00000023
+#define IOC_IOCFG29_PORT_ID_SSI1_TX 0x00000022
+#define IOC_IOCFG29_PORT_ID_SSI1_RX 0x00000021
+#define IOC_IOCFG29_PORT_ID_CPU_SWV 0x00000020
+#define IOC_IOCFG29_PORT_ID_PORT_EVENT7 0x0000001E
+#define IOC_IOCFG29_PORT_ID_PORT_EVENT6 0x0000001D
+#define IOC_IOCFG29_PORT_ID_PORT_EVENT5 0x0000001C
+#define IOC_IOCFG29_PORT_ID_PORT_EVENT4 0x0000001B
+#define IOC_IOCFG29_PORT_ID_PORT_EVENT3 0x0000001A
+#define IOC_IOCFG29_PORT_ID_PORT_EVENT2 0x00000019
+#define IOC_IOCFG29_PORT_ID_PORT_EVENT1 0x00000018
+#define IOC_IOCFG29_PORT_ID_PORT_EVENT0 0x00000017
+#define IOC_IOCFG29_PORT_ID_UART1_RTS 0x00000016
+#define IOC_IOCFG29_PORT_ID_UART1_CTS 0x00000015
+#define IOC_IOCFG29_PORT_ID_UART1_TX 0x00000014
+#define IOC_IOCFG29_PORT_ID_UART1_RX 0x00000013
+#define IOC_IOCFG29_PORT_ID_UART0_RTS 0x00000012
+#define IOC_IOCFG29_PORT_ID_UART0_CTS 0x00000011
+#define IOC_IOCFG29_PORT_ID_UART0_TX 0x00000010
+#define IOC_IOCFG29_PORT_ID_UART0_RX 0x0000000F
+#define IOC_IOCFG29_PORT_ID_I2C_MSSCL 0x0000000E
+#define IOC_IOCFG29_PORT_ID_I2C_MSSDA 0x0000000D
+#define IOC_IOCFG29_PORT_ID_SSI0_CLK 0x0000000C
+#define IOC_IOCFG29_PORT_ID_SSI0_FSS 0x0000000B
+#define IOC_IOCFG29_PORT_ID_SSI0_TX 0x0000000A
+#define IOC_IOCFG29_PORT_ID_SSI0_RX 0x00000009
+#define IOC_IOCFG29_PORT_ID_AUX_IO 0x00000008
+#define IOC_IOCFG29_PORT_ID_AON_CLK32K 0x00000007
+#define IOC_IOCFG29_PORT_ID_GPIO 0x00000000
+
+//*****************************************************************************
+//
+// Register: IOC_O_IOCFG30
+//
+//*****************************************************************************
+// Field: [30] HYST_EN
+//
+// 0: Input hysteresis disable
+// 1: Input hysteresis enable
+#define IOC_IOCFG30_HYST_EN 0x40000000
+#define IOC_IOCFG30_HYST_EN_BITN 30
+#define IOC_IOCFG30_HYST_EN_M 0x40000000
+#define IOC_IOCFG30_HYST_EN_S 30
+
+// Field: [29] IE
+//
+// 0: Input disabled
+// 1: Input enabled
+//
+// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be
+// ignored.
+#define IOC_IOCFG30_IE 0x20000000
+#define IOC_IOCFG30_IE_BITN 29
+#define IOC_IOCFG30_IE_M 0x20000000
+#define IOC_IOCFG30_IE_S 29
+
+// Field: [28:27] WU_CFG
+//
+// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or
+// >0x08:
+//
+// 00: No wake-up
+// 01: No wake-up
+// 10: Wakes up from shutdown if this pad is going low.
+// 11: Wakes up from shutdown if this pad is going high.
+//
+// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08,
+// this register only sets wakeup enable or not.
+//
+// 00, 01: Wakeup disabled
+// 10, 11: Wakeup enabled
+//
+// Polarity is controlled from AON registers.
+//
+// Note:When the MSB is set, the IOC will deactivate the output enable for the
+// DIO.
+#define IOC_IOCFG30_WU_CFG_W 2
+#define IOC_IOCFG30_WU_CFG_M 0x18000000
+#define IOC_IOCFG30_WU_CFG_S 27
+
+// Field: [26:24] IOMODE
+//
+// IO Mode
+// Not applicable for IO configured for AON periph. signals and AUX PORT_ID
+// 0x01-0x08
+// AUX has its own open_source/drain configuration.
+//
+// 0x2: Reserved. Undefined behavior.
+// 0x3: Reserved. Undefined behavior.
+// ENUMs:
+// OPENSRC_INV Open Source
+// Inverted input / output
+// OPENSRC Open Source
+// Normal input / output
+// OPENDR_INV Open Drain
+// Inverted input / output
+// OPENDR Open Drain,
+// Normal input / output
+// INV Inverted input / ouput
+// NORMAL Normal input / output
+#define IOC_IOCFG30_IOMODE_W 3
+#define IOC_IOCFG30_IOMODE_M 0x07000000
+#define IOC_IOCFG30_IOMODE_S 24
+#define IOC_IOCFG30_IOMODE_OPENSRC_INV 0x07000000
+#define IOC_IOCFG30_IOMODE_OPENSRC 0x06000000
+#define IOC_IOCFG30_IOMODE_OPENDR_INV 0x05000000
+#define IOC_IOCFG30_IOMODE_OPENDR 0x04000000
+#define IOC_IOCFG30_IOMODE_INV 0x01000000
+#define IOC_IOCFG30_IOMODE_NORMAL 0x00000000
+
+// Field: [23] IOEV_AON_PROG2_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG2 event
+// 1: Input edge detection asserts AON_PROG2 event
+#define IOC_IOCFG30_IOEV_AON_PROG2_EN 0x00800000
+#define IOC_IOCFG30_IOEV_AON_PROG2_EN_BITN 23
+#define IOC_IOCFG30_IOEV_AON_PROG2_EN_M 0x00800000
+#define IOC_IOCFG30_IOEV_AON_PROG2_EN_S 23
+
+// Field: [22] IOEV_AON_PROG1_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG1 event
+// 1: Input edge detection asserts AON_PROG1 event
+#define IOC_IOCFG30_IOEV_AON_PROG1_EN 0x00400000
+#define IOC_IOCFG30_IOEV_AON_PROG1_EN_BITN 22
+#define IOC_IOCFG30_IOEV_AON_PROG1_EN_M 0x00400000
+#define IOC_IOCFG30_IOEV_AON_PROG1_EN_S 22
+
+// Field: [21] IOEV_AON_PROG0_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG0 event
+// 1: Input edge detection asserts AON_PROG0 event
+#define IOC_IOCFG30_IOEV_AON_PROG0_EN 0x00200000
+#define IOC_IOCFG30_IOEV_AON_PROG0_EN_BITN 21
+#define IOC_IOCFG30_IOEV_AON_PROG0_EN_M 0x00200000
+#define IOC_IOCFG30_IOEV_AON_PROG0_EN_S 21
+
+// Field: [18] EDGE_IRQ_EN
+//
+// 0: No interrupt generation
+// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is
+// enabled)
+#define IOC_IOCFG30_EDGE_IRQ_EN 0x00040000
+#define IOC_IOCFG30_EDGE_IRQ_EN_BITN 18
+#define IOC_IOCFG30_EDGE_IRQ_EN_M 0x00040000
+#define IOC_IOCFG30_EDGE_IRQ_EN_S 18
+
+// Field: [17:16] EDGE_DET
+//
+// Enable generation of edge detection events on this IO
+// ENUMs:
+// BOTH Positive and negative edge detection
+// POS Positive edge detection
+// NEG Negative edge detection
+// NONE No edge detection
+#define IOC_IOCFG30_EDGE_DET_W 2
+#define IOC_IOCFG30_EDGE_DET_M 0x00030000
+#define IOC_IOCFG30_EDGE_DET_S 16
+#define IOC_IOCFG30_EDGE_DET_BOTH 0x00030000
+#define IOC_IOCFG30_EDGE_DET_POS 0x00020000
+#define IOC_IOCFG30_EDGE_DET_NEG 0x00010000
+#define IOC_IOCFG30_EDGE_DET_NONE 0x00000000
+
+// Field: [14:13] PULL_CTL
+//
+// Pull control
+// ENUMs:
+// DIS No pull
+// UP Pull up
+// DWN Pull down
+#define IOC_IOCFG30_PULL_CTL_W 2
+#define IOC_IOCFG30_PULL_CTL_M 0x00006000
+#define IOC_IOCFG30_PULL_CTL_S 13
+#define IOC_IOCFG30_PULL_CTL_DIS 0x00006000
+#define IOC_IOCFG30_PULL_CTL_UP 0x00004000
+#define IOC_IOCFG30_PULL_CTL_DWN 0x00002000
+
+// Field: [12] SLEW_RED
+//
+// 0: Normal slew rate
+// 1: Enables reduced slew rate in output driver.
+#define IOC_IOCFG30_SLEW_RED 0x00001000
+#define IOC_IOCFG30_SLEW_RED_BITN 12
+#define IOC_IOCFG30_SLEW_RED_M 0x00001000
+#define IOC_IOCFG30_SLEW_RED_S 12
+
+// Field: [11:10] IOCURR
+//
+// Selects IO current mode of this IO.
+// ENUMs:
+// 4_8MA Extended-Current (EC) mode: Min 8 mA for double
+// drive strength IOs (min 4 mA for normal IOs)
+// when IOSTR is set to AUTO
+// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set
+// to AUTO
+// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set
+// to AUTO
+#define IOC_IOCFG30_IOCURR_W 2
+#define IOC_IOCFG30_IOCURR_M 0x00000C00
+#define IOC_IOCFG30_IOCURR_S 10
+#define IOC_IOCFG30_IOCURR_4_8MA 0x00000800
+#define IOC_IOCFG30_IOCURR_4MA 0x00000400
+#define IOC_IOCFG30_IOCURR_2MA 0x00000000
+
+// Field: [9:8] IOSTR
+//
+// Select source for drive strength control of this IO.
+// This setting controls the drive strength of the Low-Current (LC) mode.
+// Higher drive strength can be selected in IOCURR
+// ENUMs:
+// MAX Maximum drive strength, controlled by
+// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default
+// values)
+// MED Medium drive strength, controlled by
+// AON_IOC:IOSTRMED (min 2 mA @2.5V with default
+// values)
+// MIN Minimum drive strength, controlled by
+// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default
+// values)
+// AUTO Automatic drive strength, controlled by AON BATMON
+// based on battery voltage. (min 2 mA @VDDS)
+#define IOC_IOCFG30_IOSTR_W 2
+#define IOC_IOCFG30_IOSTR_M 0x00000300
+#define IOC_IOCFG30_IOSTR_S 8
+#define IOC_IOCFG30_IOSTR_MAX 0x00000300
+#define IOC_IOCFG30_IOSTR_MED 0x00000200
+#define IOC_IOCFG30_IOSTR_MIN 0x00000100
+#define IOC_IOCFG30_IOSTR_AUTO 0x00000000
+
+// Field: [7] IOEV_RTC_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert RTC event
+// 1: Input edge detection asserts RTC event
+#define IOC_IOCFG30_IOEV_RTC_EN 0x00000080
+#define IOC_IOCFG30_IOEV_RTC_EN_BITN 7
+#define IOC_IOCFG30_IOEV_RTC_EN_M 0x00000080
+#define IOC_IOCFG30_IOEV_RTC_EN_S 7
+
+// Field: [6] IOEV_MCU_WU_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert MCU_WU event
+// 1: Input edge detection asserts MCU_WU event
+#define IOC_IOCFG30_IOEV_MCU_WU_EN 0x00000040
+#define IOC_IOCFG30_IOEV_MCU_WU_EN_BITN 6
+#define IOC_IOCFG30_IOEV_MCU_WU_EN_M 0x00000040
+#define IOC_IOCFG30_IOEV_MCU_WU_EN_S 6
+
+// Field: [5:0] PORT_ID
+//
+// Selects usage for DIO30
+// ENUMs:
+// RFC_SMI_CL_IN RF Core SMI Command Link In
+// RFC_SMI_CL_OUT RF Core SMI Command Link Out
+// RFC_SMI_DL_IN RF Core SMI Data Link In
+// RFC_SMI_DL_OUT RF Core SMI Data Link Out
+// RFC_GPI1 RF Core Data In 1
+// RFC_GPI0 RF Core Data In 0
+// RFC_GPO3 RF Core Data Out 3
+// RFC_GPO2 RF Core Data Out 2
+// RFC_GPO1 RF Core Data Out 1
+// RFC_GPO0 RF Core Data Out 0
+// RFC_TRC RF Core Trace
+// I2S_MCLK I2S MCLK
+// I2S_BCLK I2S BCLK
+// I2S_WCLK I2S WCLK
+// I2S_AD1 I2S Data 1
+// I2S_AD0 I2S Data 0
+// SSI1_CLK SSI1 CLK
+// SSI1_FSS SSI1 FSS
+// SSI1_TX SSI1 TX
+// SSI1_RX SSI1 RX
+// CPU_SWV CPU SWV
+// PORT_EVENT7 PORT EVENT 7
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT6 PORT EVENT 6
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT5 PORT EVENT 5
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT4 PORT EVENT 4
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT3 PORT EVENT 3
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT2 PORT EVENT 2
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT1 PORT EVENT 1
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT0 PORT EVENT 0
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// UART1_RTS UART1 RTS
+// UART1_CTS UART1 CTS
+// UART1_TX UART1 TX
+// UART1_RX UART1 RX
+// UART0_RTS UART0 RTS
+// UART0_CTS UART0 CTS
+// UART0_TX UART0 TX
+// UART0_RX UART0 RX
+// I2C_MSSCL I2C Clock
+// I2C_MSSDA I2C Data
+// SSI0_CLK SSI0 CLK
+// SSI0_FSS SSI0 FSS
+// SSI0_TX SSI0 TX
+// SSI0_RX SSI0 RX
+// AUX_IO AUX IO
+// AON_CLK32K AON 32 KHz clock (SCLK_LF)
+// GPIO General Purpose IO
+#define IOC_IOCFG30_PORT_ID_W 6
+#define IOC_IOCFG30_PORT_ID_M 0x0000003F
+#define IOC_IOCFG30_PORT_ID_S 0
+#define IOC_IOCFG30_PORT_ID_RFC_SMI_CL_IN 0x00000038
+#define IOC_IOCFG30_PORT_ID_RFC_SMI_CL_OUT 0x00000037
+#define IOC_IOCFG30_PORT_ID_RFC_SMI_DL_IN 0x00000036
+#define IOC_IOCFG30_PORT_ID_RFC_SMI_DL_OUT 0x00000035
+#define IOC_IOCFG30_PORT_ID_RFC_GPI1 0x00000034
+#define IOC_IOCFG30_PORT_ID_RFC_GPI0 0x00000033
+#define IOC_IOCFG30_PORT_ID_RFC_GPO3 0x00000032
+#define IOC_IOCFG30_PORT_ID_RFC_GPO2 0x00000031
+#define IOC_IOCFG30_PORT_ID_RFC_GPO1 0x00000030
+#define IOC_IOCFG30_PORT_ID_RFC_GPO0 0x0000002F
+#define IOC_IOCFG30_PORT_ID_RFC_TRC 0x0000002E
+#define IOC_IOCFG30_PORT_ID_I2S_MCLK 0x00000029
+#define IOC_IOCFG30_PORT_ID_I2S_BCLK 0x00000028
+#define IOC_IOCFG30_PORT_ID_I2S_WCLK 0x00000027
+#define IOC_IOCFG30_PORT_ID_I2S_AD1 0x00000026
+#define IOC_IOCFG30_PORT_ID_I2S_AD0 0x00000025
+#define IOC_IOCFG30_PORT_ID_SSI1_CLK 0x00000024
+#define IOC_IOCFG30_PORT_ID_SSI1_FSS 0x00000023
+#define IOC_IOCFG30_PORT_ID_SSI1_TX 0x00000022
+#define IOC_IOCFG30_PORT_ID_SSI1_RX 0x00000021
+#define IOC_IOCFG30_PORT_ID_CPU_SWV 0x00000020
+#define IOC_IOCFG30_PORT_ID_PORT_EVENT7 0x0000001E
+#define IOC_IOCFG30_PORT_ID_PORT_EVENT6 0x0000001D
+#define IOC_IOCFG30_PORT_ID_PORT_EVENT5 0x0000001C
+#define IOC_IOCFG30_PORT_ID_PORT_EVENT4 0x0000001B
+#define IOC_IOCFG30_PORT_ID_PORT_EVENT3 0x0000001A
+#define IOC_IOCFG30_PORT_ID_PORT_EVENT2 0x00000019
+#define IOC_IOCFG30_PORT_ID_PORT_EVENT1 0x00000018
+#define IOC_IOCFG30_PORT_ID_PORT_EVENT0 0x00000017
+#define IOC_IOCFG30_PORT_ID_UART1_RTS 0x00000016
+#define IOC_IOCFG30_PORT_ID_UART1_CTS 0x00000015
+#define IOC_IOCFG30_PORT_ID_UART1_TX 0x00000014
+#define IOC_IOCFG30_PORT_ID_UART1_RX 0x00000013
+#define IOC_IOCFG30_PORT_ID_UART0_RTS 0x00000012
+#define IOC_IOCFG30_PORT_ID_UART0_CTS 0x00000011
+#define IOC_IOCFG30_PORT_ID_UART0_TX 0x00000010
+#define IOC_IOCFG30_PORT_ID_UART0_RX 0x0000000F
+#define IOC_IOCFG30_PORT_ID_I2C_MSSCL 0x0000000E
+#define IOC_IOCFG30_PORT_ID_I2C_MSSDA 0x0000000D
+#define IOC_IOCFG30_PORT_ID_SSI0_CLK 0x0000000C
+#define IOC_IOCFG30_PORT_ID_SSI0_FSS 0x0000000B
+#define IOC_IOCFG30_PORT_ID_SSI0_TX 0x0000000A
+#define IOC_IOCFG30_PORT_ID_SSI0_RX 0x00000009
+#define IOC_IOCFG30_PORT_ID_AUX_IO 0x00000008
+#define IOC_IOCFG30_PORT_ID_AON_CLK32K 0x00000007
+#define IOC_IOCFG30_PORT_ID_GPIO 0x00000000
+
+//*****************************************************************************
+//
+// Register: IOC_O_IOCFG31
+//
+//*****************************************************************************
+// Field: [30] HYST_EN
+//
+// 0: Input hysteresis disable
+// 1: Input hysteresis enable
+#define IOC_IOCFG31_HYST_EN 0x40000000
+#define IOC_IOCFG31_HYST_EN_BITN 30
+#define IOC_IOCFG31_HYST_EN_M 0x40000000
+#define IOC_IOCFG31_HYST_EN_S 30
+
+// Field: [29] IE
+//
+// 0: Input disabled
+// 1: Input enabled
+//
+// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be
+// ignored.
+#define IOC_IOCFG31_IE 0x20000000
+#define IOC_IOCFG31_IE_BITN 29
+#define IOC_IOCFG31_IE_M 0x20000000
+#define IOC_IOCFG31_IE_S 29
+
+// Field: [28:27] WU_CFG
+//
+// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or
+// >0x08:
+//
+// 00: No wake-up
+// 01: No wake-up
+// 10: Wakes up from shutdown if this pad is going low.
+// 11: Wakes up from shutdown if this pad is going high.
+//
+// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08,
+// this register only sets wakeup enable or not.
+//
+// 00, 01: Wakeup disabled
+// 10, 11: Wakeup enabled
+//
+// Polarity is controlled from AON registers.
+//
+// Note:When the MSB is set, the IOC will deactivate the output enable for the
+// DIO.
+#define IOC_IOCFG31_WU_CFG_W 2
+#define IOC_IOCFG31_WU_CFG_M 0x18000000
+#define IOC_IOCFG31_WU_CFG_S 27
+
+// Field: [26:24] IOMODE
+//
+// IO Mode
+// Not applicable for IO configured for AON periph. signals and AUX PORT_ID
+// 0x01-0x08
+// AUX has its own open_source/drain configuration.
+//
+// 0x2: Reserved. Undefined behavior.
+// 0x3: Reserved. Undefined behavior.
+// ENUMs:
+// OPENSRC_INV Open Source
+// Inverted input / output
+// OPENSRC Open Source
+// Normal input / output
+// OPENDR_INV Open Drain
+// Inverted input / output
+// OPENDR Open Drain,
+// Normal input / output
+// INV Inverted input / ouput
+// NORMAL Normal input / output
+#define IOC_IOCFG31_IOMODE_W 3
+#define IOC_IOCFG31_IOMODE_M 0x07000000
+#define IOC_IOCFG31_IOMODE_S 24
+#define IOC_IOCFG31_IOMODE_OPENSRC_INV 0x07000000
+#define IOC_IOCFG31_IOMODE_OPENSRC 0x06000000
+#define IOC_IOCFG31_IOMODE_OPENDR_INV 0x05000000
+#define IOC_IOCFG31_IOMODE_OPENDR 0x04000000
+#define IOC_IOCFG31_IOMODE_INV 0x01000000
+#define IOC_IOCFG31_IOMODE_NORMAL 0x00000000
+
+// Field: [23] IOEV_AON_PROG2_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG2 event
+// 1: Input edge detection asserts AON_PROG2 event
+#define IOC_IOCFG31_IOEV_AON_PROG2_EN 0x00800000
+#define IOC_IOCFG31_IOEV_AON_PROG2_EN_BITN 23
+#define IOC_IOCFG31_IOEV_AON_PROG2_EN_M 0x00800000
+#define IOC_IOCFG31_IOEV_AON_PROG2_EN_S 23
+
+// Field: [22] IOEV_AON_PROG1_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG1 event
+// 1: Input edge detection asserts AON_PROG1 event
+#define IOC_IOCFG31_IOEV_AON_PROG1_EN 0x00400000
+#define IOC_IOCFG31_IOEV_AON_PROG1_EN_BITN 22
+#define IOC_IOCFG31_IOEV_AON_PROG1_EN_M 0x00400000
+#define IOC_IOCFG31_IOEV_AON_PROG1_EN_S 22
+
+// Field: [21] IOEV_AON_PROG0_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert AON_PROG0 event
+// 1: Input edge detection asserts AON_PROG0 event
+#define IOC_IOCFG31_IOEV_AON_PROG0_EN 0x00200000
+#define IOC_IOCFG31_IOEV_AON_PROG0_EN_BITN 21
+#define IOC_IOCFG31_IOEV_AON_PROG0_EN_M 0x00200000
+#define IOC_IOCFG31_IOEV_AON_PROG0_EN_S 21
+
+// Field: [18] EDGE_IRQ_EN
+//
+// 0: No interrupt generation
+// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is
+// enabled)
+#define IOC_IOCFG31_EDGE_IRQ_EN 0x00040000
+#define IOC_IOCFG31_EDGE_IRQ_EN_BITN 18
+#define IOC_IOCFG31_EDGE_IRQ_EN_M 0x00040000
+#define IOC_IOCFG31_EDGE_IRQ_EN_S 18
+
+// Field: [17:16] EDGE_DET
+//
+// Enable generation of edge detection events on this IO
+// ENUMs:
+// BOTH Positive and negative edge detection
+// POS Positive edge detection
+// NEG Negative edge detection
+// NONE No edge detection
+#define IOC_IOCFG31_EDGE_DET_W 2
+#define IOC_IOCFG31_EDGE_DET_M 0x00030000
+#define IOC_IOCFG31_EDGE_DET_S 16
+#define IOC_IOCFG31_EDGE_DET_BOTH 0x00030000
+#define IOC_IOCFG31_EDGE_DET_POS 0x00020000
+#define IOC_IOCFG31_EDGE_DET_NEG 0x00010000
+#define IOC_IOCFG31_EDGE_DET_NONE 0x00000000
+
+// Field: [14:13] PULL_CTL
+//
+// Pull control
+// ENUMs:
+// DIS No pull
+// UP Pull up
+// DWN Pull down
+#define IOC_IOCFG31_PULL_CTL_W 2
+#define IOC_IOCFG31_PULL_CTL_M 0x00006000
+#define IOC_IOCFG31_PULL_CTL_S 13
+#define IOC_IOCFG31_PULL_CTL_DIS 0x00006000
+#define IOC_IOCFG31_PULL_CTL_UP 0x00004000
+#define IOC_IOCFG31_PULL_CTL_DWN 0x00002000
+
+// Field: [12] SLEW_RED
+//
+// 0: Normal slew rate
+// 1: Enables reduced slew rate in output driver.
+#define IOC_IOCFG31_SLEW_RED 0x00001000
+#define IOC_IOCFG31_SLEW_RED_BITN 12
+#define IOC_IOCFG31_SLEW_RED_M 0x00001000
+#define IOC_IOCFG31_SLEW_RED_S 12
+
+// Field: [11:10] IOCURR
+//
+// Selects IO current mode of this IO.
+// ENUMs:
+// 4_8MA Extended-Current (EC) mode: Min 8 mA for double
+// drive strength IOs (min 4 mA for normal IOs)
+// when IOSTR is set to AUTO
+// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set
+// to AUTO
+// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set
+// to AUTO
+#define IOC_IOCFG31_IOCURR_W 2
+#define IOC_IOCFG31_IOCURR_M 0x00000C00
+#define IOC_IOCFG31_IOCURR_S 10
+#define IOC_IOCFG31_IOCURR_4_8MA 0x00000800
+#define IOC_IOCFG31_IOCURR_4MA 0x00000400
+#define IOC_IOCFG31_IOCURR_2MA 0x00000000
+
+// Field: [9:8] IOSTR
+//
+// Select source for drive strength control of this IO.
+// This setting controls the drive strength of the Low-Current (LC) mode.
+// Higher drive strength can be selected in IOCURR
+// ENUMs:
+// MAX Maximum drive strength, controlled by
+// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default
+// values)
+// MED Medium drive strength, controlled by
+// AON_IOC:IOSTRMED (min 2 mA @2.5V with default
+// values)
+// MIN Minimum drive strength, controlled by
+// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default
+// values)
+// AUTO Automatic drive strength, controlled by AON BATMON
+// based on battery voltage. (min 2 mA @VDDS)
+#define IOC_IOCFG31_IOSTR_W 2
+#define IOC_IOCFG31_IOSTR_M 0x00000300
+#define IOC_IOCFG31_IOSTR_S 8
+#define IOC_IOCFG31_IOSTR_MAX 0x00000300
+#define IOC_IOCFG31_IOSTR_MED 0x00000200
+#define IOC_IOCFG31_IOSTR_MIN 0x00000100
+#define IOC_IOCFG31_IOSTR_AUTO 0x00000000
+
+// Field: [7] IOEV_RTC_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert RTC event
+// 1: Input edge detection asserts RTC event
+#define IOC_IOCFG31_IOEV_RTC_EN 0x00000080
+#define IOC_IOCFG31_IOEV_RTC_EN_BITN 7
+#define IOC_IOCFG31_IOEV_RTC_EN_M 0x00000080
+#define IOC_IOCFG31_IOEV_RTC_EN_S 7
+
+// Field: [6] IOEV_MCU_WU_EN
+//
+// Event asserted by this IO when edge detection is enabled
+//
+// 0: Input edge detection does not assert MCU_WU event
+// 1: Input edge detection asserts MCU_WU event
+#define IOC_IOCFG31_IOEV_MCU_WU_EN 0x00000040
+#define IOC_IOCFG31_IOEV_MCU_WU_EN_BITN 6
+#define IOC_IOCFG31_IOEV_MCU_WU_EN_M 0x00000040
+#define IOC_IOCFG31_IOEV_MCU_WU_EN_S 6
+
+// Field: [5:0] PORT_ID
+//
+// Selects usage for DIO31
+// ENUMs:
+// RFC_SMI_CL_IN RF Core SMI Command Link In
+// RFC_SMI_CL_OUT RF Core SMI Command Link Out
+// RFC_SMI_DL_IN RF Core SMI Data Link In
+// RFC_SMI_DL_OUT RF Core SMI Data Link Out
+// RFC_GPI1 RF Core Data In 1
+// RFC_GPI0 RF Core Data In 0
+// RFC_GPO3 RF Core Data Out 3
+// RFC_GPO2 RF Core Data Out 2
+// RFC_GPO1 RF Core Data Out 1
+// RFC_GPO0 RF Core Data Out 0
+// RFC_TRC RF Core Trace
+// I2S_MCLK I2S MCLK
+// I2S_BCLK I2S BCLK
+// I2S_WCLK I2S WCLK
+// I2S_AD1 I2S Data 1
+// I2S_AD0 I2S Data 0
+// SSI1_CLK SSI1 CLK
+// SSI1_FSS SSI1 FSS
+// SSI1_TX SSI1 TX
+// SSI1_RX SSI1 RX
+// CPU_SWV CPU SWV
+// PORT_EVENT7 PORT EVENT 7
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT6 PORT EVENT 6
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT5 PORT EVENT 5
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT4 PORT EVENT 4
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT3 PORT EVENT 3
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT2 PORT EVENT 2
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT1 PORT EVENT 1
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// PORT_EVENT0 PORT EVENT 0
+// Can be used as a general
+// purpose IO event by selecting it through
+// registers in the EVENT module, for example
+// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV,
+// and so on
+// UART1_RTS UART1 RTS
+// UART1_CTS UART1 CTS
+// UART1_TX UART1 TX
+// UART1_RX UART1 RX
+// UART0_RTS UART0 RTS
+// UART0_CTS UART0 CTS
+// UART0_TX UART0 TX
+// UART0_RX UART0 RX
+// I2C_MSSCL I2C Clock
+// I2C_MSSDA I2C Data
+// SSI0_CLK SSI0 CLK
+// SSI0_FSS SSI0 FSS
+// SSI0_TX SSI0 TX
+// SSI0_RX SSI0 RX
+// AUX_IO AUX IO
+// AON_CLK32K AON 32 KHz clock (SCLK_LF)
+// GPIO General Purpose IO
+#define IOC_IOCFG31_PORT_ID_W 6
+#define IOC_IOCFG31_PORT_ID_M 0x0000003F
+#define IOC_IOCFG31_PORT_ID_S 0
+#define IOC_IOCFG31_PORT_ID_RFC_SMI_CL_IN 0x00000038
+#define IOC_IOCFG31_PORT_ID_RFC_SMI_CL_OUT 0x00000037
+#define IOC_IOCFG31_PORT_ID_RFC_SMI_DL_IN 0x00000036
+#define IOC_IOCFG31_PORT_ID_RFC_SMI_DL_OUT 0x00000035
+#define IOC_IOCFG31_PORT_ID_RFC_GPI1 0x00000034
+#define IOC_IOCFG31_PORT_ID_RFC_GPI0 0x00000033
+#define IOC_IOCFG31_PORT_ID_RFC_GPO3 0x00000032
+#define IOC_IOCFG31_PORT_ID_RFC_GPO2 0x00000031
+#define IOC_IOCFG31_PORT_ID_RFC_GPO1 0x00000030
+#define IOC_IOCFG31_PORT_ID_RFC_GPO0 0x0000002F
+#define IOC_IOCFG31_PORT_ID_RFC_TRC 0x0000002E
+#define IOC_IOCFG31_PORT_ID_I2S_MCLK 0x00000029
+#define IOC_IOCFG31_PORT_ID_I2S_BCLK 0x00000028
+#define IOC_IOCFG31_PORT_ID_I2S_WCLK 0x00000027
+#define IOC_IOCFG31_PORT_ID_I2S_AD1 0x00000026
+#define IOC_IOCFG31_PORT_ID_I2S_AD0 0x00000025
+#define IOC_IOCFG31_PORT_ID_SSI1_CLK 0x00000024
+#define IOC_IOCFG31_PORT_ID_SSI1_FSS 0x00000023
+#define IOC_IOCFG31_PORT_ID_SSI1_TX 0x00000022
+#define IOC_IOCFG31_PORT_ID_SSI1_RX 0x00000021
+#define IOC_IOCFG31_PORT_ID_CPU_SWV 0x00000020
+#define IOC_IOCFG31_PORT_ID_PORT_EVENT7 0x0000001E
+#define IOC_IOCFG31_PORT_ID_PORT_EVENT6 0x0000001D
+#define IOC_IOCFG31_PORT_ID_PORT_EVENT5 0x0000001C
+#define IOC_IOCFG31_PORT_ID_PORT_EVENT4 0x0000001B
+#define IOC_IOCFG31_PORT_ID_PORT_EVENT3 0x0000001A
+#define IOC_IOCFG31_PORT_ID_PORT_EVENT2 0x00000019
+#define IOC_IOCFG31_PORT_ID_PORT_EVENT1 0x00000018
+#define IOC_IOCFG31_PORT_ID_PORT_EVENT0 0x00000017
+#define IOC_IOCFG31_PORT_ID_UART1_RTS 0x00000016
+#define IOC_IOCFG31_PORT_ID_UART1_CTS 0x00000015
+#define IOC_IOCFG31_PORT_ID_UART1_TX 0x00000014
+#define IOC_IOCFG31_PORT_ID_UART1_RX 0x00000013
+#define IOC_IOCFG31_PORT_ID_UART0_RTS 0x00000012
+#define IOC_IOCFG31_PORT_ID_UART0_CTS 0x00000011
+#define IOC_IOCFG31_PORT_ID_UART0_TX 0x00000010
+#define IOC_IOCFG31_PORT_ID_UART0_RX 0x0000000F
+#define IOC_IOCFG31_PORT_ID_I2C_MSSCL 0x0000000E
+#define IOC_IOCFG31_PORT_ID_I2C_MSSDA 0x0000000D
+#define IOC_IOCFG31_PORT_ID_SSI0_CLK 0x0000000C
+#define IOC_IOCFG31_PORT_ID_SSI0_FSS 0x0000000B
+#define IOC_IOCFG31_PORT_ID_SSI0_TX 0x0000000A
+#define IOC_IOCFG31_PORT_ID_SSI0_RX 0x00000009
+#define IOC_IOCFG31_PORT_ID_AUX_IO 0x00000008
+#define IOC_IOCFG31_PORT_ID_AON_CLK32K 0x00000007
+#define IOC_IOCFG31_PORT_ID_GPIO 0x00000000
+
+
+#endif // __IOC__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_memmap.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_memmap.h
new file mode 100644
index 0000000..e8a9e8b
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_memmap.h
@@ -0,0 +1,180 @@
+/******************************************************************************
+* Filename: hw_memmap_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_MEMMAP_H__
+#define __HW_MEMMAP_H__
+
+//*****************************************************************************
+//
+// The following are defines for the base address of the memories and
+// peripherals on the CPU_MMAP interface
+//
+//*****************************************************************************
+#define FLASHMEM_BASE 0x00000000 // FLASHMEM
+#define BROM_BASE 0x10000000 // BROM
+#define GPRAM_BASE 0x11000000 // GPRAM
+#define SRAM_BASE 0x20000000 // SRAM
+#define RFC_RAM_BASE 0x21000000 // RFC_RAM
+#define RFC_ULLRAM_BASE 0x21004000 // RFC_ULLRAM
+#define SSI0_BASE 0x40000000 // SSI
+#define UART0_BASE 0x40001000 // UART
+#define I2C0_BASE 0x40002000 // I2C
+#define SSI1_BASE 0x40008000 // SSI
+#define UART1_BASE 0x4000B000 // UART
+#define GPT0_BASE 0x40010000 // GPT
+#define GPT1_BASE 0x40011000 // GPT
+#define GPT2_BASE 0x40012000 // GPT
+#define GPT3_BASE 0x40013000 // GPT
+#define UDMA0_BASE 0x40020000 // UDMA
+#define I2S0_BASE 0x40021000 // I2S
+#define GPIO_BASE 0x40022000 // GPIO
+#define CRYPTO_BASE 0x40024000 // CRYPTO
+#define PKA_BASE 0x40025000 // PKA
+#define PKA_RAM_BASE 0x40026000 // PKA_RAM
+#define PKA_INT_BASE 0x40027000 // PKA_INT
+#define TRNG_BASE 0x40028000 // TRNG
+#define FLASH_BASE 0x40030000 // FLASH
+#define VIMS_BASE 0x40034000 // VIMS
+#define SRAM_MMR_BASE 0x40035000 // SRAM_MMR
+#define RFC_PWR_BASE 0x40040000 // RFC_PWR
+#define RFC_DBELL_BASE 0x40041000 // RFC_DBELL
+#define RFC_RAT_BASE 0x40043000 // RFC_RAT
+#define RFC_FSCA_BASE 0x40044000 // RFC_FSCA
+#define WDT_BASE 0x40080000 // WDT
+#define IOC_BASE 0x40081000 // IOC
+#define PRCM_BASE 0x40082000 // PRCM
+#define EVENT_BASE 0x40083000 // EVENT
+#define SMPH_BASE 0x40084000 // SMPH
+#define ADI2_BASE 0x40086000 // ADI
+#define ADI3_BASE 0x40086200 // ADI
+#define AON_PMCTL_BASE 0x40090000 // AON_PMCTL
+#define AON_RTC_BASE 0x40092000 // AON_RTC
+#define AON_EVENT_BASE 0x40093000 // AON_EVENT
+#define AON_IOC_BASE 0x40094000 // AON_IOC
+#define AON_BATMON_BASE 0x40095000 // AON_BATMON
+#define AUX_SPIM_BASE 0x400C1000 // AUX_SPIM
+#define AUX_MAC_BASE 0x400C2000 // AUX_MAC
+#define AUX_TIMER2_BASE 0x400C3000 // AUX_TIMER2
+#define AUX_TDC_BASE 0x400C4000 // AUX_TDC
+#define AUX_EVCTL_BASE 0x400C5000 // AUX_EVCTL
+#define AUX_SYSIF_BASE 0x400C6000 // AUX_SYSIF
+#define AUX_TIMER01_BASE 0x400C7000 // AUX_TIMER01
+#define AUX_SMPH_BASE 0x400C8000 // AUX_SMPH
+#define AUX_ANAIF_BASE 0x400C9000 // AUX_ANAIF
+#define AUX_DDI0_OSC_BASE 0x400CA000 // DDI
+#define AUX_ADI4_BASE 0x400CB000 // ADI
+#define AUX_AIODIO0_BASE 0x400CC000 // AUX_AIODIO
+#define AUX_AIODIO1_BASE 0x400CD000 // AUX_AIODIO
+#define AUX_AIODIO2_BASE 0x400CE000 // AUX_AIODIO
+#define AUX_AIODIO3_BASE 0x400CF000 // AUX_AIODIO
+#define AUX_RAM_BASE 0x400E0000 // AUX_RAM
+#define AUX_SCE_BASE 0x400E1000 // AUX_SCE
+#define FLASH_CFG_BASE 0x50000000 // CC26_DUMMY_COMP
+#define FCFG1_BASE 0x50001000 // FCFG1
+#define FCFG2_BASE 0x50002000 // FCFG2
+#ifndef CCFG_BASE
+#define CCFG_BASE 0x50003000 // CCFG
+#endif
+#define CCFG_BASE_DEFAULT 0x50003000 // CCFG
+#define SSI0_NONBUF_BASE 0x60000000 // SSI CPU nonbuf base
+#define UART0_NONBUF_BASE 0x60001000 // UART CPU nonbuf base
+#define I2C0_NONBUF_BASE 0x60002000 // I2C CPU nonbuf base
+#define SSI1_NONBUF_BASE 0x60008000 // SSI CPU nonbuf base
+#define UART1_NONBUF_BASE 0x6000B000 // UART CPU nonbuf base
+#define GPT0_NONBUF_BASE 0x60010000 // GPT CPU nonbuf base
+#define GPT1_NONBUF_BASE 0x60011000 // GPT CPU nonbuf base
+#define GPT2_NONBUF_BASE 0x60012000 // GPT CPU nonbuf base
+#define GPT3_NONBUF_BASE 0x60013000 // GPT CPU nonbuf base
+#define UDMA0_NONBUF_BASE 0x60020000 // UDMA CPU nonbuf base
+#define I2S0_NONBUF_BASE 0x60021000 // I2S CPU nonbuf base
+#define GPIO_NONBUF_BASE 0x60022000 // GPIO CPU nonbuf base
+#define CRYPTO_NONBUF_BASE 0x60024000 // CRYPTO CPU nonbuf base
+#define PKA_NONBUF_BASE 0x60025000 // PKA CPU nonbuf base
+#define PKA_RAM_NONBUF_BASE 0x60026000 // PKA_RAM CPU nonbuf base
+#define PKA_INT_NONBUF_BASE 0x60027000 // PKA_INT CPU nonbuf base
+#define TRNG_NONBUF_BASE 0x60028000 // TRNG CPU nonbuf base
+#define FLASH_NONBUF_BASE 0x60030000 // FLASH CPU nonbuf base
+#define VIMS_NONBUF_BASE 0x60034000 // VIMS CPU nonbuf base
+#define SRAM_MMR_NONBUF_BASE 0x60035000 // SRAM_MMR CPU nonbuf base
+#define RFC_PWR_NONBUF_BASE 0x60040000 // RFC_PWR CPU nonbuf base
+#define RFC_DBELL_NONBUF_BASE 0x60041000 // RFC_DBELL CPU nonbuf base
+#define RFC_RAT_NONBUF_BASE 0x60043000 // RFC_RAT CPU nonbuf base
+#define RFC_FSCA_NONBUF_BASE 0x60044000 // RFC_FSCA CPU nonbuf base
+#define WDT_NONBUF_BASE 0x60080000 // WDT CPU nonbuf base
+#define IOC_NONBUF_BASE 0x60081000 // IOC CPU nonbuf base
+#define PRCM_NONBUF_BASE 0x60082000 // PRCM CPU nonbuf base
+#define EVENT_NONBUF_BASE 0x60083000 // EVENT CPU nonbuf base
+#define SMPH_NONBUF_BASE 0x60084000 // SMPH CPU nonbuf base
+#define ADI2_NONBUF_BASE 0x60086000 // ADI CPU nonbuf base
+#define ADI3_NONBUF_BASE 0x60086200 // ADI CPU nonbuf base
+#define AON_PMCTL_NONBUF_BASE 0x60090000 // AON_PMCTL CPU nonbuf base
+#define AON_RTC_NONBUF_BASE 0x60092000 // AON_RTC CPU nonbuf base
+#define AON_EVENT_NONBUF_BASE 0x60093000 // AON_EVENT CPU nonbuf base
+#define AON_IOC_NONBUF_BASE 0x60094000 // AON_IOC CPU nonbuf base
+#define AON_BATMON_NONBUF_BASE 0x60095000 // AON_BATMON CPU nonbuf base
+#define AUX_SPIM_NONBUF_BASE 0x600C1000 // AUX_SPIM CPU nonbuf base
+#define AUX_MAC_NONBUF_BASE 0x600C2000 // AUX_MAC CPU nonbuf base
+#define AUX_TIMER2_NONBUF_BASE 0x600C3000 // AUX_TIMER2 CPU nonbuf base
+#define AUX_TDC_NONBUF_BASE 0x600C4000 // AUX_TDC CPU nonbuf base
+#define AUX_EVCTL_NONBUF_BASE 0x600C5000 // AUX_EVCTL CPU nonbuf base
+#define AUX_SYSIF_NONBUF_BASE 0x600C6000 // AUX_SYSIF CPU nonbuf base
+#define AUX_TIMER01_NONBUF_BASE \
+ 0x600C7000 // AUX_TIMER01 CPU nonbuf base
+#define AUX_SMPH_NONBUF_BASE 0x600C8000 // AUX_SMPH CPU nonbuf base
+#define AUX_ANAIF_NONBUF_BASE 0x600C9000 // AUX_ANAIF CPU nonbuf base
+#define AUX_DDI0_OSC_NONBUF_BASE \
+ 0x600CA000 // DDI CPU nonbuf base
+#define AUX_ADI4_NONBUF_BASE 0x600CB000 // ADI CPU nonbuf base
+#define AUX_AIODIO0_NONBUF_BASE \
+ 0x600CC000 // AUX_AIODIO CPU nonbuf base
+#define AUX_AIODIO1_NONBUF_BASE \
+ 0x600CD000 // AUX_AIODIO CPU nonbuf base
+#define AUX_AIODIO2_NONBUF_BASE \
+ 0x600CE000 // AUX_AIODIO CPU nonbuf base
+#define AUX_AIODIO3_NONBUF_BASE \
+ 0x600CF000 // AUX_AIODIO CPU nonbuf base
+#define AUX_RAM_NONBUF_BASE 0x600E0000 // AUX_RAM CPU nonbuf base
+#define AUX_SCE_NONBUF_BASE 0x600E1000 // AUX_SCE CPU nonbuf base
+#define FLASHMEM_ALIAS_BASE 0xA0000000 // FLASHMEM Alias base
+#define CPU_ITM_BASE 0xE0000000 // CPU_ITM
+#define CPU_DWT_BASE 0xE0001000 // CPU_DWT
+#define CPU_FPB_BASE 0xE0002000 // CPU_FPB
+#define CPU_SCS_BASE 0xE000E000 // CPU_SCS
+#define CPU_TPIU_BASE 0xE0040000 // CPU_TPIU
+#define CPU_TIPROP_BASE 0xE00FE000 // CPU_TIPROP
+#define CPU_ROM_TABLE_BASE 0xE00FF000 // CPU_ROM_TABLE
+
+#endif // __HW_MEMMAP__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_nvic.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_nvic.h
new file mode 100644
index 0000000..15c5224
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_nvic.h
@@ -0,0 +1,1026 @@
+/******************************************************************************
+* Filename: hw_nvic.h
+* Revised: 2015-01-13 16:59:55 +0100 (Tue, 13 Jan 2015)
+* Revision: 42365
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_NVIC_H__
+#define __HW_NVIC_H__
+
+//*****************************************************************************
+//
+// The following are defines for the NVIC register addresses.
+//
+//*****************************************************************************
+#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg
+#define NVIC_ACTLR 0xE000E008 // Auxiliary Control
+#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status
+ // Register
+#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register
+#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register
+#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg
+#define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable
+#define NVIC_EN1 0xE000E104 // Interrupt 32-54 Set Enable
+#define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable
+#define NVIC_DIS1 0xE000E184 // Interrupt 32-54 Clear Enable
+#define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending
+#define NVIC_PEND1 0xE000E204 // Interrupt 32-54 Set Pending
+#define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending
+#define NVIC_UNPEND1 0xE000E284 // Interrupt 32-54 Clear Pending
+#define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit
+#define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-54 Active Bit
+#define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority
+#define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority
+#define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority
+#define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority
+#define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority
+#define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority
+#define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority
+#define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority
+#define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority
+#define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority
+#define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority
+#define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority
+#define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority
+#define NVIC_PRI13 0xE000E434 // Interrupt 52-55 Priority
+#define NVIC_CPUID 0xE000ED00 // CPU ID Base
+#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State
+#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset
+#define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset
+ // Control
+#define NVIC_SYS_CTRL 0xE000ED10 // System Control
+#define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control
+#define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1
+#define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2
+#define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3
+#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State
+#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status
+#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status
+#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register
+#define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address
+#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address
+#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type
+#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control
+#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number
+#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address
+#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size
+#define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1
+#define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size
+ // Alias 1
+#define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2
+#define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size
+ // Alias 2
+#define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3
+#define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size
+ // Alias 3
+#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg
+#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select
+#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data
+#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control
+#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_INT_TYPE register.
+//
+//*****************************************************************************
+#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32)
+#define NVIC_INT_TYPE_LINES_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTLR register.
+//
+//*****************************************************************************
+#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding
+#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer
+#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple
+ // Cycle Instructions
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag
+#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source
+#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable
+#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_RELOAD register.
+//
+//*****************************************************************************
+#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value
+#define NVIC_ST_RELOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CURRENT
+// register.
+//
+//*****************************************************************************
+#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value
+#define NVIC_ST_CURRENT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CAL register.
+//
+//*****************************************************************************
+#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock
+#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew
+#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value
+#define NVIC_ST_CAL_ONEMS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN0 register.
+//
+//*****************************************************************************
+#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable
+#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable
+#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable
+#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable
+#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable
+#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable
+#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable
+#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable
+#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable
+#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable
+#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable
+#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable
+#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable
+#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable
+#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable
+#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable
+#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable
+#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable
+#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable
+#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable
+#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable
+#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable
+#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable
+#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable
+#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable
+#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable
+#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable
+#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable
+#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable
+#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable
+#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable
+#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable
+#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN1 register.
+//
+//*****************************************************************************
+#define NVIC_EN1_INT_M 0x007FFFFF // Interrupt Enable
+#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable
+#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable
+#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable
+#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable
+#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable
+#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable
+#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable
+#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable
+#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable
+#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable
+#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable
+#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable
+#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable
+#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable
+#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable
+#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable
+#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable
+#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable
+#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable
+#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable
+#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable
+#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable
+#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS0 register.
+//
+//*****************************************************************************
+#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable
+#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable
+#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable
+#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable
+#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable
+#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable
+#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable
+#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable
+#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable
+#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable
+#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable
+#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable
+#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable
+#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable
+#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable
+#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable
+#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable
+#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable
+#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable
+#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable
+#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable
+#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable
+#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable
+#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable
+#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable
+#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable
+#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable
+#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable
+#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable
+#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable
+#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable
+#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable
+#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS1 register.
+//
+//*****************************************************************************
+#define NVIC_DIS1_INT_M 0x007FFFFF // Interrupt Disable
+#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable
+#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable
+#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable
+#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable
+#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable
+#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable
+#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable
+#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable
+#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable
+#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable
+#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable
+#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable
+#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable
+#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable
+#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable
+#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable
+#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable
+#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable
+#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable
+#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable
+#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable
+#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable
+#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND0 register.
+//
+//*****************************************************************************
+#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending
+#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend
+#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend
+#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend
+#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend
+#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend
+#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend
+#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend
+#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend
+#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend
+#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend
+#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend
+#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend
+#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend
+#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend
+#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend
+#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend
+#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend
+#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend
+#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend
+#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend
+#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend
+#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend
+#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend
+#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend
+#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend
+#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend
+#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend
+#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend
+#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend
+#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend
+#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend
+#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND1 register.
+//
+//*****************************************************************************
+#define NVIC_PEND1_INT_M 0x007FFFFF // Interrupt Set Pending
+#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend
+#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend
+#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend
+#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend
+#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend
+#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend
+#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend
+#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend
+#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend
+#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend
+#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend
+#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend
+#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend
+#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend
+#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend
+#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend
+#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend
+#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend
+#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend
+#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend
+#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend
+#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend
+#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND0 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending
+#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend
+#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend
+#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend
+#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend
+#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend
+#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend
+#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend
+#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend
+#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend
+#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend
+#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend
+#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend
+#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend
+#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend
+#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend
+#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend
+#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend
+#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend
+#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend
+#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend
+#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend
+#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend
+#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend
+#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend
+#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend
+#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend
+#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend
+#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend
+#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend
+#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend
+#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend
+#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND1 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND1_INT_M 0x007FFFFF // Interrupt Clear Pending
+#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend
+#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend
+#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend
+#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend
+#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend
+#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend
+#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend
+#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend
+#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend
+#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend
+#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend
+#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend
+#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend
+#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend
+#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend
+#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend
+#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend
+#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend
+#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend
+#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend
+#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend
+#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend
+#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE0 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active
+#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active
+#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active
+#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active
+#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active
+#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active
+#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active
+#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active
+#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active
+#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active
+#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active
+#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active
+#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active
+#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active
+#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active
+#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active
+#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active
+#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active
+#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active
+#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active
+#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active
+#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active
+#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active
+#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active
+#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active
+#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active
+#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active
+#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active
+#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active
+#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active
+#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active
+#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active
+#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE1 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE1_INT_M 0x007FFFFF // Interrupt Active
+#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active
+#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active
+#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active
+#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active
+#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active
+#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active
+#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active
+#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active
+#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active
+#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active
+#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active
+#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active
+#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active
+#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active
+#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active
+#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active
+#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active
+#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active
+#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active
+#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active
+#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active
+#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active
+#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI0 register.
+//
+//*****************************************************************************
+#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask
+#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask
+#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask
+#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask
+#define NVIC_PRI0_INT3_S 29
+#define NVIC_PRI0_INT2_S 21
+#define NVIC_PRI0_INT1_S 13
+#define NVIC_PRI0_INT0_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask
+#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask
+#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask
+#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask
+#define NVIC_PRI1_INT7_S 29
+#define NVIC_PRI1_INT6_S 21
+#define NVIC_PRI1_INT5_S 13
+#define NVIC_PRI1_INT4_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask
+#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask
+#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask
+#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask
+#define NVIC_PRI2_INT11_S 29
+#define NVIC_PRI2_INT10_S 21
+#define NVIC_PRI2_INT9_S 13
+#define NVIC_PRI2_INT8_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask
+#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask
+#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask
+#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask
+#define NVIC_PRI3_INT15_S 29
+#define NVIC_PRI3_INT14_S 21
+#define NVIC_PRI3_INT13_S 13
+#define NVIC_PRI3_INT12_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI4 register.
+//
+//*****************************************************************************
+#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask
+#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask
+#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask
+#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask
+#define NVIC_PRI4_INT19_S 29
+#define NVIC_PRI4_INT18_S 21
+#define NVIC_PRI4_INT17_S 13
+#define NVIC_PRI4_INT16_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI5 register.
+//
+//*****************************************************************************
+#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask
+#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask
+#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask
+#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask
+#define NVIC_PRI5_INT23_S 29
+#define NVIC_PRI5_INT22_S 21
+#define NVIC_PRI5_INT21_S 13
+#define NVIC_PRI5_INT20_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI6 register.
+//
+//*****************************************************************************
+#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask
+#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask
+#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask
+#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask
+#define NVIC_PRI6_INT27_S 29
+#define NVIC_PRI6_INT26_S 21
+#define NVIC_PRI6_INT25_S 13
+#define NVIC_PRI6_INT24_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI7 register.
+//
+//*****************************************************************************
+#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask
+#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask
+#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask
+#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask
+#define NVIC_PRI7_INT31_S 29
+#define NVIC_PRI7_INT30_S 21
+#define NVIC_PRI7_INT29_S 13
+#define NVIC_PRI7_INT28_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI8 register.
+//
+//*****************************************************************************
+#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask
+#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask
+#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask
+#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask
+#define NVIC_PRI8_INT35_S 29
+#define NVIC_PRI8_INT34_S 21
+#define NVIC_PRI8_INT33_S 13
+#define NVIC_PRI8_INT32_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI9 register.
+//
+//*****************************************************************************
+#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask
+#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask
+#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask
+#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask
+#define NVIC_PRI9_INT39_S 29
+#define NVIC_PRI9_INT38_S 21
+#define NVIC_PRI9_INT37_S 13
+#define NVIC_PRI9_INT36_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI10 register.
+//
+//*****************************************************************************
+#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask
+#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask
+#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask
+#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask
+#define NVIC_PRI10_INT43_S 29
+#define NVIC_PRI10_INT42_S 21
+#define NVIC_PRI10_INT41_S 13
+#define NVIC_PRI10_INT40_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI11 register.
+//
+//*****************************************************************************
+#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask
+#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask
+#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask
+#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask
+#define NVIC_PRI11_INT47_S 29
+#define NVIC_PRI11_INT46_S 21
+#define NVIC_PRI11_INT45_S 13
+#define NVIC_PRI11_INT44_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI12 register.
+//
+//*****************************************************************************
+#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask
+#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask
+#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask
+#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask
+#define NVIC_PRI12_INT51_S 29
+#define NVIC_PRI12_INT50_S 21
+#define NVIC_PRI12_INT49_S 13
+#define NVIC_PRI12_INT48_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI13 register.
+//
+//*****************************************************************************
+#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask
+#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask
+#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask
+#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask
+#define NVIC_PRI13_INT55_S 29
+#define NVIC_PRI13_INT54_S 21
+#define NVIC_PRI13_INT53_S 13
+#define NVIC_PRI13_INT52_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CPUID register.
+//
+//*****************************************************************************
+#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code
+#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM
+#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number
+#define NVIC_CPUID_CON_M 0x000F0000 // Constant
+#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number
+#define NVIC_CPUID_PARTNO_CM3 0x0000C230 // Cortex-M3 processor
+#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor
+#define NVIC_CPUID_REV_M 0x0000000F // Revision Number
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_INT_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending
+#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending
+#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending
+#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending
+#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending
+#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling
+#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending
+#define NVIC_INT_CTRL_VEC_PEN_M 0x0007F000 // Interrupt Pending Vector Number
+#undef NVIC_INT_CTRL_VEC_PEN_M
+#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number
+#define NVIC_INT_CTRL_VEC_PEN_NMI \
+ 0x00002000 // NMI
+#define NVIC_INT_CTRL_VEC_PEN_HARD \
+ 0x00003000 // Hard fault
+#define NVIC_INT_CTRL_VEC_PEN_MEM \
+ 0x00004000 // Memory management fault
+#define NVIC_INT_CTRL_VEC_PEN_BUS \
+ 0x00005000 // Bus fault
+#define NVIC_INT_CTRL_VEC_PEN_USG \
+ 0x00006000 // Usage fault
+#define NVIC_INT_CTRL_VEC_PEN_SVC \
+ 0x0000B000 // SVCall
+#define NVIC_INT_CTRL_VEC_PEN_PNDSV \
+ 0x0000E000 // PendSV
+#define NVIC_INT_CTRL_VEC_PEN_TICK \
+ 0x0000F000 // SysTick
+#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base
+#define NVIC_INT_CTRL_VEC_ACT_M 0x0000007F // Interrupt Pending Vector Number
+#undef NVIC_INT_CTRL_VEC_ACT_M
+#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number
+#define NVIC_INT_CTRL_VEC_PEN_S 12
+#define NVIC_INT_CTRL_VEC_ACT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_VTABLE register.
+//
+//*****************************************************************************
+#define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base
+#define NVIC_VTABLE_OFFSET_M 0x1FFFFE00 // Vector Table Offset
+#undef NVIC_VTABLE_OFFSET_M
+#define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset
+#define NVIC_VTABLE_OFFSET_S 9
+#undef NVIC_VTABLE_OFFSET_S
+#define NVIC_VTABLE_OFFSET_S 10
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_APINT register.
+//
+//*****************************************************************************
+#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key
+#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key
+#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess
+#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping
+#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split
+#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request
+#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault
+#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending
+#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable
+#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CFG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception
+ // Entry
+#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and
+ // Fault
+#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0
+#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access
+#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger
+#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority
+#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority
+#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority
+#define NVIC_SYS_PRI1_USAGE_S 21
+#define NVIC_SYS_PRI1_BUS_S 13
+#define NVIC_SYS_PRI1_MEM_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority
+#define NVIC_SYS_PRI2_SVC_S 29
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority
+#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority
+#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority
+#define NVIC_SYS_PRI3_TICK_S 29
+#define NVIC_SYS_PRI3_PENDSV_S 21
+#define NVIC_SYS_PRI3_DEBUG_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL
+// register.
+//
+//*****************************************************************************
+#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable
+#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable
+#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable
+#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending
+#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending
+#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending
+#define NVIC_SYS_HND_CTRL_USAGEP \
+ 0x00001000 // Usage Fault Pending
+#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active
+#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active
+#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active
+#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active
+#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active
+#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active
+#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault
+#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault
+#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault
+#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault
+#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault
+#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage
+ // Fault
+#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid
+#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy
+ // State Preservation
+#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault
+#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault
+#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error
+#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error
+#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error
+#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address
+ // Register Valid
+#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on
+ // Floating-Point Lazy State
+ // Preservation
+#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation
+#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation
+#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation
+#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_HFAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event
+#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault
+#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DEBUG_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted
+#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch
+#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match
+#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction
+#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MM_ADDR register.
+//
+//*****************************************************************************
+#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address
+#define NVIC_MM_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_ADDR
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address
+#define NVIC_FAULT_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask
+#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key
+#define NVIC_DBG_CTRL_S_RESET_ST \
+ 0x02000000 // Core has reset since last read
+#define NVIC_DBG_CTRL_S_RETIRE_ST \
+ 0x01000000 // Core has executed insruction
+ // since last read
+#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up
+#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping
+#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt
+#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available
+#define NVIC_DBG_CTRL_C_SNAPSTALL \
+ 0x00000020 // Breaks a stalled load/store
+#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping
+#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core
+#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core
+#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_XFER register.
+//
+//*****************************************************************************
+#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read
+#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register
+#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0
+#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1
+#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2
+#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3
+#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4
+#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5
+#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6
+#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7
+#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8
+#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9
+#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10
+#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11
+#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12
+#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13
+#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14
+#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register
+#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP
+#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP
+#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP
+#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_DATA register.
+//
+//*****************************************************************************
+#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache
+#define NVIC_DBG_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_INT register.
+//
+//*****************************************************************************
+#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault
+#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors
+#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error
+#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state
+#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check
+#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error
+#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault
+#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status
+#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset
+#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending
+#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SW_TRIG register.
+//
+//*****************************************************************************
+#define NVIC_SW_TRIG_INTID_M 0x0000003F // Interrupt ID
+#define NVIC_SW_TRIG_INTID_S 0
+
+#endif // __HW_NVIC_H__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_pka.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_pka.h
new file mode 100644
index 0000000..377f08e
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_pka.h
@@ -0,0 +1,606 @@
+/******************************************************************************
+* Filename: hw_pka_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_PKA_H__
+#define __HW_PKA_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// PKA component
+//
+//*****************************************************************************
+// PKA Vector A Address
+#define PKA_O_APTR 0x00000000
+
+// PKA Vector B Address
+#define PKA_O_BPTR 0x00000004
+
+// PKA Vector C Address
+#define PKA_O_CPTR 0x00000008
+
+// PKA Vector D Address
+#define PKA_O_DPTR 0x0000000C
+
+// PKA Vector A Length
+#define PKA_O_ALENGTH 0x00000010
+
+// PKA Vector B Length
+#define PKA_O_BLENGTH 0x00000014
+
+// PKA Bit Shift Value
+#define PKA_O_SHIFT 0x00000018
+
+// PKA Function
+#define PKA_O_FUNCTION 0x0000001C
+
+// PKA compare result
+#define PKA_O_COMPARE 0x00000020
+
+// PKA most-significant-word of result vector
+#define PKA_O_MSW 0x00000024
+
+// PKA most-significant-word of divide remainder
+#define PKA_O_DIVMSW 0x00000028
+
+// PKA sequencer control and status register
+#define PKA_O_SEQCTRL 0x000000C8
+
+// PKA hardware options register
+#define PKA_O_OPTIONS 0x000000F4
+
+// PKA firmware revision and capabilities register
+#define PKA_O_FWREV 0x000000F8
+
+// PKA hardware revision register
+#define PKA_O_HWREV 0x000000FC
+
+//*****************************************************************************
+//
+// Register: PKA_O_APTR
+//
+//*****************************************************************************
+// Field: [10:0] APTR
+//
+// This register specifies the location of vector A within the PKA RAM. Vectors
+// are identified through the location of their least-significant 32-bit word.
+// Note that bit [0] must be zero to ensure that the vector starts at an 8-byte
+// boundary.
+#define PKA_APTR_APTR_W 11
+#define PKA_APTR_APTR_M 0x000007FF
+#define PKA_APTR_APTR_S 0
+
+//*****************************************************************************
+//
+// Register: PKA_O_BPTR
+//
+//*****************************************************************************
+// Field: [10:0] BPTR
+//
+// This register specifies the location of vector B within the PKA RAM. Vectors
+// are identified through the location of their least-significant 32-bit word.
+// Note that bit [0] must be zero to ensure that the vector starts at an 8-byte
+// boundary.
+#define PKA_BPTR_BPTR_W 11
+#define PKA_BPTR_BPTR_M 0x000007FF
+#define PKA_BPTR_BPTR_S 0
+
+//*****************************************************************************
+//
+// Register: PKA_O_CPTR
+//
+//*****************************************************************************
+// Field: [10:0] CPTR
+//
+// This register specifies the location of vector C within the PKA RAM. Vectors
+// are identified through the location of their least-significant 32-bit word.
+// Note that bit [0] must be zero to ensure that the vector starts at an 8-byte
+// boundary.
+#define PKA_CPTR_CPTR_W 11
+#define PKA_CPTR_CPTR_M 0x000007FF
+#define PKA_CPTR_CPTR_S 0
+
+//*****************************************************************************
+//
+// Register: PKA_O_DPTR
+//
+//*****************************************************************************
+// Field: [10:0] DPTR
+//
+// This register specifies the location of vector D within the PKA RAM. Vectors
+// are identified through the location of their least-significant 32-bit word.
+// Note that bit [0] must be zero to ensure that the vector starts at an 8-byte
+// boundary.
+#define PKA_DPTR_DPTR_W 11
+#define PKA_DPTR_DPTR_M 0x000007FF
+#define PKA_DPTR_DPTR_S 0
+
+//*****************************************************************************
+//
+// Register: PKA_O_ALENGTH
+//
+//*****************************************************************************
+// Field: [8:0] ALENGTH
+//
+// This register specifies the length (in 32-bit words) of Vector A.
+#define PKA_ALENGTH_ALENGTH_W 9
+#define PKA_ALENGTH_ALENGTH_M 0x000001FF
+#define PKA_ALENGTH_ALENGTH_S 0
+
+//*****************************************************************************
+//
+// Register: PKA_O_BLENGTH
+//
+//*****************************************************************************
+// Field: [8:0] BLENGTH
+//
+// This register specifies the length (in 32-bit words) of Vector B.
+#define PKA_BLENGTH_BLENGTH_W 9
+#define PKA_BLENGTH_BLENGTH_M 0x000001FF
+#define PKA_BLENGTH_BLENGTH_S 0
+
+//*****************************************************************************
+//
+// Register: PKA_O_SHIFT
+//
+//*****************************************************************************
+// Field: [4:0] NUM_BITS_TO_SHIFT
+//
+// This register specifies the number of bits to shift the input vector (in the
+// range 0-31) during a Rshift or Lshift operation.
+#define PKA_SHIFT_NUM_BITS_TO_SHIFT_W 5
+#define PKA_SHIFT_NUM_BITS_TO_SHIFT_M 0x0000001F
+#define PKA_SHIFT_NUM_BITS_TO_SHIFT_S 0
+
+//*****************************************************************************
+//
+// Register: PKA_O_FUNCTION
+//
+//*****************************************************************************
+// Field: [24] STALL_RESULT
+//
+// When written with a 1b, updating of the COMPARE bit, MSW and DIVMSW
+// registers, as well as resetting the run bit is stalled beyond the point that
+// a running operation is actually finished. Use this to allow software enough
+// time to read results from a previous operation when the newly started
+// operation is known to take only a short amount of time. If a result is
+// waiting, the result registers is updated and the run bit is reset in the
+// clock cycle following writing the stall result bit back to 0b. The Stall
+// result function may only be used for basic PKCP operations.
+#define PKA_FUNCTION_STALL_RESULT 0x01000000
+#define PKA_FUNCTION_STALL_RESULT_BITN 24
+#define PKA_FUNCTION_STALL_RESULT_M 0x01000000
+#define PKA_FUNCTION_STALL_RESULT_S 24
+
+// Field: [15] RUN
+//
+// The host sets this bit to instruct the PKA module to begin processing the
+// basic PKCP or complex sequencer operation. This bit is reset low
+// automatically when the operation is complete.
+// After a reset, the run bit is always set to 1b. Depending on the option,
+// program ROM or program RAM, the following applies:
+// Program ROM - The first sequencer instruction sets the bit to 0b. This is
+// done immediately after the hardware reset is released.
+// Program RAM - The sequencer must set the bit to 0b. As a valid firmware may
+// not have been loaded, the sequencer is held in software reset after the
+// hardware reset is released (the SEQCTRL.RESET bit is set to 1b). After the
+// FW image is loaded and the Reset bit is cleared, the sequencer starts to
+// execute the FW. The first instruction clears the run bit.
+// In both cases a few clock cycles are needed before the first instruction is
+// executed and the run bit state has been propagated.
+#define PKA_FUNCTION_RUN 0x00008000
+#define PKA_FUNCTION_RUN_BITN 15
+#define PKA_FUNCTION_RUN_M 0x00008000
+#define PKA_FUNCTION_RUN_S 15
+
+// Field: [14:12] SEQUENCER_OPERATIONS
+//
+// These bits select the complex sequencer operation to perform:
+// 0x0: None
+// 0x1: ExpMod-CRT
+// 0x2: ECmontMUL
+// 0x3: ECC-ADD (if available in firmware, otherwise reserved)
+// 0x4: ExpMod-ACT2
+// 0x5: ECC-MUL (if available in firmware, otherwise reserved)
+// 0x6: ExpMod-variable
+// 0x7: ModInv (if available in firmware, otherwise reserved)
+// The encoding of these operations is determined by sequencer firmware.
+#define PKA_FUNCTION_SEQUENCER_OPERATIONS_W 3
+#define PKA_FUNCTION_SEQUENCER_OPERATIONS_M 0x00007000
+#define PKA_FUNCTION_SEQUENCER_OPERATIONS_S 12
+
+// Field: [11] COPY
+//
+// Perform copy operation
+#define PKA_FUNCTION_COPY 0x00000800
+#define PKA_FUNCTION_COPY_BITN 11
+#define PKA_FUNCTION_COPY_M 0x00000800
+#define PKA_FUNCTION_COPY_S 11
+
+// Field: [10] COMPARE
+//
+// Perform compare operation
+#define PKA_FUNCTION_COMPARE 0x00000400
+#define PKA_FUNCTION_COMPARE_BITN 10
+#define PKA_FUNCTION_COMPARE_M 0x00000400
+#define PKA_FUNCTION_COMPARE_S 10
+
+// Field: [9] MODULO
+//
+// Perform modulo operation
+#define PKA_FUNCTION_MODULO 0x00000200
+#define PKA_FUNCTION_MODULO_BITN 9
+#define PKA_FUNCTION_MODULO_M 0x00000200
+#define PKA_FUNCTION_MODULO_S 9
+
+// Field: [8] DIVIDE
+//
+// Perform divide operation
+#define PKA_FUNCTION_DIVIDE 0x00000100
+#define PKA_FUNCTION_DIVIDE_BITN 8
+#define PKA_FUNCTION_DIVIDE_M 0x00000100
+#define PKA_FUNCTION_DIVIDE_S 8
+
+// Field: [7] LSHIFT
+//
+// Perform left shift operation
+#define PKA_FUNCTION_LSHIFT 0x00000080
+#define PKA_FUNCTION_LSHIFT_BITN 7
+#define PKA_FUNCTION_LSHIFT_M 0x00000080
+#define PKA_FUNCTION_LSHIFT_S 7
+
+// Field: [6] RSHIFT
+//
+// Perform right shift operation
+#define PKA_FUNCTION_RSHIFT 0x00000040
+#define PKA_FUNCTION_RSHIFT_BITN 6
+#define PKA_FUNCTION_RSHIFT_M 0x00000040
+#define PKA_FUNCTION_RSHIFT_S 6
+
+// Field: [5] SUBTRACT
+//
+// Perform subtract operation
+#define PKA_FUNCTION_SUBTRACT 0x00000020
+#define PKA_FUNCTION_SUBTRACT_BITN 5
+#define PKA_FUNCTION_SUBTRACT_M 0x00000020
+#define PKA_FUNCTION_SUBTRACT_S 5
+
+// Field: [4] ADD
+//
+// Perform add operation
+#define PKA_FUNCTION_ADD 0x00000010
+#define PKA_FUNCTION_ADD_BITN 4
+#define PKA_FUNCTION_ADD_M 0x00000010
+#define PKA_FUNCTION_ADD_S 4
+
+// Field: [3] MS_ONE
+//
+// Loads the location of the Most Significant one bit within the result word
+// indicated in the MSW register into bits [4:0] of the DIVMSW.MSW_ADDRESS
+// register - can only be used with basic PKCP operations, except for Divide,
+// Modulo and Compare.
+#define PKA_FUNCTION_MS_ONE 0x00000008
+#define PKA_FUNCTION_MS_ONE_BITN 3
+#define PKA_FUNCTION_MS_ONE_M 0x00000008
+#define PKA_FUNCTION_MS_ONE_S 3
+
+// Field: [1] ADDSUB
+//
+// Perform combined add/subtract operation
+#define PKA_FUNCTION_ADDSUB 0x00000002
+#define PKA_FUNCTION_ADDSUB_BITN 1
+#define PKA_FUNCTION_ADDSUB_M 0x00000002
+#define PKA_FUNCTION_ADDSUB_S 1
+
+// Field: [0] MULTIPLY
+//
+// Perform multiply operation
+#define PKA_FUNCTION_MULTIPLY 0x00000001
+#define PKA_FUNCTION_MULTIPLY_BITN 0
+#define PKA_FUNCTION_MULTIPLY_M 0x00000001
+#define PKA_FUNCTION_MULTIPLY_S 0
+
+//*****************************************************************************
+//
+// Register: PKA_O_COMPARE
+//
+//*****************************************************************************
+// Field: [2] A_GREATER_THAN_B
+//
+// Vector_A is greater than Vector_B
+#define PKA_COMPARE_A_GREATER_THAN_B 0x00000004
+#define PKA_COMPARE_A_GREATER_THAN_B_BITN 2
+#define PKA_COMPARE_A_GREATER_THAN_B_M 0x00000004
+#define PKA_COMPARE_A_GREATER_THAN_B_S 2
+
+// Field: [1] A_LESS_THAN_B
+//
+// Vector_A is less than Vector_B
+#define PKA_COMPARE_A_LESS_THAN_B 0x00000002
+#define PKA_COMPARE_A_LESS_THAN_B_BITN 1
+#define PKA_COMPARE_A_LESS_THAN_B_M 0x00000002
+#define PKA_COMPARE_A_LESS_THAN_B_S 1
+
+// Field: [0] A_EQUALS_B
+//
+// Vector_A is equal to Vector_B
+#define PKA_COMPARE_A_EQUALS_B 0x00000001
+#define PKA_COMPARE_A_EQUALS_B_BITN 0
+#define PKA_COMPARE_A_EQUALS_B_M 0x00000001
+#define PKA_COMPARE_A_EQUALS_B_S 0
+
+//*****************************************************************************
+//
+// Register: PKA_O_MSW
+//
+//*****************************************************************************
+// Field: [15] RESULT_IS_ZERO
+//
+// The result vector is all zeroes, ignore the address returned in bits [10:0]
+#define PKA_MSW_RESULT_IS_ZERO 0x00008000
+#define PKA_MSW_RESULT_IS_ZERO_BITN 15
+#define PKA_MSW_RESULT_IS_ZERO_M 0x00008000
+#define PKA_MSW_RESULT_IS_ZERO_S 15
+
+// Field: [10:0] MSW_ADDRESS
+//
+// Address of the most-significant nonzero 32-bit word of the result vector in
+// PKA RAM
+#define PKA_MSW_MSW_ADDRESS_W 11
+#define PKA_MSW_MSW_ADDRESS_M 0x000007FF
+#define PKA_MSW_MSW_ADDRESS_S 0
+
+//*****************************************************************************
+//
+// Register: PKA_O_DIVMSW
+//
+//*****************************************************************************
+// Field: [15] RESULT_IS_ZERO
+//
+// The result vector is all zeroes, ignore the address returned in bits [10:0]
+#define PKA_DIVMSW_RESULT_IS_ZERO 0x00008000
+#define PKA_DIVMSW_RESULT_IS_ZERO_BITN 15
+#define PKA_DIVMSW_RESULT_IS_ZERO_M 0x00008000
+#define PKA_DIVMSW_RESULT_IS_ZERO_S 15
+
+// Field: [10:0] MSW_ADDRESS
+//
+// Address of the most significant nonzero 32-bit word of the remainder result
+// vector in PKA RAM
+#define PKA_DIVMSW_MSW_ADDRESS_W 11
+#define PKA_DIVMSW_MSW_ADDRESS_M 0x000007FF
+#define PKA_DIVMSW_MSW_ADDRESS_S 0
+
+//*****************************************************************************
+//
+// Register: PKA_O_SEQCTRL
+//
+//*****************************************************************************
+// Field: [31] RESET
+//
+// Option program ROM: Reset value = 0. Read/Write, reset value 0b (ZERO).
+// Writing 1b resets the sequencer, write to 0b to restart operations again. As
+// the reset value is 0b, the sequencer will automatically start operations
+// executing from program ROM. This bit should always be written with zero and
+// ignored when reading this register.
+//
+// Option Program RAM: Reset value =1. Read/Write, reset value 1b (ONE). When
+// 1b, the sequencer is held in a reset state and the PKA_PROGRAM area is
+// accessible for loading the sequencer program (while the PKA_DATA_RAM is
+// inaccessible), write to 0b to (re)start sequencer operations and disable
+// PKA_PROGRAM area accessibility (also enables the PKA_DATA_RAM accesses).
+// Resetting the sequencer (in order to load other firmware) should only be
+// done when the PKA Engine is not performing any operations (i.e. the
+// FUNCTION.RUN bit should be zero).
+#define PKA_SEQCTRL_RESET 0x80000000
+#define PKA_SEQCTRL_RESET_BITN 31
+#define PKA_SEQCTRL_RESET_M 0x80000000
+#define PKA_SEQCTRL_RESET_S 31
+
+// Field: [15:8] SEQUENCER_STAT
+//
+// These read-only bits can be used by the sequencer to communicate status to
+// the outside world. Bit [8] is also used as sequencer interrupt, with the
+// complement of this bit ORed into the FUNCTION.RUN bit. This field should
+// always be written with zeroes and ignored when reading this register.
+#define PKA_SEQCTRL_SEQUENCER_STAT_W 8
+#define PKA_SEQCTRL_SEQUENCER_STAT_M 0x0000FF00
+#define PKA_SEQCTRL_SEQUENCER_STAT_S 8
+
+// Field: [7:0] SW_CONTROL_STAT
+//
+// These bits can be used by software to trigger sequencer operations. External
+// logic can set these bits by writing 1b, cannot reset them by writing 0b. The
+// sequencer can reset these bits by writing 0b, cannot set them by writing 1b.
+// Setting the FUNCTION.RUN bit together with a nonzero sequencer operations
+// field automatically sets bit [0] here. This field should always be written
+// with zeroes and ignored when reading this register.
+#define PKA_SEQCTRL_SW_CONTROL_STAT_W 8
+#define PKA_SEQCTRL_SW_CONTROL_STAT_M 0x000000FF
+#define PKA_SEQCTRL_SW_CONTROL_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: PKA_O_OPTIONS
+//
+//*****************************************************************************
+// Field: [11] INT_MASKING
+//
+// Interrupt Masking
+// 0x0: indicates that the main interrupt output (bit [1] of the interrupts
+// output bus) is the direct complement of the run bit in the PKA_CONTROL
+// register, 0x1 : indicates
+// that interrupt masking logic is present for this output.
+// Note: Reset value is undefined
+#define PKA_OPTIONS_INT_MASKING 0x00000800
+#define PKA_OPTIONS_INT_MASKING_BITN 11
+#define PKA_OPTIONS_INT_MASKING_M 0x00000800
+#define PKA_OPTIONS_INT_MASKING_S 11
+
+// Field: [10:8] PROTECTION_OPTION
+//
+// Protection Option
+// 0x0: indicates no additional protection against side channel attacks,
+//
+// 0x1: indicates the SCAP option
+// 0x2: Reserved
+// 0x3: indicates the PROT option;
+// Note: Reset value is undefined
+#define PKA_OPTIONS_PROTECTION_OPTION_W 3
+#define PKA_OPTIONS_PROTECTION_OPTION_M 0x00000700
+#define PKA_OPTIONS_PROTECTION_OPTION_S 8
+
+// Field: [7] PROGRAM_RAM
+//
+// Program RAM
+// 0x1: indicates sequencer program storage in RAM, 0x0:
+// indicates sequencer program storage in ROM.
+// Note: Reset value is undefined
+#define PKA_OPTIONS_PROGRAM_RAM 0x00000080
+#define PKA_OPTIONS_PROGRAM_RAM_BITN 7
+#define PKA_OPTIONS_PROGRAM_RAM_M 0x00000080
+#define PKA_OPTIONS_PROGRAM_RAM_S 7
+
+// Field: [6:5] SEQUENCER_CONFIGURATION
+//
+// Sequencer Configuration
+// 0x0: Reserved
+// 0x1 : Indicates a standard sequencer
+// 0x2: Reserved
+// 0x3: Reserved
+#define PKA_OPTIONS_SEQUENCER_CONFIGURATION_W 2
+#define PKA_OPTIONS_SEQUENCER_CONFIGURATION_M 0x00000060
+#define PKA_OPTIONS_SEQUENCER_CONFIGURATION_S 5
+
+// Field: [1:0] PKCP_CONFIGURATION
+//
+// PKCP Configuration 0x0
+// : Reserved
+// 0x1 : Indicates a PKCP with a 16x16 multiplier, 0x2:
+// indicates a PKCP with a 32x32 multiplier, 0x3 : Reserved
+// Note: Reset value is undefined.
+#define PKA_OPTIONS_PKCP_CONFIGURATION_W 2
+#define PKA_OPTIONS_PKCP_CONFIGURATION_M 0x00000003
+#define PKA_OPTIONS_PKCP_CONFIGURATION_S 0
+
+//*****************************************************************************
+//
+// Register: PKA_O_FWREV
+//
+//*****************************************************************************
+// Field: [31:28] FW_CAPABILITIES
+//
+// Firmware Capabilities
+//
+// 4-bit binary encoding for the functionality implemented
+// in the firmware.
+// 0x0: indicates basic ModExp with/without CRT. 0x1:
+// adds Modular Inversion, 0x2: value
+// 2 adds Modular Inversion and ECC operations.
+// 0x3-0xF : Reserved.
+#define PKA_FWREV_FW_CAPABILITIES_W 4
+#define PKA_FWREV_FW_CAPABILITIES_M 0xF0000000
+#define PKA_FWREV_FW_CAPABILITIES_S 28
+
+// Field: [27:24] MAJOR_FW_REVISION
+//
+// 4-bit binary encoding of the major firmware revision number
+#define PKA_FWREV_MAJOR_FW_REVISION_W 4
+#define PKA_FWREV_MAJOR_FW_REVISION_M 0x0F000000
+#define PKA_FWREV_MAJOR_FW_REVISION_S 24
+
+// Field: [23:20] MINOR_FW_REVISION
+//
+// 4-bit binary encoding of the minor firmware revision number
+#define PKA_FWREV_MINOR_FW_REVISION_W 4
+#define PKA_FWREV_MINOR_FW_REVISION_M 0x00F00000
+#define PKA_FWREV_MINOR_FW_REVISION_S 20
+
+// Field: [19:16] FW_PATCH_LEVEL
+//
+// 4-bit binary encoding of the firmware patch level, initial release will
+// carry value zero
+// Patches are used to remove bugs without changing the functionality or
+// interface of a module.
+#define PKA_FWREV_FW_PATCH_LEVEL_W 4
+#define PKA_FWREV_FW_PATCH_LEVEL_M 0x000F0000
+#define PKA_FWREV_FW_PATCH_LEVEL_S 16
+
+//*****************************************************************************
+//
+// Register: PKA_O_HWREV
+//
+//*****************************************************************************
+// Field: [27:24] MAJOR_HW_REVISION
+//
+// 4-bit binary encoding of the major hardware revision number
+#define PKA_HWREV_MAJOR_HW_REVISION_W 4
+#define PKA_HWREV_MAJOR_HW_REVISION_M 0x0F000000
+#define PKA_HWREV_MAJOR_HW_REVISION_S 24
+
+// Field: [23:20] MINOR_HW_REVISION
+//
+// 4-bit binary encoding of the minor hardware revision number
+#define PKA_HWREV_MINOR_HW_REVISION_W 4
+#define PKA_HWREV_MINOR_HW_REVISION_M 0x00F00000
+#define PKA_HWREV_MINOR_HW_REVISION_S 20
+
+// Field: [19:16] HW_PATCH_LEVEL
+//
+// 4-bit binary encoding of the hardware patch level, initial release will
+// carry value zero
+// Patches are used to remove bugs without changing the functionality or
+// interface of a module.
+#define PKA_HWREV_HW_PATCH_LEVEL_W 4
+#define PKA_HWREV_HW_PATCH_LEVEL_M 0x000F0000
+#define PKA_HWREV_HW_PATCH_LEVEL_S 16
+
+// Field: [15:8] COMPLEMENT_OF_BASIC_EIP_NUMBER
+//
+// Bit-by-bit logic complement of bits [7:0], EIP-28 gives 0xE3
+#define PKA_HWREV_COMPLEMENT_OF_BASIC_EIP_NUMBER_W 8
+#define PKA_HWREV_COMPLEMENT_OF_BASIC_EIP_NUMBER_M 0x0000FF00
+#define PKA_HWREV_COMPLEMENT_OF_BASIC_EIP_NUMBER_S 8
+
+// Field: [7:0] BASIC_EIP_NUMBER
+//
+// 8-bit binary encoding of the EIP number, EIP-28 gives 0x1C
+#define PKA_HWREV_BASIC_EIP_NUMBER_W 8
+#define PKA_HWREV_BASIC_EIP_NUMBER_M 0x000000FF
+#define PKA_HWREV_BASIC_EIP_NUMBER_S 0
+
+
+#endif // __PKA__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_pka_int.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_pka_int.h
new file mode 100644
index 0000000..159ea4c
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_pka_int.h
@@ -0,0 +1,157 @@
+/******************************************************************************
+* Filename: hw_pka_int_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_PKA_INT_H__
+#define __HW_PKA_INT_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// PKA_INT component
+//
+//*****************************************************************************
+// PKA Options register
+#define PKA_INT_O_OPTIONS 0x00000FF8
+
+// PKA hardware revision register
+#define PKA_INT_O_REVISION 0x00000FFC
+
+//*****************************************************************************
+//
+// Register: PKA_INT_O_OPTIONS
+//
+//*****************************************************************************
+// Field: [10] AIC_PRESENT
+//
+// When set to '1', indicates that an EIP201 AIC is included in the EIP150
+#define PKA_INT_OPTIONS_AIC_PRESENT 0x00000400
+#define PKA_INT_OPTIONS_AIC_PRESENT_BITN 10
+#define PKA_INT_OPTIONS_AIC_PRESENT_M 0x00000400
+#define PKA_INT_OPTIONS_AIC_PRESENT_S 10
+
+// Field: [9] EIP76_PRESENT
+//
+// When set to '1', indicates that the EIP76 TRNG is included in the EIP150
+#define PKA_INT_OPTIONS_EIP76_PRESENT 0x00000200
+#define PKA_INT_OPTIONS_EIP76_PRESENT_BITN 9
+#define PKA_INT_OPTIONS_EIP76_PRESENT_M 0x00000200
+#define PKA_INT_OPTIONS_EIP76_PRESENT_S 9
+
+// Field: [8] EIP28_PRESENT
+//
+// When set to '1', indicates that the EIP28 PKA is included in the EIP150
+#define PKA_INT_OPTIONS_EIP28_PRESENT 0x00000100
+#define PKA_INT_OPTIONS_EIP28_PRESENT_BITN 8
+#define PKA_INT_OPTIONS_EIP28_PRESENT_M 0x00000100
+#define PKA_INT_OPTIONS_EIP28_PRESENT_S 8
+
+// Field: [3] AXI_INTERFACE
+//
+// When set to '1', indicates that the EIP150 is equipped with a AXI interface
+#define PKA_INT_OPTIONS_AXI_INTERFACE 0x00000008
+#define PKA_INT_OPTIONS_AXI_INTERFACE_BITN 3
+#define PKA_INT_OPTIONS_AXI_INTERFACE_M 0x00000008
+#define PKA_INT_OPTIONS_AXI_INTERFACE_S 3
+
+// Field: [2] AHB_IS_ASYNC
+//
+// When set to '1', indicates that AHB interface is asynchronous Only
+// applicable when AHB_INTERFACE is 1
+#define PKA_INT_OPTIONS_AHB_IS_ASYNC 0x00000004
+#define PKA_INT_OPTIONS_AHB_IS_ASYNC_BITN 2
+#define PKA_INT_OPTIONS_AHB_IS_ASYNC_M 0x00000004
+#define PKA_INT_OPTIONS_AHB_IS_ASYNC_S 2
+
+// Field: [1] AHB_INTERFACE
+//
+// When set to '1', indicates that the EIP150 is equipped with a AHB interface
+#define PKA_INT_OPTIONS_AHB_INTERFACE 0x00000002
+#define PKA_INT_OPTIONS_AHB_INTERFACE_BITN 1
+#define PKA_INT_OPTIONS_AHB_INTERFACE_M 0x00000002
+#define PKA_INT_OPTIONS_AHB_INTERFACE_S 1
+
+// Field: [0] PLB_INTERFACE
+//
+// When set to '1', indicates that the EIP150 is equipped with a PLB interface
+#define PKA_INT_OPTIONS_PLB_INTERFACE 0x00000001
+#define PKA_INT_OPTIONS_PLB_INTERFACE_BITN 0
+#define PKA_INT_OPTIONS_PLB_INTERFACE_M 0x00000001
+#define PKA_INT_OPTIONS_PLB_INTERFACE_S 0
+
+//*****************************************************************************
+//
+// Register: PKA_INT_O_REVISION
+//
+//*****************************************************************************
+// Field: [27:24] MAJOR_REVISION
+//
+// These bits encode the major version number for this module
+#define PKA_INT_REVISION_MAJOR_REVISION_W 4
+#define PKA_INT_REVISION_MAJOR_REVISION_M 0x0F000000
+#define PKA_INT_REVISION_MAJOR_REVISION_S 24
+
+// Field: [23:20] MINOR_REVISION
+//
+// These bits encode the minor version number for this module
+#define PKA_INT_REVISION_MINOR_REVISION_W 4
+#define PKA_INT_REVISION_MINOR_REVISION_M 0x00F00000
+#define PKA_INT_REVISION_MINOR_REVISION_S 20
+
+// Field: [19:16] PATCH_LEVEL
+//
+// These bits encode the hardware patch level for this module they start at
+// value 0 on the first release
+#define PKA_INT_REVISION_PATCH_LEVEL_W 4
+#define PKA_INT_REVISION_PATCH_LEVEL_M 0x000F0000
+#define PKA_INT_REVISION_PATCH_LEVEL_S 16
+
+// Field: [15:8] COMP_EIP_NUM
+//
+// These bits simply contain the complement of bits [7:0], used by a driver to
+// ascertain that the EIP150 revision register is indeed read
+#define PKA_INT_REVISION_COMP_EIP_NUM_W 8
+#define PKA_INT_REVISION_COMP_EIP_NUM_M 0x0000FF00
+#define PKA_INT_REVISION_COMP_EIP_NUM_S 8
+
+// Field: [7:0] EIP_NUM
+//
+// These bits encode the AuthenTec EIP number for the EIP150
+#define PKA_INT_REVISION_EIP_NUM_W 8
+#define PKA_INT_REVISION_EIP_NUM_M 0x000000FF
+#define PKA_INT_REVISION_EIP_NUM_S 0
+
+
+#endif // __PKA_INT__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_pka_ram.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_pka_ram.h
new file mode 100644
index 0000000..3a9c12c
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_pka_ram.h
@@ -0,0 +1,48 @@
+/******************************************************************************
+* Filename: hw_pka_ram_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_PKA_RAM_H__
+#define __HW_PKA_RAM_H__
+
+
+#define PKA_RAM_O_BANK0 0x00000000
+#define PKA_RAM_BANK0_BYTE_SIZE 2048
+
+#define PKA_RAM_TOT_BYTE_SIZE 2048
+
+
+
+#endif // __HW_PKA_RAM__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_prcm.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_prcm.h
new file mode 100644
index 0000000..1aa7f03
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_prcm.h
@@ -0,0 +1,2529 @@
+/******************************************************************************
+* Filename: hw_prcm_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_PRCM_H__
+#define __HW_PRCM_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// PRCM component
+//
+//*****************************************************************************
+// Infrastructure Clock Division Factor For Run Mode
+#define PRCM_O_INFRCLKDIVR 0x00000000
+
+// Infrastructure Clock Division Factor For Sleep Mode
+#define PRCM_O_INFRCLKDIVS 0x00000004
+
+// Infrastructure Clock Division Factor For DeepSleep Mode
+#define PRCM_O_INFRCLKDIVDS 0x00000008
+
+// MCU Voltage Domain Control
+#define PRCM_O_VDCTL 0x0000000C
+
+// Load PRCM Settings To CLKCTRL Power Domain
+#define PRCM_O_CLKLOADCTL 0x00000028
+
+// RFC Clock Gate
+#define PRCM_O_RFCCLKG 0x0000002C
+
+// VIMS Clock Gate
+#define PRCM_O_VIMSCLKG 0x00000030
+
+// SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Run And All Modes
+#define PRCM_O_SECDMACLKGR 0x0000003C
+
+// SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Sleep Mode
+#define PRCM_O_SECDMACLKGS 0x00000040
+
+// SEC (PKA And TRNG and CRYPTO) And UDMA Clock Gate For Deep Sleep Mode
+#define PRCM_O_SECDMACLKGDS 0x00000044
+
+// GPIO Clock Gate For Run And All Modes
+#define PRCM_O_GPIOCLKGR 0x00000048
+
+// GPIO Clock Gate For Sleep Mode
+#define PRCM_O_GPIOCLKGS 0x0000004C
+
+// GPIO Clock Gate For Deep Sleep Mode
+#define PRCM_O_GPIOCLKGDS 0x00000050
+
+// GPT Clock Gate For Run And All Modes
+#define PRCM_O_GPTCLKGR 0x00000054
+
+// GPT Clock Gate For Sleep Mode
+#define PRCM_O_GPTCLKGS 0x00000058
+
+// GPT Clock Gate For Deep Sleep Mode
+#define PRCM_O_GPTCLKGDS 0x0000005C
+
+// I2C Clock Gate For Run And All Modes
+#define PRCM_O_I2CCLKGR 0x00000060
+
+// I2C Clock Gate For Sleep Mode
+#define PRCM_O_I2CCLKGS 0x00000064
+
+// I2C Clock Gate For Deep Sleep Mode
+#define PRCM_O_I2CCLKGDS 0x00000068
+
+// UART Clock Gate For Run And All Modes
+#define PRCM_O_UARTCLKGR 0x0000006C
+
+// UART Clock Gate For Sleep Mode
+#define PRCM_O_UARTCLKGS 0x00000070
+
+// UART Clock Gate For Deep Sleep Mode
+#define PRCM_O_UARTCLKGDS 0x00000074
+
+// SSI Clock Gate For Run And All Modes
+#define PRCM_O_SSICLKGR 0x00000078
+
+// SSI Clock Gate For Sleep Mode
+#define PRCM_O_SSICLKGS 0x0000007C
+
+// SSI Clock Gate For Deep Sleep Mode
+#define PRCM_O_SSICLKGDS 0x00000080
+
+// I2S Clock Gate For Run And All Modes
+#define PRCM_O_I2SCLKGR 0x00000084
+
+// I2S Clock Gate For Sleep Mode
+#define PRCM_O_I2SCLKGS 0x00000088
+
+// I2S Clock Gate For Deep Sleep Mode
+#define PRCM_O_I2SCLKGDS 0x0000008C
+
+// Internal
+#define PRCM_O_SYSBUSCLKDIV 0x000000B4
+
+// Internal
+#define PRCM_O_CPUCLKDIV 0x000000B8
+
+// Internal
+#define PRCM_O_PERBUSCPUCLKDIV 0x000000BC
+
+// Internal
+#define PRCM_O_PERDMACLKDIV 0x000000C4
+
+// I2S Clock Control
+#define PRCM_O_I2SBCLKSEL 0x000000C8
+
+// GPT Scalar
+#define PRCM_O_GPTCLKDIV 0x000000CC
+
+// I2S Clock Control
+#define PRCM_O_I2SCLKCTL 0x000000D0
+
+// MCLK Division Ratio
+#define PRCM_O_I2SMCLKDIV 0x000000D4
+
+// BCLK Division Ratio
+#define PRCM_O_I2SBCLKDIV 0x000000D8
+
+// WCLK Division Ratio
+#define PRCM_O_I2SWCLKDIV 0x000000DC
+
+// RESET For SEC (PKA And TRNG And CRYPTO) And UDMA
+#define PRCM_O_RESETSECDMA 0x000000F0
+
+// RESET For GPIO IPs
+#define PRCM_O_RESETGPIO 0x000000F4
+
+// RESET For GPT Ips
+#define PRCM_O_RESETGPT 0x000000F8
+
+// RESET For I2C IPs
+#define PRCM_O_RESETI2C 0x000000FC
+
+// RESET For UART IPs
+#define PRCM_O_RESETUART 0x00000100
+
+// RESET For SSI IPs
+#define PRCM_O_RESETSSI 0x00000104
+
+// RESET For I2S IP
+#define PRCM_O_RESETI2S 0x00000108
+
+// Power Domain Control
+#define PRCM_O_PDCTL0 0x0000012C
+
+// RFC Power Domain Control
+#define PRCM_O_PDCTL0RFC 0x00000130
+
+// SERIAL Power Domain Control
+#define PRCM_O_PDCTL0SERIAL 0x00000134
+
+// PERIPH Power Domain Control
+#define PRCM_O_PDCTL0PERIPH 0x00000138
+
+// Power Domain Status
+#define PRCM_O_PDSTAT0 0x00000140
+
+// RFC Power Domain Status
+#define PRCM_O_PDSTAT0RFC 0x00000144
+
+// SERIAL Power Domain Status
+#define PRCM_O_PDSTAT0SERIAL 0x00000148
+
+// PERIPH Power Domain Status
+#define PRCM_O_PDSTAT0PERIPH 0x0000014C
+
+// Power Domain Control
+#define PRCM_O_PDCTL1 0x0000017C
+
+// CPU Power Domain Direct Control
+#define PRCM_O_PDCTL1CPU 0x00000184
+
+// RFC Power Domain Direct Control
+#define PRCM_O_PDCTL1RFC 0x00000188
+
+// VIMS Mode Direct Control
+#define PRCM_O_PDCTL1VIMS 0x0000018C
+
+// Power Manager Status
+#define PRCM_O_PDSTAT1 0x00000194
+
+// BUS Power Domain Direct Read Status
+#define PRCM_O_PDSTAT1BUS 0x00000198
+
+// RFC Power Domain Direct Read Status
+#define PRCM_O_PDSTAT1RFC 0x0000019C
+
+// CPU Power Domain Direct Read Status
+#define PRCM_O_PDSTAT1CPU 0x000001A0
+
+// VIMS Mode Direct Read Status
+#define PRCM_O_PDSTAT1VIMS 0x000001A4
+
+// Control To RFC
+#define PRCM_O_RFCBITS 0x000001CC
+
+// Selected RFC Mode
+#define PRCM_O_RFCMODESEL 0x000001D0
+
+// Allowed RFC Modes
+#define PRCM_O_RFCMODEHWOPT 0x000001D4
+
+// Power Profiler Register
+#define PRCM_O_PWRPROFSTAT 0x000001E0
+
+// MCU SRAM configuration
+#define PRCM_O_MCUSRAMCFG 0x0000021C
+
+// Memory Retention Control
+#define PRCM_O_RAMRETEN 0x00000224
+
+// Oscillator Interrupt Mask
+#define PRCM_O_OSCIMSC 0x00000290
+
+// Oscillator Raw Interrupt Status
+#define PRCM_O_OSCRIS 0x00000294
+
+// Oscillator Raw Interrupt Clear
+#define PRCM_O_OSCICR 0x00000298
+
+//*****************************************************************************
+//
+// Register: PRCM_O_INFRCLKDIVR
+//
+//*****************************************************************************
+// Field: [1:0] RATIO
+//
+// Division rate for clocks driving modules in the MCU_AON domain when system
+// CPU is in run mode. Division ratio affects both infrastructure clock and
+// perbusull clock.
+// ENUMs:
+// DIV32 Divide by 32
+// DIV8 Divide by 8
+// DIV2 Divide by 2
+// DIV1 Divide by 1
+#define PRCM_INFRCLKDIVR_RATIO_W 2
+#define PRCM_INFRCLKDIVR_RATIO_M 0x00000003
+#define PRCM_INFRCLKDIVR_RATIO_S 0
+#define PRCM_INFRCLKDIVR_RATIO_DIV32 0x00000003
+#define PRCM_INFRCLKDIVR_RATIO_DIV8 0x00000002
+#define PRCM_INFRCLKDIVR_RATIO_DIV2 0x00000001
+#define PRCM_INFRCLKDIVR_RATIO_DIV1 0x00000000
+
+//*****************************************************************************
+//
+// Register: PRCM_O_INFRCLKDIVS
+//
+//*****************************************************************************
+// Field: [1:0] RATIO
+//
+// Division rate for clocks driving modules in the MCU_AON domain when system
+// CPU is in sleep mode. Division ratio affects both infrastructure clock and
+// perbusull clock.
+// ENUMs:
+// DIV32 Divide by 32
+// DIV8 Divide by 8
+// DIV2 Divide by 2
+// DIV1 Divide by 1
+#define PRCM_INFRCLKDIVS_RATIO_W 2
+#define PRCM_INFRCLKDIVS_RATIO_M 0x00000003
+#define PRCM_INFRCLKDIVS_RATIO_S 0
+#define PRCM_INFRCLKDIVS_RATIO_DIV32 0x00000003
+#define PRCM_INFRCLKDIVS_RATIO_DIV8 0x00000002
+#define PRCM_INFRCLKDIVS_RATIO_DIV2 0x00000001
+#define PRCM_INFRCLKDIVS_RATIO_DIV1 0x00000000
+
+//*****************************************************************************
+//
+// Register: PRCM_O_INFRCLKDIVDS
+//
+//*****************************************************************************
+// Field: [1:0] RATIO
+//
+// Division rate for clocks driving modules in the MCU_AON domain when system
+// CPU is in seepsleep mode. Division ratio affects both infrastructure clock
+// and perbusull clock.
+// ENUMs:
+// DIV32 Divide by 32
+// DIV8 Divide by 8
+// DIV2 Divide by 2
+// DIV1 Divide by 1
+#define PRCM_INFRCLKDIVDS_RATIO_W 2
+#define PRCM_INFRCLKDIVDS_RATIO_M 0x00000003
+#define PRCM_INFRCLKDIVDS_RATIO_S 0
+#define PRCM_INFRCLKDIVDS_RATIO_DIV32 0x00000003
+#define PRCM_INFRCLKDIVDS_RATIO_DIV8 0x00000002
+#define PRCM_INFRCLKDIVDS_RATIO_DIV2 0x00000001
+#define PRCM_INFRCLKDIVDS_RATIO_DIV1 0x00000000
+
+//*****************************************************************************
+//
+// Register: PRCM_O_VDCTL
+//
+//*****************************************************************************
+// Field: [0] ULDO
+//
+// Request PMCTL to switch to uLDO.
+//
+// 0: No request
+// 1: Assert request when possible
+//
+// The bit will have no effect before the following requirements are met:
+// 1. PDCTL1.CPU_ON = 0
+// 2. PDCTL1.VIMS_MODE = x0
+// 3. SECDMACLKGDS.DMA_CLK_EN = 0 and S.CRYPTO_CLK_EN] = 0 and
+// SECDMACLKGR.DMA_AM_CLK_EN = 0 (Note: Settings must be loaded with
+// CLKLOADCTL.LOAD)
+// 4. SECDMACLKGDS.CRYPTO_CLK_EN = 0 and SECDMACLKGR.CRYPTO_AM_CLK_EN = 0
+// (Note: Settings must be loaded with CLKLOADCTL.LOAD)
+// 5. I2SCLKGDS.CLK_EN = 0 and I2SCLKGR.AM_CLK_EN = 0 (Note: Settings must be
+// loaded with CLKLOADCTL.LOAD)
+// 6. RFC do no request access to BUS
+// 7. System CPU in deepsleep
+#define PRCM_VDCTL_ULDO 0x00000001
+#define PRCM_VDCTL_ULDO_BITN 0
+#define PRCM_VDCTL_ULDO_M 0x00000001
+#define PRCM_VDCTL_ULDO_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_CLKLOADCTL
+//
+//*****************************************************************************
+// Field: [1] LOAD_DONE
+//
+// Status of LOAD.
+// Will be cleared to 0 when any of the registers requiring a LOAD is written
+// to, and be set to 1 when a LOAD is done.
+// Note that writing no change to a register will result in the LOAD_DONE being
+// cleared.
+//
+// 0 : One or more registers have been write accessed after last LOAD
+// 1 : No registers are write accessed after last LOAD
+#define PRCM_CLKLOADCTL_LOAD_DONE 0x00000002
+#define PRCM_CLKLOADCTL_LOAD_DONE_BITN 1
+#define PRCM_CLKLOADCTL_LOAD_DONE_M 0x00000002
+#define PRCM_CLKLOADCTL_LOAD_DONE_S 1
+
+// Field: [0] LOAD
+//
+//
+// 0: No action
+// 1: Load settings to CLKCTRL. Bit is HW cleared.
+//
+// Multiple changes to settings may be done before LOAD is written once so all
+// changes takes place at the same time. LOAD can also be done after single
+// setting updates.
+//
+// Registers that needs to be followed by LOAD before settings being applied
+// are:
+// - SYSBUSCLKDIV
+// - CPUCLKDIV
+// - PERBUSCPUCLKDIV
+// - PERDMACLKDIV
+// - PERBUSCPUCLKG
+// - RFCCLKG
+// - VIMSCLKG
+// - SECDMACLKGR
+// - SECDMACLKGS
+// - SECDMACLKGDS
+// - GPIOCLKGR
+// - GPIOCLKGS
+// - GPIOCLKGDS
+// - GPTCLKGR
+// - GPTCLKGS
+// - GPTCLKGDS
+// - GPTCLKDIV
+// - I2CCLKGR
+// - I2CCLKGS
+// - I2CCLKGDS
+// - SSICLKGR
+// - SSICLKGS
+// - SSICLKGDS
+// - UARTCLKGR
+// - UARTCLKGS
+// - UARTCLKGDS
+// - I2SCLKGR
+// - I2SCLKGS
+// - I2SCLKGDS
+// - I2SBCLKSEL
+// - I2SCLKCTL
+// - I2SMCLKDIV
+// - I2SBCLKDIV
+// - I2SWCLKDIV
+#define PRCM_CLKLOADCTL_LOAD 0x00000001
+#define PRCM_CLKLOADCTL_LOAD_BITN 0
+#define PRCM_CLKLOADCTL_LOAD_M 0x00000001
+#define PRCM_CLKLOADCTL_LOAD_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_RFCCLKG
+//
+//*****************************************************************************
+// Field: [0] CLK_EN
+//
+//
+// 0: Disable Clock
+// 1: Enable clock if RFC power domain is on
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+#define PRCM_RFCCLKG_CLK_EN 0x00000001
+#define PRCM_RFCCLKG_CLK_EN_BITN 0
+#define PRCM_RFCCLKG_CLK_EN_M 0x00000001
+#define PRCM_RFCCLKG_CLK_EN_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_VIMSCLKG
+//
+//*****************************************************************************
+// Field: [1:0] CLK_EN
+//
+// 00: Disable clock
+// 01: Disable clock when SYSBUS clock is disabled
+// 11: Enable clock
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+#define PRCM_VIMSCLKG_CLK_EN_W 2
+#define PRCM_VIMSCLKG_CLK_EN_M 0x00000003
+#define PRCM_VIMSCLKG_CLK_EN_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_SECDMACLKGR
+//
+//*****************************************************************************
+// Field: [24] DMA_AM_CLK_EN
+//
+//
+// 0: No force
+// 1: Force clock on for all modes (Run, Sleep and Deep Sleep)
+//
+// Overrides DMA_CLK_EN, SECDMACLKGS.DMA_CLK_EN and SECDMACLKGDS.DMA_CLK_EN
+// when enabled.
+//
+// SYSBUS clock will always run when enabled
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+#define PRCM_SECDMACLKGR_DMA_AM_CLK_EN 0x01000000
+#define PRCM_SECDMACLKGR_DMA_AM_CLK_EN_BITN 24
+#define PRCM_SECDMACLKGR_DMA_AM_CLK_EN_M 0x01000000
+#define PRCM_SECDMACLKGR_DMA_AM_CLK_EN_S 24
+
+// Field: [19] PKA_ZERIOZE_RESET_N
+//
+// Zeroization logic hardware reset.
+//
+// 0: pka_zeroize logic inactive.
+// 1: pka_zeroize of memory is enabled.
+//
+// This register must remain active until the memory are completely zeroized
+// which requires 256 periods on systembus clock.
+#define PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N 0x00080000
+#define PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N_BITN 19
+#define PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N_M 0x00080000
+#define PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N_S 19
+
+// Field: [18] PKA_AM_CLK_EN
+//
+//
+// 0: No force
+// 1: Force clock on for all modes (Run, Sleep and Deep Sleep)
+//
+// Overrides PKA_CLK_EN, SECDMACLKGS.PKA_CLK_EN and SECDMACLKGDS.PKA_CLK_EN
+// when enabled.
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+#define PRCM_SECDMACLKGR_PKA_AM_CLK_EN 0x00040000
+#define PRCM_SECDMACLKGR_PKA_AM_CLK_EN_BITN 18
+#define PRCM_SECDMACLKGR_PKA_AM_CLK_EN_M 0x00040000
+#define PRCM_SECDMACLKGR_PKA_AM_CLK_EN_S 18
+
+// Field: [17] TRNG_AM_CLK_EN
+//
+//
+// 0: No force
+// 1: Force clock on for all modes (Run, Sleep and Deep Sleep)
+//
+// Overrides TRNG_CLK_EN, SECDMACLKGS.TRNG_CLK_EN and SECDMACLKGDS.TRNG_CLK_EN
+// when enabled.
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+#define PRCM_SECDMACLKGR_TRNG_AM_CLK_EN 0x00020000
+#define PRCM_SECDMACLKGR_TRNG_AM_CLK_EN_BITN 17
+#define PRCM_SECDMACLKGR_TRNG_AM_CLK_EN_M 0x00020000
+#define PRCM_SECDMACLKGR_TRNG_AM_CLK_EN_S 17
+
+// Field: [16] CRYPTO_AM_CLK_EN
+//
+//
+// 0: No force
+// 1: Force clock on for all modes (Run, Sleep and Deep Sleep)
+//
+// Overrides CRYPTO_CLK_EN, SECDMACLKGS.CRYPTO_CLK_EN and
+// SECDMACLKGDS.CRYPTO_CLK_EN when enabled.
+//
+// SYSBUS clock will always run when enabled
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+#define PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN 0x00010000
+#define PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN_BITN 16
+#define PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN_M 0x00010000
+#define PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN_S 16
+
+// Field: [8] DMA_CLK_EN
+//
+//
+// 0: Disable clock
+// 1: Enable clock
+//
+// Can be forced on by DMA_AM_CLK_EN
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+#define PRCM_SECDMACLKGR_DMA_CLK_EN 0x00000100
+#define PRCM_SECDMACLKGR_DMA_CLK_EN_BITN 8
+#define PRCM_SECDMACLKGR_DMA_CLK_EN_M 0x00000100
+#define PRCM_SECDMACLKGR_DMA_CLK_EN_S 8
+
+// Field: [2] PKA_CLK_EN
+//
+//
+// 0: Disable clock
+// 1: Enable clock
+//
+// Can be forced on by PKA_AM_CLK_EN
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+#define PRCM_SECDMACLKGR_PKA_CLK_EN 0x00000004
+#define PRCM_SECDMACLKGR_PKA_CLK_EN_BITN 2
+#define PRCM_SECDMACLKGR_PKA_CLK_EN_M 0x00000004
+#define PRCM_SECDMACLKGR_PKA_CLK_EN_S 2
+
+// Field: [1] TRNG_CLK_EN
+//
+//
+// 0: Disable clock
+// 1: Enable clock
+//
+// Can be forced on by TRNG_AM_CLK_EN
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+#define PRCM_SECDMACLKGR_TRNG_CLK_EN 0x00000002
+#define PRCM_SECDMACLKGR_TRNG_CLK_EN_BITN 1
+#define PRCM_SECDMACLKGR_TRNG_CLK_EN_M 0x00000002
+#define PRCM_SECDMACLKGR_TRNG_CLK_EN_S 1
+
+// Field: [0] CRYPTO_CLK_EN
+//
+//
+// 0: Disable clock
+// 1: Enable clock
+//
+// Can be forced on by CRYPTO_AM_CLK_EN
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN 0x00000001
+#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_BITN 0
+#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_M 0x00000001
+#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_SECDMACLKGS
+//
+//*****************************************************************************
+// Field: [8] DMA_CLK_EN
+//
+//
+// 0: Disable clock
+// 1: Enable clock
+//
+// Can be forced on by SECDMACLKGR.DMA_AM_CLK_EN
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+#define PRCM_SECDMACLKGS_DMA_CLK_EN 0x00000100
+#define PRCM_SECDMACLKGS_DMA_CLK_EN_BITN 8
+#define PRCM_SECDMACLKGS_DMA_CLK_EN_M 0x00000100
+#define PRCM_SECDMACLKGS_DMA_CLK_EN_S 8
+
+// Field: [2] PKA_CLK_EN
+//
+//
+// 0: Disable clock
+// 1: Enable clock
+//
+// Can be forced on by SECDMACLKGR.PKA_AM_CLK_EN
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+#define PRCM_SECDMACLKGS_PKA_CLK_EN 0x00000004
+#define PRCM_SECDMACLKGS_PKA_CLK_EN_BITN 2
+#define PRCM_SECDMACLKGS_PKA_CLK_EN_M 0x00000004
+#define PRCM_SECDMACLKGS_PKA_CLK_EN_S 2
+
+// Field: [1] TRNG_CLK_EN
+//
+//
+// 0: Disable clock
+// 1: Enable clock
+//
+// Can be forced on by SECDMACLKGR.TRNG_AM_CLK_EN
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+#define PRCM_SECDMACLKGS_TRNG_CLK_EN 0x00000002
+#define PRCM_SECDMACLKGS_TRNG_CLK_EN_BITN 1
+#define PRCM_SECDMACLKGS_TRNG_CLK_EN_M 0x00000002
+#define PRCM_SECDMACLKGS_TRNG_CLK_EN_S 1
+
+// Field: [0] CRYPTO_CLK_EN
+//
+//
+// 0: Disable clock
+// 1: Enable clock
+//
+// Can be forced on by SECDMACLKGR.CRYPTO_AM_CLK_EN
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN 0x00000001
+#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_BITN 0
+#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_M 0x00000001
+#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_SECDMACLKGDS
+//
+//*****************************************************************************
+// Field: [8] DMA_CLK_EN
+//
+//
+// 0: Disable clock
+// 1: Enable clock
+//
+// Can be forced on by SECDMACLKGR.DMA_AM_CLK_EN
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+#define PRCM_SECDMACLKGDS_DMA_CLK_EN 0x00000100
+#define PRCM_SECDMACLKGDS_DMA_CLK_EN_BITN 8
+#define PRCM_SECDMACLKGDS_DMA_CLK_EN_M 0x00000100
+#define PRCM_SECDMACLKGDS_DMA_CLK_EN_S 8
+
+// Field: [2] PKA_CLK_EN
+//
+//
+// 0: Disable clock
+// 1: Enable clock
+//
+// Can be forced on by SECDMACLKGR.PKA_AM_CLK_EN
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+#define PRCM_SECDMACLKGDS_PKA_CLK_EN 0x00000004
+#define PRCM_SECDMACLKGDS_PKA_CLK_EN_BITN 2
+#define PRCM_SECDMACLKGDS_PKA_CLK_EN_M 0x00000004
+#define PRCM_SECDMACLKGDS_PKA_CLK_EN_S 2
+
+// Field: [1] TRNG_CLK_EN
+//
+//
+// 0: Disable clock
+// 1: Enable clock
+//
+// SYSBUS clock will always run when enabled
+//
+// Can be forced on by SECDMACLKGR.TRNG_AM_CLK_EN
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+#define PRCM_SECDMACLKGDS_TRNG_CLK_EN 0x00000002
+#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_BITN 1
+#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_M 0x00000002
+#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_S 1
+
+// Field: [0] CRYPTO_CLK_EN
+//
+//
+// 0: Disable clock
+// 1: Enable clock
+//
+// SYSBUS clock will always run when enabled
+//
+// Can be forced on by SECDMACLKGR.CRYPTO_AM_CLK_EN
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN 0x00000001
+#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_BITN 0
+#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_M 0x00000001
+#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_GPIOCLKGR
+//
+//*****************************************************************************
+// Field: [8] AM_CLK_EN
+//
+//
+// 0: No force
+// 1: Force clock on for all modes (Run, Sleep and Deep Sleep)
+//
+// Overrides CLK_EN, GPIOCLKGS.CLK_EN and GPIOCLKGDS.CLK_EN when enabled.
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+#define PRCM_GPIOCLKGR_AM_CLK_EN 0x00000100
+#define PRCM_GPIOCLKGR_AM_CLK_EN_BITN 8
+#define PRCM_GPIOCLKGR_AM_CLK_EN_M 0x00000100
+#define PRCM_GPIOCLKGR_AM_CLK_EN_S 8
+
+// Field: [0] CLK_EN
+//
+//
+// 0: Disable clock
+// 1: Enable clock
+//
+// Can be forced on by AM_CLK_EN
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+#define PRCM_GPIOCLKGR_CLK_EN 0x00000001
+#define PRCM_GPIOCLKGR_CLK_EN_BITN 0
+#define PRCM_GPIOCLKGR_CLK_EN_M 0x00000001
+#define PRCM_GPIOCLKGR_CLK_EN_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_GPIOCLKGS
+//
+//*****************************************************************************
+// Field: [0] CLK_EN
+//
+//
+// 0: Disable clock
+// 1: Enable clock
+//
+// Can be forced on by GPIOCLKGR.AM_CLK_EN
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+#define PRCM_GPIOCLKGS_CLK_EN 0x00000001
+#define PRCM_GPIOCLKGS_CLK_EN_BITN 0
+#define PRCM_GPIOCLKGS_CLK_EN_M 0x00000001
+#define PRCM_GPIOCLKGS_CLK_EN_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_GPIOCLKGDS
+//
+//*****************************************************************************
+// Field: [0] CLK_EN
+//
+//
+// 0: Disable clock
+// 1: Enable clock
+//
+// Can be forced on by GPIOCLKGR.AM_CLK_EN
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+#define PRCM_GPIOCLKGDS_CLK_EN 0x00000001
+#define PRCM_GPIOCLKGDS_CLK_EN_BITN 0
+#define PRCM_GPIOCLKGDS_CLK_EN_M 0x00000001
+#define PRCM_GPIOCLKGDS_CLK_EN_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_GPTCLKGR
+//
+//*****************************************************************************
+// Field: [11:8] AM_CLK_EN
+//
+// Each bit below has the following meaning:
+//
+// 0: No force
+// 1: Force clock on for all modes (Run, Sleep and Deep Sleep)
+//
+// Overrides CLK_EN, GPTCLKGS.CLK_EN and GPTCLKGDS.CLK_EN when enabled.
+//
+// ENUMs can be combined
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+// ENUMs:
+// AM_GPT3 Enable clock for GPT3 in all modes
+// AM_GPT2 Enable clock for GPT2 in all modes
+// AM_GPT1 Enable clock for GPT1 in all modes
+// AM_GPT0 Enable clock for GPT0 in all modes
+#define PRCM_GPTCLKGR_AM_CLK_EN_W 4
+#define PRCM_GPTCLKGR_AM_CLK_EN_M 0x00000F00
+#define PRCM_GPTCLKGR_AM_CLK_EN_S 8
+#define PRCM_GPTCLKGR_AM_CLK_EN_AM_GPT3 0x00000800
+#define PRCM_GPTCLKGR_AM_CLK_EN_AM_GPT2 0x00000400
+#define PRCM_GPTCLKGR_AM_CLK_EN_AM_GPT1 0x00000200
+#define PRCM_GPTCLKGR_AM_CLK_EN_AM_GPT0 0x00000100
+
+// Field: [3:0] CLK_EN
+//
+// Each bit below has the following meaning:
+//
+// 0: Disable clock
+// 1: Enable clock
+//
+// Can be forced on by AM_CLK_EN
+//
+// ENUMs can be combined
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+// ENUMs:
+// GPT3 Enable clock for GPT3
+// GPT2 Enable clock for GPT2
+// GPT1 Enable clock for GPT1
+// GPT0 Enable clock for GPT0
+#define PRCM_GPTCLKGR_CLK_EN_W 4
+#define PRCM_GPTCLKGR_CLK_EN_M 0x0000000F
+#define PRCM_GPTCLKGR_CLK_EN_S 0
+#define PRCM_GPTCLKGR_CLK_EN_GPT3 0x00000008
+#define PRCM_GPTCLKGR_CLK_EN_GPT2 0x00000004
+#define PRCM_GPTCLKGR_CLK_EN_GPT1 0x00000002
+#define PRCM_GPTCLKGR_CLK_EN_GPT0 0x00000001
+
+//*****************************************************************************
+//
+// Register: PRCM_O_GPTCLKGS
+//
+//*****************************************************************************
+// Field: [3:0] CLK_EN
+//
+// Each bit below has the following meaning:
+//
+// 0: Disable clock
+// 1: Enable clock
+//
+// Can be forced on by GPTCLKGR.AM_CLK_EN
+//
+// ENUMs can be combined
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+// ENUMs:
+// GPT3 Enable clock for GPT3
+// GPT2 Enable clock for GPT2
+// GPT1 Enable clock for GPT1
+// GPT0 Enable clock for GPT0
+#define PRCM_GPTCLKGS_CLK_EN_W 4
+#define PRCM_GPTCLKGS_CLK_EN_M 0x0000000F
+#define PRCM_GPTCLKGS_CLK_EN_S 0
+#define PRCM_GPTCLKGS_CLK_EN_GPT3 0x00000008
+#define PRCM_GPTCLKGS_CLK_EN_GPT2 0x00000004
+#define PRCM_GPTCLKGS_CLK_EN_GPT1 0x00000002
+#define PRCM_GPTCLKGS_CLK_EN_GPT0 0x00000001
+
+//*****************************************************************************
+//
+// Register: PRCM_O_GPTCLKGDS
+//
+//*****************************************************************************
+// Field: [3:0] CLK_EN
+//
+// Each bit below has the following meaning:
+//
+// 0: Disable clock
+// 1: Enable clock
+//
+// Can be forced on by GPTCLKGR.AM_CLK_EN
+//
+// ENUMs can be combined
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+// ENUMs:
+// GPT3 Enable clock for GPT3
+// GPT2 Enable clock for GPT2
+// GPT1 Enable clock for GPT1
+// GPT0 Enable clock for GPT0
+#define PRCM_GPTCLKGDS_CLK_EN_W 4
+#define PRCM_GPTCLKGDS_CLK_EN_M 0x0000000F
+#define PRCM_GPTCLKGDS_CLK_EN_S 0
+#define PRCM_GPTCLKGDS_CLK_EN_GPT3 0x00000008
+#define PRCM_GPTCLKGDS_CLK_EN_GPT2 0x00000004
+#define PRCM_GPTCLKGDS_CLK_EN_GPT1 0x00000002
+#define PRCM_GPTCLKGDS_CLK_EN_GPT0 0x00000001
+
+//*****************************************************************************
+//
+// Register: PRCM_O_I2CCLKGR
+//
+//*****************************************************************************
+// Field: [8] AM_CLK_EN
+//
+//
+// 0: No force
+// 1: Force clock on for all modes (Run, Sleep and Deep Sleep)
+//
+// Overrides CLK_EN, I2CCLKGS.CLK_EN and I2CCLKGDS.CLK_EN when enabled.
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+#define PRCM_I2CCLKGR_AM_CLK_EN 0x00000100
+#define PRCM_I2CCLKGR_AM_CLK_EN_BITN 8
+#define PRCM_I2CCLKGR_AM_CLK_EN_M 0x00000100
+#define PRCM_I2CCLKGR_AM_CLK_EN_S 8
+
+// Field: [0] CLK_EN
+//
+//
+// 0: Disable clock
+// 1: Enable clock
+//
+// Can be forced on by AM_CLK_EN
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+#define PRCM_I2CCLKGR_CLK_EN 0x00000001
+#define PRCM_I2CCLKGR_CLK_EN_BITN 0
+#define PRCM_I2CCLKGR_CLK_EN_M 0x00000001
+#define PRCM_I2CCLKGR_CLK_EN_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_I2CCLKGS
+//
+//*****************************************************************************
+// Field: [0] CLK_EN
+//
+//
+// 0: Disable clock
+// 1: Enable clock
+//
+// Can be forced on by I2CCLKGR.AM_CLK_EN
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+#define PRCM_I2CCLKGS_CLK_EN 0x00000001
+#define PRCM_I2CCLKGS_CLK_EN_BITN 0
+#define PRCM_I2CCLKGS_CLK_EN_M 0x00000001
+#define PRCM_I2CCLKGS_CLK_EN_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_I2CCLKGDS
+//
+//*****************************************************************************
+// Field: [0] CLK_EN
+//
+//
+// 0: Disable clock
+// 1: Enable clock
+//
+// Can be forced on by I2CCLKGR.AM_CLK_EN
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+#define PRCM_I2CCLKGDS_CLK_EN 0x00000001
+#define PRCM_I2CCLKGDS_CLK_EN_BITN 0
+#define PRCM_I2CCLKGDS_CLK_EN_M 0x00000001
+#define PRCM_I2CCLKGDS_CLK_EN_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_UARTCLKGR
+//
+//*****************************************************************************
+// Field: [9:8] AM_CLK_EN
+//
+//
+// 0: No force
+// 1: Force clock on for all modes (Run, Sleep and Deep Sleep)
+//
+// Overrides CLK_EN, UARTCLKGS.CLK_EN and UARTCLKGDS.CLK_EN when enabled.
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+// ENUMs:
+// AM_UART1 Enable clock for UART1
+// AM_UART0 Enable clock for UART0
+#define PRCM_UARTCLKGR_AM_CLK_EN_W 2
+#define PRCM_UARTCLKGR_AM_CLK_EN_M 0x00000300
+#define PRCM_UARTCLKGR_AM_CLK_EN_S 8
+#define PRCM_UARTCLKGR_AM_CLK_EN_AM_UART1 0x00000200
+#define PRCM_UARTCLKGR_AM_CLK_EN_AM_UART0 0x00000100
+
+// Field: [1:0] CLK_EN
+//
+//
+// 0: Disable clock
+// 1: Enable clock
+//
+// Can be forced on by AM_CLK_EN
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+// ENUMs:
+// UART1 Enable clock for UART1
+// UART0 Enable clock for UART0
+#define PRCM_UARTCLKGR_CLK_EN_W 2
+#define PRCM_UARTCLKGR_CLK_EN_M 0x00000003
+#define PRCM_UARTCLKGR_CLK_EN_S 0
+#define PRCM_UARTCLKGR_CLK_EN_UART1 0x00000002
+#define PRCM_UARTCLKGR_CLK_EN_UART0 0x00000001
+
+//*****************************************************************************
+//
+// Register: PRCM_O_UARTCLKGS
+//
+//*****************************************************************************
+// Field: [1:0] CLK_EN
+//
+//
+// 0: Disable clock
+// 1: Enable clock
+//
+// Can be forced on by UARTCLKGR.AM_CLK_EN
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+// ENUMs:
+// AM_UART1 Enable clock for UART1
+// AM_UART0 Enable clock for UART0
+#define PRCM_UARTCLKGS_CLK_EN_W 2
+#define PRCM_UARTCLKGS_CLK_EN_M 0x00000003
+#define PRCM_UARTCLKGS_CLK_EN_S 0
+#define PRCM_UARTCLKGS_CLK_EN_AM_UART1 0x00000002
+#define PRCM_UARTCLKGS_CLK_EN_AM_UART0 0x00000001
+
+//*****************************************************************************
+//
+// Register: PRCM_O_UARTCLKGDS
+//
+//*****************************************************************************
+// Field: [1:0] CLK_EN
+//
+//
+// 0: Disable clock
+// 1: Enable clock
+//
+// Can be forced on by UARTCLKGR.AM_CLK_EN
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+// ENUMs:
+// AM_UART1 Enable clock for UART1
+// AM_UART0 Enable clock for UART0
+#define PRCM_UARTCLKGDS_CLK_EN_W 2
+#define PRCM_UARTCLKGDS_CLK_EN_M 0x00000003
+#define PRCM_UARTCLKGDS_CLK_EN_S 0
+#define PRCM_UARTCLKGDS_CLK_EN_AM_UART1 0x00000002
+#define PRCM_UARTCLKGDS_CLK_EN_AM_UART0 0x00000001
+
+//*****************************************************************************
+//
+// Register: PRCM_O_SSICLKGR
+//
+//*****************************************************************************
+// Field: [9:8] AM_CLK_EN
+//
+//
+// 0: No force
+// 1: Force clock on for all modes (Run, Sleep and Deep Sleep)
+//
+// Overrides CLK_EN, SSICLKGS.CLK_EN and SSICLKGDS.CLK_EN when enabled.
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+// ENUMs:
+// SSI1 Enable clock for SSI1
+// SSI0 Enable clock for SSI0
+#define PRCM_SSICLKGR_AM_CLK_EN_W 2
+#define PRCM_SSICLKGR_AM_CLK_EN_M 0x00000300
+#define PRCM_SSICLKGR_AM_CLK_EN_S 8
+#define PRCM_SSICLKGR_AM_CLK_EN_SSI1 0x00000200
+#define PRCM_SSICLKGR_AM_CLK_EN_SSI0 0x00000100
+
+// Field: [1:0] CLK_EN
+//
+//
+// 0: Disable clock
+// 1: Enable clock
+//
+// Can be forced on by AM_CLK_EN
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+// ENUMs:
+// SSI1 Enable clock for SSI1
+// SSI0 Enable clock for SSI0
+#define PRCM_SSICLKGR_CLK_EN_W 2
+#define PRCM_SSICLKGR_CLK_EN_M 0x00000003
+#define PRCM_SSICLKGR_CLK_EN_S 0
+#define PRCM_SSICLKGR_CLK_EN_SSI1 0x00000002
+#define PRCM_SSICLKGR_CLK_EN_SSI0 0x00000001
+
+//*****************************************************************************
+//
+// Register: PRCM_O_SSICLKGS
+//
+//*****************************************************************************
+// Field: [1:0] CLK_EN
+//
+//
+// 0: Disable clock
+// 1: Enable clock
+//
+// Can be forced on by SSICLKGR.AM_CLK_EN
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+// ENUMs:
+// SSI1 Enable clock for SSI1
+// SSI0 Enable clock for SSI0
+#define PRCM_SSICLKGS_CLK_EN_W 2
+#define PRCM_SSICLKGS_CLK_EN_M 0x00000003
+#define PRCM_SSICLKGS_CLK_EN_S 0
+#define PRCM_SSICLKGS_CLK_EN_SSI1 0x00000002
+#define PRCM_SSICLKGS_CLK_EN_SSI0 0x00000001
+
+//*****************************************************************************
+//
+// Register: PRCM_O_SSICLKGDS
+//
+//*****************************************************************************
+// Field: [1:0] CLK_EN
+//
+//
+// 0: Disable clock
+// 1: Enable clock
+//
+// Can be forced on by SSICLKGR.AM_CLK_EN
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+// ENUMs:
+// SSI1 Enable clock for SSI1
+// SSI0 Enable clock for SSI0
+#define PRCM_SSICLKGDS_CLK_EN_W 2
+#define PRCM_SSICLKGDS_CLK_EN_M 0x00000003
+#define PRCM_SSICLKGDS_CLK_EN_S 0
+#define PRCM_SSICLKGDS_CLK_EN_SSI1 0x00000002
+#define PRCM_SSICLKGDS_CLK_EN_SSI0 0x00000001
+
+//*****************************************************************************
+//
+// Register: PRCM_O_I2SCLKGR
+//
+//*****************************************************************************
+// Field: [8] AM_CLK_EN
+//
+//
+// 0: No force
+// 1: Force clock on for all modes (Run, Sleep and Deep Sleep)
+//
+// Overrides CLK_EN, I2SCLKGS.CLK_EN and I2SCLKGDS.CLK_EN when enabled.
+// SYSBUS clock will always run when enabled
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+#define PRCM_I2SCLKGR_AM_CLK_EN 0x00000100
+#define PRCM_I2SCLKGR_AM_CLK_EN_BITN 8
+#define PRCM_I2SCLKGR_AM_CLK_EN_M 0x00000100
+#define PRCM_I2SCLKGR_AM_CLK_EN_S 8
+
+// Field: [0] CLK_EN
+//
+//
+// 0: Disable clock
+// 1: Enable clock
+//
+// Can be forced on by AM_CLK_EN
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+#define PRCM_I2SCLKGR_CLK_EN 0x00000001
+#define PRCM_I2SCLKGR_CLK_EN_BITN 0
+#define PRCM_I2SCLKGR_CLK_EN_M 0x00000001
+#define PRCM_I2SCLKGR_CLK_EN_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_I2SCLKGS
+//
+//*****************************************************************************
+// Field: [0] CLK_EN
+//
+//
+// 0: Disable clock
+// 1: Enable clock
+//
+// Can be forced on by I2SCLKGR.AM_CLK_EN
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+#define PRCM_I2SCLKGS_CLK_EN 0x00000001
+#define PRCM_I2SCLKGS_CLK_EN_BITN 0
+#define PRCM_I2SCLKGS_CLK_EN_M 0x00000001
+#define PRCM_I2SCLKGS_CLK_EN_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_I2SCLKGDS
+//
+//*****************************************************************************
+// Field: [0] CLK_EN
+//
+//
+// 0: Disable clock
+// 1: Enable clock
+//
+// SYSBUS clock will always run when enabled
+//
+// Can be forced on by I2SCLKGR.AM_CLK_EN
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+#define PRCM_I2SCLKGDS_CLK_EN 0x00000001
+#define PRCM_I2SCLKGDS_CLK_EN_BITN 0
+#define PRCM_I2SCLKGDS_CLK_EN_M 0x00000001
+#define PRCM_I2SCLKGDS_CLK_EN_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_SYSBUSCLKDIV
+//
+//*****************************************************************************
+// Field: [2:0] RATIO
+//
+// Internal. Only to be used through TI provided API.
+// ENUMs:
+// DIV2 Internal. Only to be used through TI provided API.
+// DIV1 Internal. Only to be used through TI provided API.
+#define PRCM_SYSBUSCLKDIV_RATIO_W 3
+#define PRCM_SYSBUSCLKDIV_RATIO_M 0x00000007
+#define PRCM_SYSBUSCLKDIV_RATIO_S 0
+#define PRCM_SYSBUSCLKDIV_RATIO_DIV2 0x00000001
+#define PRCM_SYSBUSCLKDIV_RATIO_DIV1 0x00000000
+
+//*****************************************************************************
+//
+// Register: PRCM_O_CPUCLKDIV
+//
+//*****************************************************************************
+// Field: [0] RATIO
+//
+// Internal. Only to be used through TI provided API.
+// ENUMs:
+// DIV2 Internal. Only to be used through TI provided API.
+// DIV1 Internal. Only to be used through TI provided API.
+#define PRCM_CPUCLKDIV_RATIO 0x00000001
+#define PRCM_CPUCLKDIV_RATIO_BITN 0
+#define PRCM_CPUCLKDIV_RATIO_M 0x00000001
+#define PRCM_CPUCLKDIV_RATIO_S 0
+#define PRCM_CPUCLKDIV_RATIO_DIV2 0x00000001
+#define PRCM_CPUCLKDIV_RATIO_DIV1 0x00000000
+
+//*****************************************************************************
+//
+// Register: PRCM_O_PERBUSCPUCLKDIV
+//
+//*****************************************************************************
+// Field: [3:0] RATIO
+//
+// Internal. Only to be used through TI provided API.
+// ENUMs:
+// DIV256 Internal. Only to be used through TI provided API.
+// DIV128 Internal. Only to be used through TI provided API.
+// DIV64 Internal. Only to be used through TI provided API.
+// DIV32 Internal. Only to be used through TI provided API.
+// DIV16 Internal. Only to be used through TI provided API.
+// DIV8 Internal. Only to be used through TI provided API.
+// DIV4 Internal. Only to be used through TI provided API.
+// DIV2 Internal. Only to be used through TI provided API.
+// DIV1 Internal. Only to be used through TI provided API.
+#define PRCM_PERBUSCPUCLKDIV_RATIO_W 4
+#define PRCM_PERBUSCPUCLKDIV_RATIO_M 0x0000000F
+#define PRCM_PERBUSCPUCLKDIV_RATIO_S 0
+#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV256 0x00000008
+#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV128 0x00000007
+#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV64 0x00000006
+#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV32 0x00000005
+#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV16 0x00000004
+#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV8 0x00000003
+#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV4 0x00000002
+#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV2 0x00000001
+#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV1 0x00000000
+
+//*****************************************************************************
+//
+// Register: PRCM_O_PERDMACLKDIV
+//
+//*****************************************************************************
+// Field: [3:0] RATIO
+//
+// Internal. Only to be used through TI provided API.
+// ENUMs:
+// DIV256 Internal. Only to be used through TI provided API.
+// DIV128 Internal. Only to be used through TI provided API.
+// DIV64 Internal. Only to be used through TI provided API.
+// DIV32 Internal. Only to be used through TI provided API.
+// DIV16 Internal. Only to be used through TI provided API.
+// DIV8 Internal. Only to be used through TI provided API.
+// DIV4 Internal. Only to be used through TI provided API.
+// DIV2 Internal. Only to be used through TI provided API.
+// DIV1 Internal. Only to be used through TI provided API.
+#define PRCM_PERDMACLKDIV_RATIO_W 4
+#define PRCM_PERDMACLKDIV_RATIO_M 0x0000000F
+#define PRCM_PERDMACLKDIV_RATIO_S 0
+#define PRCM_PERDMACLKDIV_RATIO_DIV256 0x00000008
+#define PRCM_PERDMACLKDIV_RATIO_DIV128 0x00000007
+#define PRCM_PERDMACLKDIV_RATIO_DIV64 0x00000006
+#define PRCM_PERDMACLKDIV_RATIO_DIV32 0x00000005
+#define PRCM_PERDMACLKDIV_RATIO_DIV16 0x00000004
+#define PRCM_PERDMACLKDIV_RATIO_DIV8 0x00000003
+#define PRCM_PERDMACLKDIV_RATIO_DIV4 0x00000002
+#define PRCM_PERDMACLKDIV_RATIO_DIV2 0x00000001
+#define PRCM_PERDMACLKDIV_RATIO_DIV1 0x00000000
+
+//*****************************************************************************
+//
+// Register: PRCM_O_I2SBCLKSEL
+//
+//*****************************************************************************
+// Field: [0] SRC
+//
+// BCLK source selector
+//
+// 0: Use external BCLK
+// 1: Use internally generated clock
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+#define PRCM_I2SBCLKSEL_SRC 0x00000001
+#define PRCM_I2SBCLKSEL_SRC_BITN 0
+#define PRCM_I2SBCLKSEL_SRC_M 0x00000001
+#define PRCM_I2SBCLKSEL_SRC_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_GPTCLKDIV
+//
+//*****************************************************************************
+// Field: [3:0] RATIO
+//
+// Scalar used for GPTs. The division rate will be constant and ungated for Run
+// / Sleep / DeepSleep mode. For changes to take effect, CLKLOADCTL.LOAD
+// needs to be written Other values are not supported.
+// ENUMs:
+// DIV256 Divide by 256
+// DIV128 Divide by 128
+// DIV64 Divide by 64
+// DIV32 Divide by 32
+// DIV16 Divide by 16
+// DIV8 Divide by 8
+// DIV4 Divide by 4
+// DIV2 Divide by 2
+// DIV1 Divide by 1
+#define PRCM_GPTCLKDIV_RATIO_W 4
+#define PRCM_GPTCLKDIV_RATIO_M 0x0000000F
+#define PRCM_GPTCLKDIV_RATIO_S 0
+#define PRCM_GPTCLKDIV_RATIO_DIV256 0x00000008
+#define PRCM_GPTCLKDIV_RATIO_DIV128 0x00000007
+#define PRCM_GPTCLKDIV_RATIO_DIV64 0x00000006
+#define PRCM_GPTCLKDIV_RATIO_DIV32 0x00000005
+#define PRCM_GPTCLKDIV_RATIO_DIV16 0x00000004
+#define PRCM_GPTCLKDIV_RATIO_DIV8 0x00000003
+#define PRCM_GPTCLKDIV_RATIO_DIV4 0x00000002
+#define PRCM_GPTCLKDIV_RATIO_DIV2 0x00000001
+#define PRCM_GPTCLKDIV_RATIO_DIV1 0x00000000
+
+//*****************************************************************************
+//
+// Register: PRCM_O_I2SCLKCTL
+//
+//*****************************************************************************
+// Field: [3] SMPL_ON_POSEDGE
+//
+// On the I2S serial interface, data and WCLK is sampled and clocked out on
+// opposite edges of BCLK.
+//
+// 0 - data and WCLK are sampled on the negative edge and clocked out on the
+// positive edge.
+// 1 - data and WCLK are sampled on the positive edge and clocked out on the
+// negative edge.
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE 0x00000008
+#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_BITN 3
+#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M 0x00000008
+#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_S 3
+
+// Field: [2:1] WCLK_PHASE
+//
+// Decides how the WCLK division ratio is calculated and used to generate
+// different duty cycles (See I2SWCLKDIV.WDIV).
+//
+// 0: Single phase
+// 1: Dual phase
+// 2: User Defined
+// 3: Reserved/Undefined
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+#define PRCM_I2SCLKCTL_WCLK_PHASE_W 2
+#define PRCM_I2SCLKCTL_WCLK_PHASE_M 0x00000006
+#define PRCM_I2SCLKCTL_WCLK_PHASE_S 1
+
+// Field: [0] EN
+//
+//
+// 0: MCLK, BCLK and WCLK will be static low
+// 1: Enables the generation of MCLK, BCLK and WCLK
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+#define PRCM_I2SCLKCTL_EN 0x00000001
+#define PRCM_I2SCLKCTL_EN_BITN 0
+#define PRCM_I2SCLKCTL_EN_M 0x00000001
+#define PRCM_I2SCLKCTL_EN_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_I2SMCLKDIV
+//
+//*****************************************************************************
+// Field: [9:0] MDIV
+//
+// An unsigned factor of the division ratio used to generate MCLK [2-1024]:
+//
+// MCLK = MCUCLK/MDIV[Hz]
+// MCUCLK is 48MHz.
+//
+// A value of 0 is interpreted as 1024.
+// A value of 1 is invalid.
+// If MDIV is odd the low phase of the clock is one MCUCLK period longer than
+// the high phase.
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+#define PRCM_I2SMCLKDIV_MDIV_W 10
+#define PRCM_I2SMCLKDIV_MDIV_M 0x000003FF
+#define PRCM_I2SMCLKDIV_MDIV_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_I2SBCLKDIV
+//
+//*****************************************************************************
+// Field: [9:0] BDIV
+//
+// An unsigned factor of the division ratio used to generate I2S BCLK [2-1024]:
+//
+// BCLK = MCUCLK/BDIV[Hz]
+// MCUCLK is 48MHz.
+//
+// A value of 0 is interpreted as 1024.
+// A value of 1 is invalid.
+// If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 0, the low phase of the clock
+// is one MCUCLK period longer than the high phase.
+// If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 1 , the high phase of the
+// clock is one MCUCLK period longer than the low phase.
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+#define PRCM_I2SBCLKDIV_BDIV_W 10
+#define PRCM_I2SBCLKDIV_BDIV_M 0x000003FF
+#define PRCM_I2SBCLKDIV_BDIV_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_I2SWCLKDIV
+//
+//*****************************************************************************
+// Field: [15:0] WDIV
+//
+// If I2SCLKCTL.WCLK_PHASE = 0, Single phase.
+// WCLK is high one BCLK period and low WDIV[9:0] (unsigned, [1-1023]) BCLK
+// periods.
+//
+// WCLK = MCUCLK / BDIV*(WDIV[9:0] + 1) [Hz]
+// MCUCLK is 48MHz.
+//
+// If I2SCLKCTL.WCLK_PHASE = 1, Dual phase.
+// Each phase on WCLK (50% duty cycle) is WDIV[9:0] (unsigned, [1-1023]) BCLK
+// periods.
+//
+// WCLK = MCUCLK / BDIV*(2*WDIV[9:0]) [Hz]
+//
+// If I2SCLKCTL.WCLK_PHASE = 2, User defined.
+// WCLK is high WDIV[7:0] (unsigned, [1-255]) BCLK periods and low WDIV[15:8]
+// (unsigned, [1-255]) BCLK periods.
+//
+// WCLK = MCUCLK / (BDIV*(WDIV[7:0] + WDIV[15:8]) [Hz]
+//
+// For changes to take effect, CLKLOADCTL.LOAD needs to be written
+#define PRCM_I2SWCLKDIV_WDIV_W 16
+#define PRCM_I2SWCLKDIV_WDIV_M 0x0000FFFF
+#define PRCM_I2SWCLKDIV_WDIV_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_RESETSECDMA
+//
+//*****************************************************************************
+// Field: [8] DMA
+//
+// Write 1 to reset. HW cleared.
+// Acess will only have effect when PERIPH power domain is on,
+// PDSTAT0.PERIPH_ON = 1
+// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not
+// activated while executing from flash. This means one cannot execute from
+// flash when using the SW reset.
+#define PRCM_RESETSECDMA_DMA 0x00000100
+#define PRCM_RESETSECDMA_DMA_BITN 8
+#define PRCM_RESETSECDMA_DMA_M 0x00000100
+#define PRCM_RESETSECDMA_DMA_S 8
+
+// Field: [2] PKA
+//
+// Write 1 to reset. HW cleared.
+// Acess will only have effect when PERIPH power domain is on,
+// PDSTAT0.PERIPH_ON = 1
+// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not
+// activated while executing from flash. This means one cannot execute from
+// flash when using the SW reset.
+#define PRCM_RESETSECDMA_PKA 0x00000004
+#define PRCM_RESETSECDMA_PKA_BITN 2
+#define PRCM_RESETSECDMA_PKA_M 0x00000004
+#define PRCM_RESETSECDMA_PKA_S 2
+
+// Field: [1] TRNG
+//
+// Write 1 to reset. HW cleared.
+// Acess will only have effect when PERIPH power domain is on,
+// PDSTAT0.PERIPH_ON = 1
+// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not
+// activated while executing from flash. This means one cannot execute from
+// flash when using the SW reset.
+#define PRCM_RESETSECDMA_TRNG 0x00000002
+#define PRCM_RESETSECDMA_TRNG_BITN 1
+#define PRCM_RESETSECDMA_TRNG_M 0x00000002
+#define PRCM_RESETSECDMA_TRNG_S 1
+
+// Field: [0] CRYPTO
+//
+// Write 1 to reset. HW cleared.
+// Acess will only have effect when PERIPH power domain is on,
+// PDSTAT0.PERIPH_ON = 1
+// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not
+// activated while executing from flash. This means one cannot execute from
+// flash when using the SW reset.
+#define PRCM_RESETSECDMA_CRYPTO 0x00000001
+#define PRCM_RESETSECDMA_CRYPTO_BITN 0
+#define PRCM_RESETSECDMA_CRYPTO_M 0x00000001
+#define PRCM_RESETSECDMA_CRYPTO_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_RESETGPIO
+//
+//*****************************************************************************
+// Field: [0] GPIO
+//
+//
+// 0: No action
+// 1: Reset GPIO. HW cleared.
+//
+// Acess will only have effect when PERIPH power domain is on,
+// PDSTAT0.PERIPH_ON = 1
+// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not
+// activated while executing from flash. This means one cannot execute from
+// flash when using the SW reset.
+#define PRCM_RESETGPIO_GPIO 0x00000001
+#define PRCM_RESETGPIO_GPIO_BITN 0
+#define PRCM_RESETGPIO_GPIO_M 0x00000001
+#define PRCM_RESETGPIO_GPIO_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_RESETGPT
+//
+//*****************************************************************************
+// Field: [0] GPT
+//
+//
+// 0: No action
+// 1: Reset all GPTs. HW cleared.
+//
+// Acess will only have effect when PERIPH power domain is on,
+// PDSTAT0.PERIPH_ON = 1
+// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not
+// activated while executing from flash. This means one cannot execute from
+// flash when using the SW reset.
+#define PRCM_RESETGPT_GPT 0x00000001
+#define PRCM_RESETGPT_GPT_BITN 0
+#define PRCM_RESETGPT_GPT_M 0x00000001
+#define PRCM_RESETGPT_GPT_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_RESETI2C
+//
+//*****************************************************************************
+// Field: [0] I2C
+//
+//
+// 0: No action
+// 1: Reset I2C. HW cleared.
+//
+// Acess will only have effect when SERIAL power domain is on,
+// PDSTAT0.SERIAL_ON = 1
+// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not
+// activated while executing from flash. This means one cannot execute from
+// flash when using the SW reset.
+#define PRCM_RESETI2C_I2C 0x00000001
+#define PRCM_RESETI2C_I2C_BITN 0
+#define PRCM_RESETI2C_I2C_M 0x00000001
+#define PRCM_RESETI2C_I2C_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_RESETUART
+//
+//*****************************************************************************
+// Field: [1] UART1
+//
+//
+// 0: No action
+// 1: Reset UART1. HW cleared.
+//
+// Acess will only have effect when PERIPH power domain is on,
+// PDSTAT0.PERIPH_ON = 1
+// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not
+// activated while executing from flash. This means one cannot execute from
+// flash when using the SW reset.
+#define PRCM_RESETUART_UART1 0x00000002
+#define PRCM_RESETUART_UART1_BITN 1
+#define PRCM_RESETUART_UART1_M 0x00000002
+#define PRCM_RESETUART_UART1_S 1
+
+// Field: [0] UART0
+//
+//
+// 0: No action
+// 1: Reset UART0. HW cleared.
+//
+// Acess will only have effect when SERIAL power domain is on,
+// PDSTAT0.SERIAL_ON = 1
+// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not
+// activated while executing from flash. This means one cannot execute from
+// flash when using the SW reset.
+#define PRCM_RESETUART_UART0 0x00000001
+#define PRCM_RESETUART_UART0_BITN 0
+#define PRCM_RESETUART_UART0_M 0x00000001
+#define PRCM_RESETUART_UART0_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_RESETSSI
+//
+//*****************************************************************************
+// Field: [1:0] SSI
+//
+// SSI 0:
+//
+// 0: No action
+// 1: Reset SSI. HW cleared.
+//
+// Acess will only have effect when SERIAL power domain is on,
+// PDSTAT0.SERIAL_ON = 1
+// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not
+// activated while executing from flash. This means one cannot execute from
+// flash when using the SW reset.
+//
+// SSI 1:
+//
+// 0: No action
+// 1: Reset SSI. HW cleared.
+//
+// Acess will only have effect when PERIPH power domain is on,
+// PDSTAT0.PERIPH_ON = 1
+// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not
+// activated while executing from flash. This means one cannot execute from
+// flash when using the SW reset.
+#define PRCM_RESETSSI_SSI_W 2
+#define PRCM_RESETSSI_SSI_M 0x00000003
+#define PRCM_RESETSSI_SSI_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_RESETI2S
+//
+//*****************************************************************************
+// Field: [0] I2S
+//
+//
+// 0: No action
+// 1: Reset module. HW cleared.
+//
+// Acess will only have effect when PERIPH power domain is on,
+// PDSTAT0.PERIPH_ON = 1
+// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not
+// activated while executing from flash. This means one cannot execute from
+// flash when using the SW reset.
+#define PRCM_RESETI2S_I2S 0x00000001
+#define PRCM_RESETI2S_I2S_BITN 0
+#define PRCM_RESETI2S_I2S_M 0x00000001
+#define PRCM_RESETI2S_I2S_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_PDCTL0
+//
+//*****************************************************************************
+// Field: [2] PERIPH_ON
+//
+// PERIPH Power domain.
+//
+// 0: PERIPH power domain is powered down
+// 1: PERIPH power domain is powered up
+#define PRCM_PDCTL0_PERIPH_ON 0x00000004
+#define PRCM_PDCTL0_PERIPH_ON_BITN 2
+#define PRCM_PDCTL0_PERIPH_ON_M 0x00000004
+#define PRCM_PDCTL0_PERIPH_ON_S 2
+
+// Field: [1] SERIAL_ON
+//
+// SERIAL Power domain.
+//
+// 0: SERIAL power domain is powered down
+// 1: SERIAL power domain is powered up
+#define PRCM_PDCTL0_SERIAL_ON 0x00000002
+#define PRCM_PDCTL0_SERIAL_ON_BITN 1
+#define PRCM_PDCTL0_SERIAL_ON_M 0x00000002
+#define PRCM_PDCTL0_SERIAL_ON_S 1
+
+// Field: [0] RFC_ON
+//
+//
+// 0: RFC power domain powered off if also PDCTL1.RFC_ON = 0
+// 1: RFC power domain powered on
+#define PRCM_PDCTL0_RFC_ON 0x00000001
+#define PRCM_PDCTL0_RFC_ON_BITN 0
+#define PRCM_PDCTL0_RFC_ON_M 0x00000001
+#define PRCM_PDCTL0_RFC_ON_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_PDCTL0RFC
+//
+//*****************************************************************************
+// Field: [0] ON
+//
+// Alias for PDCTL0.RFC_ON
+#define PRCM_PDCTL0RFC_ON 0x00000001
+#define PRCM_PDCTL0RFC_ON_BITN 0
+#define PRCM_PDCTL0RFC_ON_M 0x00000001
+#define PRCM_PDCTL0RFC_ON_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_PDCTL0SERIAL
+//
+//*****************************************************************************
+// Field: [0] ON
+//
+// Alias for PDCTL0.SERIAL_ON
+#define PRCM_PDCTL0SERIAL_ON 0x00000001
+#define PRCM_PDCTL0SERIAL_ON_BITN 0
+#define PRCM_PDCTL0SERIAL_ON_M 0x00000001
+#define PRCM_PDCTL0SERIAL_ON_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_PDCTL0PERIPH
+//
+//*****************************************************************************
+// Field: [0] ON
+//
+// Alias for PDCTL0.PERIPH_ON
+#define PRCM_PDCTL0PERIPH_ON 0x00000001
+#define PRCM_PDCTL0PERIPH_ON_BITN 0
+#define PRCM_PDCTL0PERIPH_ON_M 0x00000001
+#define PRCM_PDCTL0PERIPH_ON_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_PDSTAT0
+//
+//*****************************************************************************
+// Field: [2] PERIPH_ON
+//
+// PERIPH Power domain.
+//
+// 0: Domain may be powered down
+// 1: Domain powered up (guaranteed)
+#define PRCM_PDSTAT0_PERIPH_ON 0x00000004
+#define PRCM_PDSTAT0_PERIPH_ON_BITN 2
+#define PRCM_PDSTAT0_PERIPH_ON_M 0x00000004
+#define PRCM_PDSTAT0_PERIPH_ON_S 2
+
+// Field: [1] SERIAL_ON
+//
+// SERIAL Power domain.
+//
+// 0: Domain may be powered down
+// 1: Domain powered up (guaranteed)
+#define PRCM_PDSTAT0_SERIAL_ON 0x00000002
+#define PRCM_PDSTAT0_SERIAL_ON_BITN 1
+#define PRCM_PDSTAT0_SERIAL_ON_M 0x00000002
+#define PRCM_PDSTAT0_SERIAL_ON_S 1
+
+// Field: [0] RFC_ON
+//
+// RFC Power domain
+//
+// 0: Domain may be powered down
+// 1: Domain powered up (guaranteed)
+#define PRCM_PDSTAT0_RFC_ON 0x00000001
+#define PRCM_PDSTAT0_RFC_ON_BITN 0
+#define PRCM_PDSTAT0_RFC_ON_M 0x00000001
+#define PRCM_PDSTAT0_RFC_ON_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_PDSTAT0RFC
+//
+//*****************************************************************************
+// Field: [0] ON
+//
+// Alias for PDSTAT0.RFC_ON
+#define PRCM_PDSTAT0RFC_ON 0x00000001
+#define PRCM_PDSTAT0RFC_ON_BITN 0
+#define PRCM_PDSTAT0RFC_ON_M 0x00000001
+#define PRCM_PDSTAT0RFC_ON_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_PDSTAT0SERIAL
+//
+//*****************************************************************************
+// Field: [0] ON
+//
+// Alias for PDSTAT0.SERIAL_ON
+#define PRCM_PDSTAT0SERIAL_ON 0x00000001
+#define PRCM_PDSTAT0SERIAL_ON_BITN 0
+#define PRCM_PDSTAT0SERIAL_ON_M 0x00000001
+#define PRCM_PDSTAT0SERIAL_ON_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_PDSTAT0PERIPH
+//
+//*****************************************************************************
+// Field: [0] ON
+//
+// Alias for PDSTAT0.PERIPH_ON
+#define PRCM_PDSTAT0PERIPH_ON 0x00000001
+#define PRCM_PDSTAT0PERIPH_ON_BITN 0
+#define PRCM_PDSTAT0PERIPH_ON_M 0x00000001
+#define PRCM_PDSTAT0PERIPH_ON_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_PDCTL1
+//
+//*****************************************************************************
+// Field: [4:3] VIMS_MODE
+//
+//
+// 00: VIMS power domain is only powered when CPU power domain is powered.
+// 01: VIMS power domain is powered whenever the BUS power domain is powered.
+// 1X: Block power up of VIMS power domain at next wake up. This mode only has
+// effect when VIMS power domain is not powered. Used for Autonomous RF Core.
+#define PRCM_PDCTL1_VIMS_MODE_W 2
+#define PRCM_PDCTL1_VIMS_MODE_M 0x00000018
+#define PRCM_PDCTL1_VIMS_MODE_S 3
+
+// Field: [2] RFC_ON
+//
+// 0: RFC power domain powered off if also PDCTL0.RFC_ON = 0 1: RFC power
+// domain powered on Bit shall be used by RFC in autonomous mode but there is
+// no HW restrictions fom system CPU to access the bit.
+#define PRCM_PDCTL1_RFC_ON 0x00000004
+#define PRCM_PDCTL1_RFC_ON_BITN 2
+#define PRCM_PDCTL1_RFC_ON_M 0x00000004
+#define PRCM_PDCTL1_RFC_ON_S 2
+
+// Field: [1] CPU_ON
+//
+//
+// 0: Causes a power down of the CPU power domain when system CPU indicates it
+// is idle.
+// 1: Initiates power-on of the CPU power domain.
+//
+// This bit is automatically set by a WIC power-on event.
+#define PRCM_PDCTL1_CPU_ON 0x00000002
+#define PRCM_PDCTL1_CPU_ON_BITN 1
+#define PRCM_PDCTL1_CPU_ON_M 0x00000002
+#define PRCM_PDCTL1_CPU_ON_S 1
+
+//*****************************************************************************
+//
+// Register: PRCM_O_PDCTL1CPU
+//
+//*****************************************************************************
+// Field: [0] ON
+//
+// This is an alias for PDCTL1.CPU_ON
+#define PRCM_PDCTL1CPU_ON 0x00000001
+#define PRCM_PDCTL1CPU_ON_BITN 0
+#define PRCM_PDCTL1CPU_ON_M 0x00000001
+#define PRCM_PDCTL1CPU_ON_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_PDCTL1RFC
+//
+//*****************************************************************************
+// Field: [0] ON
+//
+// This is an alias for PDCTL1.RFC_ON
+#define PRCM_PDCTL1RFC_ON 0x00000001
+#define PRCM_PDCTL1RFC_ON_BITN 0
+#define PRCM_PDCTL1RFC_ON_M 0x00000001
+#define PRCM_PDCTL1RFC_ON_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_PDCTL1VIMS
+//
+//*****************************************************************************
+// Field: [1:0] MODE
+//
+// This is an alias for PDCTL1.VIMS_MODE
+#define PRCM_PDCTL1VIMS_MODE_W 2
+#define PRCM_PDCTL1VIMS_MODE_M 0x00000003
+#define PRCM_PDCTL1VIMS_MODE_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_PDSTAT1
+//
+//*****************************************************************************
+// Field: [4] BUS_ON
+//
+//
+// 0: BUS domain not accessible
+// 1: BUS domain is currently accessible
+#define PRCM_PDSTAT1_BUS_ON 0x00000010
+#define PRCM_PDSTAT1_BUS_ON_BITN 4
+#define PRCM_PDSTAT1_BUS_ON_M 0x00000010
+#define PRCM_PDSTAT1_BUS_ON_S 4
+
+// Field: [3] VIMS_ON
+//
+//
+// 0: VIMS domain not accessible
+// 1: VIMS domain is currently accessible
+#define PRCM_PDSTAT1_VIMS_ON 0x00000008
+#define PRCM_PDSTAT1_VIMS_ON_BITN 3
+#define PRCM_PDSTAT1_VIMS_ON_M 0x00000008
+#define PRCM_PDSTAT1_VIMS_ON_S 3
+
+// Field: [2] RFC_ON
+//
+//
+// 0: RFC domain not accessible
+// 1: RFC domain is currently accessible
+#define PRCM_PDSTAT1_RFC_ON 0x00000004
+#define PRCM_PDSTAT1_RFC_ON_BITN 2
+#define PRCM_PDSTAT1_RFC_ON_M 0x00000004
+#define PRCM_PDSTAT1_RFC_ON_S 2
+
+// Field: [1] CPU_ON
+//
+//
+// 0: CPU and BUS domain not accessible
+// 1: CPU and BUS domains are both currently accessible
+#define PRCM_PDSTAT1_CPU_ON 0x00000002
+#define PRCM_PDSTAT1_CPU_ON_BITN 1
+#define PRCM_PDSTAT1_CPU_ON_M 0x00000002
+#define PRCM_PDSTAT1_CPU_ON_S 1
+
+//*****************************************************************************
+//
+// Register: PRCM_O_PDSTAT1BUS
+//
+//*****************************************************************************
+// Field: [0] ON
+//
+// This is an alias for PDSTAT1.BUS_ON
+#define PRCM_PDSTAT1BUS_ON 0x00000001
+#define PRCM_PDSTAT1BUS_ON_BITN 0
+#define PRCM_PDSTAT1BUS_ON_M 0x00000001
+#define PRCM_PDSTAT1BUS_ON_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_PDSTAT1RFC
+//
+//*****************************************************************************
+// Field: [0] ON
+//
+// This is an alias for PDSTAT1.RFC_ON
+#define PRCM_PDSTAT1RFC_ON 0x00000001
+#define PRCM_PDSTAT1RFC_ON_BITN 0
+#define PRCM_PDSTAT1RFC_ON_M 0x00000001
+#define PRCM_PDSTAT1RFC_ON_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_PDSTAT1CPU
+//
+//*****************************************************************************
+// Field: [0] ON
+//
+// This is an alias for PDSTAT1.CPU_ON
+#define PRCM_PDSTAT1CPU_ON 0x00000001
+#define PRCM_PDSTAT1CPU_ON_BITN 0
+#define PRCM_PDSTAT1CPU_ON_M 0x00000001
+#define PRCM_PDSTAT1CPU_ON_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_PDSTAT1VIMS
+//
+//*****************************************************************************
+// Field: [0] ON
+//
+// This is an alias for PDSTAT1.VIMS_ON
+#define PRCM_PDSTAT1VIMS_ON 0x00000001
+#define PRCM_PDSTAT1VIMS_ON_BITN 0
+#define PRCM_PDSTAT1VIMS_ON_M 0x00000001
+#define PRCM_PDSTAT1VIMS_ON_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_RFCBITS
+//
+//*****************************************************************************
+// Field: [31:0] READ
+//
+// Control bits for RFC. The RF core CPE processor will automatically check
+// this register when it boots, and it can be used to immediately instruct CPE
+// to perform some tasks at its start-up. The supported functionality is
+// ROM-defined and may vary. See the technical reference manual for more
+// details.
+#define PRCM_RFCBITS_READ_W 32
+#define PRCM_RFCBITS_READ_M 0xFFFFFFFF
+#define PRCM_RFCBITS_READ_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_RFCMODESEL
+//
+//*****************************************************************************
+// Field: [2:0] CURR
+//
+// Selects the set of commands that the RFC will accept. Only modes permitted
+// by RFCMODEHWOPT.AVAIL are writeable. See the technical reference manual for
+// details.
+// ENUMs:
+// MODE7 Select Mode 7
+// MODE6 Select Mode 6
+// MODE5 Select Mode 5
+// MODE4 Select Mode 4
+// MODE3 Select Mode 3
+// MODE2 Select Mode 2
+// MODE1 Select Mode 1
+// MODE0 Select Mode 0
+#define PRCM_RFCMODESEL_CURR_W 3
+#define PRCM_RFCMODESEL_CURR_M 0x00000007
+#define PRCM_RFCMODESEL_CURR_S 0
+#define PRCM_RFCMODESEL_CURR_MODE7 0x00000007
+#define PRCM_RFCMODESEL_CURR_MODE6 0x00000006
+#define PRCM_RFCMODESEL_CURR_MODE5 0x00000005
+#define PRCM_RFCMODESEL_CURR_MODE4 0x00000004
+#define PRCM_RFCMODESEL_CURR_MODE3 0x00000003
+#define PRCM_RFCMODESEL_CURR_MODE2 0x00000002
+#define PRCM_RFCMODESEL_CURR_MODE1 0x00000001
+#define PRCM_RFCMODESEL_CURR_MODE0 0x00000000
+
+//*****************************************************************************
+//
+// Register: PRCM_O_RFCMODEHWOPT
+//
+//*****************************************************************************
+// Field: [7:0] AVAIL
+//
+// Permitted RFC modes. More than one mode can be permitted.
+// ENUMs:
+// MODE7 Mode 7 permitted
+// MODE6 Mode 6 permitted
+// MODE5 Mode 5 permitted
+// MODE4 Mode 4 permitted
+// MODE3 Mode 3 permitted
+// MODE2 Mode 2 permitted
+// MODE1 Mode 1 permitted
+// MODE0 Mode 0 permitted
+#define PRCM_RFCMODEHWOPT_AVAIL_W 8
+#define PRCM_RFCMODEHWOPT_AVAIL_M 0x000000FF
+#define PRCM_RFCMODEHWOPT_AVAIL_S 0
+#define PRCM_RFCMODEHWOPT_AVAIL_MODE7 0x00000080
+#define PRCM_RFCMODEHWOPT_AVAIL_MODE6 0x00000040
+#define PRCM_RFCMODEHWOPT_AVAIL_MODE5 0x00000020
+#define PRCM_RFCMODEHWOPT_AVAIL_MODE4 0x00000010
+#define PRCM_RFCMODEHWOPT_AVAIL_MODE3 0x00000008
+#define PRCM_RFCMODEHWOPT_AVAIL_MODE2 0x00000004
+#define PRCM_RFCMODEHWOPT_AVAIL_MODE1 0x00000002
+#define PRCM_RFCMODEHWOPT_AVAIL_MODE0 0x00000001
+
+//*****************************************************************************
+//
+// Register: PRCM_O_PWRPROFSTAT
+//
+//*****************************************************************************
+// Field: [7:0] VALUE
+//
+// SW can use these bits to timestamp the application. These bits are also
+// available through the testtap and can thus be used by the emulator to
+// profile in real time.
+#define PRCM_PWRPROFSTAT_VALUE_W 8
+#define PRCM_PWRPROFSTAT_VALUE_M 0x000000FF
+#define PRCM_PWRPROFSTAT_VALUE_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_MCUSRAMCFG
+//
+//*****************************************************************************
+// Field: [5] BM_OFF
+//
+// Burst Mode disable
+//
+// 0: Burst Mode enabled.
+// 1: Burst Mode off.
+#define PRCM_MCUSRAMCFG_BM_OFF 0x00000020
+#define PRCM_MCUSRAMCFG_BM_OFF_BITN 5
+#define PRCM_MCUSRAMCFG_BM_OFF_M 0x00000020
+#define PRCM_MCUSRAMCFG_BM_OFF_S 5
+
+// Field: [4] PAGE
+//
+// Page Mode select
+//
+// 0: Page Mode disabled. Memory works in standard mode
+// 1: Page Mode enabled. Only one half of butterfly array selected. Page Mode
+// will select either LSB half or MSB half of the word based on PGS setting.
+//
+// This mode can be used for additional power saving
+#define PRCM_MCUSRAMCFG_PAGE 0x00000010
+#define PRCM_MCUSRAMCFG_PAGE_BITN 4
+#define PRCM_MCUSRAMCFG_PAGE_M 0x00000010
+#define PRCM_MCUSRAMCFG_PAGE_S 4
+
+// Field: [3] PGS
+//
+// 0: Select LSB half of word during Page Mode, PAGE = 1
+// 1: Select MSB half of word during Page Mode, PAGE = 1
+#define PRCM_MCUSRAMCFG_PGS 0x00000008
+#define PRCM_MCUSRAMCFG_PGS_BITN 3
+#define PRCM_MCUSRAMCFG_PGS_M 0x00000008
+#define PRCM_MCUSRAMCFG_PGS_S 3
+
+// Field: [2] BM
+//
+// Burst Mode Enable
+//
+// 0: Burst Mode Disable. Memory works in standard mode.
+// 1: Burst Mode Enable
+//
+// When in Burst Mode bitline precharge and wordline firing depends on PCH_F
+// and PCH_L.
+// Burst Mode results in reduction in active power.
+#define PRCM_MCUSRAMCFG_BM 0x00000004
+#define PRCM_MCUSRAMCFG_BM_BITN 2
+#define PRCM_MCUSRAMCFG_BM_M 0x00000004
+#define PRCM_MCUSRAMCFG_BM_S 2
+
+// Field: [1] PCH_F
+//
+// 0: No bitline precharge in second half of cycle
+// 1: Bitline precharge in second half of cycle when in Burst Mode, BM = 1
+#define PRCM_MCUSRAMCFG_PCH_F 0x00000002
+#define PRCM_MCUSRAMCFG_PCH_F_BITN 1
+#define PRCM_MCUSRAMCFG_PCH_F_M 0x00000002
+#define PRCM_MCUSRAMCFG_PCH_F_S 1
+
+// Field: [0] PCH_L
+//
+// 0: No bitline precharge in first half of cycle
+// 1: Bitline precharge in first half of cycle when in Burst Mode, BM = 1
+#define PRCM_MCUSRAMCFG_PCH_L 0x00000001
+#define PRCM_MCUSRAMCFG_PCH_L_BITN 0
+#define PRCM_MCUSRAMCFG_PCH_L_M 0x00000001
+#define PRCM_MCUSRAMCFG_PCH_L_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_RAMRETEN
+//
+//*****************************************************************************
+// Field: [3] RFCULL
+//
+// 0: Retention for RFC ULL SRAM disabled
+// 1: Retention for RFC ULL SRAM enabled
+//
+// Memories controlled:
+// CPEULLRAM
+#define PRCM_RAMRETEN_RFCULL 0x00000008
+#define PRCM_RAMRETEN_RFCULL_BITN 3
+#define PRCM_RAMRETEN_RFCULL_M 0x00000008
+#define PRCM_RAMRETEN_RFCULL_S 3
+
+// Field: [2] RFC
+//
+// 0: Retention for RFC SRAM disabled
+// 1: Retention for RFC SRAM enabled
+//
+// Memories controlled: CPERAM MCERAM RFERAM DSBRAM
+#define PRCM_RAMRETEN_RFC 0x00000004
+#define PRCM_RAMRETEN_RFC_BITN 2
+#define PRCM_RAMRETEN_RFC_M 0x00000004
+#define PRCM_RAMRETEN_RFC_S 2
+
+// Field: [1:0] VIMS
+//
+//
+// 0: Memory retention disabled
+// 1: Memory retention enabled
+//
+// Bit 0: VIMS_TRAM
+// Bit 1: VIMS_CRAM
+//
+// Legal modes depend on settings in VIMS:CTL.MODE
+//
+// 00: VIMS:CTL.MODE must be OFF before DEEPSLEEP is asserted - must be set to
+// CACHE or SPLIT mode after waking up again
+// 01: VIMS:CTL.MODE must be GPRAM before DEEPSLEEP is asserted. Must remain in
+// GPRAM mode after wake up, alternatively select OFF mode first and then CACHE
+// or SPILT mode.
+// 10: Illegal mode
+// 11: No restrictions
+#define PRCM_RAMRETEN_VIMS_W 2
+#define PRCM_RAMRETEN_VIMS_M 0x00000003
+#define PRCM_RAMRETEN_VIMS_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_OSCIMSC
+//
+//*****************************************************************************
+// Field: [7] HFSRCPENDIM
+//
+// 0: Disable interrupt generation when HFSRCPEND is qualified
+// 1: Enable interrupt generation when HFSRCPEND is qualified
+#define PRCM_OSCIMSC_HFSRCPENDIM 0x00000080
+#define PRCM_OSCIMSC_HFSRCPENDIM_BITN 7
+#define PRCM_OSCIMSC_HFSRCPENDIM_M 0x00000080
+#define PRCM_OSCIMSC_HFSRCPENDIM_S 7
+
+// Field: [6] LFSRCDONEIM
+//
+// 0: Disable interrupt generation when LFSRCDONE is qualified
+// 1: Enable interrupt generation when LFSRCDONE is qualified
+#define PRCM_OSCIMSC_LFSRCDONEIM 0x00000040
+#define PRCM_OSCIMSC_LFSRCDONEIM_BITN 6
+#define PRCM_OSCIMSC_LFSRCDONEIM_M 0x00000040
+#define PRCM_OSCIMSC_LFSRCDONEIM_S 6
+
+// Field: [5] XOSCDLFIM
+//
+// 0: Disable interrupt generation when XOSCDLF is qualified
+// 1: Enable interrupt generation when XOSCDLF is qualified
+#define PRCM_OSCIMSC_XOSCDLFIM 0x00000020
+#define PRCM_OSCIMSC_XOSCDLFIM_BITN 5
+#define PRCM_OSCIMSC_XOSCDLFIM_M 0x00000020
+#define PRCM_OSCIMSC_XOSCDLFIM_S 5
+
+// Field: [4] XOSCLFIM
+//
+// 0: Disable interrupt generation when XOSCLF is qualified
+// 1: Enable interrupt generation when XOSCLF is qualified
+#define PRCM_OSCIMSC_XOSCLFIM 0x00000010
+#define PRCM_OSCIMSC_XOSCLFIM_BITN 4
+#define PRCM_OSCIMSC_XOSCLFIM_M 0x00000010
+#define PRCM_OSCIMSC_XOSCLFIM_S 4
+
+// Field: [3] RCOSCDLFIM
+//
+// 0: Disable interrupt generation when RCOSCDLF is qualified
+// 1: Enable interrupt generation when RCOSCDLF is qualified
+#define PRCM_OSCIMSC_RCOSCDLFIM 0x00000008
+#define PRCM_OSCIMSC_RCOSCDLFIM_BITN 3
+#define PRCM_OSCIMSC_RCOSCDLFIM_M 0x00000008
+#define PRCM_OSCIMSC_RCOSCDLFIM_S 3
+
+// Field: [2] RCOSCLFIM
+//
+// 0: Disable interrupt generation when RCOSCLF is qualified
+// 1: Enable interrupt generation when RCOSCLF is qualified
+#define PRCM_OSCIMSC_RCOSCLFIM 0x00000004
+#define PRCM_OSCIMSC_RCOSCLFIM_BITN 2
+#define PRCM_OSCIMSC_RCOSCLFIM_M 0x00000004
+#define PRCM_OSCIMSC_RCOSCLFIM_S 2
+
+// Field: [1] XOSCHFIM
+//
+// 0: Disable interrupt generation when XOSCHF is qualified
+// 1: Enable interrupt generation when XOSCHF is qualified
+#define PRCM_OSCIMSC_XOSCHFIM 0x00000002
+#define PRCM_OSCIMSC_XOSCHFIM_BITN 1
+#define PRCM_OSCIMSC_XOSCHFIM_M 0x00000002
+#define PRCM_OSCIMSC_XOSCHFIM_S 1
+
+// Field: [0] RCOSCHFIM
+//
+// 0: Disable interrupt generation when RCOSCHF is qualified
+// 1: Enable interrupt generation when RCOSCHF is qualified
+#define PRCM_OSCIMSC_RCOSCHFIM 0x00000001
+#define PRCM_OSCIMSC_RCOSCHFIM_BITN 0
+#define PRCM_OSCIMSC_RCOSCHFIM_M 0x00000001
+#define PRCM_OSCIMSC_RCOSCHFIM_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_OSCRIS
+//
+//*****************************************************************************
+// Field: [7] HFSRCPENDRIS
+//
+// 0: HFSRCPEND has not been qualified
+// 1: HFSRCPEND has been qualified since last clear
+//
+// Interrupt is qualified regardless of OSCIMSC.HFSRCPENDIM setting. The order
+// of qualifying raw interrupt and enable of interrupt mask is indifferent for
+// generating an OSC Interrupt.
+//
+// Set by HW. Cleared by writing to OSCICR.HFSRCPENDC
+#define PRCM_OSCRIS_HFSRCPENDRIS 0x00000080
+#define PRCM_OSCRIS_HFSRCPENDRIS_BITN 7
+#define PRCM_OSCRIS_HFSRCPENDRIS_M 0x00000080
+#define PRCM_OSCRIS_HFSRCPENDRIS_S 7
+
+// Field: [6] LFSRCDONERIS
+//
+// 0: LFSRCDONE has not been qualified
+// 1: LFSRCDONE has been qualified since last clear
+//
+// Interrupt is qualified regardless of OSCIMSC.LFSRCDONEIM setting. The order
+// of qualifying raw interrupt and enable of interrupt mask is indifferent for
+// generating an OSC Interrupt.
+//
+// Set by HW. Cleared by writing to OSCICR.LFSRCDONEC
+#define PRCM_OSCRIS_LFSRCDONERIS 0x00000040
+#define PRCM_OSCRIS_LFSRCDONERIS_BITN 6
+#define PRCM_OSCRIS_LFSRCDONERIS_M 0x00000040
+#define PRCM_OSCRIS_LFSRCDONERIS_S 6
+
+// Field: [5] XOSCDLFRIS
+//
+// 0: XOSCDLF has not been qualified
+// 1: XOSCDLF has been qualified since last clear.
+//
+// Interrupt is qualified regardless of OSCIMSC.XOSCDLFIM setting. The order of
+// qualifying raw interrupt and enable of interrupt mask is indifferent for
+// generating an OSC Interrupt.
+//
+// Set by HW. Cleared by writing to OSCICR.XOSCDLFC
+#define PRCM_OSCRIS_XOSCDLFRIS 0x00000020
+#define PRCM_OSCRIS_XOSCDLFRIS_BITN 5
+#define PRCM_OSCRIS_XOSCDLFRIS_M 0x00000020
+#define PRCM_OSCRIS_XOSCDLFRIS_S 5
+
+// Field: [4] XOSCLFRIS
+//
+// 0: XOSCLF has not been qualified
+// 1: XOSCLF has been qualified since last clear.
+//
+// Interrupt is qualified regardless of OSCIMSC.XOSCLFIM setting. The order of
+// qualifying raw interrupt and enable of interrupt mask is indifferent for
+// generating an OSC Interrupt.
+//
+// Set by HW. Cleared by writing to OSCICR.XOSCLFC
+#define PRCM_OSCRIS_XOSCLFRIS 0x00000010
+#define PRCM_OSCRIS_XOSCLFRIS_BITN 4
+#define PRCM_OSCRIS_XOSCLFRIS_M 0x00000010
+#define PRCM_OSCRIS_XOSCLFRIS_S 4
+
+// Field: [3] RCOSCDLFRIS
+//
+// 0: RCOSCDLF has not been qualified
+// 1: RCOSCDLF has been qualified since last clear.
+//
+// Interrupt is qualified regardless of OSCIMSC.RCOSCDLFIM setting. The order
+// of qualifying raw interrupt and enable of interrupt mask is indifferent for
+// generating an OSC Interrupt.
+//
+// Set by HW. Cleared by writing to OSCICR.RCOSCDLFC
+#define PRCM_OSCRIS_RCOSCDLFRIS 0x00000008
+#define PRCM_OSCRIS_RCOSCDLFRIS_BITN 3
+#define PRCM_OSCRIS_RCOSCDLFRIS_M 0x00000008
+#define PRCM_OSCRIS_RCOSCDLFRIS_S 3
+
+// Field: [2] RCOSCLFRIS
+//
+// 0: RCOSCLF has not been qualified
+// 1: RCOSCLF has been qualified since last clear.
+//
+// Interrupt is qualified regardless of OSCIMSC.RCOSCLFIM setting. The order of
+// qualifying raw interrupt and enable of interrupt mask is indifferent for
+// generating an OSC Interrupt.
+//
+// Set by HW. Cleared by writing to OSCICR.RCOSCLFC
+#define PRCM_OSCRIS_RCOSCLFRIS 0x00000004
+#define PRCM_OSCRIS_RCOSCLFRIS_BITN 2
+#define PRCM_OSCRIS_RCOSCLFRIS_M 0x00000004
+#define PRCM_OSCRIS_RCOSCLFRIS_S 2
+
+// Field: [1] XOSCHFRIS
+//
+// 0: XOSCHF has not been qualified
+// 1: XOSCHF has been qualified since last clear.
+//
+// Interrupt is qualified regardless of OSCIMSC.XOSCHFIM setting. The order of
+// qualifying raw interrupt and enable of interrupt mask is indifferent for
+// generating an OSC Interrupt.
+//
+// Set by HW. Cleared by writing to OSCICR.XOSCHFC
+#define PRCM_OSCRIS_XOSCHFRIS 0x00000002
+#define PRCM_OSCRIS_XOSCHFRIS_BITN 1
+#define PRCM_OSCRIS_XOSCHFRIS_M 0x00000002
+#define PRCM_OSCRIS_XOSCHFRIS_S 1
+
+// Field: [0] RCOSCHFRIS
+//
+// 0: RCOSCHF has not been qualified
+// 1: RCOSCHF has been qualified since last clear.
+//
+// Interrupt is qualified regardless of OSCIMSC.RCOSCHFIM setting. The order of
+// qualifying raw interrupt and enable of interrupt mask is indifferent for
+// generating an OSC Interrupt.
+//
+// Set by HW. Cleared by writing to OSCICR.RCOSCHFC
+#define PRCM_OSCRIS_RCOSCHFRIS 0x00000001
+#define PRCM_OSCRIS_RCOSCHFRIS_BITN 0
+#define PRCM_OSCRIS_RCOSCHFRIS_M 0x00000001
+#define PRCM_OSCRIS_RCOSCHFRIS_S 0
+
+//*****************************************************************************
+//
+// Register: PRCM_O_OSCICR
+//
+//*****************************************************************************
+// Field: [7] HFSRCPENDC
+//
+// Writing 1 to this field clears the HFSRCPEND raw interrupt status. Writing 0
+// has no effect.
+#define PRCM_OSCICR_HFSRCPENDC 0x00000080
+#define PRCM_OSCICR_HFSRCPENDC_BITN 7
+#define PRCM_OSCICR_HFSRCPENDC_M 0x00000080
+#define PRCM_OSCICR_HFSRCPENDC_S 7
+
+// Field: [6] LFSRCDONEC
+//
+// Writing 1 to this field clears the LFSRCDONE raw interrupt status. Writing 0
+// has no effect.
+#define PRCM_OSCICR_LFSRCDONEC 0x00000040
+#define PRCM_OSCICR_LFSRCDONEC_BITN 6
+#define PRCM_OSCICR_LFSRCDONEC_M 0x00000040
+#define PRCM_OSCICR_LFSRCDONEC_S 6
+
+// Field: [5] XOSCDLFC
+//
+// Writing 1 to this field clears the XOSCDLF raw interrupt status. Writing 0
+// has no effect.
+#define PRCM_OSCICR_XOSCDLFC 0x00000020
+#define PRCM_OSCICR_XOSCDLFC_BITN 5
+#define PRCM_OSCICR_XOSCDLFC_M 0x00000020
+#define PRCM_OSCICR_XOSCDLFC_S 5
+
+// Field: [4] XOSCLFC
+//
+// Writing 1 to this field clears the XOSCLF raw interrupt status. Writing 0
+// has no effect.
+#define PRCM_OSCICR_XOSCLFC 0x00000010
+#define PRCM_OSCICR_XOSCLFC_BITN 4
+#define PRCM_OSCICR_XOSCLFC_M 0x00000010
+#define PRCM_OSCICR_XOSCLFC_S 4
+
+// Field: [3] RCOSCDLFC
+//
+// Writing 1 to this field clears the RCOSCDLF raw interrupt status. Writing 0
+// has no effect.
+#define PRCM_OSCICR_RCOSCDLFC 0x00000008
+#define PRCM_OSCICR_RCOSCDLFC_BITN 3
+#define PRCM_OSCICR_RCOSCDLFC_M 0x00000008
+#define PRCM_OSCICR_RCOSCDLFC_S 3
+
+// Field: [2] RCOSCLFC
+//
+// Writing 1 to this field clears the RCOSCLF raw interrupt status. Writing 0
+// has no effect.
+#define PRCM_OSCICR_RCOSCLFC 0x00000004
+#define PRCM_OSCICR_RCOSCLFC_BITN 2
+#define PRCM_OSCICR_RCOSCLFC_M 0x00000004
+#define PRCM_OSCICR_RCOSCLFC_S 2
+
+// Field: [1] XOSCHFC
+//
+// Writing 1 to this field clears the XOSCHF raw interrupt status. Writing 0
+// has no effect.
+#define PRCM_OSCICR_XOSCHFC 0x00000002
+#define PRCM_OSCICR_XOSCHFC_BITN 1
+#define PRCM_OSCICR_XOSCHFC_M 0x00000002
+#define PRCM_OSCICR_XOSCHFC_S 1
+
+// Field: [0] RCOSCHFC
+//
+// Writing 1 to this field clears the RCOSCHF raw interrupt status. Writing 0
+// has no effect.
+#define PRCM_OSCICR_RCOSCHFC 0x00000001
+#define PRCM_OSCICR_RCOSCHFC_BITN 0
+#define PRCM_OSCICR_RCOSCHFC_M 0x00000001
+#define PRCM_OSCICR_RCOSCHFC_S 0
+
+
+#endif // __PRCM__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_dbell.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_dbell.h
new file mode 100644
index 0000000..612d3ec
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_dbell.h
@@ -0,0 +1,1672 @@
+/******************************************************************************
+* Filename: hw_rfc_dbell_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_RFC_DBELL_H__
+#define __HW_RFC_DBELL_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// RFC_DBELL component
+//
+//*****************************************************************************
+// Doorbell Command Register
+#define RFC_DBELL_O_CMDR 0x00000000
+
+// Doorbell Command Status Register
+#define RFC_DBELL_O_CMDSTA 0x00000004
+
+// Interrupt Flags From RF Hardware Modules
+#define RFC_DBELL_O_RFHWIFG 0x00000008
+
+// Interrupt Enable For RF Hardware Modules
+#define RFC_DBELL_O_RFHWIEN 0x0000000C
+
+// Interrupt Flags For Command and Packet Engine Generated Interrupts
+#define RFC_DBELL_O_RFCPEIFG 0x00000010
+
+// Interrupt Enable For Command and Packet Engine Generated Interrupts
+#define RFC_DBELL_O_RFCPEIEN 0x00000014
+
+// Interrupt Vector Selection For Command and Packet Engine Generated
+// Interrupts
+#define RFC_DBELL_O_RFCPEISL 0x00000018
+
+// Doorbell Command Acknowledgement Interrupt Flag
+#define RFC_DBELL_O_RFACKIFG 0x0000001C
+
+// RF Core General Purpose Output Control
+#define RFC_DBELL_O_SYSGPOCTL 0x00000020
+
+//*****************************************************************************
+//
+// Register: RFC_DBELL_O_CMDR
+//
+//*****************************************************************************
+// Field: [31:0] CMD
+//
+// Command register. Raises an interrupt to the Command and packet engine (CPE)
+// upon write.
+#define RFC_DBELL_CMDR_CMD_W 32
+#define RFC_DBELL_CMDR_CMD_M 0xFFFFFFFF
+#define RFC_DBELL_CMDR_CMD_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_DBELL_O_CMDSTA
+//
+//*****************************************************************************
+// Field: [31:0] STAT
+//
+// Status of the last command used
+#define RFC_DBELL_CMDSTA_STAT_W 32
+#define RFC_DBELL_CMDSTA_STAT_M 0xFFFFFFFF
+#define RFC_DBELL_CMDSTA_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_DBELL_O_RFHWIFG
+//
+//*****************************************************************************
+// Field: [19] RATCH7
+//
+// Radio timer channel 7 interrupt flag. Write zero to clear flag. Write to one
+// has no effect.
+#define RFC_DBELL_RFHWIFG_RATCH7 0x00080000
+#define RFC_DBELL_RFHWIFG_RATCH7_BITN 19
+#define RFC_DBELL_RFHWIFG_RATCH7_M 0x00080000
+#define RFC_DBELL_RFHWIFG_RATCH7_S 19
+
+// Field: [18] RATCH6
+//
+// Radio timer channel 6 interrupt flag. Write zero to clear flag. Write to one
+// has no effect.
+#define RFC_DBELL_RFHWIFG_RATCH6 0x00040000
+#define RFC_DBELL_RFHWIFG_RATCH6_BITN 18
+#define RFC_DBELL_RFHWIFG_RATCH6_M 0x00040000
+#define RFC_DBELL_RFHWIFG_RATCH6_S 18
+
+// Field: [17] RATCH5
+//
+// Radio timer channel 5 interrupt flag. Write zero to clear flag. Write to one
+// has no effect.
+#define RFC_DBELL_RFHWIFG_RATCH5 0x00020000
+#define RFC_DBELL_RFHWIFG_RATCH5_BITN 17
+#define RFC_DBELL_RFHWIFG_RATCH5_M 0x00020000
+#define RFC_DBELL_RFHWIFG_RATCH5_S 17
+
+// Field: [16] RATCH4
+//
+// Radio timer channel 4 interrupt flag. Write zero to clear flag. Write to one
+// has no effect.
+#define RFC_DBELL_RFHWIFG_RATCH4 0x00010000
+#define RFC_DBELL_RFHWIFG_RATCH4_BITN 16
+#define RFC_DBELL_RFHWIFG_RATCH4_M 0x00010000
+#define RFC_DBELL_RFHWIFG_RATCH4_S 16
+
+// Field: [15] RATCH3
+//
+// Radio timer channel 3 interrupt flag. Write zero to clear flag. Write to one
+// has no effect.
+#define RFC_DBELL_RFHWIFG_RATCH3 0x00008000
+#define RFC_DBELL_RFHWIFG_RATCH3_BITN 15
+#define RFC_DBELL_RFHWIFG_RATCH3_M 0x00008000
+#define RFC_DBELL_RFHWIFG_RATCH3_S 15
+
+// Field: [14] RATCH2
+//
+// Radio timer channel 2 interrupt flag. Write zero to clear flag. Write to one
+// has no effect.
+#define RFC_DBELL_RFHWIFG_RATCH2 0x00004000
+#define RFC_DBELL_RFHWIFG_RATCH2_BITN 14
+#define RFC_DBELL_RFHWIFG_RATCH2_M 0x00004000
+#define RFC_DBELL_RFHWIFG_RATCH2_S 14
+
+// Field: [13] RATCH1
+//
+// Radio timer channel 1 interrupt flag. Write zero to clear flag. Write to one
+// has no effect.
+#define RFC_DBELL_RFHWIFG_RATCH1 0x00002000
+#define RFC_DBELL_RFHWIFG_RATCH1_BITN 13
+#define RFC_DBELL_RFHWIFG_RATCH1_M 0x00002000
+#define RFC_DBELL_RFHWIFG_RATCH1_S 13
+
+// Field: [12] RATCH0
+//
+// Radio timer channel 0 interrupt flag. Write zero to clear flag. Write to one
+// has no effect.
+#define RFC_DBELL_RFHWIFG_RATCH0 0x00001000
+#define RFC_DBELL_RFHWIFG_RATCH0_BITN 12
+#define RFC_DBELL_RFHWIFG_RATCH0_M 0x00001000
+#define RFC_DBELL_RFHWIFG_RATCH0_S 12
+
+// Field: [11] RFESOFT2
+//
+// RF engine software defined interrupt 2 flag. Write zero to clear flag. Write
+// to one has no effect.
+#define RFC_DBELL_RFHWIFG_RFESOFT2 0x00000800
+#define RFC_DBELL_RFHWIFG_RFESOFT2_BITN 11
+#define RFC_DBELL_RFHWIFG_RFESOFT2_M 0x00000800
+#define RFC_DBELL_RFHWIFG_RFESOFT2_S 11
+
+// Field: [10] RFESOFT1
+//
+// RF engine software defined interrupt 1 flag. Write zero to clear flag. Write
+// to one has no effect.
+#define RFC_DBELL_RFHWIFG_RFESOFT1 0x00000400
+#define RFC_DBELL_RFHWIFG_RFESOFT1_BITN 10
+#define RFC_DBELL_RFHWIFG_RFESOFT1_M 0x00000400
+#define RFC_DBELL_RFHWIFG_RFESOFT1_S 10
+
+// Field: [9] RFESOFT0
+//
+// RF engine software defined interrupt 0 flag. Write zero to clear flag. Write
+// to one has no effect.
+#define RFC_DBELL_RFHWIFG_RFESOFT0 0x00000200
+#define RFC_DBELL_RFHWIFG_RFESOFT0_BITN 9
+#define RFC_DBELL_RFHWIFG_RFESOFT0_M 0x00000200
+#define RFC_DBELL_RFHWIFG_RFESOFT0_S 9
+
+// Field: [8] RFEDONE
+//
+// RF engine command done interrupt flag. Write zero to clear flag. Write to
+// one has no effect.
+#define RFC_DBELL_RFHWIFG_RFEDONE 0x00000100
+#define RFC_DBELL_RFHWIFG_RFEDONE_BITN 8
+#define RFC_DBELL_RFHWIFG_RFEDONE_M 0x00000100
+#define RFC_DBELL_RFHWIFG_RFEDONE_S 8
+
+// Field: [6] TRCTK
+//
+// Debug tracer system tick interrupt flag. Write zero to clear flag. Write to
+// one has no effect.
+#define RFC_DBELL_RFHWIFG_TRCTK 0x00000040
+#define RFC_DBELL_RFHWIFG_TRCTK_BITN 6
+#define RFC_DBELL_RFHWIFG_TRCTK_M 0x00000040
+#define RFC_DBELL_RFHWIFG_TRCTK_S 6
+
+// Field: [5] MDMSOFT
+//
+// Modem software defined interrupt flag. Write zero to clear flag. Write to
+// one has no effect.
+#define RFC_DBELL_RFHWIFG_MDMSOFT 0x00000020
+#define RFC_DBELL_RFHWIFG_MDMSOFT_BITN 5
+#define RFC_DBELL_RFHWIFG_MDMSOFT_M 0x00000020
+#define RFC_DBELL_RFHWIFG_MDMSOFT_S 5
+
+// Field: [4] MDMOUT
+//
+// Modem FIFO output interrupt flag. Write zero to clear flag. Write to one has
+// no effect.
+#define RFC_DBELL_RFHWIFG_MDMOUT 0x00000010
+#define RFC_DBELL_RFHWIFG_MDMOUT_BITN 4
+#define RFC_DBELL_RFHWIFG_MDMOUT_M 0x00000010
+#define RFC_DBELL_RFHWIFG_MDMOUT_S 4
+
+// Field: [3] MDMIN
+//
+// Modem FIFO input interrupt flag. Write zero to clear flag. Write to one has
+// no effect.
+#define RFC_DBELL_RFHWIFG_MDMIN 0x00000008
+#define RFC_DBELL_RFHWIFG_MDMIN_BITN 3
+#define RFC_DBELL_RFHWIFG_MDMIN_M 0x00000008
+#define RFC_DBELL_RFHWIFG_MDMIN_S 3
+
+// Field: [2] MDMDONE
+//
+// Modem command done interrupt flag. Write zero to clear flag. Write to one
+// has no effect.
+#define RFC_DBELL_RFHWIFG_MDMDONE 0x00000004
+#define RFC_DBELL_RFHWIFG_MDMDONE_BITN 2
+#define RFC_DBELL_RFHWIFG_MDMDONE_M 0x00000004
+#define RFC_DBELL_RFHWIFG_MDMDONE_S 2
+
+// Field: [1] FSCA
+//
+// Frequency synthesizer calibration accelerator interrupt flag. Write zero to
+// clear flag. Write to one has no effect.
+#define RFC_DBELL_RFHWIFG_FSCA 0x00000002
+#define RFC_DBELL_RFHWIFG_FSCA_BITN 1
+#define RFC_DBELL_RFHWIFG_FSCA_M 0x00000002
+#define RFC_DBELL_RFHWIFG_FSCA_S 1
+
+//*****************************************************************************
+//
+// Register: RFC_DBELL_O_RFHWIEN
+//
+//*****************************************************************************
+// Field: [19] RATCH7
+//
+// Interrupt enable for RFHWIFG.RATCH7.
+#define RFC_DBELL_RFHWIEN_RATCH7 0x00080000
+#define RFC_DBELL_RFHWIEN_RATCH7_BITN 19
+#define RFC_DBELL_RFHWIEN_RATCH7_M 0x00080000
+#define RFC_DBELL_RFHWIEN_RATCH7_S 19
+
+// Field: [18] RATCH6
+//
+// Interrupt enable for RFHWIFG.RATCH6.
+#define RFC_DBELL_RFHWIEN_RATCH6 0x00040000
+#define RFC_DBELL_RFHWIEN_RATCH6_BITN 18
+#define RFC_DBELL_RFHWIEN_RATCH6_M 0x00040000
+#define RFC_DBELL_RFHWIEN_RATCH6_S 18
+
+// Field: [17] RATCH5
+//
+// Interrupt enable for RFHWIFG.RATCH5.
+#define RFC_DBELL_RFHWIEN_RATCH5 0x00020000
+#define RFC_DBELL_RFHWIEN_RATCH5_BITN 17
+#define RFC_DBELL_RFHWIEN_RATCH5_M 0x00020000
+#define RFC_DBELL_RFHWIEN_RATCH5_S 17
+
+// Field: [16] RATCH4
+//
+// Interrupt enable for RFHWIFG.RATCH4.
+#define RFC_DBELL_RFHWIEN_RATCH4 0x00010000
+#define RFC_DBELL_RFHWIEN_RATCH4_BITN 16
+#define RFC_DBELL_RFHWIEN_RATCH4_M 0x00010000
+#define RFC_DBELL_RFHWIEN_RATCH4_S 16
+
+// Field: [15] RATCH3
+//
+// Interrupt enable for RFHWIFG.RATCH3.
+#define RFC_DBELL_RFHWIEN_RATCH3 0x00008000
+#define RFC_DBELL_RFHWIEN_RATCH3_BITN 15
+#define RFC_DBELL_RFHWIEN_RATCH3_M 0x00008000
+#define RFC_DBELL_RFHWIEN_RATCH3_S 15
+
+// Field: [14] RATCH2
+//
+// Interrupt enable for RFHWIFG.RATCH2.
+#define RFC_DBELL_RFHWIEN_RATCH2 0x00004000
+#define RFC_DBELL_RFHWIEN_RATCH2_BITN 14
+#define RFC_DBELL_RFHWIEN_RATCH2_M 0x00004000
+#define RFC_DBELL_RFHWIEN_RATCH2_S 14
+
+// Field: [13] RATCH1
+//
+// Interrupt enable for RFHWIFG.RATCH1.
+#define RFC_DBELL_RFHWIEN_RATCH1 0x00002000
+#define RFC_DBELL_RFHWIEN_RATCH1_BITN 13
+#define RFC_DBELL_RFHWIEN_RATCH1_M 0x00002000
+#define RFC_DBELL_RFHWIEN_RATCH1_S 13
+
+// Field: [12] RATCH0
+//
+// Interrupt enable for RFHWIFG.RATCH0.
+#define RFC_DBELL_RFHWIEN_RATCH0 0x00001000
+#define RFC_DBELL_RFHWIEN_RATCH0_BITN 12
+#define RFC_DBELL_RFHWIEN_RATCH0_M 0x00001000
+#define RFC_DBELL_RFHWIEN_RATCH0_S 12
+
+// Field: [11] RFESOFT2
+//
+// Interrupt enable for RFHWIFG.RFESOFT2.
+#define RFC_DBELL_RFHWIEN_RFESOFT2 0x00000800
+#define RFC_DBELL_RFHWIEN_RFESOFT2_BITN 11
+#define RFC_DBELL_RFHWIEN_RFESOFT2_M 0x00000800
+#define RFC_DBELL_RFHWIEN_RFESOFT2_S 11
+
+// Field: [10] RFESOFT1
+//
+// Interrupt enable for RFHWIFG.RFESOFT1.
+#define RFC_DBELL_RFHWIEN_RFESOFT1 0x00000400
+#define RFC_DBELL_RFHWIEN_RFESOFT1_BITN 10
+#define RFC_DBELL_RFHWIEN_RFESOFT1_M 0x00000400
+#define RFC_DBELL_RFHWIEN_RFESOFT1_S 10
+
+// Field: [9] RFESOFT0
+//
+// Interrupt enable for RFHWIFG.RFESOFT0.
+#define RFC_DBELL_RFHWIEN_RFESOFT0 0x00000200
+#define RFC_DBELL_RFHWIEN_RFESOFT0_BITN 9
+#define RFC_DBELL_RFHWIEN_RFESOFT0_M 0x00000200
+#define RFC_DBELL_RFHWIEN_RFESOFT0_S 9
+
+// Field: [8] RFEDONE
+//
+// Interrupt enable for RFHWIFG.RFEDONE.
+#define RFC_DBELL_RFHWIEN_RFEDONE 0x00000100
+#define RFC_DBELL_RFHWIEN_RFEDONE_BITN 8
+#define RFC_DBELL_RFHWIEN_RFEDONE_M 0x00000100
+#define RFC_DBELL_RFHWIEN_RFEDONE_S 8
+
+// Field: [6] TRCTK
+//
+// Interrupt enable for RFHWIFG.TRCTK.
+#define RFC_DBELL_RFHWIEN_TRCTK 0x00000040
+#define RFC_DBELL_RFHWIEN_TRCTK_BITN 6
+#define RFC_DBELL_RFHWIEN_TRCTK_M 0x00000040
+#define RFC_DBELL_RFHWIEN_TRCTK_S 6
+
+// Field: [5] MDMSOFT
+//
+// Interrupt enable for RFHWIFG.MDMSOFT.
+#define RFC_DBELL_RFHWIEN_MDMSOFT 0x00000020
+#define RFC_DBELL_RFHWIEN_MDMSOFT_BITN 5
+#define RFC_DBELL_RFHWIEN_MDMSOFT_M 0x00000020
+#define RFC_DBELL_RFHWIEN_MDMSOFT_S 5
+
+// Field: [4] MDMOUT
+//
+// Interrupt enable for RFHWIFG.MDMOUT.
+#define RFC_DBELL_RFHWIEN_MDMOUT 0x00000010
+#define RFC_DBELL_RFHWIEN_MDMOUT_BITN 4
+#define RFC_DBELL_RFHWIEN_MDMOUT_M 0x00000010
+#define RFC_DBELL_RFHWIEN_MDMOUT_S 4
+
+// Field: [3] MDMIN
+//
+// Interrupt enable for RFHWIFG.MDMIN.
+#define RFC_DBELL_RFHWIEN_MDMIN 0x00000008
+#define RFC_DBELL_RFHWIEN_MDMIN_BITN 3
+#define RFC_DBELL_RFHWIEN_MDMIN_M 0x00000008
+#define RFC_DBELL_RFHWIEN_MDMIN_S 3
+
+// Field: [2] MDMDONE
+//
+// Interrupt enable for RFHWIFG.MDMDONE.
+#define RFC_DBELL_RFHWIEN_MDMDONE 0x00000004
+#define RFC_DBELL_RFHWIEN_MDMDONE_BITN 2
+#define RFC_DBELL_RFHWIEN_MDMDONE_M 0x00000004
+#define RFC_DBELL_RFHWIEN_MDMDONE_S 2
+
+// Field: [1] FSCA
+//
+// Interrupt enable for RFHWIFG.FSCA.
+#define RFC_DBELL_RFHWIEN_FSCA 0x00000002
+#define RFC_DBELL_RFHWIEN_FSCA_BITN 1
+#define RFC_DBELL_RFHWIEN_FSCA_M 0x00000002
+#define RFC_DBELL_RFHWIEN_FSCA_S 1
+
+//*****************************************************************************
+//
+// Register: RFC_DBELL_O_RFCPEIFG
+//
+//*****************************************************************************
+// Field: [31] INTERNAL_ERROR
+//
+// Interrupt flag 31. The command and packet engine (CPE) has observed an
+// unexpected error. A reset of the CPE is needed. This can be done by
+// switching the RF Core power domain off and on in PRCM:PDCTL1RFC. Write zero
+// to clear flag. Write to one has no effect.
+#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR 0x80000000
+#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_BITN 31
+#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_M 0x80000000
+#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_S 31
+
+// Field: [30] BOOT_DONE
+//
+// Interrupt flag 30. The command and packet engine (CPE) boot is finished.
+// Write zero to clear flag. Write to one has no effect.
+#define RFC_DBELL_RFCPEIFG_BOOT_DONE 0x40000000
+#define RFC_DBELL_RFCPEIFG_BOOT_DONE_BITN 30
+#define RFC_DBELL_RFCPEIFG_BOOT_DONE_M 0x40000000
+#define RFC_DBELL_RFCPEIFG_BOOT_DONE_S 30
+
+// Field: [29] MODULES_UNLOCKED
+//
+// Interrupt flag 29. As part of command and packet engine (CPE) boot process,
+// it has opened access to RF Core modules and memories. Write zero to clear
+// flag. Write to one has no effect.
+#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED 0x20000000
+#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_BITN 29
+#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_M 0x20000000
+#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_S 29
+
+// Field: [28] SYNTH_NO_LOCK
+//
+// Interrupt flag 28. The phase-locked loop in frequency synthesizer has
+// reported loss of lock. Write zero to clear flag. Write to one has no effect.
+#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK 0x10000000
+#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_BITN 28
+#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_M 0x10000000
+#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_S 28
+
+// Field: [27] IRQ27
+//
+// Interrupt flag 27. Write zero to clear flag. Write to one has no effect.
+#define RFC_DBELL_RFCPEIFG_IRQ27 0x08000000
+#define RFC_DBELL_RFCPEIFG_IRQ27_BITN 27
+#define RFC_DBELL_RFCPEIFG_IRQ27_M 0x08000000
+#define RFC_DBELL_RFCPEIFG_IRQ27_S 27
+
+// Field: [26] RX_ABORTED
+//
+// Interrupt flag 26. Packet reception stopped before packet was done. Write
+// zero to clear flag. Write to one has no effect.
+#define RFC_DBELL_RFCPEIFG_RX_ABORTED 0x04000000
+#define RFC_DBELL_RFCPEIFG_RX_ABORTED_BITN 26
+#define RFC_DBELL_RFCPEIFG_RX_ABORTED_M 0x04000000
+#define RFC_DBELL_RFCPEIFG_RX_ABORTED_S 26
+
+// Field: [25] RX_N_DATA_WRITTEN
+//
+// Interrupt flag 25. Specified number of bytes written to partial read Rx
+// buffer. Write zero to clear flag. Write to one has no effect.
+#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN 0x02000000
+#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_BITN 25
+#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_M 0x02000000
+#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_S 25
+
+// Field: [24] RX_DATA_WRITTEN
+//
+// Interrupt flag 24. Data written to partial read Rx buffer. Write zero to
+// clear flag. Write to one has no effect.
+#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN 0x01000000
+#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_BITN 24
+#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_M 0x01000000
+#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_S 24
+
+// Field: [23] RX_ENTRY_DONE
+//
+// Interrupt flag 23. Rx queue data entry changing state to finished. Write
+// zero to clear flag. Write to one has no effect.
+#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE 0x00800000
+#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_BITN 23
+#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_M 0x00800000
+#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_S 23
+
+// Field: [22] RX_BUF_FULL
+//
+// Interrupt flag 22. Packet received that did not fit in Rx queue. BLE mode:
+// Packet received that did not fit in the Rx queue. IEEE 802.15.4 mode: Frame
+// received that did not fit in the Rx queue. Write zero to clear flag. Write
+// to one has no effect.
+#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL 0x00400000
+#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_BITN 22
+#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_M 0x00400000
+#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_S 22
+
+// Field: [21] RX_CTRL_ACK
+//
+// Interrupt flag 21. BLE mode only: LL control packet received with CRC OK,
+// not to be ignored, then acknowledgement sent. Write zero to clear flag.
+// Write to one has no effect.
+#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK 0x00200000
+#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_BITN 21
+#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_M 0x00200000
+#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_S 21
+
+// Field: [20] RX_CTRL
+//
+// Interrupt flag 20. BLE mode only: LL control packet received with CRC OK,
+// not to be ignored. Write zero to clear flag. Write to one has no effect.
+#define RFC_DBELL_RFCPEIFG_RX_CTRL 0x00100000
+#define RFC_DBELL_RFCPEIFG_RX_CTRL_BITN 20
+#define RFC_DBELL_RFCPEIFG_RX_CTRL_M 0x00100000
+#define RFC_DBELL_RFCPEIFG_RX_CTRL_S 20
+
+// Field: [19] RX_EMPTY
+//
+// Interrupt flag 19. BLE mode only: Packet received with CRC OK, not to be
+// ignored, no payload. Write zero to clear flag. Write to one has no effect.
+#define RFC_DBELL_RFCPEIFG_RX_EMPTY 0x00080000
+#define RFC_DBELL_RFCPEIFG_RX_EMPTY_BITN 19
+#define RFC_DBELL_RFCPEIFG_RX_EMPTY_M 0x00080000
+#define RFC_DBELL_RFCPEIFG_RX_EMPTY_S 19
+
+// Field: [18] RX_IGNORED
+//
+// Interrupt flag 18. Packet received, but can be ignored. BLE mode: Packet
+// received with CRC OK, but to be ignored. IEEE 802.15.4 mode: Frame received
+// with ignore flag set. Write zero to clear flag. Write to one has no effect.
+#define RFC_DBELL_RFCPEIFG_RX_IGNORED 0x00040000
+#define RFC_DBELL_RFCPEIFG_RX_IGNORED_BITN 18
+#define RFC_DBELL_RFCPEIFG_RX_IGNORED_M 0x00040000
+#define RFC_DBELL_RFCPEIFG_RX_IGNORED_S 18
+
+// Field: [17] RX_NOK
+//
+// Interrupt flag 17. Packet received with CRC error. BLE mode: Packet received
+// with CRC error. IEEE 802.15.4 mode: Frame received with CRC error. Write
+// zero to clear flag. Write to one has no effect.
+#define RFC_DBELL_RFCPEIFG_RX_NOK 0x00020000
+#define RFC_DBELL_RFCPEIFG_RX_NOK_BITN 17
+#define RFC_DBELL_RFCPEIFG_RX_NOK_M 0x00020000
+#define RFC_DBELL_RFCPEIFG_RX_NOK_S 17
+
+// Field: [16] RX_OK
+//
+// Interrupt flag 16. Packet received correctly. BLE mode: Packet received with
+// CRC OK, payload, and not to be ignored. IEEE 802.15.4 mode: Frame received
+// with CRC OK. Write zero to clear flag. Write to one has no effect.
+#define RFC_DBELL_RFCPEIFG_RX_OK 0x00010000
+#define RFC_DBELL_RFCPEIFG_RX_OK_BITN 16
+#define RFC_DBELL_RFCPEIFG_RX_OK_M 0x00010000
+#define RFC_DBELL_RFCPEIFG_RX_OK_S 16
+
+// Field: [15] IRQ15
+//
+// Interrupt flag 15. Write zero to clear flag. Write to one has no effect.
+#define RFC_DBELL_RFCPEIFG_IRQ15 0x00008000
+#define RFC_DBELL_RFCPEIFG_IRQ15_BITN 15
+#define RFC_DBELL_RFCPEIFG_IRQ15_M 0x00008000
+#define RFC_DBELL_RFCPEIFG_IRQ15_S 15
+
+// Field: [14] IRQ14
+//
+// Interrupt flag 14. Write zero to clear flag. Write to one has no effect.
+#define RFC_DBELL_RFCPEIFG_IRQ14 0x00004000
+#define RFC_DBELL_RFCPEIFG_IRQ14_BITN 14
+#define RFC_DBELL_RFCPEIFG_IRQ14_M 0x00004000
+#define RFC_DBELL_RFCPEIFG_IRQ14_S 14
+
+// Field: [13] FG_COMMAND_STARTED
+//
+// Interrupt flag 13. IEEE 802.15.4 mode only: A foreground radio operation
+// command has gone into active state.
+#define RFC_DBELL_RFCPEIFG_FG_COMMAND_STARTED 0x00002000
+#define RFC_DBELL_RFCPEIFG_FG_COMMAND_STARTED_BITN 13
+#define RFC_DBELL_RFCPEIFG_FG_COMMAND_STARTED_M 0x00002000
+#define RFC_DBELL_RFCPEIFG_FG_COMMAND_STARTED_S 13
+
+// Field: [12] COMMAND_STARTED
+//
+// Interrupt flag 12. A radio operation command has gone into active state.
+#define RFC_DBELL_RFCPEIFG_COMMAND_STARTED 0x00001000
+#define RFC_DBELL_RFCPEIFG_COMMAND_STARTED_BITN 12
+#define RFC_DBELL_RFCPEIFG_COMMAND_STARTED_M 0x00001000
+#define RFC_DBELL_RFCPEIFG_COMMAND_STARTED_S 12
+
+// Field: [11] TX_BUFFER_CHANGED
+//
+// Interrupt flag 11. BLE mode only: A buffer change is complete after
+// CMD_BLE_ADV_PAYLOAD. Write zero to clear flag. Write to one has no effect.
+#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED 0x00000800
+#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_BITN 11
+#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_M 0x00000800
+#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_S 11
+
+// Field: [10] TX_ENTRY_DONE
+//
+// Interrupt flag 10. Tx queue data entry state changed to finished. Write zero
+// to clear flag. Write to one has no effect.
+#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE 0x00000400
+#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_BITN 10
+#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_M 0x00000400
+#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_S 10
+
+// Field: [9] TX_RETRANS
+//
+// Interrupt flag 9. BLE mode only: Packet retransmitted. Write zero to clear
+// flag. Write to one has no effect.
+#define RFC_DBELL_RFCPEIFG_TX_RETRANS 0x00000200
+#define RFC_DBELL_RFCPEIFG_TX_RETRANS_BITN 9
+#define RFC_DBELL_RFCPEIFG_TX_RETRANS_M 0x00000200
+#define RFC_DBELL_RFCPEIFG_TX_RETRANS_S 9
+
+// Field: [8] TX_CTRL_ACK_ACK
+//
+// Interrupt flag 8. BLE mode only: Acknowledgement received on a transmitted
+// LL control packet, and acknowledgement transmitted for that packet. Write
+// zero to clear flag. Write to one has no effect.
+#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK 0x00000100
+#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_BITN 8
+#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_M 0x00000100
+#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_S 8
+
+// Field: [7] TX_CTRL_ACK
+//
+// Interrupt flag 7. BLE mode: Acknowledgement received on a transmitted LL
+// control packet. Write zero to clear flag. Write to one has no effect.
+#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK 0x00000080
+#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_BITN 7
+#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_M 0x00000080
+#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_S 7
+
+// Field: [6] TX_CTRL
+//
+// Interrupt flag 6. BLE mode: Transmitted LL control packet. Write zero to
+// clear flag. Write to one has no effect.
+#define RFC_DBELL_RFCPEIFG_TX_CTRL 0x00000040
+#define RFC_DBELL_RFCPEIFG_TX_CTRL_BITN 6
+#define RFC_DBELL_RFCPEIFG_TX_CTRL_M 0x00000040
+#define RFC_DBELL_RFCPEIFG_TX_CTRL_S 6
+
+// Field: [5] TX_ACK
+//
+// Interrupt flag 5. BLE mode: Acknowledgement received on a transmitted
+// packet. IEEE 802.15.4 mode: Transmitted automatic ACK frame. Write zero to
+// clear flag. Write to one has no effect.
+#define RFC_DBELL_RFCPEIFG_TX_ACK 0x00000020
+#define RFC_DBELL_RFCPEIFG_TX_ACK_BITN 5
+#define RFC_DBELL_RFCPEIFG_TX_ACK_M 0x00000020
+#define RFC_DBELL_RFCPEIFG_TX_ACK_S 5
+
+// Field: [4] TX_DONE
+//
+// Interrupt flag 4. Packet transmitted. (BLE mode: A packet has been
+// transmitted.) (IEEE 802.15.4 mode: A frame has been transmitted). Write zero
+// to clear flag. Write to one has no effect.
+#define RFC_DBELL_RFCPEIFG_TX_DONE 0x00000010
+#define RFC_DBELL_RFCPEIFG_TX_DONE_BITN 4
+#define RFC_DBELL_RFCPEIFG_TX_DONE_M 0x00000010
+#define RFC_DBELL_RFCPEIFG_TX_DONE_S 4
+
+// Field: [3] LAST_FG_COMMAND_DONE
+//
+// Interrupt flag 3. IEEE 802.15.4 mode only: The last foreground radio
+// operation command in a chain of commands has finished. Write zero to clear
+// flag. Write to one has no effect.
+#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE 0x00000008
+#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_BITN 3
+#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_M 0x00000008
+#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_S 3
+
+// Field: [2] FG_COMMAND_DONE
+//
+// Interrupt flag 2. IEEE 802.15.4 mode only: A foreground radio operation
+// command has finished. Write zero to clear flag. Write to one has no effect.
+#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE 0x00000004
+#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_BITN 2
+#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_M 0x00000004
+#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_S 2
+
+// Field: [1] LAST_COMMAND_DONE
+//
+// Interrupt flag 1. The last radio operation command in a chain of commands
+// has finished. (IEEE 802.15.4 mode: The last background level radio operation
+// command in a chain of commands has finished.) Write zero to clear flag.
+// Write to one has no effect.
+#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE 0x00000002
+#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_BITN 1
+#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_M 0x00000002
+#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_S 1
+
+// Field: [0] COMMAND_DONE
+//
+// Interrupt flag 0. A radio operation has finished. (IEEE 802.15.4 mode: A
+// background level radio operation command has finished.) Write zero to clear
+// flag. Write to one has no effect.
+#define RFC_DBELL_RFCPEIFG_COMMAND_DONE 0x00000001
+#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_BITN 0
+#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_M 0x00000001
+#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_DBELL_O_RFCPEIEN
+//
+//*****************************************************************************
+// Field: [31] INTERNAL_ERROR
+//
+// Interrupt enable for RFCPEIFG.INTERNAL_ERROR.
+#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR 0x80000000
+#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_BITN 31
+#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_M 0x80000000
+#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_S 31
+
+// Field: [30] BOOT_DONE
+//
+// Interrupt enable for RFCPEIFG.BOOT_DONE.
+#define RFC_DBELL_RFCPEIEN_BOOT_DONE 0x40000000
+#define RFC_DBELL_RFCPEIEN_BOOT_DONE_BITN 30
+#define RFC_DBELL_RFCPEIEN_BOOT_DONE_M 0x40000000
+#define RFC_DBELL_RFCPEIEN_BOOT_DONE_S 30
+
+// Field: [29] MODULES_UNLOCKED
+//
+// Interrupt enable for RFCPEIFG.MODULES_UNLOCKED.
+#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED 0x20000000
+#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_BITN 29
+#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_M 0x20000000
+#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_S 29
+
+// Field: [28] SYNTH_NO_LOCK
+//
+// Interrupt enable for RFCPEIFG.SYNTH_NO_LOCK.
+#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK 0x10000000
+#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_BITN 28
+#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_M 0x10000000
+#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_S 28
+
+// Field: [27] IRQ27
+//
+// Interrupt enable for RFCPEIFG.IRQ27.
+#define RFC_DBELL_RFCPEIEN_IRQ27 0x08000000
+#define RFC_DBELL_RFCPEIEN_IRQ27_BITN 27
+#define RFC_DBELL_RFCPEIEN_IRQ27_M 0x08000000
+#define RFC_DBELL_RFCPEIEN_IRQ27_S 27
+
+// Field: [26] RX_ABORTED
+//
+// Interrupt enable for RFCPEIFG.RX_ABORTED.
+#define RFC_DBELL_RFCPEIEN_RX_ABORTED 0x04000000
+#define RFC_DBELL_RFCPEIEN_RX_ABORTED_BITN 26
+#define RFC_DBELL_RFCPEIEN_RX_ABORTED_M 0x04000000
+#define RFC_DBELL_RFCPEIEN_RX_ABORTED_S 26
+
+// Field: [25] RX_N_DATA_WRITTEN
+//
+// Interrupt enable for RFCPEIFG.RX_N_DATA_WRITTEN.
+#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN 0x02000000
+#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_BITN 25
+#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_M 0x02000000
+#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_S 25
+
+// Field: [24] RX_DATA_WRITTEN
+//
+// Interrupt enable for RFCPEIFG.RX_DATA_WRITTEN.
+#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN 0x01000000
+#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_BITN 24
+#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_M 0x01000000
+#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_S 24
+
+// Field: [23] RX_ENTRY_DONE
+//
+// Interrupt enable for RFCPEIFG.RX_ENTRY_DONE.
+#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE 0x00800000
+#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_BITN 23
+#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_M 0x00800000
+#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_S 23
+
+// Field: [22] RX_BUF_FULL
+//
+// Interrupt enable for RFCPEIFG.RX_BUF_FULL.
+#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL 0x00400000
+#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_BITN 22
+#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_M 0x00400000
+#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_S 22
+
+// Field: [21] RX_CTRL_ACK
+//
+// Interrupt enable for RFCPEIFG.RX_CTRL_ACK.
+#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK 0x00200000
+#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_BITN 21
+#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_M 0x00200000
+#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_S 21
+
+// Field: [20] RX_CTRL
+//
+// Interrupt enable for RFCPEIFG.RX_CTRL.
+#define RFC_DBELL_RFCPEIEN_RX_CTRL 0x00100000
+#define RFC_DBELL_RFCPEIEN_RX_CTRL_BITN 20
+#define RFC_DBELL_RFCPEIEN_RX_CTRL_M 0x00100000
+#define RFC_DBELL_RFCPEIEN_RX_CTRL_S 20
+
+// Field: [19] RX_EMPTY
+//
+// Interrupt enable for RFCPEIFG.RX_EMPTY.
+#define RFC_DBELL_RFCPEIEN_RX_EMPTY 0x00080000
+#define RFC_DBELL_RFCPEIEN_RX_EMPTY_BITN 19
+#define RFC_DBELL_RFCPEIEN_RX_EMPTY_M 0x00080000
+#define RFC_DBELL_RFCPEIEN_RX_EMPTY_S 19
+
+// Field: [18] RX_IGNORED
+//
+// Interrupt enable for RFCPEIFG.RX_IGNORED.
+#define RFC_DBELL_RFCPEIEN_RX_IGNORED 0x00040000
+#define RFC_DBELL_RFCPEIEN_RX_IGNORED_BITN 18
+#define RFC_DBELL_RFCPEIEN_RX_IGNORED_M 0x00040000
+#define RFC_DBELL_RFCPEIEN_RX_IGNORED_S 18
+
+// Field: [17] RX_NOK
+//
+// Interrupt enable for RFCPEIFG.RX_NOK.
+#define RFC_DBELL_RFCPEIEN_RX_NOK 0x00020000
+#define RFC_DBELL_RFCPEIEN_RX_NOK_BITN 17
+#define RFC_DBELL_RFCPEIEN_RX_NOK_M 0x00020000
+#define RFC_DBELL_RFCPEIEN_RX_NOK_S 17
+
+// Field: [16] RX_OK
+//
+// Interrupt enable for RFCPEIFG.RX_OK.
+#define RFC_DBELL_RFCPEIEN_RX_OK 0x00010000
+#define RFC_DBELL_RFCPEIEN_RX_OK_BITN 16
+#define RFC_DBELL_RFCPEIEN_RX_OK_M 0x00010000
+#define RFC_DBELL_RFCPEIEN_RX_OK_S 16
+
+// Field: [15] IRQ15
+//
+// Interrupt enable for RFCPEIFG.IRQ15.
+#define RFC_DBELL_RFCPEIEN_IRQ15 0x00008000
+#define RFC_DBELL_RFCPEIEN_IRQ15_BITN 15
+#define RFC_DBELL_RFCPEIEN_IRQ15_M 0x00008000
+#define RFC_DBELL_RFCPEIEN_IRQ15_S 15
+
+// Field: [14] IRQ14
+//
+// Interrupt enable for RFCPEIFG.IRQ14.
+#define RFC_DBELL_RFCPEIEN_IRQ14 0x00004000
+#define RFC_DBELL_RFCPEIEN_IRQ14_BITN 14
+#define RFC_DBELL_RFCPEIEN_IRQ14_M 0x00004000
+#define RFC_DBELL_RFCPEIEN_IRQ14_S 14
+
+// Field: [13] FG_COMMAND_STARTED
+//
+// Interrupt enable for RFCPEIFG.FG_COMMAND_STARTED.
+#define RFC_DBELL_RFCPEIEN_FG_COMMAND_STARTED 0x00002000
+#define RFC_DBELL_RFCPEIEN_FG_COMMAND_STARTED_BITN 13
+#define RFC_DBELL_RFCPEIEN_FG_COMMAND_STARTED_M 0x00002000
+#define RFC_DBELL_RFCPEIEN_FG_COMMAND_STARTED_S 13
+
+// Field: [12] COMMAND_STARTED
+//
+// Interrupt enable for RFCPEIFG.COMMAND_STARTED.
+#define RFC_DBELL_RFCPEIEN_COMMAND_STARTED 0x00001000
+#define RFC_DBELL_RFCPEIEN_COMMAND_STARTED_BITN 12
+#define RFC_DBELL_RFCPEIEN_COMMAND_STARTED_M 0x00001000
+#define RFC_DBELL_RFCPEIEN_COMMAND_STARTED_S 12
+
+// Field: [11] TX_BUFFER_CHANGED
+//
+// Interrupt enable for RFCPEIFG.TX_BUFFER_CHANGED.
+#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED 0x00000800
+#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_BITN 11
+#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_M 0x00000800
+#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_S 11
+
+// Field: [10] TX_ENTRY_DONE
+//
+// Interrupt enable for RFCPEIFG.TX_ENTRY_DONE.
+#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE 0x00000400
+#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_BITN 10
+#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_M 0x00000400
+#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_S 10
+
+// Field: [9] TX_RETRANS
+//
+// Interrupt enable for RFCPEIFG.TX_RETRANS.
+#define RFC_DBELL_RFCPEIEN_TX_RETRANS 0x00000200
+#define RFC_DBELL_RFCPEIEN_TX_RETRANS_BITN 9
+#define RFC_DBELL_RFCPEIEN_TX_RETRANS_M 0x00000200
+#define RFC_DBELL_RFCPEIEN_TX_RETRANS_S 9
+
+// Field: [8] TX_CTRL_ACK_ACK
+//
+// Interrupt enable for RFCPEIFG.TX_CTRL_ACK_ACK.
+#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK 0x00000100
+#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_BITN 8
+#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_M 0x00000100
+#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_S 8
+
+// Field: [7] TX_CTRL_ACK
+//
+// Interrupt enable for RFCPEIFG.TX_CTRL_ACK.
+#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK 0x00000080
+#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_BITN 7
+#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_M 0x00000080
+#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_S 7
+
+// Field: [6] TX_CTRL
+//
+// Interrupt enable for RFCPEIFG.TX_CTRL.
+#define RFC_DBELL_RFCPEIEN_TX_CTRL 0x00000040
+#define RFC_DBELL_RFCPEIEN_TX_CTRL_BITN 6
+#define RFC_DBELL_RFCPEIEN_TX_CTRL_M 0x00000040
+#define RFC_DBELL_RFCPEIEN_TX_CTRL_S 6
+
+// Field: [5] TX_ACK
+//
+// Interrupt enable for RFCPEIFG.TX_ACK.
+#define RFC_DBELL_RFCPEIEN_TX_ACK 0x00000020
+#define RFC_DBELL_RFCPEIEN_TX_ACK_BITN 5
+#define RFC_DBELL_RFCPEIEN_TX_ACK_M 0x00000020
+#define RFC_DBELL_RFCPEIEN_TX_ACK_S 5
+
+// Field: [4] TX_DONE
+//
+// Interrupt enable for RFCPEIFG.TX_DONE.
+#define RFC_DBELL_RFCPEIEN_TX_DONE 0x00000010
+#define RFC_DBELL_RFCPEIEN_TX_DONE_BITN 4
+#define RFC_DBELL_RFCPEIEN_TX_DONE_M 0x00000010
+#define RFC_DBELL_RFCPEIEN_TX_DONE_S 4
+
+// Field: [3] LAST_FG_COMMAND_DONE
+//
+// Interrupt enable for RFCPEIFG.LAST_FG_COMMAND_DONE.
+#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE 0x00000008
+#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_BITN 3
+#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_M 0x00000008
+#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_S 3
+
+// Field: [2] FG_COMMAND_DONE
+//
+// Interrupt enable for RFCPEIFG.FG_COMMAND_DONE.
+#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE 0x00000004
+#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_BITN 2
+#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_M 0x00000004
+#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_S 2
+
+// Field: [1] LAST_COMMAND_DONE
+//
+// Interrupt enable for RFCPEIFG.LAST_COMMAND_DONE.
+#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE 0x00000002
+#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_BITN 1
+#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_M 0x00000002
+#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_S 1
+
+// Field: [0] COMMAND_DONE
+//
+// Interrupt enable for RFCPEIFG.COMMAND_DONE.
+#define RFC_DBELL_RFCPEIEN_COMMAND_DONE 0x00000001
+#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_BITN 0
+#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_M 0x00000001
+#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_DBELL_O_RFCPEISL
+//
+//*****************************************************************************
+// Field: [31] INTERNAL_ERROR
+//
+// Select which CPU interrupt vector the RFCPEIFG.INTERNAL_ERROR interrupt
+// should use.
+// ENUMs:
+// CPE1 Associate this interrupt line with INT_RF_CPE1
+// interrupt vector
+// CPE0 Associate this interrupt line with INT_RF_CPE0
+// interrupt vector
+#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR 0x80000000
+#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_BITN 31
+#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_M 0x80000000
+#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_S 31
+#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_CPE1 0x80000000
+#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_CPE0 0x00000000
+
+// Field: [30] BOOT_DONE
+//
+// Select which CPU interrupt vector the RFCPEIFG.BOOT_DONE interrupt should
+// use.
+// ENUMs:
+// CPE1 Associate this interrupt line with INT_RF_CPE1
+// interrupt vector
+// CPE0 Associate this interrupt line with INT_RF_CPE0
+// interrupt vector
+#define RFC_DBELL_RFCPEISL_BOOT_DONE 0x40000000
+#define RFC_DBELL_RFCPEISL_BOOT_DONE_BITN 30
+#define RFC_DBELL_RFCPEISL_BOOT_DONE_M 0x40000000
+#define RFC_DBELL_RFCPEISL_BOOT_DONE_S 30
+#define RFC_DBELL_RFCPEISL_BOOT_DONE_CPE1 0x40000000
+#define RFC_DBELL_RFCPEISL_BOOT_DONE_CPE0 0x00000000
+
+// Field: [29] MODULES_UNLOCKED
+//
+// Select which CPU interrupt vector the RFCPEIFG.MODULES_UNLOCKED interrupt
+// should use.
+// ENUMs:
+// CPE1 Associate this interrupt line with INT_RF_CPE1
+// interrupt vector
+// CPE0 Associate this interrupt line with INT_RF_CPE0
+// interrupt vector
+#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED 0x20000000
+#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_BITN 29
+#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_M 0x20000000
+#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_S 29
+#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_CPE1 0x20000000
+#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_CPE0 0x00000000
+
+// Field: [28] SYNTH_NO_LOCK
+//
+// Select which CPU interrupt vector the RFCPEIFG.SYNTH_NO_LOCK interrupt
+// should use.
+// ENUMs:
+// CPE1 Associate this interrupt line with INT_RF_CPE1
+// interrupt vector
+// CPE0 Associate this interrupt line with INT_RF_CPE0
+// interrupt vector
+#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK 0x10000000
+#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_BITN 28
+#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_M 0x10000000
+#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_S 28
+#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_CPE1 0x10000000
+#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_CPE0 0x00000000
+
+// Field: [27] IRQ27
+//
+// Select which CPU interrupt vector the RFCPEIFG.IRQ27 interrupt should use.
+// ENUMs:
+// CPE1 Associate this interrupt line with INT_RF_CPE1
+// interrupt vector
+// CPE0 Associate this interrupt line with INT_RF_CPE0
+// interrupt vector
+#define RFC_DBELL_RFCPEISL_IRQ27 0x08000000
+#define RFC_DBELL_RFCPEISL_IRQ27_BITN 27
+#define RFC_DBELL_RFCPEISL_IRQ27_M 0x08000000
+#define RFC_DBELL_RFCPEISL_IRQ27_S 27
+#define RFC_DBELL_RFCPEISL_IRQ27_CPE1 0x08000000
+#define RFC_DBELL_RFCPEISL_IRQ27_CPE0 0x00000000
+
+// Field: [26] RX_ABORTED
+//
+// Select which CPU interrupt vector the RFCPEIFG.RX_ABORTED interrupt should
+// use.
+// ENUMs:
+// CPE1 Associate this interrupt line with INT_RF_CPE1
+// interrupt vector
+// CPE0 Associate this interrupt line with INT_RF_CPE0
+// interrupt vector
+#define RFC_DBELL_RFCPEISL_RX_ABORTED 0x04000000
+#define RFC_DBELL_RFCPEISL_RX_ABORTED_BITN 26
+#define RFC_DBELL_RFCPEISL_RX_ABORTED_M 0x04000000
+#define RFC_DBELL_RFCPEISL_RX_ABORTED_S 26
+#define RFC_DBELL_RFCPEISL_RX_ABORTED_CPE1 0x04000000
+#define RFC_DBELL_RFCPEISL_RX_ABORTED_CPE0 0x00000000
+
+// Field: [25] RX_N_DATA_WRITTEN
+//
+// Select which CPU interrupt vector the RFCPEIFG.RX_N_DATA_WRITTEN interrupt
+// should use.
+// ENUMs:
+// CPE1 Associate this interrupt line with INT_RF_CPE1
+// interrupt vector
+// CPE0 Associate this interrupt line with INT_RF_CPE0
+// interrupt vector
+#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN 0x02000000
+#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_BITN 25
+#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_M 0x02000000
+#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_S 25
+#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_CPE1 0x02000000
+#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_CPE0 0x00000000
+
+// Field: [24] RX_DATA_WRITTEN
+//
+// Select which CPU interrupt vector the RFCPEIFG.RX_DATA_WRITTEN interrupt
+// should use.
+// ENUMs:
+// CPE1 Associate this interrupt line with INT_RF_CPE1
+// interrupt vector
+// CPE0 Associate this interrupt line with INT_RF_CPE0
+// interrupt vector
+#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN 0x01000000
+#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_BITN 24
+#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_M 0x01000000
+#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_S 24
+#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_CPE1 0x01000000
+#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_CPE0 0x00000000
+
+// Field: [23] RX_ENTRY_DONE
+//
+// Select which CPU interrupt vector the RFCPEIFG.RX_ENTRY_DONE interrupt
+// should use.
+// ENUMs:
+// CPE1 Associate this interrupt line with INT_RF_CPE1
+// interrupt vector
+// CPE0 Associate this interrupt line with INT_RF_CPE0
+// interrupt vector
+#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE 0x00800000
+#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_BITN 23
+#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_M 0x00800000
+#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_S 23
+#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_CPE1 0x00800000
+#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_CPE0 0x00000000
+
+// Field: [22] RX_BUF_FULL
+//
+// Select which CPU interrupt vector the RFCPEIFG.RX_BUF_FULL interrupt should
+// use.
+// ENUMs:
+// CPE1 Associate this interrupt line with INT_RF_CPE1
+// interrupt vector
+// CPE0 Associate this interrupt line with INT_RF_CPE0
+// interrupt vector
+#define RFC_DBELL_RFCPEISL_RX_BUF_FULL 0x00400000
+#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_BITN 22
+#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_M 0x00400000
+#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_S 22
+#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_CPE1 0x00400000
+#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_CPE0 0x00000000
+
+// Field: [21] RX_CTRL_ACK
+//
+// Select which CPU interrupt vector the RFCPEIFG.RX_CTRL_ACK interrupt should
+// use.
+// ENUMs:
+// CPE1 Associate this interrupt line with INT_RF_CPE1
+// interrupt vector
+// CPE0 Associate this interrupt line with INT_RF_CPE0
+// interrupt vector
+#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK 0x00200000
+#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_BITN 21
+#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_M 0x00200000
+#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_S 21
+#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_CPE1 0x00200000
+#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_CPE0 0x00000000
+
+// Field: [20] RX_CTRL
+//
+// Select which CPU interrupt vector the RFCPEIFG.RX_CTRL interrupt should use.
+// ENUMs:
+// CPE1 Associate this interrupt line with INT_RF_CPE1
+// interrupt vector
+// CPE0 Associate this interrupt line with INT_RF_CPE0
+// interrupt vector
+#define RFC_DBELL_RFCPEISL_RX_CTRL 0x00100000
+#define RFC_DBELL_RFCPEISL_RX_CTRL_BITN 20
+#define RFC_DBELL_RFCPEISL_RX_CTRL_M 0x00100000
+#define RFC_DBELL_RFCPEISL_RX_CTRL_S 20
+#define RFC_DBELL_RFCPEISL_RX_CTRL_CPE1 0x00100000
+#define RFC_DBELL_RFCPEISL_RX_CTRL_CPE0 0x00000000
+
+// Field: [19] RX_EMPTY
+//
+// Select which CPU interrupt vector the RFCPEIFG.RX_EMPTY interrupt should
+// use.
+// ENUMs:
+// CPE1 Associate this interrupt line with INT_RF_CPE1
+// interrupt vector
+// CPE0 Associate this interrupt line with INT_RF_CPE0
+// interrupt vector
+#define RFC_DBELL_RFCPEISL_RX_EMPTY 0x00080000
+#define RFC_DBELL_RFCPEISL_RX_EMPTY_BITN 19
+#define RFC_DBELL_RFCPEISL_RX_EMPTY_M 0x00080000
+#define RFC_DBELL_RFCPEISL_RX_EMPTY_S 19
+#define RFC_DBELL_RFCPEISL_RX_EMPTY_CPE1 0x00080000
+#define RFC_DBELL_RFCPEISL_RX_EMPTY_CPE0 0x00000000
+
+// Field: [18] RX_IGNORED
+//
+// Select which CPU interrupt vector the RFCPEIFG.RX_IGNORED interrupt should
+// use.
+// ENUMs:
+// CPE1 Associate this interrupt line with INT_RF_CPE1
+// interrupt vector
+// CPE0 Associate this interrupt line with INT_RF_CPE0
+// interrupt vector
+#define RFC_DBELL_RFCPEISL_RX_IGNORED 0x00040000
+#define RFC_DBELL_RFCPEISL_RX_IGNORED_BITN 18
+#define RFC_DBELL_RFCPEISL_RX_IGNORED_M 0x00040000
+#define RFC_DBELL_RFCPEISL_RX_IGNORED_S 18
+#define RFC_DBELL_RFCPEISL_RX_IGNORED_CPE1 0x00040000
+#define RFC_DBELL_RFCPEISL_RX_IGNORED_CPE0 0x00000000
+
+// Field: [17] RX_NOK
+//
+// Select which CPU interrupt vector the RFCPEIFG.RX_NOK interrupt should use.
+// ENUMs:
+// CPE1 Associate this interrupt line with INT_RF_CPE1
+// interrupt vector
+// CPE0 Associate this interrupt line with INT_RF_CPE0
+// interrupt vector
+#define RFC_DBELL_RFCPEISL_RX_NOK 0x00020000
+#define RFC_DBELL_RFCPEISL_RX_NOK_BITN 17
+#define RFC_DBELL_RFCPEISL_RX_NOK_M 0x00020000
+#define RFC_DBELL_RFCPEISL_RX_NOK_S 17
+#define RFC_DBELL_RFCPEISL_RX_NOK_CPE1 0x00020000
+#define RFC_DBELL_RFCPEISL_RX_NOK_CPE0 0x00000000
+
+// Field: [16] RX_OK
+//
+// Select which CPU interrupt vector the RFCPEIFG.RX_OK interrupt should use.
+// ENUMs:
+// CPE1 Associate this interrupt line with INT_RF_CPE1
+// interrupt vector
+// CPE0 Associate this interrupt line with INT_RF_CPE0
+// interrupt vector
+#define RFC_DBELL_RFCPEISL_RX_OK 0x00010000
+#define RFC_DBELL_RFCPEISL_RX_OK_BITN 16
+#define RFC_DBELL_RFCPEISL_RX_OK_M 0x00010000
+#define RFC_DBELL_RFCPEISL_RX_OK_S 16
+#define RFC_DBELL_RFCPEISL_RX_OK_CPE1 0x00010000
+#define RFC_DBELL_RFCPEISL_RX_OK_CPE0 0x00000000
+
+// Field: [15] IRQ15
+//
+// Select which CPU interrupt vector the RFCPEIFG.IRQ15 interrupt should use.
+// ENUMs:
+// CPE1 Associate this interrupt line with INT_RF_CPE1
+// interrupt vector
+// CPE0 Associate this interrupt line with INT_RF_CPE0
+// interrupt vector
+#define RFC_DBELL_RFCPEISL_IRQ15 0x00008000
+#define RFC_DBELL_RFCPEISL_IRQ15_BITN 15
+#define RFC_DBELL_RFCPEISL_IRQ15_M 0x00008000
+#define RFC_DBELL_RFCPEISL_IRQ15_S 15
+#define RFC_DBELL_RFCPEISL_IRQ15_CPE1 0x00008000
+#define RFC_DBELL_RFCPEISL_IRQ15_CPE0 0x00000000
+
+// Field: [14] IRQ14
+//
+// Select which CPU interrupt vector the RFCPEIFG.IRQ14 interrupt should use.
+// ENUMs:
+// CPE1 Associate this interrupt line with INT_RF_CPE1
+// interrupt vector
+// CPE0 Associate this interrupt line with INT_RF_CPE0
+// interrupt vector
+#define RFC_DBELL_RFCPEISL_IRQ14 0x00004000
+#define RFC_DBELL_RFCPEISL_IRQ14_BITN 14
+#define RFC_DBELL_RFCPEISL_IRQ14_M 0x00004000
+#define RFC_DBELL_RFCPEISL_IRQ14_S 14
+#define RFC_DBELL_RFCPEISL_IRQ14_CPE1 0x00004000
+#define RFC_DBELL_RFCPEISL_IRQ14_CPE0 0x00000000
+
+// Field: [13] FG_COMMAND_STARTED
+//
+// Select which CPU interrupt vector the RFCPEIFG.FG_COMMAND_STARTED interrupt
+// should use.
+// ENUMs:
+// CPE1 Associate this interrupt line with INT_RF_CPE1
+// interrupt vector
+// CPE0 Associate this interrupt line with INT_RF_CPE0
+// interrupt vector
+#define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED 0x00002000
+#define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED_BITN 13
+#define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED_M 0x00002000
+#define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED_S 13
+#define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED_CPE1 0x00002000
+#define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED_CPE0 0x00000000
+
+// Field: [12] COMMAND_STARTED
+//
+// Select which CPU interrupt vector the RFCPEIFG.COMMAND_STARTED interrupt
+// should use.
+// ENUMs:
+// CPE1 Associate this interrupt line with INT_RF_CPE1
+// interrupt vector
+// CPE0 Associate this interrupt line with INT_RF_CPE0
+// interrupt vector
+#define RFC_DBELL_RFCPEISL_COMMAND_STARTED 0x00001000
+#define RFC_DBELL_RFCPEISL_COMMAND_STARTED_BITN 12
+#define RFC_DBELL_RFCPEISL_COMMAND_STARTED_M 0x00001000
+#define RFC_DBELL_RFCPEISL_COMMAND_STARTED_S 12
+#define RFC_DBELL_RFCPEISL_COMMAND_STARTED_CPE1 0x00001000
+#define RFC_DBELL_RFCPEISL_COMMAND_STARTED_CPE0 0x00000000
+
+// Field: [11] TX_BUFFER_CHANGED
+//
+// Select which CPU interrupt vector the RFCPEIFG.TX_BUFFER_CHANGED interrupt
+// should use.
+// ENUMs:
+// CPE1 Associate this interrupt line with INT_RF_CPE1
+// interrupt vector
+// CPE0 Associate this interrupt line with INT_RF_CPE0
+// interrupt vector
+#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED 0x00000800
+#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_BITN 11
+#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_M 0x00000800
+#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_S 11
+#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_CPE1 0x00000800
+#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_CPE0 0x00000000
+
+// Field: [10] TX_ENTRY_DONE
+//
+// Select which CPU interrupt vector the RFCPEIFG.TX_ENTRY_DONE interrupt
+// should use.
+// ENUMs:
+// CPE1 Associate this interrupt line with INT_RF_CPE1
+// interrupt vector
+// CPE0 Associate this interrupt line with INT_RF_CPE0
+// interrupt vector
+#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE 0x00000400
+#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_BITN 10
+#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_M 0x00000400
+#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_S 10
+#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_CPE1 0x00000400
+#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_CPE0 0x00000000
+
+// Field: [9] TX_RETRANS
+//
+// Select which CPU interrupt vector the RFCPEIFG.TX_RETRANS interrupt should
+// use.
+// ENUMs:
+// CPE1 Associate this interrupt line with INT_RF_CPE1
+// interrupt vector
+// CPE0 Associate this interrupt line with INT_RF_CPE0
+// interrupt vector
+#define RFC_DBELL_RFCPEISL_TX_RETRANS 0x00000200
+#define RFC_DBELL_RFCPEISL_TX_RETRANS_BITN 9
+#define RFC_DBELL_RFCPEISL_TX_RETRANS_M 0x00000200
+#define RFC_DBELL_RFCPEISL_TX_RETRANS_S 9
+#define RFC_DBELL_RFCPEISL_TX_RETRANS_CPE1 0x00000200
+#define RFC_DBELL_RFCPEISL_TX_RETRANS_CPE0 0x00000000
+
+// Field: [8] TX_CTRL_ACK_ACK
+//
+// Select which CPU interrupt vector the RFCPEIFG.TX_CTRL_ACK_ACK interrupt
+// should use.
+// ENUMs:
+// CPE1 Associate this interrupt line with INT_RF_CPE1
+// interrupt vector
+// CPE0 Associate this interrupt line with INT_RF_CPE0
+// interrupt vector
+#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK 0x00000100
+#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_BITN 8
+#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_M 0x00000100
+#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_S 8
+#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_CPE1 0x00000100
+#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_CPE0 0x00000000
+
+// Field: [7] TX_CTRL_ACK
+//
+// Select which CPU interrupt vector the RFCPEIFG.TX_CTRL_ACK interrupt should
+// use.
+// ENUMs:
+// CPE1 Associate this interrupt line with INT_RF_CPE1
+// interrupt vector
+// CPE0 Associate this interrupt line with INT_RF_CPE0
+// interrupt vector
+#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK 0x00000080
+#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_BITN 7
+#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_M 0x00000080
+#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_S 7
+#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_CPE1 0x00000080
+#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_CPE0 0x00000000
+
+// Field: [6] TX_CTRL
+//
+// Select which CPU interrupt vector the RFCPEIFG.TX_CTRL interrupt should use.
+// ENUMs:
+// CPE1 Associate this interrupt line with INT_RF_CPE1
+// interrupt vector
+// CPE0 Associate this interrupt line with INT_RF_CPE0
+// interrupt vector
+#define RFC_DBELL_RFCPEISL_TX_CTRL 0x00000040
+#define RFC_DBELL_RFCPEISL_TX_CTRL_BITN 6
+#define RFC_DBELL_RFCPEISL_TX_CTRL_M 0x00000040
+#define RFC_DBELL_RFCPEISL_TX_CTRL_S 6
+#define RFC_DBELL_RFCPEISL_TX_CTRL_CPE1 0x00000040
+#define RFC_DBELL_RFCPEISL_TX_CTRL_CPE0 0x00000000
+
+// Field: [5] TX_ACK
+//
+// Select which CPU interrupt vector the RFCPEIFG.TX_ACK interrupt should use.
+// ENUMs:
+// CPE1 Associate this interrupt line with INT_RF_CPE1
+// interrupt vector
+// CPE0 Associate this interrupt line with INT_RF_CPE0
+// interrupt vector
+#define RFC_DBELL_RFCPEISL_TX_ACK 0x00000020
+#define RFC_DBELL_RFCPEISL_TX_ACK_BITN 5
+#define RFC_DBELL_RFCPEISL_TX_ACK_M 0x00000020
+#define RFC_DBELL_RFCPEISL_TX_ACK_S 5
+#define RFC_DBELL_RFCPEISL_TX_ACK_CPE1 0x00000020
+#define RFC_DBELL_RFCPEISL_TX_ACK_CPE0 0x00000000
+
+// Field: [4] TX_DONE
+//
+// Select which CPU interrupt vector the RFCPEIFG.TX_DONE interrupt should use.
+// ENUMs:
+// CPE1 Associate this interrupt line with INT_RF_CPE1
+// interrupt vector
+// CPE0 Associate this interrupt line with INT_RF_CPE0
+// interrupt vector
+#define RFC_DBELL_RFCPEISL_TX_DONE 0x00000010
+#define RFC_DBELL_RFCPEISL_TX_DONE_BITN 4
+#define RFC_DBELL_RFCPEISL_TX_DONE_M 0x00000010
+#define RFC_DBELL_RFCPEISL_TX_DONE_S 4
+#define RFC_DBELL_RFCPEISL_TX_DONE_CPE1 0x00000010
+#define RFC_DBELL_RFCPEISL_TX_DONE_CPE0 0x00000000
+
+// Field: [3] LAST_FG_COMMAND_DONE
+//
+// Select which CPU interrupt vector the RFCPEIFG.LAST_FG_COMMAND_DONE
+// interrupt should use.
+// ENUMs:
+// CPE1 Associate this interrupt line with INT_RF_CPE1
+// interrupt vector
+// CPE0 Associate this interrupt line with INT_RF_CPE0
+// interrupt vector
+#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE 0x00000008
+#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_BITN 3
+#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_M 0x00000008
+#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_S 3
+#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_CPE1 0x00000008
+#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_CPE0 0x00000000
+
+// Field: [2] FG_COMMAND_DONE
+//
+// Select which CPU interrupt vector the RFCPEIFG.FG_COMMAND_DONE interrupt
+// should use.
+// ENUMs:
+// CPE1 Associate this interrupt line with INT_RF_CPE1
+// interrupt vector
+// CPE0 Associate this interrupt line with INT_RF_CPE0
+// interrupt vector
+#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE 0x00000004
+#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_BITN 2
+#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_M 0x00000004
+#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_S 2
+#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_CPE1 0x00000004
+#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_CPE0 0x00000000
+
+// Field: [1] LAST_COMMAND_DONE
+//
+// Select which CPU interrupt vector the RFCPEIFG.LAST_COMMAND_DONE interrupt
+// should use.
+// ENUMs:
+// CPE1 Associate this interrupt line with INT_RF_CPE1
+// interrupt vector
+// CPE0 Associate this interrupt line with INT_RF_CPE0
+// interrupt vector
+#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE 0x00000002
+#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_BITN 1
+#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_M 0x00000002
+#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_S 1
+#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_CPE1 0x00000002
+#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_CPE0 0x00000000
+
+// Field: [0] COMMAND_DONE
+//
+// Select which CPU interrupt vector the RFCPEIFG.COMMAND_DONE interrupt should
+// use.
+// ENUMs:
+// CPE1 Associate this interrupt line with INT_RF_CPE1
+// interrupt vector
+// CPE0 Associate this interrupt line with INT_RF_CPE0
+// interrupt vector
+#define RFC_DBELL_RFCPEISL_COMMAND_DONE 0x00000001
+#define RFC_DBELL_RFCPEISL_COMMAND_DONE_BITN 0
+#define RFC_DBELL_RFCPEISL_COMMAND_DONE_M 0x00000001
+#define RFC_DBELL_RFCPEISL_COMMAND_DONE_S 0
+#define RFC_DBELL_RFCPEISL_COMMAND_DONE_CPE1 0x00000001
+#define RFC_DBELL_RFCPEISL_COMMAND_DONE_CPE0 0x00000000
+
+//*****************************************************************************
+//
+// Register: RFC_DBELL_O_RFACKIFG
+//
+//*****************************************************************************
+// Field: [0] ACKFLAG
+//
+// Interrupt flag for Command ACK
+#define RFC_DBELL_RFACKIFG_ACKFLAG 0x00000001
+#define RFC_DBELL_RFACKIFG_ACKFLAG_BITN 0
+#define RFC_DBELL_RFACKIFG_ACKFLAG_M 0x00000001
+#define RFC_DBELL_RFACKIFG_ACKFLAG_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_DBELL_O_SYSGPOCTL
+//
+//*****************************************************************************
+// Field: [15:12] GPOCTL3
+//
+// RF Core GPO control bit 3. Selects which signal to output on the RF Core GPO
+// line 3.
+// ENUMs:
+// RATGPO3 RAT GPO line 3
+// RATGPO2 RAT GPO line 2
+// RATGPO1 RAT GPO line 1
+// RATGPO0 RAT GPO line 0
+// RFEGPO3 RFE GPO line 3
+// RFEGPO2 RFE GPO line 2
+// RFEGPO1 RFE GPO line 1
+// RFEGPO0 RFE GPO line 0
+// MCEGPO3 MCE GPO line 3
+// MCEGPO2 MCE GPO line 2
+// MCEGPO1 MCE GPO line 1
+// MCEGPO0 MCE GPO line 0
+// CPEGPO3 CPE GPO line 3
+// CPEGPO2 CPE GPO line 2
+// CPEGPO1 CPE GPO line 1
+// CPEGPO0 CPE GPO line 0
+#define RFC_DBELL_SYSGPOCTL_GPOCTL3_W 4
+#define RFC_DBELL_SYSGPOCTL_GPOCTL3_M 0x0000F000
+#define RFC_DBELL_SYSGPOCTL_GPOCTL3_S 12
+#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO3 0x0000F000
+#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO2 0x0000E000
+#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO1 0x0000D000
+#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO0 0x0000C000
+#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO3 0x0000B000
+#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO2 0x0000A000
+#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO1 0x00009000
+#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO0 0x00008000
+#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO3 0x00007000
+#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO2 0x00006000
+#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO1 0x00005000
+#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO0 0x00004000
+#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO3 0x00003000
+#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO2 0x00002000
+#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO1 0x00001000
+#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO0 0x00000000
+
+// Field: [11:8] GPOCTL2
+//
+// RF Core GPO control bit 2. Selects which signal to output on the RF Core GPO
+// line 2.
+// ENUMs:
+// RATGPO3 RAT GPO line 3
+// RATGPO2 RAT GPO line 2
+// RATGPO1 RAT GPO line 1
+// RATGPO0 RAT GPO line 0
+// RFEGPO3 RFE GPO line 3
+// RFEGPO2 RFE GPO line 2
+// RFEGPO1 RFE GPO line 1
+// RFEGPO0 RFE GPO line 0
+// MCEGPO3 MCE GPO line 3
+// MCEGPO2 MCE GPO line 2
+// MCEGPO1 MCE GPO line 1
+// MCEGPO0 MCE GPO line 0
+// CPEGPO3 CPE GPO line 3
+// CPEGPO2 CPE GPO line 2
+// CPEGPO1 CPE GPO line 1
+// CPEGPO0 CPE GPO line 0
+#define RFC_DBELL_SYSGPOCTL_GPOCTL2_W 4
+#define RFC_DBELL_SYSGPOCTL_GPOCTL2_M 0x00000F00
+#define RFC_DBELL_SYSGPOCTL_GPOCTL2_S 8
+#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO3 0x00000F00
+#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO2 0x00000E00
+#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO1 0x00000D00
+#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO0 0x00000C00
+#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO3 0x00000B00
+#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO2 0x00000A00
+#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO1 0x00000900
+#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO0 0x00000800
+#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO3 0x00000700
+#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO2 0x00000600
+#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO1 0x00000500
+#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO0 0x00000400
+#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO3 0x00000300
+#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO2 0x00000200
+#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO1 0x00000100
+#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO0 0x00000000
+
+// Field: [7:4] GPOCTL1
+//
+// RF Core GPO control bit 1. Selects which signal to output on the RF Core GPO
+// line 1.
+// ENUMs:
+// RATGPO3 RAT GPO line 3
+// RATGPO2 RAT GPO line 2
+// RATGPO1 RAT GPO line 1
+// RATGPO0 RAT GPO line 0
+// RFEGPO3 RFE GPO line 3
+// RFEGPO2 RFE GPO line 2
+// RFEGPO1 RFE GPO line 1
+// RFEGPO0 RFE GPO line 0
+// MCEGPO3 MCE GPO line 3
+// MCEGPO2 MCE GPO line 2
+// MCEGPO1 MCE GPO line 1
+// MCEGPO0 MCE GPO line 0
+// CPEGPO3 CPE GPO line 3
+// CPEGPO2 CPE GPO line 2
+// CPEGPO1 CPE GPO line 1
+// CPEGPO0 CPE GPO line 0
+#define RFC_DBELL_SYSGPOCTL_GPOCTL1_W 4
+#define RFC_DBELL_SYSGPOCTL_GPOCTL1_M 0x000000F0
+#define RFC_DBELL_SYSGPOCTL_GPOCTL1_S 4
+#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO3 0x000000F0
+#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO2 0x000000E0
+#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO1 0x000000D0
+#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO0 0x000000C0
+#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO3 0x000000B0
+#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO2 0x000000A0
+#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO1 0x00000090
+#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO0 0x00000080
+#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO3 0x00000070
+#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO2 0x00000060
+#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO1 0x00000050
+#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO0 0x00000040
+#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO3 0x00000030
+#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO2 0x00000020
+#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO1 0x00000010
+#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO0 0x00000000
+
+// Field: [3:0] GPOCTL0
+//
+// RF Core GPO control bit 0. Selects which signal to output on the RF Core GPO
+// line 0.
+// ENUMs:
+// RATGPO3 RAT GPO line 3
+// RATGPO2 RAT GPO line 2
+// RATGPO1 RAT GPO line 1
+// RATGPO0 RAT GPO line 0
+// RFEGPO3 RFE GPO line 3
+// RFEGPO2 RFE GPO line 2
+// RFEGPO1 RFE GPO line 1
+// RFEGPO0 RFE GPO line 0
+// MCEGPO3 MCE GPO line 3
+// MCEGPO2 MCE GPO line 2
+// MCEGPO1 MCE GPO line 1
+// MCEGPO0 MCE GPO line 0
+// CPEGPO3 CPE GPO line 3
+// CPEGPO2 CPE GPO line 2
+// CPEGPO1 CPE GPO line 1
+// CPEGPO0 CPE GPO line 0
+#define RFC_DBELL_SYSGPOCTL_GPOCTL0_W 4
+#define RFC_DBELL_SYSGPOCTL_GPOCTL0_M 0x0000000F
+#define RFC_DBELL_SYSGPOCTL_GPOCTL0_S 0
+#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO3 0x0000000F
+#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO2 0x0000000E
+#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO1 0x0000000D
+#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO0 0x0000000C
+#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO3 0x0000000B
+#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO2 0x0000000A
+#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO1 0x00000009
+#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO0 0x00000008
+#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO3 0x00000007
+#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO2 0x00000006
+#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO1 0x00000005
+#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO0 0x00000004
+#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO3 0x00000003
+#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO2 0x00000002
+#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO1 0x00000001
+#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO0 0x00000000
+
+
+#endif // __RFC_DBELL__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_pwr.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_pwr.h
new file mode 100644
index 0000000..355626e
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_pwr.h
@@ -0,0 +1,153 @@
+/******************************************************************************
+* Filename: hw_rfc_pwr_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_RFC_PWR_H__
+#define __HW_RFC_PWR_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// RFC_PWR component
+//
+//*****************************************************************************
+// RF Core Power Management and Clock Enable
+#define RFC_PWR_O_PWMCLKEN 0x00000000
+
+//*****************************************************************************
+//
+// Register: RFC_PWR_O_PWMCLKEN
+//
+//*****************************************************************************
+// Field: [10] RFCTRC
+//
+// Enable clock to the RF Core Tracer (RFCTRC) module.
+#define RFC_PWR_PWMCLKEN_RFCTRC 0x00000400
+#define RFC_PWR_PWMCLKEN_RFCTRC_BITN 10
+#define RFC_PWR_PWMCLKEN_RFCTRC_M 0x00000400
+#define RFC_PWR_PWMCLKEN_RFCTRC_S 10
+
+// Field: [9] FSCA
+//
+// Enable clock to the Frequency Synthesizer Calibration Accelerator (FSCA)
+// module.
+#define RFC_PWR_PWMCLKEN_FSCA 0x00000200
+#define RFC_PWR_PWMCLKEN_FSCA_BITN 9
+#define RFC_PWR_PWMCLKEN_FSCA_M 0x00000200
+#define RFC_PWR_PWMCLKEN_FSCA_S 9
+
+// Field: [8] PHA
+//
+// Enable clock to the Packet Handling Accelerator (PHA) module.
+#define RFC_PWR_PWMCLKEN_PHA 0x00000100
+#define RFC_PWR_PWMCLKEN_PHA_BITN 8
+#define RFC_PWR_PWMCLKEN_PHA_M 0x00000100
+#define RFC_PWR_PWMCLKEN_PHA_S 8
+
+// Field: [7] RAT
+//
+// Enable clock to the Radio Timer (RAT) module.
+#define RFC_PWR_PWMCLKEN_RAT 0x00000080
+#define RFC_PWR_PWMCLKEN_RAT_BITN 7
+#define RFC_PWR_PWMCLKEN_RAT_M 0x00000080
+#define RFC_PWR_PWMCLKEN_RAT_S 7
+
+// Field: [6] RFERAM
+//
+// Enable clock to the RF Engine RAM module.
+#define RFC_PWR_PWMCLKEN_RFERAM 0x00000040
+#define RFC_PWR_PWMCLKEN_RFERAM_BITN 6
+#define RFC_PWR_PWMCLKEN_RFERAM_M 0x00000040
+#define RFC_PWR_PWMCLKEN_RFERAM_S 6
+
+// Field: [5] RFE
+//
+// Enable clock to the RF Engine (RFE) module.
+#define RFC_PWR_PWMCLKEN_RFE 0x00000020
+#define RFC_PWR_PWMCLKEN_RFE_BITN 5
+#define RFC_PWR_PWMCLKEN_RFE_M 0x00000020
+#define RFC_PWR_PWMCLKEN_RFE_S 5
+
+// Field: [4] MDMRAM
+//
+// Enable clock to the Modem RAM module.
+#define RFC_PWR_PWMCLKEN_MDMRAM 0x00000010
+#define RFC_PWR_PWMCLKEN_MDMRAM_BITN 4
+#define RFC_PWR_PWMCLKEN_MDMRAM_M 0x00000010
+#define RFC_PWR_PWMCLKEN_MDMRAM_S 4
+
+// Field: [3] MDM
+//
+// Enable clock to the Modem (MDM) module.
+#define RFC_PWR_PWMCLKEN_MDM 0x00000008
+#define RFC_PWR_PWMCLKEN_MDM_BITN 3
+#define RFC_PWR_PWMCLKEN_MDM_M 0x00000008
+#define RFC_PWR_PWMCLKEN_MDM_S 3
+
+// Field: [2] CPERAM
+//
+// Enable clock to the Command and Packet Engine (CPE) RAM module. As part of
+// RF Core initialization, set this bit together with CPE bit to enable CPE to
+// boot.
+#define RFC_PWR_PWMCLKEN_CPERAM 0x00000004
+#define RFC_PWR_PWMCLKEN_CPERAM_BITN 2
+#define RFC_PWR_PWMCLKEN_CPERAM_M 0x00000004
+#define RFC_PWR_PWMCLKEN_CPERAM_S 2
+
+// Field: [1] CPE
+//
+// Enable processor clock (hclk) to the Command and Packet Engine (CPE). As
+// part of RF Core initialization, set this bit together with CPERAM bit to
+// enable CPE to boot.
+#define RFC_PWR_PWMCLKEN_CPE 0x00000002
+#define RFC_PWR_PWMCLKEN_CPE_BITN 1
+#define RFC_PWR_PWMCLKEN_CPE_M 0x00000002
+#define RFC_PWR_PWMCLKEN_CPE_S 1
+
+// Field: [0] RFC
+//
+// Enable essential clocks for the RF Core interface. This includes the
+// interconnect, the radio doorbell DBELL command interface, the power
+// management (PWR) clock control module, and bus clock (sclk) for the CPE. To
+// remove possibility of locking yourself out from the RF Core, this bit can
+// not be cleared. If you need to disable all clocks to the RF Core, see the
+// PRCM:RFCCLKG.CLK_EN register.
+#define RFC_PWR_PWMCLKEN_RFC 0x00000001
+#define RFC_PWR_PWMCLKEN_RFC_BITN 0
+#define RFC_PWR_PWMCLKEN_RFC_M 0x00000001
+#define RFC_PWR_PWMCLKEN_RFC_S 0
+
+
+#endif // __RFC_PWR__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_rat.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_rat.h
new file mode 100644
index 0000000..4f68d8d
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_rat.h
@@ -0,0 +1,198 @@
+/******************************************************************************
+* Filename: hw_rfc_rat_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_RFC_RAT_H__
+#define __HW_RFC_RAT_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// RFC_RAT component
+//
+//*****************************************************************************
+// Radio Timer Counter Value
+#define RFC_RAT_O_RATCNT 0x00000004
+
+// Timer Channel 0 Capture/Compare Register
+#define RFC_RAT_O_RATCH0VAL 0x00000080
+
+// Timer Channel 1 Capture/Compare Register
+#define RFC_RAT_O_RATCH1VAL 0x00000084
+
+// Timer Channel 2 Capture/Compare Register
+#define RFC_RAT_O_RATCH2VAL 0x00000088
+
+// Timer Channel 3 Capture/Compare Register
+#define RFC_RAT_O_RATCH3VAL 0x0000008C
+
+// Timer Channel 4 Capture/Compare Register
+#define RFC_RAT_O_RATCH4VAL 0x00000090
+
+// Timer Channel 5 Capture/Compare Register
+#define RFC_RAT_O_RATCH5VAL 0x00000094
+
+// Timer Channel 6 Capture/Compare Register
+#define RFC_RAT_O_RATCH6VAL 0x00000098
+
+// Timer Channel 7 Capture/Compare Register
+#define RFC_RAT_O_RATCH7VAL 0x0000009C
+
+//*****************************************************************************
+//
+// Register: RFC_RAT_O_RATCNT
+//
+//*****************************************************************************
+// Field: [31:0] CNT
+//
+// Counter value. This is not writable while radio timer counter is enabled.
+#define RFC_RAT_RATCNT_CNT_W 32
+#define RFC_RAT_RATCNT_CNT_M 0xFFFFFFFF
+#define RFC_RAT_RATCNT_CNT_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_RAT_O_RATCH0VAL
+//
+//*****************************************************************************
+// Field: [31:0] VAL
+//
+// Capture/compare value. Only writable when the channel is configured for
+// compare mode. In compare mode, a write to this register will auto-arm the
+// channel.
+#define RFC_RAT_RATCH0VAL_VAL_W 32
+#define RFC_RAT_RATCH0VAL_VAL_M 0xFFFFFFFF
+#define RFC_RAT_RATCH0VAL_VAL_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_RAT_O_RATCH1VAL
+//
+//*****************************************************************************
+// Field: [31:0] VAL
+//
+// Capture/compare value. Only writable when the channel is configured for
+// compare mode. In compare mode, a write to this register will auto-arm the
+// channel.
+#define RFC_RAT_RATCH1VAL_VAL_W 32
+#define RFC_RAT_RATCH1VAL_VAL_M 0xFFFFFFFF
+#define RFC_RAT_RATCH1VAL_VAL_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_RAT_O_RATCH2VAL
+//
+//*****************************************************************************
+// Field: [31:0] VAL
+//
+// Capture/compare value. Only writable when the channel is configured for
+// compare mode. In compare mode, a write to this register will auto-arm the
+// channel.
+#define RFC_RAT_RATCH2VAL_VAL_W 32
+#define RFC_RAT_RATCH2VAL_VAL_M 0xFFFFFFFF
+#define RFC_RAT_RATCH2VAL_VAL_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_RAT_O_RATCH3VAL
+//
+//*****************************************************************************
+// Field: [31:0] VAL
+//
+// Capture/compare value. Only writable when the channel is configured for
+// compare mode. In compare mode, a write to this register will auto-arm the
+// channel.
+#define RFC_RAT_RATCH3VAL_VAL_W 32
+#define RFC_RAT_RATCH3VAL_VAL_M 0xFFFFFFFF
+#define RFC_RAT_RATCH3VAL_VAL_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_RAT_O_RATCH4VAL
+//
+//*****************************************************************************
+// Field: [31:0] VAL
+//
+// Capture/compare value. Only writable when the channel is configured for
+// compare mode. In compare mode, a write to this register will auto-arm the
+// channel.
+#define RFC_RAT_RATCH4VAL_VAL_W 32
+#define RFC_RAT_RATCH4VAL_VAL_M 0xFFFFFFFF
+#define RFC_RAT_RATCH4VAL_VAL_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_RAT_O_RATCH5VAL
+//
+//*****************************************************************************
+// Field: [31:0] VAL
+//
+// Capture/compare value. Only writable when the channel is configured for
+// compare mode. In compare mode, a write to this register will auto-arm the
+// channel.
+#define RFC_RAT_RATCH5VAL_VAL_W 32
+#define RFC_RAT_RATCH5VAL_VAL_M 0xFFFFFFFF
+#define RFC_RAT_RATCH5VAL_VAL_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_RAT_O_RATCH6VAL
+//
+//*****************************************************************************
+// Field: [31:0] VAL
+//
+// Capture/compare value. Only writable when the channel is configured for
+// compare mode. In compare mode, a write to this register will auto-arm the
+// channel.
+#define RFC_RAT_RATCH6VAL_VAL_W 32
+#define RFC_RAT_RATCH6VAL_VAL_M 0xFFFFFFFF
+#define RFC_RAT_RATCH6VAL_VAL_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_RAT_O_RATCH7VAL
+//
+//*****************************************************************************
+// Field: [31:0] VAL
+//
+// Capture/compare value. Only writable when the channel is configured for
+// compare mode. In compare mode, a write to this register will auto-arm the
+// channel.
+#define RFC_RAT_RATCH7VAL_VAL_W 32
+#define RFC_RAT_RATCH7VAL_VAL_M 0xFFFFFFFF
+#define RFC_RAT_RATCH7VAL_VAL_S 0
+
+
+#endif // __RFC_RAT__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_ullram.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_ullram.h
new file mode 100644
index 0000000..0159b94
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_ullram.h
@@ -0,0 +1,30767 @@
+/******************************************************************************
+* Filename: hw_rfc_ullram_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_RFC_ULLRAM_H__
+#define __HW_RFC_ULLRAM_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// RFC_ULLRAM component
+//
+//*****************************************************************************
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK10 0x00000000
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11 0x00000004
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12 0x00000008
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK13 0x0000000C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK14 0x00000010
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK15 0x00000014
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK16 0x00000018
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK17 0x0000001C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK18 0x00000020
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK19 0x00000024
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK110 0x00000028
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK111 0x0000002C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK112 0x00000030
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK113 0x00000034
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK114 0x00000038
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK115 0x0000003C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK116 0x00000040
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK117 0x00000044
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK118 0x00000048
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK119 0x0000004C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK120 0x00000050
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK121 0x00000054
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK122 0x00000058
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK123 0x0000005C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK124 0x00000060
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK125 0x00000064
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK126 0x00000068
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK127 0x0000006C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK128 0x00000070
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK129 0x00000074
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK130 0x00000078
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK131 0x0000007C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK132 0x00000080
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK133 0x00000084
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK134 0x00000088
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK135 0x0000008C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK136 0x00000090
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK137 0x00000094
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK138 0x00000098
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK139 0x0000009C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK140 0x000000A0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK141 0x000000A4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK142 0x000000A8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK143 0x000000AC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK144 0x000000B0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK145 0x000000B4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK146 0x000000B8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK147 0x000000BC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK148 0x000000C0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK149 0x000000C4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK150 0x000000C8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK151 0x000000CC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK152 0x000000D0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK153 0x000000D4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK154 0x000000D8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK155 0x000000DC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK156 0x000000E0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK157 0x000000E4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK158 0x000000E8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK159 0x000000EC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK160 0x000000F0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK161 0x000000F4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK162 0x000000F8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK163 0x000000FC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK164 0x00000100
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK165 0x00000104
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK166 0x00000108
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK167 0x0000010C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK168 0x00000110
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK169 0x00000114
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK170 0x00000118
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK171 0x0000011C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK172 0x00000120
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK173 0x00000124
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK174 0x00000128
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK175 0x0000012C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK176 0x00000130
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK177 0x00000134
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK178 0x00000138
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK179 0x0000013C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK180 0x00000140
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK181 0x00000144
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK182 0x00000148
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK183 0x0000014C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK184 0x00000150
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK185 0x00000154
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK186 0x00000158
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK187 0x0000015C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK188 0x00000160
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK189 0x00000164
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK190 0x00000168
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK191 0x0000016C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK192 0x00000170
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK193 0x00000174
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK194 0x00000178
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK195 0x0000017C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK196 0x00000180
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK197 0x00000184
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK198 0x00000188
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK199 0x0000018C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1100 0x00000190
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1101 0x00000194
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1102 0x00000198
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1103 0x0000019C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1104 0x000001A0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1105 0x000001A4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1106 0x000001A8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1107 0x000001AC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1108 0x000001B0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1109 0x000001B4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1110 0x000001B8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1111 0x000001BC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1112 0x000001C0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1113 0x000001C4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1114 0x000001C8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1115 0x000001CC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1116 0x000001D0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1117 0x000001D4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1118 0x000001D8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1119 0x000001DC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1120 0x000001E0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1121 0x000001E4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1122 0x000001E8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1123 0x000001EC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1124 0x000001F0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1125 0x000001F4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1126 0x000001F8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1127 0x000001FC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1128 0x00000200
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1129 0x00000204
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1130 0x00000208
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1131 0x0000020C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1132 0x00000210
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1133 0x00000214
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1134 0x00000218
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1135 0x0000021C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1136 0x00000220
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1137 0x00000224
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1138 0x00000228
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1139 0x0000022C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1140 0x00000230
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1141 0x00000234
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1142 0x00000238
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1143 0x0000023C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1144 0x00000240
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1145 0x00000244
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1146 0x00000248
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1147 0x0000024C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1148 0x00000250
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1149 0x00000254
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1150 0x00000258
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1151 0x0000025C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1152 0x00000260
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1153 0x00000264
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1154 0x00000268
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1155 0x0000026C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1156 0x00000270
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1157 0x00000274
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1158 0x00000278
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1159 0x0000027C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1160 0x00000280
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1161 0x00000284
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1162 0x00000288
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1163 0x0000028C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1164 0x00000290
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1165 0x00000294
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1166 0x00000298
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1167 0x0000029C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1168 0x000002A0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1169 0x000002A4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1170 0x000002A8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1171 0x000002AC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1172 0x000002B0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1173 0x000002B4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1174 0x000002B8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1175 0x000002BC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1176 0x000002C0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1177 0x000002C4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1178 0x000002C8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1179 0x000002CC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1180 0x000002D0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1181 0x000002D4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1182 0x000002D8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1183 0x000002DC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1184 0x000002E0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1185 0x000002E4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1186 0x000002E8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1187 0x000002EC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1188 0x000002F0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1189 0x000002F4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1190 0x000002F8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1191 0x000002FC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1192 0x00000300
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1193 0x00000304
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1194 0x00000308
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1195 0x0000030C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1196 0x00000310
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1197 0x00000314
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1198 0x00000318
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1199 0x0000031C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1200 0x00000320
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1201 0x00000324
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1202 0x00000328
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1203 0x0000032C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1204 0x00000330
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1205 0x00000334
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1206 0x00000338
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1207 0x0000033C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1208 0x00000340
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1209 0x00000344
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1210 0x00000348
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1211 0x0000034C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1212 0x00000350
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1213 0x00000354
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1214 0x00000358
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1215 0x0000035C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1216 0x00000360
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1217 0x00000364
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1218 0x00000368
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1219 0x0000036C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1220 0x00000370
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1221 0x00000374
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1222 0x00000378
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1223 0x0000037C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1224 0x00000380
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1225 0x00000384
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1226 0x00000388
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1227 0x0000038C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1228 0x00000390
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1229 0x00000394
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1230 0x00000398
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1231 0x0000039C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1232 0x000003A0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1233 0x000003A4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1234 0x000003A8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1235 0x000003AC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1236 0x000003B0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1237 0x000003B4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1238 0x000003B8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1239 0x000003BC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1240 0x000003C0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1241 0x000003C4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1242 0x000003C8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1243 0x000003CC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1244 0x000003D0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1245 0x000003D4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1246 0x000003D8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1247 0x000003DC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1248 0x000003E0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1249 0x000003E4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1250 0x000003E8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1251 0x000003EC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1252 0x000003F0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1253 0x000003F4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1254 0x000003F8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1255 0x000003FC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1256 0x00000400
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1257 0x00000404
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1258 0x00000408
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1259 0x0000040C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1260 0x00000410
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1261 0x00000414
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1262 0x00000418
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1263 0x0000041C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1264 0x00000420
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1265 0x00000424
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1266 0x00000428
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1267 0x0000042C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1268 0x00000430
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1269 0x00000434
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1270 0x00000438
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1271 0x0000043C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1272 0x00000440
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1273 0x00000444
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1274 0x00000448
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1275 0x0000044C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1276 0x00000450
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1277 0x00000454
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1278 0x00000458
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1279 0x0000045C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1280 0x00000460
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1281 0x00000464
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1282 0x00000468
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1283 0x0000046C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1284 0x00000470
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1285 0x00000474
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1286 0x00000478
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1287 0x0000047C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1288 0x00000480
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1289 0x00000484
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1290 0x00000488
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1291 0x0000048C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1292 0x00000490
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1293 0x00000494
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1294 0x00000498
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1295 0x0000049C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1296 0x000004A0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1297 0x000004A4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1298 0x000004A8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1299 0x000004AC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1300 0x000004B0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1301 0x000004B4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1302 0x000004B8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1303 0x000004BC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1304 0x000004C0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1305 0x000004C4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1306 0x000004C8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1307 0x000004CC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1308 0x000004D0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1309 0x000004D4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1310 0x000004D8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1311 0x000004DC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1312 0x000004E0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1313 0x000004E4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1314 0x000004E8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1315 0x000004EC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1316 0x000004F0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1317 0x000004F4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1318 0x000004F8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1319 0x000004FC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1320 0x00000500
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1321 0x00000504
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1322 0x00000508
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1323 0x0000050C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1324 0x00000510
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1325 0x00000514
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1326 0x00000518
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1327 0x0000051C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1328 0x00000520
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1329 0x00000524
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1330 0x00000528
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1331 0x0000052C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1332 0x00000530
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1333 0x00000534
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1334 0x00000538
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1335 0x0000053C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1336 0x00000540
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1337 0x00000544
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1338 0x00000548
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1339 0x0000054C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1340 0x00000550
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1341 0x00000554
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1342 0x00000558
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1343 0x0000055C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1344 0x00000560
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1345 0x00000564
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1346 0x00000568
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1347 0x0000056C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1348 0x00000570
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1349 0x00000574
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1350 0x00000578
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1351 0x0000057C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1352 0x00000580
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1353 0x00000584
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1354 0x00000588
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1355 0x0000058C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1356 0x00000590
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1357 0x00000594
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1358 0x00000598
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1359 0x0000059C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1360 0x000005A0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1361 0x000005A4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1362 0x000005A8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1363 0x000005AC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1364 0x000005B0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1365 0x000005B4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1366 0x000005B8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1367 0x000005BC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1368 0x000005C0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1369 0x000005C4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1370 0x000005C8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1371 0x000005CC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1372 0x000005D0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1373 0x000005D4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1374 0x000005D8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1375 0x000005DC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1376 0x000005E0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1377 0x000005E4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1378 0x000005E8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1379 0x000005EC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1380 0x000005F0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1381 0x000005F4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1382 0x000005F8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1383 0x000005FC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1384 0x00000600
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1385 0x00000604
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1386 0x00000608
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1387 0x0000060C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1388 0x00000610
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1389 0x00000614
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1390 0x00000618
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1391 0x0000061C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1392 0x00000620
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1393 0x00000624
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1394 0x00000628
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1395 0x0000062C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1396 0x00000630
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1397 0x00000634
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1398 0x00000638
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1399 0x0000063C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1400 0x00000640
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1401 0x00000644
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1402 0x00000648
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1403 0x0000064C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1404 0x00000650
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1405 0x00000654
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1406 0x00000658
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1407 0x0000065C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1408 0x00000660
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1409 0x00000664
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1410 0x00000668
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1411 0x0000066C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1412 0x00000670
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1413 0x00000674
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1414 0x00000678
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1415 0x0000067C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1416 0x00000680
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1417 0x00000684
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1418 0x00000688
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1419 0x0000068C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1420 0x00000690
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1421 0x00000694
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1422 0x00000698
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1423 0x0000069C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1424 0x000006A0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1425 0x000006A4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1426 0x000006A8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1427 0x000006AC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1428 0x000006B0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1429 0x000006B4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1430 0x000006B8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1431 0x000006BC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1432 0x000006C0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1433 0x000006C4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1434 0x000006C8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1435 0x000006CC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1436 0x000006D0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1437 0x000006D4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1438 0x000006D8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1439 0x000006DC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1440 0x000006E0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1441 0x000006E4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1442 0x000006E8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1443 0x000006EC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1444 0x000006F0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1445 0x000006F4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1446 0x000006F8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1447 0x000006FC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1448 0x00000700
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1449 0x00000704
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1450 0x00000708
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1451 0x0000070C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1452 0x00000710
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1453 0x00000714
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1454 0x00000718
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1455 0x0000071C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1456 0x00000720
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1457 0x00000724
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1458 0x00000728
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1459 0x0000072C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1460 0x00000730
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1461 0x00000734
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1462 0x00000738
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1463 0x0000073C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1464 0x00000740
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1465 0x00000744
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1466 0x00000748
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1467 0x0000074C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1468 0x00000750
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1469 0x00000754
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1470 0x00000758
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1471 0x0000075C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1472 0x00000760
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1473 0x00000764
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1474 0x00000768
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1475 0x0000076C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1476 0x00000770
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1477 0x00000774
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1478 0x00000778
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1479 0x0000077C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1480 0x00000780
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1481 0x00000784
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1482 0x00000788
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1483 0x0000078C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1484 0x00000790
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1485 0x00000794
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1486 0x00000798
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1487 0x0000079C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1488 0x000007A0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1489 0x000007A4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1490 0x000007A8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1491 0x000007AC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1492 0x000007B0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1493 0x000007B4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1494 0x000007B8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1495 0x000007BC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1496 0x000007C0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1497 0x000007C4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1498 0x000007C8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1499 0x000007CC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1500 0x000007D0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1501 0x000007D4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1502 0x000007D8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1503 0x000007DC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1504 0x000007E0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1505 0x000007E4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1506 0x000007E8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1507 0x000007EC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1508 0x000007F0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1509 0x000007F4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1510 0x000007F8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1511 0x000007FC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1512 0x00000800
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1513 0x00000804
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1514 0x00000808
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1515 0x0000080C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1516 0x00000810
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1517 0x00000814
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1518 0x00000818
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1519 0x0000081C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1520 0x00000820
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1521 0x00000824
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1522 0x00000828
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1523 0x0000082C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1524 0x00000830
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1525 0x00000834
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1526 0x00000838
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1527 0x0000083C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1528 0x00000840
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1529 0x00000844
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1530 0x00000848
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1531 0x0000084C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1532 0x00000850
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1533 0x00000854
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1534 0x00000858
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1535 0x0000085C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1536 0x00000860
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1537 0x00000864
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1538 0x00000868
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1539 0x0000086C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1540 0x00000870
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1541 0x00000874
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1542 0x00000878
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1543 0x0000087C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1544 0x00000880
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1545 0x00000884
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1546 0x00000888
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1547 0x0000088C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1548 0x00000890
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1549 0x00000894
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1550 0x00000898
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1551 0x0000089C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1552 0x000008A0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1553 0x000008A4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1554 0x000008A8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1555 0x000008AC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1556 0x000008B0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1557 0x000008B4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1558 0x000008B8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1559 0x000008BC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1560 0x000008C0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1561 0x000008C4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1562 0x000008C8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1563 0x000008CC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1564 0x000008D0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1565 0x000008D4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1566 0x000008D8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1567 0x000008DC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1568 0x000008E0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1569 0x000008E4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1570 0x000008E8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1571 0x000008EC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1572 0x000008F0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1573 0x000008F4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1574 0x000008F8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1575 0x000008FC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1576 0x00000900
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1577 0x00000904
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1578 0x00000908
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1579 0x0000090C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1580 0x00000910
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1581 0x00000914
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1582 0x00000918
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1583 0x0000091C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1584 0x00000920
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1585 0x00000924
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1586 0x00000928
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1587 0x0000092C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1588 0x00000930
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1589 0x00000934
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1590 0x00000938
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1591 0x0000093C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1592 0x00000940
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1593 0x00000944
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1594 0x00000948
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1595 0x0000094C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1596 0x00000950
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1597 0x00000954
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1598 0x00000958
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1599 0x0000095C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1600 0x00000960
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1601 0x00000964
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1602 0x00000968
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1603 0x0000096C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1604 0x00000970
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1605 0x00000974
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1606 0x00000978
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1607 0x0000097C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1608 0x00000980
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1609 0x00000984
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1610 0x00000988
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1611 0x0000098C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1612 0x00000990
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1613 0x00000994
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1614 0x00000998
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1615 0x0000099C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1616 0x000009A0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1617 0x000009A4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1618 0x000009A8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1619 0x000009AC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1620 0x000009B0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1621 0x000009B4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1622 0x000009B8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1623 0x000009BC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1624 0x000009C0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1625 0x000009C4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1626 0x000009C8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1627 0x000009CC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1628 0x000009D0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1629 0x000009D4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1630 0x000009D8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1631 0x000009DC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1632 0x000009E0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1633 0x000009E4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1634 0x000009E8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1635 0x000009EC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1636 0x000009F0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1637 0x000009F4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1638 0x000009F8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1639 0x000009FC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1640 0x00000A00
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1641 0x00000A04
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1642 0x00000A08
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1643 0x00000A0C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1644 0x00000A10
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1645 0x00000A14
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1646 0x00000A18
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1647 0x00000A1C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1648 0x00000A20
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1649 0x00000A24
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1650 0x00000A28
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1651 0x00000A2C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1652 0x00000A30
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1653 0x00000A34
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1654 0x00000A38
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1655 0x00000A3C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1656 0x00000A40
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1657 0x00000A44
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1658 0x00000A48
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1659 0x00000A4C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1660 0x00000A50
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1661 0x00000A54
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1662 0x00000A58
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1663 0x00000A5C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1664 0x00000A60
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1665 0x00000A64
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1666 0x00000A68
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1667 0x00000A6C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1668 0x00000A70
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1669 0x00000A74
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1670 0x00000A78
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1671 0x00000A7C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1672 0x00000A80
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1673 0x00000A84
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1674 0x00000A88
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1675 0x00000A8C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1676 0x00000A90
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1677 0x00000A94
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1678 0x00000A98
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1679 0x00000A9C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1680 0x00000AA0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1681 0x00000AA4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1682 0x00000AA8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1683 0x00000AAC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1684 0x00000AB0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1685 0x00000AB4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1686 0x00000AB8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1687 0x00000ABC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1688 0x00000AC0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1689 0x00000AC4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1690 0x00000AC8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1691 0x00000ACC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1692 0x00000AD0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1693 0x00000AD4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1694 0x00000AD8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1695 0x00000ADC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1696 0x00000AE0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1697 0x00000AE4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1698 0x00000AE8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1699 0x00000AEC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1700 0x00000AF0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1701 0x00000AF4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1702 0x00000AF8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1703 0x00000AFC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1704 0x00000B00
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1705 0x00000B04
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1706 0x00000B08
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1707 0x00000B0C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1708 0x00000B10
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1709 0x00000B14
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1710 0x00000B18
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1711 0x00000B1C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1712 0x00000B20
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1713 0x00000B24
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1714 0x00000B28
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1715 0x00000B2C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1716 0x00000B30
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1717 0x00000B34
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1718 0x00000B38
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1719 0x00000B3C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1720 0x00000B40
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1721 0x00000B44
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1722 0x00000B48
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1723 0x00000B4C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1724 0x00000B50
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1725 0x00000B54
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1726 0x00000B58
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1727 0x00000B5C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1728 0x00000B60
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1729 0x00000B64
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1730 0x00000B68
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1731 0x00000B6C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1732 0x00000B70
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1733 0x00000B74
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1734 0x00000B78
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1735 0x00000B7C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1736 0x00000B80
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1737 0x00000B84
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1738 0x00000B88
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1739 0x00000B8C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1740 0x00000B90
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1741 0x00000B94
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1742 0x00000B98
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1743 0x00000B9C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1744 0x00000BA0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1745 0x00000BA4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1746 0x00000BA8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1747 0x00000BAC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1748 0x00000BB0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1749 0x00000BB4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1750 0x00000BB8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1751 0x00000BBC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1752 0x00000BC0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1753 0x00000BC4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1754 0x00000BC8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1755 0x00000BCC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1756 0x00000BD0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1757 0x00000BD4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1758 0x00000BD8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1759 0x00000BDC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1760 0x00000BE0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1761 0x00000BE4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1762 0x00000BE8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1763 0x00000BEC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1764 0x00000BF0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1765 0x00000BF4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1766 0x00000BF8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1767 0x00000BFC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1768 0x00000C00
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1769 0x00000C04
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1770 0x00000C08
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1771 0x00000C0C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1772 0x00000C10
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1773 0x00000C14
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1774 0x00000C18
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1775 0x00000C1C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1776 0x00000C20
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1777 0x00000C24
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1778 0x00000C28
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1779 0x00000C2C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1780 0x00000C30
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1781 0x00000C34
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1782 0x00000C38
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1783 0x00000C3C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1784 0x00000C40
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1785 0x00000C44
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1786 0x00000C48
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1787 0x00000C4C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1788 0x00000C50
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1789 0x00000C54
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1790 0x00000C58
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1791 0x00000C5C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1792 0x00000C60
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1793 0x00000C64
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1794 0x00000C68
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1795 0x00000C6C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1796 0x00000C70
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1797 0x00000C74
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1798 0x00000C78
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1799 0x00000C7C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1800 0x00000C80
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1801 0x00000C84
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1802 0x00000C88
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1803 0x00000C8C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1804 0x00000C90
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1805 0x00000C94
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1806 0x00000C98
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1807 0x00000C9C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1808 0x00000CA0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1809 0x00000CA4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1810 0x00000CA8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1811 0x00000CAC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1812 0x00000CB0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1813 0x00000CB4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1814 0x00000CB8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1815 0x00000CBC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1816 0x00000CC0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1817 0x00000CC4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1818 0x00000CC8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1819 0x00000CCC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1820 0x00000CD0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1821 0x00000CD4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1822 0x00000CD8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1823 0x00000CDC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1824 0x00000CE0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1825 0x00000CE4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1826 0x00000CE8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1827 0x00000CEC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1828 0x00000CF0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1829 0x00000CF4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1830 0x00000CF8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1831 0x00000CFC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1832 0x00000D00
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1833 0x00000D04
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1834 0x00000D08
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1835 0x00000D0C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1836 0x00000D10
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1837 0x00000D14
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1838 0x00000D18
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1839 0x00000D1C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1840 0x00000D20
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1841 0x00000D24
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1842 0x00000D28
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1843 0x00000D2C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1844 0x00000D30
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1845 0x00000D34
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1846 0x00000D38
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1847 0x00000D3C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1848 0x00000D40
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1849 0x00000D44
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1850 0x00000D48
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1851 0x00000D4C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1852 0x00000D50
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1853 0x00000D54
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1854 0x00000D58
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1855 0x00000D5C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1856 0x00000D60
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1857 0x00000D64
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1858 0x00000D68
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1859 0x00000D6C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1860 0x00000D70
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1861 0x00000D74
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1862 0x00000D78
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1863 0x00000D7C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1864 0x00000D80
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1865 0x00000D84
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1866 0x00000D88
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1867 0x00000D8C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1868 0x00000D90
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1869 0x00000D94
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1870 0x00000D98
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1871 0x00000D9C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1872 0x00000DA0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1873 0x00000DA4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1874 0x00000DA8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1875 0x00000DAC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1876 0x00000DB0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1877 0x00000DB4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1878 0x00000DB8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1879 0x00000DBC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1880 0x00000DC0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1881 0x00000DC4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1882 0x00000DC8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1883 0x00000DCC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1884 0x00000DD0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1885 0x00000DD4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1886 0x00000DD8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1887 0x00000DDC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1888 0x00000DE0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1889 0x00000DE4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1890 0x00000DE8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1891 0x00000DEC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1892 0x00000DF0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1893 0x00000DF4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1894 0x00000DF8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1895 0x00000DFC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1896 0x00000E00
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1897 0x00000E04
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1898 0x00000E08
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1899 0x00000E0C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1900 0x00000E10
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1901 0x00000E14
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1902 0x00000E18
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1903 0x00000E1C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1904 0x00000E20
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1905 0x00000E24
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1906 0x00000E28
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1907 0x00000E2C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1908 0x00000E30
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1909 0x00000E34
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1910 0x00000E38
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1911 0x00000E3C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1912 0x00000E40
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1913 0x00000E44
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1914 0x00000E48
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1915 0x00000E4C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1916 0x00000E50
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1917 0x00000E54
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1918 0x00000E58
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1919 0x00000E5C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1920 0x00000E60
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1921 0x00000E64
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1922 0x00000E68
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1923 0x00000E6C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1924 0x00000E70
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1925 0x00000E74
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1926 0x00000E78
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1927 0x00000E7C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1928 0x00000E80
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1929 0x00000E84
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1930 0x00000E88
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1931 0x00000E8C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1932 0x00000E90
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1933 0x00000E94
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1934 0x00000E98
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1935 0x00000E9C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1936 0x00000EA0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1937 0x00000EA4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1938 0x00000EA8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1939 0x00000EAC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1940 0x00000EB0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1941 0x00000EB4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1942 0x00000EB8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1943 0x00000EBC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1944 0x00000EC0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1945 0x00000EC4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1946 0x00000EC8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1947 0x00000ECC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1948 0x00000ED0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1949 0x00000ED4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1950 0x00000ED8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1951 0x00000EDC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1952 0x00000EE0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1953 0x00000EE4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1954 0x00000EE8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1955 0x00000EEC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1956 0x00000EF0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1957 0x00000EF4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1958 0x00000EF8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1959 0x00000EFC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1960 0x00000F00
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1961 0x00000F04
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1962 0x00000F08
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1963 0x00000F0C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1964 0x00000F10
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1965 0x00000F14
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1966 0x00000F18
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1967 0x00000F1C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1968 0x00000F20
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1969 0x00000F24
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1970 0x00000F28
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1971 0x00000F2C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1972 0x00000F30
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1973 0x00000F34
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1974 0x00000F38
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1975 0x00000F3C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1976 0x00000F40
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1977 0x00000F44
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1978 0x00000F48
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1979 0x00000F4C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1980 0x00000F50
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1981 0x00000F54
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1982 0x00000F58
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1983 0x00000F5C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1984 0x00000F60
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1985 0x00000F64
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1986 0x00000F68
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1987 0x00000F6C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1988 0x00000F70
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1989 0x00000F74
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1990 0x00000F78
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1991 0x00000F7C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1992 0x00000F80
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1993 0x00000F84
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1994 0x00000F88
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1995 0x00000F8C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1996 0x00000F90
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1997 0x00000F94
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1998 0x00000F98
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK1999 0x00000F9C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11000 0x00000FA0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11001 0x00000FA4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11002 0x00000FA8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11003 0x00000FAC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11004 0x00000FB0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11005 0x00000FB4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11006 0x00000FB8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11007 0x00000FBC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11008 0x00000FC0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11009 0x00000FC4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11010 0x00000FC8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11011 0x00000FCC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11012 0x00000FD0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11013 0x00000FD4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11014 0x00000FD8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11015 0x00000FDC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11016 0x00000FE0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11017 0x00000FE4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11018 0x00000FE8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11019 0x00000FEC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11020 0x00000FF0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11021 0x00000FF4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11022 0x00000FF8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11023 0x00000FFC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11024 0x00001000
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11025 0x00001004
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11026 0x00001008
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11027 0x0000100C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11028 0x00001010
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11029 0x00001014
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11030 0x00001018
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11031 0x0000101C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11032 0x00001020
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11033 0x00001024
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11034 0x00001028
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11035 0x0000102C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11036 0x00001030
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11037 0x00001034
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11038 0x00001038
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11039 0x0000103C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11040 0x00001040
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11041 0x00001044
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11042 0x00001048
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11043 0x0000104C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11044 0x00001050
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11045 0x00001054
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11046 0x00001058
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11047 0x0000105C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11048 0x00001060
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11049 0x00001064
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11050 0x00001068
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11051 0x0000106C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11052 0x00001070
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11053 0x00001074
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11054 0x00001078
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11055 0x0000107C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11056 0x00001080
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11057 0x00001084
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11058 0x00001088
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11059 0x0000108C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11060 0x00001090
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11061 0x00001094
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11062 0x00001098
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11063 0x0000109C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11064 0x000010A0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11065 0x000010A4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11066 0x000010A8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11067 0x000010AC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11068 0x000010B0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11069 0x000010B4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11070 0x000010B8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11071 0x000010BC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11072 0x000010C0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11073 0x000010C4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11074 0x000010C8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11075 0x000010CC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11076 0x000010D0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11077 0x000010D4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11078 0x000010D8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11079 0x000010DC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11080 0x000010E0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11081 0x000010E4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11082 0x000010E8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11083 0x000010EC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11084 0x000010F0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11085 0x000010F4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11086 0x000010F8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11087 0x000010FC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11088 0x00001100
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11089 0x00001104
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11090 0x00001108
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11091 0x0000110C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11092 0x00001110
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11093 0x00001114
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11094 0x00001118
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11095 0x0000111C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11096 0x00001120
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11097 0x00001124
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11098 0x00001128
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11099 0x0000112C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11100 0x00001130
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11101 0x00001134
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11102 0x00001138
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11103 0x0000113C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11104 0x00001140
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11105 0x00001144
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11106 0x00001148
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11107 0x0000114C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11108 0x00001150
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11109 0x00001154
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11110 0x00001158
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11111 0x0000115C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11112 0x00001160
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11113 0x00001164
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11114 0x00001168
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11115 0x0000116C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11116 0x00001170
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11117 0x00001174
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11118 0x00001178
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11119 0x0000117C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11120 0x00001180
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11121 0x00001184
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11122 0x00001188
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11123 0x0000118C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11124 0x00001190
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11125 0x00001194
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11126 0x00001198
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11127 0x0000119C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11128 0x000011A0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11129 0x000011A4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11130 0x000011A8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11131 0x000011AC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11132 0x000011B0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11133 0x000011B4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11134 0x000011B8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11135 0x000011BC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11136 0x000011C0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11137 0x000011C4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11138 0x000011C8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11139 0x000011CC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11140 0x000011D0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11141 0x000011D4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11142 0x000011D8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11143 0x000011DC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11144 0x000011E0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11145 0x000011E4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11146 0x000011E8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11147 0x000011EC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11148 0x000011F0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11149 0x000011F4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11150 0x000011F8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11151 0x000011FC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11152 0x00001200
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11153 0x00001204
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11154 0x00001208
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11155 0x0000120C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11156 0x00001210
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11157 0x00001214
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11158 0x00001218
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11159 0x0000121C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11160 0x00001220
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11161 0x00001224
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11162 0x00001228
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11163 0x0000122C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11164 0x00001230
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11165 0x00001234
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11166 0x00001238
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11167 0x0000123C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11168 0x00001240
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11169 0x00001244
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11170 0x00001248
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11171 0x0000124C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11172 0x00001250
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11173 0x00001254
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11174 0x00001258
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11175 0x0000125C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11176 0x00001260
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11177 0x00001264
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11178 0x00001268
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11179 0x0000126C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11180 0x00001270
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11181 0x00001274
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11182 0x00001278
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11183 0x0000127C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11184 0x00001280
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11185 0x00001284
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11186 0x00001288
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11187 0x0000128C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11188 0x00001290
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11189 0x00001294
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11190 0x00001298
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11191 0x0000129C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11192 0x000012A0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11193 0x000012A4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11194 0x000012A8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11195 0x000012AC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11196 0x000012B0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11197 0x000012B4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11198 0x000012B8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11199 0x000012BC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11200 0x000012C0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11201 0x000012C4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11202 0x000012C8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11203 0x000012CC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11204 0x000012D0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11205 0x000012D4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11206 0x000012D8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11207 0x000012DC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11208 0x000012E0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11209 0x000012E4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11210 0x000012E8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11211 0x000012EC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11212 0x000012F0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11213 0x000012F4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11214 0x000012F8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11215 0x000012FC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11216 0x00001300
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11217 0x00001304
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11218 0x00001308
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11219 0x0000130C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11220 0x00001310
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11221 0x00001314
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11222 0x00001318
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11223 0x0000131C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11224 0x00001320
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11225 0x00001324
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11226 0x00001328
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11227 0x0000132C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11228 0x00001330
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11229 0x00001334
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11230 0x00001338
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11231 0x0000133C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11232 0x00001340
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11233 0x00001344
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11234 0x00001348
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11235 0x0000134C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11236 0x00001350
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11237 0x00001354
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11238 0x00001358
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11239 0x0000135C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11240 0x00001360
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11241 0x00001364
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11242 0x00001368
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11243 0x0000136C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11244 0x00001370
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11245 0x00001374
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11246 0x00001378
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11247 0x0000137C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11248 0x00001380
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11249 0x00001384
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11250 0x00001388
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11251 0x0000138C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11252 0x00001390
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11253 0x00001394
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11254 0x00001398
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11255 0x0000139C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11256 0x000013A0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11257 0x000013A4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11258 0x000013A8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11259 0x000013AC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11260 0x000013B0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11261 0x000013B4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11262 0x000013B8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11263 0x000013BC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11264 0x000013C0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11265 0x000013C4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11266 0x000013C8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11267 0x000013CC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11268 0x000013D0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11269 0x000013D4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11270 0x000013D8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11271 0x000013DC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11272 0x000013E0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11273 0x000013E4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11274 0x000013E8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11275 0x000013EC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11276 0x000013F0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11277 0x000013F4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11278 0x000013F8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11279 0x000013FC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11280 0x00001400
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11281 0x00001404
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11282 0x00001408
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11283 0x0000140C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11284 0x00001410
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11285 0x00001414
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11286 0x00001418
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11287 0x0000141C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11288 0x00001420
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11289 0x00001424
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11290 0x00001428
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11291 0x0000142C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11292 0x00001430
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11293 0x00001434
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11294 0x00001438
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11295 0x0000143C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11296 0x00001440
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11297 0x00001444
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11298 0x00001448
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11299 0x0000144C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11300 0x00001450
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11301 0x00001454
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11302 0x00001458
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11303 0x0000145C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11304 0x00001460
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11305 0x00001464
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11306 0x00001468
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11307 0x0000146C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11308 0x00001470
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11309 0x00001474
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11310 0x00001478
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11311 0x0000147C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11312 0x00001480
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11313 0x00001484
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11314 0x00001488
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11315 0x0000148C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11316 0x00001490
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11317 0x00001494
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11318 0x00001498
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11319 0x0000149C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11320 0x000014A0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11321 0x000014A4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11322 0x000014A8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11323 0x000014AC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11324 0x000014B0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11325 0x000014B4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11326 0x000014B8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11327 0x000014BC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11328 0x000014C0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11329 0x000014C4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11330 0x000014C8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11331 0x000014CC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11332 0x000014D0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11333 0x000014D4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11334 0x000014D8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11335 0x000014DC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11336 0x000014E0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11337 0x000014E4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11338 0x000014E8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11339 0x000014EC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11340 0x000014F0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11341 0x000014F4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11342 0x000014F8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11343 0x000014FC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11344 0x00001500
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11345 0x00001504
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11346 0x00001508
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11347 0x0000150C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11348 0x00001510
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11349 0x00001514
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11350 0x00001518
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11351 0x0000151C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11352 0x00001520
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11353 0x00001524
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11354 0x00001528
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11355 0x0000152C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11356 0x00001530
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11357 0x00001534
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11358 0x00001538
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11359 0x0000153C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11360 0x00001540
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11361 0x00001544
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11362 0x00001548
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11363 0x0000154C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11364 0x00001550
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11365 0x00001554
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11366 0x00001558
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11367 0x0000155C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11368 0x00001560
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11369 0x00001564
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11370 0x00001568
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11371 0x0000156C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11372 0x00001570
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11373 0x00001574
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11374 0x00001578
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11375 0x0000157C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11376 0x00001580
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11377 0x00001584
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11378 0x00001588
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11379 0x0000158C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11380 0x00001590
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11381 0x00001594
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11382 0x00001598
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11383 0x0000159C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11384 0x000015A0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11385 0x000015A4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11386 0x000015A8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11387 0x000015AC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11388 0x000015B0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11389 0x000015B4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11390 0x000015B8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11391 0x000015BC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11392 0x000015C0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11393 0x000015C4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11394 0x000015C8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11395 0x000015CC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11396 0x000015D0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11397 0x000015D4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11398 0x000015D8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11399 0x000015DC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11400 0x000015E0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11401 0x000015E4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11402 0x000015E8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11403 0x000015EC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11404 0x000015F0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11405 0x000015F4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11406 0x000015F8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11407 0x000015FC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11408 0x00001600
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11409 0x00001604
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11410 0x00001608
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11411 0x0000160C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11412 0x00001610
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11413 0x00001614
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11414 0x00001618
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11415 0x0000161C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11416 0x00001620
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11417 0x00001624
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11418 0x00001628
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11419 0x0000162C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11420 0x00001630
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11421 0x00001634
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11422 0x00001638
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11423 0x0000163C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11424 0x00001640
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11425 0x00001644
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11426 0x00001648
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11427 0x0000164C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11428 0x00001650
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11429 0x00001654
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11430 0x00001658
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11431 0x0000165C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11432 0x00001660
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11433 0x00001664
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11434 0x00001668
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11435 0x0000166C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11436 0x00001670
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11437 0x00001674
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11438 0x00001678
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11439 0x0000167C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11440 0x00001680
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11441 0x00001684
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11442 0x00001688
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11443 0x0000168C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11444 0x00001690
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11445 0x00001694
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11446 0x00001698
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11447 0x0000169C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11448 0x000016A0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11449 0x000016A4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11450 0x000016A8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11451 0x000016AC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11452 0x000016B0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11453 0x000016B4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11454 0x000016B8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11455 0x000016BC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11456 0x000016C0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11457 0x000016C4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11458 0x000016C8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11459 0x000016CC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11460 0x000016D0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11461 0x000016D4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11462 0x000016D8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11463 0x000016DC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11464 0x000016E0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11465 0x000016E4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11466 0x000016E8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11467 0x000016EC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11468 0x000016F0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11469 0x000016F4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11470 0x000016F8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11471 0x000016FC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11472 0x00001700
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11473 0x00001704
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11474 0x00001708
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11475 0x0000170C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11476 0x00001710
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11477 0x00001714
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11478 0x00001718
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11479 0x0000171C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11480 0x00001720
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11481 0x00001724
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11482 0x00001728
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11483 0x0000172C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11484 0x00001730
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11485 0x00001734
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11486 0x00001738
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11487 0x0000173C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11488 0x00001740
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11489 0x00001744
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11490 0x00001748
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11491 0x0000174C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11492 0x00001750
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11493 0x00001754
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11494 0x00001758
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11495 0x0000175C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11496 0x00001760
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11497 0x00001764
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11498 0x00001768
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11499 0x0000176C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11500 0x00001770
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11501 0x00001774
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11502 0x00001778
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11503 0x0000177C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11504 0x00001780
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11505 0x00001784
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11506 0x00001788
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11507 0x0000178C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11508 0x00001790
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11509 0x00001794
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11510 0x00001798
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11511 0x0000179C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11512 0x000017A0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11513 0x000017A4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11514 0x000017A8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11515 0x000017AC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11516 0x000017B0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11517 0x000017B4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11518 0x000017B8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11519 0x000017BC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11520 0x000017C0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11521 0x000017C4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11522 0x000017C8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11523 0x000017CC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11524 0x000017D0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11525 0x000017D4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11526 0x000017D8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11527 0x000017DC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11528 0x000017E0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11529 0x000017E4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11530 0x000017E8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11531 0x000017EC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11532 0x000017F0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11533 0x000017F4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11534 0x000017F8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11535 0x000017FC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11536 0x00001800
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11537 0x00001804
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11538 0x00001808
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11539 0x0000180C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11540 0x00001810
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11541 0x00001814
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11542 0x00001818
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11543 0x0000181C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11544 0x00001820
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11545 0x00001824
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11546 0x00001828
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11547 0x0000182C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11548 0x00001830
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11549 0x00001834
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11550 0x00001838
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11551 0x0000183C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11552 0x00001840
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11553 0x00001844
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11554 0x00001848
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11555 0x0000184C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11556 0x00001850
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11557 0x00001854
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11558 0x00001858
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11559 0x0000185C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11560 0x00001860
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11561 0x00001864
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11562 0x00001868
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11563 0x0000186C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11564 0x00001870
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11565 0x00001874
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11566 0x00001878
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11567 0x0000187C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11568 0x00001880
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11569 0x00001884
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11570 0x00001888
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11571 0x0000188C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11572 0x00001890
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11573 0x00001894
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11574 0x00001898
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11575 0x0000189C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11576 0x000018A0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11577 0x000018A4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11578 0x000018A8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11579 0x000018AC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11580 0x000018B0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11581 0x000018B4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11582 0x000018B8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11583 0x000018BC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11584 0x000018C0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11585 0x000018C4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11586 0x000018C8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11587 0x000018CC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11588 0x000018D0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11589 0x000018D4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11590 0x000018D8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11591 0x000018DC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11592 0x000018E0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11593 0x000018E4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11594 0x000018E8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11595 0x000018EC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11596 0x000018F0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11597 0x000018F4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11598 0x000018F8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11599 0x000018FC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11600 0x00001900
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11601 0x00001904
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11602 0x00001908
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11603 0x0000190C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11604 0x00001910
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11605 0x00001914
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11606 0x00001918
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11607 0x0000191C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11608 0x00001920
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11609 0x00001924
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11610 0x00001928
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11611 0x0000192C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11612 0x00001930
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11613 0x00001934
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11614 0x00001938
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11615 0x0000193C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11616 0x00001940
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11617 0x00001944
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11618 0x00001948
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11619 0x0000194C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11620 0x00001950
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11621 0x00001954
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11622 0x00001958
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11623 0x0000195C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11624 0x00001960
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11625 0x00001964
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11626 0x00001968
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11627 0x0000196C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11628 0x00001970
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11629 0x00001974
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11630 0x00001978
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11631 0x0000197C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11632 0x00001980
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11633 0x00001984
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11634 0x00001988
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11635 0x0000198C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11636 0x00001990
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11637 0x00001994
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11638 0x00001998
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11639 0x0000199C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11640 0x000019A0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11641 0x000019A4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11642 0x000019A8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11643 0x000019AC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11644 0x000019B0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11645 0x000019B4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11646 0x000019B8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11647 0x000019BC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11648 0x000019C0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11649 0x000019C4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11650 0x000019C8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11651 0x000019CC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11652 0x000019D0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11653 0x000019D4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11654 0x000019D8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11655 0x000019DC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11656 0x000019E0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11657 0x000019E4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11658 0x000019E8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11659 0x000019EC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11660 0x000019F0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11661 0x000019F4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11662 0x000019F8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11663 0x000019FC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11664 0x00001A00
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11665 0x00001A04
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11666 0x00001A08
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11667 0x00001A0C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11668 0x00001A10
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11669 0x00001A14
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11670 0x00001A18
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11671 0x00001A1C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11672 0x00001A20
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11673 0x00001A24
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11674 0x00001A28
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11675 0x00001A2C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11676 0x00001A30
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11677 0x00001A34
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11678 0x00001A38
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11679 0x00001A3C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11680 0x00001A40
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11681 0x00001A44
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11682 0x00001A48
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11683 0x00001A4C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11684 0x00001A50
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11685 0x00001A54
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11686 0x00001A58
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11687 0x00001A5C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11688 0x00001A60
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11689 0x00001A64
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11690 0x00001A68
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11691 0x00001A6C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11692 0x00001A70
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11693 0x00001A74
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11694 0x00001A78
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11695 0x00001A7C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11696 0x00001A80
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11697 0x00001A84
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11698 0x00001A88
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11699 0x00001A8C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11700 0x00001A90
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11701 0x00001A94
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11702 0x00001A98
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11703 0x00001A9C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11704 0x00001AA0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11705 0x00001AA4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11706 0x00001AA8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11707 0x00001AAC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11708 0x00001AB0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11709 0x00001AB4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11710 0x00001AB8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11711 0x00001ABC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11712 0x00001AC0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11713 0x00001AC4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11714 0x00001AC8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11715 0x00001ACC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11716 0x00001AD0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11717 0x00001AD4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11718 0x00001AD8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11719 0x00001ADC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11720 0x00001AE0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11721 0x00001AE4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11722 0x00001AE8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11723 0x00001AEC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11724 0x00001AF0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11725 0x00001AF4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11726 0x00001AF8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11727 0x00001AFC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11728 0x00001B00
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11729 0x00001B04
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11730 0x00001B08
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11731 0x00001B0C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11732 0x00001B10
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11733 0x00001B14
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11734 0x00001B18
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11735 0x00001B1C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11736 0x00001B20
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11737 0x00001B24
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11738 0x00001B28
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11739 0x00001B2C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11740 0x00001B30
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11741 0x00001B34
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11742 0x00001B38
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11743 0x00001B3C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11744 0x00001B40
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11745 0x00001B44
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11746 0x00001B48
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11747 0x00001B4C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11748 0x00001B50
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11749 0x00001B54
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11750 0x00001B58
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11751 0x00001B5C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11752 0x00001B60
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11753 0x00001B64
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11754 0x00001B68
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11755 0x00001B6C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11756 0x00001B70
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11757 0x00001B74
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11758 0x00001B78
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11759 0x00001B7C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11760 0x00001B80
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11761 0x00001B84
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11762 0x00001B88
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11763 0x00001B8C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11764 0x00001B90
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11765 0x00001B94
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11766 0x00001B98
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11767 0x00001B9C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11768 0x00001BA0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11769 0x00001BA4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11770 0x00001BA8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11771 0x00001BAC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11772 0x00001BB0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11773 0x00001BB4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11774 0x00001BB8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11775 0x00001BBC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11776 0x00001BC0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11777 0x00001BC4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11778 0x00001BC8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11779 0x00001BCC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11780 0x00001BD0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11781 0x00001BD4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11782 0x00001BD8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11783 0x00001BDC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11784 0x00001BE0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11785 0x00001BE4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11786 0x00001BE8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11787 0x00001BEC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11788 0x00001BF0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11789 0x00001BF4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11790 0x00001BF8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11791 0x00001BFC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11792 0x00001C00
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11793 0x00001C04
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11794 0x00001C08
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11795 0x00001C0C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11796 0x00001C10
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11797 0x00001C14
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11798 0x00001C18
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11799 0x00001C1C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11800 0x00001C20
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11801 0x00001C24
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11802 0x00001C28
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11803 0x00001C2C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11804 0x00001C30
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11805 0x00001C34
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11806 0x00001C38
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11807 0x00001C3C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11808 0x00001C40
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11809 0x00001C44
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11810 0x00001C48
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11811 0x00001C4C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11812 0x00001C50
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11813 0x00001C54
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11814 0x00001C58
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11815 0x00001C5C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11816 0x00001C60
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11817 0x00001C64
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11818 0x00001C68
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11819 0x00001C6C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11820 0x00001C70
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11821 0x00001C74
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11822 0x00001C78
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11823 0x00001C7C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11824 0x00001C80
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11825 0x00001C84
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11826 0x00001C88
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11827 0x00001C8C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11828 0x00001C90
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11829 0x00001C94
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11830 0x00001C98
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11831 0x00001C9C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11832 0x00001CA0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11833 0x00001CA4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11834 0x00001CA8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11835 0x00001CAC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11836 0x00001CB0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11837 0x00001CB4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11838 0x00001CB8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11839 0x00001CBC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11840 0x00001CC0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11841 0x00001CC4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11842 0x00001CC8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11843 0x00001CCC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11844 0x00001CD0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11845 0x00001CD4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11846 0x00001CD8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11847 0x00001CDC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11848 0x00001CE0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11849 0x00001CE4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11850 0x00001CE8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11851 0x00001CEC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11852 0x00001CF0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11853 0x00001CF4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11854 0x00001CF8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11855 0x00001CFC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11856 0x00001D00
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11857 0x00001D04
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11858 0x00001D08
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11859 0x00001D0C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11860 0x00001D10
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11861 0x00001D14
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11862 0x00001D18
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11863 0x00001D1C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11864 0x00001D20
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11865 0x00001D24
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11866 0x00001D28
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11867 0x00001D2C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11868 0x00001D30
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11869 0x00001D34
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11870 0x00001D38
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11871 0x00001D3C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11872 0x00001D40
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11873 0x00001D44
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11874 0x00001D48
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11875 0x00001D4C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11876 0x00001D50
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11877 0x00001D54
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11878 0x00001D58
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11879 0x00001D5C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11880 0x00001D60
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11881 0x00001D64
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11882 0x00001D68
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11883 0x00001D6C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11884 0x00001D70
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11885 0x00001D74
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11886 0x00001D78
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11887 0x00001D7C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11888 0x00001D80
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11889 0x00001D84
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11890 0x00001D88
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11891 0x00001D8C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11892 0x00001D90
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11893 0x00001D94
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11894 0x00001D98
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11895 0x00001D9C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11896 0x00001DA0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11897 0x00001DA4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11898 0x00001DA8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11899 0x00001DAC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11900 0x00001DB0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11901 0x00001DB4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11902 0x00001DB8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11903 0x00001DBC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11904 0x00001DC0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11905 0x00001DC4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11906 0x00001DC8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11907 0x00001DCC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11908 0x00001DD0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11909 0x00001DD4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11910 0x00001DD8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11911 0x00001DDC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11912 0x00001DE0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11913 0x00001DE4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11914 0x00001DE8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11915 0x00001DEC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11916 0x00001DF0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11917 0x00001DF4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11918 0x00001DF8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11919 0x00001DFC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11920 0x00001E00
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11921 0x00001E04
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11922 0x00001E08
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11923 0x00001E0C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11924 0x00001E10
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11925 0x00001E14
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11926 0x00001E18
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11927 0x00001E1C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11928 0x00001E20
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11929 0x00001E24
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11930 0x00001E28
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11931 0x00001E2C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11932 0x00001E30
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11933 0x00001E34
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11934 0x00001E38
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11935 0x00001E3C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11936 0x00001E40
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11937 0x00001E44
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11938 0x00001E48
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11939 0x00001E4C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11940 0x00001E50
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11941 0x00001E54
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11942 0x00001E58
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11943 0x00001E5C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11944 0x00001E60
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11945 0x00001E64
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11946 0x00001E68
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11947 0x00001E6C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11948 0x00001E70
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11949 0x00001E74
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11950 0x00001E78
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11951 0x00001E7C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11952 0x00001E80
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11953 0x00001E84
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11954 0x00001E88
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11955 0x00001E8C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11956 0x00001E90
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11957 0x00001E94
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11958 0x00001E98
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11959 0x00001E9C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11960 0x00001EA0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11961 0x00001EA4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11962 0x00001EA8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11963 0x00001EAC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11964 0x00001EB0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11965 0x00001EB4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11966 0x00001EB8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11967 0x00001EBC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11968 0x00001EC0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11969 0x00001EC4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11970 0x00001EC8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11971 0x00001ECC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11972 0x00001ED0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11973 0x00001ED4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11974 0x00001ED8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11975 0x00001EDC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11976 0x00001EE0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11977 0x00001EE4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11978 0x00001EE8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11979 0x00001EEC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11980 0x00001EF0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11981 0x00001EF4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11982 0x00001EF8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11983 0x00001EFC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11984 0x00001F00
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11985 0x00001F04
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11986 0x00001F08
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11987 0x00001F0C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11988 0x00001F10
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11989 0x00001F14
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11990 0x00001F18
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11991 0x00001F1C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11992 0x00001F20
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11993 0x00001F24
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11994 0x00001F28
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11995 0x00001F2C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11996 0x00001F30
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11997 0x00001F34
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11998 0x00001F38
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK11999 0x00001F3C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12000 0x00001F40
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12001 0x00001F44
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12002 0x00001F48
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12003 0x00001F4C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12004 0x00001F50
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12005 0x00001F54
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12006 0x00001F58
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12007 0x00001F5C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12008 0x00001F60
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12009 0x00001F64
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12010 0x00001F68
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12011 0x00001F6C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12012 0x00001F70
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12013 0x00001F74
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12014 0x00001F78
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12015 0x00001F7C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12016 0x00001F80
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12017 0x00001F84
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12018 0x00001F88
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12019 0x00001F8C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12020 0x00001F90
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12021 0x00001F94
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12022 0x00001F98
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12023 0x00001F9C
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12024 0x00001FA0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12025 0x00001FA4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12026 0x00001FA8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12027 0x00001FAC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12028 0x00001FB0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12029 0x00001FB4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12030 0x00001FB8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12031 0x00001FBC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12032 0x00001FC0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12033 0x00001FC4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12034 0x00001FC8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12035 0x00001FCC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12036 0x00001FD0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12037 0x00001FD4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12038 0x00001FD8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12039 0x00001FDC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12040 0x00001FE0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12041 0x00001FE4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12042 0x00001FE8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12043 0x00001FEC
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12044 0x00001FF0
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12045 0x00001FF4
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12046 0x00001FF8
+
+// 8 kB ULL SRAM
+#define RFC_ULLRAM_O_BANK12047 0x00001FFC
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK10
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK10_DATA_W 32
+#define RFC_ULLRAM_BANK10_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK10_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11_DATA_W 32
+#define RFC_ULLRAM_BANK11_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12_DATA_W 32
+#define RFC_ULLRAM_BANK12_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK13
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK13_DATA_W 32
+#define RFC_ULLRAM_BANK13_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK13_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK14
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK14_DATA_W 32
+#define RFC_ULLRAM_BANK14_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK14_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK15
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK15_DATA_W 32
+#define RFC_ULLRAM_BANK15_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK15_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK16
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK16_DATA_W 32
+#define RFC_ULLRAM_BANK16_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK16_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK17
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK17_DATA_W 32
+#define RFC_ULLRAM_BANK17_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK17_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK18
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK18_DATA_W 32
+#define RFC_ULLRAM_BANK18_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK18_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK19
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK19_DATA_W 32
+#define RFC_ULLRAM_BANK19_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK19_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK110
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK110_DATA_W 32
+#define RFC_ULLRAM_BANK110_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK110_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK111
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK111_DATA_W 32
+#define RFC_ULLRAM_BANK111_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK111_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK112
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK112_DATA_W 32
+#define RFC_ULLRAM_BANK112_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK112_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK113
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK113_DATA_W 32
+#define RFC_ULLRAM_BANK113_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK113_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK114
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK114_DATA_W 32
+#define RFC_ULLRAM_BANK114_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK114_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK115
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK115_DATA_W 32
+#define RFC_ULLRAM_BANK115_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK115_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK116
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK116_DATA_W 32
+#define RFC_ULLRAM_BANK116_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK116_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK117
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK117_DATA_W 32
+#define RFC_ULLRAM_BANK117_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK117_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK118
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK118_DATA_W 32
+#define RFC_ULLRAM_BANK118_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK118_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK119
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK119_DATA_W 32
+#define RFC_ULLRAM_BANK119_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK119_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK120
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK120_DATA_W 32
+#define RFC_ULLRAM_BANK120_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK120_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK121
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK121_DATA_W 32
+#define RFC_ULLRAM_BANK121_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK121_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK122
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK122_DATA_W 32
+#define RFC_ULLRAM_BANK122_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK122_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK123
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK123_DATA_W 32
+#define RFC_ULLRAM_BANK123_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK123_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK124
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK124_DATA_W 32
+#define RFC_ULLRAM_BANK124_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK124_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK125
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK125_DATA_W 32
+#define RFC_ULLRAM_BANK125_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK125_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK126
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK126_DATA_W 32
+#define RFC_ULLRAM_BANK126_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK126_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK127
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK127_DATA_W 32
+#define RFC_ULLRAM_BANK127_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK127_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK128
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK128_DATA_W 32
+#define RFC_ULLRAM_BANK128_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK128_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK129
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK129_DATA_W 32
+#define RFC_ULLRAM_BANK129_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK129_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK130
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK130_DATA_W 32
+#define RFC_ULLRAM_BANK130_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK130_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK131
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK131_DATA_W 32
+#define RFC_ULLRAM_BANK131_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK131_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK132
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK132_DATA_W 32
+#define RFC_ULLRAM_BANK132_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK132_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK133
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK133_DATA_W 32
+#define RFC_ULLRAM_BANK133_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK133_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK134
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK134_DATA_W 32
+#define RFC_ULLRAM_BANK134_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK134_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK135
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK135_DATA_W 32
+#define RFC_ULLRAM_BANK135_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK135_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK136
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK136_DATA_W 32
+#define RFC_ULLRAM_BANK136_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK136_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK137
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK137_DATA_W 32
+#define RFC_ULLRAM_BANK137_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK137_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK138
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK138_DATA_W 32
+#define RFC_ULLRAM_BANK138_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK138_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK139
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK139_DATA_W 32
+#define RFC_ULLRAM_BANK139_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK139_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK140
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK140_DATA_W 32
+#define RFC_ULLRAM_BANK140_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK140_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK141
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK141_DATA_W 32
+#define RFC_ULLRAM_BANK141_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK141_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK142
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK142_DATA_W 32
+#define RFC_ULLRAM_BANK142_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK142_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK143
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK143_DATA_W 32
+#define RFC_ULLRAM_BANK143_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK143_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK144
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK144_DATA_W 32
+#define RFC_ULLRAM_BANK144_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK144_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK145
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK145_DATA_W 32
+#define RFC_ULLRAM_BANK145_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK145_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK146
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK146_DATA_W 32
+#define RFC_ULLRAM_BANK146_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK146_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK147
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK147_DATA_W 32
+#define RFC_ULLRAM_BANK147_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK147_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK148
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK148_DATA_W 32
+#define RFC_ULLRAM_BANK148_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK148_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK149
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK149_DATA_W 32
+#define RFC_ULLRAM_BANK149_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK149_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK150
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK150_DATA_W 32
+#define RFC_ULLRAM_BANK150_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK150_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK151
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK151_DATA_W 32
+#define RFC_ULLRAM_BANK151_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK151_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK152
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK152_DATA_W 32
+#define RFC_ULLRAM_BANK152_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK152_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK153
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK153_DATA_W 32
+#define RFC_ULLRAM_BANK153_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK153_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK154
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK154_DATA_W 32
+#define RFC_ULLRAM_BANK154_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK154_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK155
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK155_DATA_W 32
+#define RFC_ULLRAM_BANK155_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK155_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK156
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK156_DATA_W 32
+#define RFC_ULLRAM_BANK156_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK156_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK157
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK157_DATA_W 32
+#define RFC_ULLRAM_BANK157_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK157_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK158
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK158_DATA_W 32
+#define RFC_ULLRAM_BANK158_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK158_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK159
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK159_DATA_W 32
+#define RFC_ULLRAM_BANK159_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK159_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK160
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK160_DATA_W 32
+#define RFC_ULLRAM_BANK160_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK160_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK161
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK161_DATA_W 32
+#define RFC_ULLRAM_BANK161_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK161_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK162
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK162_DATA_W 32
+#define RFC_ULLRAM_BANK162_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK162_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK163
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK163_DATA_W 32
+#define RFC_ULLRAM_BANK163_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK163_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK164
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK164_DATA_W 32
+#define RFC_ULLRAM_BANK164_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK164_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK165
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK165_DATA_W 32
+#define RFC_ULLRAM_BANK165_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK165_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK166
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK166_DATA_W 32
+#define RFC_ULLRAM_BANK166_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK166_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK167
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK167_DATA_W 32
+#define RFC_ULLRAM_BANK167_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK167_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK168
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK168_DATA_W 32
+#define RFC_ULLRAM_BANK168_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK168_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK169
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK169_DATA_W 32
+#define RFC_ULLRAM_BANK169_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK169_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK170
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK170_DATA_W 32
+#define RFC_ULLRAM_BANK170_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK170_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK171
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK171_DATA_W 32
+#define RFC_ULLRAM_BANK171_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK171_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK172
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK172_DATA_W 32
+#define RFC_ULLRAM_BANK172_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK172_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK173
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK173_DATA_W 32
+#define RFC_ULLRAM_BANK173_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK173_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK174
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK174_DATA_W 32
+#define RFC_ULLRAM_BANK174_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK174_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK175
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK175_DATA_W 32
+#define RFC_ULLRAM_BANK175_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK175_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK176
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK176_DATA_W 32
+#define RFC_ULLRAM_BANK176_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK176_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK177
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK177_DATA_W 32
+#define RFC_ULLRAM_BANK177_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK177_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK178
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK178_DATA_W 32
+#define RFC_ULLRAM_BANK178_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK178_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK179
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK179_DATA_W 32
+#define RFC_ULLRAM_BANK179_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK179_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK180
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK180_DATA_W 32
+#define RFC_ULLRAM_BANK180_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK180_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK181
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK181_DATA_W 32
+#define RFC_ULLRAM_BANK181_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK181_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK182
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK182_DATA_W 32
+#define RFC_ULLRAM_BANK182_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK182_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK183
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK183_DATA_W 32
+#define RFC_ULLRAM_BANK183_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK183_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK184
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK184_DATA_W 32
+#define RFC_ULLRAM_BANK184_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK184_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK185
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK185_DATA_W 32
+#define RFC_ULLRAM_BANK185_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK185_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK186
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK186_DATA_W 32
+#define RFC_ULLRAM_BANK186_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK186_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK187
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK187_DATA_W 32
+#define RFC_ULLRAM_BANK187_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK187_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK188
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK188_DATA_W 32
+#define RFC_ULLRAM_BANK188_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK188_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK189
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK189_DATA_W 32
+#define RFC_ULLRAM_BANK189_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK189_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK190
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK190_DATA_W 32
+#define RFC_ULLRAM_BANK190_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK190_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK191
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK191_DATA_W 32
+#define RFC_ULLRAM_BANK191_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK191_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK192
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK192_DATA_W 32
+#define RFC_ULLRAM_BANK192_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK192_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK193
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK193_DATA_W 32
+#define RFC_ULLRAM_BANK193_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK193_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK194
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK194_DATA_W 32
+#define RFC_ULLRAM_BANK194_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK194_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK195
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK195_DATA_W 32
+#define RFC_ULLRAM_BANK195_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK195_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK196
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK196_DATA_W 32
+#define RFC_ULLRAM_BANK196_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK196_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK197
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK197_DATA_W 32
+#define RFC_ULLRAM_BANK197_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK197_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK198
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK198_DATA_W 32
+#define RFC_ULLRAM_BANK198_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK198_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK199
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK199_DATA_W 32
+#define RFC_ULLRAM_BANK199_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK199_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1100
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1100_DATA_W 32
+#define RFC_ULLRAM_BANK1100_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1100_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1101
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1101_DATA_W 32
+#define RFC_ULLRAM_BANK1101_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1101_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1102
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1102_DATA_W 32
+#define RFC_ULLRAM_BANK1102_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1102_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1103
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1103_DATA_W 32
+#define RFC_ULLRAM_BANK1103_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1103_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1104
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1104_DATA_W 32
+#define RFC_ULLRAM_BANK1104_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1104_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1105
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1105_DATA_W 32
+#define RFC_ULLRAM_BANK1105_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1105_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1106
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1106_DATA_W 32
+#define RFC_ULLRAM_BANK1106_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1106_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1107
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1107_DATA_W 32
+#define RFC_ULLRAM_BANK1107_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1107_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1108
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1108_DATA_W 32
+#define RFC_ULLRAM_BANK1108_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1108_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1109
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1109_DATA_W 32
+#define RFC_ULLRAM_BANK1109_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1109_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1110
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1110_DATA_W 32
+#define RFC_ULLRAM_BANK1110_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1110_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1111
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1111_DATA_W 32
+#define RFC_ULLRAM_BANK1111_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1111_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1112
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1112_DATA_W 32
+#define RFC_ULLRAM_BANK1112_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1112_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1113
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1113_DATA_W 32
+#define RFC_ULLRAM_BANK1113_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1113_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1114
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1114_DATA_W 32
+#define RFC_ULLRAM_BANK1114_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1114_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1115
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1115_DATA_W 32
+#define RFC_ULLRAM_BANK1115_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1115_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1116
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1116_DATA_W 32
+#define RFC_ULLRAM_BANK1116_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1116_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1117
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1117_DATA_W 32
+#define RFC_ULLRAM_BANK1117_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1117_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1118
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1118_DATA_W 32
+#define RFC_ULLRAM_BANK1118_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1118_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1119
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1119_DATA_W 32
+#define RFC_ULLRAM_BANK1119_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1119_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1120
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1120_DATA_W 32
+#define RFC_ULLRAM_BANK1120_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1120_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1121
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1121_DATA_W 32
+#define RFC_ULLRAM_BANK1121_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1121_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1122
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1122_DATA_W 32
+#define RFC_ULLRAM_BANK1122_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1122_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1123
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1123_DATA_W 32
+#define RFC_ULLRAM_BANK1123_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1123_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1124
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1124_DATA_W 32
+#define RFC_ULLRAM_BANK1124_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1124_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1125
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1125_DATA_W 32
+#define RFC_ULLRAM_BANK1125_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1125_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1126
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1126_DATA_W 32
+#define RFC_ULLRAM_BANK1126_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1126_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1127
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1127_DATA_W 32
+#define RFC_ULLRAM_BANK1127_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1127_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1128
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1128_DATA_W 32
+#define RFC_ULLRAM_BANK1128_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1128_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1129
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1129_DATA_W 32
+#define RFC_ULLRAM_BANK1129_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1129_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1130
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1130_DATA_W 32
+#define RFC_ULLRAM_BANK1130_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1130_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1131
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1131_DATA_W 32
+#define RFC_ULLRAM_BANK1131_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1131_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1132
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1132_DATA_W 32
+#define RFC_ULLRAM_BANK1132_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1132_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1133
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1133_DATA_W 32
+#define RFC_ULLRAM_BANK1133_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1133_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1134
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1134_DATA_W 32
+#define RFC_ULLRAM_BANK1134_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1134_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1135
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1135_DATA_W 32
+#define RFC_ULLRAM_BANK1135_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1135_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1136
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1136_DATA_W 32
+#define RFC_ULLRAM_BANK1136_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1136_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1137
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1137_DATA_W 32
+#define RFC_ULLRAM_BANK1137_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1137_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1138
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1138_DATA_W 32
+#define RFC_ULLRAM_BANK1138_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1138_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1139
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1139_DATA_W 32
+#define RFC_ULLRAM_BANK1139_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1139_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1140
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1140_DATA_W 32
+#define RFC_ULLRAM_BANK1140_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1140_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1141
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1141_DATA_W 32
+#define RFC_ULLRAM_BANK1141_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1141_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1142
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1142_DATA_W 32
+#define RFC_ULLRAM_BANK1142_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1142_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1143
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1143_DATA_W 32
+#define RFC_ULLRAM_BANK1143_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1143_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1144
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1144_DATA_W 32
+#define RFC_ULLRAM_BANK1144_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1144_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1145
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1145_DATA_W 32
+#define RFC_ULLRAM_BANK1145_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1145_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1146
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1146_DATA_W 32
+#define RFC_ULLRAM_BANK1146_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1146_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1147
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1147_DATA_W 32
+#define RFC_ULLRAM_BANK1147_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1147_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1148
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1148_DATA_W 32
+#define RFC_ULLRAM_BANK1148_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1148_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1149
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1149_DATA_W 32
+#define RFC_ULLRAM_BANK1149_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1149_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1150
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1150_DATA_W 32
+#define RFC_ULLRAM_BANK1150_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1150_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1151
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1151_DATA_W 32
+#define RFC_ULLRAM_BANK1151_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1151_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1152
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1152_DATA_W 32
+#define RFC_ULLRAM_BANK1152_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1152_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1153
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1153_DATA_W 32
+#define RFC_ULLRAM_BANK1153_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1153_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1154
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1154_DATA_W 32
+#define RFC_ULLRAM_BANK1154_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1154_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1155
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1155_DATA_W 32
+#define RFC_ULLRAM_BANK1155_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1155_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1156
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1156_DATA_W 32
+#define RFC_ULLRAM_BANK1156_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1156_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1157
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1157_DATA_W 32
+#define RFC_ULLRAM_BANK1157_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1157_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1158
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1158_DATA_W 32
+#define RFC_ULLRAM_BANK1158_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1158_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1159
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1159_DATA_W 32
+#define RFC_ULLRAM_BANK1159_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1159_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1160
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1160_DATA_W 32
+#define RFC_ULLRAM_BANK1160_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1160_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1161
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1161_DATA_W 32
+#define RFC_ULLRAM_BANK1161_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1161_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1162
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1162_DATA_W 32
+#define RFC_ULLRAM_BANK1162_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1162_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1163
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1163_DATA_W 32
+#define RFC_ULLRAM_BANK1163_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1163_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1164
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1164_DATA_W 32
+#define RFC_ULLRAM_BANK1164_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1164_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1165
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1165_DATA_W 32
+#define RFC_ULLRAM_BANK1165_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1165_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1166
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1166_DATA_W 32
+#define RFC_ULLRAM_BANK1166_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1166_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1167
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1167_DATA_W 32
+#define RFC_ULLRAM_BANK1167_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1167_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1168
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1168_DATA_W 32
+#define RFC_ULLRAM_BANK1168_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1168_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1169
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1169_DATA_W 32
+#define RFC_ULLRAM_BANK1169_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1169_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1170
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1170_DATA_W 32
+#define RFC_ULLRAM_BANK1170_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1170_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1171
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1171_DATA_W 32
+#define RFC_ULLRAM_BANK1171_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1171_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1172
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1172_DATA_W 32
+#define RFC_ULLRAM_BANK1172_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1172_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1173
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1173_DATA_W 32
+#define RFC_ULLRAM_BANK1173_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1173_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1174
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1174_DATA_W 32
+#define RFC_ULLRAM_BANK1174_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1174_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1175
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1175_DATA_W 32
+#define RFC_ULLRAM_BANK1175_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1175_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1176
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1176_DATA_W 32
+#define RFC_ULLRAM_BANK1176_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1176_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1177
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1177_DATA_W 32
+#define RFC_ULLRAM_BANK1177_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1177_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1178
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1178_DATA_W 32
+#define RFC_ULLRAM_BANK1178_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1178_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1179
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1179_DATA_W 32
+#define RFC_ULLRAM_BANK1179_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1179_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1180
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1180_DATA_W 32
+#define RFC_ULLRAM_BANK1180_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1180_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1181
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1181_DATA_W 32
+#define RFC_ULLRAM_BANK1181_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1181_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1182
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1182_DATA_W 32
+#define RFC_ULLRAM_BANK1182_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1182_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1183
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1183_DATA_W 32
+#define RFC_ULLRAM_BANK1183_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1183_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1184
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1184_DATA_W 32
+#define RFC_ULLRAM_BANK1184_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1184_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1185
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1185_DATA_W 32
+#define RFC_ULLRAM_BANK1185_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1185_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1186
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1186_DATA_W 32
+#define RFC_ULLRAM_BANK1186_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1186_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1187
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1187_DATA_W 32
+#define RFC_ULLRAM_BANK1187_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1187_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1188
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1188_DATA_W 32
+#define RFC_ULLRAM_BANK1188_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1188_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1189
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1189_DATA_W 32
+#define RFC_ULLRAM_BANK1189_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1189_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1190
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1190_DATA_W 32
+#define RFC_ULLRAM_BANK1190_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1190_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1191
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1191_DATA_W 32
+#define RFC_ULLRAM_BANK1191_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1191_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1192
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1192_DATA_W 32
+#define RFC_ULLRAM_BANK1192_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1192_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1193
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1193_DATA_W 32
+#define RFC_ULLRAM_BANK1193_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1193_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1194
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1194_DATA_W 32
+#define RFC_ULLRAM_BANK1194_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1194_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1195
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1195_DATA_W 32
+#define RFC_ULLRAM_BANK1195_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1195_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1196
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1196_DATA_W 32
+#define RFC_ULLRAM_BANK1196_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1196_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1197
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1197_DATA_W 32
+#define RFC_ULLRAM_BANK1197_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1197_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1198
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1198_DATA_W 32
+#define RFC_ULLRAM_BANK1198_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1198_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1199
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1199_DATA_W 32
+#define RFC_ULLRAM_BANK1199_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1199_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1200
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1200_DATA_W 32
+#define RFC_ULLRAM_BANK1200_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1200_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1201
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1201_DATA_W 32
+#define RFC_ULLRAM_BANK1201_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1201_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1202
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1202_DATA_W 32
+#define RFC_ULLRAM_BANK1202_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1202_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1203
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1203_DATA_W 32
+#define RFC_ULLRAM_BANK1203_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1203_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1204
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1204_DATA_W 32
+#define RFC_ULLRAM_BANK1204_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1204_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1205
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1205_DATA_W 32
+#define RFC_ULLRAM_BANK1205_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1205_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1206
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1206_DATA_W 32
+#define RFC_ULLRAM_BANK1206_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1206_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1207
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1207_DATA_W 32
+#define RFC_ULLRAM_BANK1207_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1207_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1208
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1208_DATA_W 32
+#define RFC_ULLRAM_BANK1208_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1208_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1209
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1209_DATA_W 32
+#define RFC_ULLRAM_BANK1209_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1209_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1210
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1210_DATA_W 32
+#define RFC_ULLRAM_BANK1210_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1210_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1211
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1211_DATA_W 32
+#define RFC_ULLRAM_BANK1211_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1211_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1212
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1212_DATA_W 32
+#define RFC_ULLRAM_BANK1212_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1212_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1213
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1213_DATA_W 32
+#define RFC_ULLRAM_BANK1213_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1213_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1214
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1214_DATA_W 32
+#define RFC_ULLRAM_BANK1214_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1214_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1215
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1215_DATA_W 32
+#define RFC_ULLRAM_BANK1215_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1215_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1216
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1216_DATA_W 32
+#define RFC_ULLRAM_BANK1216_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1216_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1217
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1217_DATA_W 32
+#define RFC_ULLRAM_BANK1217_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1217_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1218
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1218_DATA_W 32
+#define RFC_ULLRAM_BANK1218_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1218_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1219
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1219_DATA_W 32
+#define RFC_ULLRAM_BANK1219_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1219_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1220
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1220_DATA_W 32
+#define RFC_ULLRAM_BANK1220_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1220_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1221
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1221_DATA_W 32
+#define RFC_ULLRAM_BANK1221_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1221_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1222
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1222_DATA_W 32
+#define RFC_ULLRAM_BANK1222_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1222_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1223
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1223_DATA_W 32
+#define RFC_ULLRAM_BANK1223_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1223_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1224
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1224_DATA_W 32
+#define RFC_ULLRAM_BANK1224_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1224_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1225
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1225_DATA_W 32
+#define RFC_ULLRAM_BANK1225_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1225_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1226
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1226_DATA_W 32
+#define RFC_ULLRAM_BANK1226_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1226_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1227
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1227_DATA_W 32
+#define RFC_ULLRAM_BANK1227_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1227_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1228
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1228_DATA_W 32
+#define RFC_ULLRAM_BANK1228_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1228_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1229
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1229_DATA_W 32
+#define RFC_ULLRAM_BANK1229_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1229_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1230
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1230_DATA_W 32
+#define RFC_ULLRAM_BANK1230_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1230_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1231
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1231_DATA_W 32
+#define RFC_ULLRAM_BANK1231_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1231_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1232
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1232_DATA_W 32
+#define RFC_ULLRAM_BANK1232_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1232_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1233
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1233_DATA_W 32
+#define RFC_ULLRAM_BANK1233_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1233_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1234
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1234_DATA_W 32
+#define RFC_ULLRAM_BANK1234_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1234_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1235
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1235_DATA_W 32
+#define RFC_ULLRAM_BANK1235_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1235_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1236
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1236_DATA_W 32
+#define RFC_ULLRAM_BANK1236_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1236_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1237
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1237_DATA_W 32
+#define RFC_ULLRAM_BANK1237_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1237_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1238
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1238_DATA_W 32
+#define RFC_ULLRAM_BANK1238_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1238_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1239
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1239_DATA_W 32
+#define RFC_ULLRAM_BANK1239_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1239_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1240
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1240_DATA_W 32
+#define RFC_ULLRAM_BANK1240_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1240_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1241
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1241_DATA_W 32
+#define RFC_ULLRAM_BANK1241_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1241_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1242
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1242_DATA_W 32
+#define RFC_ULLRAM_BANK1242_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1242_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1243
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1243_DATA_W 32
+#define RFC_ULLRAM_BANK1243_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1243_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1244
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1244_DATA_W 32
+#define RFC_ULLRAM_BANK1244_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1244_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1245
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1245_DATA_W 32
+#define RFC_ULLRAM_BANK1245_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1245_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1246
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1246_DATA_W 32
+#define RFC_ULLRAM_BANK1246_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1246_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1247
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1247_DATA_W 32
+#define RFC_ULLRAM_BANK1247_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1247_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1248
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1248_DATA_W 32
+#define RFC_ULLRAM_BANK1248_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1248_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1249
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1249_DATA_W 32
+#define RFC_ULLRAM_BANK1249_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1249_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1250
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1250_DATA_W 32
+#define RFC_ULLRAM_BANK1250_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1250_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1251
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1251_DATA_W 32
+#define RFC_ULLRAM_BANK1251_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1251_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1252
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1252_DATA_W 32
+#define RFC_ULLRAM_BANK1252_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1252_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1253
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1253_DATA_W 32
+#define RFC_ULLRAM_BANK1253_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1253_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1254
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1254_DATA_W 32
+#define RFC_ULLRAM_BANK1254_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1254_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1255
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1255_DATA_W 32
+#define RFC_ULLRAM_BANK1255_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1255_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1256
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1256_DATA_W 32
+#define RFC_ULLRAM_BANK1256_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1256_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1257
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1257_DATA_W 32
+#define RFC_ULLRAM_BANK1257_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1257_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1258
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1258_DATA_W 32
+#define RFC_ULLRAM_BANK1258_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1258_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1259
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1259_DATA_W 32
+#define RFC_ULLRAM_BANK1259_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1259_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1260
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1260_DATA_W 32
+#define RFC_ULLRAM_BANK1260_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1260_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1261
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1261_DATA_W 32
+#define RFC_ULLRAM_BANK1261_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1261_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1262
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1262_DATA_W 32
+#define RFC_ULLRAM_BANK1262_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1262_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1263
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1263_DATA_W 32
+#define RFC_ULLRAM_BANK1263_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1263_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1264
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1264_DATA_W 32
+#define RFC_ULLRAM_BANK1264_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1264_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1265
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1265_DATA_W 32
+#define RFC_ULLRAM_BANK1265_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1265_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1266
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1266_DATA_W 32
+#define RFC_ULLRAM_BANK1266_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1266_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1267
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1267_DATA_W 32
+#define RFC_ULLRAM_BANK1267_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1267_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1268
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1268_DATA_W 32
+#define RFC_ULLRAM_BANK1268_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1268_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1269
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1269_DATA_W 32
+#define RFC_ULLRAM_BANK1269_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1269_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1270
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1270_DATA_W 32
+#define RFC_ULLRAM_BANK1270_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1270_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1271
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1271_DATA_W 32
+#define RFC_ULLRAM_BANK1271_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1271_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1272
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1272_DATA_W 32
+#define RFC_ULLRAM_BANK1272_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1272_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1273
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1273_DATA_W 32
+#define RFC_ULLRAM_BANK1273_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1273_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1274
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1274_DATA_W 32
+#define RFC_ULLRAM_BANK1274_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1274_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1275
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1275_DATA_W 32
+#define RFC_ULLRAM_BANK1275_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1275_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1276
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1276_DATA_W 32
+#define RFC_ULLRAM_BANK1276_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1276_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1277
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1277_DATA_W 32
+#define RFC_ULLRAM_BANK1277_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1277_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1278
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1278_DATA_W 32
+#define RFC_ULLRAM_BANK1278_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1278_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1279
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1279_DATA_W 32
+#define RFC_ULLRAM_BANK1279_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1279_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1280
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1280_DATA_W 32
+#define RFC_ULLRAM_BANK1280_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1280_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1281
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1281_DATA_W 32
+#define RFC_ULLRAM_BANK1281_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1281_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1282
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1282_DATA_W 32
+#define RFC_ULLRAM_BANK1282_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1282_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1283
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1283_DATA_W 32
+#define RFC_ULLRAM_BANK1283_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1283_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1284
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1284_DATA_W 32
+#define RFC_ULLRAM_BANK1284_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1284_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1285
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1285_DATA_W 32
+#define RFC_ULLRAM_BANK1285_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1285_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1286
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1286_DATA_W 32
+#define RFC_ULLRAM_BANK1286_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1286_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1287
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1287_DATA_W 32
+#define RFC_ULLRAM_BANK1287_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1287_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1288
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1288_DATA_W 32
+#define RFC_ULLRAM_BANK1288_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1288_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1289
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1289_DATA_W 32
+#define RFC_ULLRAM_BANK1289_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1289_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1290
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1290_DATA_W 32
+#define RFC_ULLRAM_BANK1290_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1290_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1291
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1291_DATA_W 32
+#define RFC_ULLRAM_BANK1291_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1291_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1292
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1292_DATA_W 32
+#define RFC_ULLRAM_BANK1292_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1292_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1293
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1293_DATA_W 32
+#define RFC_ULLRAM_BANK1293_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1293_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1294
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1294_DATA_W 32
+#define RFC_ULLRAM_BANK1294_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1294_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1295
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1295_DATA_W 32
+#define RFC_ULLRAM_BANK1295_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1295_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1296
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1296_DATA_W 32
+#define RFC_ULLRAM_BANK1296_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1296_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1297
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1297_DATA_W 32
+#define RFC_ULLRAM_BANK1297_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1297_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1298
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1298_DATA_W 32
+#define RFC_ULLRAM_BANK1298_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1298_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1299
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1299_DATA_W 32
+#define RFC_ULLRAM_BANK1299_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1299_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1300
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1300_DATA_W 32
+#define RFC_ULLRAM_BANK1300_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1300_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1301
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1301_DATA_W 32
+#define RFC_ULLRAM_BANK1301_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1301_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1302
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1302_DATA_W 32
+#define RFC_ULLRAM_BANK1302_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1302_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1303
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1303_DATA_W 32
+#define RFC_ULLRAM_BANK1303_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1303_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1304
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1304_DATA_W 32
+#define RFC_ULLRAM_BANK1304_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1304_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1305
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1305_DATA_W 32
+#define RFC_ULLRAM_BANK1305_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1305_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1306
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1306_DATA_W 32
+#define RFC_ULLRAM_BANK1306_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1306_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1307
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1307_DATA_W 32
+#define RFC_ULLRAM_BANK1307_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1307_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1308
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1308_DATA_W 32
+#define RFC_ULLRAM_BANK1308_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1308_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1309
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1309_DATA_W 32
+#define RFC_ULLRAM_BANK1309_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1309_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1310
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1310_DATA_W 32
+#define RFC_ULLRAM_BANK1310_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1310_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1311
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1311_DATA_W 32
+#define RFC_ULLRAM_BANK1311_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1311_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1312
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1312_DATA_W 32
+#define RFC_ULLRAM_BANK1312_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1312_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1313
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1313_DATA_W 32
+#define RFC_ULLRAM_BANK1313_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1313_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1314
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1314_DATA_W 32
+#define RFC_ULLRAM_BANK1314_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1314_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1315
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1315_DATA_W 32
+#define RFC_ULLRAM_BANK1315_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1315_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1316
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1316_DATA_W 32
+#define RFC_ULLRAM_BANK1316_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1316_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1317
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1317_DATA_W 32
+#define RFC_ULLRAM_BANK1317_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1317_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1318
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1318_DATA_W 32
+#define RFC_ULLRAM_BANK1318_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1318_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1319
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1319_DATA_W 32
+#define RFC_ULLRAM_BANK1319_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1319_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1320
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1320_DATA_W 32
+#define RFC_ULLRAM_BANK1320_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1320_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1321
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1321_DATA_W 32
+#define RFC_ULLRAM_BANK1321_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1321_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1322
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1322_DATA_W 32
+#define RFC_ULLRAM_BANK1322_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1322_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1323
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1323_DATA_W 32
+#define RFC_ULLRAM_BANK1323_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1323_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1324
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1324_DATA_W 32
+#define RFC_ULLRAM_BANK1324_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1324_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1325
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1325_DATA_W 32
+#define RFC_ULLRAM_BANK1325_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1325_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1326
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1326_DATA_W 32
+#define RFC_ULLRAM_BANK1326_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1326_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1327
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1327_DATA_W 32
+#define RFC_ULLRAM_BANK1327_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1327_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1328
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1328_DATA_W 32
+#define RFC_ULLRAM_BANK1328_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1328_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1329
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1329_DATA_W 32
+#define RFC_ULLRAM_BANK1329_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1329_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1330
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1330_DATA_W 32
+#define RFC_ULLRAM_BANK1330_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1330_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1331
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1331_DATA_W 32
+#define RFC_ULLRAM_BANK1331_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1331_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1332
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1332_DATA_W 32
+#define RFC_ULLRAM_BANK1332_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1332_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1333
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1333_DATA_W 32
+#define RFC_ULLRAM_BANK1333_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1333_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1334
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1334_DATA_W 32
+#define RFC_ULLRAM_BANK1334_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1334_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1335
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1335_DATA_W 32
+#define RFC_ULLRAM_BANK1335_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1335_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1336
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1336_DATA_W 32
+#define RFC_ULLRAM_BANK1336_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1336_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1337
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1337_DATA_W 32
+#define RFC_ULLRAM_BANK1337_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1337_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1338
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1338_DATA_W 32
+#define RFC_ULLRAM_BANK1338_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1338_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1339
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1339_DATA_W 32
+#define RFC_ULLRAM_BANK1339_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1339_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1340
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1340_DATA_W 32
+#define RFC_ULLRAM_BANK1340_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1340_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1341
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1341_DATA_W 32
+#define RFC_ULLRAM_BANK1341_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1341_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1342
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1342_DATA_W 32
+#define RFC_ULLRAM_BANK1342_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1342_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1343
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1343_DATA_W 32
+#define RFC_ULLRAM_BANK1343_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1343_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1344
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1344_DATA_W 32
+#define RFC_ULLRAM_BANK1344_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1344_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1345
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1345_DATA_W 32
+#define RFC_ULLRAM_BANK1345_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1345_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1346
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1346_DATA_W 32
+#define RFC_ULLRAM_BANK1346_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1346_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1347
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1347_DATA_W 32
+#define RFC_ULLRAM_BANK1347_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1347_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1348
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1348_DATA_W 32
+#define RFC_ULLRAM_BANK1348_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1348_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1349
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1349_DATA_W 32
+#define RFC_ULLRAM_BANK1349_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1349_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1350
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1350_DATA_W 32
+#define RFC_ULLRAM_BANK1350_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1350_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1351
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1351_DATA_W 32
+#define RFC_ULLRAM_BANK1351_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1351_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1352
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1352_DATA_W 32
+#define RFC_ULLRAM_BANK1352_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1352_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1353
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1353_DATA_W 32
+#define RFC_ULLRAM_BANK1353_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1353_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1354
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1354_DATA_W 32
+#define RFC_ULLRAM_BANK1354_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1354_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1355
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1355_DATA_W 32
+#define RFC_ULLRAM_BANK1355_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1355_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1356
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1356_DATA_W 32
+#define RFC_ULLRAM_BANK1356_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1356_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1357
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1357_DATA_W 32
+#define RFC_ULLRAM_BANK1357_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1357_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1358
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1358_DATA_W 32
+#define RFC_ULLRAM_BANK1358_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1358_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1359
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1359_DATA_W 32
+#define RFC_ULLRAM_BANK1359_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1359_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1360
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1360_DATA_W 32
+#define RFC_ULLRAM_BANK1360_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1360_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1361
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1361_DATA_W 32
+#define RFC_ULLRAM_BANK1361_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1361_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1362
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1362_DATA_W 32
+#define RFC_ULLRAM_BANK1362_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1362_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1363
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1363_DATA_W 32
+#define RFC_ULLRAM_BANK1363_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1363_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1364
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1364_DATA_W 32
+#define RFC_ULLRAM_BANK1364_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1364_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1365
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1365_DATA_W 32
+#define RFC_ULLRAM_BANK1365_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1365_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1366
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1366_DATA_W 32
+#define RFC_ULLRAM_BANK1366_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1366_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1367
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1367_DATA_W 32
+#define RFC_ULLRAM_BANK1367_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1367_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1368
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1368_DATA_W 32
+#define RFC_ULLRAM_BANK1368_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1368_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1369
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1369_DATA_W 32
+#define RFC_ULLRAM_BANK1369_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1369_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1370
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1370_DATA_W 32
+#define RFC_ULLRAM_BANK1370_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1370_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1371
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1371_DATA_W 32
+#define RFC_ULLRAM_BANK1371_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1371_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1372
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1372_DATA_W 32
+#define RFC_ULLRAM_BANK1372_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1372_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1373
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1373_DATA_W 32
+#define RFC_ULLRAM_BANK1373_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1373_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1374
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1374_DATA_W 32
+#define RFC_ULLRAM_BANK1374_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1374_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1375
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1375_DATA_W 32
+#define RFC_ULLRAM_BANK1375_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1375_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1376
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1376_DATA_W 32
+#define RFC_ULLRAM_BANK1376_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1376_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1377
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1377_DATA_W 32
+#define RFC_ULLRAM_BANK1377_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1377_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1378
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1378_DATA_W 32
+#define RFC_ULLRAM_BANK1378_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1378_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1379
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1379_DATA_W 32
+#define RFC_ULLRAM_BANK1379_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1379_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1380
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1380_DATA_W 32
+#define RFC_ULLRAM_BANK1380_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1380_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1381
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1381_DATA_W 32
+#define RFC_ULLRAM_BANK1381_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1381_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1382
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1382_DATA_W 32
+#define RFC_ULLRAM_BANK1382_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1382_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1383
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1383_DATA_W 32
+#define RFC_ULLRAM_BANK1383_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1383_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1384
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1384_DATA_W 32
+#define RFC_ULLRAM_BANK1384_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1384_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1385
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1385_DATA_W 32
+#define RFC_ULLRAM_BANK1385_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1385_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1386
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1386_DATA_W 32
+#define RFC_ULLRAM_BANK1386_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1386_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1387
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1387_DATA_W 32
+#define RFC_ULLRAM_BANK1387_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1387_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1388
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1388_DATA_W 32
+#define RFC_ULLRAM_BANK1388_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1388_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1389
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1389_DATA_W 32
+#define RFC_ULLRAM_BANK1389_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1389_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1390
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1390_DATA_W 32
+#define RFC_ULLRAM_BANK1390_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1390_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1391
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1391_DATA_W 32
+#define RFC_ULLRAM_BANK1391_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1391_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1392
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1392_DATA_W 32
+#define RFC_ULLRAM_BANK1392_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1392_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1393
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1393_DATA_W 32
+#define RFC_ULLRAM_BANK1393_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1393_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1394
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1394_DATA_W 32
+#define RFC_ULLRAM_BANK1394_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1394_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1395
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1395_DATA_W 32
+#define RFC_ULLRAM_BANK1395_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1395_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1396
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1396_DATA_W 32
+#define RFC_ULLRAM_BANK1396_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1396_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1397
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1397_DATA_W 32
+#define RFC_ULLRAM_BANK1397_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1397_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1398
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1398_DATA_W 32
+#define RFC_ULLRAM_BANK1398_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1398_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1399
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1399_DATA_W 32
+#define RFC_ULLRAM_BANK1399_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1399_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1400
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1400_DATA_W 32
+#define RFC_ULLRAM_BANK1400_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1400_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1401
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1401_DATA_W 32
+#define RFC_ULLRAM_BANK1401_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1401_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1402
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1402_DATA_W 32
+#define RFC_ULLRAM_BANK1402_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1402_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1403
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1403_DATA_W 32
+#define RFC_ULLRAM_BANK1403_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1403_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1404
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1404_DATA_W 32
+#define RFC_ULLRAM_BANK1404_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1404_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1405
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1405_DATA_W 32
+#define RFC_ULLRAM_BANK1405_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1405_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1406
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1406_DATA_W 32
+#define RFC_ULLRAM_BANK1406_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1406_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1407
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1407_DATA_W 32
+#define RFC_ULLRAM_BANK1407_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1407_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1408
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1408_DATA_W 32
+#define RFC_ULLRAM_BANK1408_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1408_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1409
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1409_DATA_W 32
+#define RFC_ULLRAM_BANK1409_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1409_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1410
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1410_DATA_W 32
+#define RFC_ULLRAM_BANK1410_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1410_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1411
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1411_DATA_W 32
+#define RFC_ULLRAM_BANK1411_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1411_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1412
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1412_DATA_W 32
+#define RFC_ULLRAM_BANK1412_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1412_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1413
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1413_DATA_W 32
+#define RFC_ULLRAM_BANK1413_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1413_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1414
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1414_DATA_W 32
+#define RFC_ULLRAM_BANK1414_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1414_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1415
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1415_DATA_W 32
+#define RFC_ULLRAM_BANK1415_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1415_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1416
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1416_DATA_W 32
+#define RFC_ULLRAM_BANK1416_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1416_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1417
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1417_DATA_W 32
+#define RFC_ULLRAM_BANK1417_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1417_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1418
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1418_DATA_W 32
+#define RFC_ULLRAM_BANK1418_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1418_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1419
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1419_DATA_W 32
+#define RFC_ULLRAM_BANK1419_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1419_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1420
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1420_DATA_W 32
+#define RFC_ULLRAM_BANK1420_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1420_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1421
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1421_DATA_W 32
+#define RFC_ULLRAM_BANK1421_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1421_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1422
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1422_DATA_W 32
+#define RFC_ULLRAM_BANK1422_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1422_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1423
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1423_DATA_W 32
+#define RFC_ULLRAM_BANK1423_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1423_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1424
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1424_DATA_W 32
+#define RFC_ULLRAM_BANK1424_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1424_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1425
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1425_DATA_W 32
+#define RFC_ULLRAM_BANK1425_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1425_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1426
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1426_DATA_W 32
+#define RFC_ULLRAM_BANK1426_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1426_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1427
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1427_DATA_W 32
+#define RFC_ULLRAM_BANK1427_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1427_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1428
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1428_DATA_W 32
+#define RFC_ULLRAM_BANK1428_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1428_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1429
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1429_DATA_W 32
+#define RFC_ULLRAM_BANK1429_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1429_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1430
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1430_DATA_W 32
+#define RFC_ULLRAM_BANK1430_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1430_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1431
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1431_DATA_W 32
+#define RFC_ULLRAM_BANK1431_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1431_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1432
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1432_DATA_W 32
+#define RFC_ULLRAM_BANK1432_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1432_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1433
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1433_DATA_W 32
+#define RFC_ULLRAM_BANK1433_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1433_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1434
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1434_DATA_W 32
+#define RFC_ULLRAM_BANK1434_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1434_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1435
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1435_DATA_W 32
+#define RFC_ULLRAM_BANK1435_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1435_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1436
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1436_DATA_W 32
+#define RFC_ULLRAM_BANK1436_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1436_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1437
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1437_DATA_W 32
+#define RFC_ULLRAM_BANK1437_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1437_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1438
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1438_DATA_W 32
+#define RFC_ULLRAM_BANK1438_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1438_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1439
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1439_DATA_W 32
+#define RFC_ULLRAM_BANK1439_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1439_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1440
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1440_DATA_W 32
+#define RFC_ULLRAM_BANK1440_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1440_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1441
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1441_DATA_W 32
+#define RFC_ULLRAM_BANK1441_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1441_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1442
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1442_DATA_W 32
+#define RFC_ULLRAM_BANK1442_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1442_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1443
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1443_DATA_W 32
+#define RFC_ULLRAM_BANK1443_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1443_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1444
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1444_DATA_W 32
+#define RFC_ULLRAM_BANK1444_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1444_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1445
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1445_DATA_W 32
+#define RFC_ULLRAM_BANK1445_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1445_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1446
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1446_DATA_W 32
+#define RFC_ULLRAM_BANK1446_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1446_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1447
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1447_DATA_W 32
+#define RFC_ULLRAM_BANK1447_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1447_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1448
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1448_DATA_W 32
+#define RFC_ULLRAM_BANK1448_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1448_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1449
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1449_DATA_W 32
+#define RFC_ULLRAM_BANK1449_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1449_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1450
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1450_DATA_W 32
+#define RFC_ULLRAM_BANK1450_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1450_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1451
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1451_DATA_W 32
+#define RFC_ULLRAM_BANK1451_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1451_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1452
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1452_DATA_W 32
+#define RFC_ULLRAM_BANK1452_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1452_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1453
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1453_DATA_W 32
+#define RFC_ULLRAM_BANK1453_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1453_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1454
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1454_DATA_W 32
+#define RFC_ULLRAM_BANK1454_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1454_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1455
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1455_DATA_W 32
+#define RFC_ULLRAM_BANK1455_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1455_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1456
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1456_DATA_W 32
+#define RFC_ULLRAM_BANK1456_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1456_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1457
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1457_DATA_W 32
+#define RFC_ULLRAM_BANK1457_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1457_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1458
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1458_DATA_W 32
+#define RFC_ULLRAM_BANK1458_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1458_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1459
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1459_DATA_W 32
+#define RFC_ULLRAM_BANK1459_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1459_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1460
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1460_DATA_W 32
+#define RFC_ULLRAM_BANK1460_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1460_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1461
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1461_DATA_W 32
+#define RFC_ULLRAM_BANK1461_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1461_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1462
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1462_DATA_W 32
+#define RFC_ULLRAM_BANK1462_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1462_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1463
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1463_DATA_W 32
+#define RFC_ULLRAM_BANK1463_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1463_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1464
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1464_DATA_W 32
+#define RFC_ULLRAM_BANK1464_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1464_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1465
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1465_DATA_W 32
+#define RFC_ULLRAM_BANK1465_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1465_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1466
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1466_DATA_W 32
+#define RFC_ULLRAM_BANK1466_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1466_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1467
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1467_DATA_W 32
+#define RFC_ULLRAM_BANK1467_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1467_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1468
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1468_DATA_W 32
+#define RFC_ULLRAM_BANK1468_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1468_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1469
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1469_DATA_W 32
+#define RFC_ULLRAM_BANK1469_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1469_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1470
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1470_DATA_W 32
+#define RFC_ULLRAM_BANK1470_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1470_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1471
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1471_DATA_W 32
+#define RFC_ULLRAM_BANK1471_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1471_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1472
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1472_DATA_W 32
+#define RFC_ULLRAM_BANK1472_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1472_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1473
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1473_DATA_W 32
+#define RFC_ULLRAM_BANK1473_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1473_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1474
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1474_DATA_W 32
+#define RFC_ULLRAM_BANK1474_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1474_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1475
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1475_DATA_W 32
+#define RFC_ULLRAM_BANK1475_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1475_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1476
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1476_DATA_W 32
+#define RFC_ULLRAM_BANK1476_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1476_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1477
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1477_DATA_W 32
+#define RFC_ULLRAM_BANK1477_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1477_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1478
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1478_DATA_W 32
+#define RFC_ULLRAM_BANK1478_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1478_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1479
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1479_DATA_W 32
+#define RFC_ULLRAM_BANK1479_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1479_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1480
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1480_DATA_W 32
+#define RFC_ULLRAM_BANK1480_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1480_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1481
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1481_DATA_W 32
+#define RFC_ULLRAM_BANK1481_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1481_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1482
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1482_DATA_W 32
+#define RFC_ULLRAM_BANK1482_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1482_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1483
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1483_DATA_W 32
+#define RFC_ULLRAM_BANK1483_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1483_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1484
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1484_DATA_W 32
+#define RFC_ULLRAM_BANK1484_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1484_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1485
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1485_DATA_W 32
+#define RFC_ULLRAM_BANK1485_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1485_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1486
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1486_DATA_W 32
+#define RFC_ULLRAM_BANK1486_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1486_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1487
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1487_DATA_W 32
+#define RFC_ULLRAM_BANK1487_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1487_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1488
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1488_DATA_W 32
+#define RFC_ULLRAM_BANK1488_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1488_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1489
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1489_DATA_W 32
+#define RFC_ULLRAM_BANK1489_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1489_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1490
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1490_DATA_W 32
+#define RFC_ULLRAM_BANK1490_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1490_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1491
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1491_DATA_W 32
+#define RFC_ULLRAM_BANK1491_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1491_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1492
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1492_DATA_W 32
+#define RFC_ULLRAM_BANK1492_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1492_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1493
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1493_DATA_W 32
+#define RFC_ULLRAM_BANK1493_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1493_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1494
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1494_DATA_W 32
+#define RFC_ULLRAM_BANK1494_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1494_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1495
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1495_DATA_W 32
+#define RFC_ULLRAM_BANK1495_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1495_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1496
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1496_DATA_W 32
+#define RFC_ULLRAM_BANK1496_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1496_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1497
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1497_DATA_W 32
+#define RFC_ULLRAM_BANK1497_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1497_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1498
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1498_DATA_W 32
+#define RFC_ULLRAM_BANK1498_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1498_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1499
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1499_DATA_W 32
+#define RFC_ULLRAM_BANK1499_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1499_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1500
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1500_DATA_W 32
+#define RFC_ULLRAM_BANK1500_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1500_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1501
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1501_DATA_W 32
+#define RFC_ULLRAM_BANK1501_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1501_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1502
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1502_DATA_W 32
+#define RFC_ULLRAM_BANK1502_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1502_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1503
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1503_DATA_W 32
+#define RFC_ULLRAM_BANK1503_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1503_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1504
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1504_DATA_W 32
+#define RFC_ULLRAM_BANK1504_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1504_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1505
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1505_DATA_W 32
+#define RFC_ULLRAM_BANK1505_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1505_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1506
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1506_DATA_W 32
+#define RFC_ULLRAM_BANK1506_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1506_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1507
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1507_DATA_W 32
+#define RFC_ULLRAM_BANK1507_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1507_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1508
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1508_DATA_W 32
+#define RFC_ULLRAM_BANK1508_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1508_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1509
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1509_DATA_W 32
+#define RFC_ULLRAM_BANK1509_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1509_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1510
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1510_DATA_W 32
+#define RFC_ULLRAM_BANK1510_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1510_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1511
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1511_DATA_W 32
+#define RFC_ULLRAM_BANK1511_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1511_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1512
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1512_DATA_W 32
+#define RFC_ULLRAM_BANK1512_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1512_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1513
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1513_DATA_W 32
+#define RFC_ULLRAM_BANK1513_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1513_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1514
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1514_DATA_W 32
+#define RFC_ULLRAM_BANK1514_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1514_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1515
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1515_DATA_W 32
+#define RFC_ULLRAM_BANK1515_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1515_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1516
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1516_DATA_W 32
+#define RFC_ULLRAM_BANK1516_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1516_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1517
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1517_DATA_W 32
+#define RFC_ULLRAM_BANK1517_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1517_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1518
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1518_DATA_W 32
+#define RFC_ULLRAM_BANK1518_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1518_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1519
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1519_DATA_W 32
+#define RFC_ULLRAM_BANK1519_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1519_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1520
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1520_DATA_W 32
+#define RFC_ULLRAM_BANK1520_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1520_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1521
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1521_DATA_W 32
+#define RFC_ULLRAM_BANK1521_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1521_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1522
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1522_DATA_W 32
+#define RFC_ULLRAM_BANK1522_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1522_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1523
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1523_DATA_W 32
+#define RFC_ULLRAM_BANK1523_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1523_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1524
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1524_DATA_W 32
+#define RFC_ULLRAM_BANK1524_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1524_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1525
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1525_DATA_W 32
+#define RFC_ULLRAM_BANK1525_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1525_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1526
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1526_DATA_W 32
+#define RFC_ULLRAM_BANK1526_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1526_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1527
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1527_DATA_W 32
+#define RFC_ULLRAM_BANK1527_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1527_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1528
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1528_DATA_W 32
+#define RFC_ULLRAM_BANK1528_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1528_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1529
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1529_DATA_W 32
+#define RFC_ULLRAM_BANK1529_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1529_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1530
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1530_DATA_W 32
+#define RFC_ULLRAM_BANK1530_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1530_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1531
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1531_DATA_W 32
+#define RFC_ULLRAM_BANK1531_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1531_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1532
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1532_DATA_W 32
+#define RFC_ULLRAM_BANK1532_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1532_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1533
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1533_DATA_W 32
+#define RFC_ULLRAM_BANK1533_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1533_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1534
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1534_DATA_W 32
+#define RFC_ULLRAM_BANK1534_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1534_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1535
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1535_DATA_W 32
+#define RFC_ULLRAM_BANK1535_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1535_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1536
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1536_DATA_W 32
+#define RFC_ULLRAM_BANK1536_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1536_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1537
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1537_DATA_W 32
+#define RFC_ULLRAM_BANK1537_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1537_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1538
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1538_DATA_W 32
+#define RFC_ULLRAM_BANK1538_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1538_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1539
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1539_DATA_W 32
+#define RFC_ULLRAM_BANK1539_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1539_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1540
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1540_DATA_W 32
+#define RFC_ULLRAM_BANK1540_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1540_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1541
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1541_DATA_W 32
+#define RFC_ULLRAM_BANK1541_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1541_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1542
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1542_DATA_W 32
+#define RFC_ULLRAM_BANK1542_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1542_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1543
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1543_DATA_W 32
+#define RFC_ULLRAM_BANK1543_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1543_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1544
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1544_DATA_W 32
+#define RFC_ULLRAM_BANK1544_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1544_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1545
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1545_DATA_W 32
+#define RFC_ULLRAM_BANK1545_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1545_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1546
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1546_DATA_W 32
+#define RFC_ULLRAM_BANK1546_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1546_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1547
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1547_DATA_W 32
+#define RFC_ULLRAM_BANK1547_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1547_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1548
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1548_DATA_W 32
+#define RFC_ULLRAM_BANK1548_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1548_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1549
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1549_DATA_W 32
+#define RFC_ULLRAM_BANK1549_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1549_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1550
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1550_DATA_W 32
+#define RFC_ULLRAM_BANK1550_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1550_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1551
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1551_DATA_W 32
+#define RFC_ULLRAM_BANK1551_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1551_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1552
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1552_DATA_W 32
+#define RFC_ULLRAM_BANK1552_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1552_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1553
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1553_DATA_W 32
+#define RFC_ULLRAM_BANK1553_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1553_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1554
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1554_DATA_W 32
+#define RFC_ULLRAM_BANK1554_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1554_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1555
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1555_DATA_W 32
+#define RFC_ULLRAM_BANK1555_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1555_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1556
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1556_DATA_W 32
+#define RFC_ULLRAM_BANK1556_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1556_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1557
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1557_DATA_W 32
+#define RFC_ULLRAM_BANK1557_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1557_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1558
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1558_DATA_W 32
+#define RFC_ULLRAM_BANK1558_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1558_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1559
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1559_DATA_W 32
+#define RFC_ULLRAM_BANK1559_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1559_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1560
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1560_DATA_W 32
+#define RFC_ULLRAM_BANK1560_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1560_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1561
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1561_DATA_W 32
+#define RFC_ULLRAM_BANK1561_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1561_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1562
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1562_DATA_W 32
+#define RFC_ULLRAM_BANK1562_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1562_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1563
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1563_DATA_W 32
+#define RFC_ULLRAM_BANK1563_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1563_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1564
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1564_DATA_W 32
+#define RFC_ULLRAM_BANK1564_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1564_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1565
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1565_DATA_W 32
+#define RFC_ULLRAM_BANK1565_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1565_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1566
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1566_DATA_W 32
+#define RFC_ULLRAM_BANK1566_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1566_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1567
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1567_DATA_W 32
+#define RFC_ULLRAM_BANK1567_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1567_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1568
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1568_DATA_W 32
+#define RFC_ULLRAM_BANK1568_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1568_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1569
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1569_DATA_W 32
+#define RFC_ULLRAM_BANK1569_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1569_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1570
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1570_DATA_W 32
+#define RFC_ULLRAM_BANK1570_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1570_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1571
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1571_DATA_W 32
+#define RFC_ULLRAM_BANK1571_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1571_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1572
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1572_DATA_W 32
+#define RFC_ULLRAM_BANK1572_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1572_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1573
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1573_DATA_W 32
+#define RFC_ULLRAM_BANK1573_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1573_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1574
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1574_DATA_W 32
+#define RFC_ULLRAM_BANK1574_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1574_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1575
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1575_DATA_W 32
+#define RFC_ULLRAM_BANK1575_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1575_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1576
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1576_DATA_W 32
+#define RFC_ULLRAM_BANK1576_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1576_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1577
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1577_DATA_W 32
+#define RFC_ULLRAM_BANK1577_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1577_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1578
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1578_DATA_W 32
+#define RFC_ULLRAM_BANK1578_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1578_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1579
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1579_DATA_W 32
+#define RFC_ULLRAM_BANK1579_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1579_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1580
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1580_DATA_W 32
+#define RFC_ULLRAM_BANK1580_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1580_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1581
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1581_DATA_W 32
+#define RFC_ULLRAM_BANK1581_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1581_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1582
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1582_DATA_W 32
+#define RFC_ULLRAM_BANK1582_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1582_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1583
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1583_DATA_W 32
+#define RFC_ULLRAM_BANK1583_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1583_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1584
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1584_DATA_W 32
+#define RFC_ULLRAM_BANK1584_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1584_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1585
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1585_DATA_W 32
+#define RFC_ULLRAM_BANK1585_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1585_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1586
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1586_DATA_W 32
+#define RFC_ULLRAM_BANK1586_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1586_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1587
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1587_DATA_W 32
+#define RFC_ULLRAM_BANK1587_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1587_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1588
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1588_DATA_W 32
+#define RFC_ULLRAM_BANK1588_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1588_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1589
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1589_DATA_W 32
+#define RFC_ULLRAM_BANK1589_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1589_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1590
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1590_DATA_W 32
+#define RFC_ULLRAM_BANK1590_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1590_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1591
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1591_DATA_W 32
+#define RFC_ULLRAM_BANK1591_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1591_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1592
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1592_DATA_W 32
+#define RFC_ULLRAM_BANK1592_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1592_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1593
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1593_DATA_W 32
+#define RFC_ULLRAM_BANK1593_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1593_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1594
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1594_DATA_W 32
+#define RFC_ULLRAM_BANK1594_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1594_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1595
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1595_DATA_W 32
+#define RFC_ULLRAM_BANK1595_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1595_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1596
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1596_DATA_W 32
+#define RFC_ULLRAM_BANK1596_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1596_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1597
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1597_DATA_W 32
+#define RFC_ULLRAM_BANK1597_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1597_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1598
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1598_DATA_W 32
+#define RFC_ULLRAM_BANK1598_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1598_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1599
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1599_DATA_W 32
+#define RFC_ULLRAM_BANK1599_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1599_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1600
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1600_DATA_W 32
+#define RFC_ULLRAM_BANK1600_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1600_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1601
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1601_DATA_W 32
+#define RFC_ULLRAM_BANK1601_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1601_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1602
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1602_DATA_W 32
+#define RFC_ULLRAM_BANK1602_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1602_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1603
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1603_DATA_W 32
+#define RFC_ULLRAM_BANK1603_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1603_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1604
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1604_DATA_W 32
+#define RFC_ULLRAM_BANK1604_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1604_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1605
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1605_DATA_W 32
+#define RFC_ULLRAM_BANK1605_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1605_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1606
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1606_DATA_W 32
+#define RFC_ULLRAM_BANK1606_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1606_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1607
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1607_DATA_W 32
+#define RFC_ULLRAM_BANK1607_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1607_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1608
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1608_DATA_W 32
+#define RFC_ULLRAM_BANK1608_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1608_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1609
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1609_DATA_W 32
+#define RFC_ULLRAM_BANK1609_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1609_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1610
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1610_DATA_W 32
+#define RFC_ULLRAM_BANK1610_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1610_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1611
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1611_DATA_W 32
+#define RFC_ULLRAM_BANK1611_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1611_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1612
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1612_DATA_W 32
+#define RFC_ULLRAM_BANK1612_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1612_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1613
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1613_DATA_W 32
+#define RFC_ULLRAM_BANK1613_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1613_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1614
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1614_DATA_W 32
+#define RFC_ULLRAM_BANK1614_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1614_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1615
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1615_DATA_W 32
+#define RFC_ULLRAM_BANK1615_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1615_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1616
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1616_DATA_W 32
+#define RFC_ULLRAM_BANK1616_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1616_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1617
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1617_DATA_W 32
+#define RFC_ULLRAM_BANK1617_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1617_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1618
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1618_DATA_W 32
+#define RFC_ULLRAM_BANK1618_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1618_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1619
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1619_DATA_W 32
+#define RFC_ULLRAM_BANK1619_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1619_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1620
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1620_DATA_W 32
+#define RFC_ULLRAM_BANK1620_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1620_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1621
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1621_DATA_W 32
+#define RFC_ULLRAM_BANK1621_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1621_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1622
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1622_DATA_W 32
+#define RFC_ULLRAM_BANK1622_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1622_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1623
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1623_DATA_W 32
+#define RFC_ULLRAM_BANK1623_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1623_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1624
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1624_DATA_W 32
+#define RFC_ULLRAM_BANK1624_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1624_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1625
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1625_DATA_W 32
+#define RFC_ULLRAM_BANK1625_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1625_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1626
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1626_DATA_W 32
+#define RFC_ULLRAM_BANK1626_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1626_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1627
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1627_DATA_W 32
+#define RFC_ULLRAM_BANK1627_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1627_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1628
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1628_DATA_W 32
+#define RFC_ULLRAM_BANK1628_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1628_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1629
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1629_DATA_W 32
+#define RFC_ULLRAM_BANK1629_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1629_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1630
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1630_DATA_W 32
+#define RFC_ULLRAM_BANK1630_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1630_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1631
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1631_DATA_W 32
+#define RFC_ULLRAM_BANK1631_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1631_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1632
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1632_DATA_W 32
+#define RFC_ULLRAM_BANK1632_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1632_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1633
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1633_DATA_W 32
+#define RFC_ULLRAM_BANK1633_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1633_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1634
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1634_DATA_W 32
+#define RFC_ULLRAM_BANK1634_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1634_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1635
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1635_DATA_W 32
+#define RFC_ULLRAM_BANK1635_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1635_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1636
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1636_DATA_W 32
+#define RFC_ULLRAM_BANK1636_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1636_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1637
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1637_DATA_W 32
+#define RFC_ULLRAM_BANK1637_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1637_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1638
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1638_DATA_W 32
+#define RFC_ULLRAM_BANK1638_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1638_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1639
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1639_DATA_W 32
+#define RFC_ULLRAM_BANK1639_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1639_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1640
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1640_DATA_W 32
+#define RFC_ULLRAM_BANK1640_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1640_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1641
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1641_DATA_W 32
+#define RFC_ULLRAM_BANK1641_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1641_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1642
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1642_DATA_W 32
+#define RFC_ULLRAM_BANK1642_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1642_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1643
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1643_DATA_W 32
+#define RFC_ULLRAM_BANK1643_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1643_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1644
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1644_DATA_W 32
+#define RFC_ULLRAM_BANK1644_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1644_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1645
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1645_DATA_W 32
+#define RFC_ULLRAM_BANK1645_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1645_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1646
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1646_DATA_W 32
+#define RFC_ULLRAM_BANK1646_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1646_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1647
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1647_DATA_W 32
+#define RFC_ULLRAM_BANK1647_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1647_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1648
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1648_DATA_W 32
+#define RFC_ULLRAM_BANK1648_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1648_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1649
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1649_DATA_W 32
+#define RFC_ULLRAM_BANK1649_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1649_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1650
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1650_DATA_W 32
+#define RFC_ULLRAM_BANK1650_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1650_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1651
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1651_DATA_W 32
+#define RFC_ULLRAM_BANK1651_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1651_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1652
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1652_DATA_W 32
+#define RFC_ULLRAM_BANK1652_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1652_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1653
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1653_DATA_W 32
+#define RFC_ULLRAM_BANK1653_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1653_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1654
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1654_DATA_W 32
+#define RFC_ULLRAM_BANK1654_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1654_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1655
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1655_DATA_W 32
+#define RFC_ULLRAM_BANK1655_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1655_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1656
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1656_DATA_W 32
+#define RFC_ULLRAM_BANK1656_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1656_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1657
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1657_DATA_W 32
+#define RFC_ULLRAM_BANK1657_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1657_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1658
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1658_DATA_W 32
+#define RFC_ULLRAM_BANK1658_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1658_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1659
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1659_DATA_W 32
+#define RFC_ULLRAM_BANK1659_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1659_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1660
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1660_DATA_W 32
+#define RFC_ULLRAM_BANK1660_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1660_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1661
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1661_DATA_W 32
+#define RFC_ULLRAM_BANK1661_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1661_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1662
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1662_DATA_W 32
+#define RFC_ULLRAM_BANK1662_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1662_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1663
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1663_DATA_W 32
+#define RFC_ULLRAM_BANK1663_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1663_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1664
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1664_DATA_W 32
+#define RFC_ULLRAM_BANK1664_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1664_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1665
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1665_DATA_W 32
+#define RFC_ULLRAM_BANK1665_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1665_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1666
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1666_DATA_W 32
+#define RFC_ULLRAM_BANK1666_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1666_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1667
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1667_DATA_W 32
+#define RFC_ULLRAM_BANK1667_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1667_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1668
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1668_DATA_W 32
+#define RFC_ULLRAM_BANK1668_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1668_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1669
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1669_DATA_W 32
+#define RFC_ULLRAM_BANK1669_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1669_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1670
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1670_DATA_W 32
+#define RFC_ULLRAM_BANK1670_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1670_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1671
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1671_DATA_W 32
+#define RFC_ULLRAM_BANK1671_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1671_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1672
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1672_DATA_W 32
+#define RFC_ULLRAM_BANK1672_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1672_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1673
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1673_DATA_W 32
+#define RFC_ULLRAM_BANK1673_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1673_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1674
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1674_DATA_W 32
+#define RFC_ULLRAM_BANK1674_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1674_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1675
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1675_DATA_W 32
+#define RFC_ULLRAM_BANK1675_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1675_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1676
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1676_DATA_W 32
+#define RFC_ULLRAM_BANK1676_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1676_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1677
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1677_DATA_W 32
+#define RFC_ULLRAM_BANK1677_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1677_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1678
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1678_DATA_W 32
+#define RFC_ULLRAM_BANK1678_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1678_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1679
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1679_DATA_W 32
+#define RFC_ULLRAM_BANK1679_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1679_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1680
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1680_DATA_W 32
+#define RFC_ULLRAM_BANK1680_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1680_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1681
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1681_DATA_W 32
+#define RFC_ULLRAM_BANK1681_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1681_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1682
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1682_DATA_W 32
+#define RFC_ULLRAM_BANK1682_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1682_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1683
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1683_DATA_W 32
+#define RFC_ULLRAM_BANK1683_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1683_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1684
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1684_DATA_W 32
+#define RFC_ULLRAM_BANK1684_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1684_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1685
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1685_DATA_W 32
+#define RFC_ULLRAM_BANK1685_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1685_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1686
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1686_DATA_W 32
+#define RFC_ULLRAM_BANK1686_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1686_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1687
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1687_DATA_W 32
+#define RFC_ULLRAM_BANK1687_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1687_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1688
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1688_DATA_W 32
+#define RFC_ULLRAM_BANK1688_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1688_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1689
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1689_DATA_W 32
+#define RFC_ULLRAM_BANK1689_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1689_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1690
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1690_DATA_W 32
+#define RFC_ULLRAM_BANK1690_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1690_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1691
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1691_DATA_W 32
+#define RFC_ULLRAM_BANK1691_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1691_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1692
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1692_DATA_W 32
+#define RFC_ULLRAM_BANK1692_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1692_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1693
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1693_DATA_W 32
+#define RFC_ULLRAM_BANK1693_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1693_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1694
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1694_DATA_W 32
+#define RFC_ULLRAM_BANK1694_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1694_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1695
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1695_DATA_W 32
+#define RFC_ULLRAM_BANK1695_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1695_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1696
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1696_DATA_W 32
+#define RFC_ULLRAM_BANK1696_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1696_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1697
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1697_DATA_W 32
+#define RFC_ULLRAM_BANK1697_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1697_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1698
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1698_DATA_W 32
+#define RFC_ULLRAM_BANK1698_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1698_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1699
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1699_DATA_W 32
+#define RFC_ULLRAM_BANK1699_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1699_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1700
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1700_DATA_W 32
+#define RFC_ULLRAM_BANK1700_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1700_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1701
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1701_DATA_W 32
+#define RFC_ULLRAM_BANK1701_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1701_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1702
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1702_DATA_W 32
+#define RFC_ULLRAM_BANK1702_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1702_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1703
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1703_DATA_W 32
+#define RFC_ULLRAM_BANK1703_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1703_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1704
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1704_DATA_W 32
+#define RFC_ULLRAM_BANK1704_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1704_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1705
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1705_DATA_W 32
+#define RFC_ULLRAM_BANK1705_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1705_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1706
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1706_DATA_W 32
+#define RFC_ULLRAM_BANK1706_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1706_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1707
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1707_DATA_W 32
+#define RFC_ULLRAM_BANK1707_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1707_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1708
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1708_DATA_W 32
+#define RFC_ULLRAM_BANK1708_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1708_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1709
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1709_DATA_W 32
+#define RFC_ULLRAM_BANK1709_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1709_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1710
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1710_DATA_W 32
+#define RFC_ULLRAM_BANK1710_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1710_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1711
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1711_DATA_W 32
+#define RFC_ULLRAM_BANK1711_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1711_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1712
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1712_DATA_W 32
+#define RFC_ULLRAM_BANK1712_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1712_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1713
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1713_DATA_W 32
+#define RFC_ULLRAM_BANK1713_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1713_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1714
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1714_DATA_W 32
+#define RFC_ULLRAM_BANK1714_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1714_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1715
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1715_DATA_W 32
+#define RFC_ULLRAM_BANK1715_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1715_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1716
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1716_DATA_W 32
+#define RFC_ULLRAM_BANK1716_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1716_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1717
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1717_DATA_W 32
+#define RFC_ULLRAM_BANK1717_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1717_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1718
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1718_DATA_W 32
+#define RFC_ULLRAM_BANK1718_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1718_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1719
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1719_DATA_W 32
+#define RFC_ULLRAM_BANK1719_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1719_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1720
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1720_DATA_W 32
+#define RFC_ULLRAM_BANK1720_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1720_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1721
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1721_DATA_W 32
+#define RFC_ULLRAM_BANK1721_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1721_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1722
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1722_DATA_W 32
+#define RFC_ULLRAM_BANK1722_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1722_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1723
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1723_DATA_W 32
+#define RFC_ULLRAM_BANK1723_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1723_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1724
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1724_DATA_W 32
+#define RFC_ULLRAM_BANK1724_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1724_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1725
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1725_DATA_W 32
+#define RFC_ULLRAM_BANK1725_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1725_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1726
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1726_DATA_W 32
+#define RFC_ULLRAM_BANK1726_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1726_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1727
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1727_DATA_W 32
+#define RFC_ULLRAM_BANK1727_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1727_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1728
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1728_DATA_W 32
+#define RFC_ULLRAM_BANK1728_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1728_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1729
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1729_DATA_W 32
+#define RFC_ULLRAM_BANK1729_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1729_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1730
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1730_DATA_W 32
+#define RFC_ULLRAM_BANK1730_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1730_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1731
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1731_DATA_W 32
+#define RFC_ULLRAM_BANK1731_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1731_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1732
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1732_DATA_W 32
+#define RFC_ULLRAM_BANK1732_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1732_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1733
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1733_DATA_W 32
+#define RFC_ULLRAM_BANK1733_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1733_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1734
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1734_DATA_W 32
+#define RFC_ULLRAM_BANK1734_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1734_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1735
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1735_DATA_W 32
+#define RFC_ULLRAM_BANK1735_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1735_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1736
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1736_DATA_W 32
+#define RFC_ULLRAM_BANK1736_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1736_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1737
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1737_DATA_W 32
+#define RFC_ULLRAM_BANK1737_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1737_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1738
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1738_DATA_W 32
+#define RFC_ULLRAM_BANK1738_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1738_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1739
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1739_DATA_W 32
+#define RFC_ULLRAM_BANK1739_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1739_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1740
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1740_DATA_W 32
+#define RFC_ULLRAM_BANK1740_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1740_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1741
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1741_DATA_W 32
+#define RFC_ULLRAM_BANK1741_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1741_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1742
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1742_DATA_W 32
+#define RFC_ULLRAM_BANK1742_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1742_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1743
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1743_DATA_W 32
+#define RFC_ULLRAM_BANK1743_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1743_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1744
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1744_DATA_W 32
+#define RFC_ULLRAM_BANK1744_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1744_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1745
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1745_DATA_W 32
+#define RFC_ULLRAM_BANK1745_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1745_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1746
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1746_DATA_W 32
+#define RFC_ULLRAM_BANK1746_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1746_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1747
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1747_DATA_W 32
+#define RFC_ULLRAM_BANK1747_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1747_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1748
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1748_DATA_W 32
+#define RFC_ULLRAM_BANK1748_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1748_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1749
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1749_DATA_W 32
+#define RFC_ULLRAM_BANK1749_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1749_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1750
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1750_DATA_W 32
+#define RFC_ULLRAM_BANK1750_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1750_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1751
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1751_DATA_W 32
+#define RFC_ULLRAM_BANK1751_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1751_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1752
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1752_DATA_W 32
+#define RFC_ULLRAM_BANK1752_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1752_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1753
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1753_DATA_W 32
+#define RFC_ULLRAM_BANK1753_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1753_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1754
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1754_DATA_W 32
+#define RFC_ULLRAM_BANK1754_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1754_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1755
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1755_DATA_W 32
+#define RFC_ULLRAM_BANK1755_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1755_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1756
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1756_DATA_W 32
+#define RFC_ULLRAM_BANK1756_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1756_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1757
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1757_DATA_W 32
+#define RFC_ULLRAM_BANK1757_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1757_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1758
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1758_DATA_W 32
+#define RFC_ULLRAM_BANK1758_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1758_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1759
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1759_DATA_W 32
+#define RFC_ULLRAM_BANK1759_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1759_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1760
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1760_DATA_W 32
+#define RFC_ULLRAM_BANK1760_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1760_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1761
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1761_DATA_W 32
+#define RFC_ULLRAM_BANK1761_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1761_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1762
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1762_DATA_W 32
+#define RFC_ULLRAM_BANK1762_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1762_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1763
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1763_DATA_W 32
+#define RFC_ULLRAM_BANK1763_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1763_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1764
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1764_DATA_W 32
+#define RFC_ULLRAM_BANK1764_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1764_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1765
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1765_DATA_W 32
+#define RFC_ULLRAM_BANK1765_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1765_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1766
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1766_DATA_W 32
+#define RFC_ULLRAM_BANK1766_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1766_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1767
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1767_DATA_W 32
+#define RFC_ULLRAM_BANK1767_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1767_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1768
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1768_DATA_W 32
+#define RFC_ULLRAM_BANK1768_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1768_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1769
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1769_DATA_W 32
+#define RFC_ULLRAM_BANK1769_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1769_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1770
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1770_DATA_W 32
+#define RFC_ULLRAM_BANK1770_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1770_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1771
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1771_DATA_W 32
+#define RFC_ULLRAM_BANK1771_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1771_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1772
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1772_DATA_W 32
+#define RFC_ULLRAM_BANK1772_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1772_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1773
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1773_DATA_W 32
+#define RFC_ULLRAM_BANK1773_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1773_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1774
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1774_DATA_W 32
+#define RFC_ULLRAM_BANK1774_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1774_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1775
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1775_DATA_W 32
+#define RFC_ULLRAM_BANK1775_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1775_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1776
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1776_DATA_W 32
+#define RFC_ULLRAM_BANK1776_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1776_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1777
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1777_DATA_W 32
+#define RFC_ULLRAM_BANK1777_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1777_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1778
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1778_DATA_W 32
+#define RFC_ULLRAM_BANK1778_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1778_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1779
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1779_DATA_W 32
+#define RFC_ULLRAM_BANK1779_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1779_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1780
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1780_DATA_W 32
+#define RFC_ULLRAM_BANK1780_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1780_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1781
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1781_DATA_W 32
+#define RFC_ULLRAM_BANK1781_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1781_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1782
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1782_DATA_W 32
+#define RFC_ULLRAM_BANK1782_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1782_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1783
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1783_DATA_W 32
+#define RFC_ULLRAM_BANK1783_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1783_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1784
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1784_DATA_W 32
+#define RFC_ULLRAM_BANK1784_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1784_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1785
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1785_DATA_W 32
+#define RFC_ULLRAM_BANK1785_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1785_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1786
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1786_DATA_W 32
+#define RFC_ULLRAM_BANK1786_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1786_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1787
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1787_DATA_W 32
+#define RFC_ULLRAM_BANK1787_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1787_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1788
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1788_DATA_W 32
+#define RFC_ULLRAM_BANK1788_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1788_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1789
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1789_DATA_W 32
+#define RFC_ULLRAM_BANK1789_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1789_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1790
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1790_DATA_W 32
+#define RFC_ULLRAM_BANK1790_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1790_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1791
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1791_DATA_W 32
+#define RFC_ULLRAM_BANK1791_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1791_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1792
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1792_DATA_W 32
+#define RFC_ULLRAM_BANK1792_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1792_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1793
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1793_DATA_W 32
+#define RFC_ULLRAM_BANK1793_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1793_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1794
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1794_DATA_W 32
+#define RFC_ULLRAM_BANK1794_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1794_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1795
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1795_DATA_W 32
+#define RFC_ULLRAM_BANK1795_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1795_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1796
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1796_DATA_W 32
+#define RFC_ULLRAM_BANK1796_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1796_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1797
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1797_DATA_W 32
+#define RFC_ULLRAM_BANK1797_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1797_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1798
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1798_DATA_W 32
+#define RFC_ULLRAM_BANK1798_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1798_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1799
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1799_DATA_W 32
+#define RFC_ULLRAM_BANK1799_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1799_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1800
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1800_DATA_W 32
+#define RFC_ULLRAM_BANK1800_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1800_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1801
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1801_DATA_W 32
+#define RFC_ULLRAM_BANK1801_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1801_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1802
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1802_DATA_W 32
+#define RFC_ULLRAM_BANK1802_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1802_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1803
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1803_DATA_W 32
+#define RFC_ULLRAM_BANK1803_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1803_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1804
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1804_DATA_W 32
+#define RFC_ULLRAM_BANK1804_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1804_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1805
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1805_DATA_W 32
+#define RFC_ULLRAM_BANK1805_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1805_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1806
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1806_DATA_W 32
+#define RFC_ULLRAM_BANK1806_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1806_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1807
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1807_DATA_W 32
+#define RFC_ULLRAM_BANK1807_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1807_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1808
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1808_DATA_W 32
+#define RFC_ULLRAM_BANK1808_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1808_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1809
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1809_DATA_W 32
+#define RFC_ULLRAM_BANK1809_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1809_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1810
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1810_DATA_W 32
+#define RFC_ULLRAM_BANK1810_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1810_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1811
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1811_DATA_W 32
+#define RFC_ULLRAM_BANK1811_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1811_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1812
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1812_DATA_W 32
+#define RFC_ULLRAM_BANK1812_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1812_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1813
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1813_DATA_W 32
+#define RFC_ULLRAM_BANK1813_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1813_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1814
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1814_DATA_W 32
+#define RFC_ULLRAM_BANK1814_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1814_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1815
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1815_DATA_W 32
+#define RFC_ULLRAM_BANK1815_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1815_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1816
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1816_DATA_W 32
+#define RFC_ULLRAM_BANK1816_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1816_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1817
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1817_DATA_W 32
+#define RFC_ULLRAM_BANK1817_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1817_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1818
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1818_DATA_W 32
+#define RFC_ULLRAM_BANK1818_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1818_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1819
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1819_DATA_W 32
+#define RFC_ULLRAM_BANK1819_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1819_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1820
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1820_DATA_W 32
+#define RFC_ULLRAM_BANK1820_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1820_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1821
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1821_DATA_W 32
+#define RFC_ULLRAM_BANK1821_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1821_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1822
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1822_DATA_W 32
+#define RFC_ULLRAM_BANK1822_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1822_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1823
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1823_DATA_W 32
+#define RFC_ULLRAM_BANK1823_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1823_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1824
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1824_DATA_W 32
+#define RFC_ULLRAM_BANK1824_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1824_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1825
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1825_DATA_W 32
+#define RFC_ULLRAM_BANK1825_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1825_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1826
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1826_DATA_W 32
+#define RFC_ULLRAM_BANK1826_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1826_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1827
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1827_DATA_W 32
+#define RFC_ULLRAM_BANK1827_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1827_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1828
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1828_DATA_W 32
+#define RFC_ULLRAM_BANK1828_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1828_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1829
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1829_DATA_W 32
+#define RFC_ULLRAM_BANK1829_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1829_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1830
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1830_DATA_W 32
+#define RFC_ULLRAM_BANK1830_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1830_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1831
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1831_DATA_W 32
+#define RFC_ULLRAM_BANK1831_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1831_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1832
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1832_DATA_W 32
+#define RFC_ULLRAM_BANK1832_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1832_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1833
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1833_DATA_W 32
+#define RFC_ULLRAM_BANK1833_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1833_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1834
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1834_DATA_W 32
+#define RFC_ULLRAM_BANK1834_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1834_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1835
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1835_DATA_W 32
+#define RFC_ULLRAM_BANK1835_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1835_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1836
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1836_DATA_W 32
+#define RFC_ULLRAM_BANK1836_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1836_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1837
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1837_DATA_W 32
+#define RFC_ULLRAM_BANK1837_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1837_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1838
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1838_DATA_W 32
+#define RFC_ULLRAM_BANK1838_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1838_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1839
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1839_DATA_W 32
+#define RFC_ULLRAM_BANK1839_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1839_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1840
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1840_DATA_W 32
+#define RFC_ULLRAM_BANK1840_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1840_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1841
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1841_DATA_W 32
+#define RFC_ULLRAM_BANK1841_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1841_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1842
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1842_DATA_W 32
+#define RFC_ULLRAM_BANK1842_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1842_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1843
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1843_DATA_W 32
+#define RFC_ULLRAM_BANK1843_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1843_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1844
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1844_DATA_W 32
+#define RFC_ULLRAM_BANK1844_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1844_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1845
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1845_DATA_W 32
+#define RFC_ULLRAM_BANK1845_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1845_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1846
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1846_DATA_W 32
+#define RFC_ULLRAM_BANK1846_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1846_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1847
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1847_DATA_W 32
+#define RFC_ULLRAM_BANK1847_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1847_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1848
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1848_DATA_W 32
+#define RFC_ULLRAM_BANK1848_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1848_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1849
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1849_DATA_W 32
+#define RFC_ULLRAM_BANK1849_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1849_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1850
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1850_DATA_W 32
+#define RFC_ULLRAM_BANK1850_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1850_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1851
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1851_DATA_W 32
+#define RFC_ULLRAM_BANK1851_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1851_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1852
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1852_DATA_W 32
+#define RFC_ULLRAM_BANK1852_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1852_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1853
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1853_DATA_W 32
+#define RFC_ULLRAM_BANK1853_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1853_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1854
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1854_DATA_W 32
+#define RFC_ULLRAM_BANK1854_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1854_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1855
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1855_DATA_W 32
+#define RFC_ULLRAM_BANK1855_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1855_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1856
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1856_DATA_W 32
+#define RFC_ULLRAM_BANK1856_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1856_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1857
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1857_DATA_W 32
+#define RFC_ULLRAM_BANK1857_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1857_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1858
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1858_DATA_W 32
+#define RFC_ULLRAM_BANK1858_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1858_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1859
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1859_DATA_W 32
+#define RFC_ULLRAM_BANK1859_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1859_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1860
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1860_DATA_W 32
+#define RFC_ULLRAM_BANK1860_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1860_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1861
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1861_DATA_W 32
+#define RFC_ULLRAM_BANK1861_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1861_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1862
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1862_DATA_W 32
+#define RFC_ULLRAM_BANK1862_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1862_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1863
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1863_DATA_W 32
+#define RFC_ULLRAM_BANK1863_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1863_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1864
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1864_DATA_W 32
+#define RFC_ULLRAM_BANK1864_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1864_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1865
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1865_DATA_W 32
+#define RFC_ULLRAM_BANK1865_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1865_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1866
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1866_DATA_W 32
+#define RFC_ULLRAM_BANK1866_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1866_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1867
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1867_DATA_W 32
+#define RFC_ULLRAM_BANK1867_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1867_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1868
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1868_DATA_W 32
+#define RFC_ULLRAM_BANK1868_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1868_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1869
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1869_DATA_W 32
+#define RFC_ULLRAM_BANK1869_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1869_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1870
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1870_DATA_W 32
+#define RFC_ULLRAM_BANK1870_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1870_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1871
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1871_DATA_W 32
+#define RFC_ULLRAM_BANK1871_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1871_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1872
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1872_DATA_W 32
+#define RFC_ULLRAM_BANK1872_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1872_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1873
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1873_DATA_W 32
+#define RFC_ULLRAM_BANK1873_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1873_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1874
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1874_DATA_W 32
+#define RFC_ULLRAM_BANK1874_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1874_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1875
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1875_DATA_W 32
+#define RFC_ULLRAM_BANK1875_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1875_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1876
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1876_DATA_W 32
+#define RFC_ULLRAM_BANK1876_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1876_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1877
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1877_DATA_W 32
+#define RFC_ULLRAM_BANK1877_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1877_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1878
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1878_DATA_W 32
+#define RFC_ULLRAM_BANK1878_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1878_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1879
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1879_DATA_W 32
+#define RFC_ULLRAM_BANK1879_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1879_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1880
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1880_DATA_W 32
+#define RFC_ULLRAM_BANK1880_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1880_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1881
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1881_DATA_W 32
+#define RFC_ULLRAM_BANK1881_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1881_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1882
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1882_DATA_W 32
+#define RFC_ULLRAM_BANK1882_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1882_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1883
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1883_DATA_W 32
+#define RFC_ULLRAM_BANK1883_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1883_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1884
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1884_DATA_W 32
+#define RFC_ULLRAM_BANK1884_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1884_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1885
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1885_DATA_W 32
+#define RFC_ULLRAM_BANK1885_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1885_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1886
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1886_DATA_W 32
+#define RFC_ULLRAM_BANK1886_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1886_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1887
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1887_DATA_W 32
+#define RFC_ULLRAM_BANK1887_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1887_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1888
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1888_DATA_W 32
+#define RFC_ULLRAM_BANK1888_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1888_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1889
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1889_DATA_W 32
+#define RFC_ULLRAM_BANK1889_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1889_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1890
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1890_DATA_W 32
+#define RFC_ULLRAM_BANK1890_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1890_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1891
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1891_DATA_W 32
+#define RFC_ULLRAM_BANK1891_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1891_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1892
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1892_DATA_W 32
+#define RFC_ULLRAM_BANK1892_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1892_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1893
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1893_DATA_W 32
+#define RFC_ULLRAM_BANK1893_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1893_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1894
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1894_DATA_W 32
+#define RFC_ULLRAM_BANK1894_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1894_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1895
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1895_DATA_W 32
+#define RFC_ULLRAM_BANK1895_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1895_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1896
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1896_DATA_W 32
+#define RFC_ULLRAM_BANK1896_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1896_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1897
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1897_DATA_W 32
+#define RFC_ULLRAM_BANK1897_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1897_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1898
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1898_DATA_W 32
+#define RFC_ULLRAM_BANK1898_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1898_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1899
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1899_DATA_W 32
+#define RFC_ULLRAM_BANK1899_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1899_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1900
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1900_DATA_W 32
+#define RFC_ULLRAM_BANK1900_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1900_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1901
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1901_DATA_W 32
+#define RFC_ULLRAM_BANK1901_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1901_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1902
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1902_DATA_W 32
+#define RFC_ULLRAM_BANK1902_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1902_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1903
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1903_DATA_W 32
+#define RFC_ULLRAM_BANK1903_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1903_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1904
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1904_DATA_W 32
+#define RFC_ULLRAM_BANK1904_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1904_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1905
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1905_DATA_W 32
+#define RFC_ULLRAM_BANK1905_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1905_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1906
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1906_DATA_W 32
+#define RFC_ULLRAM_BANK1906_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1906_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1907
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1907_DATA_W 32
+#define RFC_ULLRAM_BANK1907_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1907_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1908
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1908_DATA_W 32
+#define RFC_ULLRAM_BANK1908_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1908_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1909
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1909_DATA_W 32
+#define RFC_ULLRAM_BANK1909_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1909_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1910
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1910_DATA_W 32
+#define RFC_ULLRAM_BANK1910_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1910_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1911
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1911_DATA_W 32
+#define RFC_ULLRAM_BANK1911_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1911_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1912
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1912_DATA_W 32
+#define RFC_ULLRAM_BANK1912_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1912_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1913
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1913_DATA_W 32
+#define RFC_ULLRAM_BANK1913_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1913_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1914
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1914_DATA_W 32
+#define RFC_ULLRAM_BANK1914_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1914_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1915
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1915_DATA_W 32
+#define RFC_ULLRAM_BANK1915_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1915_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1916
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1916_DATA_W 32
+#define RFC_ULLRAM_BANK1916_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1916_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1917
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1917_DATA_W 32
+#define RFC_ULLRAM_BANK1917_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1917_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1918
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1918_DATA_W 32
+#define RFC_ULLRAM_BANK1918_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1918_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1919
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1919_DATA_W 32
+#define RFC_ULLRAM_BANK1919_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1919_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1920
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1920_DATA_W 32
+#define RFC_ULLRAM_BANK1920_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1920_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1921
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1921_DATA_W 32
+#define RFC_ULLRAM_BANK1921_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1921_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1922
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1922_DATA_W 32
+#define RFC_ULLRAM_BANK1922_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1922_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1923
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1923_DATA_W 32
+#define RFC_ULLRAM_BANK1923_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1923_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1924
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1924_DATA_W 32
+#define RFC_ULLRAM_BANK1924_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1924_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1925
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1925_DATA_W 32
+#define RFC_ULLRAM_BANK1925_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1925_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1926
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1926_DATA_W 32
+#define RFC_ULLRAM_BANK1926_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1926_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1927
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1927_DATA_W 32
+#define RFC_ULLRAM_BANK1927_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1927_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1928
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1928_DATA_W 32
+#define RFC_ULLRAM_BANK1928_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1928_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1929
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1929_DATA_W 32
+#define RFC_ULLRAM_BANK1929_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1929_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1930
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1930_DATA_W 32
+#define RFC_ULLRAM_BANK1930_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1930_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1931
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1931_DATA_W 32
+#define RFC_ULLRAM_BANK1931_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1931_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1932
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1932_DATA_W 32
+#define RFC_ULLRAM_BANK1932_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1932_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1933
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1933_DATA_W 32
+#define RFC_ULLRAM_BANK1933_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1933_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1934
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1934_DATA_W 32
+#define RFC_ULLRAM_BANK1934_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1934_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1935
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1935_DATA_W 32
+#define RFC_ULLRAM_BANK1935_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1935_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1936
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1936_DATA_W 32
+#define RFC_ULLRAM_BANK1936_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1936_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1937
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1937_DATA_W 32
+#define RFC_ULLRAM_BANK1937_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1937_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1938
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1938_DATA_W 32
+#define RFC_ULLRAM_BANK1938_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1938_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1939
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1939_DATA_W 32
+#define RFC_ULLRAM_BANK1939_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1939_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1940
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1940_DATA_W 32
+#define RFC_ULLRAM_BANK1940_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1940_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1941
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1941_DATA_W 32
+#define RFC_ULLRAM_BANK1941_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1941_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1942
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1942_DATA_W 32
+#define RFC_ULLRAM_BANK1942_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1942_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1943
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1943_DATA_W 32
+#define RFC_ULLRAM_BANK1943_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1943_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1944
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1944_DATA_W 32
+#define RFC_ULLRAM_BANK1944_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1944_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1945
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1945_DATA_W 32
+#define RFC_ULLRAM_BANK1945_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1945_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1946
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1946_DATA_W 32
+#define RFC_ULLRAM_BANK1946_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1946_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1947
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1947_DATA_W 32
+#define RFC_ULLRAM_BANK1947_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1947_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1948
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1948_DATA_W 32
+#define RFC_ULLRAM_BANK1948_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1948_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1949
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1949_DATA_W 32
+#define RFC_ULLRAM_BANK1949_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1949_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1950
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1950_DATA_W 32
+#define RFC_ULLRAM_BANK1950_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1950_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1951
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1951_DATA_W 32
+#define RFC_ULLRAM_BANK1951_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1951_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1952
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1952_DATA_W 32
+#define RFC_ULLRAM_BANK1952_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1952_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1953
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1953_DATA_W 32
+#define RFC_ULLRAM_BANK1953_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1953_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1954
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1954_DATA_W 32
+#define RFC_ULLRAM_BANK1954_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1954_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1955
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1955_DATA_W 32
+#define RFC_ULLRAM_BANK1955_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1955_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1956
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1956_DATA_W 32
+#define RFC_ULLRAM_BANK1956_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1956_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1957
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1957_DATA_W 32
+#define RFC_ULLRAM_BANK1957_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1957_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1958
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1958_DATA_W 32
+#define RFC_ULLRAM_BANK1958_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1958_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1959
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1959_DATA_W 32
+#define RFC_ULLRAM_BANK1959_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1959_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1960
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1960_DATA_W 32
+#define RFC_ULLRAM_BANK1960_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1960_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1961
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1961_DATA_W 32
+#define RFC_ULLRAM_BANK1961_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1961_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1962
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1962_DATA_W 32
+#define RFC_ULLRAM_BANK1962_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1962_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1963
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1963_DATA_W 32
+#define RFC_ULLRAM_BANK1963_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1963_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1964
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1964_DATA_W 32
+#define RFC_ULLRAM_BANK1964_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1964_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1965
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1965_DATA_W 32
+#define RFC_ULLRAM_BANK1965_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1965_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1966
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1966_DATA_W 32
+#define RFC_ULLRAM_BANK1966_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1966_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1967
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1967_DATA_W 32
+#define RFC_ULLRAM_BANK1967_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1967_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1968
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1968_DATA_W 32
+#define RFC_ULLRAM_BANK1968_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1968_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1969
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1969_DATA_W 32
+#define RFC_ULLRAM_BANK1969_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1969_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1970
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1970_DATA_W 32
+#define RFC_ULLRAM_BANK1970_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1970_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1971
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1971_DATA_W 32
+#define RFC_ULLRAM_BANK1971_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1971_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1972
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1972_DATA_W 32
+#define RFC_ULLRAM_BANK1972_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1972_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1973
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1973_DATA_W 32
+#define RFC_ULLRAM_BANK1973_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1973_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1974
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1974_DATA_W 32
+#define RFC_ULLRAM_BANK1974_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1974_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1975
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1975_DATA_W 32
+#define RFC_ULLRAM_BANK1975_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1975_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1976
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1976_DATA_W 32
+#define RFC_ULLRAM_BANK1976_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1976_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1977
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1977_DATA_W 32
+#define RFC_ULLRAM_BANK1977_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1977_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1978
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1978_DATA_W 32
+#define RFC_ULLRAM_BANK1978_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1978_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1979
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1979_DATA_W 32
+#define RFC_ULLRAM_BANK1979_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1979_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1980
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1980_DATA_W 32
+#define RFC_ULLRAM_BANK1980_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1980_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1981
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1981_DATA_W 32
+#define RFC_ULLRAM_BANK1981_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1981_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1982
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1982_DATA_W 32
+#define RFC_ULLRAM_BANK1982_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1982_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1983
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1983_DATA_W 32
+#define RFC_ULLRAM_BANK1983_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1983_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1984
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1984_DATA_W 32
+#define RFC_ULLRAM_BANK1984_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1984_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1985
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1985_DATA_W 32
+#define RFC_ULLRAM_BANK1985_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1985_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1986
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1986_DATA_W 32
+#define RFC_ULLRAM_BANK1986_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1986_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1987
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1987_DATA_W 32
+#define RFC_ULLRAM_BANK1987_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1987_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1988
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1988_DATA_W 32
+#define RFC_ULLRAM_BANK1988_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1988_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1989
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1989_DATA_W 32
+#define RFC_ULLRAM_BANK1989_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1989_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1990
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1990_DATA_W 32
+#define RFC_ULLRAM_BANK1990_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1990_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1991
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1991_DATA_W 32
+#define RFC_ULLRAM_BANK1991_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1991_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1992
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1992_DATA_W 32
+#define RFC_ULLRAM_BANK1992_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1992_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1993
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1993_DATA_W 32
+#define RFC_ULLRAM_BANK1993_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1993_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1994
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1994_DATA_W 32
+#define RFC_ULLRAM_BANK1994_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1994_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1995
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1995_DATA_W 32
+#define RFC_ULLRAM_BANK1995_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1995_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1996
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1996_DATA_W 32
+#define RFC_ULLRAM_BANK1996_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1996_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1997
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1997_DATA_W 32
+#define RFC_ULLRAM_BANK1997_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1997_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1998
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1998_DATA_W 32
+#define RFC_ULLRAM_BANK1998_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1998_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK1999
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK1999_DATA_W 32
+#define RFC_ULLRAM_BANK1999_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK1999_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11000
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11000_DATA_W 32
+#define RFC_ULLRAM_BANK11000_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11000_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11001
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11001_DATA_W 32
+#define RFC_ULLRAM_BANK11001_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11001_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11002
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11002_DATA_W 32
+#define RFC_ULLRAM_BANK11002_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11002_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11003
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11003_DATA_W 32
+#define RFC_ULLRAM_BANK11003_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11003_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11004
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11004_DATA_W 32
+#define RFC_ULLRAM_BANK11004_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11004_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11005
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11005_DATA_W 32
+#define RFC_ULLRAM_BANK11005_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11005_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11006
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11006_DATA_W 32
+#define RFC_ULLRAM_BANK11006_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11006_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11007
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11007_DATA_W 32
+#define RFC_ULLRAM_BANK11007_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11007_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11008
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11008_DATA_W 32
+#define RFC_ULLRAM_BANK11008_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11008_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11009
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11009_DATA_W 32
+#define RFC_ULLRAM_BANK11009_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11009_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11010
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11010_DATA_W 32
+#define RFC_ULLRAM_BANK11010_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11010_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11011
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11011_DATA_W 32
+#define RFC_ULLRAM_BANK11011_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11011_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11012
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11012_DATA_W 32
+#define RFC_ULLRAM_BANK11012_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11012_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11013
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11013_DATA_W 32
+#define RFC_ULLRAM_BANK11013_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11013_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11014
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11014_DATA_W 32
+#define RFC_ULLRAM_BANK11014_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11014_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11015
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11015_DATA_W 32
+#define RFC_ULLRAM_BANK11015_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11015_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11016
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11016_DATA_W 32
+#define RFC_ULLRAM_BANK11016_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11016_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11017
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11017_DATA_W 32
+#define RFC_ULLRAM_BANK11017_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11017_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11018
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11018_DATA_W 32
+#define RFC_ULLRAM_BANK11018_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11018_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11019
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11019_DATA_W 32
+#define RFC_ULLRAM_BANK11019_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11019_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11020
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11020_DATA_W 32
+#define RFC_ULLRAM_BANK11020_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11020_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11021
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11021_DATA_W 32
+#define RFC_ULLRAM_BANK11021_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11021_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11022
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11022_DATA_W 32
+#define RFC_ULLRAM_BANK11022_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11022_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11023
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11023_DATA_W 32
+#define RFC_ULLRAM_BANK11023_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11023_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11024
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11024_DATA_W 32
+#define RFC_ULLRAM_BANK11024_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11024_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11025
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11025_DATA_W 32
+#define RFC_ULLRAM_BANK11025_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11025_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11026
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11026_DATA_W 32
+#define RFC_ULLRAM_BANK11026_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11026_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11027
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11027_DATA_W 32
+#define RFC_ULLRAM_BANK11027_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11027_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11028
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11028_DATA_W 32
+#define RFC_ULLRAM_BANK11028_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11028_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11029
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11029_DATA_W 32
+#define RFC_ULLRAM_BANK11029_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11029_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11030
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11030_DATA_W 32
+#define RFC_ULLRAM_BANK11030_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11030_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11031
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11031_DATA_W 32
+#define RFC_ULLRAM_BANK11031_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11031_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11032
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11032_DATA_W 32
+#define RFC_ULLRAM_BANK11032_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11032_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11033
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11033_DATA_W 32
+#define RFC_ULLRAM_BANK11033_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11033_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11034
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11034_DATA_W 32
+#define RFC_ULLRAM_BANK11034_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11034_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11035
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11035_DATA_W 32
+#define RFC_ULLRAM_BANK11035_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11035_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11036
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11036_DATA_W 32
+#define RFC_ULLRAM_BANK11036_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11036_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11037
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11037_DATA_W 32
+#define RFC_ULLRAM_BANK11037_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11037_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11038
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11038_DATA_W 32
+#define RFC_ULLRAM_BANK11038_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11038_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11039
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11039_DATA_W 32
+#define RFC_ULLRAM_BANK11039_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11039_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11040
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11040_DATA_W 32
+#define RFC_ULLRAM_BANK11040_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11040_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11041
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11041_DATA_W 32
+#define RFC_ULLRAM_BANK11041_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11041_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11042
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11042_DATA_W 32
+#define RFC_ULLRAM_BANK11042_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11042_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11043
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11043_DATA_W 32
+#define RFC_ULLRAM_BANK11043_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11043_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11044
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11044_DATA_W 32
+#define RFC_ULLRAM_BANK11044_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11044_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11045
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11045_DATA_W 32
+#define RFC_ULLRAM_BANK11045_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11045_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11046
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11046_DATA_W 32
+#define RFC_ULLRAM_BANK11046_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11046_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11047
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11047_DATA_W 32
+#define RFC_ULLRAM_BANK11047_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11047_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11048
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11048_DATA_W 32
+#define RFC_ULLRAM_BANK11048_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11048_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11049
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11049_DATA_W 32
+#define RFC_ULLRAM_BANK11049_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11049_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11050
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11050_DATA_W 32
+#define RFC_ULLRAM_BANK11050_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11050_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11051
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11051_DATA_W 32
+#define RFC_ULLRAM_BANK11051_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11051_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11052
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11052_DATA_W 32
+#define RFC_ULLRAM_BANK11052_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11052_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11053
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11053_DATA_W 32
+#define RFC_ULLRAM_BANK11053_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11053_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11054
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11054_DATA_W 32
+#define RFC_ULLRAM_BANK11054_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11054_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11055
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11055_DATA_W 32
+#define RFC_ULLRAM_BANK11055_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11055_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11056
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11056_DATA_W 32
+#define RFC_ULLRAM_BANK11056_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11056_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11057
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11057_DATA_W 32
+#define RFC_ULLRAM_BANK11057_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11057_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11058
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11058_DATA_W 32
+#define RFC_ULLRAM_BANK11058_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11058_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11059
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11059_DATA_W 32
+#define RFC_ULLRAM_BANK11059_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11059_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11060
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11060_DATA_W 32
+#define RFC_ULLRAM_BANK11060_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11060_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11061
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11061_DATA_W 32
+#define RFC_ULLRAM_BANK11061_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11061_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11062
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11062_DATA_W 32
+#define RFC_ULLRAM_BANK11062_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11062_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11063
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11063_DATA_W 32
+#define RFC_ULLRAM_BANK11063_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11063_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11064
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11064_DATA_W 32
+#define RFC_ULLRAM_BANK11064_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11064_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11065
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11065_DATA_W 32
+#define RFC_ULLRAM_BANK11065_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11065_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11066
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11066_DATA_W 32
+#define RFC_ULLRAM_BANK11066_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11066_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11067
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11067_DATA_W 32
+#define RFC_ULLRAM_BANK11067_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11067_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11068
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11068_DATA_W 32
+#define RFC_ULLRAM_BANK11068_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11068_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11069
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11069_DATA_W 32
+#define RFC_ULLRAM_BANK11069_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11069_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11070
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11070_DATA_W 32
+#define RFC_ULLRAM_BANK11070_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11070_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11071
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11071_DATA_W 32
+#define RFC_ULLRAM_BANK11071_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11071_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11072
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11072_DATA_W 32
+#define RFC_ULLRAM_BANK11072_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11072_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11073
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11073_DATA_W 32
+#define RFC_ULLRAM_BANK11073_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11073_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11074
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11074_DATA_W 32
+#define RFC_ULLRAM_BANK11074_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11074_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11075
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11075_DATA_W 32
+#define RFC_ULLRAM_BANK11075_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11075_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11076
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11076_DATA_W 32
+#define RFC_ULLRAM_BANK11076_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11076_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11077
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11077_DATA_W 32
+#define RFC_ULLRAM_BANK11077_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11077_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11078
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11078_DATA_W 32
+#define RFC_ULLRAM_BANK11078_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11078_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11079
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11079_DATA_W 32
+#define RFC_ULLRAM_BANK11079_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11079_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11080
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11080_DATA_W 32
+#define RFC_ULLRAM_BANK11080_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11080_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11081
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11081_DATA_W 32
+#define RFC_ULLRAM_BANK11081_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11081_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11082
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11082_DATA_W 32
+#define RFC_ULLRAM_BANK11082_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11082_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11083
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11083_DATA_W 32
+#define RFC_ULLRAM_BANK11083_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11083_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11084
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11084_DATA_W 32
+#define RFC_ULLRAM_BANK11084_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11084_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11085
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11085_DATA_W 32
+#define RFC_ULLRAM_BANK11085_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11085_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11086
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11086_DATA_W 32
+#define RFC_ULLRAM_BANK11086_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11086_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11087
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11087_DATA_W 32
+#define RFC_ULLRAM_BANK11087_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11087_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11088
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11088_DATA_W 32
+#define RFC_ULLRAM_BANK11088_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11088_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11089
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11089_DATA_W 32
+#define RFC_ULLRAM_BANK11089_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11089_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11090
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11090_DATA_W 32
+#define RFC_ULLRAM_BANK11090_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11090_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11091
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11091_DATA_W 32
+#define RFC_ULLRAM_BANK11091_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11091_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11092
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11092_DATA_W 32
+#define RFC_ULLRAM_BANK11092_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11092_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11093
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11093_DATA_W 32
+#define RFC_ULLRAM_BANK11093_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11093_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11094
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11094_DATA_W 32
+#define RFC_ULLRAM_BANK11094_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11094_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11095
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11095_DATA_W 32
+#define RFC_ULLRAM_BANK11095_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11095_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11096
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11096_DATA_W 32
+#define RFC_ULLRAM_BANK11096_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11096_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11097
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11097_DATA_W 32
+#define RFC_ULLRAM_BANK11097_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11097_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11098
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11098_DATA_W 32
+#define RFC_ULLRAM_BANK11098_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11098_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11099
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11099_DATA_W 32
+#define RFC_ULLRAM_BANK11099_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11099_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11100
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11100_DATA_W 32
+#define RFC_ULLRAM_BANK11100_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11100_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11101
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11101_DATA_W 32
+#define RFC_ULLRAM_BANK11101_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11101_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11102
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11102_DATA_W 32
+#define RFC_ULLRAM_BANK11102_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11102_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11103
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11103_DATA_W 32
+#define RFC_ULLRAM_BANK11103_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11103_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11104
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11104_DATA_W 32
+#define RFC_ULLRAM_BANK11104_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11104_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11105
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11105_DATA_W 32
+#define RFC_ULLRAM_BANK11105_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11105_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11106
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11106_DATA_W 32
+#define RFC_ULLRAM_BANK11106_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11106_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11107
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11107_DATA_W 32
+#define RFC_ULLRAM_BANK11107_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11107_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11108
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11108_DATA_W 32
+#define RFC_ULLRAM_BANK11108_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11108_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11109
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11109_DATA_W 32
+#define RFC_ULLRAM_BANK11109_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11109_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11110
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11110_DATA_W 32
+#define RFC_ULLRAM_BANK11110_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11110_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11111
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11111_DATA_W 32
+#define RFC_ULLRAM_BANK11111_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11111_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11112
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11112_DATA_W 32
+#define RFC_ULLRAM_BANK11112_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11112_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11113
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11113_DATA_W 32
+#define RFC_ULLRAM_BANK11113_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11113_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11114
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11114_DATA_W 32
+#define RFC_ULLRAM_BANK11114_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11114_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11115
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11115_DATA_W 32
+#define RFC_ULLRAM_BANK11115_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11115_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11116
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11116_DATA_W 32
+#define RFC_ULLRAM_BANK11116_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11116_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11117
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11117_DATA_W 32
+#define RFC_ULLRAM_BANK11117_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11117_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11118
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11118_DATA_W 32
+#define RFC_ULLRAM_BANK11118_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11118_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11119
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11119_DATA_W 32
+#define RFC_ULLRAM_BANK11119_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11119_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11120
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11120_DATA_W 32
+#define RFC_ULLRAM_BANK11120_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11120_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11121
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11121_DATA_W 32
+#define RFC_ULLRAM_BANK11121_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11121_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11122
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11122_DATA_W 32
+#define RFC_ULLRAM_BANK11122_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11122_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11123
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11123_DATA_W 32
+#define RFC_ULLRAM_BANK11123_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11123_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11124
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11124_DATA_W 32
+#define RFC_ULLRAM_BANK11124_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11124_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11125
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11125_DATA_W 32
+#define RFC_ULLRAM_BANK11125_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11125_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11126
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11126_DATA_W 32
+#define RFC_ULLRAM_BANK11126_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11126_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11127
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11127_DATA_W 32
+#define RFC_ULLRAM_BANK11127_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11127_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11128
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11128_DATA_W 32
+#define RFC_ULLRAM_BANK11128_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11128_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11129
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11129_DATA_W 32
+#define RFC_ULLRAM_BANK11129_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11129_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11130
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11130_DATA_W 32
+#define RFC_ULLRAM_BANK11130_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11130_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11131
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11131_DATA_W 32
+#define RFC_ULLRAM_BANK11131_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11131_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11132
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11132_DATA_W 32
+#define RFC_ULLRAM_BANK11132_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11132_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11133
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11133_DATA_W 32
+#define RFC_ULLRAM_BANK11133_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11133_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11134
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11134_DATA_W 32
+#define RFC_ULLRAM_BANK11134_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11134_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11135
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11135_DATA_W 32
+#define RFC_ULLRAM_BANK11135_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11135_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11136
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11136_DATA_W 32
+#define RFC_ULLRAM_BANK11136_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11136_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11137
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11137_DATA_W 32
+#define RFC_ULLRAM_BANK11137_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11137_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11138
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11138_DATA_W 32
+#define RFC_ULLRAM_BANK11138_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11138_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11139
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11139_DATA_W 32
+#define RFC_ULLRAM_BANK11139_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11139_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11140
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11140_DATA_W 32
+#define RFC_ULLRAM_BANK11140_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11140_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11141
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11141_DATA_W 32
+#define RFC_ULLRAM_BANK11141_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11141_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11142
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11142_DATA_W 32
+#define RFC_ULLRAM_BANK11142_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11142_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11143
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11143_DATA_W 32
+#define RFC_ULLRAM_BANK11143_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11143_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11144
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11144_DATA_W 32
+#define RFC_ULLRAM_BANK11144_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11144_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11145
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11145_DATA_W 32
+#define RFC_ULLRAM_BANK11145_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11145_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11146
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11146_DATA_W 32
+#define RFC_ULLRAM_BANK11146_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11146_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11147
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11147_DATA_W 32
+#define RFC_ULLRAM_BANK11147_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11147_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11148
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11148_DATA_W 32
+#define RFC_ULLRAM_BANK11148_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11148_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11149
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11149_DATA_W 32
+#define RFC_ULLRAM_BANK11149_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11149_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11150
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11150_DATA_W 32
+#define RFC_ULLRAM_BANK11150_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11150_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11151
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11151_DATA_W 32
+#define RFC_ULLRAM_BANK11151_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11151_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11152
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11152_DATA_W 32
+#define RFC_ULLRAM_BANK11152_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11152_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11153
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11153_DATA_W 32
+#define RFC_ULLRAM_BANK11153_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11153_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11154
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11154_DATA_W 32
+#define RFC_ULLRAM_BANK11154_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11154_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11155
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11155_DATA_W 32
+#define RFC_ULLRAM_BANK11155_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11155_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11156
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11156_DATA_W 32
+#define RFC_ULLRAM_BANK11156_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11156_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11157
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11157_DATA_W 32
+#define RFC_ULLRAM_BANK11157_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11157_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11158
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11158_DATA_W 32
+#define RFC_ULLRAM_BANK11158_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11158_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11159
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11159_DATA_W 32
+#define RFC_ULLRAM_BANK11159_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11159_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11160
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11160_DATA_W 32
+#define RFC_ULLRAM_BANK11160_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11160_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11161
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11161_DATA_W 32
+#define RFC_ULLRAM_BANK11161_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11161_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11162
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11162_DATA_W 32
+#define RFC_ULLRAM_BANK11162_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11162_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11163
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11163_DATA_W 32
+#define RFC_ULLRAM_BANK11163_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11163_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11164
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11164_DATA_W 32
+#define RFC_ULLRAM_BANK11164_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11164_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11165
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11165_DATA_W 32
+#define RFC_ULLRAM_BANK11165_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11165_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11166
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11166_DATA_W 32
+#define RFC_ULLRAM_BANK11166_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11166_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11167
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11167_DATA_W 32
+#define RFC_ULLRAM_BANK11167_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11167_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11168
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11168_DATA_W 32
+#define RFC_ULLRAM_BANK11168_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11168_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11169
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11169_DATA_W 32
+#define RFC_ULLRAM_BANK11169_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11169_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11170
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11170_DATA_W 32
+#define RFC_ULLRAM_BANK11170_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11170_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11171
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11171_DATA_W 32
+#define RFC_ULLRAM_BANK11171_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11171_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11172
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11172_DATA_W 32
+#define RFC_ULLRAM_BANK11172_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11172_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11173
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11173_DATA_W 32
+#define RFC_ULLRAM_BANK11173_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11173_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11174
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11174_DATA_W 32
+#define RFC_ULLRAM_BANK11174_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11174_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11175
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11175_DATA_W 32
+#define RFC_ULLRAM_BANK11175_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11175_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11176
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11176_DATA_W 32
+#define RFC_ULLRAM_BANK11176_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11176_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11177
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11177_DATA_W 32
+#define RFC_ULLRAM_BANK11177_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11177_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11178
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11178_DATA_W 32
+#define RFC_ULLRAM_BANK11178_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11178_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11179
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11179_DATA_W 32
+#define RFC_ULLRAM_BANK11179_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11179_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11180
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11180_DATA_W 32
+#define RFC_ULLRAM_BANK11180_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11180_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11181
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11181_DATA_W 32
+#define RFC_ULLRAM_BANK11181_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11181_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11182
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11182_DATA_W 32
+#define RFC_ULLRAM_BANK11182_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11182_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11183
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11183_DATA_W 32
+#define RFC_ULLRAM_BANK11183_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11183_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11184
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11184_DATA_W 32
+#define RFC_ULLRAM_BANK11184_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11184_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11185
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11185_DATA_W 32
+#define RFC_ULLRAM_BANK11185_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11185_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11186
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11186_DATA_W 32
+#define RFC_ULLRAM_BANK11186_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11186_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11187
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11187_DATA_W 32
+#define RFC_ULLRAM_BANK11187_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11187_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11188
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11188_DATA_W 32
+#define RFC_ULLRAM_BANK11188_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11188_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11189
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11189_DATA_W 32
+#define RFC_ULLRAM_BANK11189_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11189_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11190
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11190_DATA_W 32
+#define RFC_ULLRAM_BANK11190_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11190_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11191
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11191_DATA_W 32
+#define RFC_ULLRAM_BANK11191_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11191_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11192
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11192_DATA_W 32
+#define RFC_ULLRAM_BANK11192_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11192_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11193
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11193_DATA_W 32
+#define RFC_ULLRAM_BANK11193_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11193_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11194
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11194_DATA_W 32
+#define RFC_ULLRAM_BANK11194_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11194_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11195
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11195_DATA_W 32
+#define RFC_ULLRAM_BANK11195_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11195_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11196
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11196_DATA_W 32
+#define RFC_ULLRAM_BANK11196_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11196_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11197
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11197_DATA_W 32
+#define RFC_ULLRAM_BANK11197_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11197_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11198
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11198_DATA_W 32
+#define RFC_ULLRAM_BANK11198_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11198_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11199
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11199_DATA_W 32
+#define RFC_ULLRAM_BANK11199_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11199_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11200
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11200_DATA_W 32
+#define RFC_ULLRAM_BANK11200_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11200_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11201
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11201_DATA_W 32
+#define RFC_ULLRAM_BANK11201_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11201_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11202
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11202_DATA_W 32
+#define RFC_ULLRAM_BANK11202_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11202_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11203
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11203_DATA_W 32
+#define RFC_ULLRAM_BANK11203_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11203_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11204
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11204_DATA_W 32
+#define RFC_ULLRAM_BANK11204_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11204_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11205
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11205_DATA_W 32
+#define RFC_ULLRAM_BANK11205_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11205_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11206
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11206_DATA_W 32
+#define RFC_ULLRAM_BANK11206_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11206_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11207
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11207_DATA_W 32
+#define RFC_ULLRAM_BANK11207_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11207_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11208
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11208_DATA_W 32
+#define RFC_ULLRAM_BANK11208_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11208_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11209
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11209_DATA_W 32
+#define RFC_ULLRAM_BANK11209_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11209_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11210
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11210_DATA_W 32
+#define RFC_ULLRAM_BANK11210_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11210_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11211
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11211_DATA_W 32
+#define RFC_ULLRAM_BANK11211_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11211_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11212
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11212_DATA_W 32
+#define RFC_ULLRAM_BANK11212_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11212_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11213
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11213_DATA_W 32
+#define RFC_ULLRAM_BANK11213_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11213_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11214
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11214_DATA_W 32
+#define RFC_ULLRAM_BANK11214_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11214_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11215
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11215_DATA_W 32
+#define RFC_ULLRAM_BANK11215_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11215_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11216
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11216_DATA_W 32
+#define RFC_ULLRAM_BANK11216_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11216_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11217
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11217_DATA_W 32
+#define RFC_ULLRAM_BANK11217_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11217_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11218
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11218_DATA_W 32
+#define RFC_ULLRAM_BANK11218_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11218_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11219
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11219_DATA_W 32
+#define RFC_ULLRAM_BANK11219_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11219_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11220
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11220_DATA_W 32
+#define RFC_ULLRAM_BANK11220_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11220_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11221
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11221_DATA_W 32
+#define RFC_ULLRAM_BANK11221_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11221_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11222
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11222_DATA_W 32
+#define RFC_ULLRAM_BANK11222_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11222_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11223
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11223_DATA_W 32
+#define RFC_ULLRAM_BANK11223_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11223_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11224
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11224_DATA_W 32
+#define RFC_ULLRAM_BANK11224_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11224_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11225
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11225_DATA_W 32
+#define RFC_ULLRAM_BANK11225_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11225_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11226
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11226_DATA_W 32
+#define RFC_ULLRAM_BANK11226_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11226_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11227
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11227_DATA_W 32
+#define RFC_ULLRAM_BANK11227_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11227_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11228
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11228_DATA_W 32
+#define RFC_ULLRAM_BANK11228_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11228_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11229
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11229_DATA_W 32
+#define RFC_ULLRAM_BANK11229_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11229_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11230
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11230_DATA_W 32
+#define RFC_ULLRAM_BANK11230_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11230_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11231
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11231_DATA_W 32
+#define RFC_ULLRAM_BANK11231_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11231_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11232
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11232_DATA_W 32
+#define RFC_ULLRAM_BANK11232_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11232_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11233
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11233_DATA_W 32
+#define RFC_ULLRAM_BANK11233_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11233_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11234
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11234_DATA_W 32
+#define RFC_ULLRAM_BANK11234_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11234_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11235
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11235_DATA_W 32
+#define RFC_ULLRAM_BANK11235_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11235_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11236
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11236_DATA_W 32
+#define RFC_ULLRAM_BANK11236_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11236_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11237
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11237_DATA_W 32
+#define RFC_ULLRAM_BANK11237_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11237_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11238
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11238_DATA_W 32
+#define RFC_ULLRAM_BANK11238_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11238_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11239
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11239_DATA_W 32
+#define RFC_ULLRAM_BANK11239_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11239_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11240
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11240_DATA_W 32
+#define RFC_ULLRAM_BANK11240_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11240_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11241
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11241_DATA_W 32
+#define RFC_ULLRAM_BANK11241_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11241_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11242
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11242_DATA_W 32
+#define RFC_ULLRAM_BANK11242_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11242_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11243
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11243_DATA_W 32
+#define RFC_ULLRAM_BANK11243_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11243_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11244
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11244_DATA_W 32
+#define RFC_ULLRAM_BANK11244_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11244_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11245
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11245_DATA_W 32
+#define RFC_ULLRAM_BANK11245_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11245_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11246
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11246_DATA_W 32
+#define RFC_ULLRAM_BANK11246_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11246_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11247
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11247_DATA_W 32
+#define RFC_ULLRAM_BANK11247_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11247_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11248
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11248_DATA_W 32
+#define RFC_ULLRAM_BANK11248_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11248_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11249
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11249_DATA_W 32
+#define RFC_ULLRAM_BANK11249_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11249_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11250
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11250_DATA_W 32
+#define RFC_ULLRAM_BANK11250_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11250_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11251
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11251_DATA_W 32
+#define RFC_ULLRAM_BANK11251_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11251_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11252
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11252_DATA_W 32
+#define RFC_ULLRAM_BANK11252_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11252_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11253
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11253_DATA_W 32
+#define RFC_ULLRAM_BANK11253_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11253_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11254
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11254_DATA_W 32
+#define RFC_ULLRAM_BANK11254_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11254_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11255
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11255_DATA_W 32
+#define RFC_ULLRAM_BANK11255_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11255_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11256
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11256_DATA_W 32
+#define RFC_ULLRAM_BANK11256_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11256_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11257
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11257_DATA_W 32
+#define RFC_ULLRAM_BANK11257_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11257_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11258
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11258_DATA_W 32
+#define RFC_ULLRAM_BANK11258_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11258_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11259
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11259_DATA_W 32
+#define RFC_ULLRAM_BANK11259_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11259_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11260
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11260_DATA_W 32
+#define RFC_ULLRAM_BANK11260_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11260_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11261
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11261_DATA_W 32
+#define RFC_ULLRAM_BANK11261_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11261_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11262
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11262_DATA_W 32
+#define RFC_ULLRAM_BANK11262_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11262_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11263
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11263_DATA_W 32
+#define RFC_ULLRAM_BANK11263_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11263_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11264
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11264_DATA_W 32
+#define RFC_ULLRAM_BANK11264_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11264_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11265
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11265_DATA_W 32
+#define RFC_ULLRAM_BANK11265_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11265_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11266
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11266_DATA_W 32
+#define RFC_ULLRAM_BANK11266_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11266_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11267
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11267_DATA_W 32
+#define RFC_ULLRAM_BANK11267_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11267_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11268
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11268_DATA_W 32
+#define RFC_ULLRAM_BANK11268_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11268_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11269
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11269_DATA_W 32
+#define RFC_ULLRAM_BANK11269_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11269_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11270
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11270_DATA_W 32
+#define RFC_ULLRAM_BANK11270_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11270_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11271
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11271_DATA_W 32
+#define RFC_ULLRAM_BANK11271_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11271_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11272
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11272_DATA_W 32
+#define RFC_ULLRAM_BANK11272_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11272_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11273
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11273_DATA_W 32
+#define RFC_ULLRAM_BANK11273_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11273_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11274
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11274_DATA_W 32
+#define RFC_ULLRAM_BANK11274_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11274_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11275
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11275_DATA_W 32
+#define RFC_ULLRAM_BANK11275_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11275_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11276
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11276_DATA_W 32
+#define RFC_ULLRAM_BANK11276_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11276_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11277
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11277_DATA_W 32
+#define RFC_ULLRAM_BANK11277_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11277_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11278
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11278_DATA_W 32
+#define RFC_ULLRAM_BANK11278_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11278_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11279
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11279_DATA_W 32
+#define RFC_ULLRAM_BANK11279_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11279_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11280
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11280_DATA_W 32
+#define RFC_ULLRAM_BANK11280_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11280_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11281
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11281_DATA_W 32
+#define RFC_ULLRAM_BANK11281_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11281_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11282
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11282_DATA_W 32
+#define RFC_ULLRAM_BANK11282_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11282_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11283
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11283_DATA_W 32
+#define RFC_ULLRAM_BANK11283_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11283_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11284
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11284_DATA_W 32
+#define RFC_ULLRAM_BANK11284_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11284_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11285
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11285_DATA_W 32
+#define RFC_ULLRAM_BANK11285_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11285_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11286
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11286_DATA_W 32
+#define RFC_ULLRAM_BANK11286_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11286_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11287
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11287_DATA_W 32
+#define RFC_ULLRAM_BANK11287_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11287_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11288
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11288_DATA_W 32
+#define RFC_ULLRAM_BANK11288_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11288_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11289
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11289_DATA_W 32
+#define RFC_ULLRAM_BANK11289_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11289_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11290
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11290_DATA_W 32
+#define RFC_ULLRAM_BANK11290_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11290_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11291
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11291_DATA_W 32
+#define RFC_ULLRAM_BANK11291_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11291_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11292
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11292_DATA_W 32
+#define RFC_ULLRAM_BANK11292_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11292_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11293
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11293_DATA_W 32
+#define RFC_ULLRAM_BANK11293_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11293_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11294
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11294_DATA_W 32
+#define RFC_ULLRAM_BANK11294_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11294_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11295
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11295_DATA_W 32
+#define RFC_ULLRAM_BANK11295_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11295_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11296
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11296_DATA_W 32
+#define RFC_ULLRAM_BANK11296_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11296_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11297
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11297_DATA_W 32
+#define RFC_ULLRAM_BANK11297_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11297_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11298
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11298_DATA_W 32
+#define RFC_ULLRAM_BANK11298_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11298_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11299
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11299_DATA_W 32
+#define RFC_ULLRAM_BANK11299_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11299_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11300
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11300_DATA_W 32
+#define RFC_ULLRAM_BANK11300_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11300_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11301
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11301_DATA_W 32
+#define RFC_ULLRAM_BANK11301_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11301_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11302
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11302_DATA_W 32
+#define RFC_ULLRAM_BANK11302_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11302_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11303
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11303_DATA_W 32
+#define RFC_ULLRAM_BANK11303_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11303_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11304
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11304_DATA_W 32
+#define RFC_ULLRAM_BANK11304_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11304_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11305
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11305_DATA_W 32
+#define RFC_ULLRAM_BANK11305_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11305_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11306
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11306_DATA_W 32
+#define RFC_ULLRAM_BANK11306_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11306_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11307
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11307_DATA_W 32
+#define RFC_ULLRAM_BANK11307_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11307_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11308
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11308_DATA_W 32
+#define RFC_ULLRAM_BANK11308_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11308_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11309
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11309_DATA_W 32
+#define RFC_ULLRAM_BANK11309_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11309_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11310
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11310_DATA_W 32
+#define RFC_ULLRAM_BANK11310_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11310_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11311
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11311_DATA_W 32
+#define RFC_ULLRAM_BANK11311_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11311_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11312
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11312_DATA_W 32
+#define RFC_ULLRAM_BANK11312_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11312_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11313
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11313_DATA_W 32
+#define RFC_ULLRAM_BANK11313_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11313_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11314
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11314_DATA_W 32
+#define RFC_ULLRAM_BANK11314_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11314_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11315
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11315_DATA_W 32
+#define RFC_ULLRAM_BANK11315_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11315_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11316
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11316_DATA_W 32
+#define RFC_ULLRAM_BANK11316_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11316_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11317
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11317_DATA_W 32
+#define RFC_ULLRAM_BANK11317_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11317_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11318
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11318_DATA_W 32
+#define RFC_ULLRAM_BANK11318_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11318_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11319
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11319_DATA_W 32
+#define RFC_ULLRAM_BANK11319_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11319_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11320
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11320_DATA_W 32
+#define RFC_ULLRAM_BANK11320_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11320_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11321
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11321_DATA_W 32
+#define RFC_ULLRAM_BANK11321_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11321_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11322
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11322_DATA_W 32
+#define RFC_ULLRAM_BANK11322_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11322_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11323
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11323_DATA_W 32
+#define RFC_ULLRAM_BANK11323_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11323_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11324
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11324_DATA_W 32
+#define RFC_ULLRAM_BANK11324_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11324_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11325
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11325_DATA_W 32
+#define RFC_ULLRAM_BANK11325_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11325_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11326
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11326_DATA_W 32
+#define RFC_ULLRAM_BANK11326_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11326_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11327
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11327_DATA_W 32
+#define RFC_ULLRAM_BANK11327_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11327_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11328
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11328_DATA_W 32
+#define RFC_ULLRAM_BANK11328_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11328_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11329
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11329_DATA_W 32
+#define RFC_ULLRAM_BANK11329_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11329_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11330
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11330_DATA_W 32
+#define RFC_ULLRAM_BANK11330_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11330_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11331
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11331_DATA_W 32
+#define RFC_ULLRAM_BANK11331_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11331_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11332
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11332_DATA_W 32
+#define RFC_ULLRAM_BANK11332_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11332_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11333
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11333_DATA_W 32
+#define RFC_ULLRAM_BANK11333_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11333_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11334
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11334_DATA_W 32
+#define RFC_ULLRAM_BANK11334_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11334_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11335
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11335_DATA_W 32
+#define RFC_ULLRAM_BANK11335_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11335_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11336
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11336_DATA_W 32
+#define RFC_ULLRAM_BANK11336_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11336_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11337
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11337_DATA_W 32
+#define RFC_ULLRAM_BANK11337_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11337_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11338
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11338_DATA_W 32
+#define RFC_ULLRAM_BANK11338_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11338_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11339
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11339_DATA_W 32
+#define RFC_ULLRAM_BANK11339_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11339_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11340
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11340_DATA_W 32
+#define RFC_ULLRAM_BANK11340_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11340_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11341
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11341_DATA_W 32
+#define RFC_ULLRAM_BANK11341_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11341_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11342
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11342_DATA_W 32
+#define RFC_ULLRAM_BANK11342_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11342_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11343
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11343_DATA_W 32
+#define RFC_ULLRAM_BANK11343_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11343_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11344
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11344_DATA_W 32
+#define RFC_ULLRAM_BANK11344_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11344_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11345
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11345_DATA_W 32
+#define RFC_ULLRAM_BANK11345_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11345_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11346
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11346_DATA_W 32
+#define RFC_ULLRAM_BANK11346_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11346_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11347
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11347_DATA_W 32
+#define RFC_ULLRAM_BANK11347_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11347_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11348
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11348_DATA_W 32
+#define RFC_ULLRAM_BANK11348_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11348_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11349
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11349_DATA_W 32
+#define RFC_ULLRAM_BANK11349_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11349_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11350
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11350_DATA_W 32
+#define RFC_ULLRAM_BANK11350_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11350_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11351
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11351_DATA_W 32
+#define RFC_ULLRAM_BANK11351_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11351_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11352
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11352_DATA_W 32
+#define RFC_ULLRAM_BANK11352_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11352_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11353
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11353_DATA_W 32
+#define RFC_ULLRAM_BANK11353_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11353_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11354
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11354_DATA_W 32
+#define RFC_ULLRAM_BANK11354_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11354_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11355
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11355_DATA_W 32
+#define RFC_ULLRAM_BANK11355_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11355_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11356
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11356_DATA_W 32
+#define RFC_ULLRAM_BANK11356_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11356_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11357
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11357_DATA_W 32
+#define RFC_ULLRAM_BANK11357_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11357_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11358
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11358_DATA_W 32
+#define RFC_ULLRAM_BANK11358_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11358_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11359
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11359_DATA_W 32
+#define RFC_ULLRAM_BANK11359_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11359_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11360
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11360_DATA_W 32
+#define RFC_ULLRAM_BANK11360_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11360_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11361
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11361_DATA_W 32
+#define RFC_ULLRAM_BANK11361_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11361_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11362
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11362_DATA_W 32
+#define RFC_ULLRAM_BANK11362_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11362_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11363
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11363_DATA_W 32
+#define RFC_ULLRAM_BANK11363_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11363_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11364
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11364_DATA_W 32
+#define RFC_ULLRAM_BANK11364_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11364_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11365
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11365_DATA_W 32
+#define RFC_ULLRAM_BANK11365_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11365_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11366
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11366_DATA_W 32
+#define RFC_ULLRAM_BANK11366_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11366_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11367
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11367_DATA_W 32
+#define RFC_ULLRAM_BANK11367_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11367_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11368
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11368_DATA_W 32
+#define RFC_ULLRAM_BANK11368_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11368_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11369
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11369_DATA_W 32
+#define RFC_ULLRAM_BANK11369_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11369_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11370
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11370_DATA_W 32
+#define RFC_ULLRAM_BANK11370_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11370_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11371
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11371_DATA_W 32
+#define RFC_ULLRAM_BANK11371_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11371_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11372
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11372_DATA_W 32
+#define RFC_ULLRAM_BANK11372_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11372_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11373
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11373_DATA_W 32
+#define RFC_ULLRAM_BANK11373_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11373_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11374
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11374_DATA_W 32
+#define RFC_ULLRAM_BANK11374_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11374_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11375
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11375_DATA_W 32
+#define RFC_ULLRAM_BANK11375_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11375_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11376
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11376_DATA_W 32
+#define RFC_ULLRAM_BANK11376_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11376_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11377
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11377_DATA_W 32
+#define RFC_ULLRAM_BANK11377_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11377_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11378
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11378_DATA_W 32
+#define RFC_ULLRAM_BANK11378_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11378_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11379
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11379_DATA_W 32
+#define RFC_ULLRAM_BANK11379_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11379_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11380
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11380_DATA_W 32
+#define RFC_ULLRAM_BANK11380_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11380_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11381
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11381_DATA_W 32
+#define RFC_ULLRAM_BANK11381_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11381_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11382
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11382_DATA_W 32
+#define RFC_ULLRAM_BANK11382_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11382_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11383
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11383_DATA_W 32
+#define RFC_ULLRAM_BANK11383_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11383_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11384
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11384_DATA_W 32
+#define RFC_ULLRAM_BANK11384_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11384_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11385
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11385_DATA_W 32
+#define RFC_ULLRAM_BANK11385_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11385_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11386
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11386_DATA_W 32
+#define RFC_ULLRAM_BANK11386_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11386_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11387
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11387_DATA_W 32
+#define RFC_ULLRAM_BANK11387_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11387_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11388
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11388_DATA_W 32
+#define RFC_ULLRAM_BANK11388_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11388_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11389
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11389_DATA_W 32
+#define RFC_ULLRAM_BANK11389_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11389_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11390
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11390_DATA_W 32
+#define RFC_ULLRAM_BANK11390_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11390_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11391
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11391_DATA_W 32
+#define RFC_ULLRAM_BANK11391_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11391_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11392
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11392_DATA_W 32
+#define RFC_ULLRAM_BANK11392_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11392_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11393
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11393_DATA_W 32
+#define RFC_ULLRAM_BANK11393_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11393_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11394
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11394_DATA_W 32
+#define RFC_ULLRAM_BANK11394_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11394_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11395
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11395_DATA_W 32
+#define RFC_ULLRAM_BANK11395_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11395_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11396
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11396_DATA_W 32
+#define RFC_ULLRAM_BANK11396_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11396_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11397
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11397_DATA_W 32
+#define RFC_ULLRAM_BANK11397_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11397_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11398
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11398_DATA_W 32
+#define RFC_ULLRAM_BANK11398_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11398_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11399
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11399_DATA_W 32
+#define RFC_ULLRAM_BANK11399_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11399_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11400
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11400_DATA_W 32
+#define RFC_ULLRAM_BANK11400_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11400_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11401
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11401_DATA_W 32
+#define RFC_ULLRAM_BANK11401_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11401_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11402
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11402_DATA_W 32
+#define RFC_ULLRAM_BANK11402_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11402_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11403
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11403_DATA_W 32
+#define RFC_ULLRAM_BANK11403_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11403_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11404
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11404_DATA_W 32
+#define RFC_ULLRAM_BANK11404_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11404_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11405
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11405_DATA_W 32
+#define RFC_ULLRAM_BANK11405_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11405_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11406
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11406_DATA_W 32
+#define RFC_ULLRAM_BANK11406_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11406_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11407
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11407_DATA_W 32
+#define RFC_ULLRAM_BANK11407_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11407_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11408
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11408_DATA_W 32
+#define RFC_ULLRAM_BANK11408_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11408_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11409
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11409_DATA_W 32
+#define RFC_ULLRAM_BANK11409_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11409_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11410
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11410_DATA_W 32
+#define RFC_ULLRAM_BANK11410_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11410_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11411
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11411_DATA_W 32
+#define RFC_ULLRAM_BANK11411_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11411_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11412
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11412_DATA_W 32
+#define RFC_ULLRAM_BANK11412_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11412_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11413
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11413_DATA_W 32
+#define RFC_ULLRAM_BANK11413_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11413_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11414
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11414_DATA_W 32
+#define RFC_ULLRAM_BANK11414_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11414_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11415
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11415_DATA_W 32
+#define RFC_ULLRAM_BANK11415_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11415_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11416
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11416_DATA_W 32
+#define RFC_ULLRAM_BANK11416_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11416_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11417
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11417_DATA_W 32
+#define RFC_ULLRAM_BANK11417_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11417_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11418
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11418_DATA_W 32
+#define RFC_ULLRAM_BANK11418_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11418_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11419
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11419_DATA_W 32
+#define RFC_ULLRAM_BANK11419_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11419_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11420
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11420_DATA_W 32
+#define RFC_ULLRAM_BANK11420_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11420_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11421
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11421_DATA_W 32
+#define RFC_ULLRAM_BANK11421_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11421_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11422
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11422_DATA_W 32
+#define RFC_ULLRAM_BANK11422_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11422_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11423
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11423_DATA_W 32
+#define RFC_ULLRAM_BANK11423_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11423_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11424
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11424_DATA_W 32
+#define RFC_ULLRAM_BANK11424_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11424_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11425
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11425_DATA_W 32
+#define RFC_ULLRAM_BANK11425_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11425_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11426
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11426_DATA_W 32
+#define RFC_ULLRAM_BANK11426_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11426_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11427
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11427_DATA_W 32
+#define RFC_ULLRAM_BANK11427_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11427_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11428
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11428_DATA_W 32
+#define RFC_ULLRAM_BANK11428_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11428_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11429
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11429_DATA_W 32
+#define RFC_ULLRAM_BANK11429_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11429_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11430
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11430_DATA_W 32
+#define RFC_ULLRAM_BANK11430_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11430_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11431
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11431_DATA_W 32
+#define RFC_ULLRAM_BANK11431_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11431_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11432
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11432_DATA_W 32
+#define RFC_ULLRAM_BANK11432_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11432_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11433
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11433_DATA_W 32
+#define RFC_ULLRAM_BANK11433_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11433_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11434
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11434_DATA_W 32
+#define RFC_ULLRAM_BANK11434_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11434_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11435
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11435_DATA_W 32
+#define RFC_ULLRAM_BANK11435_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11435_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11436
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11436_DATA_W 32
+#define RFC_ULLRAM_BANK11436_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11436_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11437
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11437_DATA_W 32
+#define RFC_ULLRAM_BANK11437_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11437_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11438
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11438_DATA_W 32
+#define RFC_ULLRAM_BANK11438_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11438_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11439
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11439_DATA_W 32
+#define RFC_ULLRAM_BANK11439_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11439_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11440
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11440_DATA_W 32
+#define RFC_ULLRAM_BANK11440_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11440_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11441
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11441_DATA_W 32
+#define RFC_ULLRAM_BANK11441_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11441_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11442
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11442_DATA_W 32
+#define RFC_ULLRAM_BANK11442_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11442_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11443
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11443_DATA_W 32
+#define RFC_ULLRAM_BANK11443_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11443_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11444
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11444_DATA_W 32
+#define RFC_ULLRAM_BANK11444_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11444_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11445
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11445_DATA_W 32
+#define RFC_ULLRAM_BANK11445_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11445_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11446
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11446_DATA_W 32
+#define RFC_ULLRAM_BANK11446_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11446_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11447
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11447_DATA_W 32
+#define RFC_ULLRAM_BANK11447_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11447_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11448
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11448_DATA_W 32
+#define RFC_ULLRAM_BANK11448_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11448_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11449
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11449_DATA_W 32
+#define RFC_ULLRAM_BANK11449_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11449_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11450
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11450_DATA_W 32
+#define RFC_ULLRAM_BANK11450_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11450_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11451
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11451_DATA_W 32
+#define RFC_ULLRAM_BANK11451_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11451_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11452
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11452_DATA_W 32
+#define RFC_ULLRAM_BANK11452_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11452_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11453
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11453_DATA_W 32
+#define RFC_ULLRAM_BANK11453_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11453_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11454
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11454_DATA_W 32
+#define RFC_ULLRAM_BANK11454_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11454_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11455
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11455_DATA_W 32
+#define RFC_ULLRAM_BANK11455_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11455_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11456
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11456_DATA_W 32
+#define RFC_ULLRAM_BANK11456_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11456_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11457
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11457_DATA_W 32
+#define RFC_ULLRAM_BANK11457_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11457_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11458
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11458_DATA_W 32
+#define RFC_ULLRAM_BANK11458_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11458_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11459
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11459_DATA_W 32
+#define RFC_ULLRAM_BANK11459_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11459_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11460
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11460_DATA_W 32
+#define RFC_ULLRAM_BANK11460_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11460_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11461
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11461_DATA_W 32
+#define RFC_ULLRAM_BANK11461_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11461_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11462
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11462_DATA_W 32
+#define RFC_ULLRAM_BANK11462_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11462_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11463
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11463_DATA_W 32
+#define RFC_ULLRAM_BANK11463_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11463_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11464
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11464_DATA_W 32
+#define RFC_ULLRAM_BANK11464_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11464_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11465
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11465_DATA_W 32
+#define RFC_ULLRAM_BANK11465_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11465_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11466
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11466_DATA_W 32
+#define RFC_ULLRAM_BANK11466_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11466_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11467
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11467_DATA_W 32
+#define RFC_ULLRAM_BANK11467_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11467_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11468
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11468_DATA_W 32
+#define RFC_ULLRAM_BANK11468_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11468_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11469
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11469_DATA_W 32
+#define RFC_ULLRAM_BANK11469_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11469_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11470
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11470_DATA_W 32
+#define RFC_ULLRAM_BANK11470_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11470_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11471
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11471_DATA_W 32
+#define RFC_ULLRAM_BANK11471_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11471_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11472
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11472_DATA_W 32
+#define RFC_ULLRAM_BANK11472_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11472_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11473
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11473_DATA_W 32
+#define RFC_ULLRAM_BANK11473_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11473_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11474
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11474_DATA_W 32
+#define RFC_ULLRAM_BANK11474_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11474_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11475
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11475_DATA_W 32
+#define RFC_ULLRAM_BANK11475_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11475_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11476
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11476_DATA_W 32
+#define RFC_ULLRAM_BANK11476_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11476_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11477
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11477_DATA_W 32
+#define RFC_ULLRAM_BANK11477_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11477_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11478
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11478_DATA_W 32
+#define RFC_ULLRAM_BANK11478_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11478_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11479
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11479_DATA_W 32
+#define RFC_ULLRAM_BANK11479_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11479_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11480
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11480_DATA_W 32
+#define RFC_ULLRAM_BANK11480_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11480_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11481
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11481_DATA_W 32
+#define RFC_ULLRAM_BANK11481_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11481_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11482
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11482_DATA_W 32
+#define RFC_ULLRAM_BANK11482_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11482_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11483
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11483_DATA_W 32
+#define RFC_ULLRAM_BANK11483_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11483_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11484
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11484_DATA_W 32
+#define RFC_ULLRAM_BANK11484_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11484_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11485
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11485_DATA_W 32
+#define RFC_ULLRAM_BANK11485_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11485_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11486
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11486_DATA_W 32
+#define RFC_ULLRAM_BANK11486_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11486_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11487
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11487_DATA_W 32
+#define RFC_ULLRAM_BANK11487_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11487_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11488
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11488_DATA_W 32
+#define RFC_ULLRAM_BANK11488_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11488_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11489
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11489_DATA_W 32
+#define RFC_ULLRAM_BANK11489_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11489_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11490
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11490_DATA_W 32
+#define RFC_ULLRAM_BANK11490_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11490_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11491
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11491_DATA_W 32
+#define RFC_ULLRAM_BANK11491_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11491_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11492
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11492_DATA_W 32
+#define RFC_ULLRAM_BANK11492_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11492_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11493
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11493_DATA_W 32
+#define RFC_ULLRAM_BANK11493_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11493_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11494
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11494_DATA_W 32
+#define RFC_ULLRAM_BANK11494_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11494_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11495
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11495_DATA_W 32
+#define RFC_ULLRAM_BANK11495_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11495_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11496
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11496_DATA_W 32
+#define RFC_ULLRAM_BANK11496_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11496_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11497
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11497_DATA_W 32
+#define RFC_ULLRAM_BANK11497_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11497_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11498
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11498_DATA_W 32
+#define RFC_ULLRAM_BANK11498_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11498_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11499
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11499_DATA_W 32
+#define RFC_ULLRAM_BANK11499_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11499_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11500
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11500_DATA_W 32
+#define RFC_ULLRAM_BANK11500_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11500_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11501
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11501_DATA_W 32
+#define RFC_ULLRAM_BANK11501_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11501_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11502
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11502_DATA_W 32
+#define RFC_ULLRAM_BANK11502_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11502_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11503
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11503_DATA_W 32
+#define RFC_ULLRAM_BANK11503_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11503_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11504
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11504_DATA_W 32
+#define RFC_ULLRAM_BANK11504_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11504_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11505
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11505_DATA_W 32
+#define RFC_ULLRAM_BANK11505_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11505_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11506
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11506_DATA_W 32
+#define RFC_ULLRAM_BANK11506_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11506_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11507
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11507_DATA_W 32
+#define RFC_ULLRAM_BANK11507_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11507_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11508
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11508_DATA_W 32
+#define RFC_ULLRAM_BANK11508_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11508_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11509
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11509_DATA_W 32
+#define RFC_ULLRAM_BANK11509_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11509_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11510
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11510_DATA_W 32
+#define RFC_ULLRAM_BANK11510_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11510_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11511
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11511_DATA_W 32
+#define RFC_ULLRAM_BANK11511_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11511_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11512
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11512_DATA_W 32
+#define RFC_ULLRAM_BANK11512_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11512_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11513
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11513_DATA_W 32
+#define RFC_ULLRAM_BANK11513_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11513_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11514
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11514_DATA_W 32
+#define RFC_ULLRAM_BANK11514_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11514_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11515
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11515_DATA_W 32
+#define RFC_ULLRAM_BANK11515_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11515_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11516
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11516_DATA_W 32
+#define RFC_ULLRAM_BANK11516_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11516_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11517
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11517_DATA_W 32
+#define RFC_ULLRAM_BANK11517_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11517_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11518
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11518_DATA_W 32
+#define RFC_ULLRAM_BANK11518_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11518_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11519
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11519_DATA_W 32
+#define RFC_ULLRAM_BANK11519_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11519_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11520
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11520_DATA_W 32
+#define RFC_ULLRAM_BANK11520_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11520_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11521
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11521_DATA_W 32
+#define RFC_ULLRAM_BANK11521_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11521_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11522
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11522_DATA_W 32
+#define RFC_ULLRAM_BANK11522_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11522_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11523
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11523_DATA_W 32
+#define RFC_ULLRAM_BANK11523_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11523_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11524
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11524_DATA_W 32
+#define RFC_ULLRAM_BANK11524_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11524_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11525
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11525_DATA_W 32
+#define RFC_ULLRAM_BANK11525_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11525_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11526
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11526_DATA_W 32
+#define RFC_ULLRAM_BANK11526_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11526_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11527
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11527_DATA_W 32
+#define RFC_ULLRAM_BANK11527_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11527_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11528
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11528_DATA_W 32
+#define RFC_ULLRAM_BANK11528_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11528_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11529
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11529_DATA_W 32
+#define RFC_ULLRAM_BANK11529_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11529_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11530
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11530_DATA_W 32
+#define RFC_ULLRAM_BANK11530_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11530_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11531
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11531_DATA_W 32
+#define RFC_ULLRAM_BANK11531_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11531_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11532
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11532_DATA_W 32
+#define RFC_ULLRAM_BANK11532_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11532_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11533
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11533_DATA_W 32
+#define RFC_ULLRAM_BANK11533_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11533_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11534
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11534_DATA_W 32
+#define RFC_ULLRAM_BANK11534_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11534_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11535
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11535_DATA_W 32
+#define RFC_ULLRAM_BANK11535_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11535_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11536
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11536_DATA_W 32
+#define RFC_ULLRAM_BANK11536_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11536_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11537
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11537_DATA_W 32
+#define RFC_ULLRAM_BANK11537_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11537_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11538
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11538_DATA_W 32
+#define RFC_ULLRAM_BANK11538_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11538_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11539
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11539_DATA_W 32
+#define RFC_ULLRAM_BANK11539_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11539_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11540
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11540_DATA_W 32
+#define RFC_ULLRAM_BANK11540_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11540_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11541
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11541_DATA_W 32
+#define RFC_ULLRAM_BANK11541_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11541_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11542
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11542_DATA_W 32
+#define RFC_ULLRAM_BANK11542_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11542_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11543
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11543_DATA_W 32
+#define RFC_ULLRAM_BANK11543_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11543_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11544
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11544_DATA_W 32
+#define RFC_ULLRAM_BANK11544_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11544_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11545
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11545_DATA_W 32
+#define RFC_ULLRAM_BANK11545_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11545_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11546
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11546_DATA_W 32
+#define RFC_ULLRAM_BANK11546_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11546_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11547
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11547_DATA_W 32
+#define RFC_ULLRAM_BANK11547_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11547_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11548
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11548_DATA_W 32
+#define RFC_ULLRAM_BANK11548_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11548_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11549
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11549_DATA_W 32
+#define RFC_ULLRAM_BANK11549_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11549_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11550
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11550_DATA_W 32
+#define RFC_ULLRAM_BANK11550_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11550_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11551
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11551_DATA_W 32
+#define RFC_ULLRAM_BANK11551_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11551_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11552
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11552_DATA_W 32
+#define RFC_ULLRAM_BANK11552_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11552_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11553
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11553_DATA_W 32
+#define RFC_ULLRAM_BANK11553_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11553_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11554
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11554_DATA_W 32
+#define RFC_ULLRAM_BANK11554_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11554_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11555
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11555_DATA_W 32
+#define RFC_ULLRAM_BANK11555_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11555_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11556
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11556_DATA_W 32
+#define RFC_ULLRAM_BANK11556_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11556_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11557
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11557_DATA_W 32
+#define RFC_ULLRAM_BANK11557_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11557_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11558
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11558_DATA_W 32
+#define RFC_ULLRAM_BANK11558_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11558_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11559
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11559_DATA_W 32
+#define RFC_ULLRAM_BANK11559_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11559_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11560
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11560_DATA_W 32
+#define RFC_ULLRAM_BANK11560_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11560_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11561
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11561_DATA_W 32
+#define RFC_ULLRAM_BANK11561_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11561_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11562
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11562_DATA_W 32
+#define RFC_ULLRAM_BANK11562_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11562_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11563
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11563_DATA_W 32
+#define RFC_ULLRAM_BANK11563_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11563_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11564
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11564_DATA_W 32
+#define RFC_ULLRAM_BANK11564_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11564_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11565
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11565_DATA_W 32
+#define RFC_ULLRAM_BANK11565_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11565_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11566
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11566_DATA_W 32
+#define RFC_ULLRAM_BANK11566_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11566_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11567
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11567_DATA_W 32
+#define RFC_ULLRAM_BANK11567_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11567_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11568
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11568_DATA_W 32
+#define RFC_ULLRAM_BANK11568_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11568_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11569
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11569_DATA_W 32
+#define RFC_ULLRAM_BANK11569_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11569_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11570
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11570_DATA_W 32
+#define RFC_ULLRAM_BANK11570_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11570_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11571
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11571_DATA_W 32
+#define RFC_ULLRAM_BANK11571_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11571_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11572
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11572_DATA_W 32
+#define RFC_ULLRAM_BANK11572_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11572_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11573
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11573_DATA_W 32
+#define RFC_ULLRAM_BANK11573_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11573_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11574
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11574_DATA_W 32
+#define RFC_ULLRAM_BANK11574_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11574_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11575
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11575_DATA_W 32
+#define RFC_ULLRAM_BANK11575_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11575_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11576
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11576_DATA_W 32
+#define RFC_ULLRAM_BANK11576_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11576_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11577
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11577_DATA_W 32
+#define RFC_ULLRAM_BANK11577_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11577_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11578
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11578_DATA_W 32
+#define RFC_ULLRAM_BANK11578_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11578_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11579
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11579_DATA_W 32
+#define RFC_ULLRAM_BANK11579_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11579_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11580
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11580_DATA_W 32
+#define RFC_ULLRAM_BANK11580_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11580_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11581
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11581_DATA_W 32
+#define RFC_ULLRAM_BANK11581_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11581_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11582
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11582_DATA_W 32
+#define RFC_ULLRAM_BANK11582_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11582_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11583
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11583_DATA_W 32
+#define RFC_ULLRAM_BANK11583_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11583_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11584
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11584_DATA_W 32
+#define RFC_ULLRAM_BANK11584_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11584_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11585
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11585_DATA_W 32
+#define RFC_ULLRAM_BANK11585_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11585_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11586
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11586_DATA_W 32
+#define RFC_ULLRAM_BANK11586_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11586_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11587
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11587_DATA_W 32
+#define RFC_ULLRAM_BANK11587_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11587_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11588
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11588_DATA_W 32
+#define RFC_ULLRAM_BANK11588_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11588_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11589
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11589_DATA_W 32
+#define RFC_ULLRAM_BANK11589_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11589_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11590
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11590_DATA_W 32
+#define RFC_ULLRAM_BANK11590_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11590_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11591
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11591_DATA_W 32
+#define RFC_ULLRAM_BANK11591_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11591_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11592
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11592_DATA_W 32
+#define RFC_ULLRAM_BANK11592_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11592_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11593
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11593_DATA_W 32
+#define RFC_ULLRAM_BANK11593_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11593_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11594
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11594_DATA_W 32
+#define RFC_ULLRAM_BANK11594_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11594_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11595
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11595_DATA_W 32
+#define RFC_ULLRAM_BANK11595_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11595_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11596
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11596_DATA_W 32
+#define RFC_ULLRAM_BANK11596_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11596_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11597
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11597_DATA_W 32
+#define RFC_ULLRAM_BANK11597_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11597_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11598
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11598_DATA_W 32
+#define RFC_ULLRAM_BANK11598_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11598_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11599
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11599_DATA_W 32
+#define RFC_ULLRAM_BANK11599_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11599_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11600
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11600_DATA_W 32
+#define RFC_ULLRAM_BANK11600_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11600_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11601
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11601_DATA_W 32
+#define RFC_ULLRAM_BANK11601_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11601_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11602
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11602_DATA_W 32
+#define RFC_ULLRAM_BANK11602_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11602_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11603
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11603_DATA_W 32
+#define RFC_ULLRAM_BANK11603_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11603_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11604
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11604_DATA_W 32
+#define RFC_ULLRAM_BANK11604_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11604_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11605
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11605_DATA_W 32
+#define RFC_ULLRAM_BANK11605_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11605_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11606
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11606_DATA_W 32
+#define RFC_ULLRAM_BANK11606_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11606_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11607
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11607_DATA_W 32
+#define RFC_ULLRAM_BANK11607_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11607_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11608
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11608_DATA_W 32
+#define RFC_ULLRAM_BANK11608_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11608_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11609
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11609_DATA_W 32
+#define RFC_ULLRAM_BANK11609_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11609_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11610
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11610_DATA_W 32
+#define RFC_ULLRAM_BANK11610_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11610_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11611
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11611_DATA_W 32
+#define RFC_ULLRAM_BANK11611_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11611_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11612
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11612_DATA_W 32
+#define RFC_ULLRAM_BANK11612_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11612_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11613
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11613_DATA_W 32
+#define RFC_ULLRAM_BANK11613_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11613_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11614
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11614_DATA_W 32
+#define RFC_ULLRAM_BANK11614_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11614_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11615
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11615_DATA_W 32
+#define RFC_ULLRAM_BANK11615_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11615_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11616
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11616_DATA_W 32
+#define RFC_ULLRAM_BANK11616_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11616_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11617
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11617_DATA_W 32
+#define RFC_ULLRAM_BANK11617_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11617_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11618
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11618_DATA_W 32
+#define RFC_ULLRAM_BANK11618_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11618_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11619
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11619_DATA_W 32
+#define RFC_ULLRAM_BANK11619_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11619_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11620
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11620_DATA_W 32
+#define RFC_ULLRAM_BANK11620_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11620_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11621
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11621_DATA_W 32
+#define RFC_ULLRAM_BANK11621_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11621_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11622
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11622_DATA_W 32
+#define RFC_ULLRAM_BANK11622_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11622_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11623
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11623_DATA_W 32
+#define RFC_ULLRAM_BANK11623_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11623_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11624
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11624_DATA_W 32
+#define RFC_ULLRAM_BANK11624_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11624_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11625
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11625_DATA_W 32
+#define RFC_ULLRAM_BANK11625_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11625_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11626
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11626_DATA_W 32
+#define RFC_ULLRAM_BANK11626_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11626_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11627
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11627_DATA_W 32
+#define RFC_ULLRAM_BANK11627_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11627_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11628
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11628_DATA_W 32
+#define RFC_ULLRAM_BANK11628_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11628_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11629
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11629_DATA_W 32
+#define RFC_ULLRAM_BANK11629_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11629_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11630
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11630_DATA_W 32
+#define RFC_ULLRAM_BANK11630_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11630_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11631
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11631_DATA_W 32
+#define RFC_ULLRAM_BANK11631_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11631_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11632
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11632_DATA_W 32
+#define RFC_ULLRAM_BANK11632_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11632_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11633
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11633_DATA_W 32
+#define RFC_ULLRAM_BANK11633_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11633_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11634
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11634_DATA_W 32
+#define RFC_ULLRAM_BANK11634_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11634_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11635
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11635_DATA_W 32
+#define RFC_ULLRAM_BANK11635_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11635_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11636
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11636_DATA_W 32
+#define RFC_ULLRAM_BANK11636_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11636_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11637
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11637_DATA_W 32
+#define RFC_ULLRAM_BANK11637_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11637_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11638
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11638_DATA_W 32
+#define RFC_ULLRAM_BANK11638_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11638_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11639
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11639_DATA_W 32
+#define RFC_ULLRAM_BANK11639_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11639_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11640
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11640_DATA_W 32
+#define RFC_ULLRAM_BANK11640_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11640_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11641
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11641_DATA_W 32
+#define RFC_ULLRAM_BANK11641_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11641_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11642
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11642_DATA_W 32
+#define RFC_ULLRAM_BANK11642_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11642_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11643
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11643_DATA_W 32
+#define RFC_ULLRAM_BANK11643_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11643_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11644
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11644_DATA_W 32
+#define RFC_ULLRAM_BANK11644_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11644_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11645
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11645_DATA_W 32
+#define RFC_ULLRAM_BANK11645_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11645_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11646
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11646_DATA_W 32
+#define RFC_ULLRAM_BANK11646_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11646_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11647
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11647_DATA_W 32
+#define RFC_ULLRAM_BANK11647_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11647_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11648
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11648_DATA_W 32
+#define RFC_ULLRAM_BANK11648_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11648_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11649
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11649_DATA_W 32
+#define RFC_ULLRAM_BANK11649_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11649_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11650
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11650_DATA_W 32
+#define RFC_ULLRAM_BANK11650_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11650_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11651
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11651_DATA_W 32
+#define RFC_ULLRAM_BANK11651_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11651_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11652
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11652_DATA_W 32
+#define RFC_ULLRAM_BANK11652_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11652_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11653
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11653_DATA_W 32
+#define RFC_ULLRAM_BANK11653_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11653_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11654
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11654_DATA_W 32
+#define RFC_ULLRAM_BANK11654_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11654_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11655
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11655_DATA_W 32
+#define RFC_ULLRAM_BANK11655_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11655_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11656
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11656_DATA_W 32
+#define RFC_ULLRAM_BANK11656_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11656_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11657
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11657_DATA_W 32
+#define RFC_ULLRAM_BANK11657_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11657_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11658
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11658_DATA_W 32
+#define RFC_ULLRAM_BANK11658_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11658_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11659
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11659_DATA_W 32
+#define RFC_ULLRAM_BANK11659_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11659_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11660
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11660_DATA_W 32
+#define RFC_ULLRAM_BANK11660_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11660_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11661
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11661_DATA_W 32
+#define RFC_ULLRAM_BANK11661_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11661_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11662
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11662_DATA_W 32
+#define RFC_ULLRAM_BANK11662_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11662_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11663
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11663_DATA_W 32
+#define RFC_ULLRAM_BANK11663_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11663_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11664
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11664_DATA_W 32
+#define RFC_ULLRAM_BANK11664_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11664_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11665
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11665_DATA_W 32
+#define RFC_ULLRAM_BANK11665_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11665_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11666
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11666_DATA_W 32
+#define RFC_ULLRAM_BANK11666_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11666_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11667
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11667_DATA_W 32
+#define RFC_ULLRAM_BANK11667_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11667_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11668
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11668_DATA_W 32
+#define RFC_ULLRAM_BANK11668_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11668_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11669
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11669_DATA_W 32
+#define RFC_ULLRAM_BANK11669_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11669_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11670
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11670_DATA_W 32
+#define RFC_ULLRAM_BANK11670_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11670_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11671
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11671_DATA_W 32
+#define RFC_ULLRAM_BANK11671_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11671_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11672
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11672_DATA_W 32
+#define RFC_ULLRAM_BANK11672_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11672_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11673
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11673_DATA_W 32
+#define RFC_ULLRAM_BANK11673_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11673_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11674
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11674_DATA_W 32
+#define RFC_ULLRAM_BANK11674_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11674_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11675
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11675_DATA_W 32
+#define RFC_ULLRAM_BANK11675_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11675_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11676
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11676_DATA_W 32
+#define RFC_ULLRAM_BANK11676_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11676_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11677
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11677_DATA_W 32
+#define RFC_ULLRAM_BANK11677_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11677_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11678
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11678_DATA_W 32
+#define RFC_ULLRAM_BANK11678_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11678_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11679
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11679_DATA_W 32
+#define RFC_ULLRAM_BANK11679_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11679_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11680
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11680_DATA_W 32
+#define RFC_ULLRAM_BANK11680_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11680_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11681
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11681_DATA_W 32
+#define RFC_ULLRAM_BANK11681_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11681_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11682
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11682_DATA_W 32
+#define RFC_ULLRAM_BANK11682_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11682_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11683
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11683_DATA_W 32
+#define RFC_ULLRAM_BANK11683_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11683_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11684
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11684_DATA_W 32
+#define RFC_ULLRAM_BANK11684_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11684_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11685
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11685_DATA_W 32
+#define RFC_ULLRAM_BANK11685_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11685_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11686
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11686_DATA_W 32
+#define RFC_ULLRAM_BANK11686_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11686_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11687
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11687_DATA_W 32
+#define RFC_ULLRAM_BANK11687_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11687_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11688
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11688_DATA_W 32
+#define RFC_ULLRAM_BANK11688_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11688_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11689
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11689_DATA_W 32
+#define RFC_ULLRAM_BANK11689_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11689_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11690
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11690_DATA_W 32
+#define RFC_ULLRAM_BANK11690_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11690_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11691
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11691_DATA_W 32
+#define RFC_ULLRAM_BANK11691_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11691_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11692
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11692_DATA_W 32
+#define RFC_ULLRAM_BANK11692_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11692_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11693
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11693_DATA_W 32
+#define RFC_ULLRAM_BANK11693_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11693_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11694
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11694_DATA_W 32
+#define RFC_ULLRAM_BANK11694_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11694_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11695
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11695_DATA_W 32
+#define RFC_ULLRAM_BANK11695_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11695_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11696
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11696_DATA_W 32
+#define RFC_ULLRAM_BANK11696_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11696_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11697
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11697_DATA_W 32
+#define RFC_ULLRAM_BANK11697_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11697_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11698
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11698_DATA_W 32
+#define RFC_ULLRAM_BANK11698_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11698_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11699
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11699_DATA_W 32
+#define RFC_ULLRAM_BANK11699_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11699_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11700
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11700_DATA_W 32
+#define RFC_ULLRAM_BANK11700_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11700_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11701
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11701_DATA_W 32
+#define RFC_ULLRAM_BANK11701_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11701_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11702
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11702_DATA_W 32
+#define RFC_ULLRAM_BANK11702_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11702_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11703
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11703_DATA_W 32
+#define RFC_ULLRAM_BANK11703_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11703_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11704
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11704_DATA_W 32
+#define RFC_ULLRAM_BANK11704_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11704_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11705
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11705_DATA_W 32
+#define RFC_ULLRAM_BANK11705_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11705_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11706
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11706_DATA_W 32
+#define RFC_ULLRAM_BANK11706_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11706_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11707
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11707_DATA_W 32
+#define RFC_ULLRAM_BANK11707_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11707_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11708
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11708_DATA_W 32
+#define RFC_ULLRAM_BANK11708_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11708_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11709
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11709_DATA_W 32
+#define RFC_ULLRAM_BANK11709_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11709_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11710
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11710_DATA_W 32
+#define RFC_ULLRAM_BANK11710_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11710_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11711
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11711_DATA_W 32
+#define RFC_ULLRAM_BANK11711_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11711_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11712
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11712_DATA_W 32
+#define RFC_ULLRAM_BANK11712_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11712_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11713
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11713_DATA_W 32
+#define RFC_ULLRAM_BANK11713_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11713_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11714
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11714_DATA_W 32
+#define RFC_ULLRAM_BANK11714_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11714_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11715
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11715_DATA_W 32
+#define RFC_ULLRAM_BANK11715_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11715_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11716
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11716_DATA_W 32
+#define RFC_ULLRAM_BANK11716_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11716_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11717
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11717_DATA_W 32
+#define RFC_ULLRAM_BANK11717_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11717_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11718
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11718_DATA_W 32
+#define RFC_ULLRAM_BANK11718_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11718_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11719
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11719_DATA_W 32
+#define RFC_ULLRAM_BANK11719_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11719_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11720
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11720_DATA_W 32
+#define RFC_ULLRAM_BANK11720_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11720_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11721
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11721_DATA_W 32
+#define RFC_ULLRAM_BANK11721_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11721_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11722
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11722_DATA_W 32
+#define RFC_ULLRAM_BANK11722_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11722_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11723
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11723_DATA_W 32
+#define RFC_ULLRAM_BANK11723_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11723_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11724
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11724_DATA_W 32
+#define RFC_ULLRAM_BANK11724_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11724_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11725
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11725_DATA_W 32
+#define RFC_ULLRAM_BANK11725_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11725_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11726
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11726_DATA_W 32
+#define RFC_ULLRAM_BANK11726_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11726_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11727
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11727_DATA_W 32
+#define RFC_ULLRAM_BANK11727_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11727_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11728
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11728_DATA_W 32
+#define RFC_ULLRAM_BANK11728_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11728_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11729
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11729_DATA_W 32
+#define RFC_ULLRAM_BANK11729_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11729_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11730
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11730_DATA_W 32
+#define RFC_ULLRAM_BANK11730_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11730_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11731
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11731_DATA_W 32
+#define RFC_ULLRAM_BANK11731_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11731_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11732
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11732_DATA_W 32
+#define RFC_ULLRAM_BANK11732_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11732_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11733
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11733_DATA_W 32
+#define RFC_ULLRAM_BANK11733_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11733_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11734
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11734_DATA_W 32
+#define RFC_ULLRAM_BANK11734_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11734_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11735
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11735_DATA_W 32
+#define RFC_ULLRAM_BANK11735_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11735_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11736
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11736_DATA_W 32
+#define RFC_ULLRAM_BANK11736_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11736_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11737
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11737_DATA_W 32
+#define RFC_ULLRAM_BANK11737_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11737_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11738
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11738_DATA_W 32
+#define RFC_ULLRAM_BANK11738_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11738_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11739
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11739_DATA_W 32
+#define RFC_ULLRAM_BANK11739_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11739_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11740
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11740_DATA_W 32
+#define RFC_ULLRAM_BANK11740_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11740_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11741
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11741_DATA_W 32
+#define RFC_ULLRAM_BANK11741_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11741_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11742
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11742_DATA_W 32
+#define RFC_ULLRAM_BANK11742_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11742_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11743
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11743_DATA_W 32
+#define RFC_ULLRAM_BANK11743_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11743_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11744
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11744_DATA_W 32
+#define RFC_ULLRAM_BANK11744_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11744_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11745
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11745_DATA_W 32
+#define RFC_ULLRAM_BANK11745_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11745_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11746
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11746_DATA_W 32
+#define RFC_ULLRAM_BANK11746_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11746_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11747
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11747_DATA_W 32
+#define RFC_ULLRAM_BANK11747_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11747_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11748
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11748_DATA_W 32
+#define RFC_ULLRAM_BANK11748_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11748_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11749
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11749_DATA_W 32
+#define RFC_ULLRAM_BANK11749_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11749_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11750
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11750_DATA_W 32
+#define RFC_ULLRAM_BANK11750_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11750_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11751
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11751_DATA_W 32
+#define RFC_ULLRAM_BANK11751_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11751_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11752
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11752_DATA_W 32
+#define RFC_ULLRAM_BANK11752_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11752_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11753
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11753_DATA_W 32
+#define RFC_ULLRAM_BANK11753_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11753_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11754
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11754_DATA_W 32
+#define RFC_ULLRAM_BANK11754_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11754_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11755
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11755_DATA_W 32
+#define RFC_ULLRAM_BANK11755_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11755_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11756
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11756_DATA_W 32
+#define RFC_ULLRAM_BANK11756_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11756_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11757
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11757_DATA_W 32
+#define RFC_ULLRAM_BANK11757_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11757_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11758
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11758_DATA_W 32
+#define RFC_ULLRAM_BANK11758_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11758_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11759
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11759_DATA_W 32
+#define RFC_ULLRAM_BANK11759_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11759_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11760
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11760_DATA_W 32
+#define RFC_ULLRAM_BANK11760_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11760_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11761
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11761_DATA_W 32
+#define RFC_ULLRAM_BANK11761_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11761_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11762
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11762_DATA_W 32
+#define RFC_ULLRAM_BANK11762_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11762_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11763
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11763_DATA_W 32
+#define RFC_ULLRAM_BANK11763_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11763_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11764
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11764_DATA_W 32
+#define RFC_ULLRAM_BANK11764_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11764_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11765
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11765_DATA_W 32
+#define RFC_ULLRAM_BANK11765_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11765_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11766
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11766_DATA_W 32
+#define RFC_ULLRAM_BANK11766_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11766_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11767
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11767_DATA_W 32
+#define RFC_ULLRAM_BANK11767_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11767_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11768
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11768_DATA_W 32
+#define RFC_ULLRAM_BANK11768_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11768_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11769
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11769_DATA_W 32
+#define RFC_ULLRAM_BANK11769_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11769_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11770
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11770_DATA_W 32
+#define RFC_ULLRAM_BANK11770_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11770_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11771
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11771_DATA_W 32
+#define RFC_ULLRAM_BANK11771_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11771_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11772
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11772_DATA_W 32
+#define RFC_ULLRAM_BANK11772_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11772_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11773
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11773_DATA_W 32
+#define RFC_ULLRAM_BANK11773_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11773_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11774
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11774_DATA_W 32
+#define RFC_ULLRAM_BANK11774_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11774_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11775
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11775_DATA_W 32
+#define RFC_ULLRAM_BANK11775_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11775_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11776
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11776_DATA_W 32
+#define RFC_ULLRAM_BANK11776_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11776_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11777
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11777_DATA_W 32
+#define RFC_ULLRAM_BANK11777_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11777_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11778
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11778_DATA_W 32
+#define RFC_ULLRAM_BANK11778_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11778_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11779
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11779_DATA_W 32
+#define RFC_ULLRAM_BANK11779_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11779_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11780
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11780_DATA_W 32
+#define RFC_ULLRAM_BANK11780_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11780_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11781
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11781_DATA_W 32
+#define RFC_ULLRAM_BANK11781_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11781_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11782
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11782_DATA_W 32
+#define RFC_ULLRAM_BANK11782_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11782_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11783
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11783_DATA_W 32
+#define RFC_ULLRAM_BANK11783_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11783_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11784
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11784_DATA_W 32
+#define RFC_ULLRAM_BANK11784_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11784_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11785
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11785_DATA_W 32
+#define RFC_ULLRAM_BANK11785_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11785_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11786
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11786_DATA_W 32
+#define RFC_ULLRAM_BANK11786_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11786_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11787
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11787_DATA_W 32
+#define RFC_ULLRAM_BANK11787_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11787_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11788
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11788_DATA_W 32
+#define RFC_ULLRAM_BANK11788_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11788_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11789
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11789_DATA_W 32
+#define RFC_ULLRAM_BANK11789_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11789_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11790
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11790_DATA_W 32
+#define RFC_ULLRAM_BANK11790_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11790_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11791
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11791_DATA_W 32
+#define RFC_ULLRAM_BANK11791_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11791_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11792
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11792_DATA_W 32
+#define RFC_ULLRAM_BANK11792_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11792_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11793
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11793_DATA_W 32
+#define RFC_ULLRAM_BANK11793_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11793_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11794
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11794_DATA_W 32
+#define RFC_ULLRAM_BANK11794_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11794_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11795
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11795_DATA_W 32
+#define RFC_ULLRAM_BANK11795_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11795_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11796
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11796_DATA_W 32
+#define RFC_ULLRAM_BANK11796_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11796_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11797
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11797_DATA_W 32
+#define RFC_ULLRAM_BANK11797_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11797_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11798
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11798_DATA_W 32
+#define RFC_ULLRAM_BANK11798_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11798_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11799
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11799_DATA_W 32
+#define RFC_ULLRAM_BANK11799_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11799_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11800
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11800_DATA_W 32
+#define RFC_ULLRAM_BANK11800_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11800_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11801
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11801_DATA_W 32
+#define RFC_ULLRAM_BANK11801_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11801_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11802
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11802_DATA_W 32
+#define RFC_ULLRAM_BANK11802_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11802_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11803
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11803_DATA_W 32
+#define RFC_ULLRAM_BANK11803_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11803_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11804
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11804_DATA_W 32
+#define RFC_ULLRAM_BANK11804_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11804_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11805
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11805_DATA_W 32
+#define RFC_ULLRAM_BANK11805_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11805_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11806
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11806_DATA_W 32
+#define RFC_ULLRAM_BANK11806_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11806_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11807
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11807_DATA_W 32
+#define RFC_ULLRAM_BANK11807_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11807_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11808
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11808_DATA_W 32
+#define RFC_ULLRAM_BANK11808_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11808_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11809
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11809_DATA_W 32
+#define RFC_ULLRAM_BANK11809_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11809_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11810
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11810_DATA_W 32
+#define RFC_ULLRAM_BANK11810_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11810_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11811
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11811_DATA_W 32
+#define RFC_ULLRAM_BANK11811_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11811_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11812
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11812_DATA_W 32
+#define RFC_ULLRAM_BANK11812_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11812_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11813
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11813_DATA_W 32
+#define RFC_ULLRAM_BANK11813_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11813_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11814
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11814_DATA_W 32
+#define RFC_ULLRAM_BANK11814_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11814_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11815
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11815_DATA_W 32
+#define RFC_ULLRAM_BANK11815_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11815_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11816
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11816_DATA_W 32
+#define RFC_ULLRAM_BANK11816_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11816_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11817
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11817_DATA_W 32
+#define RFC_ULLRAM_BANK11817_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11817_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11818
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11818_DATA_W 32
+#define RFC_ULLRAM_BANK11818_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11818_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11819
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11819_DATA_W 32
+#define RFC_ULLRAM_BANK11819_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11819_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11820
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11820_DATA_W 32
+#define RFC_ULLRAM_BANK11820_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11820_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11821
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11821_DATA_W 32
+#define RFC_ULLRAM_BANK11821_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11821_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11822
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11822_DATA_W 32
+#define RFC_ULLRAM_BANK11822_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11822_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11823
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11823_DATA_W 32
+#define RFC_ULLRAM_BANK11823_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11823_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11824
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11824_DATA_W 32
+#define RFC_ULLRAM_BANK11824_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11824_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11825
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11825_DATA_W 32
+#define RFC_ULLRAM_BANK11825_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11825_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11826
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11826_DATA_W 32
+#define RFC_ULLRAM_BANK11826_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11826_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11827
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11827_DATA_W 32
+#define RFC_ULLRAM_BANK11827_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11827_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11828
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11828_DATA_W 32
+#define RFC_ULLRAM_BANK11828_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11828_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11829
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11829_DATA_W 32
+#define RFC_ULLRAM_BANK11829_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11829_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11830
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11830_DATA_W 32
+#define RFC_ULLRAM_BANK11830_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11830_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11831
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11831_DATA_W 32
+#define RFC_ULLRAM_BANK11831_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11831_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11832
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11832_DATA_W 32
+#define RFC_ULLRAM_BANK11832_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11832_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11833
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11833_DATA_W 32
+#define RFC_ULLRAM_BANK11833_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11833_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11834
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11834_DATA_W 32
+#define RFC_ULLRAM_BANK11834_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11834_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11835
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11835_DATA_W 32
+#define RFC_ULLRAM_BANK11835_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11835_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11836
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11836_DATA_W 32
+#define RFC_ULLRAM_BANK11836_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11836_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11837
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11837_DATA_W 32
+#define RFC_ULLRAM_BANK11837_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11837_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11838
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11838_DATA_W 32
+#define RFC_ULLRAM_BANK11838_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11838_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11839
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11839_DATA_W 32
+#define RFC_ULLRAM_BANK11839_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11839_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11840
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11840_DATA_W 32
+#define RFC_ULLRAM_BANK11840_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11840_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11841
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11841_DATA_W 32
+#define RFC_ULLRAM_BANK11841_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11841_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11842
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11842_DATA_W 32
+#define RFC_ULLRAM_BANK11842_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11842_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11843
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11843_DATA_W 32
+#define RFC_ULLRAM_BANK11843_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11843_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11844
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11844_DATA_W 32
+#define RFC_ULLRAM_BANK11844_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11844_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11845
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11845_DATA_W 32
+#define RFC_ULLRAM_BANK11845_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11845_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11846
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11846_DATA_W 32
+#define RFC_ULLRAM_BANK11846_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11846_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11847
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11847_DATA_W 32
+#define RFC_ULLRAM_BANK11847_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11847_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11848
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11848_DATA_W 32
+#define RFC_ULLRAM_BANK11848_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11848_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11849
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11849_DATA_W 32
+#define RFC_ULLRAM_BANK11849_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11849_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11850
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11850_DATA_W 32
+#define RFC_ULLRAM_BANK11850_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11850_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11851
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11851_DATA_W 32
+#define RFC_ULLRAM_BANK11851_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11851_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11852
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11852_DATA_W 32
+#define RFC_ULLRAM_BANK11852_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11852_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11853
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11853_DATA_W 32
+#define RFC_ULLRAM_BANK11853_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11853_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11854
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11854_DATA_W 32
+#define RFC_ULLRAM_BANK11854_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11854_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11855
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11855_DATA_W 32
+#define RFC_ULLRAM_BANK11855_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11855_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11856
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11856_DATA_W 32
+#define RFC_ULLRAM_BANK11856_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11856_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11857
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11857_DATA_W 32
+#define RFC_ULLRAM_BANK11857_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11857_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11858
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11858_DATA_W 32
+#define RFC_ULLRAM_BANK11858_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11858_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11859
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11859_DATA_W 32
+#define RFC_ULLRAM_BANK11859_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11859_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11860
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11860_DATA_W 32
+#define RFC_ULLRAM_BANK11860_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11860_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11861
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11861_DATA_W 32
+#define RFC_ULLRAM_BANK11861_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11861_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11862
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11862_DATA_W 32
+#define RFC_ULLRAM_BANK11862_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11862_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11863
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11863_DATA_W 32
+#define RFC_ULLRAM_BANK11863_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11863_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11864
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11864_DATA_W 32
+#define RFC_ULLRAM_BANK11864_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11864_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11865
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11865_DATA_W 32
+#define RFC_ULLRAM_BANK11865_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11865_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11866
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11866_DATA_W 32
+#define RFC_ULLRAM_BANK11866_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11866_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11867
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11867_DATA_W 32
+#define RFC_ULLRAM_BANK11867_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11867_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11868
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11868_DATA_W 32
+#define RFC_ULLRAM_BANK11868_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11868_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11869
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11869_DATA_W 32
+#define RFC_ULLRAM_BANK11869_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11869_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11870
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11870_DATA_W 32
+#define RFC_ULLRAM_BANK11870_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11870_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11871
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11871_DATA_W 32
+#define RFC_ULLRAM_BANK11871_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11871_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11872
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11872_DATA_W 32
+#define RFC_ULLRAM_BANK11872_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11872_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11873
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11873_DATA_W 32
+#define RFC_ULLRAM_BANK11873_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11873_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11874
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11874_DATA_W 32
+#define RFC_ULLRAM_BANK11874_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11874_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11875
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11875_DATA_W 32
+#define RFC_ULLRAM_BANK11875_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11875_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11876
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11876_DATA_W 32
+#define RFC_ULLRAM_BANK11876_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11876_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11877
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11877_DATA_W 32
+#define RFC_ULLRAM_BANK11877_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11877_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11878
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11878_DATA_W 32
+#define RFC_ULLRAM_BANK11878_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11878_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11879
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11879_DATA_W 32
+#define RFC_ULLRAM_BANK11879_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11879_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11880
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11880_DATA_W 32
+#define RFC_ULLRAM_BANK11880_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11880_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11881
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11881_DATA_W 32
+#define RFC_ULLRAM_BANK11881_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11881_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11882
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11882_DATA_W 32
+#define RFC_ULLRAM_BANK11882_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11882_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11883
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11883_DATA_W 32
+#define RFC_ULLRAM_BANK11883_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11883_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11884
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11884_DATA_W 32
+#define RFC_ULLRAM_BANK11884_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11884_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11885
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11885_DATA_W 32
+#define RFC_ULLRAM_BANK11885_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11885_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11886
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11886_DATA_W 32
+#define RFC_ULLRAM_BANK11886_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11886_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11887
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11887_DATA_W 32
+#define RFC_ULLRAM_BANK11887_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11887_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11888
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11888_DATA_W 32
+#define RFC_ULLRAM_BANK11888_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11888_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11889
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11889_DATA_W 32
+#define RFC_ULLRAM_BANK11889_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11889_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11890
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11890_DATA_W 32
+#define RFC_ULLRAM_BANK11890_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11890_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11891
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11891_DATA_W 32
+#define RFC_ULLRAM_BANK11891_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11891_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11892
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11892_DATA_W 32
+#define RFC_ULLRAM_BANK11892_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11892_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11893
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11893_DATA_W 32
+#define RFC_ULLRAM_BANK11893_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11893_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11894
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11894_DATA_W 32
+#define RFC_ULLRAM_BANK11894_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11894_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11895
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11895_DATA_W 32
+#define RFC_ULLRAM_BANK11895_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11895_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11896
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11896_DATA_W 32
+#define RFC_ULLRAM_BANK11896_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11896_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11897
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11897_DATA_W 32
+#define RFC_ULLRAM_BANK11897_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11897_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11898
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11898_DATA_W 32
+#define RFC_ULLRAM_BANK11898_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11898_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11899
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11899_DATA_W 32
+#define RFC_ULLRAM_BANK11899_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11899_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11900
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11900_DATA_W 32
+#define RFC_ULLRAM_BANK11900_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11900_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11901
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11901_DATA_W 32
+#define RFC_ULLRAM_BANK11901_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11901_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11902
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11902_DATA_W 32
+#define RFC_ULLRAM_BANK11902_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11902_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11903
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11903_DATA_W 32
+#define RFC_ULLRAM_BANK11903_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11903_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11904
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11904_DATA_W 32
+#define RFC_ULLRAM_BANK11904_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11904_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11905
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11905_DATA_W 32
+#define RFC_ULLRAM_BANK11905_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11905_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11906
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11906_DATA_W 32
+#define RFC_ULLRAM_BANK11906_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11906_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11907
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11907_DATA_W 32
+#define RFC_ULLRAM_BANK11907_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11907_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11908
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11908_DATA_W 32
+#define RFC_ULLRAM_BANK11908_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11908_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11909
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11909_DATA_W 32
+#define RFC_ULLRAM_BANK11909_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11909_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11910
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11910_DATA_W 32
+#define RFC_ULLRAM_BANK11910_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11910_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11911
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11911_DATA_W 32
+#define RFC_ULLRAM_BANK11911_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11911_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11912
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11912_DATA_W 32
+#define RFC_ULLRAM_BANK11912_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11912_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11913
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11913_DATA_W 32
+#define RFC_ULLRAM_BANK11913_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11913_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11914
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11914_DATA_W 32
+#define RFC_ULLRAM_BANK11914_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11914_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11915
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11915_DATA_W 32
+#define RFC_ULLRAM_BANK11915_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11915_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11916
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11916_DATA_W 32
+#define RFC_ULLRAM_BANK11916_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11916_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11917
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11917_DATA_W 32
+#define RFC_ULLRAM_BANK11917_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11917_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11918
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11918_DATA_W 32
+#define RFC_ULLRAM_BANK11918_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11918_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11919
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11919_DATA_W 32
+#define RFC_ULLRAM_BANK11919_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11919_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11920
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11920_DATA_W 32
+#define RFC_ULLRAM_BANK11920_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11920_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11921
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11921_DATA_W 32
+#define RFC_ULLRAM_BANK11921_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11921_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11922
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11922_DATA_W 32
+#define RFC_ULLRAM_BANK11922_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11922_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11923
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11923_DATA_W 32
+#define RFC_ULLRAM_BANK11923_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11923_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11924
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11924_DATA_W 32
+#define RFC_ULLRAM_BANK11924_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11924_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11925
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11925_DATA_W 32
+#define RFC_ULLRAM_BANK11925_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11925_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11926
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11926_DATA_W 32
+#define RFC_ULLRAM_BANK11926_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11926_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11927
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11927_DATA_W 32
+#define RFC_ULLRAM_BANK11927_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11927_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11928
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11928_DATA_W 32
+#define RFC_ULLRAM_BANK11928_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11928_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11929
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11929_DATA_W 32
+#define RFC_ULLRAM_BANK11929_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11929_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11930
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11930_DATA_W 32
+#define RFC_ULLRAM_BANK11930_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11930_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11931
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11931_DATA_W 32
+#define RFC_ULLRAM_BANK11931_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11931_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11932
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11932_DATA_W 32
+#define RFC_ULLRAM_BANK11932_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11932_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11933
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11933_DATA_W 32
+#define RFC_ULLRAM_BANK11933_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11933_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11934
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11934_DATA_W 32
+#define RFC_ULLRAM_BANK11934_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11934_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11935
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11935_DATA_W 32
+#define RFC_ULLRAM_BANK11935_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11935_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11936
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11936_DATA_W 32
+#define RFC_ULLRAM_BANK11936_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11936_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11937
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11937_DATA_W 32
+#define RFC_ULLRAM_BANK11937_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11937_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11938
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11938_DATA_W 32
+#define RFC_ULLRAM_BANK11938_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11938_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11939
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11939_DATA_W 32
+#define RFC_ULLRAM_BANK11939_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11939_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11940
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11940_DATA_W 32
+#define RFC_ULLRAM_BANK11940_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11940_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11941
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11941_DATA_W 32
+#define RFC_ULLRAM_BANK11941_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11941_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11942
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11942_DATA_W 32
+#define RFC_ULLRAM_BANK11942_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11942_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11943
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11943_DATA_W 32
+#define RFC_ULLRAM_BANK11943_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11943_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11944
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11944_DATA_W 32
+#define RFC_ULLRAM_BANK11944_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11944_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11945
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11945_DATA_W 32
+#define RFC_ULLRAM_BANK11945_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11945_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11946
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11946_DATA_W 32
+#define RFC_ULLRAM_BANK11946_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11946_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11947
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11947_DATA_W 32
+#define RFC_ULLRAM_BANK11947_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11947_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11948
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11948_DATA_W 32
+#define RFC_ULLRAM_BANK11948_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11948_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11949
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11949_DATA_W 32
+#define RFC_ULLRAM_BANK11949_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11949_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11950
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11950_DATA_W 32
+#define RFC_ULLRAM_BANK11950_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11950_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11951
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11951_DATA_W 32
+#define RFC_ULLRAM_BANK11951_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11951_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11952
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11952_DATA_W 32
+#define RFC_ULLRAM_BANK11952_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11952_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11953
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11953_DATA_W 32
+#define RFC_ULLRAM_BANK11953_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11953_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11954
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11954_DATA_W 32
+#define RFC_ULLRAM_BANK11954_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11954_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11955
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11955_DATA_W 32
+#define RFC_ULLRAM_BANK11955_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11955_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11956
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11956_DATA_W 32
+#define RFC_ULLRAM_BANK11956_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11956_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11957
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11957_DATA_W 32
+#define RFC_ULLRAM_BANK11957_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11957_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11958
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11958_DATA_W 32
+#define RFC_ULLRAM_BANK11958_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11958_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11959
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11959_DATA_W 32
+#define RFC_ULLRAM_BANK11959_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11959_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11960
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11960_DATA_W 32
+#define RFC_ULLRAM_BANK11960_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11960_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11961
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11961_DATA_W 32
+#define RFC_ULLRAM_BANK11961_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11961_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11962
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11962_DATA_W 32
+#define RFC_ULLRAM_BANK11962_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11962_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11963
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11963_DATA_W 32
+#define RFC_ULLRAM_BANK11963_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11963_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11964
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11964_DATA_W 32
+#define RFC_ULLRAM_BANK11964_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11964_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11965
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11965_DATA_W 32
+#define RFC_ULLRAM_BANK11965_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11965_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11966
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11966_DATA_W 32
+#define RFC_ULLRAM_BANK11966_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11966_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11967
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11967_DATA_W 32
+#define RFC_ULLRAM_BANK11967_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11967_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11968
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11968_DATA_W 32
+#define RFC_ULLRAM_BANK11968_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11968_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11969
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11969_DATA_W 32
+#define RFC_ULLRAM_BANK11969_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11969_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11970
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11970_DATA_W 32
+#define RFC_ULLRAM_BANK11970_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11970_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11971
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11971_DATA_W 32
+#define RFC_ULLRAM_BANK11971_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11971_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11972
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11972_DATA_W 32
+#define RFC_ULLRAM_BANK11972_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11972_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11973
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11973_DATA_W 32
+#define RFC_ULLRAM_BANK11973_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11973_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11974
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11974_DATA_W 32
+#define RFC_ULLRAM_BANK11974_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11974_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11975
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11975_DATA_W 32
+#define RFC_ULLRAM_BANK11975_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11975_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11976
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11976_DATA_W 32
+#define RFC_ULLRAM_BANK11976_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11976_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11977
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11977_DATA_W 32
+#define RFC_ULLRAM_BANK11977_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11977_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11978
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11978_DATA_W 32
+#define RFC_ULLRAM_BANK11978_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11978_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11979
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11979_DATA_W 32
+#define RFC_ULLRAM_BANK11979_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11979_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11980
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11980_DATA_W 32
+#define RFC_ULLRAM_BANK11980_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11980_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11981
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11981_DATA_W 32
+#define RFC_ULLRAM_BANK11981_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11981_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11982
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11982_DATA_W 32
+#define RFC_ULLRAM_BANK11982_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11982_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11983
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11983_DATA_W 32
+#define RFC_ULLRAM_BANK11983_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11983_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11984
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11984_DATA_W 32
+#define RFC_ULLRAM_BANK11984_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11984_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11985
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11985_DATA_W 32
+#define RFC_ULLRAM_BANK11985_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11985_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11986
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11986_DATA_W 32
+#define RFC_ULLRAM_BANK11986_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11986_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11987
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11987_DATA_W 32
+#define RFC_ULLRAM_BANK11987_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11987_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11988
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11988_DATA_W 32
+#define RFC_ULLRAM_BANK11988_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11988_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11989
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11989_DATA_W 32
+#define RFC_ULLRAM_BANK11989_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11989_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11990
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11990_DATA_W 32
+#define RFC_ULLRAM_BANK11990_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11990_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11991
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11991_DATA_W 32
+#define RFC_ULLRAM_BANK11991_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11991_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11992
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11992_DATA_W 32
+#define RFC_ULLRAM_BANK11992_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11992_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11993
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11993_DATA_W 32
+#define RFC_ULLRAM_BANK11993_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11993_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11994
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11994_DATA_W 32
+#define RFC_ULLRAM_BANK11994_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11994_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11995
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11995_DATA_W 32
+#define RFC_ULLRAM_BANK11995_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11995_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11996
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11996_DATA_W 32
+#define RFC_ULLRAM_BANK11996_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11996_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11997
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11997_DATA_W 32
+#define RFC_ULLRAM_BANK11997_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11997_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11998
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11998_DATA_W 32
+#define RFC_ULLRAM_BANK11998_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11998_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK11999
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK11999_DATA_W 32
+#define RFC_ULLRAM_BANK11999_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK11999_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12000
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12000_DATA_W 32
+#define RFC_ULLRAM_BANK12000_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12000_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12001
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12001_DATA_W 32
+#define RFC_ULLRAM_BANK12001_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12001_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12002
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12002_DATA_W 32
+#define RFC_ULLRAM_BANK12002_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12002_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12003
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12003_DATA_W 32
+#define RFC_ULLRAM_BANK12003_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12003_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12004
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12004_DATA_W 32
+#define RFC_ULLRAM_BANK12004_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12004_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12005
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12005_DATA_W 32
+#define RFC_ULLRAM_BANK12005_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12005_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12006
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12006_DATA_W 32
+#define RFC_ULLRAM_BANK12006_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12006_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12007
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12007_DATA_W 32
+#define RFC_ULLRAM_BANK12007_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12007_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12008
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12008_DATA_W 32
+#define RFC_ULLRAM_BANK12008_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12008_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12009
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12009_DATA_W 32
+#define RFC_ULLRAM_BANK12009_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12009_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12010
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12010_DATA_W 32
+#define RFC_ULLRAM_BANK12010_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12010_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12011
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12011_DATA_W 32
+#define RFC_ULLRAM_BANK12011_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12011_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12012
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12012_DATA_W 32
+#define RFC_ULLRAM_BANK12012_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12012_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12013
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12013_DATA_W 32
+#define RFC_ULLRAM_BANK12013_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12013_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12014
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12014_DATA_W 32
+#define RFC_ULLRAM_BANK12014_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12014_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12015
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12015_DATA_W 32
+#define RFC_ULLRAM_BANK12015_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12015_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12016
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12016_DATA_W 32
+#define RFC_ULLRAM_BANK12016_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12016_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12017
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12017_DATA_W 32
+#define RFC_ULLRAM_BANK12017_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12017_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12018
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12018_DATA_W 32
+#define RFC_ULLRAM_BANK12018_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12018_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12019
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12019_DATA_W 32
+#define RFC_ULLRAM_BANK12019_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12019_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12020
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12020_DATA_W 32
+#define RFC_ULLRAM_BANK12020_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12020_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12021
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12021_DATA_W 32
+#define RFC_ULLRAM_BANK12021_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12021_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12022
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12022_DATA_W 32
+#define RFC_ULLRAM_BANK12022_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12022_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12023
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12023_DATA_W 32
+#define RFC_ULLRAM_BANK12023_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12023_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12024
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12024_DATA_W 32
+#define RFC_ULLRAM_BANK12024_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12024_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12025
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12025_DATA_W 32
+#define RFC_ULLRAM_BANK12025_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12025_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12026
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12026_DATA_W 32
+#define RFC_ULLRAM_BANK12026_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12026_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12027
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12027_DATA_W 32
+#define RFC_ULLRAM_BANK12027_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12027_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12028
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12028_DATA_W 32
+#define RFC_ULLRAM_BANK12028_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12028_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12029
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12029_DATA_W 32
+#define RFC_ULLRAM_BANK12029_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12029_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12030
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12030_DATA_W 32
+#define RFC_ULLRAM_BANK12030_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12030_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12031
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12031_DATA_W 32
+#define RFC_ULLRAM_BANK12031_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12031_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12032
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12032_DATA_W 32
+#define RFC_ULLRAM_BANK12032_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12032_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12033
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12033_DATA_W 32
+#define RFC_ULLRAM_BANK12033_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12033_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12034
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12034_DATA_W 32
+#define RFC_ULLRAM_BANK12034_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12034_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12035
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12035_DATA_W 32
+#define RFC_ULLRAM_BANK12035_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12035_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12036
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12036_DATA_W 32
+#define RFC_ULLRAM_BANK12036_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12036_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12037
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12037_DATA_W 32
+#define RFC_ULLRAM_BANK12037_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12037_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12038
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12038_DATA_W 32
+#define RFC_ULLRAM_BANK12038_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12038_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12039
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12039_DATA_W 32
+#define RFC_ULLRAM_BANK12039_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12039_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12040
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12040_DATA_W 32
+#define RFC_ULLRAM_BANK12040_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12040_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12041
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12041_DATA_W 32
+#define RFC_ULLRAM_BANK12041_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12041_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12042
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12042_DATA_W 32
+#define RFC_ULLRAM_BANK12042_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12042_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12043
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12043_DATA_W 32
+#define RFC_ULLRAM_BANK12043_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12043_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12044
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12044_DATA_W 32
+#define RFC_ULLRAM_BANK12044_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12044_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12045
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12045_DATA_W 32
+#define RFC_ULLRAM_BANK12045_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12045_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12046
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12046_DATA_W 32
+#define RFC_ULLRAM_BANK12046_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12046_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: RFC_ULLRAM_O_BANK12047
+//
+//*****************************************************************************
+// Field: [31:0] DATA
+//
+// SRAM data
+#define RFC_ULLRAM_BANK12047_DATA_W 32
+#define RFC_ULLRAM_BANK12047_DATA_M 0xFFFFFFFF
+#define RFC_ULLRAM_BANK12047_DATA_S 0
+
+
+#endif // __RFC_ULLRAM__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_smph.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_smph.h
new file mode 100644
index 0000000..7bbdcd6
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_smph.h
@@ -0,0 +1,1455 @@
+/******************************************************************************
+* Filename: hw_smph_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_SMPH_H__
+#define __HW_SMPH_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// SMPH component
+//
+//*****************************************************************************
+// MCU SEMAPHORE 0
+#define SMPH_O_SMPH0 0x00000000
+
+// MCU SEMAPHORE 1
+#define SMPH_O_SMPH1 0x00000004
+
+// MCU SEMAPHORE 2
+#define SMPH_O_SMPH2 0x00000008
+
+// MCU SEMAPHORE 3
+#define SMPH_O_SMPH3 0x0000000C
+
+// MCU SEMAPHORE 4
+#define SMPH_O_SMPH4 0x00000010
+
+// MCU SEMAPHORE 5
+#define SMPH_O_SMPH5 0x00000014
+
+// MCU SEMAPHORE 6
+#define SMPH_O_SMPH6 0x00000018
+
+// MCU SEMAPHORE 7
+#define SMPH_O_SMPH7 0x0000001C
+
+// MCU SEMAPHORE 8
+#define SMPH_O_SMPH8 0x00000020
+
+// MCU SEMAPHORE 9
+#define SMPH_O_SMPH9 0x00000024
+
+// MCU SEMAPHORE 10
+#define SMPH_O_SMPH10 0x00000028
+
+// MCU SEMAPHORE 11
+#define SMPH_O_SMPH11 0x0000002C
+
+// MCU SEMAPHORE 12
+#define SMPH_O_SMPH12 0x00000030
+
+// MCU SEMAPHORE 13
+#define SMPH_O_SMPH13 0x00000034
+
+// MCU SEMAPHORE 14
+#define SMPH_O_SMPH14 0x00000038
+
+// MCU SEMAPHORE 15
+#define SMPH_O_SMPH15 0x0000003C
+
+// MCU SEMAPHORE 16
+#define SMPH_O_SMPH16 0x00000040
+
+// MCU SEMAPHORE 17
+#define SMPH_O_SMPH17 0x00000044
+
+// MCU SEMAPHORE 18
+#define SMPH_O_SMPH18 0x00000048
+
+// MCU SEMAPHORE 19
+#define SMPH_O_SMPH19 0x0000004C
+
+// MCU SEMAPHORE 20
+#define SMPH_O_SMPH20 0x00000050
+
+// MCU SEMAPHORE 21
+#define SMPH_O_SMPH21 0x00000054
+
+// MCU SEMAPHORE 22
+#define SMPH_O_SMPH22 0x00000058
+
+// MCU SEMAPHORE 23
+#define SMPH_O_SMPH23 0x0000005C
+
+// MCU SEMAPHORE 24
+#define SMPH_O_SMPH24 0x00000060
+
+// MCU SEMAPHORE 25
+#define SMPH_O_SMPH25 0x00000064
+
+// MCU SEMAPHORE 26
+#define SMPH_O_SMPH26 0x00000068
+
+// MCU SEMAPHORE 27
+#define SMPH_O_SMPH27 0x0000006C
+
+// MCU SEMAPHORE 28
+#define SMPH_O_SMPH28 0x00000070
+
+// MCU SEMAPHORE 29
+#define SMPH_O_SMPH29 0x00000074
+
+// MCU SEMAPHORE 30
+#define SMPH_O_SMPH30 0x00000078
+
+// MCU SEMAPHORE 31
+#define SMPH_O_SMPH31 0x0000007C
+
+// MCU SEMAPHORE 0 ALIAS
+#define SMPH_O_PEEK0 0x00000800
+
+// MCU SEMAPHORE 1 ALIAS
+#define SMPH_O_PEEK1 0x00000804
+
+// MCU SEMAPHORE 2 ALIAS
+#define SMPH_O_PEEK2 0x00000808
+
+// MCU SEMAPHORE 3 ALIAS
+#define SMPH_O_PEEK3 0x0000080C
+
+// MCU SEMAPHORE 4 ALIAS
+#define SMPH_O_PEEK4 0x00000810
+
+// MCU SEMAPHORE 5 ALIAS
+#define SMPH_O_PEEK5 0x00000814
+
+// MCU SEMAPHORE 6 ALIAS
+#define SMPH_O_PEEK6 0x00000818
+
+// MCU SEMAPHORE 7 ALIAS
+#define SMPH_O_PEEK7 0x0000081C
+
+// MCU SEMAPHORE 8 ALIAS
+#define SMPH_O_PEEK8 0x00000820
+
+// MCU SEMAPHORE 9 ALIAS
+#define SMPH_O_PEEK9 0x00000824
+
+// MCU SEMAPHORE 10 ALIAS
+#define SMPH_O_PEEK10 0x00000828
+
+// MCU SEMAPHORE 11 ALIAS
+#define SMPH_O_PEEK11 0x0000082C
+
+// MCU SEMAPHORE 12 ALIAS
+#define SMPH_O_PEEK12 0x00000830
+
+// MCU SEMAPHORE 13 ALIAS
+#define SMPH_O_PEEK13 0x00000834
+
+// MCU SEMAPHORE 14 ALIAS
+#define SMPH_O_PEEK14 0x00000838
+
+// MCU SEMAPHORE 15 ALIAS
+#define SMPH_O_PEEK15 0x0000083C
+
+// MCU SEMAPHORE 16 ALIAS
+#define SMPH_O_PEEK16 0x00000840
+
+// MCU SEMAPHORE 17 ALIAS
+#define SMPH_O_PEEK17 0x00000844
+
+// MCU SEMAPHORE 18 ALIAS
+#define SMPH_O_PEEK18 0x00000848
+
+// MCU SEMAPHORE 19 ALIAS
+#define SMPH_O_PEEK19 0x0000084C
+
+// MCU SEMAPHORE 20 ALIAS
+#define SMPH_O_PEEK20 0x00000850
+
+// MCU SEMAPHORE 21 ALIAS
+#define SMPH_O_PEEK21 0x00000854
+
+// MCU SEMAPHORE 22 ALIAS
+#define SMPH_O_PEEK22 0x00000858
+
+// MCU SEMAPHORE 23 ALIAS
+#define SMPH_O_PEEK23 0x0000085C
+
+// MCU SEMAPHORE 24 ALIAS
+#define SMPH_O_PEEK24 0x00000860
+
+// MCU SEMAPHORE 25 ALIAS
+#define SMPH_O_PEEK25 0x00000864
+
+// MCU SEMAPHORE 26 ALIAS
+#define SMPH_O_PEEK26 0x00000868
+
+// MCU SEMAPHORE 27 ALIAS
+#define SMPH_O_PEEK27 0x0000086C
+
+// MCU SEMAPHORE 28 ALIAS
+#define SMPH_O_PEEK28 0x00000870
+
+// MCU SEMAPHORE 29 ALIAS
+#define SMPH_O_PEEK29 0x00000874
+
+// MCU SEMAPHORE 30 ALIAS
+#define SMPH_O_PEEK30 0x00000878
+
+// MCU SEMAPHORE 31 ALIAS
+#define SMPH_O_PEEK31 0x0000087C
+
+//*****************************************************************************
+//
+// Register: SMPH_O_SMPH0
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Reading the register causes it to change value to 0. Releasing the semaphore
+// is done by writing 1.
+#define SMPH_SMPH0_STAT 0x00000001
+#define SMPH_SMPH0_STAT_BITN 0
+#define SMPH_SMPH0_STAT_M 0x00000001
+#define SMPH_SMPH0_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_SMPH1
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Reading the register causes it to change value to 0. Releasing the semaphore
+// is done by writing 1.
+#define SMPH_SMPH1_STAT 0x00000001
+#define SMPH_SMPH1_STAT_BITN 0
+#define SMPH_SMPH1_STAT_M 0x00000001
+#define SMPH_SMPH1_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_SMPH2
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Reading the register causes it to change value to 0. Releasing the semaphore
+// is done by writing 1.
+#define SMPH_SMPH2_STAT 0x00000001
+#define SMPH_SMPH2_STAT_BITN 0
+#define SMPH_SMPH2_STAT_M 0x00000001
+#define SMPH_SMPH2_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_SMPH3
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Reading the register causes it to change value to 0. Releasing the semaphore
+// is done by writing 1.
+#define SMPH_SMPH3_STAT 0x00000001
+#define SMPH_SMPH3_STAT_BITN 0
+#define SMPH_SMPH3_STAT_M 0x00000001
+#define SMPH_SMPH3_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_SMPH4
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Reading the register causes it to change value to 0. Releasing the semaphore
+// is done by writing 1.
+#define SMPH_SMPH4_STAT 0x00000001
+#define SMPH_SMPH4_STAT_BITN 0
+#define SMPH_SMPH4_STAT_M 0x00000001
+#define SMPH_SMPH4_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_SMPH5
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Reading the register causes it to change value to 0. Releasing the semaphore
+// is done by writing 1.
+#define SMPH_SMPH5_STAT 0x00000001
+#define SMPH_SMPH5_STAT_BITN 0
+#define SMPH_SMPH5_STAT_M 0x00000001
+#define SMPH_SMPH5_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_SMPH6
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Reading the register causes it to change value to 0. Releasing the semaphore
+// is done by writing 1.
+#define SMPH_SMPH6_STAT 0x00000001
+#define SMPH_SMPH6_STAT_BITN 0
+#define SMPH_SMPH6_STAT_M 0x00000001
+#define SMPH_SMPH6_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_SMPH7
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Reading the register causes it to change value to 0. Releasing the semaphore
+// is done by writing 1.
+#define SMPH_SMPH7_STAT 0x00000001
+#define SMPH_SMPH7_STAT_BITN 0
+#define SMPH_SMPH7_STAT_M 0x00000001
+#define SMPH_SMPH7_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_SMPH8
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Reading the register causes it to change value to 0. Releasing the semaphore
+// is done by writing 1.
+#define SMPH_SMPH8_STAT 0x00000001
+#define SMPH_SMPH8_STAT_BITN 0
+#define SMPH_SMPH8_STAT_M 0x00000001
+#define SMPH_SMPH8_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_SMPH9
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Reading the register causes it to change value to 0. Releasing the semaphore
+// is done by writing 1.
+#define SMPH_SMPH9_STAT 0x00000001
+#define SMPH_SMPH9_STAT_BITN 0
+#define SMPH_SMPH9_STAT_M 0x00000001
+#define SMPH_SMPH9_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_SMPH10
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Reading the register causes it to change value to 0. Releasing the semaphore
+// is done by writing 1.
+#define SMPH_SMPH10_STAT 0x00000001
+#define SMPH_SMPH10_STAT_BITN 0
+#define SMPH_SMPH10_STAT_M 0x00000001
+#define SMPH_SMPH10_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_SMPH11
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Reading the register causes it to change value to 0. Releasing the semaphore
+// is done by writing 1.
+#define SMPH_SMPH11_STAT 0x00000001
+#define SMPH_SMPH11_STAT_BITN 0
+#define SMPH_SMPH11_STAT_M 0x00000001
+#define SMPH_SMPH11_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_SMPH12
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Reading the register causes it to change value to 0. Releasing the semaphore
+// is done by writing 1.
+#define SMPH_SMPH12_STAT 0x00000001
+#define SMPH_SMPH12_STAT_BITN 0
+#define SMPH_SMPH12_STAT_M 0x00000001
+#define SMPH_SMPH12_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_SMPH13
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Reading the register causes it to change value to 0. Releasing the semaphore
+// is done by writing 1.
+#define SMPH_SMPH13_STAT 0x00000001
+#define SMPH_SMPH13_STAT_BITN 0
+#define SMPH_SMPH13_STAT_M 0x00000001
+#define SMPH_SMPH13_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_SMPH14
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Reading the register causes it to change value to 0. Releasing the semaphore
+// is done by writing 1.
+#define SMPH_SMPH14_STAT 0x00000001
+#define SMPH_SMPH14_STAT_BITN 0
+#define SMPH_SMPH14_STAT_M 0x00000001
+#define SMPH_SMPH14_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_SMPH15
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Reading the register causes it to change value to 0. Releasing the semaphore
+// is done by writing 1.
+#define SMPH_SMPH15_STAT 0x00000001
+#define SMPH_SMPH15_STAT_BITN 0
+#define SMPH_SMPH15_STAT_M 0x00000001
+#define SMPH_SMPH15_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_SMPH16
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Reading the register causes it to change value to 0. Releasing the semaphore
+// is done by writing 1.
+#define SMPH_SMPH16_STAT 0x00000001
+#define SMPH_SMPH16_STAT_BITN 0
+#define SMPH_SMPH16_STAT_M 0x00000001
+#define SMPH_SMPH16_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_SMPH17
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Reading the register causes it to change value to 0. Releasing the semaphore
+// is done by writing 1.
+#define SMPH_SMPH17_STAT 0x00000001
+#define SMPH_SMPH17_STAT_BITN 0
+#define SMPH_SMPH17_STAT_M 0x00000001
+#define SMPH_SMPH17_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_SMPH18
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Reading the register causes it to change value to 0. Releasing the semaphore
+// is done by writing 1.
+#define SMPH_SMPH18_STAT 0x00000001
+#define SMPH_SMPH18_STAT_BITN 0
+#define SMPH_SMPH18_STAT_M 0x00000001
+#define SMPH_SMPH18_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_SMPH19
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Reading the register causes it to change value to 0. Releasing the semaphore
+// is done by writing 1.
+#define SMPH_SMPH19_STAT 0x00000001
+#define SMPH_SMPH19_STAT_BITN 0
+#define SMPH_SMPH19_STAT_M 0x00000001
+#define SMPH_SMPH19_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_SMPH20
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Reading the register causes it to change value to 0. Releasing the semaphore
+// is done by writing 1.
+#define SMPH_SMPH20_STAT 0x00000001
+#define SMPH_SMPH20_STAT_BITN 0
+#define SMPH_SMPH20_STAT_M 0x00000001
+#define SMPH_SMPH20_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_SMPH21
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Reading the register causes it to change value to 0. Releasing the semaphore
+// is done by writing 1.
+#define SMPH_SMPH21_STAT 0x00000001
+#define SMPH_SMPH21_STAT_BITN 0
+#define SMPH_SMPH21_STAT_M 0x00000001
+#define SMPH_SMPH21_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_SMPH22
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Reading the register causes it to change value to 0. Releasing the semaphore
+// is done by writing 1.
+#define SMPH_SMPH22_STAT 0x00000001
+#define SMPH_SMPH22_STAT_BITN 0
+#define SMPH_SMPH22_STAT_M 0x00000001
+#define SMPH_SMPH22_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_SMPH23
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Reading the register causes it to change value to 0. Releasing the semaphore
+// is done by writing 1.
+#define SMPH_SMPH23_STAT 0x00000001
+#define SMPH_SMPH23_STAT_BITN 0
+#define SMPH_SMPH23_STAT_M 0x00000001
+#define SMPH_SMPH23_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_SMPH24
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Reading the register causes it to change value to 0. Releasing the semaphore
+// is done by writing 1.
+#define SMPH_SMPH24_STAT 0x00000001
+#define SMPH_SMPH24_STAT_BITN 0
+#define SMPH_SMPH24_STAT_M 0x00000001
+#define SMPH_SMPH24_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_SMPH25
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Reading the register causes it to change value to 0. Releasing the semaphore
+// is done by writing 1.
+#define SMPH_SMPH25_STAT 0x00000001
+#define SMPH_SMPH25_STAT_BITN 0
+#define SMPH_SMPH25_STAT_M 0x00000001
+#define SMPH_SMPH25_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_SMPH26
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Reading the register causes it to change value to 0. Releasing the semaphore
+// is done by writing 1.
+#define SMPH_SMPH26_STAT 0x00000001
+#define SMPH_SMPH26_STAT_BITN 0
+#define SMPH_SMPH26_STAT_M 0x00000001
+#define SMPH_SMPH26_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_SMPH27
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Reading the register causes it to change value to 0. Releasing the semaphore
+// is done by writing 1.
+#define SMPH_SMPH27_STAT 0x00000001
+#define SMPH_SMPH27_STAT_BITN 0
+#define SMPH_SMPH27_STAT_M 0x00000001
+#define SMPH_SMPH27_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_SMPH28
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Reading the register causes it to change value to 0. Releasing the semaphore
+// is done by writing 1.
+#define SMPH_SMPH28_STAT 0x00000001
+#define SMPH_SMPH28_STAT_BITN 0
+#define SMPH_SMPH28_STAT_M 0x00000001
+#define SMPH_SMPH28_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_SMPH29
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Reading the register causes it to change value to 0. Releasing the semaphore
+// is done by writing 1.
+#define SMPH_SMPH29_STAT 0x00000001
+#define SMPH_SMPH29_STAT_BITN 0
+#define SMPH_SMPH29_STAT_M 0x00000001
+#define SMPH_SMPH29_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_SMPH30
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Reading the register causes it to change value to 0. Releasing the semaphore
+// is done by writing 1.
+#define SMPH_SMPH30_STAT 0x00000001
+#define SMPH_SMPH30_STAT_BITN 0
+#define SMPH_SMPH30_STAT_M 0x00000001
+#define SMPH_SMPH30_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_SMPH31
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Reading the register causes it to change value to 0. Releasing the semaphore
+// is done by writing 1.
+#define SMPH_SMPH31_STAT 0x00000001
+#define SMPH_SMPH31_STAT_BITN 0
+#define SMPH_SMPH31_STAT_M 0x00000001
+#define SMPH_SMPH31_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_PEEK0
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Used for semaphore debugging. A read operation will not change register
+// value. Register writing is not possible.
+#define SMPH_PEEK0_STAT 0x00000001
+#define SMPH_PEEK0_STAT_BITN 0
+#define SMPH_PEEK0_STAT_M 0x00000001
+#define SMPH_PEEK0_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_PEEK1
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Used for semaphore debugging. A read operation will not change register
+// value. Register writing is not possible.
+#define SMPH_PEEK1_STAT 0x00000001
+#define SMPH_PEEK1_STAT_BITN 0
+#define SMPH_PEEK1_STAT_M 0x00000001
+#define SMPH_PEEK1_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_PEEK2
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Used for semaphore debugging. A read operation will not change register
+// value. Register writing is not possible.
+#define SMPH_PEEK2_STAT 0x00000001
+#define SMPH_PEEK2_STAT_BITN 0
+#define SMPH_PEEK2_STAT_M 0x00000001
+#define SMPH_PEEK2_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_PEEK3
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Used for semaphore debugging. A read operation will not change register
+// value. Register writing is not possible.
+#define SMPH_PEEK3_STAT 0x00000001
+#define SMPH_PEEK3_STAT_BITN 0
+#define SMPH_PEEK3_STAT_M 0x00000001
+#define SMPH_PEEK3_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_PEEK4
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Used for semaphore debugging. A read operation will not change register
+// value. Register writing is not possible.
+#define SMPH_PEEK4_STAT 0x00000001
+#define SMPH_PEEK4_STAT_BITN 0
+#define SMPH_PEEK4_STAT_M 0x00000001
+#define SMPH_PEEK4_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_PEEK5
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Used for semaphore debugging. A read operation will not change register
+// value. Register writing is not possible.
+#define SMPH_PEEK5_STAT 0x00000001
+#define SMPH_PEEK5_STAT_BITN 0
+#define SMPH_PEEK5_STAT_M 0x00000001
+#define SMPH_PEEK5_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_PEEK6
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Used for semaphore debugging. A read operation will not change register
+// value. Register writing is not possible.
+#define SMPH_PEEK6_STAT 0x00000001
+#define SMPH_PEEK6_STAT_BITN 0
+#define SMPH_PEEK6_STAT_M 0x00000001
+#define SMPH_PEEK6_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_PEEK7
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Used for semaphore debugging. A read operation will not change register
+// value. Register writing is not possible.
+#define SMPH_PEEK7_STAT 0x00000001
+#define SMPH_PEEK7_STAT_BITN 0
+#define SMPH_PEEK7_STAT_M 0x00000001
+#define SMPH_PEEK7_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_PEEK8
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Used for semaphore debugging. A read operation will not change register
+// value. Register writing is not possible.
+#define SMPH_PEEK8_STAT 0x00000001
+#define SMPH_PEEK8_STAT_BITN 0
+#define SMPH_PEEK8_STAT_M 0x00000001
+#define SMPH_PEEK8_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_PEEK9
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Used for semaphore debugging. A read operation will not change register
+// value. Register writing is not possible.
+#define SMPH_PEEK9_STAT 0x00000001
+#define SMPH_PEEK9_STAT_BITN 0
+#define SMPH_PEEK9_STAT_M 0x00000001
+#define SMPH_PEEK9_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_PEEK10
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Used for semaphore debugging. A read operation will not change register
+// value. Register writing is not possible.
+#define SMPH_PEEK10_STAT 0x00000001
+#define SMPH_PEEK10_STAT_BITN 0
+#define SMPH_PEEK10_STAT_M 0x00000001
+#define SMPH_PEEK10_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_PEEK11
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Used for semaphore debugging. A read operation will not change register
+// value. Register writing is not possible.
+#define SMPH_PEEK11_STAT 0x00000001
+#define SMPH_PEEK11_STAT_BITN 0
+#define SMPH_PEEK11_STAT_M 0x00000001
+#define SMPH_PEEK11_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_PEEK12
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Used for semaphore debugging. A read operation will not change register
+// value. Register writing is not possible.
+#define SMPH_PEEK12_STAT 0x00000001
+#define SMPH_PEEK12_STAT_BITN 0
+#define SMPH_PEEK12_STAT_M 0x00000001
+#define SMPH_PEEK12_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_PEEK13
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Used for semaphore debugging. A read operation will not change register
+// value. Register writing is not possible.
+#define SMPH_PEEK13_STAT 0x00000001
+#define SMPH_PEEK13_STAT_BITN 0
+#define SMPH_PEEK13_STAT_M 0x00000001
+#define SMPH_PEEK13_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_PEEK14
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Used for semaphore debugging. A read operation will not change register
+// value. Register writing is not possible.
+#define SMPH_PEEK14_STAT 0x00000001
+#define SMPH_PEEK14_STAT_BITN 0
+#define SMPH_PEEK14_STAT_M 0x00000001
+#define SMPH_PEEK14_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_PEEK15
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Used for semaphore debugging. A read operation will not change register
+// value. Register writing is not possible.
+#define SMPH_PEEK15_STAT 0x00000001
+#define SMPH_PEEK15_STAT_BITN 0
+#define SMPH_PEEK15_STAT_M 0x00000001
+#define SMPH_PEEK15_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_PEEK16
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Used for semaphore debugging. A read operation will not change register
+// value. Register writing is not possible.
+#define SMPH_PEEK16_STAT 0x00000001
+#define SMPH_PEEK16_STAT_BITN 0
+#define SMPH_PEEK16_STAT_M 0x00000001
+#define SMPH_PEEK16_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_PEEK17
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Used for semaphore debugging. A read operation will not change register
+// value. Register writing is not possible.
+#define SMPH_PEEK17_STAT 0x00000001
+#define SMPH_PEEK17_STAT_BITN 0
+#define SMPH_PEEK17_STAT_M 0x00000001
+#define SMPH_PEEK17_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_PEEK18
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Used for semaphore debugging. A read operation will not change register
+// value. Register writing is not possible.
+#define SMPH_PEEK18_STAT 0x00000001
+#define SMPH_PEEK18_STAT_BITN 0
+#define SMPH_PEEK18_STAT_M 0x00000001
+#define SMPH_PEEK18_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_PEEK19
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Used for semaphore debugging. A read operation will not change register
+// value. Register writing is not possible.
+#define SMPH_PEEK19_STAT 0x00000001
+#define SMPH_PEEK19_STAT_BITN 0
+#define SMPH_PEEK19_STAT_M 0x00000001
+#define SMPH_PEEK19_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_PEEK20
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Used for semaphore debugging. A read operation will not change register
+// value. Register writing is not possible.
+#define SMPH_PEEK20_STAT 0x00000001
+#define SMPH_PEEK20_STAT_BITN 0
+#define SMPH_PEEK20_STAT_M 0x00000001
+#define SMPH_PEEK20_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_PEEK21
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Used for semaphore debugging. A read operation will not change register
+// value. Register writing is not possible.
+#define SMPH_PEEK21_STAT 0x00000001
+#define SMPH_PEEK21_STAT_BITN 0
+#define SMPH_PEEK21_STAT_M 0x00000001
+#define SMPH_PEEK21_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_PEEK22
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Used for semaphore debugging. A read operation will not change register
+// value. Register writing is not possible.
+#define SMPH_PEEK22_STAT 0x00000001
+#define SMPH_PEEK22_STAT_BITN 0
+#define SMPH_PEEK22_STAT_M 0x00000001
+#define SMPH_PEEK22_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_PEEK23
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Used for semaphore debugging. A read operation will not change register
+// value. Register writing is not possible.
+#define SMPH_PEEK23_STAT 0x00000001
+#define SMPH_PEEK23_STAT_BITN 0
+#define SMPH_PEEK23_STAT_M 0x00000001
+#define SMPH_PEEK23_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_PEEK24
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Used for semaphore debugging. A read operation will not change register
+// value. Register writing is not possible.
+#define SMPH_PEEK24_STAT 0x00000001
+#define SMPH_PEEK24_STAT_BITN 0
+#define SMPH_PEEK24_STAT_M 0x00000001
+#define SMPH_PEEK24_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_PEEK25
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Used for semaphore debugging. A read operation will not change register
+// value. Register writing is not possible.
+#define SMPH_PEEK25_STAT 0x00000001
+#define SMPH_PEEK25_STAT_BITN 0
+#define SMPH_PEEK25_STAT_M 0x00000001
+#define SMPH_PEEK25_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_PEEK26
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Used for semaphore debugging. A read operation will not change register
+// value. Register writing is not possible.
+#define SMPH_PEEK26_STAT 0x00000001
+#define SMPH_PEEK26_STAT_BITN 0
+#define SMPH_PEEK26_STAT_M 0x00000001
+#define SMPH_PEEK26_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_PEEK27
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Used for semaphore debugging. A read operation will not change register
+// value. Register writing is not possible.
+#define SMPH_PEEK27_STAT 0x00000001
+#define SMPH_PEEK27_STAT_BITN 0
+#define SMPH_PEEK27_STAT_M 0x00000001
+#define SMPH_PEEK27_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_PEEK28
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Used for semaphore debugging. A read operation will not change register
+// value. Register writing is not possible.
+#define SMPH_PEEK28_STAT 0x00000001
+#define SMPH_PEEK28_STAT_BITN 0
+#define SMPH_PEEK28_STAT_M 0x00000001
+#define SMPH_PEEK28_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_PEEK29
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Used for semaphore debugging. A read operation will not change register
+// value. Register writing is not possible.
+#define SMPH_PEEK29_STAT 0x00000001
+#define SMPH_PEEK29_STAT_BITN 0
+#define SMPH_PEEK29_STAT_M 0x00000001
+#define SMPH_PEEK29_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_PEEK30
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Used for semaphore debugging. A read operation will not change register
+// value. Register writing is not possible.
+#define SMPH_PEEK30_STAT 0x00000001
+#define SMPH_PEEK30_STAT_BITN 0
+#define SMPH_PEEK30_STAT_M 0x00000001
+#define SMPH_PEEK30_STAT_S 0
+
+//*****************************************************************************
+//
+// Register: SMPH_O_PEEK31
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// Status when reading:
+//
+// 0: Semaphore is taken
+// 1: Semaphore is available
+//
+// Used for semaphore debugging. A read operation will not change register
+// value. Register writing is not possible.
+#define SMPH_PEEK31_STAT 0x00000001
+#define SMPH_PEEK31_STAT_BITN 0
+#define SMPH_PEEK31_STAT_M 0x00000001
+#define SMPH_PEEK31_STAT_S 0
+
+
+#endif // __SMPH__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_sram_mmr.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_sram_mmr.h
new file mode 100644
index 0000000..80d6422
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_sram_mmr.h
@@ -0,0 +1,150 @@
+/******************************************************************************
+* Filename: hw_sram_mmr_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_SRAM_MMR_H__
+#define __HW_SRAM_MMR_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// SRAM_MMR component
+//
+//*****************************************************************************
+// Parity Error Control
+#define SRAM_MMR_O_PER_CTL 0x00000000
+
+// Parity Error Check
+#define SRAM_MMR_O_PER_CHK 0x00000004
+
+// Parity Error Debug
+#define SRAM_MMR_O_PER_DBG 0x00000008
+
+// Memory Control
+#define SRAM_MMR_O_MEM_CTL 0x0000000C
+
+//*****************************************************************************
+//
+// Register: SRAM_MMR_O_PER_CTL
+//
+//*****************************************************************************
+// Field: [8] PER_DISABLE
+//
+// Parity Status Disable
+//
+// 0: A parity error will update PER_CHK.PER_ADDR field
+// 1: Parity error does not update PER_CHK.PER_ADDR field
+#define SRAM_MMR_PER_CTL_PER_DISABLE 0x00000100
+#define SRAM_MMR_PER_CTL_PER_DISABLE_BITN 8
+#define SRAM_MMR_PER_CTL_PER_DISABLE_M 0x00000100
+#define SRAM_MMR_PER_CTL_PER_DISABLE_S 8
+
+// Field: [0] PER_DEBUG_ENABLE
+//
+// Parity Error Debug Enable
+//
+// 0: Normal operation
+// 1: An address offset can be written to PER_DBG.PER_DEBUG_ADDR and parity
+// errors will be generated on reads from within this offset
+#define SRAM_MMR_PER_CTL_PER_DEBUG_ENABLE 0x00000001
+#define SRAM_MMR_PER_CTL_PER_DEBUG_ENABLE_BITN 0
+#define SRAM_MMR_PER_CTL_PER_DEBUG_ENABLE_M 0x00000001
+#define SRAM_MMR_PER_CTL_PER_DEBUG_ENABLE_S 0
+
+//*****************************************************************************
+//
+// Register: SRAM_MMR_O_PER_CHK
+//
+//*****************************************************************************
+// Field: [23:0] PER_ADDR
+//
+// Parity Error Address Offset
+// Returns the last address offset which resulted in a parity error during an
+// SRAM read. The address offset returned is always the word-aligned address
+// that contains the location with the parity error. For parity faults on non
+// word-aligned accesses, CPU_SCS:BFAR.ADDRESS will hold the address of the
+// location that resulted in parity error.
+#define SRAM_MMR_PER_CHK_PER_ADDR_W 24
+#define SRAM_MMR_PER_CHK_PER_ADDR_M 0x00FFFFFF
+#define SRAM_MMR_PER_CHK_PER_ADDR_S 0
+
+//*****************************************************************************
+//
+// Register: SRAM_MMR_O_PER_DBG
+//
+//*****************************************************************************
+// Field: [23:0] PER_DEBUG_ADDR
+//
+// Debug Parity Error Address Offset
+// When PER_CTL.PER_DEBUG is 1, this field is used to set a parity debug
+// address offset. The address offset must be a word-aligned address. Writes
+// within this address offset will force incorrect parity bits to be stored
+// together with the data written. The following reads within this same address
+// offset will thus result in parity errors to be generated.
+#define SRAM_MMR_PER_DBG_PER_DEBUG_ADDR_W 24
+#define SRAM_MMR_PER_DBG_PER_DEBUG_ADDR_M 0x00FFFFFF
+#define SRAM_MMR_PER_DBG_PER_DEBUG_ADDR_S 0
+
+//*****************************************************************************
+//
+// Register: SRAM_MMR_O_MEM_CTL
+//
+//*****************************************************************************
+// Field: [1] MEM_BUSY
+//
+// Memory Busy status
+//
+// 0: Memory accepts transfers
+// 1: Memory controller is busy during initialization. Read and write transfers
+// are not performed.
+#define SRAM_MMR_MEM_CTL_MEM_BUSY 0x00000002
+#define SRAM_MMR_MEM_CTL_MEM_BUSY_BITN 1
+#define SRAM_MMR_MEM_CTL_MEM_BUSY_M 0x00000002
+#define SRAM_MMR_MEM_CTL_MEM_BUSY_S 1
+
+// Field: [0] MEM_CLR_EN
+//
+// Memory Contents Initialization enable
+//
+// Writing 1 to MEM_CLR_EN will start memory initialization. The contents of
+// all byte locations will be initialized to 0x00. MEM_BUSY will be 1 until
+// memory initialization has completed.
+#define SRAM_MMR_MEM_CTL_MEM_CLR_EN 0x00000001
+#define SRAM_MMR_MEM_CTL_MEM_CLR_EN_BITN 0
+#define SRAM_MMR_MEM_CTL_MEM_CLR_EN_M 0x00000001
+#define SRAM_MMR_MEM_CTL_MEM_CLR_EN_S 0
+
+
+#endif // __SRAM_MMR__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ssi.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ssi.h
new file mode 100644
index 0000000..403d662
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ssi.h
@@ -0,0 +1,544 @@
+/******************************************************************************
+* Filename: hw_ssi_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_SSI_H__
+#define __HW_SSI_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// SSI component
+//
+//*****************************************************************************
+// Control 0
+#define SSI_O_CR0 0x00000000
+
+// Control 1
+#define SSI_O_CR1 0x00000004
+
+// Data
+#define SSI_O_DR 0x00000008
+
+// Status
+#define SSI_O_SR 0x0000000C
+
+// Clock Prescale
+#define SSI_O_CPSR 0x00000010
+
+// Interrupt Mask Set and Clear
+#define SSI_O_IMSC 0x00000014
+
+// Raw Interrupt Status
+#define SSI_O_RIS 0x00000018
+
+// Masked Interrupt Status
+#define SSI_O_MIS 0x0000001C
+
+// Interrupt Clear
+#define SSI_O_ICR 0x00000020
+
+// DMA Control
+#define SSI_O_DMACR 0x00000024
+
+//*****************************************************************************
+//
+// Register: SSI_O_CR0
+//
+//*****************************************************************************
+// Field: [15:8] SCR
+//
+// Serial clock rate:
+// This is used to generate the transmit and receive bit rate of the SSI. The
+// bit rate is
+// (SSI's clock frequency)/((SCR+1)*CPSR.CPSDVSR).
+// SCR is a value from 0-255.
+#define SSI_CR0_SCR_W 8
+#define SSI_CR0_SCR_M 0x0000FF00
+#define SSI_CR0_SCR_S 8
+
+// Field: [7] SPH
+//
+// CLKOUT phase (Motorola SPI frame format only)
+// This bit selects the clock edge that captures data and enables it to change
+// state. It
+// has the most impact on the first bit transmitted by either permitting or not
+// permitting a clock transition before the first data capture edge.
+// ENUMs:
+// 2ND_CLK_EDGE Data is captured on the second clock edge
+// transition.
+// 1ST_CLK_EDGE Data is captured on the first clock edge
+// transition.
+#define SSI_CR0_SPH 0x00000080
+#define SSI_CR0_SPH_BITN 7
+#define SSI_CR0_SPH_M 0x00000080
+#define SSI_CR0_SPH_S 7
+#define SSI_CR0_SPH_2ND_CLK_EDGE 0x00000080
+#define SSI_CR0_SPH_1ST_CLK_EDGE 0x00000000
+
+// Field: [6] SPO
+//
+// CLKOUT polarity (Motorola SPI frame format only)
+// ENUMs:
+// HIGH SSI produces a steady state HIGH value on the
+// CLKOUT pin when data is not being transferred.
+// LOW SSI produces a steady state LOW value on the
+// CLKOUT pin when data is
+// not being transferred.
+#define SSI_CR0_SPO 0x00000040
+#define SSI_CR0_SPO_BITN 6
+#define SSI_CR0_SPO_M 0x00000040
+#define SSI_CR0_SPO_S 6
+#define SSI_CR0_SPO_HIGH 0x00000040
+#define SSI_CR0_SPO_LOW 0x00000000
+
+// Field: [5:4] FRF
+//
+// Frame format.
+// The supported frame formats are Motorola SPI, TI synchronous serial and
+// National Microwire.
+// Value 0'b11 is reserved and shall not be used.
+// ENUMs:
+// NATIONAL_MICROWIRE National Microwire frame format
+// TI_SYNC_SERIAL TI synchronous serial frame format
+// MOTOROLA_SPI Motorola SPI frame format
+#define SSI_CR0_FRF_W 2
+#define SSI_CR0_FRF_M 0x00000030
+#define SSI_CR0_FRF_S 4
+#define SSI_CR0_FRF_NATIONAL_MICROWIRE 0x00000020
+#define SSI_CR0_FRF_TI_SYNC_SERIAL 0x00000010
+#define SSI_CR0_FRF_MOTOROLA_SPI 0x00000000
+
+// Field: [3:0] DSS
+//
+// Data Size Select.
+// Values 0b0000, 0b0001, 0b0010 are reserved and shall not be used.
+// ENUMs:
+// 16_BIT 16-bit data
+// 15_BIT 15-bit data
+// 14_BIT 14-bit data
+// 13_BIT 13-bit data
+// 12_BIT 12-bit data
+// 11_BIT 11-bit data
+// 10_BIT 10-bit data
+// 9_BIT 9-bit data
+// 8_BIT 8-bit data
+// 7_BIT 7-bit data
+// 6_BIT 6-bit data
+// 5_BIT 5-bit data
+// 4_BIT 4-bit data
+#define SSI_CR0_DSS_W 4
+#define SSI_CR0_DSS_M 0x0000000F
+#define SSI_CR0_DSS_S 0
+#define SSI_CR0_DSS_16_BIT 0x0000000F
+#define SSI_CR0_DSS_15_BIT 0x0000000E
+#define SSI_CR0_DSS_14_BIT 0x0000000D
+#define SSI_CR0_DSS_13_BIT 0x0000000C
+#define SSI_CR0_DSS_12_BIT 0x0000000B
+#define SSI_CR0_DSS_11_BIT 0x0000000A
+#define SSI_CR0_DSS_10_BIT 0x00000009
+#define SSI_CR0_DSS_9_BIT 0x00000008
+#define SSI_CR0_DSS_8_BIT 0x00000007
+#define SSI_CR0_DSS_7_BIT 0x00000006
+#define SSI_CR0_DSS_6_BIT 0x00000005
+#define SSI_CR0_DSS_5_BIT 0x00000004
+#define SSI_CR0_DSS_4_BIT 0x00000003
+
+//*****************************************************************************
+//
+// Register: SSI_O_CR1
+//
+//*****************************************************************************
+// Field: [3] SOD
+//
+// Slave-mode output disabled
+// This bit is relevant only in the slave mode, MS=1. In multiple-slave
+// systems, it is possible for an SSI master to broadcast a message to all
+// slaves in the system while ensuring that only one slave drives data onto its
+// serial output line. In such systems the RXD lines from multiple slaves could
+// be tied together. To operate in such systems, this bitfield can be set if
+// the SSI slave is not supposed to drive the TXD line:
+//
+// 0: SSI can drive the TXD output in slave mode.
+// 1: SSI cannot drive the TXD output in slave mode.
+#define SSI_CR1_SOD 0x00000008
+#define SSI_CR1_SOD_BITN 3
+#define SSI_CR1_SOD_M 0x00000008
+#define SSI_CR1_SOD_S 3
+
+// Field: [2] MS
+//
+// Master or slave mode select. This bit can be modified only when SSI is
+// disabled, SSE=0.
+// ENUMs:
+// SLAVE Device configured as slave
+// MASTER Device configured as master
+#define SSI_CR1_MS 0x00000004
+#define SSI_CR1_MS_BITN 2
+#define SSI_CR1_MS_M 0x00000004
+#define SSI_CR1_MS_S 2
+#define SSI_CR1_MS_SLAVE 0x00000004
+#define SSI_CR1_MS_MASTER 0x00000000
+
+// Field: [1] SSE
+//
+// Synchronous serial interface enable.
+// ENUMs:
+// SSI_ENABLED Operation enabled
+// SSI_DISABLED Operation disabled
+#define SSI_CR1_SSE 0x00000002
+#define SSI_CR1_SSE_BITN 1
+#define SSI_CR1_SSE_M 0x00000002
+#define SSI_CR1_SSE_S 1
+#define SSI_CR1_SSE_SSI_ENABLED 0x00000002
+#define SSI_CR1_SSE_SSI_DISABLED 0x00000000
+
+// Field: [0] LBM
+//
+// Loop back mode:
+//
+// 0: Normal serial port operation enabled.
+// 1: Output of transmit serial shifter is connected to input of receive serial
+// shifter internally.
+#define SSI_CR1_LBM 0x00000001
+#define SSI_CR1_LBM_BITN 0
+#define SSI_CR1_LBM_M 0x00000001
+#define SSI_CR1_LBM_S 0
+
+//*****************************************************************************
+//
+// Register: SSI_O_DR
+//
+//*****************************************************************************
+// Field: [15:0] DATA
+//
+// Transmit/receive data
+// The values read from this field or written to this field must be
+// right-justified when SSI is programmed for a data size that is less than 16
+// bits (CR0.DSS != 0b1111). Unused bits at the top are ignored by transmit
+// logic. The receive logic automatically right-justifies.
+#define SSI_DR_DATA_W 16
+#define SSI_DR_DATA_M 0x0000FFFF
+#define SSI_DR_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: SSI_O_SR
+//
+//*****************************************************************************
+// Field: [4] BSY
+//
+// Serial interface busy:
+//
+// 0: SSI is idle
+// 1: SSI is currently transmitting and/or receiving a frame or the transmit
+// FIFO is not empty.
+#define SSI_SR_BSY 0x00000010
+#define SSI_SR_BSY_BITN 4
+#define SSI_SR_BSY_M 0x00000010
+#define SSI_SR_BSY_S 4
+
+// Field: [3] RFF
+//
+// Receive FIFO full:
+//
+// 0: Receive FIFO is not full.
+// 1: Receive FIFO is full.
+#define SSI_SR_RFF 0x00000008
+#define SSI_SR_RFF_BITN 3
+#define SSI_SR_RFF_M 0x00000008
+#define SSI_SR_RFF_S 3
+
+// Field: [2] RNE
+//
+// Receive FIFO not empty
+//
+// 0: Receive FIFO is empty.
+// 1: Receive FIFO is not empty.
+#define SSI_SR_RNE 0x00000004
+#define SSI_SR_RNE_BITN 2
+#define SSI_SR_RNE_M 0x00000004
+#define SSI_SR_RNE_S 2
+
+// Field: [1] TNF
+//
+// Transmit FIFO not full:
+//
+// 0: Transmit FIFO is full.
+// 1: Transmit FIFO is not full.
+#define SSI_SR_TNF 0x00000002
+#define SSI_SR_TNF_BITN 1
+#define SSI_SR_TNF_M 0x00000002
+#define SSI_SR_TNF_S 1
+
+// Field: [0] TFE
+//
+// Transmit FIFO empty:
+//
+// 0: Transmit FIFO is not empty.
+// 1: Transmit FIFO is empty.
+#define SSI_SR_TFE 0x00000001
+#define SSI_SR_TFE_BITN 0
+#define SSI_SR_TFE_M 0x00000001
+#define SSI_SR_TFE_S 0
+
+//*****************************************************************************
+//
+// Register: SSI_O_CPSR
+//
+//*****************************************************************************
+// Field: [7:0] CPSDVSR
+//
+// Clock prescale divisor:
+// This field specifies the division factor by which the input system clock to
+// SSI must be internally divided before further use.
+// The value programmed into this field must be an even non-zero number
+// (2-254). The least significant bit of the programmed number is hard-coded to
+// zero. If an odd number is written to this register, data read back from
+// this register has the least significant bit as zero.
+#define SSI_CPSR_CPSDVSR_W 8
+#define SSI_CPSR_CPSDVSR_M 0x000000FF
+#define SSI_CPSR_CPSDVSR_S 0
+
+//*****************************************************************************
+//
+// Register: SSI_O_IMSC
+//
+//*****************************************************************************
+// Field: [3] TXIM
+//
+// Transmit FIFO interrupt mask:
+// A read returns the current mask for transmit FIFO interrupt. On a write of
+// 1, the mask for transmit FIFO interrupt is set which means the interrupt
+// state will be reflected in MIS.TXMIS. A write of 0 clears the mask which
+// means MIS.TXMIS will not reflect the interrupt.
+#define SSI_IMSC_TXIM 0x00000008
+#define SSI_IMSC_TXIM_BITN 3
+#define SSI_IMSC_TXIM_M 0x00000008
+#define SSI_IMSC_TXIM_S 3
+
+// Field: [2] RXIM
+//
+// Receive FIFO interrupt mask:
+// A read returns the current mask for receive FIFO interrupt. On a write of 1,
+// the mask for receive FIFO interrupt is set which means the interrupt state
+// will be reflected in MIS.RXMIS. A write of 0 clears the mask which means
+// MIS.RXMIS will not reflect the interrupt.
+#define SSI_IMSC_RXIM 0x00000004
+#define SSI_IMSC_RXIM_BITN 2
+#define SSI_IMSC_RXIM_M 0x00000004
+#define SSI_IMSC_RXIM_S 2
+
+// Field: [1] RTIM
+//
+// Receive timeout interrupt mask:
+// A read returns the current mask for receive timeout interrupt. On a write of
+// 1, the mask for receive timeout interrupt is set which means the interrupt
+// state will be reflected in MIS.RTMIS. A write of 0 clears the mask which
+// means MIS.RTMIS will not reflect the interrupt.
+#define SSI_IMSC_RTIM 0x00000002
+#define SSI_IMSC_RTIM_BITN 1
+#define SSI_IMSC_RTIM_M 0x00000002
+#define SSI_IMSC_RTIM_S 1
+
+// Field: [0] RORIM
+//
+// Receive overrun interrupt mask:
+// A read returns the current mask for receive overrun interrupt. On a write of
+// 1, the mask for receive overrun interrupt is set which means the interrupt
+// state will be reflected in MIS.RORMIS. A write of 0 clears the mask which
+// means MIS.RORMIS will not reflect the interrupt.
+#define SSI_IMSC_RORIM 0x00000001
+#define SSI_IMSC_RORIM_BITN 0
+#define SSI_IMSC_RORIM_M 0x00000001
+#define SSI_IMSC_RORIM_S 0
+
+//*****************************************************************************
+//
+// Register: SSI_O_RIS
+//
+//*****************************************************************************
+// Field: [3] TXRIS
+//
+// Raw transmit FIFO interrupt status:
+// The transmit interrupt is asserted when there are four or fewer valid
+// entries in the transmit FIFO. The transmit interrupt is not qualified with
+// the SSI enable signal. Therefore one of the following ways can be used:
+// - data can be written to the transmit FIFO prior to enabling the SSI and
+// the
+// interrupts.
+// - SSI and interrupts can be enabled so that data can be written to the
+// transmit FIFO by an interrupt service routine.
+#define SSI_RIS_TXRIS 0x00000008
+#define SSI_RIS_TXRIS_BITN 3
+#define SSI_RIS_TXRIS_M 0x00000008
+#define SSI_RIS_TXRIS_S 3
+
+// Field: [2] RXRIS
+//
+// Raw interrupt state of receive FIFO interrupt:
+// The receive interrupt is asserted when there are four or more valid entries
+// in the receive FIFO.
+#define SSI_RIS_RXRIS 0x00000004
+#define SSI_RIS_RXRIS_BITN 2
+#define SSI_RIS_RXRIS_M 0x00000004
+#define SSI_RIS_RXRIS_S 2
+
+// Field: [1] RTRIS
+//
+// Raw interrupt state of receive timeout interrupt:
+// The receive timeout interrupt is asserted when the receive FIFO is not empty
+// and SSI has remained idle for a fixed 32 bit period. This mechanism can be
+// used to notify the user that data is still present in the receive FIFO and
+// requires servicing. This interrupt is deasserted if the receive FIFO becomes
+// empty by subsequent reads, or if new data is received on RXD.
+// It can also be cleared by writing to ICR.RTIC.
+#define SSI_RIS_RTRIS 0x00000002
+#define SSI_RIS_RTRIS_BITN 1
+#define SSI_RIS_RTRIS_M 0x00000002
+#define SSI_RIS_RTRIS_S 1
+
+// Field: [0] RORRIS
+//
+// Raw interrupt state of receive overrun interrupt:
+// The receive overrun interrupt is asserted when the FIFO is already full and
+// an additional data frame is received, causing an overrun of the FIFO. Data
+// is over-written in the
+// receive shift register, but not the FIFO so the FIFO contents stay valid.
+// It can also be cleared by writing to ICR.RORIC.
+#define SSI_RIS_RORRIS 0x00000001
+#define SSI_RIS_RORRIS_BITN 0
+#define SSI_RIS_RORRIS_M 0x00000001
+#define SSI_RIS_RORRIS_S 0
+
+//*****************************************************************************
+//
+// Register: SSI_O_MIS
+//
+//*****************************************************************************
+// Field: [3] TXMIS
+//
+// Masked interrupt state of transmit FIFO interrupt:
+// This field returns the masked interrupt state of transmit FIFO interrupt
+// which is the AND product of raw interrupt state RIS.TXRIS and the mask
+// setting IMSC.TXIM.
+#define SSI_MIS_TXMIS 0x00000008
+#define SSI_MIS_TXMIS_BITN 3
+#define SSI_MIS_TXMIS_M 0x00000008
+#define SSI_MIS_TXMIS_S 3
+
+// Field: [2] RXMIS
+//
+// Masked interrupt state of receive FIFO interrupt:
+// This field returns the masked interrupt state of receive FIFO interrupt
+// which is the AND product of raw interrupt state RIS.RXRIS and the mask
+// setting IMSC.RXIM.
+#define SSI_MIS_RXMIS 0x00000004
+#define SSI_MIS_RXMIS_BITN 2
+#define SSI_MIS_RXMIS_M 0x00000004
+#define SSI_MIS_RXMIS_S 2
+
+// Field: [1] RTMIS
+//
+// Masked interrupt state of receive timeout interrupt:
+// This field returns the masked interrupt state of receive timeout interrupt
+// which is the AND product of raw interrupt state RIS.RTRIS and the mask
+// setting IMSC.RTIM.
+#define SSI_MIS_RTMIS 0x00000002
+#define SSI_MIS_RTMIS_BITN 1
+#define SSI_MIS_RTMIS_M 0x00000002
+#define SSI_MIS_RTMIS_S 1
+
+// Field: [0] RORMIS
+//
+// Masked interrupt state of receive overrun interrupt:
+// This field returns the masked interrupt state of receive overrun interrupt
+// which is the AND product of raw interrupt state RIS.RORRIS and the mask
+// setting IMSC.RORIM.
+#define SSI_MIS_RORMIS 0x00000001
+#define SSI_MIS_RORMIS_BITN 0
+#define SSI_MIS_RORMIS_M 0x00000001
+#define SSI_MIS_RORMIS_S 0
+
+//*****************************************************************************
+//
+// Register: SSI_O_ICR
+//
+//*****************************************************************************
+// Field: [1] RTIC
+//
+// Clear the receive timeout interrupt:
+// Writing 1 to this field clears the timeout interrupt (RIS.RTRIS). Writing 0
+// has no effect.
+#define SSI_ICR_RTIC 0x00000002
+#define SSI_ICR_RTIC_BITN 1
+#define SSI_ICR_RTIC_M 0x00000002
+#define SSI_ICR_RTIC_S 1
+
+// Field: [0] RORIC
+//
+// Clear the receive overrun interrupt:
+// Writing 1 to this field clears the overrun error interrupt (RIS.RORRIS).
+// Writing 0 has no effect.
+#define SSI_ICR_RORIC 0x00000001
+#define SSI_ICR_RORIC_BITN 0
+#define SSI_ICR_RORIC_M 0x00000001
+#define SSI_ICR_RORIC_S 0
+
+//*****************************************************************************
+//
+// Register: SSI_O_DMACR
+//
+//*****************************************************************************
+// Field: [1] TXDMAE
+//
+// Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is
+// enabled.
+#define SSI_DMACR_TXDMAE 0x00000002
+#define SSI_DMACR_TXDMAE_BITN 1
+#define SSI_DMACR_TXDMAE_M 0x00000002
+#define SSI_DMACR_TXDMAE_S 1
+
+// Field: [0] RXDMAE
+//
+// Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is
+// enabled.
+#define SSI_DMACR_RXDMAE 0x00000001
+#define SSI_DMACR_RXDMAE_BITN 0
+#define SSI_DMACR_RXDMAE_M 0x00000001
+#define SSI_DMACR_RXDMAE_S 0
+
+
+#endif // __SSI__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_sysctl.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_sysctl.h
new file mode 100644
index 0000000..3fdb02f
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_sysctl.h
@@ -0,0 +1,49 @@
+/******************************************************************************
+* Filename: hw_sysctl.h
+* Revised: 2015-03-16 14:43:45 +0100 (Mon, 16 Mar 2015)
+* Revision: 42989
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_SYSCTL_H__
+#define __HW_SYSCTL_H__
+
+
+//*****************************************************************************
+//
+// The following are initial defines for the MCU clock
+//
+//*****************************************************************************
+#define GET_MCU_CLOCK 48000000
+
+
+#endif // __HW_SYSCTL_H__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_trng.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_trng.h
new file mode 100644
index 0000000..44d4eb2
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_trng.h
@@ -0,0 +1,609 @@
+/******************************************************************************
+* Filename: hw_trng_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_TRNG_H__
+#define __HW_TRNG_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// TRNG component
+//
+//*****************************************************************************
+// Random Number Lower Word Readout Value
+#define TRNG_O_OUT0 0x00000000
+
+// Random Number Upper Word Readout Value
+#define TRNG_O_OUT1 0x00000004
+
+// Interrupt Status
+#define TRNG_O_IRQFLAGSTAT 0x00000008
+
+// Interrupt Mask
+#define TRNG_O_IRQFLAGMASK 0x0000000C
+
+// Interrupt Flag Clear
+#define TRNG_O_IRQFLAGCLR 0x00000010
+
+// Control
+#define TRNG_O_CTL 0x00000014
+
+// Configuration 0
+#define TRNG_O_CFG0 0x00000018
+
+// Alarm Control
+#define TRNG_O_ALARMCNT 0x0000001C
+
+// FRO Enable
+#define TRNG_O_FROEN 0x00000020
+
+// FRO De-tune Bit
+#define TRNG_O_FRODETUNE 0x00000024
+
+// Alarm Event
+#define TRNG_O_ALARMMASK 0x00000028
+
+// Alarm Shutdown
+#define TRNG_O_ALARMSTOP 0x0000002C
+
+// LFSR Readout Value
+#define TRNG_O_LFSR0 0x00000030
+
+// LFSR Readout Value
+#define TRNG_O_LFSR1 0x00000034
+
+// LFSR Readout Value
+#define TRNG_O_LFSR2 0x00000038
+
+// TRNG Engine Options Information
+#define TRNG_O_HWOPT 0x00000078
+
+// HW Version 0
+#define TRNG_O_HWVER0 0x0000007C
+
+// Interrupt Status After Masking
+#define TRNG_O_IRQSTATMASK 0x00001FD8
+
+// HW Version 1
+#define TRNG_O_HWVER1 0x00001FE0
+
+// Interrupt Set
+#define TRNG_O_IRQSET 0x00001FEC
+
+// SW Reset Control
+#define TRNG_O_SWRESET 0x00001FF0
+
+// Interrupt Status
+#define TRNG_O_IRQSTAT 0x00001FF8
+
+//*****************************************************************************
+//
+// Register: TRNG_O_OUT0
+//
+//*****************************************************************************
+// Field: [31:0] VALUE_31_0
+//
+// LSW of 64- bit random value. New value ready when IRQFLAGSTAT.RDY = 1.
+#define TRNG_OUT0_VALUE_31_0_W 32
+#define TRNG_OUT0_VALUE_31_0_M 0xFFFFFFFF
+#define TRNG_OUT0_VALUE_31_0_S 0
+
+//*****************************************************************************
+//
+// Register: TRNG_O_OUT1
+//
+//*****************************************************************************
+// Field: [31:0] VALUE_63_32
+//
+// MSW of 64-bit random value. New value ready when IRQFLAGSTAT.RDY = 1.
+#define TRNG_OUT1_VALUE_63_32_W 32
+#define TRNG_OUT1_VALUE_63_32_M 0xFFFFFFFF
+#define TRNG_OUT1_VALUE_63_32_S 0
+
+//*****************************************************************************
+//
+// Register: TRNG_O_IRQFLAGSTAT
+//
+//*****************************************************************************
+// Field: [31] NEED_CLOCK
+//
+// 1: Indicates that the TRNG is busy generating entropy or is in one of its
+// test modes - clocks may not be turned off and the power supply voltage must
+// be kept stable.
+// 0: TRNG is idle and can be shut down
+#define TRNG_IRQFLAGSTAT_NEED_CLOCK 0x80000000
+#define TRNG_IRQFLAGSTAT_NEED_CLOCK_BITN 31
+#define TRNG_IRQFLAGSTAT_NEED_CLOCK_M 0x80000000
+#define TRNG_IRQFLAGSTAT_NEED_CLOCK_S 31
+
+// Field: [1] SHUTDOWN_OVF
+//
+// 1: The number of FROs shut down (i.e. the number of '1' bits in the
+// ALARMSTOP register) has exceeded the threshold set by ALARMCNT.SHUTDOWN_THR
+//
+// Writing '1' to IRQFLAGCLR.SHUTDOWN_OVF clears this bit to '0' again.
+#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF 0x00000002
+#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_BITN 1
+#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_M 0x00000002
+#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_S 1
+
+// Field: [0] RDY
+//
+// 1: Data are available in OUT0 and OUT1.
+//
+// Acknowledging this state by writing '1' to IRQFLAGCLR.RDY clears this bit to
+// '0'.
+// If a new number is already available in the internal register of the TRNG,
+// the number is directly clocked into the result register. In this case the
+// status bit is asserted again, after one clock cycle.
+#define TRNG_IRQFLAGSTAT_RDY 0x00000001
+#define TRNG_IRQFLAGSTAT_RDY_BITN 0
+#define TRNG_IRQFLAGSTAT_RDY_M 0x00000001
+#define TRNG_IRQFLAGSTAT_RDY_S 0
+
+//*****************************************************************************
+//
+// Register: TRNG_O_IRQFLAGMASK
+//
+//*****************************************************************************
+// Field: [1] SHUTDOWN_OVF
+//
+// 1: Allow IRQFLAGSTAT.SHUTDOWN_OVF to activate the interrupt from this
+// module.
+#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF 0x00000002
+#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_BITN 1
+#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_M 0x00000002
+#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_S 1
+
+// Field: [0] RDY
+//
+// 1: Allow IRQFLAGSTAT.RDY to activate the interrupt from this module.
+#define TRNG_IRQFLAGMASK_RDY 0x00000001
+#define TRNG_IRQFLAGMASK_RDY_BITN 0
+#define TRNG_IRQFLAGMASK_RDY_M 0x00000001
+#define TRNG_IRQFLAGMASK_RDY_S 0
+
+//*****************************************************************************
+//
+// Register: TRNG_O_IRQFLAGCLR
+//
+//*****************************************************************************
+// Field: [1] SHUTDOWN_OVF
+//
+// 1: Clear IRQFLAGSTAT.SHUTDOWN_OVF.
+#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF 0x00000002
+#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_BITN 1
+#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_M 0x00000002
+#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_S 1
+
+// Field: [0] RDY
+//
+// 1: Clear IRQFLAGSTAT.RDY.
+#define TRNG_IRQFLAGCLR_RDY 0x00000001
+#define TRNG_IRQFLAGCLR_RDY_BITN 0
+#define TRNG_IRQFLAGCLR_RDY_M 0x00000001
+#define TRNG_IRQFLAGCLR_RDY_S 0
+
+//*****************************************************************************
+//
+// Register: TRNG_O_CTL
+//
+//*****************************************************************************
+// Field: [31:16] STARTUP_CYCLES
+//
+// This field determines the number of samples (between 2^8 and 2^24) taken to
+// gather entropy from the FROs during startup. If the written value of this
+// field is zero, the number of samples is 2^24, otherwise the number of
+// samples equals the written value times 2^8.
+//
+// 0x0000: 2^24 samples
+// 0x0001: 1*2^8 samples
+// 0x0002: 2*2^8 samples
+// 0x0003: 3*2^8 samples
+// ...
+// 0x8000: 32768*2^8 samples
+// 0xC000: 49152*2^8 samples
+// ...
+// 0xFFFF: 65535*2^8 samples
+//
+// This field can only be modified while TRNG_EN is 0. If 1 an update will be
+// ignored.
+#define TRNG_CTL_STARTUP_CYCLES_W 16
+#define TRNG_CTL_STARTUP_CYCLES_M 0xFFFF0000
+#define TRNG_CTL_STARTUP_CYCLES_S 16
+
+// Field: [10] TRNG_EN
+//
+// 0: Forces all TRNG logic back into the idle state immediately.
+// 1: Starts TRNG, gathering entropy from the FROs for the number of samples
+// determined by STARTUP_CYCLES.
+#define TRNG_CTL_TRNG_EN 0x00000400
+#define TRNG_CTL_TRNG_EN_BITN 10
+#define TRNG_CTL_TRNG_EN_M 0x00000400
+#define TRNG_CTL_TRNG_EN_S 10
+
+// Field: [2] NO_LFSR_FB
+//
+// 1: Remove XNOR feedback from the main LFSR, converting it into a normal
+// shift register for the XOR-ed outputs of the FROs (shifting data in on the
+// LSB side). A '1' also forces the LFSR to sample continuously.
+//
+// This bit can only be set to '1' when TEST_MODE is also set to '1' and should
+// not be used for other than test purposes
+#define TRNG_CTL_NO_LFSR_FB 0x00000004
+#define TRNG_CTL_NO_LFSR_FB_BITN 2
+#define TRNG_CTL_NO_LFSR_FB_M 0x00000004
+#define TRNG_CTL_NO_LFSR_FB_S 2
+
+// Field: [1] TEST_MODE
+//
+// 1: Enables access to the TESTCNT and LFSR0/LFSR1/LFSR2 registers (the latter
+// are automatically cleared before enabling access) and keeps
+// IRQFLAGSTAT.NEED_CLOCK at '1'.
+//
+// This bit shall not be used unless you need to change the LFSR seed prior to
+// creating a new random value. All other testing is done external to register
+// control.
+#define TRNG_CTL_TEST_MODE 0x00000002
+#define TRNG_CTL_TEST_MODE_BITN 1
+#define TRNG_CTL_TEST_MODE_M 0x00000002
+#define TRNG_CTL_TEST_MODE_S 1
+
+//*****************************************************************************
+//
+// Register: TRNG_O_CFG0
+//
+//*****************************************************************************
+// Field: [31:16] MAX_REFILL_CYCLES
+//
+// This field determines the maximum number of samples (between 2^8 and 2^24)
+// taken to re-generate entropy from the FROs after reading out a 64 bits
+// random number. If the written value of this field is zero, the number of
+// samples is 2^24, otherwise the number of samples equals the written value
+// times 2^8.
+//
+// 0x0000: 2^24 samples
+// 0x0001: 1*2^8 samples
+// 0x0002: 2*2^8 samples
+// 0x0003: 3*2^8 samples
+// ...
+// 0x8000: 32768*2^8 samples
+// 0xC000: 49152*2^8 samples
+// ...
+// 0xFFFF: 65535*2^8 samples
+//
+// This field can only be modified while CTL.TRNG_EN is 0.
+#define TRNG_CFG0_MAX_REFILL_CYCLES_W 16
+#define TRNG_CFG0_MAX_REFILL_CYCLES_M 0xFFFF0000
+#define TRNG_CFG0_MAX_REFILL_CYCLES_S 16
+
+// Field: [11:8] SMPL_DIV
+//
+// This field directly controls the number of clock cycles between samples
+// taken from the FROs. Default value 0 indicates that samples are taken every
+// clock cycle,
+// maximum value 0xF takes one sample every 16 clock cycles.
+// This field must be set to a value such that the slowest FRO (even under
+// worst-case
+// conditions) has a cycle time less than twice the sample period.
+//
+// This field can only be modified while CTL.TRNG_EN is '0'.
+#define TRNG_CFG0_SMPL_DIV_W 4
+#define TRNG_CFG0_SMPL_DIV_M 0x00000F00
+#define TRNG_CFG0_SMPL_DIV_S 8
+
+// Field: [7:0] MIN_REFILL_CYCLES
+//
+// This field determines the minimum number of samples (between 2^6 and 2^14)
+// taken to re-generate entropy from the FROs after reading out a 64 bits
+// random number. If the value of this field is zero, the number of samples is
+// fixed to the value determined by the MAX_REFILL_CYCLES field, otherwise the
+// minimum number of samples equals the written value times 64 (which can be up
+// to 2^14). To ensure same entropy in all generated random numbers the value 0
+// should be used. Then MAX_REFILL_CYCLES controls the minimum refill interval.
+// The number of samples defined here cannot be higher than the number defined
+// by the 'max_refill_cycles' field (i.e. that field takes precedence). No
+// random value will be created if min refill > max refill.
+//
+// This field can only be modified while CTL.TRNG_EN = 0.
+//
+// 0x00: Minimum samples = MAX_REFILL_CYCLES (all numbers have same entropy)
+// 0x01: 1*2^6 samples
+// 0x02: 2*2^6 samples
+// ...
+// 0xFF: 255*2^6 samples
+#define TRNG_CFG0_MIN_REFILL_CYCLES_W 8
+#define TRNG_CFG0_MIN_REFILL_CYCLES_M 0x000000FF
+#define TRNG_CFG0_MIN_REFILL_CYCLES_S 0
+
+//*****************************************************************************
+//
+// Register: TRNG_O_ALARMCNT
+//
+//*****************************************************************************
+// Field: [29:24] SHUTDOWN_CNT
+//
+// Read-only, indicates the number of '1' bits in ALARMSTOP register.
+// The maximum value equals the number of FROs.
+#define TRNG_ALARMCNT_SHUTDOWN_CNT_W 6
+#define TRNG_ALARMCNT_SHUTDOWN_CNT_M 0x3F000000
+#define TRNG_ALARMCNT_SHUTDOWN_CNT_S 24
+
+// Field: [20:16] SHUTDOWN_THR
+//
+// Threshold setting for generating IRQFLAGSTAT.SHUTDOWN_OVF interrupt. The
+// interrupt is triggered when SHUTDOWN_CNT value exceeds this bit field.
+#define TRNG_ALARMCNT_SHUTDOWN_THR_W 5
+#define TRNG_ALARMCNT_SHUTDOWN_THR_M 0x001F0000
+#define TRNG_ALARMCNT_SHUTDOWN_THR_S 16
+
+// Field: [7:0] ALARM_THR
+//
+// Alarm detection threshold for the repeating pattern detectors on each FRO.
+// An FRO 'alarm event' is declared when a repeating pattern (of up to four
+// samples length) is detected continuously for the number of samples defined
+// by this field's value. Reset value 0xFF should keep the number of 'alarm
+// events' to a manageable level.
+#define TRNG_ALARMCNT_ALARM_THR_W 8
+#define TRNG_ALARMCNT_ALARM_THR_M 0x000000FF
+#define TRNG_ALARMCNT_ALARM_THR_S 0
+
+//*****************************************************************************
+//
+// Register: TRNG_O_FROEN
+//
+//*****************************************************************************
+// Field: [23:0] FRO_MASK
+//
+// Enable bits for the individual FROs. A '1' in bit [n] enables FRO 'n'.
+// Default state is all '1's to enable all FROs after power-up. Note that they
+// are not actually started up before the CTL.TRNG_EN bit is set to '1'.
+//
+// Bits are automatically forced to '0' here (and cannot be written to '1')
+// while the corresponding bit in ALARMSTOP.FRO_FLAGS has value '1'.
+#define TRNG_FROEN_FRO_MASK_W 24
+#define TRNG_FROEN_FRO_MASK_M 0x00FFFFFF
+#define TRNG_FROEN_FRO_MASK_S 0
+
+//*****************************************************************************
+//
+// Register: TRNG_O_FRODETUNE
+//
+//*****************************************************************************
+// Field: [23:0] FRO_MASK
+//
+// De-tune bits for the individual FROs. A '1' in bit [n] lets FRO 'n' run
+// approximately 5% faster. The value of one of these bits may only be changed
+// while the corresponding FRO is turned off (by temporarily writing a '0' in
+// the corresponding
+// bit of the FROEN.FRO_MASK register).
+#define TRNG_FRODETUNE_FRO_MASK_W 24
+#define TRNG_FRODETUNE_FRO_MASK_M 0x00FFFFFF
+#define TRNG_FRODETUNE_FRO_MASK_S 0
+
+//*****************************************************************************
+//
+// Register: TRNG_O_ALARMMASK
+//
+//*****************************************************************************
+// Field: [23:0] FRO_MASK
+//
+// Logging bits for the 'alarm events' of individual FROs. A '1' in bit [n]
+// indicates FRO 'n' experienced an 'alarm event'.
+#define TRNG_ALARMMASK_FRO_MASK_W 24
+#define TRNG_ALARMMASK_FRO_MASK_M 0x00FFFFFF
+#define TRNG_ALARMMASK_FRO_MASK_S 0
+
+//*****************************************************************************
+//
+// Register: TRNG_O_ALARMSTOP
+//
+//*****************************************************************************
+// Field: [23:0] FRO_FLAGS
+//
+// Logging bits for the 'alarm events' of individual FROs. A '1' in bit [n]
+// indicates FRO 'n' experienced more than one 'alarm event' in quick
+// succession and has been turned off. A '1' in this field forces the
+// corresponding bit in FROEN.FRO_MASK to '0'.
+#define TRNG_ALARMSTOP_FRO_FLAGS_W 24
+#define TRNG_ALARMSTOP_FRO_FLAGS_M 0x00FFFFFF
+#define TRNG_ALARMSTOP_FRO_FLAGS_S 0
+
+//*****************************************************************************
+//
+// Register: TRNG_O_LFSR0
+//
+//*****************************************************************************
+// Field: [31:0] LFSR_31_0
+//
+// Bits [31:0] of the main entropy accumulation LFSR. Register can only be
+// accessed when CTL.TEST_MODE = 1.
+// Register contents will be cleared to zero before access is enabled.
+#define TRNG_LFSR0_LFSR_31_0_W 32
+#define TRNG_LFSR0_LFSR_31_0_M 0xFFFFFFFF
+#define TRNG_LFSR0_LFSR_31_0_S 0
+
+//*****************************************************************************
+//
+// Register: TRNG_O_LFSR1
+//
+//*****************************************************************************
+// Field: [31:0] LFSR_63_32
+//
+// Bits [63:32] of the main entropy accumulation LFSR. Register can only be
+// accessed when CTL.TEST_MODE = 1.
+// Register contents will be cleared to zero before access is enabled.
+#define TRNG_LFSR1_LFSR_63_32_W 32
+#define TRNG_LFSR1_LFSR_63_32_M 0xFFFFFFFF
+#define TRNG_LFSR1_LFSR_63_32_S 0
+
+//*****************************************************************************
+//
+// Register: TRNG_O_LFSR2
+//
+//*****************************************************************************
+// Field: [16:0] LFSR_80_64
+//
+// Bits [80:64] of the main entropy accumulation LFSR. Register can only be
+// accessed when CTL.TEST_MODE = 1.
+// Register contents will be cleared to zero before access is enabled.
+#define TRNG_LFSR2_LFSR_80_64_W 17
+#define TRNG_LFSR2_LFSR_80_64_M 0x0001FFFF
+#define TRNG_LFSR2_LFSR_80_64_S 0
+
+//*****************************************************************************
+//
+// Register: TRNG_O_HWOPT
+//
+//*****************************************************************************
+// Field: [11:6] NR_OF_FROS
+//
+// Number of FROs implemented in this TRNG, value 24 (decimal).
+#define TRNG_HWOPT_NR_OF_FROS_W 6
+#define TRNG_HWOPT_NR_OF_FROS_M 0x00000FC0
+#define TRNG_HWOPT_NR_OF_FROS_S 6
+
+//*****************************************************************************
+//
+// Register: TRNG_O_HWVER0
+//
+//*****************************************************************************
+// Field: [27:24] HW_MAJOR_VER
+//
+// 4 bits binary encoding of the major hardware revision number.
+#define TRNG_HWVER0_HW_MAJOR_VER_W 4
+#define TRNG_HWVER0_HW_MAJOR_VER_M 0x0F000000
+#define TRNG_HWVER0_HW_MAJOR_VER_S 24
+
+// Field: [23:20] HW_MINOR_VER
+//
+// 4 bits binary encoding of the minor hardware revision number.
+#define TRNG_HWVER0_HW_MINOR_VER_W 4
+#define TRNG_HWVER0_HW_MINOR_VER_M 0x00F00000
+#define TRNG_HWVER0_HW_MINOR_VER_S 20
+
+// Field: [19:16] HW_PATCH_LVL
+//
+// 4 bits binary encoding of the hardware patch level, initial release will
+// carry value zero.
+#define TRNG_HWVER0_HW_PATCH_LVL_W 4
+#define TRNG_HWVER0_HW_PATCH_LVL_M 0x000F0000
+#define TRNG_HWVER0_HW_PATCH_LVL_S 16
+
+// Field: [15:8] EIP_NUM_COMPL
+//
+// Bit-by-bit logic complement of bits [7:0]. This TRNG gives 0xB4.
+#define TRNG_HWVER0_EIP_NUM_COMPL_W 8
+#define TRNG_HWVER0_EIP_NUM_COMPL_M 0x0000FF00
+#define TRNG_HWVER0_EIP_NUM_COMPL_S 8
+
+// Field: [7:0] EIP_NUM
+//
+// 8 bits binary encoding of the module number. This TRNG gives 0x4B.
+#define TRNG_HWVER0_EIP_NUM_W 8
+#define TRNG_HWVER0_EIP_NUM_M 0x000000FF
+#define TRNG_HWVER0_EIP_NUM_S 0
+
+//*****************************************************************************
+//
+// Register: TRNG_O_IRQSTATMASK
+//
+//*****************************************************************************
+// Field: [1] SHUTDOWN_OVF
+//
+// Shutdown Overflow (result of IRQFLAGSTAT.SHUTDOWN_OVF AND'ed with
+// IRQFLAGMASK.SHUTDOWN_OVF)
+#define TRNG_IRQSTATMASK_SHUTDOWN_OVF 0x00000002
+#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_BITN 1
+#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_M 0x00000002
+#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_S 1
+
+// Field: [0] RDY
+//
+// New random value available (result of IRQFLAGSTAT.RDY AND'ed with
+// IRQFLAGMASK.RDY)
+#define TRNG_IRQSTATMASK_RDY 0x00000001
+#define TRNG_IRQSTATMASK_RDY_BITN 0
+#define TRNG_IRQSTATMASK_RDY_M 0x00000001
+#define TRNG_IRQSTATMASK_RDY_S 0
+
+//*****************************************************************************
+//
+// Register: TRNG_O_HWVER1
+//
+//*****************************************************************************
+// Field: [7:0] REV
+//
+// The revision number of this module is Rev 2.0.
+#define TRNG_HWVER1_REV_W 8
+#define TRNG_HWVER1_REV_M 0x000000FF
+#define TRNG_HWVER1_REV_S 0
+
+//*****************************************************************************
+//
+// Register: TRNG_O_IRQSET
+//
+//*****************************************************************************
+//*****************************************************************************
+//
+// Register: TRNG_O_SWRESET
+//
+//*****************************************************************************
+// Field: [0] RESET
+//
+// Write '1' to soft reset , reset will be low for 4-5 clock cycles. Poll to 0
+// for reset to be completed.
+#define TRNG_SWRESET_RESET 0x00000001
+#define TRNG_SWRESET_RESET_BITN 0
+#define TRNG_SWRESET_RESET_M 0x00000001
+#define TRNG_SWRESET_RESET_S 0
+
+//*****************************************************************************
+//
+// Register: TRNG_O_IRQSTAT
+//
+//*****************************************************************************
+// Field: [0] STAT
+//
+// TRNG Interrupt status. OR'ed version of IRQFLAGSTAT.SHUTDOWN_OVF and
+// IRQFLAGSTAT.RDY
+#define TRNG_IRQSTAT_STAT 0x00000001
+#define TRNG_IRQSTAT_STAT_BITN 0
+#define TRNG_IRQSTAT_STAT_M 0x00000001
+#define TRNG_IRQSTAT_STAT_S 0
+
+
+#endif // __TRNG__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_types.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_types.h
new file mode 100644
index 0000000..3f6fe14
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_types.h
@@ -0,0 +1,123 @@
+/******************************************************************************
+* Filename: hw_types.h
+* Revised: 2016-09-13 14:21:40 +0200 (Tue, 13 Sep 2016)
+* Revision: 47152
+*
+* Description: Common types and macros.
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_TYPES_H__
+#define __HW_TYPES_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "../inc/hw_chip_def.h"
+
+//*****************************************************************************
+//
+// Common driverlib types
+//
+//*****************************************************************************
+typedef void (* FPTR_VOID_VOID_T) (void);
+typedef void (* FPTR_VOID_UINT8_T) (uint8_t);
+
+//*****************************************************************************
+//
+// This symbol forces simple driverlib functions to be inlined in the code
+// instead of using function calls.
+//
+//*****************************************************************************
+#ifndef __STATIC_INLINE
+#define __STATIC_INLINE static inline
+#endif
+
+//*****************************************************************************
+//
+// C99 types only allows bitfield defintions on certain datatypes.
+//
+//*****************************************************************************
+typedef unsigned int __UINT32;
+
+//*****************************************************************************
+//
+// Macros for direct hardware access.
+//
+// If using these macros the programmer should be aware of any limitations to
+// the address accessed i.e. if it supports word and/or byte access.
+//
+//*****************************************************************************
+// Word (32 bit) access to address x
+// Read example : my32BitVar = HWREG(base_addr + offset) ;
+// Write example : HWREG(base_addr + offset) = my32BitVar ;
+#define HWREG(x) \
+ (*((volatile unsigned long *)(x)))
+
+// Half word (16 bit) access to address x
+// Read example : my16BitVar = HWREGH(base_addr + offset) ;
+// Write example : HWREGH(base_addr + offset) = my16BitVar ;
+#define HWREGH(x) \
+ (*((volatile unsigned short *)(x)))
+
+// Byte (8 bit) access to address x
+// Read example : my8BitVar = HWREGB(base_addr + offset) ;
+// Write example : HWREGB(base_addr + offset) = my8BitVar ;
+#define HWREGB(x) \
+ (*((volatile unsigned char *)(x)))
+
+//*****************************************************************************
+//
+// Macros for hardware access to bit-band supported addresses via the bit-band region.
+//
+// Macros calculate the corresponding address to access in the bit-band region
+// based on the actual address of the memory/register and the bit number.
+//
+// Do NOT use these macros to access the bit-band region directly!
+//
+//*****************************************************************************
+// Bit-band access to address x bit number b using word access (32 bit)
+#define HWREGBITW(x, b) \
+ HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+
+// Bit-band access to address x bit number b using half word access (16 bit)
+#define HWREGBITH(x, b) \
+ HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+
+// Bit-band access to address x bit number b using byte access (8 bit)
+#define HWREGBITB(x, b) \
+ HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+
+
+#endif // __HW_TYPES_H__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_uart.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_uart.h
new file mode 100644
index 0000000..b35541f
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_uart.h
@@ -0,0 +1,1087 @@
+/******************************************************************************
+* Filename: hw_uart_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_UART_H__
+#define __HW_UART_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// UART component
+//
+//*****************************************************************************
+// Data
+#define UART_O_DR 0x00000000
+
+// Status
+#define UART_O_RSR 0x00000004
+
+// Error Clear
+#define UART_O_ECR 0x00000004
+
+// Flag
+#define UART_O_FR 0x00000018
+
+// Integer Baud-Rate Divisor
+#define UART_O_IBRD 0x00000024
+
+// Fractional Baud-Rate Divisor
+#define UART_O_FBRD 0x00000028
+
+// Line Control
+#define UART_O_LCRH 0x0000002C
+
+// Control
+#define UART_O_CTL 0x00000030
+
+// Interrupt FIFO Level Select
+#define UART_O_IFLS 0x00000034
+
+// Interrupt Mask Set/Clear
+#define UART_O_IMSC 0x00000038
+
+// Raw Interrupt Status
+#define UART_O_RIS 0x0000003C
+
+// Masked Interrupt Status
+#define UART_O_MIS 0x00000040
+
+// Interrupt Clear
+#define UART_O_ICR 0x00000044
+
+// DMA Control
+#define UART_O_DMACTL 0x00000048
+
+//*****************************************************************************
+//
+// Register: UART_O_DR
+//
+//*****************************************************************************
+// Field: [11] OE
+//
+// UART Overrun Error:
+// This bit is set to 1 if data is received and the receive FIFO is already
+// full. The FIFO contents remain valid because no more data is written when
+// the FIFO is full, , only the contents of the shift register are overwritten.
+// This is cleared to 0 once there is an empty space in the FIFO and a new
+// character can be written to it.
+#define UART_DR_OE 0x00000800
+#define UART_DR_OE_BITN 11
+#define UART_DR_OE_M 0x00000800
+#define UART_DR_OE_S 11
+
+// Field: [10] BE
+//
+// UART Break Error:
+// This bit is set to 1 if a break condition was detected, indicating that the
+// received data input (UARTRXD input pin) was held LOW for longer than a
+// full-word transmission time (defined as start, data, parity and stop bits).
+// In FIFO mode, this error is associated with the character at the top of the
+// FIFO (that is., the oldest received data character since last read). When a
+// break occurs, a 0 character is loaded into the FIFO. The next character is
+// enabled after the receive data input (UARTRXD input pin) goes to a 1
+// (marking state), and the next valid start bit is received.
+#define UART_DR_BE 0x00000400
+#define UART_DR_BE_BITN 10
+#define UART_DR_BE_M 0x00000400
+#define UART_DR_BE_S 10
+
+// Field: [9] PE
+//
+// UART Parity Error:
+// When set to 1, it indicates that the parity of the received data character
+// does not match the parity that the LCRH.EPS and LCRH.SPS select.
+// In FIFO mode, this error is associated with the character at the top of the
+// FIFO (that is, the oldest received data character since last read).
+#define UART_DR_PE 0x00000200
+#define UART_DR_PE_BITN 9
+#define UART_DR_PE_M 0x00000200
+#define UART_DR_PE_S 9
+
+// Field: [8] FE
+//
+// UART Framing Error:
+// When set to 1, it indicates that the received character did not have a valid
+// stop bit (a valid stop bit is 1).
+// In FIFO mode, this error is associated with the character at the top of the
+// FIFO (that is., the oldest received data character since last read).
+#define UART_DR_FE 0x00000100
+#define UART_DR_FE_BITN 8
+#define UART_DR_FE_M 0x00000100
+#define UART_DR_FE_S 8
+
+// Field: [7:0] DATA
+//
+// Data transmitted or received:
+// On writes, the transmit data character is pushed into the FIFO.
+// On reads, the oldest received data character since the last read is
+// returned.
+#define UART_DR_DATA_W 8
+#define UART_DR_DATA_M 0x000000FF
+#define UART_DR_DATA_S 0
+
+//*****************************************************************************
+//
+// Register: UART_O_RSR
+//
+//*****************************************************************************
+// Field: [3] OE
+//
+// UART Overrun Error:
+// This bit is set to 1 if data is received and the receive FIFO is already
+// full. The FIFO contents remain valid because no more data is written when
+// the FIFO is full, , only the contents of the shift register are overwritten.
+// This is cleared to 0 once there is an empty space in the FIFO and a new
+// character can be written to it.
+#define UART_RSR_OE 0x00000008
+#define UART_RSR_OE_BITN 3
+#define UART_RSR_OE_M 0x00000008
+#define UART_RSR_OE_S 3
+
+// Field: [2] BE
+//
+// UART Break Error:
+// This bit is set to 1 if a break condition was detected, indicating that the
+// received data input (UARTRXD input pin) was held LOW for longer than a
+// full-word transmission time (defined as start, data, parity and stop bits).
+// When a break occurs, a 0 character is loaded into the FIFO. The next
+// character is enabled after the receive data input (UARTRXD input pin) goes
+// to a 1 (marking state), and the next valid start bit is received.
+#define UART_RSR_BE 0x00000004
+#define UART_RSR_BE_BITN 2
+#define UART_RSR_BE_M 0x00000004
+#define UART_RSR_BE_S 2
+
+// Field: [1] PE
+//
+// UART Parity Error:
+// When set to 1, it indicates that the parity of the received data character
+// does not match the parity that the LCRH.EPS and LCRH.SPS select.
+#define UART_RSR_PE 0x00000002
+#define UART_RSR_PE_BITN 1
+#define UART_RSR_PE_M 0x00000002
+#define UART_RSR_PE_S 1
+
+// Field: [0] FE
+//
+// UART Framing Error:
+// When set to 1, it indicates that the received character did not have a valid
+// stop bit (a valid stop bit is 1).
+#define UART_RSR_FE 0x00000001
+#define UART_RSR_FE_BITN 0
+#define UART_RSR_FE_M 0x00000001
+#define UART_RSR_FE_S 0
+
+//*****************************************************************************
+//
+// Register: UART_O_ECR
+//
+//*****************************************************************************
+// Field: [3] OE
+//
+// The framing (FE), parity (PE), break (BE) and overrun (OE) errors are
+// cleared to 0 by any write to this register.
+#define UART_ECR_OE 0x00000008
+#define UART_ECR_OE_BITN 3
+#define UART_ECR_OE_M 0x00000008
+#define UART_ECR_OE_S 3
+
+// Field: [2] BE
+//
+// The framing (FE), parity (PE), break (BE) and overrun (OE) errors are
+// cleared to 0 by any write to this register.
+#define UART_ECR_BE 0x00000004
+#define UART_ECR_BE_BITN 2
+#define UART_ECR_BE_M 0x00000004
+#define UART_ECR_BE_S 2
+
+// Field: [1] PE
+//
+// The framing (FE), parity (PE), break (BE) and overrun (OE) errors are
+// cleared to 0 by any write to this register.
+#define UART_ECR_PE 0x00000002
+#define UART_ECR_PE_BITN 1
+#define UART_ECR_PE_M 0x00000002
+#define UART_ECR_PE_S 1
+
+// Field: [0] FE
+//
+// The framing (FE), parity (PE), break (BE) and overrun (OE) errors are
+// cleared to 0 by any write to this register.
+#define UART_ECR_FE 0x00000001
+#define UART_ECR_FE_BITN 0
+#define UART_ECR_FE_M 0x00000001
+#define UART_ECR_FE_S 0
+
+//*****************************************************************************
+//
+// Register: UART_O_FR
+//
+//*****************************************************************************
+// Field: [7] TXFE
+//
+// UART Transmit FIFO Empty:
+// The meaning of this bit depends on the state of LCRH.FEN .
+// - If the FIFO is disabled, this bit is set when the transmit holding
+// register is empty.
+// - If the FIFO is enabled, this bit is set when the transmit FIFO is empty.
+// This bit does not indicate if there is data in the transmit shift register.
+#define UART_FR_TXFE 0x00000080
+#define UART_FR_TXFE_BITN 7
+#define UART_FR_TXFE_M 0x00000080
+#define UART_FR_TXFE_S 7
+
+// Field: [6] RXFF
+//
+// UART Receive FIFO Full:
+// The meaning of this bit depends on the state of LCRH.FEN.
+// - If the FIFO is disabled, this bit is set when the receive holding
+// register is full.
+// - If the FIFO is enabled, this bit is set when the receive FIFO is full.
+#define UART_FR_RXFF 0x00000040
+#define UART_FR_RXFF_BITN 6
+#define UART_FR_RXFF_M 0x00000040
+#define UART_FR_RXFF_S 6
+
+// Field: [5] TXFF
+//
+// UART Transmit FIFO Full:
+// Transmit FIFO full. The meaning of this bit depends on the state of
+// LCRH.FEN.
+// - If the FIFO is disabled, this bit is set when the transmit holding
+// register is full.
+// - If the FIFO is enabled, this bit is set when the transmit FIFO is full.
+#define UART_FR_TXFF 0x00000020
+#define UART_FR_TXFF_BITN 5
+#define UART_FR_TXFF_M 0x00000020
+#define UART_FR_TXFF_S 5
+
+// Field: [4] RXFE
+//
+// UART Receive FIFO Empty:
+// Receive FIFO empty. The meaning of this bit depends on the state of
+// LCRH.FEN.
+// - If the FIFO is disabled, this bit is set when the receive holding
+// register is empty.
+// - If the FIFO is enabled, this bit is set when the receive FIFO is empty.
+#define UART_FR_RXFE 0x00000010
+#define UART_FR_RXFE_BITN 4
+#define UART_FR_RXFE_M 0x00000010
+#define UART_FR_RXFE_S 4
+
+// Field: [3] BUSY
+//
+// UART Busy:
+// If this bit is set to 1, the UART is busy transmitting data. This bit
+// remains set until the complete byte, including all the stop bits, has been
+// sent from the shift register.
+// This bit is set as soon as the transmit FIFO becomes non-empty, regardless
+// of whether the UART is enabled or not.
+#define UART_FR_BUSY 0x00000008
+#define UART_FR_BUSY_BITN 3
+#define UART_FR_BUSY_M 0x00000008
+#define UART_FR_BUSY_S 3
+
+// Field: [0] CTS
+//
+// Clear To Send:
+// This bit is the complement of the active-low UART CTS input pin.
+// That is, the bit is 1 when CTS input pin is LOW.
+#define UART_FR_CTS 0x00000001
+#define UART_FR_CTS_BITN 0
+#define UART_FR_CTS_M 0x00000001
+#define UART_FR_CTS_S 0
+
+//*****************************************************************************
+//
+// Register: UART_O_IBRD
+//
+//*****************************************************************************
+// Field: [15:0] DIVINT
+//
+// The integer baud rate divisor:
+// The baud rate divisor is calculated using the formula below:
+// Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate)
+// Baud rate divisor must be minimum 1 and maximum 65535.
+// That is, DIVINT=0 does not give a valid baud rate.
+// Similarly, if DIVINT=0xFFFF, any non-zero values in FBRD.DIVFRAC will be
+// illegal.
+// A valid value must be written to this field before the UART can be used for
+// RX or TX operations.
+#define UART_IBRD_DIVINT_W 16
+#define UART_IBRD_DIVINT_M 0x0000FFFF
+#define UART_IBRD_DIVINT_S 0
+
+//*****************************************************************************
+//
+// Register: UART_O_FBRD
+//
+//*****************************************************************************
+// Field: [5:0] DIVFRAC
+//
+// Fractional Baud-Rate Divisor:
+// The baud rate divisor is calculated using the formula below:
+// Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate)
+// Baud rate divisor must be minimum 1 and maximum 65535.
+// That is, IBRD.DIVINT=0 does not give a valid baud rate.
+// Similarly, if IBRD.DIVINT=0xFFFF, any non-zero values in DIVFRAC will be
+// illegal.
+// A valid value must be written to this field before the UART can be used for
+// RX or TX operations.
+#define UART_FBRD_DIVFRAC_W 6
+#define UART_FBRD_DIVFRAC_M 0x0000003F
+#define UART_FBRD_DIVFRAC_S 0
+
+//*****************************************************************************
+//
+// Register: UART_O_LCRH
+//
+//*****************************************************************************
+// Field: [7] SPS
+//
+// UART Stick Parity Select:
+//
+// 0: Stick parity is disabled
+// 1: The parity bit is transmitted and checked as invert of EPS field (i.e.
+// the parity bit is transmitted and checked as 1 when EPS = 0).
+//
+// This bit has no effect when PEN disables parity checking and generation.
+#define UART_LCRH_SPS 0x00000080
+#define UART_LCRH_SPS_BITN 7
+#define UART_LCRH_SPS_M 0x00000080
+#define UART_LCRH_SPS_S 7
+
+// Field: [6:5] WLEN
+//
+// UART Word Length:
+// These bits indicate the number of data bits transmitted or received in a
+// frame.
+// ENUMs:
+// 8 Word Length 8 bits
+// 7 Word Length 7 bits
+// 6 Word Length 6 bits
+// 5 Word Length 5 bits
+#define UART_LCRH_WLEN_W 2
+#define UART_LCRH_WLEN_M 0x00000060
+#define UART_LCRH_WLEN_S 5
+#define UART_LCRH_WLEN_8 0x00000060
+#define UART_LCRH_WLEN_7 0x00000040
+#define UART_LCRH_WLEN_6 0x00000020
+#define UART_LCRH_WLEN_5 0x00000000
+
+// Field: [4] FEN
+//
+// UART Enable FIFOs
+// ENUMs:
+// EN Transmit and receive FIFO buffers are enabled
+// (FIFO mode)
+// DIS FIFOs are disabled (character mode) that is, the
+// FIFOs become 1-byte-deep holding registers.
+#define UART_LCRH_FEN 0x00000010
+#define UART_LCRH_FEN_BITN 4
+#define UART_LCRH_FEN_M 0x00000010
+#define UART_LCRH_FEN_S 4
+#define UART_LCRH_FEN_EN 0x00000010
+#define UART_LCRH_FEN_DIS 0x00000000
+
+// Field: [3] STP2
+//
+// UART Two Stop Bits Select:
+// If this bit is set to 1, two stop bits are transmitted at the end of the
+// frame. The receive logic does not check for two stop bits being received.
+#define UART_LCRH_STP2 0x00000008
+#define UART_LCRH_STP2_BITN 3
+#define UART_LCRH_STP2_M 0x00000008
+#define UART_LCRH_STP2_S 3
+
+// Field: [2] EPS
+//
+// UART Even Parity Select
+// ENUMs:
+// EVEN Even parity: The UART generates or checks for an
+// even number of 1s in the data and parity bits.
+// ODD Odd parity: The UART generates or checks for an
+// odd number of 1s in the data and parity bits.
+#define UART_LCRH_EPS 0x00000004
+#define UART_LCRH_EPS_BITN 2
+#define UART_LCRH_EPS_M 0x00000004
+#define UART_LCRH_EPS_S 2
+#define UART_LCRH_EPS_EVEN 0x00000004
+#define UART_LCRH_EPS_ODD 0x00000000
+
+// Field: [1] PEN
+//
+// UART Parity Enable
+// This bit controls generation and checking of parity bit.
+// ENUMs:
+// EN Parity checking and generation is enabled.
+// DIS Parity is disabled and no parity bit is added to
+// the data frame
+#define UART_LCRH_PEN 0x00000002
+#define UART_LCRH_PEN_BITN 1
+#define UART_LCRH_PEN_M 0x00000002
+#define UART_LCRH_PEN_S 1
+#define UART_LCRH_PEN_EN 0x00000002
+#define UART_LCRH_PEN_DIS 0x00000000
+
+// Field: [0] BRK
+//
+// UART Send Break
+// If this bit is set to 1, a low-level is continually output on the UARTTXD
+// output pin, after completing transmission of the current character. For the
+// proper execution of the break command, the
+// software must set this bit for at least two complete frames. For normal use,
+// this bit must be cleared to 0.
+#define UART_LCRH_BRK 0x00000001
+#define UART_LCRH_BRK_BITN 0
+#define UART_LCRH_BRK_M 0x00000001
+#define UART_LCRH_BRK_S 0
+
+//*****************************************************************************
+//
+// Register: UART_O_CTL
+//
+//*****************************************************************************
+// Field: [15] CTSEN
+//
+// CTS hardware flow control enable
+// ENUMs:
+// EN CTS hardware flow control enabled
+// DIS CTS hardware flow control disabled
+#define UART_CTL_CTSEN 0x00008000
+#define UART_CTL_CTSEN_BITN 15
+#define UART_CTL_CTSEN_M 0x00008000
+#define UART_CTL_CTSEN_S 15
+#define UART_CTL_CTSEN_EN 0x00008000
+#define UART_CTL_CTSEN_DIS 0x00000000
+
+// Field: [14] RTSEN
+//
+// RTS hardware flow control enable
+// ENUMs:
+// EN RTS hardware flow control enabled
+// DIS RTS hardware flow control disabled
+#define UART_CTL_RTSEN 0x00004000
+#define UART_CTL_RTSEN_BITN 14
+#define UART_CTL_RTSEN_M 0x00004000
+#define UART_CTL_RTSEN_S 14
+#define UART_CTL_RTSEN_EN 0x00004000
+#define UART_CTL_RTSEN_DIS 0x00000000
+
+// Field: [11] RTS
+//
+// Request to Send
+// This bit is the complement of the active-low UART RTS output. That is, when
+// the bit is programmed to a 1 then RTS output on the pins is LOW.
+#define UART_CTL_RTS 0x00000800
+#define UART_CTL_RTS_BITN 11
+#define UART_CTL_RTS_M 0x00000800
+#define UART_CTL_RTS_S 11
+
+// Field: [9] RXE
+//
+// UART Receive Enable
+// If the UART is disabled in the middle of reception, it completes the current
+// character before stopping.
+// ENUMs:
+// EN UART Receive enabled
+// DIS UART Receive disabled
+#define UART_CTL_RXE 0x00000200
+#define UART_CTL_RXE_BITN 9
+#define UART_CTL_RXE_M 0x00000200
+#define UART_CTL_RXE_S 9
+#define UART_CTL_RXE_EN 0x00000200
+#define UART_CTL_RXE_DIS 0x00000000
+
+// Field: [8] TXE
+//
+// UART Transmit Enable
+// If the UART is disabled in the middle of transmission, it completes the
+// current character before stopping.
+// ENUMs:
+// EN UART Transmit enabled
+// DIS UART Transmit disabled
+#define UART_CTL_TXE 0x00000100
+#define UART_CTL_TXE_BITN 8
+#define UART_CTL_TXE_M 0x00000100
+#define UART_CTL_TXE_S 8
+#define UART_CTL_TXE_EN 0x00000100
+#define UART_CTL_TXE_DIS 0x00000000
+
+// Field: [7] LBE
+//
+// UART Loop Back Enable:
+// Enabling the loop-back mode connects the UARTTXD output from the UART to
+// UARTRXD input of the UART.
+// ENUMs:
+// EN Loop Back enabled
+// DIS Loop Back disabled
+#define UART_CTL_LBE 0x00000080
+#define UART_CTL_LBE_BITN 7
+#define UART_CTL_LBE_M 0x00000080
+#define UART_CTL_LBE_S 7
+#define UART_CTL_LBE_EN 0x00000080
+#define UART_CTL_LBE_DIS 0x00000000
+
+// Field: [0] UARTEN
+//
+// UART Enable
+// ENUMs:
+// EN UART enabled
+// DIS UART disabled
+#define UART_CTL_UARTEN 0x00000001
+#define UART_CTL_UARTEN_BITN 0
+#define UART_CTL_UARTEN_M 0x00000001
+#define UART_CTL_UARTEN_S 0
+#define UART_CTL_UARTEN_EN 0x00000001
+#define UART_CTL_UARTEN_DIS 0x00000000
+
+//*****************************************************************************
+//
+// Register: UART_O_IFLS
+//
+//*****************************************************************************
+// Field: [5:3] RXSEL
+//
+// Receive interrupt FIFO level select:
+// This field sets the trigger points for the receive interrupt. Values
+// 0b101-0b111 are reserved.
+// ENUMs:
+// 7_8 Receive FIFO becomes >= 7/8 full
+// 6_8 Receive FIFO becomes >= 3/4 full
+// 4_8 Receive FIFO becomes >= 1/2 full
+// 2_8 Receive FIFO becomes >= 1/4 full
+// 1_8 Receive FIFO becomes >= 1/8 full
+#define UART_IFLS_RXSEL_W 3
+#define UART_IFLS_RXSEL_M 0x00000038
+#define UART_IFLS_RXSEL_S 3
+#define UART_IFLS_RXSEL_7_8 0x00000020
+#define UART_IFLS_RXSEL_6_8 0x00000018
+#define UART_IFLS_RXSEL_4_8 0x00000010
+#define UART_IFLS_RXSEL_2_8 0x00000008
+#define UART_IFLS_RXSEL_1_8 0x00000000
+
+// Field: [2:0] TXSEL
+//
+// Transmit interrupt FIFO level select:
+// This field sets the trigger points for the transmit interrupt. Values
+// 0b101-0b111 are reserved.
+// ENUMs:
+// 7_8 Transmit FIFO becomes <= 7/8 full
+// 6_8 Transmit FIFO becomes <= 3/4 full
+// 4_8 Transmit FIFO becomes <= 1/2 full
+// 2_8 Transmit FIFO becomes <= 1/4 full
+// 1_8 Transmit FIFO becomes <= 1/8 full
+#define UART_IFLS_TXSEL_W 3
+#define UART_IFLS_TXSEL_M 0x00000007
+#define UART_IFLS_TXSEL_S 0
+#define UART_IFLS_TXSEL_7_8 0x00000004
+#define UART_IFLS_TXSEL_6_8 0x00000003
+#define UART_IFLS_TXSEL_4_8 0x00000002
+#define UART_IFLS_TXSEL_2_8 0x00000001
+#define UART_IFLS_TXSEL_1_8 0x00000000
+
+//*****************************************************************************
+//
+// Register: UART_O_IMSC
+//
+//*****************************************************************************
+// Field: [11] EOTIM
+//
+// End of Transmission interrupt mask. A read returns the current mask for
+// UART's EoT interrupt. On a write of 1, the mask of the EoT interrupt is set
+// which means the interrupt state will be reflected in MIS.EOTMIS. A write of
+// 0 clears the mask which means MIS.EOTMIS will not reflect the interrupt.
+#define UART_IMSC_EOTIM 0x00000800
+#define UART_IMSC_EOTIM_BITN 11
+#define UART_IMSC_EOTIM_M 0x00000800
+#define UART_IMSC_EOTIM_S 11
+
+// Field: [10] OEIM
+//
+// Overrun error interrupt mask. A read returns the current mask for UART's
+// overrun error interrupt. On a write of 1, the mask of the overrun error
+// interrupt is set which means the interrupt state will be reflected in
+// MIS.OEMIS. A write of 0 clears the mask which means MIS.OEMIS will not
+// reflect the interrupt.
+#define UART_IMSC_OEIM 0x00000400
+#define UART_IMSC_OEIM_BITN 10
+#define UART_IMSC_OEIM_M 0x00000400
+#define UART_IMSC_OEIM_S 10
+
+// Field: [9] BEIM
+//
+// Break error interrupt mask. A read returns the current mask for UART's break
+// error interrupt. On a write of 1, the mask of the overrun error interrupt is
+// set which means the interrupt state will be reflected in MIS.BEMIS. A write
+// of 0 clears the mask which means MIS.BEMIS will not reflect the interrupt.
+#define UART_IMSC_BEIM 0x00000200
+#define UART_IMSC_BEIM_BITN 9
+#define UART_IMSC_BEIM_M 0x00000200
+#define UART_IMSC_BEIM_S 9
+
+// Field: [8] PEIM
+//
+// Parity error interrupt mask. A read returns the current mask for UART's
+// parity error interrupt. On a write of 1, the mask of the overrun error
+// interrupt is set which means the interrupt state will be reflected in
+// MIS.PEMIS. A write of 0 clears the mask which means MIS.PEMIS will not
+// reflect the interrupt.
+#define UART_IMSC_PEIM 0x00000100
+#define UART_IMSC_PEIM_BITN 8
+#define UART_IMSC_PEIM_M 0x00000100
+#define UART_IMSC_PEIM_S 8
+
+// Field: [7] FEIM
+//
+// Framing error interrupt mask. A read returns the current mask for UART's
+// framing error interrupt. On a write of 1, the mask of the overrun error
+// interrupt is set which means the interrupt state will be reflected in
+// MIS.FEMIS. A write of 0 clears the mask which means MIS.FEMIS will not
+// reflect the interrupt.
+#define UART_IMSC_FEIM 0x00000080
+#define UART_IMSC_FEIM_BITN 7
+#define UART_IMSC_FEIM_M 0x00000080
+#define UART_IMSC_FEIM_S 7
+
+// Field: [6] RTIM
+//
+// Receive timeout interrupt mask. A read returns the current mask for UART's
+// receive timeout interrupt. On a write of 1, the mask of the overrun error
+// interrupt is set which means the interrupt state will be reflected in
+// MIS.RTMIS. A write of 0 clears the mask which means this bitfield will not
+// reflect the interrupt.
+// The raw interrupt for receive timeout RIS.RTRIS cannot be set unless the
+// mask is set (RTIM = 1). This is because the mask acts as an enable for power
+// saving. That is, the same status can be read from MIS.RTMIS and RIS.RTRIS.
+#define UART_IMSC_RTIM 0x00000040
+#define UART_IMSC_RTIM_BITN 6
+#define UART_IMSC_RTIM_M 0x00000040
+#define UART_IMSC_RTIM_S 6
+
+// Field: [5] TXIM
+//
+// Transmit interrupt mask. A read returns the current mask for UART's transmit
+// interrupt. On a write of 1, the mask of the overrun error interrupt is set
+// which means the interrupt state will be reflected in MIS.TXMIS. A write of 0
+// clears the mask which means MIS.TXMIS will not reflect the interrupt.
+#define UART_IMSC_TXIM 0x00000020
+#define UART_IMSC_TXIM_BITN 5
+#define UART_IMSC_TXIM_M 0x00000020
+#define UART_IMSC_TXIM_S 5
+
+// Field: [4] RXIM
+//
+// Receive interrupt mask. A read returns the current mask for UART's receive
+// interrupt. On a write of 1, the mask of the overrun error interrupt is set
+// which means the interrupt state will be reflected in MIS.RXMIS. A write of 0
+// clears the mask which means MIS.RXMIS will not reflect the interrupt.
+#define UART_IMSC_RXIM 0x00000010
+#define UART_IMSC_RXIM_BITN 4
+#define UART_IMSC_RXIM_M 0x00000010
+#define UART_IMSC_RXIM_S 4
+
+// Field: [1] CTSMIM
+//
+// Clear to Send (CTS) modem interrupt mask. A read returns the current mask
+// for UART's clear to send interrupt. On a write of 1, the mask of the overrun
+// error interrupt is set which means the interrupt state will be reflected in
+// MIS.CTSMMIS. A write of 0 clears the mask which means MIS.CTSMMIS will not
+// reflect the interrupt.
+#define UART_IMSC_CTSMIM 0x00000002
+#define UART_IMSC_CTSMIM_BITN 1
+#define UART_IMSC_CTSMIM_M 0x00000002
+#define UART_IMSC_CTSMIM_S 1
+
+//*****************************************************************************
+//
+// Register: UART_O_RIS
+//
+//*****************************************************************************
+// Field: [11] EOTRIS
+//
+// End of Transmission interrupt status:
+// This field returns the raw interrupt state of UART's end of transmission
+// interrupt. End of transmission flag is set when all the Transmit data in the
+// FIFO and on the TX Line is tranmitted.
+#define UART_RIS_EOTRIS 0x00000800
+#define UART_RIS_EOTRIS_BITN 11
+#define UART_RIS_EOTRIS_M 0x00000800
+#define UART_RIS_EOTRIS_S 11
+
+// Field: [10] OERIS
+//
+// Overrun error interrupt status:
+// This field returns the raw interrupt state of UART's overrun error
+// interrupt. Overrun error occurs if data is received and the receive FIFO is
+// full.
+#define UART_RIS_OERIS 0x00000400
+#define UART_RIS_OERIS_BITN 10
+#define UART_RIS_OERIS_M 0x00000400
+#define UART_RIS_OERIS_S 10
+
+// Field: [9] BERIS
+//
+// Break error interrupt status:
+// This field returns the raw interrupt state of UART's break error interrupt.
+// Break error is set when a break condition is detected, indicating that the
+// received data input (UARTRXD input pin) was held LOW for longer than a
+// full-word transmission time (defined as start, data, parity and stop bits).
+#define UART_RIS_BERIS 0x00000200
+#define UART_RIS_BERIS_BITN 9
+#define UART_RIS_BERIS_M 0x00000200
+#define UART_RIS_BERIS_S 9
+
+// Field: [8] PERIS
+//
+// Parity error interrupt status:
+// This field returns the raw interrupt state of UART's parity error interrupt.
+// Parity error is set if the parity of the received data character does not
+// match the parity that the LCRH.EPS and LCRH.SPS select.
+#define UART_RIS_PERIS 0x00000100
+#define UART_RIS_PERIS_BITN 8
+#define UART_RIS_PERIS_M 0x00000100
+#define UART_RIS_PERIS_S 8
+
+// Field: [7] FERIS
+//
+// Framing error interrupt status:
+// This field returns the raw interrupt state of UART's framing error
+// interrupt. Framing error is set if the received character does not have a
+// valid stop bit (a valid stop bit is 1).
+#define UART_RIS_FERIS 0x00000080
+#define UART_RIS_FERIS_BITN 7
+#define UART_RIS_FERIS_M 0x00000080
+#define UART_RIS_FERIS_S 7
+
+// Field: [6] RTRIS
+//
+// Receive timeout interrupt status:
+// This field returns the raw interrupt state of UART's receive timeout
+// interrupt. The receive timeout interrupt is asserted when the receive FIFO
+// is not empty, and no more data is received during a 32-bit period. The
+// receive timeout interrupt is cleared either when the FIFO becomes empty
+// through reading all the data, or when a 1 is written to ICR.RTIC.
+// The raw interrupt for receive timeout cannot be set unless the mask is set
+// (IMSC.RTIM = 1). This is because the mask acts as an enable for power
+// saving. That is, the same status can be read from MIS.RTMIS and RTRIS.
+#define UART_RIS_RTRIS 0x00000040
+#define UART_RIS_RTRIS_BITN 6
+#define UART_RIS_RTRIS_M 0x00000040
+#define UART_RIS_RTRIS_S 6
+
+// Field: [5] TXRIS
+//
+// Transmit interrupt status:
+// This field returns the raw interrupt state of UART's transmit interrupt.
+// When FIFOs are enabled (LCRH.FEN = 1), the transmit interrupt is asserted if
+// the number of bytes in transmit FIFO is equal to or lower than the
+// programmed trigger level (IFLS.TXSEL). The transmit interrupt is cleared by
+// writing data to the transmit FIFO until it becomes greater than the trigger
+// level, or by clearing the interrupt through ICR.TXIC.
+// When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth of one
+// location, the transmit interrupt is asserted if there is no data present in
+// the transmitters single location. It is cleared by performing a single write
+// to the transmit FIFO, or by clearing the interrupt through ICR.TXIC.
+#define UART_RIS_TXRIS 0x00000020
+#define UART_RIS_TXRIS_BITN 5
+#define UART_RIS_TXRIS_M 0x00000020
+#define UART_RIS_TXRIS_S 5
+
+// Field: [4] RXRIS
+//
+// Receive interrupt status:
+// This field returns the raw interrupt state of UART's receive interrupt.
+// When FIFOs are enabled (LCRH.FEN = 1), the receive interrupt is asserted if
+// the receive FIFO reaches the programmed trigger
+// level (IFLS.RXSEL). The receive interrupt is cleared by reading data from
+// the receive FIFO until it becomes less than the trigger level, or by
+// clearing the interrupt through ICR.RXIC.
+// When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth of one
+// location, the receive interrupt is asserted if data is received
+// thereby filling the location. The receive interrupt is cleared by performing
+// a single read of the receive FIFO, or by clearing the interrupt through
+// ICR.RXIC.
+#define UART_RIS_RXRIS 0x00000010
+#define UART_RIS_RXRIS_BITN 4
+#define UART_RIS_RXRIS_M 0x00000010
+#define UART_RIS_RXRIS_S 4
+
+// Field: [1] CTSRMIS
+//
+// Clear to Send (CTS) modem interrupt status:
+// This field returns the raw interrupt state of UART's clear to send
+// interrupt.
+#define UART_RIS_CTSRMIS 0x00000002
+#define UART_RIS_CTSRMIS_BITN 1
+#define UART_RIS_CTSRMIS_M 0x00000002
+#define UART_RIS_CTSRMIS_S 1
+
+//*****************************************************************************
+//
+// Register: UART_O_MIS
+//
+//*****************************************************************************
+// Field: [11] EOTMIS
+//
+// End of Transmission interrupt status:
+// This field returns the masked interrupt state of the overrun interrupt which
+// is the AND product of raw interrupt state RIS.EOTRIS and the mask setting
+// IMSC.EOTIM.
+#define UART_MIS_EOTMIS 0x00000800
+#define UART_MIS_EOTMIS_BITN 11
+#define UART_MIS_EOTMIS_M 0x00000800
+#define UART_MIS_EOTMIS_S 11
+
+// Field: [10] OEMIS
+//
+// Overrun error masked interrupt status:
+// This field returns the masked interrupt state of the overrun interrupt which
+// is the AND product of raw interrupt state RIS.OERIS and the mask setting
+// IMSC.OEIM.
+#define UART_MIS_OEMIS 0x00000400
+#define UART_MIS_OEMIS_BITN 10
+#define UART_MIS_OEMIS_M 0x00000400
+#define UART_MIS_OEMIS_S 10
+
+// Field: [9] BEMIS
+//
+// Break error masked interrupt status:
+// This field returns the masked interrupt state of the break error interrupt
+// which is the AND product of raw interrupt state RIS.BERIS and the mask
+// setting IMSC.BEIM.
+#define UART_MIS_BEMIS 0x00000200
+#define UART_MIS_BEMIS_BITN 9
+#define UART_MIS_BEMIS_M 0x00000200
+#define UART_MIS_BEMIS_S 9
+
+// Field: [8] PEMIS
+//
+// Parity error masked interrupt status:
+// This field returns the masked interrupt state of the parity error interrupt
+// which is the AND product of raw interrupt state RIS.PERIS and the mask
+// setting IMSC.PEIM.
+#define UART_MIS_PEMIS 0x00000100
+#define UART_MIS_PEMIS_BITN 8
+#define UART_MIS_PEMIS_M 0x00000100
+#define UART_MIS_PEMIS_S 8
+
+// Field: [7] FEMIS
+//
+// Framing error masked interrupt status: Returns the masked interrupt state of
+// the framing error interrupt which is the AND product of raw interrupt state
+// RIS.FERIS and the mask setting IMSC.FEIM.
+#define UART_MIS_FEMIS 0x00000080
+#define UART_MIS_FEMIS_BITN 7
+#define UART_MIS_FEMIS_M 0x00000080
+#define UART_MIS_FEMIS_S 7
+
+// Field: [6] RTMIS
+//
+// Receive timeout masked interrupt status:
+// Returns the masked interrupt state of the receive timeout interrupt.
+// The raw interrupt for receive timeout cannot be set unless the mask is set
+// (IMSC.RTIM = 1). This is because the mask acts as an enable for power
+// saving. That is, the same status can be read from RTMIS and RIS.RTRIS.
+#define UART_MIS_RTMIS 0x00000040
+#define UART_MIS_RTMIS_BITN 6
+#define UART_MIS_RTMIS_M 0x00000040
+#define UART_MIS_RTMIS_S 6
+
+// Field: [5] TXMIS
+//
+// Transmit masked interrupt status:
+// This field returns the masked interrupt state of the transmit interrupt
+// which is the AND product of raw interrupt state RIS.TXRIS and the mask
+// setting IMSC.TXIM.
+#define UART_MIS_TXMIS 0x00000020
+#define UART_MIS_TXMIS_BITN 5
+#define UART_MIS_TXMIS_M 0x00000020
+#define UART_MIS_TXMIS_S 5
+
+// Field: [4] RXMIS
+//
+// Receive masked interrupt status:
+// This field returns the masked interrupt state of the receive interrupt
+// which is the AND product of raw interrupt state RIS.RXRIS and the mask
+// setting IMSC.RXIM.
+#define UART_MIS_RXMIS 0x00000010
+#define UART_MIS_RXMIS_BITN 4
+#define UART_MIS_RXMIS_M 0x00000010
+#define UART_MIS_RXMIS_S 4
+
+// Field: [1] CTSMMIS
+//
+// Clear to Send (CTS) modem masked interrupt status:
+// This field returns the masked interrupt state of the clear to send interrupt
+// which is the AND product of raw interrupt state RIS.CTSRMIS and the mask
+// setting IMSC.CTSMIM.
+#define UART_MIS_CTSMMIS 0x00000002
+#define UART_MIS_CTSMMIS_BITN 1
+#define UART_MIS_CTSMMIS_M 0x00000002
+#define UART_MIS_CTSMMIS_S 1
+
+//*****************************************************************************
+//
+// Register: UART_O_ICR
+//
+//*****************************************************************************
+// Field: [11] EOTIC
+//
+// End of Transmission interrupt clear:
+// Writing 1 to this field clears the overrun error interrupt (RIS.EOTRIS).
+// Writing 0 has no effect.
+#define UART_ICR_EOTIC 0x00000800
+#define UART_ICR_EOTIC_BITN 11
+#define UART_ICR_EOTIC_M 0x00000800
+#define UART_ICR_EOTIC_S 11
+
+// Field: [10] OEIC
+//
+// Overrun error interrupt clear:
+// Writing 1 to this field clears the overrun error interrupt (RIS.OERIS).
+// Writing 0 has no effect.
+#define UART_ICR_OEIC 0x00000400
+#define UART_ICR_OEIC_BITN 10
+#define UART_ICR_OEIC_M 0x00000400
+#define UART_ICR_OEIC_S 10
+
+// Field: [9] BEIC
+//
+// Break error interrupt clear:
+// Writing 1 to this field clears the break error interrupt (RIS.BERIS).
+// Writing 0 has no effect.
+#define UART_ICR_BEIC 0x00000200
+#define UART_ICR_BEIC_BITN 9
+#define UART_ICR_BEIC_M 0x00000200
+#define UART_ICR_BEIC_S 9
+
+// Field: [8] PEIC
+//
+// Parity error interrupt clear:
+// Writing 1 to this field clears the parity error interrupt (RIS.PERIS).
+// Writing 0 has no effect.
+#define UART_ICR_PEIC 0x00000100
+#define UART_ICR_PEIC_BITN 8
+#define UART_ICR_PEIC_M 0x00000100
+#define UART_ICR_PEIC_S 8
+
+// Field: [7] FEIC
+//
+// Framing error interrupt clear:
+// Writing 1 to this field clears the framing error interrupt (RIS.FERIS).
+// Writing 0 has no effect.
+#define UART_ICR_FEIC 0x00000080
+#define UART_ICR_FEIC_BITN 7
+#define UART_ICR_FEIC_M 0x00000080
+#define UART_ICR_FEIC_S 7
+
+// Field: [6] RTIC
+//
+// Receive timeout interrupt clear:
+// Writing 1 to this field clears the receive timeout interrupt (RIS.RTRIS).
+// Writing 0 has no effect.
+#define UART_ICR_RTIC 0x00000040
+#define UART_ICR_RTIC_BITN 6
+#define UART_ICR_RTIC_M 0x00000040
+#define UART_ICR_RTIC_S 6
+
+// Field: [5] TXIC
+//
+// Transmit interrupt clear:
+// Writing 1 to this field clears the transmit interrupt (RIS.TXRIS). Writing 0
+// has no effect.
+#define UART_ICR_TXIC 0x00000020
+#define UART_ICR_TXIC_BITN 5
+#define UART_ICR_TXIC_M 0x00000020
+#define UART_ICR_TXIC_S 5
+
+// Field: [4] RXIC
+//
+// Receive interrupt clear:
+// Writing 1 to this field clears the receive interrupt (RIS.RXRIS). Writing 0
+// has no effect.
+#define UART_ICR_RXIC 0x00000010
+#define UART_ICR_RXIC_BITN 4
+#define UART_ICR_RXIC_M 0x00000010
+#define UART_ICR_RXIC_S 4
+
+// Field: [1] CTSMIC
+//
+// Clear to Send (CTS) modem interrupt clear:
+// Writing 1 to this field clears the clear to send interrupt (RIS.CTSRMIS).
+// Writing 0 has no effect.
+#define UART_ICR_CTSMIC 0x00000002
+#define UART_ICR_CTSMIC_BITN 1
+#define UART_ICR_CTSMIC_M 0x00000002
+#define UART_ICR_CTSMIC_S 1
+
+//*****************************************************************************
+//
+// Register: UART_O_DMACTL
+//
+//*****************************************************************************
+// Field: [2] DMAONERR
+//
+// DMA on error. If this bit is set to 1, the DMA receive request outputs (for
+// single and burst requests) are disabled when the UART error interrupt is
+// asserted (more specifically if any of the error interrupts RIS.PERIS,
+// RIS.BERIS, RIS.FERIS or RIS.OERIS are asserted).
+#define UART_DMACTL_DMAONERR 0x00000004
+#define UART_DMACTL_DMAONERR_BITN 2
+#define UART_DMACTL_DMAONERR_M 0x00000004
+#define UART_DMACTL_DMAONERR_S 2
+
+// Field: [1] TXDMAE
+//
+// Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is
+// enabled.
+#define UART_DMACTL_TXDMAE 0x00000002
+#define UART_DMACTL_TXDMAE_BITN 1
+#define UART_DMACTL_TXDMAE_M 0x00000002
+#define UART_DMACTL_TXDMAE_S 1
+
+// Field: [0] RXDMAE
+//
+// Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is
+// enabled.
+#define UART_DMACTL_RXDMAE 0x00000001
+#define UART_DMACTL_RXDMAE_BITN 0
+#define UART_DMACTL_RXDMAE_M 0x00000001
+#define UART_DMACTL_RXDMAE_S 0
+
+
+#endif // __UART__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_udma.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_udma.h
new file mode 100644
index 0000000..2a4b161
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_udma.h
@@ -0,0 +1,575 @@
+/******************************************************************************
+* Filename: hw_udma_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_UDMA_H__
+#define __HW_UDMA_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// UDMA component
+//
+//*****************************************************************************
+// Status
+#define UDMA_O_STATUS 0x00000000
+
+// Configuration
+#define UDMA_O_CFG 0x00000004
+
+// Channel Control Data Base Pointer
+#define UDMA_O_CTRL 0x00000008
+
+// Channel Alternate Control Data Base Pointer
+#define UDMA_O_ALTCTRL 0x0000000C
+
+// Channel Wait On Request Status
+#define UDMA_O_WAITONREQ 0x00000010
+
+// Channel Software Request
+#define UDMA_O_SOFTREQ 0x00000014
+
+// Channel Set UseBurst
+#define UDMA_O_SETBURST 0x00000018
+
+// Channel Clear UseBurst
+#define UDMA_O_CLEARBURST 0x0000001C
+
+// Channel Set Request Mask
+#define UDMA_O_SETREQMASK 0x00000020
+
+// Clear Channel Request Mask
+#define UDMA_O_CLEARREQMASK 0x00000024
+
+// Set Channel Enable
+#define UDMA_O_SETCHANNELEN 0x00000028
+
+// Clear Channel Enable
+#define UDMA_O_CLEARCHANNELEN 0x0000002C
+
+// Channel Set Primary-Alternate
+#define UDMA_O_SETCHNLPRIALT 0x00000030
+
+// Channel Clear Primary-Alternate
+#define UDMA_O_CLEARCHNLPRIALT 0x00000034
+
+// Set Channel Priority
+#define UDMA_O_SETCHNLPRIORITY 0x00000038
+
+// Clear Channel Priority
+#define UDMA_O_CLEARCHNLPRIORITY 0x0000003C
+
+// Error Status and Clear
+#define UDMA_O_ERROR 0x0000004C
+
+// Channel Request Done
+#define UDMA_O_REQDONE 0x00000504
+
+// Channel Request Done Mask
+#define UDMA_O_DONEMASK 0x00000520
+
+//*****************************************************************************
+//
+// Register: UDMA_O_STATUS
+//
+//*****************************************************************************
+// Field: [31:28] TEST
+//
+//
+// 0x0: Controller does not include the integration test logic
+// 0x1: Controller includes the integration test logic
+// 0x2: Undefined
+// ...
+// 0xF: Undefined
+#define UDMA_STATUS_TEST_W 4
+#define UDMA_STATUS_TEST_M 0xF0000000
+#define UDMA_STATUS_TEST_S 28
+
+// Field: [20:16] TOTALCHANNELS
+//
+// Register value returns number of available uDMA channels minus one. For
+// example a read out value of:
+//
+// 0x00: Show that the controller is configured to use 1 uDMA channel
+// 0x01: Shows that the controller is configured to use 2 uDMA channels
+// ...
+// 0x1F: Shows that the controller is configured to use 32 uDMA channels
+// (32-1=31=0x1F)
+#define UDMA_STATUS_TOTALCHANNELS_W 5
+#define UDMA_STATUS_TOTALCHANNELS_M 0x001F0000
+#define UDMA_STATUS_TOTALCHANNELS_S 16
+
+// Field: [7:4] STATE
+//
+// Current state of the control state machine. State can be one of the
+// following:
+//
+// 0x0: Idle
+// 0x1: Reading channel controller data
+// 0x2: Reading source data end pointer
+// 0x3: Reading destination data end pointer
+// 0x4: Reading source data
+// 0x5: Writing destination data
+// 0x6: Waiting for uDMA request to clear
+// 0x7: Writing channel controller data
+// 0x8: Stalled
+// 0x9: Done
+// 0xA: Peripheral scatter-gather transition
+// 0xB: Undefined
+// ...
+// 0xF: Undefined.
+#define UDMA_STATUS_STATE_W 4
+#define UDMA_STATUS_STATE_M 0x000000F0
+#define UDMA_STATUS_STATE_S 4
+
+// Field: [0] MASTERENABLE
+//
+// Shows the enable status of the controller as configured by CFG.MASTERENABLE:
+//
+// 0: Controller is disabled
+// 1: Controller is enabled
+#define UDMA_STATUS_MASTERENABLE 0x00000001
+#define UDMA_STATUS_MASTERENABLE_BITN 0
+#define UDMA_STATUS_MASTERENABLE_M 0x00000001
+#define UDMA_STATUS_MASTERENABLE_S 0
+
+//*****************************************************************************
+//
+// Register: UDMA_O_CFG
+//
+//*****************************************************************************
+// Field: [7:5] PRTOCTRL
+//
+// Sets the AHB-Lite bus protocol protection state by controlling the AHB
+// signal HProt[3:1] as follows:
+//
+// Bit [7] Controls HProt[3] to indicate if a cacheable access is occurring.
+// Bit [6] Controls HProt[2] to indicate if a bufferable access is occurring.
+// Bit [5] Controls HProt[1] to indicate if a privileged access is occurring.
+//
+// When bit [n] = 1 then the corresponding HProt bit is high.
+// When bit [n] = 0 then the corresponding HProt bit is low.
+//
+// This field controls HProt[3:1] signal for all transactions initiated by uDMA
+// except two transactions below:
+// - the read from the address indicated by source address pointer
+// - the write to the address indicated by destination address pointer
+// HProt[3:1] for these two exceptions can be controlled by dedicated fields in
+// the channel configutation descriptor.
+#define UDMA_CFG_PRTOCTRL_W 3
+#define UDMA_CFG_PRTOCTRL_M 0x000000E0
+#define UDMA_CFG_PRTOCTRL_S 5
+
+// Field: [0] MASTERENABLE
+//
+// Enables the controller:
+//
+// 0: Disables the controller
+// 1: Enables the controller
+#define UDMA_CFG_MASTERENABLE 0x00000001
+#define UDMA_CFG_MASTERENABLE_BITN 0
+#define UDMA_CFG_MASTERENABLE_M 0x00000001
+#define UDMA_CFG_MASTERENABLE_S 0
+
+//*****************************************************************************
+//
+// Register: UDMA_O_CTRL
+//
+//*****************************************************************************
+// Field: [31:10] BASEPTR
+//
+// This register point to the base address for the primary data structures of
+// each DMA channel. This is not stored in module, but in system memory, thus
+// space must be allocated for this usage when DMA is in usage
+#define UDMA_CTRL_BASEPTR_W 22
+#define UDMA_CTRL_BASEPTR_M 0xFFFFFC00
+#define UDMA_CTRL_BASEPTR_S 10
+
+//*****************************************************************************
+//
+// Register: UDMA_O_ALTCTRL
+//
+//*****************************************************************************
+// Field: [31:0] BASEPTR
+//
+// This register shows the base address for the alternate data structures and
+// is calculated by module, thus read only
+#define UDMA_ALTCTRL_BASEPTR_W 32
+#define UDMA_ALTCTRL_BASEPTR_M 0xFFFFFFFF
+#define UDMA_ALTCTRL_BASEPTR_S 0
+
+//*****************************************************************************
+//
+// Register: UDMA_O_WAITONREQ
+//
+//*****************************************************************************
+// Field: [31:0] CHNLSTATUS
+//
+// Channel wait on request status:
+//
+// Bit [Ch] = 0: Once uDMA receives a single or burst request on channel Ch,
+// this channel may come out of active state even if request is still present.
+// Bit [Ch] = 1: Once uDMA receives a single or burst request on channel Ch, it
+// keeps channel Ch in active state until the requests are deasserted. This
+// handshake is necessary for channels where the requester is in an
+// asynchronous domain or can run at slower clock speed than uDMA
+#define UDMA_WAITONREQ_CHNLSTATUS_W 32
+#define UDMA_WAITONREQ_CHNLSTATUS_M 0xFFFFFFFF
+#define UDMA_WAITONREQ_CHNLSTATUS_S 0
+
+//*****************************************************************************
+//
+// Register: UDMA_O_SOFTREQ
+//
+//*****************************************************************************
+// Field: [31:0] CHNLS
+//
+// Set the appropriate bit to generate a software uDMA request on the
+// corresponding uDMA channel
+//
+// Bit [Ch] = 0: Does not create a uDMA request for channel Ch
+// Bit [Ch] = 1: Creates a uDMA request for channel Ch
+//
+// Writing to a bit where a uDMA channel is not implemented does not create a
+// uDMA request for that channel
+#define UDMA_SOFTREQ_CHNLS_W 32
+#define UDMA_SOFTREQ_CHNLS_M 0xFFFFFFFF
+#define UDMA_SOFTREQ_CHNLS_S 0
+
+//*****************************************************************************
+//
+// Register: UDMA_O_SETBURST
+//
+//*****************************************************************************
+// Field: [31:0] CHNLS
+//
+// Returns the useburst status, or disables individual channels from generating
+// single uDMA requests. The value R is the arbitration rate and stored in the
+// controller data structure.
+//
+// Read as:
+//
+// Bit [Ch] = 0: uDMA channel Ch responds to both burst and single requests on
+// channel C. The controller performs 2^R, or single, bus transfers.
+//
+// Bit [Ch] = 1: uDMA channel Ch does not respond to single transfer requests.
+// The controller only responds to burst transfer requests and performs 2^R
+// transfers.
+//
+// Write as:
+// Bit [Ch] = 0: No effect. Use the CLEARBURST.CHNLS to set bit [Ch] to 0.
+// Bit [Ch] = 1: Disables single transfer requests on channel Ch. The
+// controller performs 2^R transfers for burst requests.
+//
+// Writing to a bit where a uDMA channel is not implemented has no effect
+#define UDMA_SETBURST_CHNLS_W 32
+#define UDMA_SETBURST_CHNLS_M 0xFFFFFFFF
+#define UDMA_SETBURST_CHNLS_S 0
+
+//*****************************************************************************
+//
+// Register: UDMA_O_CLEARBURST
+//
+//*****************************************************************************
+// Field: [31:0] CHNLS
+//
+// Set the appropriate bit to enable single transfer requests.
+//
+// Write as:
+//
+// Bit [Ch] = 0: No effect. Use the SETBURST.CHNLS to disable single transfer
+// requests.
+//
+// Bit [Ch] = 1: Enables single transfer requests on channel Ch.
+//
+// Writing to a bit where a DMA channel is not implemented has no effect.
+#define UDMA_CLEARBURST_CHNLS_W 32
+#define UDMA_CLEARBURST_CHNLS_M 0xFFFFFFFF
+#define UDMA_CLEARBURST_CHNLS_S 0
+
+//*****************************************************************************
+//
+// Register: UDMA_O_SETREQMASK
+//
+//*****************************************************************************
+// Field: [31:0] CHNLS
+//
+// Returns the burst and single request mask status, or disables the
+// corresponding channel from generating uDMA requests.
+//
+// Read as:
+// Bit [Ch] = 0: External requests are enabled for channel Ch.
+// Bit [Ch] = 1: External requests are disabled for channel Ch.
+//
+// Write as:
+// Bit [Ch] = 0: No effect. Use the CLEARREQMASK.CHNLS to enable uDMA requests.
+// Bit [Ch] = 1: Disables uDMA burst request channel [C] and uDMA single
+// request channel [C] input from generating uDMA requests.
+//
+// Writing to a bit where a uDMA channel is not implemented has no effect
+#define UDMA_SETREQMASK_CHNLS_W 32
+#define UDMA_SETREQMASK_CHNLS_M 0xFFFFFFFF
+#define UDMA_SETREQMASK_CHNLS_S 0
+
+//*****************************************************************************
+//
+// Register: UDMA_O_CLEARREQMASK
+//
+//*****************************************************************************
+// Field: [31:0] CHNLS
+//
+// Set the appropriate bit to enable DMA request for the channel.
+//
+// Write as:
+// Bit [Ch] = 0: No effect. Use the SETREQMASK.CHNLS to disable channel C from
+// generating requests.
+// Bit [Ch] = 1: Enables channel [C] to generate DMA requests.
+//
+// Writing to a bit where a DMA channel is not implemented has no effect.
+#define UDMA_CLEARREQMASK_CHNLS_W 32
+#define UDMA_CLEARREQMASK_CHNLS_M 0xFFFFFFFF
+#define UDMA_CLEARREQMASK_CHNLS_S 0
+
+//*****************************************************************************
+//
+// Register: UDMA_O_SETCHANNELEN
+//
+//*****************************************************************************
+// Field: [31:0] CHNLS
+//
+// Returns the enable status of the channels, or enables the corresponding
+// channels.
+//
+// Read as:
+// Bit [Ch] = 0: Channel Ch is disabled.
+// Bit [Ch] = 1: Channel Ch is enabled.
+//
+// Write as:
+// Bit [Ch] = 0: No effect. Use the CLEARCHANNELEN.CHNLS to disable a channel
+// Bit [Ch] = 1: Enables channel Ch
+//
+// Writing to a bit where a DMA channel is not implemented has no effect
+#define UDMA_SETCHANNELEN_CHNLS_W 32
+#define UDMA_SETCHANNELEN_CHNLS_M 0xFFFFFFFF
+#define UDMA_SETCHANNELEN_CHNLS_S 0
+
+//*****************************************************************************
+//
+// Register: UDMA_O_CLEARCHANNELEN
+//
+//*****************************************************************************
+// Field: [31:0] CHNLS
+//
+// Set the appropriate bit to disable the corresponding uDMA channel.
+//
+// Write as:
+// Bit [Ch] = 0: No effect. Use the SETCHANNELEN.CHNLS to enable uDMA channels.
+// Bit [Ch] = 1: Disables channel Ch
+//
+// Writing to a bit where a uDMA channel is not implemented has no effect
+#define UDMA_CLEARCHANNELEN_CHNLS_W 32
+#define UDMA_CLEARCHANNELEN_CHNLS_M 0xFFFFFFFF
+#define UDMA_CLEARCHANNELEN_CHNLS_S 0
+
+//*****************************************************************************
+//
+// Register: UDMA_O_SETCHNLPRIALT
+//
+//*****************************************************************************
+// Field: [31:0] CHNLS
+//
+// Returns the channel control data structure status, or selects the alternate
+// data structure for the corresponding uDMA channel.
+//
+// Read as:
+// Bit [Ch] = 0: uDMA channel Ch is using the primary data structure.
+// Bit [Ch] = 1: uDMA channel Ch is using the alternate data structure.
+//
+// Write as:
+// Bit [Ch] = 0: No effect. Use the CLEARCHNLPRIALT.CHNLS to disable a channel
+// Bit [Ch] = 1: Selects the alternate data structure for channel Ch
+//
+// Writing to a bit where a uDMA channel is not implemented has no effect
+#define UDMA_SETCHNLPRIALT_CHNLS_W 32
+#define UDMA_SETCHNLPRIALT_CHNLS_M 0xFFFFFFFF
+#define UDMA_SETCHNLPRIALT_CHNLS_S 0
+
+//*****************************************************************************
+//
+// Register: UDMA_O_CLEARCHNLPRIALT
+//
+//*****************************************************************************
+// Field: [31:0] CHNLS
+//
+// Clears the appropriate bit to select the primary data structure for the
+// corresponding uDMA channel.
+//
+// Write as:
+// Bit [Ch] = 0: No effect. Use the SETCHNLPRIALT.CHNLS to select the alternate
+// data structure.
+// Bit [Ch] = 1: Selects the primary data structure for channel Ch.
+//
+// Writing to a bit where a uDMA channel is not implemented has no effect
+#define UDMA_CLEARCHNLPRIALT_CHNLS_W 32
+#define UDMA_CLEARCHNLPRIALT_CHNLS_M 0xFFFFFFFF
+#define UDMA_CLEARCHNLPRIALT_CHNLS_S 0
+
+//*****************************************************************************
+//
+// Register: UDMA_O_SETCHNLPRIORITY
+//
+//*****************************************************************************
+// Field: [31:0] CHNLS
+//
+// Returns the channel priority mask status, or sets the channel priority to
+// high.
+//
+// Read as:
+// Bit [Ch] = 0: uDMA channel Ch is using the default priority level.
+// Bit [Ch] = 1: uDMA channel Ch is using a high priority level.
+//
+// Write as:
+// Bit [Ch] = 0: No effect. Use the CLEARCHNLPRIORITY.CHNLS to set channel Ch
+// to the default priority level.
+// Bit [Ch] = 1: Channel Ch uses the high priority level.
+//
+// Writing to a bit where a uDMA channel is not implemented has no effect
+#define UDMA_SETCHNLPRIORITY_CHNLS_W 32
+#define UDMA_SETCHNLPRIORITY_CHNLS_M 0xFFFFFFFF
+#define UDMA_SETCHNLPRIORITY_CHNLS_S 0
+
+//*****************************************************************************
+//
+// Register: UDMA_O_CLEARCHNLPRIORITY
+//
+//*****************************************************************************
+// Field: [31:0] CHNLS
+//
+// Clear the appropriate bit to select the default priority level for the
+// specified uDMA channel.
+//
+// Write as:
+// Bit [Ch] = 0: No effect. Use the SETCHNLPRIORITY.CHNLS to set channel Ch to
+// the high priority level.
+// Bit [Ch] = 1: Channel Ch uses the default priority level.
+//
+// Writing to a bit where a uDMA channel is not implemented has no effect
+#define UDMA_CLEARCHNLPRIORITY_CHNLS_W 32
+#define UDMA_CLEARCHNLPRIORITY_CHNLS_M 0xFFFFFFFF
+#define UDMA_CLEARCHNLPRIORITY_CHNLS_S 0
+
+//*****************************************************************************
+//
+// Register: UDMA_O_ERROR
+//
+//*****************************************************************************
+// Field: [0] STATUS
+//
+// Returns the status of bus error flag in uDMA, or clears this bit
+//
+// Read as:
+//
+// 0: No bus error detected
+// 1: Bus error detected
+//
+// Write as:
+//
+// 0: No effect, status of bus error flag is unchanged.
+// 1: Clears the bus error flag.
+#define UDMA_ERROR_STATUS 0x00000001
+#define UDMA_ERROR_STATUS_BITN 0
+#define UDMA_ERROR_STATUS_M 0x00000001
+#define UDMA_ERROR_STATUS_S 0
+
+//*****************************************************************************
+//
+// Register: UDMA_O_REQDONE
+//
+//*****************************************************************************
+// Field: [31:0] CHNLS
+//
+// Reflects the uDMA done status for the given channel, channel [Ch]. It's a
+// sticky done bit. Unless cleared by writing a 1, it holds the value of 1.
+//
+// Read as:
+// Bit [Ch] = 0: Request has not completed for channel Ch
+// Bit [Ch] = 1: Request has completed for the channel Ch
+//
+// Writing a 1 to individual bits would clear the corresponding bit.
+//
+// Write as:
+// Bit [Ch] = 0: No effect.
+// Bit [Ch] = 1: The corresponding [Ch] bit is cleared and is set to 0
+#define UDMA_REQDONE_CHNLS_W 32
+#define UDMA_REQDONE_CHNLS_M 0xFFFFFFFF
+#define UDMA_REQDONE_CHNLS_S 0
+
+//*****************************************************************************
+//
+// Register: UDMA_O_DONEMASK
+//
+//*****************************************************************************
+// Field: [31:0] CHNLS
+//
+// Controls the propagation of the uDMA done and active state to the assigned
+// peripheral. Specifically used for software channels.
+//
+// Read as:
+// Bit [Ch] = 0: uDMA done and active state for channel Ch is not blocked from
+// reaching to the peripherals.
+// Note that the uDMA done state for channel [Ch] is blocked from contributing
+// to generation of combined uDMA done signal
+//
+// Bit [Ch] = 1: uDMA done and active state for channel Ch is blocked from
+// reaching to the peripherals.
+// Note that the uDMA done state for channel [Ch] is not blocked from
+// contributing to generation of combined uDMA done signal
+//
+// Write as:
+// Bit [Ch] = 0: Allows uDMA done and active stat to propagate to the
+// peripherals.
+// Note that this disables uDMA done state for channel [Ch] from contributing
+// to generation of combined uDMA done signal
+//
+// Bit [Ch] = 1: Blocks uDMA done and active state to propagate to the
+// peripherals.
+// Note that this enables uDMA done for channel [Ch] to contribute to
+// generation of combined uDMA done signal.
+#define UDMA_DONEMASK_CHNLS_W 32
+#define UDMA_DONEMASK_CHNLS_M 0xFFFFFFFF
+#define UDMA_DONEMASK_CHNLS_S 0
+
+
+#endif // __UDMA__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_vims.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_vims.h
new file mode 100644
index 0000000..e3de5ea
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_vims.h
@@ -0,0 +1,204 @@
+/******************************************************************************
+* Filename: hw_vims_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_VIMS_H__
+#define __HW_VIMS_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// VIMS component
+//
+//*****************************************************************************
+// Status
+#define VIMS_O_STAT 0x00000000
+
+// Control
+#define VIMS_O_CTL 0x00000004
+
+//*****************************************************************************
+//
+// Register: VIMS_O_STAT
+//
+//*****************************************************************************
+// Field: [5] IDCODE_LB_DIS
+//
+// Icode/Dcode flash line buffer status
+//
+// 0: Enabled or in transition to disabled
+// 1: Disabled and flushed
+#define VIMS_STAT_IDCODE_LB_DIS 0x00000020
+#define VIMS_STAT_IDCODE_LB_DIS_BITN 5
+#define VIMS_STAT_IDCODE_LB_DIS_M 0x00000020
+#define VIMS_STAT_IDCODE_LB_DIS_S 5
+
+// Field: [4] SYSBUS_LB_DIS
+//
+// Sysbus flash line buffer control
+//
+// 0: Enabled or in transition to disabled
+// 1: Disabled and flushed
+#define VIMS_STAT_SYSBUS_LB_DIS 0x00000010
+#define VIMS_STAT_SYSBUS_LB_DIS_BITN 4
+#define VIMS_STAT_SYSBUS_LB_DIS_M 0x00000010
+#define VIMS_STAT_SYSBUS_LB_DIS_S 4
+
+// Field: [3] MODE_CHANGING
+//
+// VIMS mode change status
+//
+// 0: VIMS is in the mode defined by MODE
+// 1: VIMS is in the process of changing to the mode given in CTL.MODE
+#define VIMS_STAT_MODE_CHANGING 0x00000008
+#define VIMS_STAT_MODE_CHANGING_BITN 3
+#define VIMS_STAT_MODE_CHANGING_M 0x00000008
+#define VIMS_STAT_MODE_CHANGING_S 3
+
+// Field: [2] INV
+//
+// This bit is set when invalidation of the cache memory is active / ongoing
+#define VIMS_STAT_INV 0x00000004
+#define VIMS_STAT_INV_BITN 2
+#define VIMS_STAT_INV_M 0x00000004
+#define VIMS_STAT_INV_S 2
+
+// Field: [1:0] MODE
+//
+// Current VIMS mode
+// ENUMs:
+// OFF VIMS Off mode
+// CACHE VIMS Cache mode
+// GPRAM VIMS GPRAM mode
+#define VIMS_STAT_MODE_W 2
+#define VIMS_STAT_MODE_M 0x00000003
+#define VIMS_STAT_MODE_S 0
+#define VIMS_STAT_MODE_OFF 0x00000003
+#define VIMS_STAT_MODE_CACHE 0x00000001
+#define VIMS_STAT_MODE_GPRAM 0x00000000
+
+//*****************************************************************************
+//
+// Register: VIMS_O_CTL
+//
+//*****************************************************************************
+// Field: [31] STATS_CLR
+//
+// Set this bit to clear statistic counters.
+#define VIMS_CTL_STATS_CLR 0x80000000
+#define VIMS_CTL_STATS_CLR_BITN 31
+#define VIMS_CTL_STATS_CLR_M 0x80000000
+#define VIMS_CTL_STATS_CLR_S 31
+
+// Field: [30] STATS_EN
+//
+// Set this bit to enable statistic counters.
+#define VIMS_CTL_STATS_EN 0x40000000
+#define VIMS_CTL_STATS_EN_BITN 30
+#define VIMS_CTL_STATS_EN_M 0x40000000
+#define VIMS_CTL_STATS_EN_S 30
+
+// Field: [29] DYN_CG_EN
+//
+// 0: The in-built clock gate functionality is bypassed.
+// 1: The in-built clock gate functionality is enabled, automatically gating
+// the clock when not needed.
+#define VIMS_CTL_DYN_CG_EN 0x20000000
+#define VIMS_CTL_DYN_CG_EN_BITN 29
+#define VIMS_CTL_DYN_CG_EN_M 0x20000000
+#define VIMS_CTL_DYN_CG_EN_S 29
+
+// Field: [5] IDCODE_LB_DIS
+//
+// Icode/Dcode flash line buffer control
+//
+// 0: Enable
+// 1: Disable
+#define VIMS_CTL_IDCODE_LB_DIS 0x00000020
+#define VIMS_CTL_IDCODE_LB_DIS_BITN 5
+#define VIMS_CTL_IDCODE_LB_DIS_M 0x00000020
+#define VIMS_CTL_IDCODE_LB_DIS_S 5
+
+// Field: [4] SYSBUS_LB_DIS
+//
+// Sysbus flash line buffer control
+//
+// 0: Enable
+// 1: Disable
+#define VIMS_CTL_SYSBUS_LB_DIS 0x00000010
+#define VIMS_CTL_SYSBUS_LB_DIS_BITN 4
+#define VIMS_CTL_SYSBUS_LB_DIS_M 0x00000010
+#define VIMS_CTL_SYSBUS_LB_DIS_S 4
+
+// Field: [3] ARB_CFG
+//
+// Icode/Dcode and sysbus arbitation scheme
+//
+// 0: Static arbitration (icode/docde > sysbus)
+// 1: Round-robin arbitration
+#define VIMS_CTL_ARB_CFG 0x00000008
+#define VIMS_CTL_ARB_CFG_BITN 3
+#define VIMS_CTL_ARB_CFG_M 0x00000008
+#define VIMS_CTL_ARB_CFG_S 3
+
+// Field: [2] PREF_EN
+//
+// Tag prefetch control
+//
+// 0: Disabled
+// 1: Enabled
+#define VIMS_CTL_PREF_EN 0x00000004
+#define VIMS_CTL_PREF_EN_BITN 2
+#define VIMS_CTL_PREF_EN_M 0x00000004
+#define VIMS_CTL_PREF_EN_S 2
+
+// Field: [1:0] MODE
+//
+// VIMS mode request.
+// Write accesses to this field will be blocked while STAT.MODE_CHANGING is set
+// to 1.
+// ENUMs:
+// OFF VIMS Off mode
+// CACHE VIMS Cache mode
+// GPRAM VIMS GPRAM mode
+#define VIMS_CTL_MODE_W 2
+#define VIMS_CTL_MODE_M 0x00000003
+#define VIMS_CTL_MODE_S 0
+#define VIMS_CTL_MODE_OFF 0x00000003
+#define VIMS_CTL_MODE_CACHE 0x00000001
+#define VIMS_CTL_MODE_GPRAM 0x00000000
+
+
+#endif // __VIMS__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_wdt.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_wdt.h
new file mode 100644
index 0000000..2c826ea
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_wdt.h
@@ -0,0 +1,290 @@
+/******************************************************************************
+* Filename: hw_wdt_h
+* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018)
+* Revision: 51990
+*
+* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HW_WDT_H__
+#define __HW_WDT_H__
+
+//*****************************************************************************
+//
+// This section defines the register offsets of
+// WDT component
+//
+//*****************************************************************************
+// Configuration
+#define WDT_O_LOAD 0x00000000
+
+// Current Count Value
+#define WDT_O_VALUE 0x00000004
+
+// Control
+#define WDT_O_CTL 0x00000008
+
+// Interrupt Clear
+#define WDT_O_ICR 0x0000000C
+
+// Raw Interrupt Status
+#define WDT_O_RIS 0x00000010
+
+// Masked Interrupt Status
+#define WDT_O_MIS 0x00000014
+
+// Test Mode
+#define WDT_O_TEST 0x00000418
+
+// Interrupt Cause Test Mode
+#define WDT_O_INT_CAUS 0x0000041C
+
+// Lock
+#define WDT_O_LOCK 0x00000C00
+
+//*****************************************************************************
+//
+// Register: WDT_O_LOAD
+//
+//*****************************************************************************
+// Field: [31:0] WDTLOAD
+//
+// This register is the 32-bit interval value used by the 32-bit counter. When
+// this register is written, the value is immediately loaded and the counter is
+// restarted to count down from the new value. If this register is loaded with
+// 0x0000.0000, an interrupt is immediately generated.
+#define WDT_LOAD_WDTLOAD_W 32
+#define WDT_LOAD_WDTLOAD_M 0xFFFFFFFF
+#define WDT_LOAD_WDTLOAD_S 0
+
+//*****************************************************************************
+//
+// Register: WDT_O_VALUE
+//
+//*****************************************************************************
+// Field: [31:0] WDTVALUE
+//
+// This register contains the current count value of the timer.
+#define WDT_VALUE_WDTVALUE_W 32
+#define WDT_VALUE_WDTVALUE_M 0xFFFFFFFF
+#define WDT_VALUE_WDTVALUE_S 0
+
+//*****************************************************************************
+//
+// Register: WDT_O_CTL
+//
+//*****************************************************************************
+// Field: [2] INTTYPE
+//
+// WDT Interrupt Type
+//
+// 0: WDT interrupt is a standard interrupt.
+// 1: WDT interrupt is a non-maskable interrupt.
+// ENUMs:
+// NONMASKABLE Non-maskable interrupt
+// MASKABLE Maskable interrupt
+#define WDT_CTL_INTTYPE 0x00000004
+#define WDT_CTL_INTTYPE_BITN 2
+#define WDT_CTL_INTTYPE_M 0x00000004
+#define WDT_CTL_INTTYPE_S 2
+#define WDT_CTL_INTTYPE_NONMASKABLE 0x00000004
+#define WDT_CTL_INTTYPE_MASKABLE 0x00000000
+
+// Field: [1] RESEN
+//
+// WDT Reset Enable. Defines the function of the WDT reset source (see
+// PRCM:WARMRESET.WDT_STAT if enabled)
+//
+// 0: Disabled.
+// 1: Enable the Watchdog reset output.
+// ENUMs:
+// EN Reset output Enabled
+// DIS Reset output Disabled
+#define WDT_CTL_RESEN 0x00000002
+#define WDT_CTL_RESEN_BITN 1
+#define WDT_CTL_RESEN_M 0x00000002
+#define WDT_CTL_RESEN_S 1
+#define WDT_CTL_RESEN_EN 0x00000002
+#define WDT_CTL_RESEN_DIS 0x00000000
+
+// Field: [0] INTEN
+//
+// WDT Interrupt Enable
+//
+// 0: Interrupt event disabled.
+// 1: Interrupt event enabled. Once set, this bit can only be cleared by a
+// hardware reset.
+// ENUMs:
+// EN Interrupt Enabled
+// DIS Interrupt Disabled
+#define WDT_CTL_INTEN 0x00000001
+#define WDT_CTL_INTEN_BITN 0
+#define WDT_CTL_INTEN_M 0x00000001
+#define WDT_CTL_INTEN_S 0
+#define WDT_CTL_INTEN_EN 0x00000001
+#define WDT_CTL_INTEN_DIS 0x00000000
+
+//*****************************************************************************
+//
+// Register: WDT_O_ICR
+//
+//*****************************************************************************
+// Field: [31:0] WDTICR
+//
+// This register is the interrupt clear register. A write of any value to this
+// register clears the WDT interrupt and reloads the 32-bit counter from the
+// LOAD register.
+#define WDT_ICR_WDTICR_W 32
+#define WDT_ICR_WDTICR_M 0xFFFFFFFF
+#define WDT_ICR_WDTICR_S 0
+
+//*****************************************************************************
+//
+// Register: WDT_O_RIS
+//
+//*****************************************************************************
+// Field: [0] WDTRIS
+//
+// This register is the raw interrupt status register. WDT interrupt events can
+// be monitored via this register if the controller interrupt is masked.
+//
+// Value Description
+//
+// 0: The WDT has not timed out
+// 1: A WDT time-out event has occurred
+//
+#define WDT_RIS_WDTRIS 0x00000001
+#define WDT_RIS_WDTRIS_BITN 0
+#define WDT_RIS_WDTRIS_M 0x00000001
+#define WDT_RIS_WDTRIS_S 0
+
+//*****************************************************************************
+//
+// Register: WDT_O_MIS
+//
+//*****************************************************************************
+// Field: [0] WDTMIS
+//
+// This register is the masked interrupt status register. The value of this
+// register is the logical AND of the raw interrupt bit and the WDT interrupt
+// enable bit CTL.INTEN.
+//
+// Value Description
+//
+// 0: The WDT has not timed out or is masked.
+// 1: An unmasked WDT time-out event has occurred.
+#define WDT_MIS_WDTMIS 0x00000001
+#define WDT_MIS_WDTMIS_BITN 0
+#define WDT_MIS_WDTMIS_M 0x00000001
+#define WDT_MIS_WDTMIS_S 0
+
+//*****************************************************************************
+//
+// Register: WDT_O_TEST
+//
+//*****************************************************************************
+// Field: [8] STALL
+//
+// WDT Stall Enable
+//
+// 0: The WDT timer continues counting if the CPU is stopped with a debugger.
+// 1: If the CPU is stopped with a debugger, the WDT stops counting. Once the
+// CPU is restarted, the WDT resumes counting.
+// ENUMs:
+// EN Enable STALL
+// DIS Disable STALL
+#define WDT_TEST_STALL 0x00000100
+#define WDT_TEST_STALL_BITN 8
+#define WDT_TEST_STALL_M 0x00000100
+#define WDT_TEST_STALL_S 8
+#define WDT_TEST_STALL_EN 0x00000100
+#define WDT_TEST_STALL_DIS 0x00000000
+
+// Field: [0] TEST_EN
+//
+// The test enable bit
+//
+// 0: Enable external reset
+// 1: Disables the generation of an external reset. Instead bit 1 of the
+// INT_CAUS register is set and an interrupt is generated
+// ENUMs:
+// EN Test mode Enabled
+// DIS Test mode Disabled
+#define WDT_TEST_TEST_EN 0x00000001
+#define WDT_TEST_TEST_EN_BITN 0
+#define WDT_TEST_TEST_EN_M 0x00000001
+#define WDT_TEST_TEST_EN_S 0
+#define WDT_TEST_TEST_EN_EN 0x00000001
+#define WDT_TEST_TEST_EN_DIS 0x00000000
+
+//*****************************************************************************
+//
+// Register: WDT_O_INT_CAUS
+//
+//*****************************************************************************
+// Field: [1] CAUSE_RESET
+//
+// Indicates that the cause of an interrupt was a reset generated but blocked
+// due to TEST.TEST_EN (only possible when TEST.TEST_EN is set).
+#define WDT_INT_CAUS_CAUSE_RESET 0x00000002
+#define WDT_INT_CAUS_CAUSE_RESET_BITN 1
+#define WDT_INT_CAUS_CAUSE_RESET_M 0x00000002
+#define WDT_INT_CAUS_CAUSE_RESET_S 1
+
+// Field: [0] CAUSE_INTR
+//
+// Replica of RIS.WDTRIS
+#define WDT_INT_CAUS_CAUSE_INTR 0x00000001
+#define WDT_INT_CAUS_CAUSE_INTR_BITN 0
+#define WDT_INT_CAUS_CAUSE_INTR_M 0x00000001
+#define WDT_INT_CAUS_CAUSE_INTR_S 0
+
+//*****************************************************************************
+//
+// Register: WDT_O_LOCK
+//
+//*****************************************************************************
+// Field: [31:0] WDTLOCK
+//
+// WDT Lock: A write of the value 0x1ACC.E551 unlocks the watchdog registers
+// for write access. A write of any other value reapplies the lock, preventing
+// any register updates (NOTE: TEST.TEST_EN bit is not lockable).
+//
+// A read of this register returns the following values:
+//
+// 0x0000.0000: Unlocked
+// 0x0000.0001: Locked
+#define WDT_LOCK_WDTLOCK_W 32
+#define WDT_LOCK_WDTLOCK_M 0xFFFFFFFF
+#define WDT_LOCK_WDTLOCK_S 0
+
+
+#endif // __WDT__
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_bt5.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_bt5.h
new file mode 100644
index 0000000..b293749
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_bt5.h
@@ -0,0 +1,218 @@
+/******************************************************************************
+* Filename: rf_patch_cpe_bt5.h
+* Revised: $Date: 2019-02-27 16:13:01 +0100 (on, 27 feb 2019) $
+* Revision: $Revision: 18889 $
+*
+* Description: RF core patch for Bluetooth 5 support ("BLE" and "BLE5" API command sets) in CC13x2 and CC26x2
+*
+* Copyright (c) 2015-2019, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+#ifndef _RF_PATCH_CPE_BT5_H
+#define _RF_PATCH_CPE_BT5_H
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include <string.h>
+
+#ifndef CPE_PATCH_TYPE
+#define CPE_PATCH_TYPE static const uint32_t
+#endif
+
+#ifndef SYS_PATCH_TYPE
+#define SYS_PATCH_TYPE static const uint32_t
+#endif
+
+#ifndef PATCH_FUN_SPEC
+#define PATCH_FUN_SPEC static inline
+#endif
+
+#ifndef _APPLY_PATCH_TAB
+#define _APPLY_PATCH_TAB
+#endif
+
+
+CPE_PATCH_TYPE patchImageBt5[] = {
+ 0x21004059,
+ 0x210040a5,
+ 0x21004085,
+ 0x79654c07,
+ 0xf809f000,
+ 0x40697961,
+ 0xd5030749,
+ 0x4a042101,
+ 0x60110389,
+ 0xb570bd70,
+ 0x47084902,
+ 0x21000380,
+ 0x40041108,
+ 0x0000592d,
+ 0x21014805,
+ 0x438a6802,
+ 0x6b836002,
+ 0x6383438b,
+ 0x6002430a,
+ 0x47004801,
+ 0x40046000,
+ 0x00005b3f,
+ 0x490cb510,
+ 0x4a0c4788,
+ 0x5e512106,
+ 0xd0072900,
+ 0xd0052902,
+ 0xd0032909,
+ 0xd0012910,
+ 0xd1072911,
+ 0x43c92177,
+ 0xdd014288,
+ 0xdd012800,
+ 0x43c0207f,
+ 0x0000bd10,
+ 0x000065a9,
+ 0x21000380,
+};
+#define _NWORD_PATCHIMAGE_BT5 37
+
+#define _NWORD_PATCHCPEHD_BT5 0
+
+#define _NWORD_PATCHSYS_BT5 0
+
+
+
+#ifndef _BT5_SYSRAM_START
+#define _BT5_SYSRAM_START 0x20000000
+#endif
+
+#ifndef _BT5_CPERAM_START
+#define _BT5_CPERAM_START 0x21000000
+#endif
+
+#define _BT5_SYS_PATCH_FIXED_ADDR 0x20000000
+
+#define _BT5_PATCH_VEC_ADDR_OFFSET 0x03D0
+#define _BT5_PATCH_TAB_OFFSET 0x03D4
+#define _BT5_IRQPATCH_OFFSET 0x0480
+#define _BT5_PATCH_VEC_OFFSET 0x404C
+
+#define _BT5_PATCH_CPEHD_OFFSET 0x04E0
+
+#ifndef _BT5_NO_PROG_STATE_VAR
+static uint8_t bBt5PatchEntered = 0;
+#endif
+
+PATCH_FUN_SPEC void enterBt5CpePatch(void)
+{
+#if (_NWORD_PATCHIMAGE_BT5 > 0)
+ uint32_t *pPatchVec = (uint32_t *) (_BT5_CPERAM_START + _BT5_PATCH_VEC_OFFSET);
+
+ memcpy(pPatchVec, patchImageBt5, sizeof(patchImageBt5));
+#endif
+}
+
+PATCH_FUN_SPEC void enterBt5CpeHdPatch(void)
+{
+#if (_NWORD_PATCHCPEHD_BT5 > 0)
+ uint32_t *pPatchCpeHd = (uint32_t *) (_BT5_CPERAM_START + _BT5_PATCH_CPEHD_OFFSET);
+
+ memcpy(pPatchCpeHd, patchCpeHd, sizeof(patchCpeHd));
+#endif
+}
+
+PATCH_FUN_SPEC void enterBt5SysPatch(void)
+{
+}
+
+PATCH_FUN_SPEC void configureBt5Patch(void)
+{
+ uint8_t *pPatchTab = (uint8_t *) (_BT5_CPERAM_START + _BT5_PATCH_TAB_OFFSET);
+
+
+ pPatchTab[76] = 0;
+ pPatchTab[91] = 1;
+ pPatchTab[79] = 2;
+}
+
+PATCH_FUN_SPEC void applyBt5Patch(void)
+{
+#ifdef _BT5_NO_PROG_STATE_VAR
+ enterBt5SysPatch();
+ enterBt5CpePatch();
+#else
+ if (!bBt5PatchEntered)
+ {
+ enterBt5SysPatch();
+ enterBt5CpePatch();
+ bBt5PatchEntered = 1;
+ }
+#endif
+ enterBt5CpeHdPatch();
+ configureBt5Patch();
+}
+
+PATCH_FUN_SPEC void refreshBt5Patch(void)
+{
+ enterBt5CpeHdPatch();
+ configureBt5Patch();
+}
+
+#ifndef _BT5_NO_PROG_STATE_VAR
+PATCH_FUN_SPEC void cleanBt5Patch(void)
+{
+ bBt5PatchEntered = 0;
+}
+#endif
+
+PATCH_FUN_SPEC void rf_patch_cpe_bt5(void)
+{
+ applyBt5Patch();
+}
+
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _RF_PATCH_CPE_BT5_H
+
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_ieee_802_15_4.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_ieee_802_15_4.h
new file mode 100644
index 0000000..855993d
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_ieee_802_15_4.h
@@ -0,0 +1,191 @@
+/******************************************************************************
+* Filename: rf_patch_cpe_ieee_802_15_4.h
+* Revised: $Date: 2019-02-27 16:13:01 +0100 (on, 27 feb 2019) $
+* Revision: $Revision: 18889 $
+*
+* Description: RF core patch for IEEE 802.15.4-2006 support ("IEEE" API command set) in CC13x2 and CC26x2
+*
+* Copyright (c) 2015-2019, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+#ifndef _RF_PATCH_CPE_IEEE_802_15_4_H
+#define _RF_PATCH_CPE_IEEE_802_15_4_H
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include <string.h>
+
+#ifndef CPE_PATCH_TYPE
+#define CPE_PATCH_TYPE static const uint32_t
+#endif
+
+#ifndef SYS_PATCH_TYPE
+#define SYS_PATCH_TYPE static const uint32_t
+#endif
+
+#ifndef PATCH_FUN_SPEC
+#define PATCH_FUN_SPEC static inline
+#endif
+
+#ifndef _APPLY_PATCH_TAB
+#define _APPLY_PATCH_TAB
+#endif
+
+
+CPE_PATCH_TYPE patchImageIeee802154[] = {
+ 0x21004051,
+ 0x79654c07,
+ 0xf809f000,
+ 0x40697961,
+ 0xd5030749,
+ 0x4a042101,
+ 0x60110389,
+ 0xb570bd70,
+ 0x47084902,
+ 0x21000380,
+ 0x40041108,
+ 0x0000592d,
+};
+#define _NWORD_PATCHIMAGE_IEEE_802_15_4 12
+
+#define _NWORD_PATCHCPEHD_IEEE_802_15_4 0
+
+#define _NWORD_PATCHSYS_IEEE_802_15_4 0
+
+
+
+#ifndef _IEEE_802_15_4_SYSRAM_START
+#define _IEEE_802_15_4_SYSRAM_START 0x20000000
+#endif
+
+#ifndef _IEEE_802_15_4_CPERAM_START
+#define _IEEE_802_15_4_CPERAM_START 0x21000000
+#endif
+
+#define _IEEE_802_15_4_SYS_PATCH_FIXED_ADDR 0x20000000
+
+#define _IEEE_802_15_4_PATCH_VEC_ADDR_OFFSET 0x03D0
+#define _IEEE_802_15_4_PATCH_TAB_OFFSET 0x03D4
+#define _IEEE_802_15_4_IRQPATCH_OFFSET 0x0480
+#define _IEEE_802_15_4_PATCH_VEC_OFFSET 0x404C
+
+#define _IEEE_802_15_4_PATCH_CPEHD_OFFSET 0x04E0
+
+#ifndef _IEEE_802_15_4_NO_PROG_STATE_VAR
+static uint8_t bIeee802154PatchEntered = 0;
+#endif
+
+PATCH_FUN_SPEC void enterIeee802154CpePatch(void)
+{
+#if (_NWORD_PATCHIMAGE_IEEE_802_15_4 > 0)
+ uint32_t *pPatchVec = (uint32_t *) (_IEEE_802_15_4_CPERAM_START + _IEEE_802_15_4_PATCH_VEC_OFFSET);
+
+ memcpy(pPatchVec, patchImageIeee802154, sizeof(patchImageIeee802154));
+#endif
+}
+
+PATCH_FUN_SPEC void enterIeee802154CpeHdPatch(void)
+{
+#if (_NWORD_PATCHCPEHD_IEEE_802_15_4 > 0)
+ uint32_t *pPatchCpeHd = (uint32_t *) (_IEEE_802_15_4_CPERAM_START + _IEEE_802_15_4_PATCH_CPEHD_OFFSET);
+
+ memcpy(pPatchCpeHd, patchCpeHd, sizeof(patchCpeHd));
+#endif
+}
+
+PATCH_FUN_SPEC void enterIeee802154SysPatch(void)
+{
+}
+
+PATCH_FUN_SPEC void configureIeee802154Patch(void)
+{
+ uint8_t *pPatchTab = (uint8_t *) (_IEEE_802_15_4_CPERAM_START + _IEEE_802_15_4_PATCH_TAB_OFFSET);
+
+
+ pPatchTab[76] = 0;
+}
+
+PATCH_FUN_SPEC void applyIeee802154Patch(void)
+{
+#ifdef _IEEE_802_15_4_NO_PROG_STATE_VAR
+ enterIeee802154SysPatch();
+ enterIeee802154CpePatch();
+#else
+ if (!bIeee802154PatchEntered)
+ {
+ enterIeee802154SysPatch();
+ enterIeee802154CpePatch();
+ bIeee802154PatchEntered = 1;
+ }
+#endif
+ enterIeee802154CpeHdPatch();
+ configureIeee802154Patch();
+}
+
+PATCH_FUN_SPEC void refreshIeee802154Patch(void)
+{
+ enterIeee802154CpeHdPatch();
+ configureIeee802154Patch();
+}
+
+#ifndef _IEEE_802_15_4_NO_PROG_STATE_VAR
+PATCH_FUN_SPEC void cleanIeee802154Patch(void)
+{
+ bIeee802154PatchEntered = 0;
+}
+#endif
+
+PATCH_FUN_SPEC void rf_patch_cpe_ieee_802_15_4(void)
+{
+ applyIeee802154Patch();
+}
+
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _RF_PATCH_CPE_IEEE_802_15_4_H
+
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_multi_protocol.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_multi_protocol.h
new file mode 100644
index 0000000..6a19733
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_multi_protocol.h
@@ -0,0 +1,246 @@
+/******************************************************************************
+* Filename: rf_patch_cpe_multi_protocol.h
+* Revised: $Date: 2019-02-27 16:13:01 +0100 (on, 27 feb 2019) $
+* Revision: $Revision: 18889 $
+*
+* Description: RF core patch for multi-protocol support (all available API command sets) in CC13x2 and CC26x2
+*
+* Copyright (c) 2015-2019, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+#ifndef _RF_PATCH_CPE_MULTI_PROTOCOL_H
+#define _RF_PATCH_CPE_MULTI_PROTOCOL_H
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include <string.h>
+
+#ifndef CPE_PATCH_TYPE
+#define CPE_PATCH_TYPE static const uint32_t
+#endif
+
+#ifndef SYS_PATCH_TYPE
+#define SYS_PATCH_TYPE static const uint32_t
+#endif
+
+#ifndef PATCH_FUN_SPEC
+#define PATCH_FUN_SPEC static inline
+#endif
+
+#ifndef _APPLY_PATCH_TAB
+#define _APPLY_PATCH_TAB
+#endif
+
+
+CPE_PATCH_TYPE patchImageMultiProtocol[] = {
+ 0x21004061,
+ 0x210040cb,
+ 0x2100408d,
+ 0x2100410d,
+ 0x210040ed,
+ 0x79654c07,
+ 0xf809f000,
+ 0x40697961,
+ 0xd5030749,
+ 0x4a042101,
+ 0x60110389,
+ 0xb570bd70,
+ 0x47084902,
+ 0x21000380,
+ 0x40041108,
+ 0x0000592d,
+ 0xf819f000,
+ 0x296cb2e1,
+ 0x2804d00b,
+ 0x2806d001,
+ 0x490ed107,
+ 0x07c97809,
+ 0x7821d103,
+ 0xd4000709,
+ 0x490b2002,
+ 0x210c780a,
+ 0xd0024211,
+ 0x22804909,
+ 0xb003600a,
+ 0xb5f0bdf0,
+ 0x4907b083,
+ 0x48044708,
+ 0x22407801,
+ 0x70014391,
+ 0x47004804,
+ 0x210000c8,
+ 0x21000133,
+ 0xe000e200,
+ 0x00031641,
+ 0x00031b23,
+ 0x21014805,
+ 0x438a6802,
+ 0x6b836002,
+ 0x6383438b,
+ 0x6002430a,
+ 0x47004801,
+ 0x40046000,
+ 0x00005b3f,
+ 0x490cb510,
+ 0x4a0c4788,
+ 0x5e512106,
+ 0xd0072900,
+ 0xd0052902,
+ 0xd0032909,
+ 0xd0012910,
+ 0xd1072911,
+ 0x43c92177,
+ 0xdd014288,
+ 0xdd012800,
+ 0x43c0207f,
+ 0x0000bd10,
+ 0x000065a9,
+ 0x21000380,
+};
+#define _NWORD_PATCHIMAGE_MULTI_PROTOCOL 63
+
+#define _NWORD_PATCHCPEHD_MULTI_PROTOCOL 0
+
+#define _NWORD_PATCHSYS_MULTI_PROTOCOL 0
+
+
+
+#ifndef _MULTI_PROTOCOL_SYSRAM_START
+#define _MULTI_PROTOCOL_SYSRAM_START 0x20000000
+#endif
+
+#ifndef _MULTI_PROTOCOL_CPERAM_START
+#define _MULTI_PROTOCOL_CPERAM_START 0x21000000
+#endif
+
+#define _MULTI_PROTOCOL_SYS_PATCH_FIXED_ADDR 0x20000000
+
+#define _MULTI_PROTOCOL_PATCH_VEC_ADDR_OFFSET 0x03D0
+#define _MULTI_PROTOCOL_PATCH_TAB_OFFSET 0x03D4
+#define _MULTI_PROTOCOL_IRQPATCH_OFFSET 0x0480
+#define _MULTI_PROTOCOL_PATCH_VEC_OFFSET 0x404C
+
+#define _MULTI_PROTOCOL_PATCH_CPEHD_OFFSET 0x04E0
+
+#ifndef _MULTI_PROTOCOL_NO_PROG_STATE_VAR
+static uint8_t bMultiProtocolPatchEntered = 0;
+#endif
+
+PATCH_FUN_SPEC void enterMultiProtocolCpePatch(void)
+{
+#if (_NWORD_PATCHIMAGE_MULTI_PROTOCOL > 0)
+ uint32_t *pPatchVec = (uint32_t *) (_MULTI_PROTOCOL_CPERAM_START + _MULTI_PROTOCOL_PATCH_VEC_OFFSET);
+
+ memcpy(pPatchVec, patchImageMultiProtocol, sizeof(patchImageMultiProtocol));
+#endif
+}
+
+PATCH_FUN_SPEC void enterMultiProtocolCpeHdPatch(void)
+{
+#if (_NWORD_PATCHCPEHD_MULTI_PROTOCOL > 0)
+ uint32_t *pPatchCpeHd = (uint32_t *) (_MULTI_PROTOCOL_CPERAM_START + _MULTI_PROTOCOL_PATCH_CPEHD_OFFSET);
+
+ memcpy(pPatchCpeHd, patchCpeHd, sizeof(patchCpeHd));
+#endif
+}
+
+PATCH_FUN_SPEC void enterMultiProtocolSysPatch(void)
+{
+}
+
+PATCH_FUN_SPEC void configureMultiProtocolPatch(void)
+{
+ uint8_t *pPatchTab = (uint8_t *) (_MULTI_PROTOCOL_CPERAM_START + _MULTI_PROTOCOL_PATCH_TAB_OFFSET);
+
+
+ pPatchTab[76] = 0;
+ pPatchTab[62] = 1;
+ pPatchTab[64] = 2;
+ pPatchTab[91] = 3;
+ pPatchTab[79] = 4;
+}
+
+PATCH_FUN_SPEC void applyMultiProtocolPatch(void)
+{
+#ifdef _MULTI_PROTOCOL_NO_PROG_STATE_VAR
+ enterMultiProtocolSysPatch();
+ enterMultiProtocolCpePatch();
+#else
+ if (!bMultiProtocolPatchEntered)
+ {
+ enterMultiProtocolSysPatch();
+ enterMultiProtocolCpePatch();
+ bMultiProtocolPatchEntered = 1;
+ }
+#endif
+ enterMultiProtocolCpeHdPatch();
+ configureMultiProtocolPatch();
+}
+
+PATCH_FUN_SPEC void refreshMultiProtocolPatch(void)
+{
+ enterMultiProtocolCpeHdPatch();
+ configureMultiProtocolPatch();
+}
+
+#ifndef _MULTI_PROTOCOL_NO_PROG_STATE_VAR
+PATCH_FUN_SPEC void cleanMultiProtocolPatch(void)
+{
+ bMultiProtocolPatchEntered = 0;
+}
+#endif
+
+PATCH_FUN_SPEC void rf_patch_cpe_multi_protocol(void)
+{
+ applyMultiProtocolPatch();
+}
+
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _RF_PATCH_CPE_MULTI_PROTOCOL_H
+
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_multi_protocol_rtls.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_multi_protocol_rtls.h
new file mode 100644
index 0000000..6c6ddc9
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_multi_protocol_rtls.h
@@ -0,0 +1,1452 @@
+/******************************************************************************
+* Filename: rf_patch_cpe_multi_protocol_rtls.h
+* Revised: $Date: 2019-02-27 16:13:01 +0100 (on, 27 feb 2019) $
+* Revision: $Revision: 18889 $
+*
+* Description: RF core patch for multi-protocol support (all available API command sets) with RTLS components in CC13x2 and CC26x2
+*
+* Copyright (c) 2015-2019, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+#ifndef _RF_PATCH_CPE_MULTI_PROTOCOL_RTLS_H
+#define _RF_PATCH_CPE_MULTI_PROTOCOL_RTLS_H
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include <string.h>
+
+#ifndef CPE_PATCH_TYPE
+#define CPE_PATCH_TYPE static const uint32_t
+#endif
+
+#ifndef SYS_PATCH_TYPE
+#define SYS_PATCH_TYPE static const uint32_t
+#endif
+
+#ifndef PATCH_FUN_SPEC
+#define PATCH_FUN_SPEC static inline
+#endif
+
+#ifndef _APPLY_PATCH_TAB
+#define _APPLY_PATCH_TAB
+#endif
+
+
+CPE_PATCH_TYPE patchImageMultiProtocolRtls[] = {
+ 0x21004631,
+ 0x21004683,
+ 0x21004075,
+ 0x2100486f,
+ 0x210040ad,
+ 0x21004117,
+ 0x210040d9,
+ 0x2100492d,
+ 0x21004139,
+ 0x21005349,
+ 0x68084908,
+ 0x43902221,
+ 0x48076008,
+ 0x68c34700,
+ 0x230260c3,
+ 0xd1fd1e5b,
+ 0x68c32210,
+ 0x60c34393,
+ 0x4770618a,
+ 0x40048000,
+ 0x00005c01,
+ 0x4801b430,
+ 0x00004700,
+ 0x00020efd,
+ 0x79654c07,
+ 0xf809f000,
+ 0x40697961,
+ 0xd5030749,
+ 0x4a042101,
+ 0x60110389,
+ 0xb570bd70,
+ 0x47084902,
+ 0x21000380,
+ 0x40041108,
+ 0x0000592d,
+ 0xf819f000,
+ 0x296cb2e1,
+ 0x2804d00b,
+ 0x2806d001,
+ 0x490ed107,
+ 0x07c97809,
+ 0x7821d103,
+ 0xd4000709,
+ 0x490b2002,
+ 0x210c780a,
+ 0xd0024211,
+ 0x22804909,
+ 0xb003600a,
+ 0xb5f0bdf0,
+ 0x4907b083,
+ 0x48044708,
+ 0x22407801,
+ 0x70014391,
+ 0x47004804,
+ 0x210000c8,
+ 0x21000133,
+ 0xe000e200,
+ 0x00031641,
+ 0x00031b23,
+ 0x21014805,
+ 0x438a6802,
+ 0x6b836002,
+ 0x6383438b,
+ 0x6002430a,
+ 0x47004801,
+ 0x40046000,
+ 0x00005b3f,
+ 0x4803b510,
+ 0x30106800,
+ 0xfe72f000,
+ 0x47084901,
+ 0x21000108,
+ 0x000095e3,
+ 0x4cffb570,
+ 0x5d002044,
+ 0x008049fe,
+ 0x68801840,
+ 0x46054780,
+ 0xd0112801,
+ 0x5d00207e,
+ 0xd30d2805,
+ 0x06002021,
+ 0x00897e41,
+ 0x7f0a1809,
+ 0xd0072a02,
+ 0x77082003,
+ 0x49f43480,
+ 0x478888a0,
+ 0xbd704628,
+ 0x77012104,
+ 0x700148f1,
+ 0xb5ffe7f4,
+ 0x7e934aec,
+ 0x49ef185b,
+ 0x3280600b,
+ 0x09897891,
+ 0x49edd16e,
+ 0x29006909,
+ 0x680bd06a,
+ 0x041bb2da,
+ 0x4be40e1c,
+ 0x7edb3360,
+ 0xd01b2c01,
+ 0x005b2410,
+ 0x1edb46a6,
+ 0x4be5469c,
+ 0x681b684d,
+ 0x00923108,
+ 0x1f121852,
+ 0x9202402b,
+ 0x4ae13030,
+ 0x93002401,
+ 0x60549103,
+ 0x26224adf,
+ 0x27106914,
+ 0x6114433c,
+ 0xe0302200,
+ 0x009b2408,
+ 0x1f9b46a6,
+ 0xc910e7e2,
+ 0x40634fd9,
+ 0x9301402b,
+ 0x24014623,
+ 0x603c0364,
+ 0x34404cd3,
+ 0x4cd26060,
+ 0x68643c40,
+ 0xd5061a24,
+ 0x3c804cd1,
+ 0x04bf6827,
+ 0xbf20d401,
+ 0x4fcbe7fa,
+ 0x633c9c01,
+ 0x44709c02,
+ 0xd90042a1,
+ 0x4cc59903,
+ 0x42346864,
+ 0x4cc3d006,
+ 0x68263c80,
+ 0x43be2702,
+ 0x26006026,
+ 0x45621c52,
+ 0x9c00d3d1,
+ 0x405c49c0,
+ 0x3940402c,
+ 0x1a12684a,
+ 0x48bcd4fc,
+ 0x48bc6304,
+ 0x60412100,
+ 0x690248bb,
+ 0x438a2110,
+ 0xbdff6102,
+ 0x212248b4,
+ 0x420a6842,
+ 0x4ab2d0fc,
+ 0x68103a80,
+ 0x43882102,
+ 0xbdff6010,
+ 0x4daab5f3,
+ 0x5d46202f,
+ 0xb08148b2,
+ 0x05806900,
+ 0x2e011600,
+ 0x1c40d002,
+ 0xe0001040,
+ 0x49ad301e,
+ 0x6a093140,
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+ 0x68402201,
+ 0x6b402300,
+ 0x5bc04611,
+ 0xf0000400,
+ 0x488dfa09,
+ 0x48924780,
+ 0x29037801,
+ 0x4882d1fc,
+ 0x8f096841,
+ 0x497e8041,
+ 0x46026848,
+ 0xe0073238,
+ 0x7c381c6d,
+ 0x42a8b2ed,
+ 0x2500d8cd,
+ 0x6848e7cb,
+ 0xd3fc4290,
+ 0x68404878,
+ 0x5bc06b40,
+ 0x48799000,
+ 0x68813840,
+ 0xf000207e,
+ 0x4873f9eb,
+ 0x6a386847,
+ 0xd0062800,
+ 0x46200041,
+ 0xf9d0f000,
+ 0xd0052900,
+ 0x496de014,
+ 0x780a69b8,
+ 0xe0334621,
+ 0xd00b2c00,
+ 0x30204638,
+ 0x07ca7fc1,
+ 0x2201d018,
+ 0x43917782,
+ 0x496f77c1,
+ 0x608802d0,
+ 0x900469b8,
+ 0x90076a38,
+ 0x46200041,
+ 0xf9b2f000,
+ 0x42819807,
+ 0x2c00d113,
+ 0x4638d00f,
+ 0x7fc13020,
+ 0xd401078a,
+ 0xe7664869,
+ 0x77822202,
+ 0x401122fd,
+ 0x200177c1,
+ 0x02c04960,
+ 0x69f86088,
+ 0x46209004,
+ 0xf0006a39,
+ 0x4852f997,
+ 0x98047802,
+ 0xfec1f7ff,
+ 0xd1042c00,
+ 0x6840484e,
+ 0x28027980,
+ 0x9806d00c,
+ 0x484b9001,
+ 0x79806840,
+ 0xd0072801,
+ 0x28004f48,
+ 0x2802d058,
+ 0xe078d07e,
+ 0xe12f2402,
+ 0xf7ff4620,
+ 0xb280fe87,
+ 0x48414684,
+ 0x6ac33040,
+ 0x68504a40,
+ 0x98016907,
+ 0x1d4800c1,
+ 0x6850543b,
+ 0x1d086903,
+ 0x4660541d,
+ 0xd00e2800,
+ 0x20006852,
+ 0x691243c0,
+ 0x50502c00,
+ 0xe002d167,
+ 0xb2a41ca4,
+ 0x9803e053,
+ 0x90031c40,
+ 0x6857e04f,
+ 0x5dc02027,
+ 0xd0012801,
+ 0xe0146950,
+ 0x30804832,
+ 0x071b6a83,
+ 0x61530f1b,
+ 0x05806a80,
+ 0x2b070e80,
+ 0x3b10dd01,
+ 0x281f6153,
+ 0x3840dd01,
+ 0x0100b200,
+ 0x010018c0,
+ 0x30ff6150,
+ 0x30014b33,
+ 0xd3014298,
+ 0x61502000,
+ 0x30804824,
+ 0x69536a40,
+ 0x18c00200,
+ 0x5058693b,
+ 0xb2816950,
+ 0xe0ca207f,
+ 0xf7ff4620,
+ 0xb281fddf,
+ 0x30404817,
+ 0x48176ac3,
+ 0x69076840,
+ 0x00c09801,
+ 0x54bb1d42,
+ 0x1d034a13,
+ 0x29006852,
+ 0x54d56912,
+ 0x4910d04e,
+ 0x68492200,
+ 0x690943d2,
+ 0x500a2c00,
+ 0x1c76d0af,
+ 0x2c01b2b6,
+ 0xf7ffd8a8,
+ 0x4809fbf5,
+ 0x8d386847,
+ 0xe00042b0,
+ 0xd303e040,
+ 0x99038d7a,
+ 0xd27e428a,
+ 0x42884914,
+ 0xe054e028,
+ 0x40043000,
+ 0x40046000,
+ 0x210053e8,
+ 0x0000aaaa,
+ 0x08180532,
+ 0x40044040,
+ 0x40045140,
+ 0x40045300,
+ 0x0000424f,
+ 0x00009083,
+ 0x00004be3,
+ 0x0000c210,
+ 0x40041100,
+ 0x00000de5,
+ 0x21000128,
+ 0x04040003,
+ 0x210002e4,
+ 0x04060003,
+ 0x00000201,
+ 0x0000ffff,
+ 0x8d78d102,
+ 0xd06f4288,
+ 0x484d2101,
+ 0x60810449,
+ 0xe684484c,
+ 0x21004a4c,
+ 0x69126852,
+ 0xe75f5011,
+ 0xf7ff4620,
+ 0xb282fcc6,
+ 0x46946878,
+ 0x98016903,
+ 0x00c04639,
+ 0x549d1d02,
+ 0x6ad34a44,
+ 0x6917687a,
+ 0x54bb1d42,
+ 0x2a004662,
+ 0x6849d00a,
+ 0x43d22200,
+ 0x2c026909,
+ 0xd800500a,
+ 0x1c76e745,
+ 0xe73fb2b6,
+ 0x68494939,
+ 0x3120468c,
+ 0x290179c9,
+ 0x4938d125,
+ 0x07136a8a,
+ 0x0f1b4a37,
+ 0x6a896997,
+ 0x0f3f073f,
+ 0x69920589,
+ 0x05920e89,
+ 0x2b070e92,
+ 0x3b10dd00,
+ 0xdd002f07,
+ 0x291f3f10,
+ 0x3940dd01,
+ 0x2a1fb209,
+ 0x3a40dd03,
+ 0xe01fe000,
+ 0x0109b212,
+ 0x19c918c9,
+ 0x18890112,
+ 0x4924010a,
+ 0x4923614a,
+ 0x694a4b26,
+ 0x320132ff,
+ 0xd301429a,
+ 0x614a2200,
+ 0x6a524a20,
+ 0x0212694b,
+ 0x466218d3,
+ 0x50136912,
+ 0xb2816948,
+ 0xf0002083,
+ 0xe6fbf873,
+ 0x98018fb9,
+ 0xf856f000,
+ 0xd1072900,
+ 0x28009801,
+ 0x8778d004,
+ 0x48102101,
+ 0x608103c9,
+ 0x68414810,
+ 0x42a18889,
+ 0xe5ecd900,
+ 0x480b2101,
+ 0x60810409,
+ 0x1e49480b,
+ 0x8d026840,
+ 0xd103428a,
+ 0x42888d40,
+ 0xe5d3d100,
+ 0x98014906,
+ 0x87486849,
+ 0xf0002081,
+ 0x2000f825,
+ 0x0000e5ef,
+ 0x40041100,
+ 0x04030003,
+ 0x210053e8,
+ 0x40046040,
+ 0x400451c0,
+ 0x40045080,
+ 0x00000201,
+ 0x49068800,
+ 0xd1064288,
+ 0x21004805,
+ 0x49058501,
+ 0x20016241,
+ 0x20824770,
+ 0x00004770,
+ 0x00006801,
+ 0x21000108,
+ 0x21004159,
+ 0x4801b403,
+ 0xbd019001,
+ 0x00003cc3,
+ 0x4801b403,
+ 0xbd019001,
+ 0x0000937d,
+ 0x4801b403,
+ 0xbd019001,
+ 0x00009361,
+ 0x4801b403,
+ 0xbd019001,
+ 0x0000867b,
+ 0x4801b403,
+ 0xbd019001,
+ 0x000049a3,
+ 0x4801b403,
+ 0xbd019001,
+ 0x00003c8f,
+ 0x4801b403,
+ 0xbd019001,
+ 0x00003ca9,
+ 0x4674b430,
+ 0x78251e64,
+ 0x42ab1c64,
+ 0x461dd200,
+ 0x005b5d63,
+ 0xbc3018e3,
+ 0x00004718,
+ 0x08180532,
+ 0x0818070e,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+};
+#define _NWORD_PATCHIMAGE_MULTI_PROTOCOL_RTLS 1261
+
+CPE_PATCH_TYPE patchCpeHd[] = {
+ 0x00000000,
+};
+#define _NWORD_PATCHCPEHD_MULTI_PROTOCOL_RTLS 1
+
+#define _NWORD_PATCHSYS_MULTI_PROTOCOL_RTLS 0
+
+
+
+#ifndef _MULTI_PROTOCOL_RTLS_SYSRAM_START
+#define _MULTI_PROTOCOL_RTLS_SYSRAM_START 0x20000000
+#endif
+
+#ifndef _MULTI_PROTOCOL_RTLS_CPERAM_START
+#define _MULTI_PROTOCOL_RTLS_CPERAM_START 0x21000000
+#endif
+
+#define _MULTI_PROTOCOL_RTLS_SYS_PATCH_FIXED_ADDR 0x20000000
+
+#define _MULTI_PROTOCOL_RTLS_PATCH_VEC_ADDR_OFFSET 0x03D0
+#define _MULTI_PROTOCOL_RTLS_PATCH_TAB_OFFSET 0x03D4
+#define _MULTI_PROTOCOL_RTLS_IRQPATCH_OFFSET 0x0480
+#define _MULTI_PROTOCOL_RTLS_PATCH_VEC_OFFSET 0x404C
+
+#define _MULTI_PROTOCOL_RTLS_PATCH_CPEHD_OFFSET 0x04E0
+
+#ifndef _MULTI_PROTOCOL_RTLS_NO_PROG_STATE_VAR
+static uint8_t bMultiProtocolRtlsPatchEntered = 0;
+#endif
+
+PATCH_FUN_SPEC void enterMultiProtocolRtlsCpePatch(void)
+{
+#if (_NWORD_PATCHIMAGE_MULTI_PROTOCOL_RTLS > 0)
+ uint32_t *pPatchVec = (uint32_t *) (_MULTI_PROTOCOL_RTLS_CPERAM_START + _MULTI_PROTOCOL_RTLS_PATCH_VEC_OFFSET);
+
+ memcpy(pPatchVec, patchImageMultiProtocolRtls, sizeof(patchImageMultiProtocolRtls));
+#endif
+}
+
+PATCH_FUN_SPEC void enterMultiProtocolRtlsCpeHdPatch(void)
+{
+#if (_NWORD_PATCHCPEHD_MULTI_PROTOCOL_RTLS > 0)
+ uint32_t *pPatchCpeHd = (uint32_t *) (_MULTI_PROTOCOL_RTLS_CPERAM_START + _MULTI_PROTOCOL_RTLS_PATCH_CPEHD_OFFSET);
+
+ memcpy(pPatchCpeHd, patchCpeHd, sizeof(patchCpeHd));
+#endif
+}
+
+PATCH_FUN_SPEC void enterMultiProtocolRtlsSysPatch(void)
+{
+}
+
+PATCH_FUN_SPEC void configureMultiProtocolRtlsPatch(void)
+{
+ uint8_t *pPatchTab = (uint8_t *) (_MULTI_PROTOCOL_RTLS_CPERAM_START + _MULTI_PROTOCOL_RTLS_PATCH_TAB_OFFSET);
+
+
+ pPatchTab[1] = 0;
+ pPatchTab[18] = 1;
+ pPatchTab[81] = 2;
+ pPatchTab[26] = 3;
+ pPatchTab[76] = 4;
+ pPatchTab[62] = 5;
+ pPatchTab[64] = 6;
+ pPatchTab[91] = 7;
+ pPatchTab[79] = 8;
+ pPatchTab[168] = 9;
+}
+
+PATCH_FUN_SPEC void applyMultiProtocolRtlsPatch(void)
+{
+#ifdef _MULTI_PROTOCOL_RTLS_NO_PROG_STATE_VAR
+ enterMultiProtocolRtlsSysPatch();
+ enterMultiProtocolRtlsCpePatch();
+#else
+ if (!bMultiProtocolRtlsPatchEntered)
+ {
+ enterMultiProtocolRtlsSysPatch();
+ enterMultiProtocolRtlsCpePatch();
+ bMultiProtocolRtlsPatchEntered = 1;
+ }
+#endif
+ enterMultiProtocolRtlsCpeHdPatch();
+ configureMultiProtocolRtlsPatch();
+}
+
+PATCH_FUN_SPEC void refreshMultiProtocolRtlsPatch(void)
+{
+ enterMultiProtocolRtlsCpeHdPatch();
+ configureMultiProtocolRtlsPatch();
+}
+
+#ifndef _MULTI_PROTOCOL_RTLS_NO_PROG_STATE_VAR
+PATCH_FUN_SPEC void cleanMultiProtocolRtlsPatch(void)
+{
+ bMultiProtocolRtlsPatchEntered = 0;
+}
+#endif
+
+PATCH_FUN_SPEC void rf_patch_cpe_multi_protocol_rtls(void)
+{
+ applyMultiProtocolRtlsPatch();
+}
+
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _RF_PATCH_CPE_MULTI_PROTOCOL_RTLS_H
+
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_prop.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_prop.h
new file mode 100644
index 0000000..e9baefa
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_prop.h
@@ -0,0 +1,219 @@
+/******************************************************************************
+* Filename: rf_patch_cpe_prop.h
+* Revised: $Date: 2019-02-27 16:13:01 +0100 (on, 27 feb 2019) $
+* Revision: $Revision: 18889 $
+*
+* Description: RF core patch for proprietary radio support ("PROP" API command set) in CC13x2 and CC26x2
+*
+* Copyright (c) 2015-2019, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+#ifndef _RF_PATCH_CPE_PROP_H
+#define _RF_PATCH_CPE_PROP_H
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include <string.h>
+
+#ifndef CPE_PATCH_TYPE
+#define CPE_PATCH_TYPE static const uint32_t
+#endif
+
+#ifndef SYS_PATCH_TYPE
+#define SYS_PATCH_TYPE static const uint32_t
+#endif
+
+#ifndef PATCH_FUN_SPEC
+#define PATCH_FUN_SPEC static inline
+#endif
+
+#ifndef _APPLY_PATCH_TAB
+#define _APPLY_PATCH_TAB
+#endif
+
+
+CPE_PATCH_TYPE patchImageProp[] = {
+ 0x21004059,
+ 0x210040c3,
+ 0x21004085,
+ 0x79654c07,
+ 0xf809f000,
+ 0x40697961,
+ 0xd5030749,
+ 0x4a042101,
+ 0x60110389,
+ 0xb570bd70,
+ 0x47084902,
+ 0x21000380,
+ 0x40041108,
+ 0x0000592d,
+ 0xf819f000,
+ 0x296cb2e1,
+ 0x2804d00b,
+ 0x2806d001,
+ 0x490ed107,
+ 0x07c97809,
+ 0x7821d103,
+ 0xd4000709,
+ 0x490b2002,
+ 0x210c780a,
+ 0xd0024211,
+ 0x22804909,
+ 0xb003600a,
+ 0xb5f0bdf0,
+ 0x4907b083,
+ 0x48044708,
+ 0x22407801,
+ 0x70014391,
+ 0x47004804,
+ 0x210000c8,
+ 0x21000133,
+ 0xe000e200,
+ 0x00031641,
+ 0x00031b23,
+};
+#define _NWORD_PATCHIMAGE_PROP 38
+
+#define _NWORD_PATCHCPEHD_PROP 0
+
+#define _NWORD_PATCHSYS_PROP 0
+
+
+
+#ifndef _PROP_SYSRAM_START
+#define _PROP_SYSRAM_START 0x20000000
+#endif
+
+#ifndef _PROP_CPERAM_START
+#define _PROP_CPERAM_START 0x21000000
+#endif
+
+#define _PROP_SYS_PATCH_FIXED_ADDR 0x20000000
+
+#define _PROP_PATCH_VEC_ADDR_OFFSET 0x03D0
+#define _PROP_PATCH_TAB_OFFSET 0x03D4
+#define _PROP_IRQPATCH_OFFSET 0x0480
+#define _PROP_PATCH_VEC_OFFSET 0x404C
+
+#define _PROP_PATCH_CPEHD_OFFSET 0x04E0
+
+#ifndef _PROP_NO_PROG_STATE_VAR
+static uint8_t bPropPatchEntered = 0;
+#endif
+
+PATCH_FUN_SPEC void enterPropCpePatch(void)
+{
+#if (_NWORD_PATCHIMAGE_PROP > 0)
+ uint32_t *pPatchVec = (uint32_t *) (_PROP_CPERAM_START + _PROP_PATCH_VEC_OFFSET);
+
+ memcpy(pPatchVec, patchImageProp, sizeof(patchImageProp));
+#endif
+}
+
+PATCH_FUN_SPEC void enterPropCpeHdPatch(void)
+{
+#if (_NWORD_PATCHCPEHD_PROP > 0)
+ uint32_t *pPatchCpeHd = (uint32_t *) (_PROP_CPERAM_START + _PROP_PATCH_CPEHD_OFFSET);
+
+ memcpy(pPatchCpeHd, patchCpeHd, sizeof(patchCpeHd));
+#endif
+}
+
+PATCH_FUN_SPEC void enterPropSysPatch(void)
+{
+}
+
+PATCH_FUN_SPEC void configurePropPatch(void)
+{
+ uint8_t *pPatchTab = (uint8_t *) (_PROP_CPERAM_START + _PROP_PATCH_TAB_OFFSET);
+
+
+ pPatchTab[76] = 0;
+ pPatchTab[62] = 1;
+ pPatchTab[64] = 2;
+}
+
+PATCH_FUN_SPEC void applyPropPatch(void)
+{
+#ifdef _PROP_NO_PROG_STATE_VAR
+ enterPropSysPatch();
+ enterPropCpePatch();
+#else
+ if (!bPropPatchEntered)
+ {
+ enterPropSysPatch();
+ enterPropCpePatch();
+ bPropPatchEntered = 1;
+ }
+#endif
+ enterPropCpeHdPatch();
+ configurePropPatch();
+}
+
+PATCH_FUN_SPEC void refreshPropPatch(void)
+{
+ enterPropCpeHdPatch();
+ configurePropPatch();
+}
+
+#ifndef _PROP_NO_PROG_STATE_VAR
+PATCH_FUN_SPEC void cleanPropPatch(void)
+{
+ bPropPatchEntered = 0;
+}
+#endif
+
+PATCH_FUN_SPEC void rf_patch_cpe_prop(void)
+{
+ applyPropPatch();
+}
+
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _RF_PATCH_CPE_PROP_H
+
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_iqdump.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_iqdump.h
new file mode 100644
index 0000000..12390d3
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_iqdump.h
@@ -0,0 +1,438 @@
+/******************************************************************************
+* Filename: rf_patch_mce_iqdump.h
+* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $
+* Revision: $Revision: 18842 $
+*
+* Description: RF core patch for IQ-dump support in CC13x2 PG2.1 and CC26x2 PG2.1
+*
+* Copyright (c) 2015-2019, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef _RF_PATCH_MCE_IQDUMP_H
+#define _RF_PATCH_MCE_IQDUMP_H
+
+#include <stdint.h>
+#include "../inc/hw_types.h"
+
+#ifndef MCE_PATCH_TYPE
+#define MCE_PATCH_TYPE static const uint32_t
+#endif
+
+#ifndef PATCH_FUN_SPEC
+#define PATCH_FUN_SPEC static inline
+#endif
+
+#ifndef RFC_MCERAM_BASE
+#define RFC_MCERAM_BASE 0x21008000
+#endif
+
+#ifndef MCE_PATCH_MODE
+#define MCE_PATCH_MODE 0
+#endif
+
+MCE_PATCH_TYPE patchIqdumpMce[337] = {
+ 0x2fcf6030,
+ 0x00013f9d,
+ 0xff00003f,
+ 0x07ff0fff,
+ 0x0300f800,
+ 0x00068080,
+ 0x00170003,
+ 0x00003d1f,
+ 0x08000000,
+ 0x0000000f,
+ 0x00000387,
+ 0x00434074,
+ 0x00828000,
+ 0x06f00080,
+ 0x091e0000,
+ 0x00540510,
+ 0x00000007,
+ 0x00505014,
+ 0xc02f0000,
+ 0x017f0c30,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x0000aa00,
+ 0x66957223,
+ 0xa4e5a35d,
+ 0x73057303,
+ 0x73047203,
+ 0x72047306,
+ 0x72917391,
+ 0xffc0b008,
+ 0xa0089010,
+ 0x720e720d,
+ 0x7210720f,
+ 0x7100b0d0,
+ 0xa0d0b110,
+ 0x8162721b,
+ 0x39521020,
+ 0x00200670,
+ 0x11011630,
+ 0x6c011401,
+ 0x60816080,
+ 0x610b60fd,
+ 0x60806080,
+ 0x60806080,
+ 0x60816080,
+ 0x61af60fd,
+ 0x60806080,
+ 0x60806080,
+ 0x60816080,
+ 0x611b60fd,
+ 0x60806080,
+ 0x60806080,
+ 0x60816080,
+ 0x61cb60fd,
+ 0x60806080,
+ 0x60806080,
+ 0x60816080,
+ 0x615360fd,
+ 0x72231210,
+ 0x73127311,
+ 0x81b17313,
+ 0x91b00010,
+ 0x6044b070,
+ 0xc0306076,
+ 0xc0c1669b,
+ 0xc4e0c2b2,
+ 0x6f131820,
+ 0x16116e23,
+ 0x68871612,
+ 0x99c07830,
+ 0x948078a0,
+ 0xc4f29490,
+ 0x1820c750,
+ 0x12034099,
+ 0x16126e23,
+ 0x78b06896,
+ 0x72639990,
+ 0x6076b63c,
+ 0x96408190,
+ 0x39808170,
+ 0x10012a70,
+ 0x84a21611,
+ 0xc0f384b4,
+ 0xc200c0f5,
+ 0x40c21c01,
+ 0x1c10c100,
+ 0x4cba40b8,
+ 0x18031013,
+ 0x1a131830,
+ 0x39121a10,
+ 0x60c268b5,
+ 0x60c213f3,
+ 0x101513f3,
+ 0x1850c100,
+ 0x1a101a15,
+ 0x68c03914,
+ 0x7100b0e8,
+ 0xa0e8b128,
+ 0xb910b230,
+ 0x99308990,
+ 0xb0d1b111,
+ 0xb0027100,
+ 0xb111b012,
+ 0x7291a0d1,
+ 0xb003b630,
+ 0x722cb013,
+ 0x7100b0e0,
+ 0x8170b120,
+ 0x710092c0,
+ 0x8170b120,
+ 0x44db22f0,
+ 0x1c0313f0,
+ 0x92c340e7,
+ 0x71009642,
+ 0x92c5b120,
+ 0x71009644,
+ 0xb0e0b120,
+ 0x7000a630,
+ 0xc030a0e1,
+ 0xc0409910,
+ 0xb1119930,
+ 0x7100b0d1,
+ 0xa0d1b111,
+ 0xa0037291,
+ 0xa230a002,
+ 0x73117000,
+ 0xc0407312,
+ 0xc100669b,
+ 0x649e91f0,
+ 0xb113b633,
+ 0x7100b0d3,
+ 0x64eea0d3,
+ 0xa0d26076,
+ 0xa0f3a0f0,
+ 0x73127311,
+ 0xc050660f,
+ 0xb0d2669b,
+ 0x7100c035,
+ 0xba389b75,
+ 0xb112b074,
+ 0xa0d26115,
+ 0xa0f3a0f0,
+ 0x73127311,
+ 0xc18b660f,
+ 0x91e0c000,
+ 0x1218120c,
+ 0x787d786a,
+ 0x10a9788e,
+ 0xb0d2b074,
+ 0xb112c020,
+ 0x692d7100,
+ 0x669bc060,
+ 0xb112c035,
+ 0x9b757100,
+ 0x65a48bf0,
+ 0x22018ca1,
+ 0x10804140,
+ 0x453f1ca8,
+ 0x16181208,
+ 0x8c00659b,
+ 0x8ca165a4,
+ 0x414b2201,
+ 0x1a191090,
+ 0x454b1e09,
+ 0x659b10a9,
+ 0x1e048184,
+ 0x14bc4133,
+ 0x4e7e1c4c,
+ 0xa0d26133,
+ 0xa0f3a0f0,
+ 0x73127311,
+ 0x721e660f,
+ 0x1205120c,
+ 0xb0d2b074,
+ 0xb112c020,
+ 0x695f7100,
+ 0x669bc070,
+ 0x89ce789d,
+ 0x7100b112,
+ 0x22008c90,
+ 0x8230416f,
+ 0x456f2210,
+ 0x9a3db231,
+ 0x31828ab2,
+ 0x8af03d82,
+ 0x3d803180,
+ 0x063e1802,
+ 0x41911e0e,
+ 0x41831e2e,
+ 0x418a1e3e,
+ 0x14261056,
+ 0x10653d16,
+ 0x10566192,
+ 0x18563126,
+ 0x3d261426,
+ 0x61921065,
+ 0x31361056,
+ 0x14261856,
+ 0x10653d36,
+ 0x10266192,
+ 0x91c63976,
+ 0x1e048184,
+ 0x161c4166,
+ 0x4e7e1c4c,
+ 0x10016166,
+ 0x91c1c0b0,
+ 0x10003911,
+ 0x10001000,
+ 0x7000699d,
+ 0x3d303130,
+ 0x4dab1cd0,
+ 0x49ad1ce0,
+ 0x10d07000,
+ 0x10e07000,
+ 0xc0807000,
+ 0xa0d2669b,
+ 0xa0f3a0f0,
+ 0x73127311,
+ 0xb130660f,
+ 0x7100b0f0,
+ 0x220080b0,
+ 0x61b945be,
+ 0xc090b231,
+ 0xb130669b,
+ 0xb0d2a0f0,
+ 0x7100c035,
+ 0xba389b75,
+ 0xb112b074,
+ 0xc0a061c5,
+ 0xa0d2669b,
+ 0xa0f3a0f0,
+ 0x73127311,
+ 0xc18b660f,
+ 0x91e0c000,
+ 0x1218120c,
+ 0x787d786a,
+ 0x10a9788e,
+ 0xb0f0b130,
+ 0x80b07100,
+ 0x45e32200,
+ 0xb07461de,
+ 0xc0b0b231,
+ 0xb130669b,
+ 0xb0d2a0f0,
+ 0xb112c020,
+ 0x69eb7100,
+ 0xb112c035,
+ 0x9b757100,
+ 0x65a48bf0,
+ 0x22018ca1,
+ 0x108041fc,
+ 0x45fb1ca8,
+ 0x16181208,
+ 0x8c00659b,
+ 0x8ca165a4,
+ 0x42072201,
+ 0x1a191090,
+ 0x46071e09,
+ 0x659b10a9,
+ 0x1e048184,
+ 0x14bc41ef,
+ 0x4e7e1c4c,
+ 0x824061ef,
+ 0x46172230,
+ 0x7100b0d5,
+ 0xa0d5b115,
+ 0xc0c0620f,
+ 0xb118669b,
+ 0xb016b006,
+ 0xb014b004,
+ 0xb012b002,
+ 0x78428440,
+ 0x81730420,
+ 0x2a733983,
+ 0xc1f294e3,
+ 0x31621832,
+ 0x31511021,
+ 0x00200012,
+ 0x10309440,
+ 0x39301610,
+ 0x42352210,
+ 0x31501220,
+ 0x31801003,
+ 0x93801630,
+ 0x12041202,
+ 0x42472273,
+ 0x997084a0,
+ 0x1a828982,
+ 0x997084c0,
+ 0x1a848984,
+ 0x22636249,
+ 0x84b04254,
+ 0x89809970,
+ 0x14021a80,
+ 0x997084d0,
+ 0x1a808980,
+ 0x62601404,
+ 0x785184b0,
+ 0x99700410,
+ 0x1a428982,
+ 0x785184d0,
+ 0x99700410,
+ 0x1a448984,
+ 0x31543152,
+ 0x06333963,
+ 0x38321613,
+ 0x31823834,
+ 0x31843982,
+ 0x97220042,
+ 0x959084a0,
+ 0x95a084b0,
+ 0x95b084c0,
+ 0x95c084d0,
+ 0x90307810,
+ 0x78209050,
+ 0x90609040,
+ 0xcd90b235,
+ 0x70009170,
+ 0xb112a235,
+ 0xa0d27100,
+ 0xba3cb112,
+ 0x8b5481b0,
+ 0x31843924,
+ 0x91b40004,
+ 0x669bc0d0,
+ 0x72917391,
+ 0x72066695,
+ 0x72047202,
+ 0x73067305,
+ 0x86306076,
+ 0x3151c801,
+ 0x96300410,
+ 0x9a007000,
+ 0x220089f0,
+ 0xb9e0469c,
+ 0x00007000
+};
+
+PATCH_FUN_SPEC void rf_patch_mce_iqdump(void)
+{
+#ifdef __PATCH_NO_UNROLLING
+ uint32_t i;
+ for (i = 0; i < 337; i++) {
+ HWREG(RFC_MCERAM_BASE + 4 * i) = patchIqdumpMce[i];
+ }
+#else
+ const uint32_t *pS = patchIqdumpMce;
+ volatile unsigned long *pD = &HWREG(RFC_MCERAM_BASE);
+ uint32_t t1, t2, t3, t4, t5, t6, t7, t8;
+ uint32_t nIterations = 42;
+
+ do {
+ t1 = *pS++;
+ t2 = *pS++;
+ t3 = *pS++;
+ t4 = *pS++;
+ t5 = *pS++;
+ t6 = *pS++;
+ t7 = *pS++;
+ t8 = *pS++;
+ *pD++ = t1;
+ *pD++ = t2;
+ *pD++ = t3;
+ *pD++ = t4;
+ *pD++ = t5;
+ *pD++ = t6;
+ *pD++ = t7;
+ *pD++ = t8;
+ } while (--nIterations);
+
+ t1 = *pS++;
+ *pD++ = t1;
+#endif
+}
+
+#endif
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_tof.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_tof.h
new file mode 100644
index 0000000..eeabf34
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_tof.h
@@ -0,0 +1,609 @@
+/******************************************************************************
+* Filename: rf_patch_mce_tof.h
+* Revised: $Date: 2019-01-31 15:04:59 +0100 (to, 31 jan 2019) $
+* Revision: $Revision: 18843 $
+*
+* Description: RF core MCE patch for time of flight 2Mbps PHY for CC13x2 and CC26x2
+*
+* Copyright (c) 2015-2019, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef _RF_PATCH_MCE_TOF_H
+#define _RF_PATCH_MCE_TOF_H
+
+#include <stdint.h>
+#include "../inc/hw_types.h"
+
+#ifndef MCE_PATCH_TYPE
+#define MCE_PATCH_TYPE static const uint32_t
+#endif
+
+#ifndef PATCH_FUN_SPEC
+#define PATCH_FUN_SPEC static inline
+#endif
+
+#ifndef RFC_MCERAM_BASE
+#define RFC_MCERAM_BASE 0x21008000
+#endif
+
+#ifndef MCE_PATCH_MODE
+#define MCE_PATCH_MODE 0
+#endif
+
+MCE_PATCH_TYPE patchTofMce[506] = {
+ 0x0003605b,
+ 0x00f1000f,
+ 0x00000000,
+ 0x000c8000,
+ 0x00000000,
+ 0x0c650000,
+ 0x80000000,
+ 0x00800010,
+ 0x00000000,
+ 0x0594091e,
+ 0x00000350,
+ 0x7c200000,
+ 0x000000c2,
+ 0x34340013,
+ 0x0003005a,
+ 0x00000032,
+ 0xfe6b2840,
+ 0xdeade8ca,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x07d00011,
+ 0x6fdd2fea,
+ 0x0fb00ff0,
+ 0xf80f0003,
+ 0x007f7f30,
+ 0x3434001f,
+ 0x8010005a,
+ 0x01900000,
+ 0x40000800,
+ 0xc0300c65,
+ 0x722367ee,
+ 0xa35d7263,
+ 0x73057303,
+ 0x73047203,
+ 0x72047306,
+ 0x72917391,
+ 0x8001c7c0,
+ 0x90010001,
+ 0x08019010,
+ 0x720d9001,
+ 0x720f720e,
+ 0xb0d07210,
+ 0xc0407100,
+ 0xa0d067ee,
+ 0x721bb110,
+ 0x10208162,
+ 0x06703952,
+ 0x16300020,
+ 0x14011101,
+ 0x60936c01,
+ 0x60c260a4,
+ 0x6219617b,
+ 0x60936093,
+ 0x60936093,
+ 0x60c260a4,
+ 0x6219617b,
+ 0x60936093,
+ 0x60976093,
+ 0x12206095,
+ 0xc050609a,
+ 0x121267ee,
+ 0x73117223,
+ 0x73137312,
+ 0x81b17314,
+ 0x91b20012,
+ 0x6073b070,
+ 0xc2b2c011,
+ 0x1820c710,
+ 0x6e236f13,
+ 0x16121611,
+ 0x7d7068a8,
+ 0xc0229990,
+ 0x39818161,
+ 0xd0601812,
+ 0x67ee9a12,
+ 0x40971e01,
+ 0x99907d80,
+ 0x93807d50,
+ 0x93307d60,
+ 0x93007d90,
+ 0x6097b360,
+ 0xc07067e5,
+ 0x677e67ee,
+ 0x91f0c070,
+ 0x670bb750,
+ 0xb233b914,
+ 0xa750672d,
+ 0x95b488d4,
+ 0x95c488e4,
+ 0x95948ca4,
+ 0x95a487c4,
+ 0x2a007cb0,
+ 0x88d49060,
+ 0x88e495d4,
+ 0xc0f495e4,
+ 0x91449134,
+ 0x22008c80,
+ 0xb0f040e5,
+ 0xb0f6b130,
+ 0xb0d5b0d0,
+ 0xb110b136,
+ 0xb140b100,
+ 0x73137314,
+ 0x2a007cb0,
+ 0xc0f19060,
+ 0x40f51e0e,
+ 0x99311611,
+ 0xc037b912,
+ 0xb115b041,
+ 0xa910c031,
+ 0xb0737100,
+ 0xba3eb910,
+ 0x22008090,
+ 0x80b24574,
+ 0x45182262,
+ 0x220280c2,
+ 0xb061410b,
+ 0x2250b140,
+ 0x824040f9,
+ 0x45152200,
+ 0x40f9220f,
+ 0x679e100f,
+ 0x100f60f9,
+ 0x60f967b4,
+ 0xb234a913,
+ 0x93acba39,
+ 0xa0d58462,
+ 0xb0d1720f,
+ 0x7100b111,
+ 0xb1119937,
+ 0xb35d7100,
+ 0x9930c3f0,
+ 0xc0d0b074,
+ 0x894193f0,
+ 0x67bf9791,
+ 0x14018941,
+ 0x7100b111,
+ 0xba3aba3b,
+ 0xc210b078,
+ 0xa2329930,
+ 0xb111b235,
+ 0xa35d7100,
+ 0x7291b06e,
+ 0x8af2a0d1,
+ 0x3d823182,
+ 0x67eec080,
+ 0x8c528c33,
+ 0x8c441423,
+ 0x14248c62,
+ 0x06f28b32,
+ 0x31418b21,
+ 0x97a20012,
+ 0x0424cff2,
+ 0x31433143,
+ 0x97b40034,
+ 0x6957c8f0,
+ 0xb130b235,
+ 0xb136a0f0,
+ 0xb140a0f6,
+ 0xb914a100,
+ 0xa7507291,
+ 0xa002a003,
+ 0x9010c7c0,
+ 0x72047203,
+ 0x73067305,
+ 0xa23267e5,
+ 0x8242b235,
+ 0x456b1e02,
+ 0xc0907223,
+ 0x609767ee,
+ 0xa232b235,
+ 0xd0a08942,
+ 0x67ee9a12,
+ 0x67e56159,
+ 0x677ec00f,
+ 0x91f0c070,
+ 0xc0b0670b,
+ 0xb01367ee,
+ 0x22008c80,
+ 0xb0f04189,
+ 0xb0f6b130,
+ 0xb0d5b0d0,
+ 0xb136b111,
+ 0x72917313,
+ 0xc0e1b912,
+ 0x41951e0e,
+ 0x99311611,
+ 0xb041c037,
+ 0xc031b232,
+ 0xb115a910,
+ 0xb0737100,
+ 0xba3eb910,
+ 0x22008090,
+ 0x80b24614,
+ 0x45b32262,
+ 0x41992250,
+ 0x22008240,
+ 0x220f45b0,
+ 0x100f4199,
+ 0x6199679e,
+ 0x67b4100f,
+ 0xb9136199,
+ 0xba39b234,
+ 0xa0d593ac,
+ 0x7313720f,
+ 0x73147210,
+ 0x264081b0,
+ 0xb0d191b0,
+ 0x7100b111,
+ 0x9937b041,
+ 0x7100b111,
+ 0xc3f0b35d,
+ 0xb0749930,
+ 0x93f0c0d0,
+ 0x7100b111,
+ 0xc210b078,
+ 0xa2329930,
+ 0x7100b111,
+ 0xb06ea35d,
+ 0xa0d1a910,
+ 0x899167bf,
+ 0x81a01401,
+ 0x99311401,
+ 0xb0d6b116,
+ 0xb1167100,
+ 0x8090a0d6,
+ 0x46142200,
+ 0x88d4b012,
+ 0x88e495b4,
+ 0x8ca495c4,
+ 0x87c49594,
+ 0x729195a4,
+ 0x2a208230,
+ 0x92302630,
+ 0xc070672d,
+ 0x8af287b1,
+ 0x3d823182,
+ 0x69fbc310,
+ 0xb111b064,
+ 0xa0f6b136,
+ 0xa0f0b130,
+ 0x8242b235,
+ 0x46021e02,
+ 0x7291b914,
+ 0xa002a003,
+ 0x9010c7c0,
+ 0x72047203,
+ 0x73067305,
+ 0x67eec0c0,
+ 0x609767e5,
+ 0x67eec0d0,
+ 0x7291b235,
+ 0x677e6202,
+ 0xc070c00b,
+ 0x670b91f0,
+ 0x67eec0e0,
+ 0x727ab914,
+ 0xb0137226,
+ 0x73147313,
+ 0x8c8072c9,
+ 0x422d2200,
+ 0xb130b0f0,
+ 0x85b06231,
+ 0x95d085c1,
+ 0xb10095e1,
+ 0xb110b140,
+ 0xb0f6b064,
+ 0xb0d5b0d0,
+ 0x7313b136,
+ 0xb041b061,
+ 0x42411e1b,
+ 0xb9127291,
+ 0xc13772c9,
+ 0x1e0ec070,
+ 0x16104247,
+ 0x9930c0b7,
+ 0xb115b232,
+ 0xa910c031,
+ 0xb0737100,
+ 0xba3eb910,
+ 0x22008090,
+ 0x80b24705,
+ 0x46682262,
+ 0x220280c2,
+ 0xb061425b,
+ 0x2250b140,
+ 0x82404249,
+ 0x46652200,
+ 0x4249220f,
+ 0x679e100f,
+ 0x100f6249,
+ 0x624967b4,
+ 0x1e1bb234,
+ 0xa9154285,
+ 0xb913b916,
+ 0x8b33ba3b,
+ 0x8b2406f3,
+ 0x00433144,
+ 0x8c3397a3,
+ 0x14038c50,
+ 0x8c448c60,
+ 0x31431404,
+ 0x00343143,
+ 0x81b097b4,
+ 0x91b02650,
+ 0x67eec0f0,
+ 0xa91362bf,
+ 0x264081b0,
+ 0x993791b0,
+ 0x93acba39,
+ 0x720fa0d5,
+ 0xb111b0d1,
+ 0x7100b111,
+ 0xc3e0b35d,
+ 0xb0749930,
+ 0x93f0c0d0,
+ 0x97918941,
+ 0xb11167bf,
+ 0xb0787100,
+ 0x9930c210,
+ 0xb235a232,
+ 0x7100b111,
+ 0xb06ea35d,
+ 0xa0d17291,
+ 0x31828af2,
+ 0xba3b3d82,
+ 0x06f38b33,
+ 0x31448b24,
+ 0x92630043,
+ 0x8c508c33,
+ 0x8c601403,
+ 0x14048c44,
+ 0x31433143,
+ 0x97b40034,
+ 0x6abdc8f0,
+ 0xbc9062e3,
+ 0x95b488d4,
+ 0x95c488e4,
+ 0x95948ca4,
+ 0x95a487c4,
+ 0x85b0c01b,
+ 0x95d085c1,
+ 0x731195e1,
+ 0x73137312,
+ 0xb1007314,
+ 0xb0f6b140,
+ 0xb110b136,
+ 0xa232b064,
+ 0x22628242,
+ 0x722342d7,
+ 0xb115b064,
+ 0xc410b232,
+ 0x679e6ae0,
+ 0xb2356249,
+ 0xa100b140,
+ 0xa0f6b136,
+ 0x7291b914,
+ 0xa003a750,
+ 0xc7c0a002,
+ 0x72039010,
+ 0x73057204,
+ 0x73117306,
+ 0x73137312,
+ 0x720f7314,
+ 0x7210720d,
+ 0x7223720e,
+ 0xb235a232,
+ 0x1e028242,
+ 0x722346fc,
+ 0x67eec100,
+ 0xc1106097,
+ 0xb23567ee,
+ 0x8942a232,
+ 0x824262e4,
+ 0x430b2212,
+ 0xb016b006,
+ 0xb002b012,
+ 0xb014b004,
+ 0x90307ca0,
+ 0x7cb09050,
+ 0x90609040,
+ 0x73127311,
+ 0x73147313,
+ 0x720e720d,
+ 0x7210720f,
+ 0xb0e1b121,
+ 0xb0727100,
+ 0xd680a0e1,
+ 0x679e6b28,
+ 0x93f0c090,
+ 0xbc907000,
+ 0x9930c040,
+ 0xb910b911,
+ 0xb111b0d1,
+ 0x72917100,
+ 0xb111a0d1,
+ 0x9635722c,
+ 0xc0f38c82,
+ 0xb013b003,
+ 0x92c08170,
+ 0x96408190,
+ 0xb120b0e0,
+ 0x22027100,
+ 0x85b04750,
+ 0x92c39640,
+ 0x7100b120,
+ 0x964085c0,
+ 0x7100b120,
+ 0x96408590,
+ 0xb12092c3,
+ 0x85a07100,
+ 0xb1209640,
+ 0x8cb07100,
+ 0x0410cff1,
+ 0xb1209640,
+ 0x96367100,
+ 0x9930c040,
+ 0xb910b911,
+ 0xb111b0d1,
+ 0xb120a0e0,
+ 0x72917100,
+ 0xb111a0d1,
+ 0x1e108750,
+ 0xb2354371,
+ 0xa9156378,
+ 0xb913b916,
+ 0x2a308230,
+ 0x92302620,
+ 0x6b79c090,
+ 0xc120ac90,
+ 0x700067ee,
+ 0x721b7223,
+ 0x92c0c0f0,
+ 0xc1f1722f,
+ 0xc01592d1,
+ 0x7c977c86,
+ 0x8c807ccc,
+ 0x43912200,
+ 0x94407cf0,
+ 0x94607d10,
+ 0x7d206393,
+ 0xac909440,
+ 0xc1009636,
+ 0x816e91e0,
+ 0xc01d398e,
+ 0x439d1e0e,
+ 0x7000c03d,
+ 0x726a7269,
+ 0xb0537ce2,
+ 0xc76093a2,
+ 0x73a36ba4,
+ 0x96908a40,
+ 0x96a18a51,
+ 0x7cd093a6,
+ 0x8a4393a0,
+ 0x31338a54,
+ 0x31343d33,
+ 0x70003d34,
+ 0x8a439a31,
+ 0x31338a54,
+ 0x31343d63,
+ 0x96933d64,
+ 0xb05396a4,
+ 0x1e0e7000,
+ 0x8c3143d6,
+ 0x18108c40,
+ 0xc0024fd0,
+ 0x161110d1,
+ 0x16201812,
+ 0x1c203d20,
+ 0x10204fe4,
+ 0x63e41610,
+ 0x3d201620,
+ 0x4be41cd0,
+ 0x63e410d0,
+ 0xc082c000,
+ 0x8c448c33,
+ 0x1c241834,
+ 0x14424fe0,
+ 0x63e44be2,
+ 0x63e410d0,
+ 0x18d0c000,
+ 0x720d7000,
+ 0x720f720e,
+ 0x73117210,
+ 0x73137312,
+ 0x70007314,
+ 0x89f09a00,
+ 0x47ef2200,
+ 0x7000b9e0
+};
+
+PATCH_FUN_SPEC void rf_patch_mce_tof(void)
+{
+#ifdef __PATCH_NO_UNROLLING
+ uint32_t i;
+ for (i = 0; i < 506; i++) {
+ HWREG(RFC_MCERAM_BASE + 4 * i) = patchTofMce[i];
+ }
+#else
+ const uint32_t *pS = patchTofMce;
+ volatile unsigned long *pD = &HWREG(RFC_MCERAM_BASE);
+ uint32_t t1, t2, t3, t4, t5, t6, t7, t8;
+ uint32_t nIterations = 63;
+
+ do {
+ t1 = *pS++;
+ t2 = *pS++;
+ t3 = *pS++;
+ t4 = *pS++;
+ t5 = *pS++;
+ t6 = *pS++;
+ t7 = *pS++;
+ t8 = *pS++;
+ *pD++ = t1;
+ *pD++ = t2;
+ *pD++ = t3;
+ *pD++ = t4;
+ *pD++ = t5;
+ *pD++ = t6;
+ *pD++ = t7;
+ *pD++ = t8;
+ } while (--nIterations);
+
+ t1 = *pS++;
+ t2 = *pS++;
+ *pD++ = t1;
+ *pD++ = t2;
+#endif
+}
+
+#endif
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_rfe_tof.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_rfe_tof.h
new file mode 100644
index 0000000..d09cb4a
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_rfe_tof.h
@@ -0,0 +1,571 @@
+/******************************************************************************
+* Filename: rf_patch_rfe_tof.h
+* Revised: $Date: 2019-01-31 15:04:59 +0100 (to, 31 jan 2019) $
+* Revision: $Revision: 18843 $
+*
+* Description: RF core RFE patch for time of flight 2Mbps PHY for CC13x2 and CC26x2
+*
+* Copyright (c) 2015-2019, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1) Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2) Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
+* be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+
+#ifndef _RF_PATCH_RFE_TOF_H
+#define _RF_PATCH_RFE_TOF_H
+
+#include <stdint.h>
+#include "../inc/hw_types.h"
+
+#ifndef RFE_PATCH_TYPE
+#define RFE_PATCH_TYPE static const uint32_t
+#endif
+
+#ifndef PATCH_FUN_SPEC
+#define PATCH_FUN_SPEC static inline
+#endif
+
+#ifndef RFC_RFERAM_BASE
+#define RFC_RFERAM_BASE 0x2100C000
+#endif
+
+#ifndef RFE_PATCH_MODE
+#define RFE_PATCH_MODE 0
+#endif
+
+RFE_PATCH_TYPE patchTofRfe[461] = {
+ 0x00006194,
+ 0x004535aa,
+ 0x0421a355,
+ 0x1f40004c,
+ 0x0000003f,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x40004030,
+ 0x40034001,
+ 0x400f4007,
+ 0x40cf404f,
+ 0x43cf41cf,
+ 0x4fcf47cf,
+ 0x2fcf3fcf,
+ 0x0fcf1fcf,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x40004030,
+ 0x40034001,
+ 0x400f4007,
+ 0x40cf404f,
+ 0x6fcf7fcf,
+ 0x4fcf5fcf,
+ 0x2fcf3fcf,
+ 0x0fcf1fcf,
+ 0x00000000,
+ 0x00000000,
+ 0x9100c050,
+ 0xc0707000,
+ 0x70009100,
+ 0x00213182,
+ 0xb1109131,
+ 0x81017000,
+ 0xa100b101,
+ 0x91323182,
+ 0x9101b110,
+ 0x81411011,
+ 0x40772241,
+ 0x700006f1,
+ 0x9150c050,
+ 0xc0707000,
+ 0x70009150,
+ 0x00213182,
+ 0xb1609181,
+ 0x10257000,
+ 0x9100c050,
+ 0xc140c3f4,
+ 0x6f031420,
+ 0x04411031,
+ 0x22f082a0,
+ 0x26514094,
+ 0x3182c022,
+ 0x91310021,
+ 0x3963b110,
+ 0x04411031,
+ 0x3182c082,
+ 0x91310021,
+ 0x3963b110,
+ 0xc0a21031,
+ 0x00213182,
+ 0xb1109131,
+ 0x31151050,
+ 0x92551405,
+ 0x64677000,
+ 0x1031c2b2,
+ 0x31610631,
+ 0x646a02c1,
+ 0x1031c112,
+ 0x06713921,
+ 0x02e13151,
+ 0x7000646a,
+ 0x82b16464,
+ 0x39813181,
+ 0x646ac0e2,
+ 0xc1116467,
+ 0x646ac122,
+ 0x68c7c470,
+ 0xc0c2c111,
+ 0x64e0646a,
+ 0x700064f3,
+ 0x82b1647c,
+ 0x39813181,
+ 0x6482c182,
+ 0xc111647f,
+ 0x6482c0a2,
+ 0x68d9c470,
+ 0xc162c331,
+ 0x64e06482,
+ 0x700064f3,
+ 0xb054b050,
+ 0x80407100,
+ 0x44ed2240,
+ 0x40e02200,
+ 0x8081b060,
+ 0x44e01e11,
+ 0xa0547000,
+ 0x80f0b064,
+ 0x40e02200,
+ 0x12407000,
+ 0xb03290b0,
+ 0x395382a3,
+ 0x64ad3953,
+ 0x68fbc2f0,
+ 0xc1f18080,
+ 0xc1510410,
+ 0x41071c10,
+ 0xc2216467,
+ 0x646ac0c2,
+ 0x647f610b,
+ 0xc162c441,
+ 0xce306482,
+ 0x1280690c,
+ 0xb03290b0,
+ 0x64677000,
+ 0xc0c2c201,
+ 0x80a0646a,
+ 0x39403180,
+ 0xc1016918,
+ 0x646ac0c2,
+ 0xc122c101,
+ 0x82a3646a,
+ 0x12c064ad,
+ 0xb03290b0,
+ 0x647f7000,
+ 0xc162c401,
+ 0x80a06482,
+ 0x39403180,
+ 0xc301692c,
+ 0x6482c162,
+ 0xc0a2c101,
+ 0x82a36482,
+ 0x12c064ad,
+ 0xb03290b0,
+ 0x64677000,
+ 0xc081c272,
+ 0xc122646a,
+ 0x646ac111,
+ 0xc111c002,
+ 0xc062646a,
+ 0x646ac331,
+ 0xc111c362,
+ 0xc302646a,
+ 0x646ac111,
+ 0x395382a3,
+ 0xc3e264ad,
+ 0x2211646f,
+ 0xc242414f,
+ 0x646ac881,
+ 0xc111c252,
+ 0xc272646a,
+ 0x646acee1,
+ 0xc881c202,
+ 0xc202646a,
+ 0x646ac801,
+ 0x6963c170,
+ 0x64677000,
+ 0xc801c242,
+ 0xc252646a,
+ 0x646ac011,
+ 0xc0e1c272,
+ 0xc002646a,
+ 0x646ac101,
+ 0xc301c062,
+ 0xc122646a,
+ 0x646ac101,
+ 0xc101c362,
+ 0xc302646a,
+ 0x646ac101,
+ 0x64ad82a3,
+ 0x80817000,
+ 0x418f1e11,
+ 0xb054b050,
+ 0x80407100,
+ 0x41902240,
+ 0xb064a054,
+ 0x220180f1,
+ 0x70004584,
+ 0x41842200,
+ 0x6181b060,
+ 0x72057306,
+ 0x720e720b,
+ 0x7100b050,
+ 0xa050b060,
+ 0x80928081,
+ 0x45b32241,
+ 0xc1f18080,
+ 0x16300410,
+ 0x14011101,
+ 0x61c66c01,
+ 0x61c661c6,
+ 0x61c661c6,
+ 0x61e661c6,
+ 0x61e661c6,
+ 0x61c661c6,
+ 0x809161c6,
+ 0x0421c0f2,
+ 0x80823121,
+ 0x14122a42,
+ 0x11011632,
+ 0x6c011421,
+ 0x61c661cf,
+ 0x61c661cf,
+ 0x61c661c6,
+ 0x61c661c6,
+ 0x61c861c8,
+ 0x61cbb0b0,
+ 0x7306b0b1,
+ 0xb0307205,
+ 0x78206198,
+ 0x78427831,
+ 0x78547873,
+ 0x78667885,
+ 0x92719260,
+ 0x92939282,
+ 0x92b592a4,
+ 0xc01f91a6,
+ 0x3940924f,
+ 0x100106f0,
+ 0x14103110,
+ 0x61c89250,
+ 0xcff0b060,
+ 0x66306793,
+ 0xb0e16624,
+ 0xb054b050,
+ 0x8262b064,
+ 0x39823182,
+ 0x64873942,
+ 0x7100b0e1,
+ 0x22008040,
+ 0xb0644621,
+ 0x225280f2,
+ 0x22224611,
+ 0x22324608,
+ 0x1e02460f,
+ 0xdfe041f5,
+ 0x67939342,
+ 0x61f56511,
+ 0x663f663a,
+ 0x80f0b064,
+ 0x46112250,
+ 0x663561f5,
+ 0xcfd061f5,
+ 0xa0546793,
+ 0xa050b064,
+ 0xa052b060,
+ 0xa053b062,
+ 0x6565b063,
+ 0xcfc06511,
+ 0x720e6793,
+ 0xcfb061c8,
+ 0x62116793,
+ 0x82b16464,
+ 0x39813181,
+ 0x646ac0e2,
+ 0xc1116467,
+ 0x646ac122,
+ 0x700064f3,
+ 0x70006539,
+ 0x70006511,
+ 0x64676565,
+ 0xc0c2c111,
+ 0x7000646a,
+ 0xc1016467,
+ 0x646ac0c2,
+ 0xc8007000,
+ 0x81a991b0,
+ 0x8091b050,
+ 0x46b02241,
+ 0x31828262,
+ 0x39423982,
+ 0x82626487,
+ 0x102f06f2,
+ 0x142f311f,
+ 0x22d68266,
+ 0xc1404655,
+ 0xc5006256,
+ 0x6f0d1420,
+ 0x10de396d,
+ 0x044ec3f4,
+ 0x3182c082,
+ 0x396d002e,
+ 0x3182c0a2,
+ 0x826a002d,
+ 0x06fa398a,
+ 0x31808270,
+ 0xc00b3980,
+ 0x10bc180b,
+ 0x825318ac,
+ 0x149b1439,
+ 0x06f08260,
+ 0x31101001,
+ 0x81a11410,
+ 0x140c1410,
+ 0x46ea22c6,
+ 0x39408280,
+ 0x100206f0,
+ 0x3001c011,
+ 0x1801c010,
+ 0x31821802,
+ 0x26c10021,
+ 0xb00391e1,
+ 0xb063b013,
+ 0x8041b053,
+ 0x46e12201,
+ 0x92148204,
+ 0x1cb58225,
+ 0x18954e99,
+ 0x80f091b5,
+ 0x428b2240,
+ 0x913d62ae,
+ 0x913eb110,
+ 0x80e0b110,
+ 0x46a32200,
+ 0x42a322e6,
+ 0x1895b0e0,
+ 0x925f91b5,
+ 0x14f981a9,
+ 0x225080f0,
+ 0x224046e1,
+ 0x637646ae,
+ 0x6793cfa0,
+ 0xa052b063,
+ 0xc0f28280,
+ 0x10020420,
+ 0x3001c011,
+ 0x1801c010,
+ 0x31821802,
+ 0x26c10021,
+ 0x720e91e1,
+ 0xb01391e1,
+ 0xb063b003,
+ 0xb064b053,
+ 0x7100b054,
+ 0x22018041,
+ 0xb06346e1,
+ 0x80f0b064,
+ 0x42e12220,
+ 0x92118201,
+ 0x18918221,
+ 0xb03191b1,
+ 0x674e62c7,
+ 0x81a9a0e0,
+ 0x14598255,
+ 0x7100c080,
+ 0x6addb063,
+ 0xb0e6628b,
+ 0xa053a052,
+ 0x81b28251,
+ 0x3d823182,
+ 0x7000a003,
+ 0x39478287,
+ 0x82803987,
+ 0x06f03980,
+ 0xc0111002,
+ 0xc0103001,
+ 0x18021801,
+ 0x00213182,
+ 0x91d126c1,
+ 0xb012b002,
+ 0x39408280,
+ 0x100206f0,
+ 0x3001c011,
+ 0x1801c010,
+ 0x31821802,
+ 0x26c10021,
+ 0xb00391e1,
+ 0xb063b013,
+ 0x7100b053,
+ 0xb062a053,
+ 0x8041b052,
+ 0x46e12201,
+ 0x921481f4,
+ 0x82048225,
+ 0x4f201cb5,
+ 0x91b51895,
+ 0x224080f0,
+ 0x62ae4311,
+ 0x92148204,
+ 0x10408224,
+ 0x91b01890,
+ 0x1c751845,
+ 0x80f04f2d,
+ 0x43112240,
+ 0x913d62ae,
+ 0x913eb110,
+ 0x80e0b110,
+ 0x47372200,
+ 0x433722e6,
+ 0x91b5b0e0,
+ 0x81a9925f,
+ 0x80f014f9,
+ 0x463f2250,
+ 0x46ae2240,
+ 0x674e6355,
+ 0x81a9a0e0,
+ 0x14598255,
+ 0x7100c140,
+ 0x6b47b062,
+ 0x80a26311,
+ 0x61c86487,
+ 0x39428262,
+ 0x608706f2,
+ 0x7100b050,
+ 0x829061c8,
+ 0x22018041,
+ 0x81f446e1,
+ 0x82259214,
+ 0x91b51895,
+ 0x224180f1,
+ 0x6b5646ae,
+ 0x318181b1,
+ 0xdf903d81,
+ 0x67939341,
+ 0x22018041,
+ 0x81f446e1,
+ 0x82259214,
+ 0x4b411cc5,
+ 0x91b51895,
+ 0x224080f0,
+ 0x62ae4362,
+ 0x6793cf80,
+ 0x80418290,
+ 0x46e12201,
+ 0x92148204,
+ 0x18958225,
+ 0x80f191b5,
+ 0x46ae2241,
+ 0x80416b79,
+ 0x46e12201,
+ 0x92148204,
+ 0x1cc58225,
+ 0x18954ad7,
+ 0x80f091b5,
+ 0x43852240,
+ 0x933062ae,
+ 0x22008320,
+ 0xb3104794,
+ 0x00007000
+};
+
+PATCH_FUN_SPEC void rf_patch_rfe_tof(void)
+{
+#ifdef __PATCH_NO_UNROLLING
+ uint32_t i;
+ for (i = 0; i < 461; i++) {
+ HWREG(RFC_RFERAM_BASE + 4 * i) = patchTofRfe[i];
+ }
+#else
+ const uint32_t *pS = patchTofRfe;
+ volatile unsigned long *pD = &HWREG(RFC_RFERAM_BASE);
+ uint32_t t1, t2, t3, t4, t5, t6, t7, t8;
+ uint32_t nIterations = 57;
+
+ do {
+ t1 = *pS++;
+ t2 = *pS++;
+ t3 = *pS++;
+ t4 = *pS++;
+ t5 = *pS++;
+ t6 = *pS++;
+ t7 = *pS++;
+ t8 = *pS++;
+ *pD++ = t1;
+ *pD++ = t2;
+ *pD++ = t3;
+ *pD++ = t4;
+ *pD++ = t5;
+ *pD++ = t6;
+ *pD++ = t7;
+ *pD++ = t8;
+ } while (--nIterations);
+
+ t1 = *pS++;
+ t2 = *pS++;
+ t3 = *pS++;
+ t4 = *pS++;
+ t5 = *pS++;
+ *pD++ = t1;
+ *pD++ = t2;
+ *pD++ = t3;
+ *pD++ = t4;
+ *pD++ = t5;
+#endif
+}
+
+#endif
diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/startup_files/ccfg.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/startup_files/ccfg.c
new file mode 100644
index 0000000..00c0c9c
--- /dev/null
+++ b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/startup_files/ccfg.c
@@ -0,0 +1,532 @@
+/******************************************************************************
+* Filename: ccfg.c
+* Revised: $Date: 2017-11-02 11:36:28 +0100 (Thu, 02 Nov 2017) $
+* Revision: $Revision: 18030 $
+*
+* Description: Customer Configuration for:
+* CC13x2, CC13x4, CC26x2, CC26x4 device family (HW rev 2).
+*
+* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __CCFC_C__
+#define __CCFC_C__
+
+#include <stdint.h>
+#include "../inc/hw_types.h"
+#include "../inc/hw_ccfg.h"
+#include "../inc/hw_ccfg_simple_struct.h"
+
+//*****************************************************************************
+//
+// Introduction
+//
+// This file contains fields used by Boot ROM, startup code, and SW radio
+// stacks to configure chip behavior.
+//
+// Fields are documented in more details in hw_ccfg.h and CCFG.html in
+// DriverLib documentation (doc_overview.html -> CPU Domain Memory Map -> CCFG).
+//
+// PLEASE NOTE:
+// It is not recommended to do modifications inside the ccfg.c file.
+// This file is part of the CoreSDK release and future releases may have
+// important modifications and new fields added without notice.
+// The recommended method to modify the CCFG settings is to have a separate
+// <customer_ccfg>.c file that defines the specific CCFG values to be
+// overridden and then include the TI provided ccfg.c at the very end,
+// giving default values for non-overriden settings.
+//
+// Example:
+// #define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0xC5 // Enable ROM boot loader
+// #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x3 // LF RCOSC
+// //---- Use default values for all others ----
+// #include "<project-path>/source/ti/devices/<device>/startup_files/ccfg.c"
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Internal settings, forcing several bit-fields to be set to a specific value.
+//
+//*****************************************************************************
+
+//#####################################
+// Force VDDR high setting (Higher output power but also higher power consumption)
+// This is also called "boost mode"
+//#####################################
+
+#ifndef CCFG_FORCE_VDDR_HH
+#define CCFG_FORCE_VDDR_HH 0x0 // Use default VDDR trim
+// #define CCFG_FORCE_VDDR_HH 0x1 // Force VDDR voltage to the factory HH setting (FCFG1..VDDR_TRIM_HH)
+#endif
+
+//*****************************************************************************
+//
+// Set the values of the individual bit fields.
+//
+//*****************************************************************************
+
+//#####################################
+// Alternative DC/DC settings
+//#####################################
+
+#ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING
+#define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x0 // Alternative DC/DC setting enabled
+// #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x1 // Alternative DC/DC setting disabled
+#endif
+
+#if ( CCFG_FORCE_VDDR_HH )
+#define SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN 0xC // Special VMIN level (2.5V) when forced VDDR HH voltage
+#else
+#ifndef SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN
+#define SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN 0x8 // 2.25V
+#endif
+#endif
+
+#ifndef SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN
+#define SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x0 // Dithering disabled
+// #define SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x1 // Dithering enabled
+#endif
+
+#ifndef SET_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK
+#define SET_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK 0x0 // Peak current
+#endif
+
+//#####################################
+// XOSC override settings
+//#####################################
+
+#ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR
+// #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x0 // Enable override
+#define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x1 // Disable override
+#endif
+
+#ifndef SET_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT
+#define SET_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT 0x0 // Delta = 0
+#endif
+
+#ifndef SET_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET
+#define SET_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET 0x0 // Delta = 0
+#endif
+
+#ifndef SET_CCFG_MODE_CONF_1_XOSC_MAX_START
+#define SET_CCFG_MODE_CONF_1_XOSC_MAX_START 0x10 // 1600us
+#endif
+
+//#####################################
+// Power settings
+//#####################################
+
+#ifndef SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA
+#define SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA 0xF // Signed delta value +1 to apply to the VDDR_TRIM_SLEEP target (0xF=-1=default=no compensation)
+#endif
+
+#ifndef SET_CCFG_MODE_CONF_DCDC_RECHARGE
+#define SET_CCFG_MODE_CONF_DCDC_RECHARGE 0x0 // Use the DC/DC during recharge in powerdown
+// #define SET_CCFG_MODE_CONF_DCDC_RECHARGE 0x1 // Do not use the DC/DC during recharge in powerdown
+#endif
+
+#ifndef SET_CCFG_MODE_CONF_DCDC_ACTIVE
+#define SET_CCFG_MODE_CONF_DCDC_ACTIVE 0x0 // Use the DC/DC during active mode
+// #define SET_CCFG_MODE_CONF_DCDC_ACTIVE 0x1 // Do not use the DC/DC during active mode
+#endif
+
+#if ( CCFG_FORCE_VDDR_HH )
+#define SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x1 // Special setting to enable forced VDDR HH voltage
+#else
+#ifndef SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL
+// #define SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x0 // VDDS BOD level is 2.0V
+#define SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x1 // VDDS BOD level is 1.8V (or 1.65V for external regulator mode)
+#endif
+#endif
+
+#ifndef SET_CCFG_MODE_CONF_VDDR_CAP
+#define SET_CCFG_MODE_CONF_VDDR_CAP 0x3A // Unsigned 8-bit integer representing the min. decoupling capacitance on VDDR in units of 100nF
+#endif
+
+#ifndef SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC
+#define SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x1 // Temperature compensation on VDDR sleep trim disabled (default)
+// #define SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x0 // Temperature compensation on VDDR sleep trim enabled
+#endif
+
+//#####################################
+// Clock settings
+//#####################################
+
+#ifndef SET_CCFG_MODE_CONF_SCLK_LF_OPTION
+// #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x0 // LF clock derived from High Frequency XOSC
+// #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x1 // External LF clock
+#define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x2 // LF XOSC
+// #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x3 // LF RCOSC
+#endif
+
+#ifndef SET_CCFG_MODE_CONF_XOSC_CAP_MOD
+// #define SET_CCFG_MODE_CONF_XOSC_CAP_MOD 0x0 // Apply cap-array delta
+#define SET_CCFG_MODE_CONF_XOSC_CAP_MOD 0x1 // Don't apply cap-array delta
+#endif
+
+#ifndef SET_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA
+#define SET_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA 0xFF // Signed 8-bit value, directly modifying trimmed XOSC cap-array value
+#endif
+
+#ifndef SET_CCFG_EXT_LF_CLK_DIO
+#define SET_CCFG_EXT_LF_CLK_DIO 0x01 // DIO number if using external LF clock
+#endif
+
+#ifndef SET_CCFG_EXT_LF_CLK_RTC_INCREMENT
+#define SET_CCFG_EXT_LF_CLK_RTC_INCREMENT 0x800000 // RTC increment representing the external LF clock frequency
+#endif
+
+//#####################################
+// Special HF clock source setting
+//#####################################
+#ifndef SET_CCFG_MODE_CONF_XOSC_FREQ
+// #define SET_CCFG_MODE_CONF_XOSC_FREQ 0x1 // Use HPOSC as HF source (if executing on a HPOSC chip, otherwise using default (=0x3))
+#define SET_CCFG_MODE_CONF_XOSC_FREQ 0x2 // HF source is a 48 MHz xtal (default on x2/x4 chips)
+// #define SET_CCFG_MODE_CONF_XOSC_FREQ 0x3 // HF source is a 24 MHz xtal (default on x0 chips)
+#endif
+
+//#####################################
+// Bootloader settings
+//#####################################
+
+#ifndef SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE
+#define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0x00 // Disable ROM boot loader
+// #define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0xC5 // Enable ROM boot loader
+#endif
+
+#ifndef SET_CCFG_BL_CONFIG_BL_LEVEL
+// #define SET_CCFG_BL_CONFIG_BL_LEVEL 0x0 // Active low to open boot loader backdoor
+#define SET_CCFG_BL_CONFIG_BL_LEVEL 0x1 // Active high to open boot loader backdoor
+#endif
+
+#ifndef SET_CCFG_BL_CONFIG_BL_PIN_NUMBER
+#define SET_CCFG_BL_CONFIG_BL_PIN_NUMBER 0xFF // DIO number for boot loader backdoor
+#endif
+
+#ifndef SET_CCFG_BL_CONFIG_BL_ENABLE
+// #define SET_CCFG_BL_CONFIG_BL_ENABLE 0xC5 // Enabled boot loader backdoor
+#define SET_CCFG_BL_CONFIG_BL_ENABLE 0xFF // Disabled boot loader backdoor
+#endif
+
+//#####################################
+// Debug access settings
+//#####################################
+
+#ifndef SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE
+#define SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE 0x00 // Disable unlocking of TI FA option.
+// #define SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE 0xC5 // Enable unlocking of TI FA option with the unlock code
+#endif
+
+#ifndef SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE
+// #define SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE 0x00 // Access disabled
+#define SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG
+#endif
+
+#ifndef SET_CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE
+//#define SET_CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE 0x00 // Access disabled
+#define SET_CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG
+#endif
+
+#ifndef SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE
+#define SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE 0x00 // Access disabled
+//#define SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG
+#endif
+
+#ifndef SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE
+#define SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE 0x00 // Access disabled
+// #define SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG
+#endif
+
+#ifndef SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE
+#define SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE 0x00 // Access disabled
+// #define SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG
+#endif
+
+#ifndef SET_CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE
+#define SET_CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE 0x00 // Access disabled
+// #define SET_CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG
+#endif
+
+//#####################################
+// Alternative IEEE 802.15.4 MAC address
+//#####################################
+#ifndef SET_CCFG_IEEE_MAC_0
+#define SET_CCFG_IEEE_MAC_0 0xFFFFFFFF // Bits [31:0]
+#endif
+
+#ifndef SET_CCFG_IEEE_MAC_1
+#define SET_CCFG_IEEE_MAC_1 0xFFFFFFFF // Bits [63:32]
+#endif
+
+//#####################################
+// Alternative BLE address
+//#####################################
+#ifndef SET_CCFG_IEEE_BLE_0
+#define SET_CCFG_IEEE_BLE_0 0xFFFFFFFF // Bits [31:0]
+#endif
+
+#ifndef SET_CCFG_IEEE_BLE_1
+#define SET_CCFG_IEEE_BLE_1 0xFFFFFFFF // Bits [63:32]
+#endif
+
+//#####################################
+// Flash erase settings
+//#####################################
+
+#ifndef SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N
+// #define SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x0 // Any chip erase request detected during boot will be ignored
+#define SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x1 // Any chip erase request detected during boot will be performed by the boot FW
+#endif
+
+#ifndef SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N
+// #define SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x0 // Disable the boot loader bank erase function
+#define SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x1 // Enable the boot loader bank erase function
+#endif
+
+//#####################################
+// Flash image valid
+//#####################################
+#ifndef SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID
+#define SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID 0x00000000 // Flash image vector table is at address 0x00000000 (default)
+// #define SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID <valid_vector_table_addr> // Flash image vector table is at address <valid_vector_table_addr>
+// #define SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID <invalid_vector_table_addr> // Flash image vector table address is invalid. ROM boot loader is called.
+#endif
+
+//#####################################
+// Flash sector write protection
+//#####################################
+#ifndef SET_CCFG_CCFG_PROT_31_0
+#define SET_CCFG_CCFG_PROT_31_0 0xFFFFFFFF
+#endif
+
+#ifndef SET_CCFG_CCFG_PROT_63_32
+#define SET_CCFG_CCFG_PROT_63_32 0xFFFFFFFF
+#endif
+
+#ifndef SET_CCFG_CCFG_PROT_95_64
+#define SET_CCFG_CCFG_PROT_95_64 0xFFFFFFFF
+#endif
+
+#ifndef SET_CCFG_CCFG_PROT_127_96
+#define SET_CCFG_CCFG_PROT_127_96 0xFFFFFFFF
+#endif
+
+//#####################################
+// Select between cache or GPRAM
+//#####################################
+#ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM
+// #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x0 // Cache is disabled and GPRAM is available at 0x11000000-0x11001FFF
+#define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x1 // Cache is enabled and GPRAM is disabled (unavailable)
+#endif
+
+//#####################################
+// Select TCXO
+//#####################################
+#ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO
+#define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x1 // Disable TCXO
+// #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x0 // Enable TXCO
+#endif
+
+//*****************************************************************************
+//
+// CCFG values that should not be modified.
+//
+//*****************************************************************************
+#define SET_CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG 0x0058
+#define SET_CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS (CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M >> CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S)
+
+#if ( CCFG_FORCE_VDDR_HH )
+#define SET_CCFG_MODE_CONF_VDDR_EXT_LOAD 0x0 // Special setting to enable forced VDDR HH voltage
+#else
+#define SET_CCFG_MODE_CONF_VDDR_EXT_LOAD 0x1
+#endif
+
+#define SET_CCFG_MODE_CONF_RTC_COMP 0x1
+#define SET_CCFG_MODE_CONF_HF_COMP 0x1
+
+#define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP45 0xFF
+#define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP25 0xFF
+#define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP5 0xFF
+#define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TM15 0xFF
+
+#define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP125 0xFF
+#define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP105 0xFF
+#define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP85 0xFF
+#define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP65 0xFF
+
+#define SET_CCFG_RTC_OFFSET_RTC_COMP_P0 0xFFFF
+#define SET_CCFG_RTC_OFFSET_RTC_COMP_P1 0xFF
+#define SET_CCFG_RTC_OFFSET_RTC_COMP_P2 0xFF
+
+#define SET_CCFG_FREQ_OFFSET_HF_COMP_P0 0xFFFF
+#define SET_CCFG_FREQ_OFFSET_HF_COMP_P1 0xFF
+#define SET_CCFG_FREQ_OFFSET_HF_COMP_P2 0xFF
+
+//*****************************************************************************
+//
+// Concatenate bit fields to words.
+// DO NOT EDIT!
+//
+//*****************************************************************************
+#define DEFAULT_CCFG_EXT_LF_CLK ( \
+ ((((uint32_t)( SET_CCFG_EXT_LF_CLK_DIO )) << CCFG_EXT_LF_CLK_DIO_S ) | ~CCFG_EXT_LF_CLK_DIO_M ) & \
+ ((((uint32_t)( SET_CCFG_EXT_LF_CLK_RTC_INCREMENT )) << CCFG_EXT_LF_CLK_RTC_INCREMENT_S ) | ~CCFG_EXT_LF_CLK_RTC_INCREMENT_M ) )
+
+#define DEFAULT_CCFG_MODE_CONF_1 ( \
+ ((((uint32_t)( SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN )) << CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S ) | ~CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M ) & \
+ ((((uint32_t)( SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN )) << CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_S ) | ~CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_M ) & \
+ ((((uint32_t)( SET_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK )) << CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S ) | ~CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_M ) & \
+ ((((uint32_t)( SET_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT )) << CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S ) | ~CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_M ) & \
+ ((((uint32_t)( SET_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET )) << CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S ) | ~CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_M ) & \
+ ((((uint32_t)( SET_CCFG_MODE_CONF_1_XOSC_MAX_START )) << CCFG_MODE_CONF_1_XOSC_MAX_START_S ) | ~CCFG_MODE_CONF_1_XOSC_MAX_START_M ) )
+
+#define DEFAULT_CCFG_SIZE_AND_DIS_FLAGS ( \
+ ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG )) << CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_M ) & \
+ ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS )) << CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M ) & \
+ ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_M ) & \
+ ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M ) & \
+ ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_M ) & \
+ ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M ) )
+
+#define DEFAULT_CCFG_MODE_CONF ( \
+ ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA )) << CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S ) | ~CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_M ) & \
+ ((((uint32_t)( SET_CCFG_MODE_CONF_DCDC_RECHARGE )) << CCFG_MODE_CONF_DCDC_RECHARGE_S ) | ~CCFG_MODE_CONF_DCDC_RECHARGE_M ) & \
+ ((((uint32_t)( SET_CCFG_MODE_CONF_DCDC_ACTIVE )) << CCFG_MODE_CONF_DCDC_ACTIVE_S ) | ~CCFG_MODE_CONF_DCDC_ACTIVE_M ) & \
+ ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_EXT_LOAD )) << CCFG_MODE_CONF_VDDR_EXT_LOAD_S ) | ~CCFG_MODE_CONF_VDDR_EXT_LOAD_M ) & \
+ ((((uint32_t)( SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL )) << CCFG_MODE_CONF_VDDS_BOD_LEVEL_S ) | ~CCFG_MODE_CONF_VDDS_BOD_LEVEL_M ) & \
+ ((((uint32_t)( SET_CCFG_MODE_CONF_SCLK_LF_OPTION )) << CCFG_MODE_CONF_SCLK_LF_OPTION_S ) | ~CCFG_MODE_CONF_SCLK_LF_OPTION_M ) & \
+ ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC )) << CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_S ) | ~CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_M ) & \
+ ((((uint32_t)( SET_CCFG_MODE_CONF_RTC_COMP )) << CCFG_MODE_CONF_RTC_COMP_S ) | ~CCFG_MODE_CONF_RTC_COMP_M ) & \
+ ((((uint32_t)( SET_CCFG_MODE_CONF_XOSC_FREQ )) << CCFG_MODE_CONF_XOSC_FREQ_S ) | ~CCFG_MODE_CONF_XOSC_FREQ_M ) & \
+ ((((uint32_t)( SET_CCFG_MODE_CONF_XOSC_CAP_MOD )) << CCFG_MODE_CONF_XOSC_CAP_MOD_S ) | ~CCFG_MODE_CONF_XOSC_CAP_MOD_M ) & \
+ ((((uint32_t)( SET_CCFG_MODE_CONF_HF_COMP )) << CCFG_MODE_CONF_HF_COMP_S ) | ~CCFG_MODE_CONF_HF_COMP_M ) & \
+ ((((uint32_t)( SET_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA )) << CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S ) | ~CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M ) & \
+ ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_CAP )) << CCFG_MODE_CONF_VDDR_CAP_S ) | ~CCFG_MODE_CONF_VDDR_CAP_M ) )
+
+#define DEFAULT_CCFG_VOLT_LOAD_0 ( \
+ ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP45 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_M ) & \
+ ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP25 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_M ) & \
+ ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP5 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_M ) & \
+ ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TM15 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_M ) )
+
+#define DEFAULT_CCFG_VOLT_LOAD_1 ( \
+ ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP125 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_M ) & \
+ ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP105 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_M ) & \
+ ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP85 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_M ) & \
+ ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP65 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_M ) )
+
+#define DEFAULT_CCFG_RTC_OFFSET ( \
+ ((((uint32_t)( SET_CCFG_RTC_OFFSET_RTC_COMP_P0 )) << CCFG_RTC_OFFSET_RTC_COMP_P0_S ) | ~CCFG_RTC_OFFSET_RTC_COMP_P0_M ) & \
+ ((((uint32_t)( SET_CCFG_RTC_OFFSET_RTC_COMP_P1 )) << CCFG_RTC_OFFSET_RTC_COMP_P1_S ) | ~CCFG_RTC_OFFSET_RTC_COMP_P1_M ) & \
+ ((((uint32_t)( SET_CCFG_RTC_OFFSET_RTC_COMP_P2 )) << CCFG_RTC_OFFSET_RTC_COMP_P2_S ) | ~CCFG_RTC_OFFSET_RTC_COMP_P2_M ) )
+
+#define DEFAULT_CCFG_FREQ_OFFSET ( \
+ ((((uint32_t)( SET_CCFG_FREQ_OFFSET_HF_COMP_P0 )) << CCFG_FREQ_OFFSET_HF_COMP_P0_S ) | ~CCFG_FREQ_OFFSET_HF_COMP_P0_M ) & \
+ ((((uint32_t)( SET_CCFG_FREQ_OFFSET_HF_COMP_P1 )) << CCFG_FREQ_OFFSET_HF_COMP_P1_S ) | ~CCFG_FREQ_OFFSET_HF_COMP_P1_M ) & \
+ ((((uint32_t)( SET_CCFG_FREQ_OFFSET_HF_COMP_P2 )) << CCFG_FREQ_OFFSET_HF_COMP_P2_S ) | ~CCFG_FREQ_OFFSET_HF_COMP_P2_M ) )
+
+#define DEFAULT_CCFG_IEEE_MAC_0 SET_CCFG_IEEE_MAC_0
+#define DEFAULT_CCFG_IEEE_MAC_1 SET_CCFG_IEEE_MAC_1
+#define DEFAULT_CCFG_IEEE_BLE_0 SET_CCFG_IEEE_BLE_0
+#define DEFAULT_CCFG_IEEE_BLE_1 SET_CCFG_IEEE_BLE_1
+
+#define DEFAULT_CCFG_BL_CONFIG ( \
+ ((((uint32_t)( SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE )) << CCFG_BL_CONFIG_BOOTLOADER_ENABLE_S ) | ~CCFG_BL_CONFIG_BOOTLOADER_ENABLE_M ) & \
+ ((((uint32_t)( SET_CCFG_BL_CONFIG_BL_LEVEL )) << CCFG_BL_CONFIG_BL_LEVEL_S ) | ~CCFG_BL_CONFIG_BL_LEVEL_M ) & \
+ ((((uint32_t)( SET_CCFG_BL_CONFIG_BL_PIN_NUMBER )) << CCFG_BL_CONFIG_BL_PIN_NUMBER_S ) | ~CCFG_BL_CONFIG_BL_PIN_NUMBER_M ) & \
+ ((((uint32_t)( SET_CCFG_BL_CONFIG_BL_ENABLE )) << CCFG_BL_CONFIG_BL_ENABLE_S ) | ~CCFG_BL_CONFIG_BL_ENABLE_M ) )
+
+#define DEFAULT_CCFG_ERASE_CONF ( \
+ ((((uint32_t)( SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N )) << CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_S ) | ~CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_M ) & \
+ ((((uint32_t)( SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N )) << CCFG_ERASE_CONF_BANK_ERASE_DIS_N_S ) | ~CCFG_ERASE_CONF_BANK_ERASE_DIS_N_M ) )
+
+#define DEFAULT_CCFG_CCFG_TI_OPTIONS ( \
+ ((((uint32_t)( SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE )) << CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_S ) | ~CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_M ) )
+
+#define DEFAULT_CCFG_CCFG_TAP_DAP_0 ( \
+ ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE )) << CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_M ) & \
+ ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_M ) & \
+ ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_M ) )
+
+#define DEFAULT_CCFG_CCFG_TAP_DAP_1 ( \
+ ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_M ) & \
+ ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_M ) & \
+ ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE_M ) )
+
+#define DEFAULT_CCFG_IMAGE_VALID_CONF SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID
+
+#define DEFAULT_CCFG_CCFG_PROT_31_0 SET_CCFG_CCFG_PROT_31_0
+#define DEFAULT_CCFG_CCFG_PROT_63_32 SET_CCFG_CCFG_PROT_63_32
+#define DEFAULT_CCFG_CCFG_PROT_95_64 SET_CCFG_CCFG_PROT_95_64
+#define DEFAULT_CCFG_CCFG_PROT_127_96 SET_CCFG_CCFG_PROT_127_96
+
+//*****************************************************************************
+//
+// Customer Configuration Area in Lock Page
+//
+//*****************************************************************************
+#if defined(__IAR_SYSTEMS_ICC__)
+__root const ccfg_t __ccfg @ ".ccfg" =
+#elif defined(__TI_COMPILER_VERSION__)
+#pragma DATA_SECTION(__ccfg, ".ccfg")
+#pragma RETAIN(__ccfg)
+const ccfg_t __ccfg =
+#else
+const ccfg_t __ccfg __attribute__((section(".ccfg"))) __attribute__((used)) =
+#endif
+{ // Mapped to address
+ DEFAULT_CCFG_EXT_LF_CLK , // 0x50003FA8 (0x50003xxx maps to last
+ DEFAULT_CCFG_MODE_CONF_1 , // 0x50003FAC sector in FLASH.
+ DEFAULT_CCFG_SIZE_AND_DIS_FLAGS , // 0x50003FB0 Independent of FLASH size)
+ DEFAULT_CCFG_MODE_CONF , // 0x50003FB4
+ DEFAULT_CCFG_VOLT_LOAD_0 , // 0x50003FB8
+ DEFAULT_CCFG_VOLT_LOAD_1 , // 0x50003FBC
+ DEFAULT_CCFG_RTC_OFFSET , // 0x50003FC0
+ DEFAULT_CCFG_FREQ_OFFSET , // 0x50003FC4
+ DEFAULT_CCFG_IEEE_MAC_0 , // 0x50003FC8
+ DEFAULT_CCFG_IEEE_MAC_1 , // 0x50003FCC
+ DEFAULT_CCFG_IEEE_BLE_0 , // 0x50003FD0
+ DEFAULT_CCFG_IEEE_BLE_1 , // 0x50003FD4
+ DEFAULT_CCFG_BL_CONFIG , // 0x50003FD8
+ DEFAULT_CCFG_ERASE_CONF , // 0x50003FDC
+ DEFAULT_CCFG_CCFG_TI_OPTIONS , // 0x50003FE0
+ DEFAULT_CCFG_CCFG_TAP_DAP_0 , // 0x50003FE4
+ DEFAULT_CCFG_CCFG_TAP_DAP_1 , // 0x50003FE8
+ DEFAULT_CCFG_IMAGE_VALID_CONF , // 0x50003FEC
+ DEFAULT_CCFG_CCFG_PROT_31_0 , // 0x50003FF0
+ DEFAULT_CCFG_CCFG_PROT_63_32 , // 0x50003FF4
+ DEFAULT_CCFG_CCFG_PROT_95_64 , // 0x50003FF8
+ DEFAULT_CCFG_CCFG_PROT_127_96 , // 0x50003FFC
+};
+
+#endif // __CCFC_C__
