/*
 * Copyright (c) 2021, NXP
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <nxp/nxp_rt11xx.dtsi>

/ {
	cpus {
		/delete-node/ cpu@1;
	};
	/*
	 * ITCM & DTCM are available only to the M7 core. EDMA interrupts are connected
	 * to the M7 core alone, hence this EDMA controller has been designated M7 only.
	 * GPIO 6 is available to both M4 and M7 cores, however the GPIO interrupt is
	 * only accesssible to the M7.
	 *
	 * Refer to Chapter 3 of the Reference Manual
	 */
	soc {
		/delete-node/ dma-controller@40c14000;

		flexram: flexram@40028000 {
			reg = <0x40028000 0x4000>;
			interrupts = <50 0>;

			#address-cells = <1>;
			#size-cells = <1>;

			itcm: itcm@0 {
				compatible = "nxp,imx-itcm";
				reg = <0x00000000 DT_SIZE_K(256)>;
				zephyr,memory-region = "ITCM";
			};

			dtcm: dtcm@20000000 {
				compatible = "nxp,imx-dtcm";
				reg = <0x20000000 DT_SIZE_K(256)>;
				zephyr,memory-region = "DTCM";
			};
		};

		/*
		 * M7 uses different addresses from the M4 core for GPIO2 and
		 * GPIO3, see pg. 1460 of RT1170 ref manual for example
		 */
		gpio2: gpio@42008000 {
			compatible = "nxp,imx-gpio";
			reg = <0x42008000 0x4000>;
			interrupts = <102 0>, <103 0>;
			label = "GPIO_2";
			gpio-controller;
			#gpio-cells = <2>;
		};

		gpio3: gpio@4200c000 {
			compatible = "nxp,imx-gpio";
			reg = <0x4200c000 0x4000>;
			interrupts = <104 0>, <105 0>;
			label = "GPIO_3";
			gpio-controller;
			#gpio-cells = <2>;
		};

		sai1: sai@40404000 {
			dmas = <&edma0 0 54>, <&edma0 0 55>;
			dma-names = "rx", "tx";
			nxp,tx-dma-channel = <0>;
			nxp,rx-dma-channel = <1>;
		};

		sai2: sai@40408000 {
			dmas = <&edma0 0 56>, <&edma0 0 57>;
			dma-names = "rx", "tx";
			nxp,tx-dma-channel = <3>;
			nxp,rx-dma-channel = <4>;
		};

		sai3: sai@4040c000 {
			dmas = <&edma0 0 58>, <&edma0 0 59>;
			dma-names = "rx", "tx";
			nxp,tx-dma-channel = <5>;
			nxp,rx-dma-channel = <6>;
		};

		sai4: sai@40c40000 {
			dmas = <&edma0 0 60>, <&edma0 0 61>;
			dma-names = "rx", "tx";
			nxp,tx-dma-channel = <7>;
			nxp,rx-dma-channel = <8>;
		};
	};
};

&gpio6 {
	interrupts = <61 0>, <62 0>;
};

/* Set default power states for CM7 cpu */
&cpu0 {
	cpu-power-states = <&idle &suspend>;
};