/*
 * Copyright (c) 2022 Linaro Limited
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/* Clocks clean up config
 * Aim is to avoid conflict with specific default board configuration
 */

&clk_hse {
	status = "disabled";
	/delete-property/ hse-bypass;
	/delete-property/ clock-frequency;
	/delete-property/ hse-tcxo;
	/delete-property/ hse-div2;
};

&clk_hsi {
	status = "disabled";
	/delete-property/ hsi-div;
};

&clk_msi {
	status = "disabled";
	/delete-property/ msi-range;
};

&pll {
	/delete-property/ div-m;
	/delete-property/ mul-n;
	/delete-property/ div-p;
	/delete-property/ div-q;
	/delete-property/ div-r;
	/delete-property/ clocks;
	status = "disabled";
};

&rcc {
	/delete-property/ clocks;
	/delete-property/ clock-frequency;
};


/* Core set up
 * Aim of this part is to provide a base working clock config
 */

&clk_hse {
	status = "okay";
	clock-frequency = <DT_FREQ_M(32)>;
};

&clk_lsi1 {
	status = "okay";
};

&clk_hsi {
	status = "okay";
};

&rcc {
	clocks = <&clk_hse>;
	clock-frequency = <DT_FREQ_M(32)>;
	cpu1-prescaler = <1>;
	cpu2-prescaler = <1>;
	ahb4-prescaler = <1>;
	apb1-prescaler = <1>;
	apb2-prescaler = <1>;
};

&i2c1 {
	/delete-property/ clocks;
	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,
			<&rcc STM32_SRC_SYSCLK I2C1_SEL(1)>;
	status = "okay";
};

&adc1 {
	/* Basic test only. Don't configure domain clock. */
	status = "okay";
};