diff --git a/drivers/interrupt_controller/Kconfig b/drivers/interrupt_controller/Kconfig
index 4cb3fd4..ca6f61c 100644
--- a/drivers/interrupt_controller/Kconfig
+++ b/drivers/interrupt_controller/Kconfig
@@ -5,77 +5,6 @@
 
 menu "Interrupt Controllers"
 
-menuconfig LOAPIC
-	bool "LOAPIC"
-	depends on X86
-	help
-	  This option selects local APIC as the interrupt controller.
-
-if LOAPIC
-
-config LOAPIC_BASE_ADDRESS
-	hex "Local APIC Base Address"
-	default 0xFEE00000
-	help
-	  This option specifies the base address of the Local APIC device.
-
-config X2APIC
-	bool "Access local APIC in x2APIC mode"
-	help
-	  If your local APIC supports x2APIC mode, turn this on.
-
-config LOAPIC_SPURIOUS_VECTOR
-	bool "Handle LOAPIC spurious interrupts"
-	help
-	  A special situation may occur when a processor raises its task
-	  priority to be greater than or equal to the level of the
-	  interrupt for which the processor INTR signal is currently being
-	  asserted. If at the time the INTA cycle is issued, the
-	  interrupt that was to be dispensed has become masked (programmed
-	  by software), the local APIC will deliver a spurious-interrupt
-	  vector. Dispensing the spurious-interrupt vector does not affect
-	  the ISR, so the handler for this vector should return without an EOI.
-	  From x86 manual Volume 3 Section 10.9.
-
-config LOAPIC_SPURIOUS_VECTOR_ID
-	int "LOAPIC spurious vector ID"
-	default -1
-	depends on LOAPIC_SPURIOUS_VECTOR
-	help
-	  IDT vector to use for spurious LOAPIC interrupts. Note that some
-	  arches (P6, Pentium) ignore the low 4 bits and fix them at 0xF.
-	  If this value is left at -1 the last entry in the IDT will be used.
-
-config IOAPIC
-	bool "IO-APIC"
-	default y
-	help
-	  This option signifies that the target has an IO-APIC device. This
-	  capability allows IO-APIC-dependent code to be included.
-
-config IOAPIC_NUM_RTES
-	int "Number of Redirection Table Entries available"
-	default 24
-	depends on IOAPIC
-	help
-	  This option indicates the maximum number of Redirection Table Entries
-	  (RTEs) (one per IRQ available to the IO-APIC) made available to the
-	  kernel, regardless of the number provided by the hardware itself. For
-	  most efficient usage of memory, it should match the number of IRQ lines
-	  needed by devices connected to the IO-APIC.
-
-config IOAPIC_MASK_RTE
-	bool "Mask out RTE entries on boot"
-	default y
-	depends on IOAPIC
-	help
-	  At boot, mask all IOAPIC RTEs if they may be in an undefined state.
-	  You don't need this if the RTEs are either all guaranteed to be masked
-	  when the OS starts up, or a previous boot stage has done some IOAPIC
-	  configuration that needs to be preserved.
-
-endif # LOAPIC
-
 config ARCV2_INTERRUPT_UNIT
 	bool "ARCv2 Interrupt Unit"
 	default y
@@ -110,43 +39,6 @@
 	help
 	  IRQ implementation for LiteX VexRiscv
 
-config DW_ICTL
-	bool "Designware Interrupt Controller"
-	depends on MULTI_LEVEL_INTERRUPTS
-	help
-	  Designware Interrupt Controller can be used as a 2nd level interrupt
-	  controller which combines several sources of interrupt into one line
-	  that is then routed to the 1st level interrupt controller.
-
-config DW_ICTL_NAME
-	string "Name for Designware Interrupt Controller"
-	depends on DW_ICTL
-	default "DW_ICTL"
-	help
-	  Give a name for the instance of Designware Interrupt Controller
-
-config DW_ICTL_OFFSET
-	int "Parent interrupt number to which DW_ICTL maps"
-	default 0
-	depends on DW_ICTL
-	help
-	  Parent interrupt number to which DW_ICTL maps
-
-config DW_ISR_TBL_OFFSET
-	int "Offset in the SW ISR Table"
-	default 0
-	depends on DW_ICTL
-	help
-	  This indicates the offset in the SW_ISR_TABLE beginning from where
-	  the ISRs for Designware Interrupt Controller are assigned.
-
-config DW_ICTL_INIT_PRIORITY
-	int "Init priority for DW interrupt controller"
-	default 60
-	depends on DW_ICTL
-	help
-	  DesignWare Interrupt Controller initialization priority.
-
 config GIC
 	bool "ARM Generic Interrupt Controller (GIC)"
 	depends on CPU_CORTEX_R
@@ -154,10 +46,14 @@
 	  The ARM Generic Interrupt Controller works with Cortex-A and
 	  Cortex-R processors.
 
-source "drivers/interrupt_controller/Kconfig.stm32"
-
 source "drivers/interrupt_controller/Kconfig.multilevel"
 
+source "drivers/interrupt_controller/Kconfig.loapic"
+
+source "drivers/interrupt_controller/Kconfig.dw"
+
+source "drivers/interrupt_controller/Kconfig.stm32"
+
 source "drivers/interrupt_controller/Kconfig.s1000"
 
 source "drivers/interrupt_controller/Kconfig.rv32m1"
diff --git a/drivers/interrupt_controller/Kconfig.dw b/drivers/interrupt_controller/Kconfig.dw
new file mode 100644
index 0000000..34b9f7d
--- /dev/null
+++ b/drivers/interrupt_controller/Kconfig.dw
@@ -0,0 +1,39 @@
+# Copyright (c) 2019 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+menuconfig DW_ICTL
+	bool "Designware Interrupt Controller"
+	depends on MULTI_LEVEL_INTERRUPTS
+	help
+	  Designware Interrupt Controller can be used as a 2nd level interrupt
+	  controller which combines several sources of interrupt into one line
+	  that is then routed to the 1st level interrupt controller.
+
+if DW_ICTL
+
+config DW_ICTL_NAME
+	string "Name for Designware Interrupt Controller"
+	default "DW_ICTL"
+	help
+	  Give a name for the instance of Designware Interrupt Controller
+
+config DW_ICTL_OFFSET
+	int "Parent interrupt number to which DW_ICTL maps"
+	default 0
+	help
+	  Parent interrupt number to which DW_ICTL maps
+
+config DW_ISR_TBL_OFFSET
+	int "Offset in the SW ISR Table"
+	default 0
+	help
+	  This indicates the offset in the SW_ISR_TABLE beginning from where
+	  the ISRs for Designware Interrupt Controller are assigned.
+
+config DW_ICTL_INIT_PRIORITY
+	int "Init priority for DW interrupt controller"
+	default 60
+	help
+	  DesignWare Interrupt Controller initialization priority.
+
+endif # DW_ICTL
diff --git a/drivers/interrupt_controller/Kconfig.loapic b/drivers/interrupt_controller/Kconfig.loapic
new file mode 100644
index 0000000..251b6b0
--- /dev/null
+++ b/drivers/interrupt_controller/Kconfig.loapic
@@ -0,0 +1,73 @@
+# Copyright (c) 2019 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+menuconfig LOAPIC
+	bool "LOAPIC"
+	depends on X86
+	help
+	  This option selects local APIC as the interrupt controller.
+
+if LOAPIC
+
+config LOAPIC_BASE_ADDRESS
+	hex "Local APIC Base Address"
+	default 0xFEE00000
+	help
+	  This option specifies the base address of the Local APIC device.
+
+config X2APIC
+	bool "Access local APIC in x2APIC mode"
+	help
+	  If your local APIC supports x2APIC mode, turn this on.
+
+config LOAPIC_SPURIOUS_VECTOR
+	bool "Handle LOAPIC spurious interrupts"
+	help
+	  A special situation may occur when a processor raises its task
+	  priority to be greater than or equal to the level of the
+	  interrupt for which the processor INTR signal is currently being
+	  asserted. If at the time the INTA cycle is issued, the
+	  interrupt that was to be dispensed has become masked (programmed
+	  by software), the local APIC will deliver a spurious-interrupt
+	  vector. Dispensing the spurious-interrupt vector does not affect
+	  the ISR, so the handler for this vector should return without an EOI.
+	  From x86 manual Volume 3 Section 10.9.
+
+config LOAPIC_SPURIOUS_VECTOR_ID
+	int "LOAPIC spurious vector ID"
+	default -1
+	depends on LOAPIC_SPURIOUS_VECTOR
+	help
+	  IDT vector to use for spurious LOAPIC interrupts. Note that some
+	  arches (P6, Pentium) ignore the low 4 bits and fix them at 0xF.
+	  If this value is left at -1 the last entry in the IDT will be used.
+
+config IOAPIC
+	bool "IO-APIC"
+	default y
+	help
+	  This option signifies that the target has an IO-APIC device. This
+	  capability allows IO-APIC-dependent code to be included.
+
+config IOAPIC_NUM_RTES
+	int "Number of Redirection Table Entries available"
+	default 24
+	depends on IOAPIC
+	help
+	  This option indicates the maximum number of Redirection Table Entries
+	  (RTEs) (one per IRQ available to the IO-APIC) made available to the
+	  kernel, regardless of the number provided by the hardware itself. For
+	  most efficient usage of memory, it should match the number of IRQ lines
+	  needed by devices connected to the IO-APIC.
+
+config IOAPIC_MASK_RTE
+	bool "Mask out RTE entries on boot"
+	default y
+	depends on IOAPIC
+	help
+	  At boot, mask all IOAPIC RTEs if they may be in an undefined state.
+	  You don't need this if the RTEs are either all guaranteed to be masked
+	  when the OS starts up, or a previous boot stage has done some IOAPIC
+	  configuration that needs to be preserved.
+
+endif # LOAPIC