/*
 * Copyright (c) 2020 Thomas Stranger
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <st/g0/stm32g031.dtsi>

/ {
	soc {
		timers6: timers@40001000 {
			compatible = "st,stm32-timers";
			reg = <0x40001000 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
			interrupts = <17 0>;
			interrupt-names = "global";
			status = "disabled";
			label = "TIMERS_6";
		};

		timers7: timers@40001400 {
			compatible = "st,stm32-timers";
			reg = <0x40001400 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
			interrupts = <18 0>;
			interrupt-names = "global";
			status = "disabled";
			label = "TIMERS_7";
		};

		timers15: timers@40014000 {
			compatible = "st,stm32-timers";
			reg = <0x40014000 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
			interrupts = <20 0>;
			interrupt-names = "global";
			status = "disabled";
			label = "TIMERS_15";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				st,prescaler = <0>;
				label = "PWM_15";
				#pwm-cells = <3>;
			};
		};

		dac1: dac@40007400 {
			compatible = "st,stm32-dac";
			reg = <0x40007400 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
			status = "disabled";
			label = "DAC_1";
			#io-channel-cells = <1>;
		};

		dma1: dma@40020000 {
			interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>;
			dma-requests = <7>;
		};

		dmamux1: dmamux@40020800 {
			dma-channels = <7>;
		};
	};
};