# Intel CAVS SoC family configuration options
#
# Copyright (c) 2020 Intel Corporation
# SPDX-License-Identifier: Apache-2.0

config SOC_FAMILY_INTEL_ADSP
	select WINSTREAM
	select ARCH_SUPPORTS_COREDUMP
	select CPU_HAS_DCACHE
	select ARCH_HAS_USERSPACE if XTENSA_MMU
	select CPU_CACHE_INCOHERENT
	bool

if SOC_FAMILY_INTEL_ADSP

config SOC_FAMILY
	string
	default "intel_adsp"

# Select SoC Part No. and configuration options
source "soc/xtensa/intel_adsp/*/Kconfig.soc"

DT_COMPAT_INTEL_ADSP_HOST_IPC := intel,adsp-host-ipc
DT_COMPAT_INTEL_ADSP_IDC := intel,adsp-idc

config INTEL_ADSP_IPC
	bool "Driver for the host IPC interrupt delivery"
	default $(dt_compat_enabled,$(DT_COMPAT_INTEL_ADSP_HOST_IPC)) if !SOF
	default $(dt_compat_enabled,$(DT_COMPAT_INTEL_ADSP_IDC)) if !SOF
	help
	  Driver for the host IPC interrupt delivery mechanism.
	  Currently SOF has its own driver for this hardware.

config MEMORY_WIN_0_SIZE
	int "Size of memory window 0"
	default 8192
	help
	  Size of memory window 0.

	  This window is used for firmware status & outbox/uplink mbox.

config MEMORY_WIN_1_SIZE
	int "Size of memory window 1"
	default 8192
	help
	  Size of memory window 1.

	  This window is used for inbox/downlink mbox.

config MEMORY_WIN_2_SIZE
	int "Size of memory window 2"
	default 8192
	help
	  Size of memory window 2.

	  This window is used for debug.

config MEMORY_WIN_3_SIZE
	int "Size of memory window 3"
	default 8192
	help
	  Size of memory window 3.

	  This window is used for trace.

config ADSP_CLOCK
	bool
	help
	  Driver for the CAVS clocks. Allow type of clock (and
	  thus frequency) to be chosen.

config HP_SRAM_RESERVE
	int "Bytes to reserve at start of HP-SRAM"
	default 65536
	help
	  Bytes to reserve at the start of HP-SRAM.  Zephyr will not
	  place any symbols here, though the host windows have
	  addresses here.  The SOF application also makes direct use
	  of this region, so be very careful changing this value.

config ADSP_TRACE_SIMCALL
	bool "Emit SIMCALL output in addition to window tracing"
	help
	  When true, the trace_out layer will also use a SIMCALL
	  instruction to emit the passed data to the standard output
	  of an enclosing simulator process.  All window contents will
	  remain identical.

config ADSP_NEED_POWER_ON_CACHE
	bool
	help
	  Need to power cache SRAM banks on.

config ADSP_INIT_HPSRAM
	bool
	default y
	help
	  Need to init HP SRAM.

config ADSP_POWER_DOWN_HPSRAM
	bool
	default n if ZTEST
	default y
	help
	 Switch off HP SRAM during power down.

config ADSP_DISABLE_L2CACHE_AT_BOOT
	bool

config ADSP_IMR_CONTEXT_SAVE
	bool "Saves FW context into IMR before core is shut down"
	default n
	help
	  When true, FW will store its entire context into IMR before
	  entering D3 state. Later this context can be used to FW restore
	  when Host power up DSP again.

config XTENSA_CPU_IDLE_SPIN
	bool "Use busy loop for k_cpu_idle"
	help
	  Use a spin loop instead of WAITI for the CPU idle state.

config XTENSA_WAITI_BUG
	bool "Workaround sequence for WAITI bug on LX6"
	help
	  SOF traditionally contains this workaround on its ADSP
	  platforms which prefixes a WAITI entry with 128 NOP
	  instructions followed by an ISYNC and EXTW.

config ADSP_IDLE_CLOCK_GATING
	bool "DSP clock gating in Idle"
	help
	  When true, FW will run with enabled clock gating. This options change
	  HW configuration of a DSP. Evry time core goes to the WAITI state
	  (wait for interrupt) during idle, the clock can be gated (however, this
	  does not mean that this will happen).

endif # SOC_FAMILY_INTEL_ADSP