# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
# SPDX-License-Identifier: Apache-2.0

config SOC_NEORV32
	bool "NEORV32 Processor"
	select RISCV
	select RISCV_ISA_RV32I
	select RISCV_ISA_EXT_M
	select RISCV_ISA_EXT_A
	select RISCV_ISA_EXT_ZICSR
	select RISCV_ISA_EXT_ZIFENCEI
	select RISCV_PRIVILEGED
	help
	  Enable support for the NEORV32 Processor (SoC).

	  The NEORV32 CPU implementation must have the following RISC-V ISA
	  extensions enabled in order to support Zephyr:
	  - M (Integer Multiplication and Division)
	  - Zicsr (Control and Status Register (CSR) Instructions)

	  The following NEORV32 CPU ISA extensions are not currently supported
	  by Zephyr and can safely be disabled:
	  - A (Atomic Instructions)
	  - E (Embedded, only 16 integer registers)
	  - Zbb (Basic Bit Manipulation)
	  - Zfinx (Floating Point in Integer Registers)

if SOC_NEORV32

config SOC_NEORV32_V1_8_6
	bool "v1.8.6"
	# NEORV32 RISC-V ISA A extension implements only LR/SC, not AMO
	select ATOMIC_OPERATIONS_C

config SOC_NEORV32_VERSION
	hex
	default 0x01080600 if SOC_NEORV32_V1_8_6
	help
	  The targeted NEORV32 version as BCD-coded number. The format is
	  identical to that of the NEORV32 Machine implementation ID (mimpid)
	  register.

config SOC_NEORV32_ISA_C
	bool "RISC-V ISA Extension \"C\""
	select RISCV_ISA_EXT_C
	help
	  Enable this if the NEORV32 CPU implementation supports the RISC-V ISA
	  "C" extension (Compressed Instructions).

endif # SOC_NEORV32