# Nordic Semiconductor nRF53 MCU line

# Copyright (c) 2019 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0

if SOC_SERIES_NRF53X
config SOC_NRF5340_CPUAPP
	bool
	select CPU_HAS_NRF_IDAU
	select CPU_HAS_FPU
	select ARMV8_M_DSP
	select HAS_POWEROFF
	select SOC_COMPATIBLE_NRF5340_CPUAPP
	imply SOC_NRF53_RTC_PRETICK
	imply SOC_NRF53_ANOMALY_168_WORKAROUND

config SOC_NRF5340_CPUNET
	bool
	select SOC_COMPATIBLE_NRF5340_CPUNET
	imply SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED
	imply SOC_NRF53_RTC_PRETICK if !WDT_NRFX
	imply SOC_NRF53_ANOMALY_168_WORKAROUND

choice
	prompt "nRF53x MCU Selection"

config SOC_NRF5340_CPUAPP_QKAA
	bool "NRF5340_CPUAPP_QKAA"
	select SOC_NRF5340_CPUAPP

config SOC_NRF5340_CPUNET_QKAA
	bool "NRF5340_CPUNET_QKAA"
	select SOC_NRF5340_CPUNET

endchoice

config SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED
	bool "Workaround for nRF5340 anomaly 160"
	imply SOC_NRF53_ANOMALY_160_WORKAROUND
	help
	  Indicates that the workaround for the anomaly 160 that affects
	  the nRF5340 SoC should be applied.
	  This option is enabled by default for the Application MCU when
	  DC/DC mode is enabled for the VREGMAIN or VREGRADIO regulator
	  and always for the Network MCU.
	  If this option is enabled, but the workaround cannot be applied,
	  because the system clock is disabled, a related cmake warning is
	  issued.

config SOC_NRF53_ANOMALY_160_WORKAROUND
	bool
	depends on SYS_CLOCK_EXISTS
	select ARM_ON_ENTER_CPU_IDLE_HOOK

config SOC_NRF53_RTC_PRETICK
	bool "Pre-tick workaround for nRF5340 anomaly 165"
	depends on (SYS_CLOCK_EXISTS && SOC_NRF5340_CPUNET) || SOC_NRF5340_CPUAPP
	select NRFX_DPPI
	select ARM_ON_ENTER_CPU_IDLE_HOOK if SOC_NRF5340_CPUNET
	select ARM_ON_ENTER_CPU_IDLE_PREPARE_HOOK if SOC_NRF5340_CPUNET
	help
	  Indicates that the pre-tick workaround for the anomaly 165 that affects
	  the nRF5340 SoC should be applied. The workaround applies to wake ups caused
	  by EVENTS_COMPARE and EVENTS_OVRFLW on RTC0 and RTC1 for which interrupts are
	  enabled through INTENSET register. The case when these events are generated
	  by EVTEN but without interrupts enabled through INTENSET is not handled.
	  The EVENTS_TICK event is not handled.

if SOC_NRF53_RTC_PRETICK

config SOC_NRF53_RTC_PRETICK_IPC_CH_FROM_NET
	int "IPC 0 channel for RTC pretick"
	range 0 15
	default 10

config SOC_NRF53_RTC_PRETICK_IPC_CH_TO_NET
	int "IPC 1 channel for RTC pretick"
	range 0 15
	default 11

endif

config SOC_NRF53_ANOMALY_168_WORKAROUND
	bool "Workaround for nRF5340 anomaly 168"
	select ARM_ON_EXIT_CPU_IDLE
	help
	  Indicates that the workaround for the anomaly 168 that affects
	  the nRF5340 SoC should be applied.
	  The workaround involves execution of 8 NOP instructions when the CPU
	  exist its idle state (when the WFI/WFE instruction returns) and it is
	  enabled by default for both the application and network core.

config SOC_NRF53_ANOMALY_168_WORKAROUND_FOR_EXECUTION_FROM_RAM
	bool "Extend the workaround to execution at 128 MHz from RAM"
	depends on SOC_NRF53_ANOMALY_168_WORKAROUND && SOC_NRF5340_CPUAPP
	help
	  Indicates that the anomaly 168 workaround is to be extended to cover
	  also a specific case when the WFI/WFE instruction is executed at 128
	  MHz from RAM. Then, 26 instead of 8 NOP instructions needs to be
	  executed after WFI/WFE. This extension is not enabled by default.

if SOC_NRF5340_CPUAPP

config SOC_DCDC_NRF53X_APP
	bool
	imply SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED
	help
	  Enable nRF53 series System on Chip Application MCU DC/DC converter.

config SOC_DCDC_NRF53X_NET
	bool
	imply SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED
	help
	  Enable nRF53 series System on Chip Network MCU DC/DC converter.

config SOC_DCDC_NRF53X_HV
	bool
	help
	  Enable nRF53 series System on Chip High Voltage DC/DC converter.

config NRF_SPU_FLASH_REGION_SIZE
	hex
	default 0x4000
	help
	  FLASH region size for the NRF_SPU peripheral

config NRF_SPU_RAM_REGION_SIZE
	hex
	default 0x2000
	help
	  RAM region size for the NRF_SPU peripheral

config SOC_NRF_GPIO_FORWARDER_FOR_NRF5340
	bool
	depends on NRF_SOC_SECURE_SUPPORTED
	help
	  hidden option for including the nRF GPIO pin forwarding

if !TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM

config SOC_ENABLE_LFXO
	bool "LFXO"
	default y
	help
	  Enable the low-frequency oscillator (LFXO) functionality on XL1 and
	  XL2 pins.
	  This option must be enabled if either application or network core is
	  to use the LFXO. Otherwise, XL1 and XL2 pins will behave as regular
	  GPIOs.

choice SOC_LFXO_LOAD_CAPACITANCE
	prompt "LFXO load capacitance"
	depends on SOC_ENABLE_LFXO
	default SOC_LFXO_CAP_INT_7PF

config SOC_LFXO_CAP_EXTERNAL
	bool "Use external load capacitors"

config SOC_LFXO_CAP_INT_6PF
	bool "6 pF internal load capacitance"

config SOC_LFXO_CAP_INT_7PF
	bool "7 pF internal load capacitance"

config SOC_LFXO_CAP_INT_9PF
	bool "9 pF internal load capacitance"

endchoice

choice SOC_HFXO_LOAD_CAPACITANCE
	prompt "HFXO load capacitance"
	default SOC_HFXO_CAP_DEFAULT

config SOC_HFXO_CAP_DEFAULT
	bool "SoC default"
	help
	  When this option is used, the SoC initialization routine does not
	  touch the XOSC32MCAPS register value, so the default setting for
	  the SoC is in effect. Please note that this may not necessarily be
	  the reset value (0) for the register, as the register can be set
	  during the device trimming in the SystemInit() function.

config SOC_HFXO_CAP_EXTERNAL
	bool "Use external load capacitors"

config SOC_HFXO_CAP_INTERNAL
	bool "Use internal load capacitors"
	depends on NRF_SOC_SECURE_SUPPORTED

endchoice

config SOC_HFXO_CAP_INT_VALUE_X2
	int "Doubled value of HFXO internal load capacitors (in pF)"
	depends on SOC_HFXO_CAP_INTERNAL
	range 14 40
	help
	  Internal capacitors ranging from 7.0 pF to 20.0 pF in 0.5 pF steps
	  can be enabled on pins XC1 and XC2. This option specifies doubled
	  capacitance value for the two capacitors. Set it to 14 to get 7.0 pF
	  for each capacitor, 15 to get 7.5 pF, and so on.

endif # !TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM

endif # SOC_NRF5340_CPUAPP


config NRF_ENABLE_CACHE
	bool "Cache"
	depends on (SOC_NRF5340_CPUAPP && (!TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM)) \
			|| SOC_NRF5340_CPUNET
	default y
	help
	  Instruction and Data cache is available on nRF5340 CPUAPP
	  (Application MCU). It may only be accessed by Secure code.

	  Instruction cache only (I-Cache) is available in nRF5340
	  CPUNET (Network MCU).

config BUILD_WITH_TFM
	# TF-M nRF53 platform enables the cache unconditionally.
	select NRF_ENABLE_CACHE if SOC_NRF5340_CPUAPP

rsource "Kconfig.sync_rtc"

endif # SOC_SERIES_NRF53X