/*
 * Copyright (c) 2023 Graphcore Ltd, All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/* Set div-q to get test clk freq into acceptable SPI freq range */
&pll {
	/delete-property/ div-q;
	div-q = <8>;
};

&sram2 {
	zephyr,memory-attr = < DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) >;
};

&spi1 {
	dmas = <&dmamux1 0 38 (STM32_DMA_PERIPH_TX | STM32_DMA_PRIORITY_HIGH | STM32_DMA_MEM_16BITS | STM32_DMA_PERIPH_16BITS)
		&dmamux1 1 37 (STM32_DMA_PERIPH_RX | STM32_DMA_PRIORITY_HIGH | STM32_DMA_MEM_16BITS | STM32_DMA_PERIPH_16BITS)>;
	dma-names = "tx", "rx";
	slow@0 {
		compatible = "test-spi-loopback-slow";
		reg = <0>;
		spi-max-frequency = <500000>;
	};
	fast@0 {
		compatible = "test-spi-loopback-fast";
		reg = <0>;
		spi-max-frequency = <16000000>;
	};
};

&dma1 {
	status = "okay";
};

&dma2 {
	status = "okay";
};

&dmamux1 {
	status = "okay";
};