/*
 * Copyright (c) 2019, NXP
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/* SoC level DTS fixup file */

#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V8M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS

#define DT_USART_MCUX_LPC_0_BASE_ADDRESS DT_NXP_LPC_USART_50086000_BASE_ADDRESS
#define DT_USART_MCUX_LPC_0_BAUD_RATE   DT_NXP_LPC_USART_50086000_CURRENT_SPEED
#define DT_USART_MCUX_LPC_0_IRQ     DT_NXP_LPC_USART_50086000_IRQ_0
#define DT_USART_MCUX_LPC_0_IRQ_PRI DT_NXP_LPC_USART_50086000_IRQ_0_PRIORITY
#define DT_USART_MCUX_LPC_0_NAME    DT_NXP_LPC_USART_50086000_LABEL

/* End of SoC Level DTS fixup file */