/*
 * Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/*
 * Derived from DTS extracted with:
 *
 *   qemu-system-aarch64 -machine virt -cpu cortex-a53 -nographic
 *         -machine dumpdtb=virt.dtb
 *
 *   dtc -I dtb -O dts virt.dtb
 */

#include <mem.h>
#include <arm/armv8-a.dtsi>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0>;
		};
	};

	soc {
		interrupt-parent = <&gic>;

		gic: interrupt-controller@8000000 {
			compatible = "arm,gic";
			reg = <0x8000000 0x10000>,
			      <0x8010000 0x10000>;
			interrupt-controller;
			#interrupt-cells = <4>;
			label = "GIC";
			status = "okay";
		};

		uart0: uart@9000000 {
			compatible = "arm,pl011";
			reg = <0x9000000 0x1000>;
			status = "disabled";
			interrupts = <GIC_SPI 1 0 IRQ_TYPE_LEVEL>;
			interrupt-names = "irq_0";
			label = "UART_0";
		};

		sharedirq0: sharedirq0 {
			compatible = "shared-irq";
			label = "SHARED_IRQ";
			interrupts = <GIC_SPI 1 0 IRQ_TYPE_LEVEL>;
			interrupt-controller;
			#interrupt-cells = <0>;
			status = "okay";
		};

		flash0: flash@0 {
			compatible = "soc-nv-flash";
			reg = <0x0 DT_SIZE_K(64)>;
		};

		arch_timer: timer {
			compatible = "arm,arm-timer";
			interrupts = <GIC_PPI 13 IRQ_DEFAULT_PRIORITY
					IRQ_TYPE_EDGE>,
				     <GIC_PPI 14 IRQ_DEFAULT_PRIORITY
					IRQ_TYPE_EDGE>,
				     <GIC_PPI 11 IRQ_DEFAULT_PRIORITY
					IRQ_TYPE_EDGE>,
				     <GIC_PPI 10 IRQ_DEFAULT_PRIORITY
					IRQ_TYPE_EDGE>;
			label = "arch_timer";
		};
	};
};