/*
 * Copyright (c) 2019 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <xtensa/xtensa.dtsi>
#include <dt-bindings/i2c/i2c.h>
#include <mem.h>

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "cadence,tensilica-xtensa-lx4";
			reg = <0>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "cadence,tensilica-xtensa-lx4";
			reg = <1>;
		};
	};

	sram0: memory@be000000 {
		device_type = "memory";
		compatible = "mmio-sram";
		reg = <0xbe000000 DT_SIZE_K(512)>;
	};

	sram1: memory@be800000 {
		device_type = "memory";
		compatible = "mmio-sram";
		reg = <0xbe800000 DT_SIZE_K(128)>;
	};

	soc {
		core_intc: core_intc@0 {
			compatible = "xtensa,core-intc";
			reg = <0x00 0x400>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};

		cavs0: cavs@1600  {
			compatible = "intel,cavs-intc";
			reg = <0x1600 0x10>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <6 0 0>;
			interrupt-parent = <&core_intc>;
			label = "CAVS_0";
		};

		cavs1: cavs@1610  {
			compatible = "intel,cavs-intc";
			reg = <0x1610 0x10>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <0xA 0 0>;
			interrupt-parent = <&core_intc>;
			label = "CAVS_1";
		};

		cavs2: cavs@1620  {
			compatible = "intel,cavs-intc";
			reg = <0x1620 0x10>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <0XD 0 0>;
			interrupt-parent = <&core_intc>;
			label = "CAVS_2";
		};

		cavs3: cavs@1630  {
			compatible = "intel,cavs-intc";
			reg = <0x1630 0x10>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <0x10 0 0>;
			interrupt-parent = <&core_intc>;
			label = "CAVS_3";
		};

		idc: idc@1200 {
			compatible = "intel,cavs-idc";
			label = "CAVS_IDC";
			reg = <0x1200 0x80>;
			interrupts = <8 0 0>;
			interrupt-parent = <&cavs0>;
		};
	};
};