# i.MX RT5XX Series

# Copyright 2022-2023, NXP
# SPDX-License-Identifier: Apache-2.0

choice
	prompt "i.MX RT5XX Series MCU Selection"
	depends on SOC_SERIES_IMX_RT5XX

config SOC_MIMXRT595S_CM33
	bool "SOC_MIMXRT595S M33"
	select CPU_HAS_ARM_SAU
	select CPU_HAS_ARM_MPU
	select CPU_HAS_FPU
	select PLATFORM_SPECIFIC_INIT
	select ARMV8_M_DSP
	select ARM_TRUSTZONE_M
	select CPU_CORTEX_M_HAS_SYSTICK
	select HAS_MCUX
	select HAS_MCUX_SYSCON
	select HAS_MCUX_FLEXCOMM
	select HAS_MCUX_FLEXSPI
	select HAS_MCUX_CACHE
	select HAS_MCUX_LPC_DMA
	select HAS_MCUX_LPADC
	select HAS_MCUX_OS_TIMER
	select HAS_MCUX_LPC_RTC
	select HAS_MCUX_TRNG
	select HAS_MCUX_SCTIMER
	select HAS_MCUX_USDHC1
	select HAS_MCUX_USDHC2
	select HAS_MCUX_USB_LPCIP3511
	select HAS_MCUX_CTIMER
endchoice

if SOC_SERIES_IMX_RT5XX

config SOC_PART_NUMBER_MIMXRT533SFFOC
	bool

config SOC_PART_NUMBER_MIMXRT555SFFOC
	bool

config SOC_PART_NUMBER_MIMXRT595SFFOC
	bool

config SOC_PART_NUMBER_MIMXRT533SFAWC
	bool

config SOC_PART_NUMBER_MIMXRT555SFAWC
	bool

config SOC_PART_NUMBER_MIMXRT595SFAWC
	bool

config SOC_PART_NUMBER_IMX_RT5XX
	string
	default "MIMXRT533SFAWC" if SOC_PART_NUMBER_MIMXRT533SFAWC
	default "MIMXRT555SFAWC" if SOC_PART_NUMBER_MIMXRT555SFAWC
	default "MIMXRT595SFAWC" if SOC_PART_NUMBER_MIMXRT595SFAWC
	default "MIMXRT533SFFOC" if SOC_PART_NUMBER_MIMXRT533SFFOC
	default "MIMXRT555SFFOC" if SOC_PART_NUMBER_MIMXRT555SFFOC
	default "MIMXRT595SFFOC" if SOC_PART_NUMBER_MIMXRT595SFFOC

	help
	  This string holds the full part number of the SoC. It is a hidden
	  option that you should not set directly. The part number selection
	  choice defines the default value for this string.

menuconfig NXP_IMX_RT5XX_BOOT_HEADER
	bool "The boot header"
	depends on !BOOTLOADER_MCUBOOT
	help
	  Enable data structures required by the boot ROM to boot the
	  application from an external flash device.

if NXP_IMX_RT5XX_BOOT_HEADER

choice BOOT_DEVICE
	prompt "Boot device selection"
	default BOOT_FLEXSPI_NOR

config BOOT_FLEXSPI_NOR
	bool "FlexSPI serial NOR"

endchoice

config FLASH_CONFIG_OFFSET
	hex "Flash config data offset"
	default 0x400
	help
	  The flash config offset provides the boot ROM with the on-board
	  flash type and parameters. The boot ROM requires a fixed flash config
	  offset for FlexSPI device.

config IMAGE_VECTOR_TABLE_OFFSET
	hex "Image vector table offset"
	default 0x1000
	help
	  The Image Vector Table (IVT) provides the boot ROM with pointers to
	  the application entry point and device configuration data. The boot
	  ROM requires a fixed IVT offset for each type of boot device.

config NXP_IMX_RT_ROM_RAMLOADER
	depends on !FLASH_MCUX_FLEXSPI_XIP
	# Required so that debugger will load image to correct offset
	select BUILD_OUTPUT_HEX
	bool "Create output image that IMX RT ROM can load from FlexSPI to ram"
	help
	  Builds an output image that the IMX RT BootROM can load from the
	  FlexSPI boot device into RAM region. The image will be loaded
	  from FLEXSPI0 into the region specified by `zephyr,flash` node.

# Setup LMA adjustment if using the RAMLOADER feature of ROM
FLASH_CHOSEN := zephyr,flash
FLASH_BASE := $(dt_chosen_reg_addr_hex,$(FLASH_CHOSEN))
FLEXSPI_BASE := $(dt_node_reg_addr_hex,/soc/spi@134000,1)
config BUILD_OUTPUT_ADJUST_LMA
	default "$(FLEXSPI_BASE) - $(FLASH_BASE)" if NXP_IMX_RT_ROM_RAMLOADER

endif # NXP_IMX_RT5XX_BOOT_HEADER


config IMXRT5XX_CODE_CACHE
	bool "Code cache"
	default y
	help
	  Enable code cache for FlexSPI region at boot. If this Kconfig is
	  cleared, the CACHE64 controller will be disabled during SOC init

choice FLEXCOMM0_CLK_SRC
	prompt "Clock source for Flexcomm0"
	default FLEXCOMM0_CLK_SRC_FRG

config FLEXCOMM0_CLK_SRC_FRG
	bool "FRG is source of Flexcomm0 clock"

config FLEXCOMM0_CLK_SRC_FRO
	bool "FRO_DIV4 is source of Flexcomm0 clock"

endchoice

choice MIPI_DPHY_CLK_SRC
	prompt "Clock source for MIPI DPHY"
	default MIPI_DPHY_CLK_SRC_AUX1_PLL

config MIPI_DPHY_CLK_SRC_AUX1_PLL
	bool "AUX1_PLL is source of MIPI_DPHY clock"

config MIPI_DPHY_CLK_SRC_FRO
	bool "FRO 192/96M is source of MIPI_DPHY clock"

endchoice

endif # SOC_SERIES_IMX_RT5XX