# Copyright (c) 2023, STMicroelectronics
# SPDX-License-Identifier: Apache-2.0

description: |
  STM32 Reset and Clock controller node.
  This node is in charge of system clock ('SYSCLK') source selection and controlling
  clocks for AHB (Advanced High Performance) and APB (Advanced Peripheral) bus domains.

  Configuring STM32 Reset and Clock controller node:

  System clock source should be selected amongst the clock nodes available in "clocks"
  node (typically 'clk_hse, clk_hsi', 'pll').
  Core clock frequency should also be defined, using "clock-frequency" property.
  Note:
          Core clock frequency  = SYSCLK / AHB prescaler
  Last, peripheral bus clocks (typically PCLK1, PCLK2, PCLK7) should be configured using
  matching prescaler properties.
  Here is an example of correctly configured rcc node:
  &rcc {
           clocks = <&pll>;                   /* Select pll as SYSCLK source */
           ahb-prescaler = <2>;
           clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
           apb1-presacler = <1>;
           apb2-presacler = <1>;
           apb7-presacler = <7>;
  }

  Specifying a gated clock:

  To specify a gated clock, a peripheral should define a "clocks" property encoded
  in the following way:
  ... {
           ...
           clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
           ...
  }
  After the phandle referring to rcc node, the first index specifies the registers of
  the bus controlling the peripheral and the second index specifies the bit used to
  control the peripheral clock in that bus register.

  Specifying an alternate clock source:

  Specifying an alternate source clock could be done by adding a clock specifier to the
  clock property:
  ... {
           ...
           clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>,
                        <&rcc STM32_SRC_HSI I2C1_SEL(2)>;
           ...
  }
  In this example I2C1 device is assigned HSI as clock source.
  It is device driver's responsibility to query and use clock source information in
  accordance with clock_control API specifications.

compatible: "st,stm32wba-rcc"

include: [clock-controller.yaml, base.yaml]

properties:
  reg:
    required: true

  "#clock-cells":
    const: 2

  clock-frequency:
    required: true
    type: int
    description: |
      default frequency in Hz for clock output (HCLK1)

  ahb-prescaler:
    type: int
    required: true
    enum:
      - 1
      - 2
      - 4
      - 8
      - 16
    description: |
        Common AHB1, AHB2, AHB4 prescaler. Defines actual core clock frequency
        (HCLK) based on system frequency input. AKA HPRE.
        The HCLK clocks CPU, AHB1, AHB2, memories and DMA.

  ahb5-prescaler:
    type: int
    enum:
      - 1
      - 2
      - 3
      - 4
      - 6
    description: |
        AHB5 prescaler. Defines actual core clock frequency (HCLK5) based on
        system frequency input. It is used to limit HCLK5 below 32MHz.
        Only required when SysClock source is PLL1.
        AKA HPRE5.

  apb1-prescaler:
    type: int
    required: true
    enum:
      - 1
      - 2
      - 4
      - 8
      - 16

  apb2-prescaler:
    type: int
    required: true
    enum:
      - 1
      - 2
      - 4
      - 8
      - 16

  apb7-prescaler:
    type: int
    required: true
    enum:
      - 1
      - 2
      - 4
      - 8
      - 16

  ahb5-div:
    type: boolean
    description: |
      AHB5 divider. Applies only when SysClock source is HSI16 or HSE32.
      When enabled, AHB5 clock is SysClock / 2.
      When disabled, SysClock is not divided.

clock-cells:
  - bus
  - bits