/*
 * Copyright (c) 2020 Teslabs Engineering S.L.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <st/h7/stm32h7.dtsi>

/ {
	soc {
		dmamux1: dmamux@40020800 {
			dma-requests= <107>;
		};
	};

	/* System data RAM accessible over AXI bus: AXI SRAM in D1 domain */
	sram0: memory@24000000 {
		reg = <0x24000000 DT_SIZE_K(512)>;
		compatible = "mmio-sram";
	};

	/* System data RAM accessible over AHB bus: SRAM1 in D2 domain */
	sram1: memory@30000000 {
		reg = <0x30000000 DT_SIZE_K(128)>;
		compatible = "mmio-sram";
	};

	/* System data RAM accessible over AHB bus: SRAM2 in D2 domain */
	sram2: memory@30020000 {
		compatible = "mmio-sram";
		reg = <0x30020000 DT_SIZE_K(128)>;
	};

	/* System data RAM accessible over AHB bus: SRAM3 in D2 domain */
	sram3: memory@30040000 {
		compatible = "mmio-sram";
		reg = <0x30040000 DT_SIZE_K(32)>;
	};

	/* System data RAM accessible over AHB bus: SRAM4 in D3 domain  */
	sram4: memory@38000000 {
		reg = <0x38000000 DT_SIZE_K(64)>;
		compatible = "mmio-sram";
	};

	dtcm: memory@20000000 {
		compatible = "arm,dtcm";
		reg = <0x20000000 DT_SIZE_K(128)>;
	};
};