/*
 * Copyright (c) 2021 Nuvoton Technology Corporation.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <arm/armv7-m.dtsi>

/* Macros for device tree declarations of npcx soc family */
#include <dt-bindings/clock/npcx_clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/pinctrl/npcx-pinctrl.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/sensor/npcx_tach.h>
#include <freq.h>

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-m4f";
			reg = <0>;
		};
	};

	def-io-conf-list {
		compatible = "nuvoton,npcx-pinctrl-def";
		/* Change default functional pads to GPIOs
		 * no_spip - PIN95.97.A1.A3
		 * no_fpip - PIN96.A0.A2.A4 - Internal flash only
		 * no_pwrgd - PIN72
		 * no_lpc_espi - PIN46.47.51.52.53.54.55.57
		 * no_peci_en - PIN81
		 * npsl_in1_sl - PIND2
		 * npsl_in2_sl - PIN00
		 * no_ksi0-7 - PIN31.30.27.26.25.24.23.22
		 * no_ks000-17 - PIN21.20.17.16.15.14.13.12.11.10.07.06.05.04.
		 *                  82.83.03.B1
		 */
		pinctrl-0 = <>;
	};

	def-lvol-io-list {
		compatible = "nuvoton,npcx-lvolctrl-def";
		/* Put low-voltage io pads into "lvol-io-pads" property if the
		 * detection level of them is 1.8V, For example, if the bus
		 * voltage of i2c1_0 port is 1.8V, this property should be:
		 * lvol-io-pads = <&lvol_io90 &lvol_io87>;
		 */
		lvol-io-pads = <>;
	};

	vsby-psl-in-list {
		compatible = "nuvoton,npcx-pslctrl-def";
		/* Put Power Switch Logic (PSL) input pads which detect the
		 * wake-up events and turn on core power supply (VCC1) from
		 * standby power state (ultra-low-power mode) into "psl-in-pads"
		 * property. For example, if PSL input 1 that is plan to detect
		 * a 'falling edge' event, this property should be:
		 *   psl-in-pads = <&psl_in1>;
		 * And the flag property in psl_in1 should change to
		 *   flag = <NPCX_PSL_FALLING_EDGE>;
		 */
		psl-in-pads = <>;
	};

	soc {
		bbram: bb-ram@400af000 {
			compatible = "nuvoton,npcx-bbram";
			reg = <0x400af000 0x80
			       0x400af100 0x1>;
			reg-names = "memory", "status";
			label = "BBRAM";
		};

		pcc: clock-controller@4000d000 {
			compatible = "nuvoton,npcx-pcc";
			/* Cells for bus type, clock control reg and bit */
			#clock-cells = <3>;
			/* First reg region is Power Management Controller */
			/* Second reg region is Core Domain Clock Generator */
			reg = <0x4000d000 0x2000
			       0x400b5000 0x2000>;
			reg-names = "pmc", "cdcg";
			label = "PMC_CDCG";
		};

		scfg: scfg@400c3000 {
			compatible = "nuvoton,npcx-scfg";
			/* First reg region is System Configuration Device */
			/* Second reg region is System Glue Device */
			reg = <0x400c3000 0x70
			       0x400a5000 0x2000>;
			reg-names = "scfg", "glue";
			#alt-cells = <3>;
			#lvol-cells = <4>;
			label = "SCFG";
		};

		mdc: mdc@4000c000 {
			compatible = "syscon";
			reg = <0x4000c000 0xa>;
			reg-io-width = <1>;
		};

		mdc_header: mdc@4000c00a {
			compatible = "syscon";
			reg = <0x4000c00a 0x4>;
			reg-io-width = <2>;
		};

		miwu0: miwu@400bb000 {
			compatible = "nuvoton,npcx-miwu";
			reg = <0x400bb000 0x2000>;
			index = <0>;
			#miwu-cells = <2>;
			label="MIWU_0";
		};

		miwu1: miwu@400bd000 {
			compatible = "nuvoton,npcx-miwu";
			reg = <0x400bd000 0x2000>;
			index = <1>;
			#miwu-cells = <2>;
			label="MIWU_1";
		};

		miwu2: miwu@400bf000 {
			compatible = "nuvoton,npcx-miwu";
			reg = <0x400bf000 0x2000>;
			index = <2>;
			#miwu-cells = <2>;
			label="MIWU_2";
		};

		gpio0: gpio@40081000 {
			compatible = "nuvoton,npcx-gpio";
			reg = <0x40081000 0x2000>;
			gpio-controller;
			index = <0x0>;
			#gpio-cells=<2>;
			label="GPIO_0";
		};

		gpio1: gpio@40083000 {
			compatible = "nuvoton,npcx-gpio";
			reg = <0x40083000 0x2000>;
			gpio-controller;
			index = <0x1>;
			#gpio-cells=<2>;
			label="GPIO_1";
		};

		gpio2: gpio@40085000 {
			compatible = "nuvoton,npcx-gpio";
			reg = <0x40085000 0x2000>;
			gpio-controller;
			index = <0x2>;
			#gpio-cells=<2>;
			label="GPIO_2";
		};

		gpio3: gpio@40087000 {
			compatible = "nuvoton,npcx-gpio";
			reg = <0x40087000 0x2000>;
			gpio-controller;
			index = <0x3>;
			#gpio-cells=<2>;
			label="GPIO_3";
		};

		gpio4: gpio@40089000 {
			compatible = "nuvoton,npcx-gpio";
			reg = <0x40089000 0x2000>;
			gpio-controller;
			index = <0x4>;
			#gpio-cells=<2>;
			label="GPIO_4";
		};

		gpio5: gpio@4008b000 {
			compatible = "nuvoton,npcx-gpio";
			reg = <0x4008b000 0x2000>;
			gpio-controller;
			index = <0x5>;
			#gpio-cells=<2>;
			label="GPIO_5";
		};

		gpio6: gpio@4008d000 {
			compatible = "nuvoton,npcx-gpio";
			reg = <0x4008d000 0x2000>;
			gpio-controller;
			index = <0x6>;
			#gpio-cells=<2>;
			label="GPIO_6";
		};

		gpio7: gpio@4008f000 {
			compatible = "nuvoton,npcx-gpio";
			reg = <0x4008f000 0x2000>;
			gpio-controller;
			index = <0x7>;
			#gpio-cells=<2>;
			label="GPIO_7";
		};

		gpio8: gpio@40091000 {
			compatible = "nuvoton,npcx-gpio";
			reg = <0x40091000 0x2000>;
			gpio-controller;
			index = <0x8>;
			#gpio-cells=<2>;
			label="GPIO_8";
		};

		gpio9: gpio@40093000 {
			compatible = "nuvoton,npcx-gpio";
			reg = <0x40093000 0x2000>;
			gpio-controller;
			index = <0x9>;
			#gpio-cells=<2>;
			label="GPIO_9";
		};

		gpioa: gpio@40095000 {
			compatible = "nuvoton,npcx-gpio";
			reg = <0x40095000 0x2000>;
			gpio-controller;
			index = <0xA>;
			#gpio-cells=<2>;
			label="GPIO_A";
		};

		gpiob: gpio@40097000 {
			compatible = "nuvoton,npcx-gpio";
			reg = <0x40097000 0x2000>;
			gpio-controller;
			index = <0xB>;
			#gpio-cells=<2>;
			label="GPIO_B";
		};

		gpioc: gpio@40099000 {
			compatible = "nuvoton,npcx-gpio";
			reg = <0x40099000 0x2000>;
			gpio-controller;
			index = <0xC>;
			#gpio-cells=<2>;
			label="GPIO_C";
		};

		gpiod: gpio@4009b000 {
			compatible = "nuvoton,npcx-gpio";
			reg = <0x4009b000 0x2000>;
			gpio-controller;
			index = <0xD>;
			#gpio-cells=<2>;
			label="GPIO_D";
		};

		gpioe: gpio@4009d000 {
			compatible = "nuvoton,npcx-gpio";
			reg = <0x4009d000 0x2000>;
			gpio-controller;
			index = <0xE>;
			#gpio-cells=<2>;
			label="GPIO_E";
		};

		gpiof: gpio@4009f000 {
			compatible = "nuvoton,npcx-gpio";
			reg = <0x4009f000 0x2000>;
			gpio-controller;
			index = <0xF>;
			#gpio-cells=<2>;
			label="GPIO_F";
		};

		pwm0: pwm@40080000 {
			compatible = "nuvoton,npcx-pwm";
			reg = <0x40080000 0x2000>;
			clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 0>;
			pinctrl-0 = <&alt4_pwm0_sl>; /* PINC3 */
			#pwm-cells = <2>;
			status = "disabled";
			label = "PWM_0";
		};

		pwm1: pwm@40082000 {
			compatible = "nuvoton,npcx-pwm";
			reg = <0x40082000 0x2000>;
			clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 1>;
			pinctrl-0 = <&alt4_pwm1_sl>; /* PINC2 */
			#pwm-cells = <2>;
			status = "disabled";
			label = "PWM_1";
		};

		pwm2: pwm@40084000 {
			compatible = "nuvoton,npcx-pwm";
			reg = <0x40084000 0x2000>;
			clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 2>;
			pinctrl-0 = <&alt4_pwm2_sl>; /* PINC4 */
			#pwm-cells = <2>;
			status = "disabled";
			label = "PWM_2";
		};

		pwm3: pwm@40086000 {
			compatible = "nuvoton,npcx-pwm";
			reg = <0x40086000 0x2000>;
			clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 3>;
			pinctrl-0 = <&alt4_pwm3_sl>; /* PIN80 */
			#pwm-cells = <2>;
			status = "disabled";
			label = "PWM_3";
		};

		pwm4: pwm@40088000 {
			compatible = "nuvoton,npcx-pwm";
			reg = <0x40088000 0x2000>;
			clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 4>;
			pinctrl-0 = <&alt4_pwm4_sl>; /* PINB6 */
			#pwm-cells = <2>;
			status = "disabled";
			label = "PWM_4";
		};

		pwm5: pwm@4008a000 {
			compatible = "nuvoton,npcx-pwm";
			reg = <0x4008a000 0x2000>;
			clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 5>;
			pinctrl-0 = <&alt4_pwm5_sl>; /* PINB7 */
			#pwm-cells = <2>;
			status = "disabled";
			label = "PWM_5";
		};

		pwm6: pwm@4008c000 {
			compatible = "nuvoton,npcx-pwm";
			reg = <0x4008c000 0x2000>;
			clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 6>;
			pinctrl-0 = <&alt4_pwm6_sl>; /* PINC0 */
			#pwm-cells = <2>;
			status = "disabled";
			label = "PWM_6";
		};

		pwm7: pwm@4008e000 {
			compatible = "nuvoton,npcx-pwm";
			reg = <0x4008e000 0x2000>;
			clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 7>;
			pinctrl-0 = <&alt4_pwm7_sl>; /* PIN60 */
			#pwm-cells = <2>;
			status = "disabled";
			label = "PWM_7";
		};

		adc0: adc@400d1000 {
			compatible = "nuvoton,npcx-adc";
			#io-channel-cells = <1>;
			reg = <0x400d1000 0x2000>;
			interrupts = <10 3>;
			clocks = <&pcc NPCX_CLOCK_BUS_APB1 NPCX_PWDWN_CTL4 4>;
			status = "disabled";
			label = "ADC_0";
		};

		twd0: watchdog@400d8000 {
			compatible = "nuvoton,npcx-watchdog";
			reg = <0x400d8000 0x2000>;
			t0-out = <&wui_t0out>;
			label = "TWD_0";
		};

		espi0: espi@4000a000 {
			compatible = "nuvoton,npcx-espi";
			reg = <0x4000a000 0x2000>;
			interrupts = <18 3>; /* Interrupt for eSPI Bus */

			/* clocks for eSPI modules */
			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL6 7>;
			/* PIN46.47.51.52.53.54.55.57 */
			pinctrl-0 = <&alt1_no_lpc_espi>;
			/* WUI maps for eSPI signals */
			espi-rst-wui = <&wui_espi_rst>;
			label = "ESPI_0";

			#address-cells = <1>;
			#size-cells = <0>;
			#vw-cells = <3>;
			status = "disabled";
		};

		host_sub: lpc@400c1000 {
			compatible = "nuvoton,npcx-host-sub";
			/* host sub-module register address & size */
			reg = <0x400c1000 0x2000
			       0x40010000 0x2000
			       0x4000e000 0x2000
			       0x400c7000 0x2000
			       0x400c9000 0x2000
			       0x400cb000 0x2000>;
			reg-names = "mswc", "shm", "c2h", "kbc", "pm_acpi",
				    "pm_hcmd";

			/* host sub-module IRQ and priority */
			interrupts = <25 3>, /* KBC Input-Buf-Full (IBF) */
				     <56 3>, /* KBC Output-Buf-Empty (OBE) */
				     <26 3>, /* PMCH Input-Buf-Full (IBF) */
				     <3 3>,  /* PMCH Output-Buf-Empty (OBE) */
				     <6 3>;  /* Port80 FIFO Not Empty */
			interrupt-names = "kbc_ibf", "kbc_obe", "pmch_ibf",
					  "pmch_obe", "p80_fifo";

			/* WUI map for accessing host sub-modules */
			host-acc-wui = <&wui_host_acc>;

			/* clocks for host sub-modules */
			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 3>,
				<&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 4>,
				<&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 5>,
				<&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 6>,
				<&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 7>;
			label = "HOST_SUBS";
		};

		/* I2c Controllers - Do not use them as i2c node directly */
		i2c_ctrl0: i2c@40009000 {
			compatible = "nuvoton,npcx-i2c-ctrl";
			reg = <0x40009000 0x1000>;
			interrupts = <13 3>;
			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 0>;
			label = "I2CCTRL_0";
			status = "disabled";
		};

		i2c_ctrl1: i2c@4000b000 {
			compatible = "nuvoton,npcx-i2c-ctrl";
			reg = <0x4000b000 0x1000>;
			interrupts = <14 3>;
			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 1>;
			label = "I2CCTRL_1";
			status = "disabled";
		};

		i2c_ctrl2: i2c@400c0000 {
			compatible = "nuvoton,npcx-i2c-ctrl";
			reg = <0x400c0000 0x1000>;
			interrupts = <36 3>;
			clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL3 2>;
			label = "I2CCTRL_2";
			status = "disabled";
		};

		i2c_ctrl3: i2c@400c2000 {
			compatible = "nuvoton,npcx-i2c-ctrl";
			reg = <0x400c2000 0x1000>;
			interrupts = <37 3>;
			clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL3 3>;
			label = "I2CCTRL_3";
			status = "disabled";
		};

		i2c_ctrl4: i2c@40008000 {
			compatible = "nuvoton,npcx-i2c-ctrl";
			reg = <0x40008000 0x1000>;
			interrupts = <19 3>;
			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 4>;
			label = "I2CCTRL_4";
			status = "disabled";
		};

		i2c_ctrl5: i2c@40017000 {
			compatible = "nuvoton,npcx-i2c-ctrl";
			reg = <0x40017000 0x1000>;
			interrupts = <20 3>;
			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 0>;
			label = "I2CCTRL_5";
			status = "disabled";
		};

		i2c_ctrl6: i2c@40018000 {
			compatible = "nuvoton,npcx-i2c-ctrl";
			reg = <0x40018000 0x1000>;
			interrupts = <16 3>;
			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 1>;
			label = "I2CCTRL_6";
			status = "disabled";
		};

		i2c_ctrl7: i2c@40019000 {
			compatible = "nuvoton,npcx-i2c-ctrl";
			reg = <0x40019000 0x1000>;
			interrupts = <8 3>;
			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 2>;
			label = "I2CCTRL_7";
			status = "disabled";
		};

		tach1: tach@400e1000 {
			compatible = "nuvoton,npcx-tach";
			reg = <0x400e1000 0x2000>;
			clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL1 5>;
			label = "TACH_1";
			status = "disabled";
		};

		tach2: tach@400e3000 {
			compatible = "nuvoton,npcx-tach";
			reg = <0x400e3000 0x2000>;
			clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL1 6>;
			label = "TACH_2";
			status = "disabled";
		};

		ps2_ctrl0: ps2@400b1000 {
			compatible = "nuvoton,npcx-ps2-ctrl";
			reg = <0x400b1000 0x1000>;
			interrupts = <21 4>;
			clocks = <&pcc NPCX_CLOCK_BUS_FREERUN NPCX_PWDWN_CTL1 3>;
			label = "PS2_CTRL_0";

			/* PS2 Channels - Please use them as PS2 node */
			ps2_channel0: io_ps2_channel0 {
				compatible = "nuvoton,npcx-ps2-channel";
				channel = <0x00>;
				pinctrl-0 = <&alt3_ps2_0_sl>; /* PIN67.70 */
				label = "PS2_CHANNEL_0";
				status = "disabled";
			};

			ps2_channel1: io_ps2_channel1 {
				compatible = "nuvoton,npcx-ps2-channel";
				channel = <0x01>;
				pinctrl-0 = <&alt3_ps2_1_sl>; /* PIN62.63 */
				label = "PS2_CHANNEL_1";
				status = "disabled";
			};

			ps2_channel2: io_ps2_channel2 {
				compatible = "nuvoton,npcx-ps2-channel";
				channel = <0x02>;
				pinctrl-0 = <&alt3_ps2_2_sl>; /* PIN37.34 */
				label = "PS2_CHANNEL_2";
				status = "disabled";
			};

			ps2_channel3: io_ps2_channel3 {
				compatible = "nuvoton,npcx-ps2-channel";
				channel = <0x03>;
				pinctrl-0 = <&altc_ps2_3_sl2>; /* PINA6.A7 */
				label = "PS2_CHANNEL_3";
				status = "disabled";
			};
		};

		/* Dedicated SPI interface to access SPI flashes */
		spi_fiu0: spi@40020000 {
			compatible = "nuvoton,npcx-spi-fiu";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40020000 0x2000>;
			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL1 2>;
			label = "SPI_FIU";
		};
	};

	soc-if {
		/* Soc specific peripheral interface phandles which don't contain
		 * 'reg' prop. Please overwrite 'status' prop. to 'okay' if you
		 * want to switch the interface from io to specific peripheral.
		 */
		host_uart: io_host_uart {
			compatible = "nuvoton,npcx-host-uart";
			/* Host serial port pinmux PIN75 86 36 33 42 C7 B3 B2 */
			pinctrl-0 = <&altb_rxd_sl &altb_txd_sl
						&altb_rts_sl &altb_cts_sl
						&altb_ri_sl &altb_dtr_bout_sl
						&altb_dcd_sl &altb_dsr_sl>;
			label = "HOST_UART_IO";
			status = "disabled";
		};

		psl_out: psl-out {
			compatible = "nuvoton,npcx-psl-out";
			controller = <&gpio8>;
			pin = <5>;
			label = "PSL_OUT";
		};

		i2c0_0: io_i2c_ctrl0_port0 {
			compatible = "nuvoton,npcx-i2c-port";
			#address-cells = <1>;
			#size-cells = <0>;
			port = <0x00>;
			controller = <&i2c_ctrl0>;
			pinctrl-0 = <&alt2_i2c0_0_sl>; /* PINB5.B4 */
			label = "I2C_0_PORT_0";
			status = "disabled";
		};

		i2c1_0: io_i2c_ctrl1_port0 {
			compatible = "nuvoton,npcx-i2c-port";
			#address-cells = <1>;
			#size-cells = <0>;
			port = <0x10>;
			controller = <&i2c_ctrl1>;
			pinctrl-0 = <&alt2_i2c1_0_sl>; /* PIN90.87 */
			label = "I2C_1_PORT_0";
			status = "disabled";
		};

		i2c2_0: io_i2c_ctrl2_port0 {
			compatible = "nuvoton,npcx-i2c-port";
			#address-cells = <1>;
			#size-cells = <0>;
			port = <0x20>;
			controller = <&i2c_ctrl2>;
			pinctrl-0 = <&alt2_i2c2_0_sl>; /* PIN92.91 */
			label = "I2C_2_PORT_0";
			status = "disabled";
		};

		i2c3_0: io_i2c_ctrl3_port0 {
			compatible = "nuvoton,npcx-i2c-port";
			#address-cells = <1>;
			#size-cells = <0>;
			port = <0x30>;
			controller = <&i2c_ctrl3>;
			pinctrl-0 = <&alt2_i2c3_0_sl>; /* PIND1.D0 */
			label = "I2C_3_PORT_0";
			status = "disabled";
		};

		i2c4_1: io_i2c_ctrl4_port1 {
			compatible = "nuvoton,npcx-i2c-port";
			#address-cells = <1>;
			#size-cells = <0>;
			port = <0x41>;
			controller = <&i2c_ctrl4>;
			pinctrl-0 = <&alt6_i2c4_1_sl>; /* PINF3.F2 */
			label = "I2C_4_PORT_1";
			status = "disabled";
		};

		i2c5_0: io_i2c_ctrl5_port0 {
			compatible = "nuvoton,npcx-i2c-port";
			#address-cells = <1>;
			#size-cells = <0>;
			port = <0x50>;
			controller = <&i2c_ctrl5>;
			pinctrl-0 = <&alt2_i2c5_0_sl>; /* PIN33.36 */
			label = "I2C_5_PORT_0";
			status = "disabled";
		};

		i2c5_1: io_i2c_ctrl5_port1 {
			compatible = "nuvoton,npcx-i2c-port";
			#address-cells = <1>;
			#size-cells = <0>;
			port = <0x51>;
			controller = <&i2c_ctrl5>;
			pinctrl-0 = <&alt6_i2c5_1_sl>; /* PINF5.F4 */
			label = "I2C_5_PORT_1";
			status = "disabled";
		};

		i2c6_0: io_i2c_ctrl6_port0 {
			compatible = "nuvoton,npcx-i2c-port";
			#address-cells = <1>;
			#size-cells = <0>;
			port = <0x60>;
			controller = <&i2c_ctrl6>;
			pinctrl-0 = <&alt2_i2c6_0_sl>; /* PINC2.C1 */
			label = "I2C_6_PORT_0";
			status = "disabled";
		};

		i2c6_1: io_i2c_ctrl6_port1 {
			compatible = "nuvoton,npcx-i2c-port";
			#address-cells = <1>;
			#size-cells = <0>;
			port = <0x61>;
			controller = <&i2c_ctrl6>;
			pinctrl-0 = <&alt6_i2c6_1_sl>; /* PINE4.E3 */
			label = "I2C_6_PORT_1";
			status = "disabled";
		};

		i2c7_0: io_i2c_ctrl7_port0 {
			compatible = "nuvoton,npcx-i2c-port";
			#address-cells = <1>;
			#size-cells = <0>;
			port = <0x70>;
			controller = <&i2c_ctrl7>;
			pinctrl-0 = <&alt2_i2c7_0_sl>; /* PINB3.B2 */
			label = "I2C_7_PORT_0";
			status = "disabled";
		};
	};

	soc-id {
		compatible = "nuvoton,npcx-soc-id";
		family-id = <0x20>;
	};

	booter-variant {
		compatible = "nuvoton,npcx-booter-variant";
	};
};

&nvic {
	arm,num-irq-priority-bits = <3>;
};