# Copyright (c) 2020 Nuvoton Technology Corporation.
# SPDX-License-Identifier: Apache-2.0

description: |
  Nuvoton, NPCX PCC (Power and Clock Controller) node.
  Besides power management, this node is also in charge of configuring the
  Oscillator Frequency Multiplier Clock (OFMCLK), which is derived from
  High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
  and most of NPCX hardware modules.

  Here is an example of configuring OFMCLK and the other clock sources derived
  from it in board dts file.
  &pcc {
      clock-frequency = <DT_FREQ_M(100)>; /* OFMCLK runs at 100MHz */
      core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
      apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
      apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
      apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
  };

compatible: "nuvoton,npcx-pcc"

include: [clock-controller.yaml, base.yaml]

properties:
  reg:
    required: true

  clock-frequency:
    required: true
    type: int
    description: |
      Default frequency in Hz for HFCG output clock (OFMCLK). Currently,
      only the following values are allowed:
        100000000, 100 MHz
        96000000, 96 MHz
        90000000, 90 MHz
        80000000, 80 MHz
        66000000, 66 MHz
        50000000, 50 MHz
        48000000, 48 MHz
        40000000, 40 MHz (default value after reset)
        33000000, 33 MHz
    enum:
      - 100000000
      - 96000000
      - 90000000
      - 80000000
      - 66000000
      - 50000000
      - 48000000
      - 40000000
      - 33000000

  core-prescaler:
    type: int
    required: true
    description: |
      Core clock prescaler (FPRED). It sets the Core frequency, CORE_CLK, by
      dividing OFMCLK(MCLK) and needs to meet the following requirements.
      - CORE_CLK must be set to 4MHz <= CORE_CLK <= 100MHz.
      = Only the following values are allowed:
        1, CORE_CLK = OFMCLK
        2, CORE_CLK = OFMCLK / 2
        3, CORE_CLK = OFMCLK / 3
        4, CORE_CLK = OFMCLK / 4
        5, CORE_CLK = OFMCLK / 5
        6, CORE_CLK = OFMCLK / 6
        7, CORE_CLK = OFMCLK / 7
        8, CORE_CLK = OFMCLK / 8
        9, CORE_CLK = OFMCLK / 9
        10, CORE_CLK = OFMCLK / 10
    enum:
      - 1
      - 2
      - 3
      - 4
      - 5
      - 6
      - 7
      - 8
      - 9
      - 10

  apb1-prescaler:
    type: int
    required: true
    description: |
      APB1 prescaler. It sets the APB1 bus frequency, APB1_CLK, by dividing
      OFMCLK(MCLK) and needs to meet the following requirements.
      - APB1_CLK must be set to 4MHz <= APB1_CLK <= 50MHz.
      - APB1_CLK must be an integer division (including 1) of CORE_CLK.
      = Only the following values are allowed:
        1, APB1_CLK = OFMCLK
        2, APB1_CLK = OFMCLK / 2
        3, APB1_CLK = OFMCLK / 3
        4, APB1_CLK = OFMCLK / 4
        5, APB1_CLK = OFMCLK / 5
        6, APB1_CLK = OFMCLK / 6
        7, APB1_CLK = OFMCLK / 7
        8, APB1_CLK = OFMCLK / 8
        9, APB1_CLK = OFMCLK / 9
        10, APB1_CLK = OFMCLK / 10
    enum:
      - 1
      - 2
      - 3
      - 4
      - 5
      - 6
      - 7
      - 8
      - 9
      - 10

  apb2-prescaler:
    type: int
    required: true
    description: |
      APB2 prescaler. It sets the APB2 bus frequency, APB2_CLK, by dividing
      OFMCLK(MCLK) and needs to meet the following requirements.
      - APB2_CLK must be set to 8MHz <= APB2_CLK <= 50MHz.
      - APB2_CLK must be an integer division (including 1) of CORE_CLK.
      = Only the following values are allowed:
        1, APB2_CLK = OFMCLK
        2, APB2_CLK = OFMCLK / 2
        3, APB2_CLK = OFMCLK / 3
        4, APB2_CLK = OFMCLK / 4
        5, APB2_CLK = OFMCLK / 5
        6, APB2_CLK = OFMCLK / 6
        7, APB2_CLK = OFMCLK / 7
        8, APB2_CLK = OFMCLK / 8
        9, APB2_CLK = OFMCLK / 9
        10, APB2_CLK = OFMCLK / 10
    enum:
      - 1
      - 2
      - 3
      - 4
      - 5
      - 6
      - 7
      - 8
      - 9
      - 10

  apb3-prescaler:
    type: int
    required: true
    description: |
      APB3 prescaler. It sets the APB3 bus frequency, APB3_CLK, by dividing
      OFMCLK(MCLK) and needs to meet the following requirements.
      - APB3_CLK must be set to 12.5MHz <= APB3_CLK <= 50MHz.
      - APB3_CLK must be an integer division (including 1) of CORE_CLK.
      = Only the following values are allowed:
        1, APB3_CLK = OFMCLK
        2, APB3_CLK = OFMCLK / 2
        3, APB3_CLK = OFMCLK / 3
        4, APB3_CLK = OFMCLK / 4
        5, APB3_CLK = OFMCLK / 5
        6, APB3_CLK = OFMCLK / 6
        7, APB3_CLK = OFMCLK / 7
        8, APB3_CLK = OFMCLK / 8
        9, APB3_CLK = OFMCLK / 9
        10, APB3_CLK = OFMCLK / 10
    enum:
      - 1
      - 2
      - 3
      - 4
      - 5
      - 6
      - 7
      - 8
      - 9
      - 10

  apb4-prescaler:
    type: int
    description: |
      APB4 prescaler. It sets the APB4 bus frequency, APB4_CLK, by dividing
      OFMCLK(MCLK) and needs to meet the following requirements.
      - APB4_CLK must be set to 8MHz <= APB4_CLK <= 50MHz.
      - APB4_CLK must be an integer division (including 1) of CORE_CLK.
      = Only the following values are allowed:
        1, APB4_CLK = OFMCLK
        2, APB4_CLK = OFMCLK / 2
        3, APB4_CLK = OFMCLK / 3
        4, APB4_CLK = OFMCLK / 4
        5, APB4_CLK = OFMCLK / 5
        6, APB4_CLK = OFMCLK / 6
        7, APB4_CLK = OFMCLK / 7
        8, APB4_CLK = OFMCLK / 8
        9, APB4_CLK = OFMCLK / 9
        10, APB4_CLK = OFMCLK / 10
    enum:
      - 1
      - 2
      - 3
      - 4
      - 5
      - 6
      - 7
      - 8
      - 9
      - 10

  ram-pd-depth:
    type: int
    enum:
      - 12
      - 15
    description: |
      Valid bit-depth of RAM block Power-Down control (RAM_PD) registers.
      Each bit in RAM_PDn can power down the relevant RAM block by setting
      itself to 1 for better power consumption and this valid bit-depth
      varies in different NPCX series.

clock-cells:
  - bus
  - ctl
  - bit