fpga/gonk/csa_ctl_top.v

// Copyright 2023 The Pigweed Authors
//
// Licensed under the Apache License, Version 2.0 (the "License"); you may not
// use this file except in compliance with the License. You may obtain a copy of
// the License at
//
//     https://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
// License for the specific language governing permissions and limitations under
// the License.

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
//////////////////////////////////////////////////////////////////////////////////


module csa_ctl_top (
    input mclk_i,
    input rst_i,
    input r_w_en_i,
    input en_i,
    input mode_i,
    input [10:0] adc_sel_i,
    input [10:0] poll_adc_en_i,
    input [5:0] rwaddr_i,
    input [15:0] wdata_i,
    output reg dn_o,
    output reg [39:0] rdata_o,
    // spi interfaces
    input miso_i_1,
    input alertl_i_1,
    output sclk_o_1,
    output mosi_o_1,
    output cs_o_1,
    //
    input miso_i_2,
    input alertl_i_2,
    output sclk_o_2,
    output mosi_o_2,
    output cs_o_2,
    // spi interface
    input miso_i_3,
    input alertl_i_3,
    output sclk_o_3,
    output mosi_o_3,
    output cs_o_3,
    //
    input miso_i_4,
    input alertl_i_4,
    output sclk_o_4,
    output mosi_o_4,
    output cs_o_4,
    //
    input miso_i_5,
    input alertl_i_5,
    output sclk_o_5,
    output mosi_o_5,
    output cs_o_5,
    //
    input miso_i_6,
    input alertl_i_6,
    output sclk_o_6,
    output mosi_o_6,
    output cs_o_6,
    //
    input miso_i_7,
    input alertl_i_7,
    output sclk_o_7,
    output mosi_o_7,
    output cs_o_7,
    //
    input miso_i_8,
    input alertl_i_8,
    output sclk_o_8,
    output mosi_o_8,
    output cs_o_8,
    //
    input miso_i_9,
    input alertl_i_9,
    output sclk_o_9,
    output mosi_o_9,
    output cs_o_9,
    //
    input miso_i_10,
    input alertl_i_10,
    output sclk_o_10,
    output mosi_o_10,
    output cs_o_10,
    //
    input miso_i_11,
    input alertl_i_11,
    output sclk_o_11,
    output mosi_o_11,
    output cs_o_11,
    //
    input dn_clr_i,
    output reg poll_dn_o,
    // output [11:0] poll_dn,
    output [23:0] vbus_1,
    output [23:0] vshunt_1,
    output [23:0] vbus_2,
    output [23:0] vshunt_2,
    output [23:0] vbus_3,
    output [23:0] vshunt_3,
    output [23:0] vbus_4,
    output [23:0] vshunt_4,
    output [23:0] vbus_5,
    output [23:0] vshunt_5,
    output [23:0] vbus_6,
    output [23:0] vshunt_6,
    output [23:0] vbus_7,
    output [23:0] vshunt_7,
    output [23:0] vbus_8,
    output [23:0] vshunt_8,
    output [23:0] vbus_9,
    output [23:0] vshunt_9,
    output [23:0] vbus_10,
    output [23:0] vshunt_10,
    output [23:0] vbus_11,
    output [23:0] vshunt_11
    //
);
  //
  reg
      dn_latch_r1,
      dn_latch_r2,
      dn_latch_r3,
      dn_latch_r4,
      dn_latch_r5,
      dn_latch_r6,
      dn_latch_r7,
      dn_latch_r8,
      dn_latch_r9,
      dn_latch_r10,
      dn_latch_r11,
      rst_i_r;
  reg
      poll_dn_latch_r1,
      poll_dn_latch_r2,
      poll_dn_latch_r3,
      poll_dn_latch_r4,
      poll_dn_latch_r5,
      poll_dn_latch_r6,
      poll_dn_latch_r7,
      poll_dn_latch_r8,
      poll_dn_latch_r9,
      poll_dn_latch_r10,
      poll_dn_latch_r11;
  reg en_r1, en_r2, en_r3, en_r4, en_r5, en_r6, en_r7, en_r8, en_r9, en_r10, en_r11;
  reg dn_r, poll_dn_r;
  reg
      r_w_en_r1,
      r_w_en_r2,
      r_w_en_r3,
      r_w_en_r4,
      r_w_en_r5,
      r_w_en_r6,
      r_w_en_r7,
      r_w_en_r8,
      r_w_en_r9,
      r_w_en_r10,
      r_w_en_r11;
  reg en_r, r_w_en_r;
  reg [ 5:0] rwaddr_r;
  reg [10:0] adc_sel_r;
  reg [15:0] wdata_r;
  //
  wire poll_dn_r1,poll_dn_r2,poll_dn_r3,poll_dn_r4,poll_dn_r5,poll_dn_r6,poll_dn_r7,poll_dn_r8,poll_dn_r9,poll_dn_r10,poll_dn_r11;
  wire dn_r1, dn_r2, dn_r3, dn_r4, dn_r5, dn_r6, dn_r7, dn_r8, dn_r9, dn_r10, dn_r11;
  wire [39:0] rdata_w1,rdata_w2,rdata_w3,rdata_w4,rdata_w5,rdata_w6,rdata_w7,rdata_w8,rdata_w9,rdata_w10,rdata_w11;
  //

  always @(posedge mclk_i) begin
    rst_i_r <= rst_i;
  end

  spi_m_core_ctl csa_1 (
      .mclk_i(mclk_i),
      .rst_i(rst_i_r),
      .dn_clr_i(dn_clr_i),
      .r_w_en_i(r_w_en_r1),
      .en_i(en_r1),
      .mode_i(mode_i),
      .rwaddr_i(rwaddr_r),
      .wdata_i(wdata_r),
      //.poll_en_i(poll_adc_en_i[0]),
      .dn_o(dn_r1),
      .rdata_o(rdata_w1),
      .vbus_o(vbus_1),
      .vshunt_o(vshunt_1),
      .poll_dn_o(poll_dn_r1),
      .miso_i(miso_i_1),
      .alert_n_i(alertl_i_1),
      .sclk_o(sclk_o_1),
      .mosi_o(mosi_o_1),
      .cs_o(cs_o_1)
  );

  spi_m_core_ctl csa_2 (
      .mclk_i(mclk_i),
      .rst_i(rst_i_r),
      .dn_clr_i(dn_clr_i),
      .r_w_en_i(r_w_en_r2),
      .en_i(en_r2),
      .mode_i(mode_i),
      .rwaddr_i(rwaddr_r),
      .wdata_i(wdata_r),
      //.poll_en_i(poll_adc_en_i[1]),
      .dn_o(dn_r2),
      .rdata_o(rdata_w2),
      .vbus_o(vbus_2),
      .vshunt_o(vshunt_2),
      .poll_dn_o(poll_dn_r2),
      .miso_i(miso_i_2),
      .alert_n_i(alertl_i_2),
      .sclk_o(sclk_o_2),
      .mosi_o(mosi_o_2),
      .cs_o(cs_o_2)
  );

  spi_m_core_ctl csa_3 (
      .mclk_i(mclk_i),
      .rst_i(rst_i_r),
      .dn_clr_i(dn_clr_i),
      .r_w_en_i(r_w_en_r3),
      .en_i(en_r3),
      .mode_i(mode_i),
      .rwaddr_i(rwaddr_r),
      .wdata_i(wdata_r),
      //.poll_en_i(poll_adc_en_i[2]),
      .dn_o(dn_r3),
      .rdata_o(rdata_w3),
      .vbus_o(vbus_3),
      .vshunt_o(vshunt_3),
      .poll_dn_o(poll_dn_r3),
      .miso_i(miso_i_3),
      .alert_n_i(alertl_i_3),
      .sclk_o(sclk_o_3),
      .mosi_o(mosi_o_3),
      .cs_o(cs_o_3)
  );

  spi_m_core_ctl csa_4 (
      .mclk_i(mclk_i),
      .rst_i(rst_i_r),
      .dn_clr_i(dn_clr_i),
      .r_w_en_i(r_w_en_r4),
      .en_i(en_r4),
      .mode_i(mode_i),
      .rwaddr_i(rwaddr_r),
      .wdata_i(wdata_r),
      //.poll_en_i(poll_adc_en_i[3]),
      .dn_o(dn_r4),
      .rdata_o(rdata_w4),
      .vbus_o(vbus_4),
      .vshunt_o(vshunt_4),
      .poll_dn_o(poll_dn_r4),
      .miso_i(miso_i_4),
      .alert_n_i(alertl_i_4),
      .sclk_o(sclk_o_4),
      .mosi_o(mosi_o_4),
      .cs_o(cs_o_4)
  );

  spi_m_core_ctl csa_5 (
      .mclk_i(mclk_i),
      .rst_i(rst_i_r),
      .dn_clr_i(dn_clr_i),
      .r_w_en_i(r_w_en_r5),
      .en_i(en_r5),
      .mode_i(mode_i),
      .rwaddr_i(rwaddr_r),
      .wdata_i(wdata_r),
      //.poll_en_i(poll_adc_en_i[4]),
      .dn_o(dn_r5),
      .rdata_o(rdata_w5),
      .vbus_o(vbus_5),
      .vshunt_o(vshunt_5),
      .poll_dn_o(poll_dn_r5),
      .miso_i(miso_i_5),
      .alert_n_i(alertl_i_5),
      .sclk_o(sclk_o_5),
      .mosi_o(mosi_o_5),
      .cs_o(cs_o_5)
  );


  spi_m_core_ctl csa_6 (
      .mclk_i(mclk_i),
      .rst_i(rst_i_r),
      .dn_clr_i(dn_clr_i),
      .r_w_en_i(r_w_en_r6),
      .en_i(en_r6),
      .mode_i(mode_i),
      .rwaddr_i(rwaddr_r),
      .wdata_i(wdata_r),
      //.poll_en_i(poll_adc_en_i[5]),
      .dn_o(dn_r6),
      .rdata_o(rdata_w6),
      .vbus_o(vbus_6),
      .vshunt_o(vshunt_6),
      .poll_dn_o(poll_dn_r6),
      .miso_i(miso_i_6),
      .alert_n_i(alertl_i_6),
      .sclk_o(sclk_o_6),
      .mosi_o(mosi_o_6),
      .cs_o(cs_o_6)
  );

  spi_m_core_ctl csa_7 (
      .mclk_i(mclk_i),
      .rst_i(rst_i_r),
      .dn_clr_i(dn_clr_i),
      .r_w_en_i(r_w_en_r7),
      .en_i(en_r7),
      .mode_i(mode_i),
      .rwaddr_i(rwaddr_r),
      .wdata_i(wdata_r),
      //.poll_en_i(poll_adc_en_i[6]),
      .dn_o(dn_r7),
      .rdata_o(rdata_w7),
      .vbus_o(vbus_7),
      .vshunt_o(vshunt_7),
      .poll_dn_o(poll_dn_r7),
      .miso_i(miso_i_7),
      .alert_n_i(alertl_i_7),
      .sclk_o(sclk_o_7),
      .mosi_o(mosi_o_7),
      .cs_o(cs_o_7)
  );

  spi_m_core_ctl csa_8 (
      .mclk_i(mclk_i),
      .rst_i(rst_i_r),
      .dn_clr_i(dn_clr_i),
      .r_w_en_i(r_w_en_r8),
      .en_i(en_r8),
      .mode_i(mode_i),
      .rwaddr_i(rwaddr_r),
      .wdata_i(wdata_r),
      //.poll_en_i(poll_adc_en_i[7]),
      .dn_o(dn_r8),
      .rdata_o(rdata_w8),
      .vbus_o(vbus_8),
      .vshunt_o(vshunt_8),
      .poll_dn_o(poll_dn_r8),
      .miso_i(miso_i_8),
      .alert_n_i(alertl_i_8),
      .sclk_o(sclk_o_8),
      .mosi_o(mosi_o_8),
      .cs_o(cs_o_8)
  );

  spi_m_core_ctl csa_9 (
      .mclk_i(mclk_i),
      .rst_i(rst_i_r),
      .dn_clr_i(dn_clr_i),
      .r_w_en_i(r_w_en_r9),
      .en_i(en_r9),
      .mode_i(mode_i),
      .rwaddr_i(rwaddr_r),
      .wdata_i(wdata_r),
      //.poll_en_i(poll_adc_en_i[8]),
      .dn_o(dn_r9),
      .rdata_o(rdata_w9),
      .vbus_o(vbus_9),
      .vshunt_o(vshunt_9),
      .poll_dn_o(poll_dn_r9),
      .miso_i(miso_i_9),
      .alert_n_i(alertl_i_9),
      .sclk_o(sclk_o_9),
      .mosi_o(mosi_o_9),
      .cs_o(cs_o_9)
  );

  spi_m_core_ctl csa_10 (
      .mclk_i(mclk_i),
      .rst_i(rst_i_r),
      .dn_clr_i(dn_clr_i),
      .r_w_en_i(r_w_en_r10),
      .en_i(en_r10),
      .mode_i(mode_i),
      .rwaddr_i(rwaddr_r),
      .wdata_i(wdata_r),
      //.poll_en_i(poll_adc_en_i[9]),
      .dn_o(dn_r10),
      .rdata_o(rdata_w10),
      .vbus_o(vbus_10),
      .vshunt_o(vshunt_10),
      .poll_dn_o(poll_dn_r10),
      .miso_i(miso_i_10),
      .alert_n_i(alertl_i_10),
      .sclk_o(sclk_o_10),
      .mosi_o(mosi_o_10),
      .cs_o(cs_o_10)
  );

  spi_m_core_ctl csa_11 (
      .mclk_i(mclk_i),
      .rst_i(rst_i_r),
      .dn_clr_i(dn_clr_i),
      .r_w_en_i(r_w_en_r11),
      .en_i(en_r11),
      .mode_i(mode_i),
      .rwaddr_i(rwaddr_r),
      .wdata_i(wdata_r),
      //.poll_en_i(poll_adc_en_i[10]),
      .dn_o(dn_r11),
      .rdata_o(rdata_w11),
      .vbus_o(vbus_11),
      .vshunt_o(vshunt_11),
      .poll_dn_o(poll_dn_r11),
      .miso_i(miso_i_11),
      .alert_n_i(alertl_i_11),
      .sclk_o(sclk_o_11),
      .mosi_o(mosi_o_11),
      .cs_o(cs_o_11)
  );

  always @(posedge mclk_i) begin
    if (rst_i_r) begin
      poll_dn_o <= 0;
      dn_o <= 0;
      en_r <= 0;
    end else begin
      poll_dn_o <= poll_dn_r;
      dn_o <= dn_r;
      en_r <= en_i;  // (en_i & !mode_i) ;
    end
  end

  always @(posedge mclk_i) begin
    if (rst_i_r) begin
      wdata_r  <= 0;
      rwaddr_r <= 0;
      r_w_en_r <= 0;
    end else begin
      if (en_i) begin
        wdata_r   <= wdata_i;
        rwaddr_r  <= rwaddr_i[5:0];
        r_w_en_r  <= r_w_en_i;
        adc_sel_r <= adc_sel_i;
      end
    end
  end

  always @(posedge mclk_i) begin
    if (r_w_en_r) begin
      r_w_en_r1  <= 1;
      r_w_en_r2  <= 1;
      r_w_en_r3  <= 1;
      r_w_en_r4  <= 1;
      r_w_en_r5  <= 1;
      r_w_en_r6  <= 1;
      r_w_en_r7  <= 1;
      r_w_en_r8  <= 1;
      r_w_en_r9  <= 1;
      r_w_en_r10 <= 1;
      r_w_en_r11 <= 1;
    end else begin
      r_w_en_r1  <= 0;
      r_w_en_r2  <= 0;
      r_w_en_r3  <= 0;
      r_w_en_r4  <= 0;
      r_w_en_r5  <= 0;
      r_w_en_r6  <= 0;
      r_w_en_r7  <= 0;
      r_w_en_r8  <= 0;
      r_w_en_r9  <= 0;
      r_w_en_r10 <= 0;
      r_w_en_r11 <= 0;
    end
  end

  always @(posedge mclk_i) begin
    if (rst_i_r) begin
      en_r1  <= 0;
      en_r2  <= 0;
      en_r3  <= 0;
      en_r4  <= 0;
      en_r5  <= 0;
      en_r6  <= 0;
      en_r7  <= 0;
      en_r8  <= 0;
      en_r9  <= 0;
      en_r10 <= 0;
      en_r11 <= 0;
    end else begin
      if (en_r) begin
        en_r1  <= adc_sel_r[0];
        en_r2  <= adc_sel_r[1];
        en_r3  <= adc_sel_r[2];
        en_r4  <= adc_sel_r[3];
        en_r5  <= adc_sel_r[4];
        en_r6  <= adc_sel_r[5];
        en_r7  <= adc_sel_r[6];
        en_r8  <= adc_sel_r[7];
        en_r9  <= adc_sel_r[8];
        en_r10 <= adc_sel_r[9];
        en_r11 <= adc_sel_r[10];
      end else begin
        en_r1  <= 0;
        en_r2  <= 0;
        en_r3  <= 0;
        en_r4  <= 0;
        en_r5  <= 0;
        en_r6  <= 0;
        en_r7  <= 0;
        en_r8  <= 0;
        en_r9  <= 0;
        en_r10 <= 0;
        en_r11 <= 0;
      end
    end
  end

  always @(posedge mclk_i) begin
    // priority.
    if (adc_sel_r < 64) begin
      if (adc_sel_r[0]) rdata_o <= rdata_w1;
      else if (adc_sel_r[1]) rdata_o <= rdata_w2;
      else if (adc_sel_r[2]) rdata_o <= rdata_w3;
      else if (adc_sel_r[3]) rdata_o <= rdata_w4;
      else if (adc_sel_r[4]) rdata_o <= rdata_w5;
      else if (adc_sel_r[5]) rdata_o <= rdata_w6;
    end else begin
      if (adc_sel_r[6]) rdata_o <= rdata_w7;
      else if (adc_sel_r[7]) rdata_o <= rdata_w8;
      else if (adc_sel_r[8]) rdata_o <= rdata_w9;
      else if (adc_sel_r[9]) rdata_o <= rdata_w10;
      else if (adc_sel_r[10]) rdata_o <= rdata_w11;
      else rdata_o <= 0;
    end
  end

  reg dn_latch_0_r, dn_latch_1_r, dn_latch_2_r, dn_latch_3_r;
  wire dn_latch_0, dn_latch_1, dn_latch_2, dn_latch_3, dn_w;

  // Change to AND to sync after bring-up
  assign dn_latch_0 = (dn_latch_r7 | dn_latch_r9 | dn_latch_r10);  // bank0
  assign dn_latch_1 = (dn_latch_r5 | dn_latch_r8 | dn_latch_r1);
  assign dn_latch_2 = (dn_latch_r4 | dn_latch_r6 | dn_latch_r3);
  assign dn_latch_3 = (dn_latch_r2 | dn_latch_r11);
  assign dn_w       = (dn_latch_0_r | dn_latch_1_r | dn_latch_2_r | dn_latch_3_r);

  always @(posedge mclk_i) begin
    if (rst_i_r) begin
      dn_r <= 0;
      dn_latch_0_r <= 0;
      dn_latch_1_r <= 0;
      dn_latch_2_r <= 0;
      dn_latch_3_r <= 0;
    end else begin
      dn_latch_0_r <= dn_latch_0;
      dn_latch_1_r <= dn_latch_1;
      dn_latch_2_r <= dn_latch_2;
      dn_latch_3_r <= dn_latch_3;
      dn_r <= dn_w;
    end
  end

  ///

  reg poll_dn_latch_1_r, poll_dn_latch_2_r, poll_dn_latch_3_r;
  reg poll_dn_latch_4_r, poll_dn_latch_5_r, poll_dn_latch_6_r, poll_dn_latch_7_r;
  reg poll_dn_latch_8_r, poll_dn_latch_9_r, poll_dn_latch_10_r, poll_dn_latch_11_r;

  wire poll_dn_latch_0, poll_dn_latch_1, poll_dn_latch_2, poll_dn_latch_3, poll_dn_w;
  wire poll_dn_latch_4, poll_dn_latch_5, poll_dn_latch_6, poll_dn_latch_7;
  wire poll_dn_latch_8, poll_dn_latch_9, poll_dn_latch_10, poll_dn_sync0, poll_dn_sync1,poll_dn_sync2,poll_dn_sync3 ;

  reg poll_dn_sync0_r, poll_dn_sync1_r, poll_dn_sync2_r, poll_dn_sync3_r;

  assign poll_dn_latch_0  = (poll_dn_latch_r1 | (!poll_adc_en_i[0]));
  assign poll_dn_latch_1  = (poll_dn_latch_r2 | (!poll_adc_en_i[1]));
  assign poll_dn_latch_2  = (poll_dn_latch_r3 | (!poll_adc_en_i[2]));
  assign poll_dn_latch_3  = (poll_dn_latch_r4 | (!poll_adc_en_i[3]));
  assign poll_dn_latch_4  = (poll_dn_latch_r5 | (!poll_adc_en_i[4]));
  assign poll_dn_latch_5  = (poll_dn_latch_r6 | (!poll_adc_en_i[5]));
  assign poll_dn_latch_6  = (poll_dn_latch_r7 | (!poll_adc_en_i[6]));
  assign poll_dn_latch_7  = (poll_dn_latch_r8 | (!poll_adc_en_i[7]));
  assign poll_dn_latch_8  = (poll_dn_latch_r9 | (!poll_adc_en_i[8]));
  assign poll_dn_latch_9  = (poll_dn_latch_r10 | (!poll_adc_en_i[9]));
  assign poll_dn_latch_10 = (poll_dn_latch_r11 | (!poll_adc_en_i[10]));

  assign poll_dn_sync0    = (poll_dn_latch_7_r & poll_dn_latch_9_r & poll_dn_latch_10_r);  // bank0
  assign poll_dn_sync1    = (poll_dn_latch_5_r & poll_dn_latch_8_r & poll_dn_latch_1_r);
  assign poll_dn_sync2    = (poll_dn_latch_4_r & poll_dn_latch_6_r & poll_dn_latch_3_r);
  assign poll_dn_sync3    = (poll_dn_latch_2_r & poll_dn_latch_11_r);

  assign poll_dn_w        = poll_dn_sync0 & poll_dn_sync1 & poll_dn_sync2 & poll_dn_sync3;

  always @(posedge mclk_i) begin
    if (rst_i_r) begin
      poll_dn_r <= 0;
      poll_dn_latch_1_r <= 0;
      poll_dn_latch_2_r <= 0;
      poll_dn_latch_3_r <= 0;
      poll_dn_latch_4_r <= 0;
      poll_dn_latch_5_r <= 0;
      poll_dn_latch_6_r <= 0;
      poll_dn_latch_7_r <= 0;
      poll_dn_latch_8_r <= 0;
      poll_dn_latch_9_r <= 0;
      poll_dn_latch_10_r <= 0;
      poll_dn_latch_11_r <= 0;
      poll_dn_sync0_r <= 0;
      poll_dn_sync1_r <= 0;
      poll_dn_sync2_r <= 0;
      poll_dn_sync3_r <= 0;
    end else begin
      poll_dn_latch_1_r <= poll_dn_latch_0;
      poll_dn_latch_2_r <= poll_dn_latch_1;
      poll_dn_latch_3_r <= poll_dn_latch_2;
      poll_dn_latch_4_r <= poll_dn_latch_3;
      poll_dn_latch_5_r <= poll_dn_latch_4;
      poll_dn_latch_6_r <= poll_dn_latch_5;
      poll_dn_latch_7_r <= poll_dn_latch_6;
      poll_dn_latch_8_r <= poll_dn_latch_7;
      poll_dn_latch_9_r <= poll_dn_latch_8;
      poll_dn_latch_10_r <= poll_dn_latch_9;
      poll_dn_latch_11_r <= poll_dn_latch_10;
      poll_dn_sync0_r <= poll_dn_sync0;
      poll_dn_sync1_r <= poll_dn_sync1;
      poll_dn_sync2_r <= poll_dn_sync2;
      poll_dn_sync3_r <= poll_dn_sync3;
      poll_dn_r <= poll_dn_w;
    end
  end

  always @(posedge mclk_i) begin
    if (rst_i_r | dn_clr_i) begin
      dn_latch_r1 <= 0;
    end else begin
      if (dn_r1) dn_latch_r1 <= 1;
    end
  end

  always @(posedge mclk_i) begin
    if (rst_i_r | dn_clr_i) begin
      dn_latch_r2 <= 0;
    end else begin
      if (dn_r2) dn_latch_r2 <= 1;
    end
  end

  always @(posedge mclk_i) begin
    if (rst_i_r | dn_clr_i) begin
      dn_latch_r3 <= 0;
    end else begin
      if (dn_r3) dn_latch_r3 <= 1;
    end
  end

  always @(posedge mclk_i) begin
    if (rst_i_r | dn_clr_i) begin
      dn_latch_r4 <= 0;
    end else begin
      if (dn_r4) dn_latch_r4 <= 1;
    end
  end

  always @(posedge mclk_i) begin
    if (rst_i_r | dn_clr_i) begin
      dn_latch_r5 <= 0;
    end else begin
      if (dn_r5) dn_latch_r5 <= 1;
    end
  end

  always @(posedge mclk_i) begin
    if (rst_i_r | dn_clr_i) begin
      dn_latch_r6 <= 0;
    end else begin
      if (dn_r6) dn_latch_r6 <= 1;
    end
  end

  always @(posedge mclk_i) begin
    if (rst_i_r | dn_clr_i) begin
      dn_latch_r7 <= 0;
    end else begin
      if (dn_r7) dn_latch_r7 <= 1;
    end
  end

  always @(posedge mclk_i) begin
    if (rst_i_r | dn_clr_i) begin
      dn_latch_r8 <= 0;
    end else begin
      if (dn_r8) dn_latch_r8 <= 1;
    end
  end

  always @(posedge mclk_i) begin
    if (rst_i_r | dn_clr_i) begin
      dn_latch_r9 <= 0;
    end else begin
      if (dn_r9) dn_latch_r9 <= 1;
    end
  end

  always @(posedge mclk_i) begin
    if (rst_i_r | dn_clr_i) begin
      dn_latch_r10 <= 0;
    end else begin
      if (dn_r10) dn_latch_r10 <= 1;
    end
  end

  always @(posedge mclk_i) begin
    if (rst_i_r | dn_clr_i) begin
      dn_latch_r11 <= 0;
    end else begin
      if (dn_r11) dn_latch_r11 <= 1;
    end
  end

  always @(posedge mclk_i) begin
    if (rst_i_r | dn_clr_i) begin
      poll_dn_latch_r1 <= 0;
    end else begin
      if (poll_dn_r1) poll_dn_latch_r1 <= 1;
    end
  end

  always @(posedge mclk_i) begin
    if (rst_i_r | dn_clr_i) begin
      poll_dn_latch_r2 <= 0;
    end else begin
      if (poll_dn_r2) poll_dn_latch_r2 <= 1;
    end
  end

  always @(posedge mclk_i) begin
    if (rst_i_r | dn_clr_i) begin
      poll_dn_latch_r3 <= 0;
    end else begin
      if (poll_dn_r3) poll_dn_latch_r3 <= 1;
    end
  end

  always @(posedge mclk_i) begin
    if (rst_i_r | dn_clr_i) begin
      poll_dn_latch_r4 <= 0;
    end else begin
      if (poll_dn_r4) poll_dn_latch_r4 <= 1;
    end
  end

  always @(posedge mclk_i) begin
    if (rst_i_r | dn_clr_i) begin
      poll_dn_latch_r5 <= 0;
    end else begin
      if (poll_dn_r5) poll_dn_latch_r5 <= 1;
    end
  end

  always @(posedge mclk_i) begin
    if (rst_i_r | dn_clr_i) begin
      poll_dn_latch_r6 <= 0;
    end else begin
      if (poll_dn_r6) poll_dn_latch_r6 <= 1;
    end
  end

  always @(posedge mclk_i) begin
    if (rst_i_r | dn_clr_i) begin
      poll_dn_latch_r7 <= 0;
    end else begin
      if (poll_dn_r7) poll_dn_latch_r7 <= 1;
    end
  end

  always @(posedge mclk_i) begin
    if (rst_i_r | dn_clr_i) begin
      poll_dn_latch_r8 <= 0;
    end else begin
      if (poll_dn_r8) poll_dn_latch_r8 <= 1;
    end
  end

  always @(posedge mclk_i) begin
    if (rst_i_r | dn_clr_i) begin
      poll_dn_latch_r9 <= 0;
    end else begin
      if (poll_dn_r9) poll_dn_latch_r9 <= 1;
    end
  end

  always @(posedge mclk_i) begin
    if (rst_i_r | dn_clr_i) begin
      poll_dn_latch_r10 <= 0;
    end else begin
      if (poll_dn_r10) poll_dn_latch_r10 <= 1;
    end
  end

  always @(posedge mclk_i) begin
    if (rst_i_r | dn_clr_i) begin
      poll_dn_latch_r11 <= 0;
    end else begin
      if (poll_dn_r11) poll_dn_latch_r11 <= 1;
    end
  end

endmodule