fpga/gonk/sig_sync.v

// Copyright 2023 The Pigweed Authors
//
// Licensed under the Apache License, Version 2.0 (the "License"); you may not
// use this file except in compliance with the License. You may obtain a copy of
// the License at
//
//     https://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
// License for the specific language governing permissions and limitations under
// the License.

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
//
//////////////////////////////////////////////////////////////////////////////////


module sig_sync (
    input  clk_i,
    input  rst_i,
    input  sig_i,
    output sig_o
);

  reg sig_i_r0, sig_i_r1, sig_i_r2;
  assign sig_o = sig_i_r2;

  always @(posedge clk_i) begin
    //    if (rst_i) begin  Commented out - to get rid of xor'ed pulses in rst_sync.v
    //      sig_i_r0 <= 0;
    //      sig_i_r1 <= 0;
    //      sig_i_r2 <= 0;
    //    end else begin
    sig_i_r0 <= sig_i;
    sig_i_r1 <= sig_i_r0;
    sig_i_r2 <= sig_i_r1;

    //    end
  end

endmodule