Starting point for the SAMD20 demo.
diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_ac.h b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_ac.h new file mode 100644 index 0000000..a2b5ac5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_ac.h
@@ -0,0 +1,86 @@ +/** + * \file + * + * \brief Instance description for AC + * + * Copyright (c) 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD20_AC_INSTANCE_ +#define _SAMD20_AC_INSTANCE_ + +/* ========== Register definition for AC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_AC_CTRLA (0x42004400U) /**< \brief (AC) Control A Register */ +#define REG_AC_CTRLB (0x42004401U) /**< \brief (AC) Control B Register */ +#define REG_AC_EVCTRL (0x42004402U) /**< \brief (AC) Event Control Register */ +#define REG_AC_INTENCLR (0x42004404U) /**< \brief (AC) Interrupt Enable Clear Register */ +#define REG_AC_INTENSET (0x42004405U) /**< \brief (AC) Interrupt Enable Set Register */ +#define REG_AC_INTFLAG (0x42004406U) /**< \brief (AC) Interrupt Flag Status and Clear Register */ +#define REG_AC_STATUSA (0x42004408U) /**< \brief (AC) Status A Register */ +#define REG_AC_STATUSB (0x42004409U) /**< \brief (AC) Status B Register */ +#define REG_AC_STATUSC (0x4200440AU) /**< \brief (AC) Status C Register */ +#define REG_AC_WINCTRL (0x4200440CU) /**< \brief (AC) Window Control Register */ +#define REG_AC_COMPCTRL0 (0x42004410U) /**< \brief (AC) Comparator Control Register 0 */ +#define REG_AC_COMPCTRL1 (0x42004414U) /**< \brief (AC) Comparator Control Register 1 */ +#define REG_AC_SCALER0 (0x42004420U) /**< \brief (AC) Scaler Register 0 */ +#define REG_AC_SCALER1 (0x42004421U) /**< \brief (AC) Scaler Register 1 */ +#else +#define REG_AC_CTRLA (*(RwReg8 *)0x42004400U) /**< \brief (AC) Control A Register */ +#define REG_AC_CTRLB (*(WoReg8 *)0x42004401U) /**< \brief (AC) Control B Register */ +#define REG_AC_EVCTRL (*(RwReg16*)0x42004402U) /**< \brief (AC) Event Control Register */ +#define REG_AC_INTENCLR (*(RwReg8 *)0x42004404U) /**< \brief (AC) Interrupt Enable Clear Register */ +#define REG_AC_INTENSET (*(RwReg8 *)0x42004405U) /**< \brief (AC) Interrupt Enable Set Register */ +#define REG_AC_INTFLAG (*(RwReg8 *)0x42004406U) /**< \brief (AC) Interrupt Flag Status and Clear Register */ +#define REG_AC_STATUSA (*(RoReg8 *)0x42004408U) /**< \brief (AC) Status A Register */ +#define REG_AC_STATUSB (*(RoReg8 *)0x42004409U) /**< \brief (AC) Status B Register */ +#define REG_AC_STATUSC (*(RoReg8 *)0x4200440AU) /**< \brief (AC) Status C Register */ +#define REG_AC_WINCTRL (*(RwReg8 *)0x4200440CU) /**< \brief (AC) Window Control Register */ +#define REG_AC_COMPCTRL0 (*(RwReg *)0x42004410U) /**< \brief (AC) Comparator Control Register 0 */ +#define REG_AC_COMPCTRL1 (*(RwReg *)0x42004414U) /**< \brief (AC) Comparator Control Register 1 */ +#define REG_AC_SCALER0 (*(RwReg8 *)0x42004420U) /**< \brief (AC) Scaler Register 0 */ +#define REG_AC_SCALER1 (*(RwReg8 *)0x42004421U) /**< \brief (AC) Scaler Register 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for AC peripheral ========== */ +#define AC_GCLK_ID_ANA 25 +#define AC_GCLK_ID_DIG 24 +#define AC_NUM_CMP 2 +#define AC_PAIRS 1 + +#endif /* _SAMD20_AC_INSTANCE_ */
diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_adc.h b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_adc.h new file mode 100644 index 0000000..423c767 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_adc.h
@@ -0,0 +1,103 @@ +/** + * \file + * + * \brief Instance description for ADC + * + * Copyright (c) 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD20_ADC_INSTANCE_ +#define _SAMD20_ADC_INSTANCE_ + +/* ========== Register definition for ADC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_ADC_CTRLA (0x42004000U) /**< \brief (ADC) Control Register A */ +#define REG_ADC_REFCTRL (0x42004001U) /**< \brief (ADC) Reference Control Register */ +#define REG_ADC_AVGCTRL (0x42004002U) /**< \brief (ADC) Average Control Register */ +#define REG_ADC_SAMPCTRL (0x42004003U) /**< \brief (ADC) Sample Time Control Register */ +#define REG_ADC_CTRLB (0x42004004U) /**< \brief (ADC) Control Register B */ +#define REG_ADC_WINCTRL (0x42004008U) /**< \brief (ADC) Window Monitor Control Register */ +#define REG_ADC_SWTRIG (0x4200400CU) /**< \brief (ADC) Control Register B */ +#define REG_ADC_INPUTCTRL (0x42004010U) /**< \brief (ADC) Input Control Register */ +#define REG_ADC_EVCTRL (0x42004014U) /**< \brief (ADC) Event Control Register */ +#define REG_ADC_INTENCLR (0x42004016U) /**< \brief (ADC) Interrupt Enable Clear Register */ +#define REG_ADC_INTENSET (0x42004017U) /**< \brief (ADC) Interrupt Enable Set Register */ +#define REG_ADC_INTFLAG (0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear Register */ +#define REG_ADC_STATUS (0x42004019U) /**< \brief (ADC) Status Register */ +#define REG_ADC_RESULT (0x4200401AU) /**< \brief (ADC) Result Register */ +#define REG_ADC_WINLT (0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold Register */ +#define REG_ADC_WINUT (0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold Register */ +#define REG_ADC_GAINCORR (0x42004024U) /**< \brief (ADC) Gain Correction Register */ +#define REG_ADC_OFFSETCORR (0x42004026U) /**< \brief (ADC) Offset Correction Register */ +#define REG_ADC_CALIB (0x42004028U) /**< \brief (ADC) Calibration Register */ +#define REG_ADC_DBGCTRL (0x4200402AU) /**< \brief (ADC) Debug Register */ +#define REG_ADC_TEST (0x4200402BU) /**< \brief (ADC) Test Modes Register */ +#define REG_ADC_TESTRESULT (0x4200402CU) /**< \brief (ADC) Test Result Register */ +#define REG_ADC_DCFG (0x42004030U) /**< \brief (ADC) Device Configuration */ +#else +#define REG_ADC_CTRLA (*(RwReg8 *)0x42004000U) /**< \brief (ADC) Control Register A */ +#define REG_ADC_REFCTRL (*(RwReg8 *)0x42004001U) /**< \brief (ADC) Reference Control Register */ +#define REG_ADC_AVGCTRL (*(RwReg8 *)0x42004002U) /**< \brief (ADC) Average Control Register */ +#define REG_ADC_SAMPCTRL (*(RwReg8 *)0x42004003U) /**< \brief (ADC) Sample Time Control Register */ +#define REG_ADC_CTRLB (*(RwReg16*)0x42004004U) /**< \brief (ADC) Control Register B */ +#define REG_ADC_WINCTRL (*(RwReg8 *)0x42004008U) /**< \brief (ADC) Window Monitor Control Register */ +#define REG_ADC_SWTRIG (*(RwReg8 *)0x4200400CU) /**< \brief (ADC) Control Register B */ +#define REG_ADC_INPUTCTRL (*(RwReg *)0x42004010U) /**< \brief (ADC) Input Control Register */ +#define REG_ADC_EVCTRL (*(RwReg8 *)0x42004014U) /**< \brief (ADC) Event Control Register */ +#define REG_ADC_INTENCLR (*(RwReg8 *)0x42004016U) /**< \brief (ADC) Interrupt Enable Clear Register */ +#define REG_ADC_INTENSET (*(RwReg8 *)0x42004017U) /**< \brief (ADC) Interrupt Enable Set Register */ +#define REG_ADC_INTFLAG (*(RwReg8 *)0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear Register */ +#define REG_ADC_STATUS (*(RoReg8 *)0x42004019U) /**< \brief (ADC) Status Register */ +#define REG_ADC_RESULT (*(RoReg16*)0x4200401AU) /**< \brief (ADC) Result Register */ +#define REG_ADC_WINLT (*(RwReg16*)0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold Register */ +#define REG_ADC_WINUT (*(RwReg16*)0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold Register */ +#define REG_ADC_GAINCORR (*(RwReg16*)0x42004024U) /**< \brief (ADC) Gain Correction Register */ +#define REG_ADC_OFFSETCORR (*(RwReg16*)0x42004026U) /**< \brief (ADC) Offset Correction Register */ +#define REG_ADC_CALIB (*(RwReg16*)0x42004028U) /**< \brief (ADC) Calibration Register */ +#define REG_ADC_DBGCTRL (*(RwReg8 *)0x4200402AU) /**< \brief (ADC) Debug Register */ +#define REG_ADC_TEST (*(RwReg8 *)0x4200402BU) /**< \brief (ADC) Test Modes Register */ +#define REG_ADC_TESTRESULT (*(RwReg *)0x4200402CU) /**< \brief (ADC) Test Result Register */ +#define REG_ADC_DCFG (*(RwReg8 *)0x42004030U) /**< \brief (ADC) Device Configuration */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for ADC peripheral ========== */ +#define ADC_EXTCHANNEL_MSB 19 +#define ADC_GCLK_ID 23 +#define ADC_RESULT_MSB 15 + +#endif /* _SAMD20_ADC_INSTANCE_ */
diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_dac.h b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_dac.h new file mode 100644 index 0000000..b006b1e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_dac.h
@@ -0,0 +1,75 @@ +/** + * \file + * + * \brief Instance description for DAC + * + * Copyright (c) 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD20_DAC_INSTANCE_ +#define _SAMD20_DAC_INSTANCE_ + +/* ========== Register definition for DAC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_DAC_CTRLA (0x42004800U) /**< \brief (DAC) Control Register A */ +#define REG_DAC_CTRLB (0x42004801U) /**< \brief (DAC) Control Register B */ +#define REG_DAC_EVCTRL (0x42004802U) /**< \brief (DAC) Event Control Register */ +#define REG_DAC_TEST (0x42004803U) /**< \brief (DAC) Test Register */ +#define REG_DAC_INTENCLR (0x42004804U) /**< \brief (DAC) Interrupt Enable Clear Register */ +#define REG_DAC_INTENSET (0x42004805U) /**< \brief (DAC) Interrupt Enable Set Register */ +#define REG_DAC_INTFLAG (0x42004806U) /**< \brief (DAC) Interrupt Flag Status and Clear Register */ +#define REG_DAC_STATUS (0x42004807U) /**< \brief (DAC) Status Register */ +#define REG_DAC_DATA (0x42004808U) /**< \brief (DAC) Data Register */ +#define REG_DAC_DATABUF (0x4200480CU) /**< \brief (DAC) Data Buffer Register */ +#else +#define REG_DAC_CTRLA (*(RwReg8 *)0x42004800U) /**< \brief (DAC) Control Register A */ +#define REG_DAC_CTRLB (*(RwReg8 *)0x42004801U) /**< \brief (DAC) Control Register B */ +#define REG_DAC_EVCTRL (*(RwReg8 *)0x42004802U) /**< \brief (DAC) Event Control Register */ +#define REG_DAC_TEST (*(RwReg8 *)0x42004803U) /**< \brief (DAC) Test Register */ +#define REG_DAC_INTENCLR (*(RwReg8 *)0x42004804U) /**< \brief (DAC) Interrupt Enable Clear Register */ +#define REG_DAC_INTENSET (*(RwReg8 *)0x42004805U) /**< \brief (DAC) Interrupt Enable Set Register */ +#define REG_DAC_INTFLAG (*(RwReg8 *)0x42004806U) /**< \brief (DAC) Interrupt Flag Status and Clear Register */ +#define REG_DAC_STATUS (*(RoReg8 *)0x42004807U) /**< \brief (DAC) Status Register */ +#define REG_DAC_DATA (*(RwReg16*)0x42004808U) /**< \brief (DAC) Data Register */ +#define REG_DAC_DATABUF (*(RwReg16*)0x4200480CU) /**< \brief (DAC) Data Buffer Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for DAC peripheral ========== */ +#define DAC_GCLK_ID 26 + +#endif /* _SAMD20_DAC_INSTANCE_ */
diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_dsu.h b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_dsu.h new file mode 100644 index 0000000..01ca63a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_dsu.h
@@ -0,0 +1,113 @@ +/** + * \file + * + * \brief Instance description for DSU + * + * Copyright (c) 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD20_DSU_INSTANCE_ +#define _SAMD20_DSU_INSTANCE_ + +/* ========== Register definition for DSU peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_DSU_CTRL (0x41002000U) /**< \brief (DSU) Control Register */ +#define REG_DSU_STATUSA (0x41002001U) /**< \brief (DSU) Status Register A */ +#define REG_DSU_STATUSB (0x41002002U) /**< \brief (DSU) Status Register B */ +#define REG_DSU_ADDR (0x41002004U) /**< \brief (DSU) Address Register */ +#define REG_DSU_LENGTH (0x41002008U) /**< \brief (DSU) Length Register */ +#define REG_DSU_DATA (0x4100200CU) /**< \brief (DSU) Data Register */ +#define REG_DSU_DCC0 (0x41002010U) /**< \brief (DSU) Debug Communication Channel Register 0 */ +#define REG_DSU_DCC1 (0x41002014U) /**< \brief (DSU) Debug Communication Channel Register 1 */ +#define REG_DSU_DID (0x41002018U) /**< \brief (DSU) Device Identification Register */ +#define REG_DSU_DCFG0 (0x410020F0U) /**< \brief (DSU) Device Configuration Register 0 */ +#define REG_DSU_DCFG1 (0x410020F4U) /**< \brief (DSU) Device Configuration Register 1 */ +#define REG_DSU_UPTM (0x410020F8U) /**< \brief (DSU) UnProtected Test Mode Register */ +#define REG_DSU_TESTMODE (0x410020FCU) /**< \brief (DSU) Test Mode Register */ +#define REG_DSU_ENTRY0 (0x41003000U) /**< \brief (DSU) CoreSight ROM Table Entry Register 0 */ +#define REG_DSU_ENTRY1 (0x41003004U) /**< \brief (DSU) CoreSight ROM Table Entry Register 1 */ +#define REG_DSU_END (0x41003008U) /**< \brief (DSU) CoreSight ROM Table End Register */ +#define REG_DSU_MEMTYPE (0x41003FCCU) /**< \brief (DSU) CoreSight ROM Table Memory Type Register */ +#define REG_DSU_PID4 (0x41003FD0U) /**< \brief (DSU) Peripheral Identification Register 4 */ +#define REG_DSU_PID5 (0x41003FD4U) /**< \brief (DSU) Peripheral Identification Register 5 */ +#define REG_DSU_PID6 (0x41003FD8U) /**< \brief (DSU) Peripheral Identification Register 6 */ +#define REG_DSU_PID7 (0x41003FDCU) /**< \brief (DSU) Peripheral Identification Register 7 */ +#define REG_DSU_PID0 (0x41003FE0U) /**< \brief (DSU) Peripheral Identification Register 0 */ +#define REG_DSU_PID1 (0x41003FE4U) /**< \brief (DSU) Peripheral Identification Register 1 */ +#define REG_DSU_PID2 (0x41003FE8U) /**< \brief (DSU) Peripheral Identification Register 2 */ +#define REG_DSU_PID3 (0x41003FECU) /**< \brief (DSU) Peripheral Identification Register 3 */ +#define REG_DSU_CID0 (0x41003FF0U) /**< \brief (DSU) Component Identification Register 0 */ +#define REG_DSU_CID1 (0x41003FF4U) /**< \brief (DSU) Component Identification Register 1 */ +#define REG_DSU_CID2 (0x41003FF8U) /**< \brief (DSU) Component Identification Register 2 */ +#define REG_DSU_CID3 (0x41003FFCU) /**< \brief (DSU) Component Identification Register 3 */ +#else +#define REG_DSU_CTRL (*(WoReg8 *)0x41002000U) /**< \brief (DSU) Control Register */ +#define REG_DSU_STATUSA (*(RwReg8 *)0x41002001U) /**< \brief (DSU) Status Register A */ +#define REG_DSU_STATUSB (*(RoReg8 *)0x41002002U) /**< \brief (DSU) Status Register B */ +#define REG_DSU_ADDR (*(RwReg *)0x41002004U) /**< \brief (DSU) Address Register */ +#define REG_DSU_LENGTH (*(RwReg *)0x41002008U) /**< \brief (DSU) Length Register */ +#define REG_DSU_DATA (*(RwReg *)0x4100200CU) /**< \brief (DSU) Data Register */ +#define REG_DSU_DCC0 (*(RwReg *)0x41002010U) /**< \brief (DSU) Debug Communication Channel Register 0 */ +#define REG_DSU_DCC1 (*(RwReg *)0x41002014U) /**< \brief (DSU) Debug Communication Channel Register 1 */ +#define REG_DSU_DID (*(RoReg *)0x41002018U) /**< \brief (DSU) Device Identification Register */ +#define REG_DSU_DCFG0 (*(RwReg *)0x410020F0U) /**< \brief (DSU) Device Configuration Register 0 */ +#define REG_DSU_DCFG1 (*(RwReg *)0x410020F4U) /**< \brief (DSU) Device Configuration Register 1 */ +#define REG_DSU_UPTM (*(RwReg *)0x410020F8U) /**< \brief (DSU) UnProtected Test Mode Register */ +#define REG_DSU_TESTMODE (*(RwReg *)0x410020FCU) /**< \brief (DSU) Test Mode Register */ +#define REG_DSU_ENTRY0 (*(RoReg *)0x41003000U) /**< \brief (DSU) CoreSight ROM Table Entry Register 0 */ +#define REG_DSU_ENTRY1 (*(RoReg *)0x41003004U) /**< \brief (DSU) CoreSight ROM Table Entry Register 1 */ +#define REG_DSU_END (*(RoReg *)0x41003008U) /**< \brief (DSU) CoreSight ROM Table End Register */ +#define REG_DSU_MEMTYPE (*(RoReg *)0x41003FCCU) /**< \brief (DSU) CoreSight ROM Table Memory Type Register */ +#define REG_DSU_PID4 (*(RoReg *)0x41003FD0U) /**< \brief (DSU) Peripheral Identification Register 4 */ +#define REG_DSU_PID5 (*(RoReg *)0x41003FD4U) /**< \brief (DSU) Peripheral Identification Register 5 */ +#define REG_DSU_PID6 (*(RoReg *)0x41003FD8U) /**< \brief (DSU) Peripheral Identification Register 6 */ +#define REG_DSU_PID7 (*(RoReg *)0x41003FDCU) /**< \brief (DSU) Peripheral Identification Register 7 */ +#define REG_DSU_PID0 (*(RoReg *)0x41003FE0U) /**< \brief (DSU) Peripheral Identification Register 0 */ +#define REG_DSU_PID1 (*(RoReg *)0x41003FE4U) /**< \brief (DSU) Peripheral Identification Register 1 */ +#define REG_DSU_PID2 (*(RoReg *)0x41003FE8U) /**< \brief (DSU) Peripheral Identification Register 2 */ +#define REG_DSU_PID3 (*(RoReg *)0x41003FECU) /**< \brief (DSU) Peripheral Identification Register 3 */ +#define REG_DSU_CID0 (*(RoReg *)0x41003FF0U) /**< \brief (DSU) Component Identification Register 0 */ +#define REG_DSU_CID1 (*(RoReg *)0x41003FF4U) /**< \brief (DSU) Component Identification Register 1 */ +#define REG_DSU_CID2 (*(RoReg *)0x41003FF8U) /**< \brief (DSU) Component Identification Register 2 */ +#define REG_DSU_CID3 (*(RoReg *)0x41003FFCU) /**< \brief (DSU) Component Identification Register 3 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for DSU peripheral ========== */ +#define DSU_CLK_HSB_ID 3 + +#endif /* _SAMD20_DSU_INSTANCE_ */
diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_eic.h b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_eic.h new file mode 100644 index 0000000..14bd4c7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_eic.h
@@ -0,0 +1,80 @@ +/** + * \file + * + * \brief Instance description for EIC + * + * Copyright (c) 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD20_EIC_INSTANCE_ +#define _SAMD20_EIC_INSTANCE_ + +/* ========== Register definition for EIC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_EIC_CTRL (0x40001800U) /**< \brief (EIC) Control Register */ +#define REG_EIC_STATUS (0x40001801U) /**< \brief (EIC) Status Register */ +#define REG_EIC_NMICTRL (0x40001802U) /**< \brief (EIC) NMI Control Register */ +#define REG_EIC_NMIFLAG (0x40001803U) /**< \brief (EIC) NMI Interrupt Flag Register */ +#define REG_EIC_EVCTRL (0x40001804U) /**< \brief (EIC) Event Control Register */ +#define REG_EIC_INTENCLR (0x40001808U) /**< \brief (EIC) Interrupt Enable Clear Register */ +#define REG_EIC_INTENSET (0x4000180CU) /**< \brief (EIC) Interrupt Enable Set Register */ +#define REG_EIC_INTFLAG (0x40001810U) /**< \brief (EIC) Interrupt Flag Status and Clear Register */ +#define REG_EIC_WAKEUP (0x40001814U) /**< \brief (EIC) Wake-up Enable Register */ +#define REG_EIC_CONFIG0 (0x40001818U) /**< \brief (EIC) Config Register 0 */ +#define REG_EIC_CONFIG1 (0x4000181CU) /**< \brief (EIC) Config Register 1 */ +#else +#define REG_EIC_CTRL (*(RwReg8 *)0x40001800U) /**< \brief (EIC) Control Register */ +#define REG_EIC_STATUS (*(RoReg8 *)0x40001801U) /**< \brief (EIC) Status Register */ +#define REG_EIC_NMICTRL (*(RwReg8 *)0x40001802U) /**< \brief (EIC) NMI Control Register */ +#define REG_EIC_NMIFLAG (*(RwReg8 *)0x40001803U) /**< \brief (EIC) NMI Interrupt Flag Register */ +#define REG_EIC_EVCTRL (*(RwReg *)0x40001804U) /**< \brief (EIC) Event Control Register */ +#define REG_EIC_INTENCLR (*(RwReg *)0x40001808U) /**< \brief (EIC) Interrupt Enable Clear Register */ +#define REG_EIC_INTENSET (*(RwReg *)0x4000180CU) /**< \brief (EIC) Interrupt Enable Set Register */ +#define REG_EIC_INTFLAG (*(RwReg *)0x40001810U) /**< \brief (EIC) Interrupt Flag Status and Clear Register */ +#define REG_EIC_WAKEUP (*(RwReg *)0x40001814U) /**< \brief (EIC) Wake-up Enable Register */ +#define REG_EIC_CONFIG0 (*(RwReg *)0x40001818U) /**< \brief (EIC) Config Register 0 */ +#define REG_EIC_CONFIG1 (*(RwReg *)0x4000181CU) /**< \brief (EIC) Config Register 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for EIC peripheral ========== */ +#define EIC_GCLK_ID 3 +#define EIC_NMI_NO_DETECT_ALLOWED 0 +#define EIC_NUMBER_OF_CONFIG_REGS 2 +#define EIC_NUMBER_OF_INTERRUPTS 16 + +#endif /* _SAMD20_EIC_INSTANCE_ */
diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_evsys.h b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_evsys.h new file mode 100644 index 0000000..81a177f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_evsys.h
@@ -0,0 +1,161 @@ +/** + * \file + * + * \brief Instance description for EVSYS + * + * Copyright (c) 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD20_EVSYS_INSTANCE_ +#define _SAMD20_EVSYS_INSTANCE_ + +/* ========== Register definition for EVSYS peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_EVSYS_CTRL (0x42000400U) /**< \brief (EVSYS) Control Register */ +#define REG_EVSYS_CHANNEL (0x42000404U) /**< \brief (EVSYS) Channel Register */ +#define REG_EVSYS_USER (0x42000408U) /**< \brief (EVSYS) User Mux Register */ +#define REG_EVSYS_CHSTATUS (0x4200040CU) /**< \brief (EVSYS) Channel Status Register */ +#define REG_EVSYS_INTENCLR (0x42000410U) /**< \brief (EVSYS) Interrupt Enable Clear Register */ +#define REG_EVSYS_INTENSET (0x42000414U) /**< \brief (EVSYS) Interrupt Enable Set Register */ +#define REG_EVSYS_INTFLAG (0x42000418U) /**< \brief (EVSYS) Interrupt Flag Status and Clear Register */ +#else +#define REG_EVSYS_CTRL (*(WoReg8 *)0x42000400U) /**< \brief (EVSYS) Control Register */ +#define REG_EVSYS_CHANNEL (*(RwReg *)0x42000404U) /**< \brief (EVSYS) Channel Register */ +#define REG_EVSYS_USER (*(RwReg16*)0x42000408U) /**< \brief (EVSYS) User Mux Register */ +#define REG_EVSYS_CHSTATUS (*(RoReg *)0x4200040CU) /**< \brief (EVSYS) Channel Status Register */ +#define REG_EVSYS_INTENCLR (*(RwReg *)0x42000410U) /**< \brief (EVSYS) Interrupt Enable Clear Register */ +#define REG_EVSYS_INTENSET (*(RwReg *)0x42000414U) /**< \brief (EVSYS) Interrupt Enable Set Register */ +#define REG_EVSYS_INTFLAG (*(RwReg *)0x42000418U) /**< \brief (EVSYS) Interrupt Flag Status and Clear Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for EVSYS peripheral ========== */ +#define EVSYS_CHANNELS 8 +#define EVSYS_CHANNELS_MSB 7 +#define EVSYS_EXT_EVT_MSB 0 +#define EVSYS_GCLK_ID_0 4 +#define EVSYS_GCLK_ID_1 5 +#define EVSYS_GCLK_ID_2 6 +#define EVSYS_GCLK_ID_3 7 +#define EVSYS_GCLK_ID_4 8 +#define EVSYS_GCLK_ID_5 9 +#define EVSYS_GCLK_ID_6 10 +#define EVSYS_GCLK_ID_7 11 +#define EVSYS_GCLK_ID_LSB 4 +#define EVSYS_GCLK_ID_MSB 11 +#define EVSYS_GCLK_ID_SIZE 8 +#define EVSYS_GENERATORS 49 +#define EVSYS_USERS 14 + +// GENERATORS +#define EVSYS_ID_GEN_RTC_CMP_0 1 +#define EVSYS_ID_GEN_RTC_CMP_1 2 +#define EVSYS_ID_GEN_RTC_OVF 3 +#define EVSYS_ID_GEN_RTC_PER_0 4 +#define EVSYS_ID_GEN_RTC_PER_1 5 +#define EVSYS_ID_GEN_RTC_PER_2 6 +#define EVSYS_ID_GEN_RTC_PER_3 7 +#define EVSYS_ID_GEN_RTC_PER_4 8 +#define EVSYS_ID_GEN_RTC_PER_5 9 +#define EVSYS_ID_GEN_RTC_PER_6 10 +#define EVSYS_ID_GEN_RTC_PER_7 11 +#define EVSYS_ID_GEN_EIC_EXTINT_0 12 +#define EVSYS_ID_GEN_EIC_EXTINT_1 13 +#define EVSYS_ID_GEN_EIC_EXTINT_2 14 +#define EVSYS_ID_GEN_EIC_EXTINT_3 15 +#define EVSYS_ID_GEN_EIC_EXTINT_4 16 +#define EVSYS_ID_GEN_EIC_EXTINT_5 17 +#define EVSYS_ID_GEN_EIC_EXTINT_6 18 +#define EVSYS_ID_GEN_EIC_EXTINT_7 19 +#define EVSYS_ID_GEN_EIC_EXTINT_8 20 +#define EVSYS_ID_GEN_EIC_EXTINT_9 21 +#define EVSYS_ID_GEN_EIC_EXTINT_10 22 +#define EVSYS_ID_GEN_EIC_EXTINT_11 23 +#define EVSYS_ID_GEN_EIC_EXTINT_12 24 +#define EVSYS_ID_GEN_EIC_EXTINT_13 25 +#define EVSYS_ID_GEN_EIC_EXTINT_14 26 +#define EVSYS_ID_GEN_EIC_EXTINT_15 27 +#define EVSYS_ID_GEN_TC0_OVF 28 +#define EVSYS_ID_GEN_TC0_MCX_0 29 +#define EVSYS_ID_GEN_TC0_MCX_1 30 +#define EVSYS_ID_GEN_TC1_OVF 31 +#define EVSYS_ID_GEN_TC1_MCX_0 32 +#define EVSYS_ID_GEN_TC1_MCX_1 33 +#define EVSYS_ID_GEN_TC2_OVF 34 +#define EVSYS_ID_GEN_TC2_MCX_0 35 +#define EVSYS_ID_GEN_TC2_MCX_1 36 +#define EVSYS_ID_GEN_TC3_OVF 37 +#define EVSYS_ID_GEN_TC3_MCX_0 38 +#define EVSYS_ID_GEN_TC3_MCX_1 39 +#define EVSYS_ID_GEN_TC4_OVF 40 +#define EVSYS_ID_GEN_TC4_MCX_0 41 +#define EVSYS_ID_GEN_TC4_MCX_1 42 +#define EVSYS_ID_GEN_TC5_OVF 43 +#define EVSYS_ID_GEN_TC5_MCX_0 44 +#define EVSYS_ID_GEN_TC5_MCX_1 45 +#define EVSYS_ID_GEN_TC6_OVF 46 +#define EVSYS_ID_GEN_TC6_MCX_0 47 +#define EVSYS_ID_GEN_TC6_MCX_1 48 +#define EVSYS_ID_GEN_TC7_OVF 49 +#define EVSYS_ID_GEN_TC7_MCX_0 50 +#define EVSYS_ID_GEN_TC7_MCX_1 51 +#define EVSYS_ID_GEN_ADC_RESRDY 52 +#define EVSYS_ID_GEN_ADC_WINMON 53 +#define EVSYS_ID_GEN_AC_COMP_0 54 +#define EVSYS_ID_GEN_AC_COMP_1 55 +#define EVSYS_ID_GEN_AC_WIN 56 +#define EVSYS_ID_GEN_DAC_EMPTY 57 +#define EVSYS_ID_GEN_PTC_EOC 58 +#define EVSYS_ID_GEN_PTC_WCOMP 59 + +// USERS +#define EVSYS_ID_USER_TC0_EVU 0 +#define EVSYS_ID_USER_TC1_EVU 1 +#define EVSYS_ID_USER_TC2_EVU 2 +#define EVSYS_ID_USER_TC3_EVU 3 +#define EVSYS_ID_USER_TC4_EVU 4 +#define EVSYS_ID_USER_TC5_EVU 5 +#define EVSYS_ID_USER_TC6_EVU 6 +#define EVSYS_ID_USER_TC7_EVU 7 +#define EVSYS_ID_USER_ADC_START 8 +#define EVSYS_ID_USER_ADC_SYNC 9 +#define EVSYS_ID_USER_AC_SOC_0 10 +#define EVSYS_ID_USER_AC_SOC_1 11 +#define EVSYS_ID_USER_DAC_START 12 +#define EVSYS_ID_USER_PTC_STCONV 13 + +#endif /* _SAMD20_EVSYS_INSTANCE_ */
diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_gclk.h b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_gclk.h new file mode 100644 index 0000000..dba56c1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_gclk.h
@@ -0,0 +1,76 @@ +/** + * \file + * + * \brief Instance description for GCLK + * + * Copyright (c) 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD20_GCLK_INSTANCE_ +#define _SAMD20_GCLK_INSTANCE_ + +/* ========== Register definition for GCLK peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_GCLK_CTRL (0x40000C00U) /**< \brief (GCLK) Control Register */ +#define REG_GCLK_STATUS (0x40000C01U) /**< \brief (GCLK) Status Register */ +#define REG_GCLK_CLKCTRL (0x40000C02U) /**< \brief (GCLK) Generic Clock Control Register */ +#define REG_GCLK_GENCTRL (0x40000C04U) /**< \brief (GCLK) Generic Clock Generator Control Register */ +#define REG_GCLK_GENDIV (0x40000C08U) /**< \brief (GCLK) Generic Clock Generator Division Register */ +#else +#define REG_GCLK_CTRL (*(RwReg8 *)0x40000C00U) /**< \brief (GCLK) Control Register */ +#define REG_GCLK_STATUS (*(RoReg8 *)0x40000C01U) /**< \brief (GCLK) Status Register */ +#define REG_GCLK_CLKCTRL (*(RwReg16*)0x40000C02U) /**< \brief (GCLK) Generic Clock Control Register */ +#define REG_GCLK_GENCTRL (*(RwReg *)0x40000C04U) /**< \brief (GCLK) Generic Clock Generator Control Register */ +#define REG_GCLK_GENDIV (*(RwReg *)0x40000C08U) /**< \brief (GCLK) Generic Clock Generator Division Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for GCLK peripheral ========== */ +#define GCLK_GEN_NUM_MSB 7 +#define GCLK_GEN_SOURCE_NUM_MSB 7 +#define GCLK_MAX_DIV_BITS 16 +#define GCLK_NUM 28 +#define GCLK_SOURCE_DFLL48M 7 +#define GCLK_SOURCE_GCLKGEN1 2 +#define GCLK_SOURCE_GCLKIN 1 +#define GCLK_SOURCE_OSCULP32K 3 +#define GCLK_SOURCE_OSC8M 6 +#define GCLK_SOURCE_OSC32K 4 +#define GCLK_SOURCE_XOSC 0 +#define GCLK_SOURCE_XOSC32K 5 + +#endif /* _SAMD20_GCLK_INSTANCE_ */
diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_nvmctrl.h b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_nvmctrl.h new file mode 100644 index 0000000..7852e76 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_nvmctrl.h
@@ -0,0 +1,94 @@ +/** + * \file + * + * \brief Instance description for NVMCTRL + * + * Copyright (c) 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD20_NVMCTRL_INSTANCE_ +#define _SAMD20_NVMCTRL_INSTANCE_ + +/* ========== Register definition for NVMCTRL peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_NVMCTRL_CTRLA (0x41004000U) /**< \brief (NVMCTRL) NVM Control Register A */ +#define REG_NVMCTRL_CTRLB (0x41004004U) /**< \brief (NVMCTRL) NVM Control Register B */ +#define REG_NVMCTRL_PARAM (0x41004008U) /**< \brief (NVMCTRL) Parameter Register */ +#define REG_NVMCTRL_INTENCLR (0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear Register */ +#define REG_NVMCTRL_INTENSET (0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set Register */ +#define REG_NVMCTRL_INTFLAG (0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear Register */ +#define REG_NVMCTRL_STATUS (0x41004018U) /**< \brief (NVMCTRL) Status Register */ +#define REG_NVMCTRL_ADDR (0x4100401CU) /**< \brief (NVMCTRL) Address Register */ +#define REG_NVMCTRL_LOCK (0x41004020U) /**< \brief (NVMCTRL) Lock Register */ +#else +#define REG_NVMCTRL_CTRLA (*(RwReg16*)0x41004000U) /**< \brief (NVMCTRL) NVM Control Register A */ +#define REG_NVMCTRL_CTRLB (*(RwReg *)0x41004004U) /**< \brief (NVMCTRL) NVM Control Register B */ +#define REG_NVMCTRL_PARAM (*(RwReg *)0x41004008U) /**< \brief (NVMCTRL) Parameter Register */ +#define REG_NVMCTRL_INTENCLR (*(RwReg8 *)0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear Register */ +#define REG_NVMCTRL_INTENSET (*(RwReg8 *)0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set Register */ +#define REG_NVMCTRL_INTFLAG (*(RwReg8 *)0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear Register */ +#define REG_NVMCTRL_STATUS (*(RwReg16*)0x41004018U) /**< \brief (NVMCTRL) Status Register */ +#define REG_NVMCTRL_ADDR (*(RwReg *)0x4100401CU) /**< \brief (NVMCTRL) Address Register */ +#define REG_NVMCTRL_LOCK (*(RwReg16*)0x41004020U) /**< \brief (NVMCTRL) Lock Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for NVMCTRL peripheral ========== */ +#define NVMCTRL_AUX0_ADDRESS (NVMCTRL_USER_PAGE_ADDRESS + 0x00004000) +#define NVMCTRL_AUX1_ADDRESS (NVMCTRL_USER_PAGE_ADDRESS + 0x00006000) +#define NVMCTRL_AUX2_ADDRESS (NVMCTRL_USER_PAGE_ADDRESS + 0x00008000) +#define NVMCTRL_AUX3_ADDRESS (NVMCTRL_USER_PAGE_ADDRESS + 0x0000A000) +#define NVMCTRL_CLK_AHB_ID 4 +#define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0XC0000007FFFFFFFF +#define NVMCTRL_FLASH_SIZE (NVMCTRL_PAGES*NVMCTRL_PAGE_SIZE) +#define NVMCTRL_FUSES_SECURE_NVM +#define NVMCTRL_FUSES_SECURE_RAM +#define NVMCTRL_FUSES_SECURE_STATE +#define NVMCTRL_LOCKBIT_ADDRESS (NVMCTRL_USER_PAGE_ADDRESS + 0x00002000) +#define NVMCTRL_PAGES 4096 +#define NVMCTRL_PAGE_HW (NVMCTRL_PAGE_SIZE/2) +#define NVMCTRL_PAGE_SIZE (1<<NVMCTRL_PSZ_BITS) +#define NVMCTRL_PAGE_W (NVMCTRL_PAGE_SIZE/4) +#define NVMCTRL_PMSB 3 +#define NVMCTRL_PSZ_BITS 6 +#define NVMCTRL_ROW_PAGES (NVMCTRL_ROW_SIZE/NVMCTRL_PAGE_SIZE) +#define NVMCTRL_ROW_SIZE (NVMCTRL_PAGE_SIZE*4) +#define NVMCTRL_USER_PAGE_ADDRESS (FLASH_ADDR + NVMCTRL_USER_PAGE_OFFSET) +#define NVMCTRL_USER_PAGE_OFFSET 0x00800000 +#define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0XC01FFFFFFFFFFFFF + +#endif /* _SAMD20_NVMCTRL_INSTANCE_ */
diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_pac0.h b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_pac0.h new file mode 100644 index 0000000..96b74dc --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_pac0.h
@@ -0,0 +1,59 @@ +/** + * \file + * + * \brief Instance description for PAC0 + * + * Copyright (c) 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD20_PAC0_INSTANCE_ +#define _SAMD20_PAC0_INSTANCE_ + +/* ========== Register definition for PAC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PAC0_WPCLR (0x40000000U) /**< \brief (PAC0) Write Protection Clear Register */ +#define REG_PAC0_WPSET (0x40000004U) /**< \brief (PAC0) Write Protection Set Register */ +#else +#define REG_PAC0_WPCLR (*(RwReg *)0x40000000U) /**< \brief (PAC0) Write Protection Clear Register */ +#define REG_PAC0_WPSET (*(RwReg *)0x40000004U) /**< \brief (PAC0) Write Protection Set Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for PAC0 peripheral ========== */ +#define PAC0_WPROT_DEFAULT_VAL 0x00000000 + +#endif /* _SAMD20_PAC0_INSTANCE_ */
diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_pac1.h b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_pac1.h new file mode 100644 index 0000000..1455ba2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_pac1.h
@@ -0,0 +1,59 @@ +/** + * \file + * + * \brief Instance description for PAC1 + * + * Copyright (c) 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD20_PAC1_INSTANCE_ +#define _SAMD20_PAC1_INSTANCE_ + +/* ========== Register definition for PAC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PAC1_WPCLR (0x41000000U) /**< \brief (PAC1) Write Protection Clear Register */ +#define REG_PAC1_WPSET (0x41000004U) /**< \brief (PAC1) Write Protection Set Register */ +#else +#define REG_PAC1_WPCLR (*(RwReg *)0x41000000U) /**< \brief (PAC1) Write Protection Clear Register */ +#define REG_PAC1_WPSET (*(RwReg *)0x41000004U) /**< \brief (PAC1) Write Protection Set Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for PAC1 peripheral ========== */ +#define PAC1_WPROT_DEFAULT_VAL 0x00000002 + +#endif /* _SAMD20_PAC1_INSTANCE_ */
diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_pac2.h b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_pac2.h new file mode 100644 index 0000000..1c120f3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_pac2.h
@@ -0,0 +1,59 @@ +/** + * \file + * + * \brief Instance description for PAC2 + * + * Copyright (c) 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD20_PAC2_INSTANCE_ +#define _SAMD20_PAC2_INSTANCE_ + +/* ========== Register definition for PAC2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PAC2_WPCLR (0x42000000U) /**< \brief (PAC2) Write Protection Clear Register */ +#define REG_PAC2_WPSET (0x42000004U) /**< \brief (PAC2) Write Protection Set Register */ +#else +#define REG_PAC2_WPCLR (*(RwReg *)0x42000000U) /**< \brief (PAC2) Write Protection Clear Register */ +#define REG_PAC2_WPSET (*(RwReg *)0x42000004U) /**< \brief (PAC2) Write Protection Set Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for PAC2 peripheral ========== */ +#define PAC2_WPROT_DEFAULT_VAL 0x00100000 + +#endif /* _SAMD20_PAC2_INSTANCE_ */
diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_pm.h b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_pm.h new file mode 100644 index 0000000..7a2c1ab --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_pm.h
@@ -0,0 +1,87 @@ +/** + * \file + * + * \brief Instance description for PM + * + * Copyright (c) 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD20_PM_INSTANCE_ +#define _SAMD20_PM_INSTANCE_ + +/* ========== Register definition for PM peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PM_CTRL (0x40000400U) /**< \brief (PM) Control Register */ +#define REG_PM_SLEEP (0x40000401U) /**< \brief (PM) Sleep Register */ +#define REG_PM_CPUSEL (0x40000408U) /**< \brief (PM) CPU Clock Select */ +#define REG_PM_APBASEL (0x40000409U) /**< \brief (PM) APBA Clock Select */ +#define REG_PM_APBBSEL (0x4000040AU) /**< \brief (PM) APBB Clock Select */ +#define REG_PM_APBCSEL (0x4000040BU) /**< \brief (PM) APBC Clock Select */ +#define REG_PM_AHBMASK (0x40000414U) /**< \brief (PM) AHB Mask */ +#define REG_PM_APBAMASK (0x40000418U) /**< \brief (PM) APBA Mask */ +#define REG_PM_APBBMASK (0x4000041CU) /**< \brief (PM) APBB Mask */ +#define REG_PM_APBCMASK (0x40000420U) /**< \brief (PM) APBC Mask */ +#define REG_PM_INTENCLR (0x40000434U) /**< \brief (PM) Interrupt Enable Clear Register */ +#define REG_PM_INTENSET (0x40000435U) /**< \brief (PM) Interrupt Enable Set Register */ +#define REG_PM_INTFLAG (0x40000436U) /**< \brief (PM) Interrupt Flag Status and Clear Register */ +#define REG_PM_RCAUSE (0x40000438U) /**< \brief (PM) Reset Cause Register */ +#else +#define REG_PM_CTRL (*(RwReg8 *)0x40000400U) /**< \brief (PM) Control Register */ +#define REG_PM_SLEEP (*(RwReg8 *)0x40000401U) /**< \brief (PM) Sleep Register */ +#define REG_PM_CPUSEL (*(RwReg8 *)0x40000408U) /**< \brief (PM) CPU Clock Select */ +#define REG_PM_APBASEL (*(RwReg8 *)0x40000409U) /**< \brief (PM) APBA Clock Select */ +#define REG_PM_APBBSEL (*(RwReg8 *)0x4000040AU) /**< \brief (PM) APBB Clock Select */ +#define REG_PM_APBCSEL (*(RwReg8 *)0x4000040BU) /**< \brief (PM) APBC Clock Select */ +#define REG_PM_AHBMASK (*(RwReg *)0x40000414U) /**< \brief (PM) AHB Mask */ +#define REG_PM_APBAMASK (*(RwReg *)0x40000418U) /**< \brief (PM) APBA Mask */ +#define REG_PM_APBBMASK (*(RwReg *)0x4000041CU) /**< \brief (PM) APBB Mask */ +#define REG_PM_APBCMASK (*(RwReg *)0x40000420U) /**< \brief (PM) APBC Mask */ +#define REG_PM_INTENCLR (*(RwReg8 *)0x40000434U) /**< \brief (PM) Interrupt Enable Clear Register */ +#define REG_PM_INTENSET (*(RwReg8 *)0x40000435U) /**< \brief (PM) Interrupt Enable Set Register */ +#define REG_PM_INTFLAG (*(RwReg8 *)0x40000436U) /**< \brief (PM) Interrupt Flag Status and Clear Register */ +#define REG_PM_RCAUSE (*(RoReg8 *)0x40000438U) /**< \brief (PM) Reset Cause Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for PM peripheral ========== */ +#define PM_CTRL_MCSEL_DFLL48M 3 +#define PM_CTRL_MCSEL_GCLK 0 +#define PM_CTRL_MCSEL_OSC8M 1 +#define PM_CTRL_MCSEL_XOSC 2 +#define PM_PM_CLK_APB_NUM 2 + +#endif /* _SAMD20_PM_INSTANCE_ */
diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_port.h b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_port.h new file mode 100644 index 0000000..0be37a2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_port.h
@@ -0,0 +1,133 @@ +/** + * \file + * + * \brief Instance description for PORT + * + * Copyright (c) 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD20_PORT_INSTANCE_ +#define _SAMD20_PORT_INSTANCE_ + +/* ========== Register definition for PORT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_PORT_DIR0 (0x41004400U) /**< \brief (PORT) Data Direction Register 0 */ +#define REG_PORT_DIRCLR0 (0x41004404U) /**< \brief (PORT) Data Direction Clear Register 0 */ +#define REG_PORT_DIRSET0 (0x41004408U) /**< \brief (PORT) Data Direction Set Register 0 */ +#define REG_PORT_DIRTGL0 (0x4100440CU) /**< \brief (PORT) Data Direction Toggle Register 0 */ +#define REG_PORT_OUT0 (0x41004410U) /**< \brief (PORT) Data Output Value Register 0 */ +#define REG_PORT_OUTCLR0 (0x41004414U) /**< \brief (PORT) Data Output Value Clear Register 0 */ +#define REG_PORT_OUTSET0 (0x41004418U) /**< \brief (PORT) Data Output Value Set Register 0 */ +#define REG_PORT_OUTTGL0 (0x4100441CU) /**< \brief (PORT) Data Output Value Toggle Register 0 */ +#define REG_PORT_IN0 (0x41004420U) /**< \brief (PORT) Data Input Value Register 0 */ +#define REG_PORT_CTRL0 (0x41004424U) /**< \brief (PORT) Control Register 0 */ +#define REG_PORT_WRCONFIG0 (0x41004428U) /**< \brief (PORT) Write Configuration Register 0 */ +#define REG_PORT_PMUX0 (0x41004430U) /**< \brief (PORT) Peripheral Multiplexing Register 0 */ +#define REG_PORT_PINCFG0 (0x41004440U) /**< \brief (PORT) Pin Configuration Register 0 */ +#define REG_PORT_DIR1 (0x41004480U) /**< \brief (PORT) Data Direction Register 1 */ +#define REG_PORT_DIRCLR1 (0x41004484U) /**< \brief (PORT) Data Direction Clear Register 1 */ +#define REG_PORT_DIRSET1 (0x41004488U) /**< \brief (PORT) Data Direction Set Register 1 */ +#define REG_PORT_DIRTGL1 (0x4100448CU) /**< \brief (PORT) Data Direction Toggle Register 1 */ +#define REG_PORT_OUT1 (0x41004490U) /**< \brief (PORT) Data Output Value Register 1 */ +#define REG_PORT_OUTCLR1 (0x41004494U) /**< \brief (PORT) Data Output Value Clear Register 1 */ +#define REG_PORT_OUTSET1 (0x41004498U) /**< \brief (PORT) Data Output Value Set Register 1 */ +#define REG_PORT_OUTTGL1 (0x4100449CU) /**< \brief (PORT) Data Output Value Toggle Register 1 */ +#define REG_PORT_IN1 (0x410044A0U) /**< \brief (PORT) Data Input Value Register 1 */ +#define REG_PORT_CTRL1 (0x410044A4U) /**< \brief (PORT) Control Register 1 */ +#define REG_PORT_WRCONFIG1 (0x410044A8U) /**< \brief (PORT) Write Configuration Register 1 */ +#define REG_PORT_PMUX1 (0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing Register 1 */ +#define REG_PORT_PINCFG1 (0x410044C0U) /**< \brief (PORT) Pin Configuration Register 1 */ +#else +#define REG_PORT_DIR0 (*(RwReg *)0x41004400U) /**< \brief (PORT) Data Direction Register 0 */ +#define REG_PORT_DIRCLR0 (*(RwReg *)0x41004404U) /**< \brief (PORT) Data Direction Clear Register 0 */ +#define REG_PORT_DIRSET0 (*(RwReg *)0x41004408U) /**< \brief (PORT) Data Direction Set Register 0 */ +#define REG_PORT_DIRTGL0 (*(RwReg *)0x4100440CU) /**< \brief (PORT) Data Direction Toggle Register 0 */ +#define REG_PORT_OUT0 (*(RwReg *)0x41004410U) /**< \brief (PORT) Data Output Value Register 0 */ +#define REG_PORT_OUTCLR0 (*(RwReg *)0x41004414U) /**< \brief (PORT) Data Output Value Clear Register 0 */ +#define REG_PORT_OUTSET0 (*(RwReg *)0x41004418U) /**< \brief (PORT) Data Output Value Set Register 0 */ +#define REG_PORT_OUTTGL0 (*(RwReg *)0x4100441CU) /**< \brief (PORT) Data Output Value Toggle Register 0 */ +#define REG_PORT_IN0 (*(RoReg *)0x41004420U) /**< \brief (PORT) Data Input Value Register 0 */ +#define REG_PORT_CTRL0 (*(RwReg *)0x41004424U) /**< \brief (PORT) Control Register 0 */ +#define REG_PORT_WRCONFIG0 (*(WoReg *)0x41004428U) /**< \brief (PORT) Write Configuration Register 0 */ +#define REG_PORT_PMUX0 (*(RwReg *)0x41004430U) /**< \brief (PORT) Peripheral Multiplexing Register 0 */ +#define REG_PORT_PINCFG0 (*(RwReg *)0x41004440U) /**< \brief (PORT) Pin Configuration Register 0 */ +#define REG_PORT_DIR1 (*(RwReg *)0x41004480U) /**< \brief (PORT) Data Direction Register 1 */ +#define REG_PORT_DIRCLR1 (*(RwReg *)0x41004484U) /**< \brief (PORT) Data Direction Clear Register 1 */ +#define REG_PORT_DIRSET1 (*(RwReg *)0x41004488U) /**< \brief (PORT) Data Direction Set Register 1 */ +#define REG_PORT_DIRTGL1 (*(RwReg *)0x4100448CU) /**< \brief (PORT) Data Direction Toggle Register 1 */ +#define REG_PORT_OUT1 (*(RwReg *)0x41004490U) /**< \brief (PORT) Data Output Value Register 1 */ +#define REG_PORT_OUTCLR1 (*(RwReg *)0x41004494U) /**< \brief (PORT) Data Output Value Clear Register 1 */ +#define REG_PORT_OUTSET1 (*(RwReg *)0x41004498U) /**< \brief (PORT) Data Output Value Set Register 1 */ +#define REG_PORT_OUTTGL1 (*(RwReg *)0x4100449CU) /**< \brief (PORT) Data Output Value Toggle Register 1 */ +#define REG_PORT_IN1 (*(RoReg *)0x410044A0U) /**< \brief (PORT) Data Input Value Register 1 */ +#define REG_PORT_CTRL1 (*(RwReg *)0x410044A4U) /**< \brief (PORT) Control Register 1 */ +#define REG_PORT_WRCONFIG1 (*(WoReg *)0x410044A8U) /**< \brief (PORT) Write Configuration Register 1 */ +#define REG_PORT_PMUX1 (*(RwReg *)0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing Register 1 */ +#define REG_PORT_PINCFG1 (*(RwReg *)0x410044C0U) /**< \brief (PORT) Pin Configuration Register 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for PORT peripheral ========== */ +#define PORT_BITS 64 +#define PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000 } +#define PORT_DIR_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF } +#define PORT_DRVSTR_DEFAULT_VAL { 0x00000000, 0x00000000 } +#define PORT_DRVSTR_IMPLEMENTED { 0x00000000, 0x00000000 } +#define PORT_GROUPS 2 +#define PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000 } +#define PORT_INEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF } +#define PORT_ODRAIN_DEFAULT_VAL { 0x00000000, 0x00000000 } +#define PORT_ODRAIN_IMPLEMENTED { 0x00000000, 0x00000000 } +#define PORT_OUT_DEFAULT_VAL { 0x00000000, 0x00000000 } +#define PORT_OUT_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF } +#define PORT_PIN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF } +#define PORT_PMUXBIT0_DEFAULT_VAL { 0x00000000, 0x00000000 } +#define PORT_PMUXBIT0_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF } +#define PORT_PMUXBIT1_DEFAULT_VAL { 0x40000000, 0x00000000 } +#define PORT_PMUXBIT1_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F } +#define PORT_PMUXBIT2_DEFAULT_VAL { 0x40000000, 0x00000000 } +#define PORT_PMUXBIT2_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F } +#define PORT_PMUXBIT3_DEFAULT_VAL { 0x00000000, 0x00000000 } +#define PORT_PMUXBIT3_IMPLEMENTED { 0x00000000, 0x00000000 } +#define PORT_PMUXEN_DEFAULT_VAL { 0x64000000, 0x3F3C0000 } +#define PORT_PMUXEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF } +#define PORT_PULLEN_DEFAULT_VAL { 0x00000000, 0x00000000 } +#define PORT_PULLEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF } +#define PORT_SLEWLIM_DEFAULT_VAL { 0x00000000, 0x00000000 } +#define PORT_SLEWLIM_IMPLEMENTED { 0x00000000, 0x00000000 } + +#endif /* _SAMD20_PORT_INSTANCE_ */
diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_rtc.h b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_rtc.h new file mode 100644 index 0000000..d8bcd30 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_rtc.h
@@ -0,0 +1,114 @@ +/** + * \file + * + * \brief Instance description for RTC + * + * Copyright (c) 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD20_RTC_INSTANCE_ +#define _SAMD20_RTC_INSTANCE_ + +/* ========== Register definition for RTC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_RTC_MODE0_CTRL (0x40001400U) /**< \brief (RTC) MODE0 Control Register */ +#define REG_RTC_MODE1_CTRL (0x40001400U) /**< \brief (RTC) MODE1 Control Register */ +#define REG_RTC_MODE2_CTRL (0x40001400U) /**< \brief (RTC) MODE2 Control Register */ +#define REG_RTC_READREQ (0x40001402U) /**< \brief (RTC) Read Request Register */ +#define REG_RTC_MODE0_EVCTRL (0x40001404U) /**< \brief (RTC) MODE0 Event Control Register */ +#define REG_RTC_MODE1_EVCTRL (0x40001404U) /**< \brief (RTC) MODE1 Event Control Register */ +#define REG_RTC_MODE2_EVCTRL (0x40001404U) /**< \brief (RTC) MODE2 Event Control Register */ +#define REG_RTC_MODE0_INTENCLR (0x40001406U) /**< \brief (RTC) MODE0 Interrupt Enable Clear Register */ +#define REG_RTC_MODE1_INTENCLR (0x40001406U) /**< \brief (RTC) MODE1 Interrupt Enable Clear Register */ +#define REG_RTC_MODE2_INTENCLR (0x40001406U) /**< \brief (RTC) MODE2 Interrupt Enable Clear Register */ +#define REG_RTC_MODE0_INTENSET (0x40001407U) /**< \brief (RTC) MODE0 Interrupt Enable Set Register */ +#define REG_RTC_MODE1_INTENSET (0x40001407U) /**< \brief (RTC) MODE1 Interrupt Enable Set Register */ +#define REG_RTC_MODE2_INTENSET (0x40001407U) /**< \brief (RTC) MODE2 Interrupt Enable Set Register */ +#define REG_RTC_MODE0_INTFLAG (0x40001408U) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear Register */ +#define REG_RTC_MODE1_INTFLAG (0x40001408U) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear Register */ +#define REG_RTC_MODE2_INTFLAG (0x40001408U) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear Register */ +#define REG_RTC_STATUS (0x4000140AU) /**< \brief (RTC) Status Register */ +#define REG_RTC_DBGCTRL (0x4000140BU) /**< \brief (RTC) Debug Register */ +#define REG_RTC_FREQCORR (0x4000140CU) /**< \brief (RTC) Frequency Correction Register */ +#define REG_RTC_MODE0_COUNT (0x40001410U) /**< \brief (RTC) MODE0 Count Register */ +#define REG_RTC_MODE1_COUNT (0x40001410U) /**< \brief (RTC) MODE1 Count Register */ +#define REG_RTC_MODE2_CLOCK (0x40001410U) /**< \brief (RTC) MODE2 Clock Register */ +#define REG_RTC_MODE1_PER (0x40001414U) /**< \brief (RTC) MODE1 Period Register */ +#define REG_RTC_MODE0_COMP0 (0x40001418U) /**< \brief (RTC) MODE0 Compare Register 0 */ +#define REG_RTC_MODE1_COMP0 (0x40001418U) /**< \brief (RTC) MODE1 Compare Register 0 */ +#define REG_RTC_MODE1_COMP1 (0x4000141AU) /**< \brief (RTC) MODE1 Compare Register 1 */ +#define REG_RTC_MODE2_ALARM_ALARM0 (0x40001418U) /**< \brief (RTC) MODE2_ALARM Alarm Register 0 */ +#define REG_RTC_MODE2_ALARM_MASK0 (0x4000141CU) /**< \brief (RTC) MODE2_ALARM Alarm Mask Register 0 */ +#else +#define REG_RTC_MODE0_CTRL (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE0 Control Register */ +#define REG_RTC_MODE1_CTRL (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE1 Control Register */ +#define REG_RTC_MODE2_CTRL (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE2 Control Register */ +#define REG_RTC_READREQ (*(RwReg16*)0x40001402U) /**< \brief (RTC) Read Request Register */ +#define REG_RTC_MODE0_EVCTRL (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE0 Event Control Register */ +#define REG_RTC_MODE1_EVCTRL (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE1 Event Control Register */ +#define REG_RTC_MODE2_EVCTRL (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE2 Event Control Register */ +#define REG_RTC_MODE0_INTENCLR (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE0 Interrupt Enable Clear Register */ +#define REG_RTC_MODE1_INTENCLR (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE1 Interrupt Enable Clear Register */ +#define REG_RTC_MODE2_INTENCLR (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE2 Interrupt Enable Clear Register */ +#define REG_RTC_MODE0_INTENSET (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE0 Interrupt Enable Set Register */ +#define REG_RTC_MODE1_INTENSET (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE1 Interrupt Enable Set Register */ +#define REG_RTC_MODE2_INTENSET (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE2 Interrupt Enable Set Register */ +#define REG_RTC_MODE0_INTFLAG (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear Register */ +#define REG_RTC_MODE1_INTFLAG (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear Register */ +#define REG_RTC_MODE2_INTFLAG (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear Register */ +#define REG_RTC_STATUS (*(RwReg8 *)0x4000140AU) /**< \brief (RTC) Status Register */ +#define REG_RTC_DBGCTRL (*(RwReg8 *)0x4000140BU) /**< \brief (RTC) Debug Register */ +#define REG_RTC_FREQCORR (*(RwReg8 *)0x4000140CU) /**< \brief (RTC) Frequency Correction Register */ +#define REG_RTC_MODE0_COUNT (*(RwReg *)0x40001410U) /**< \brief (RTC) MODE0 Count Register */ +#define REG_RTC_MODE1_COUNT (*(RwReg16*)0x40001410U) /**< \brief (RTC) MODE1 Count Register */ +#define REG_RTC_MODE2_CLOCK (*(RwReg *)0x40001410U) /**< \brief (RTC) MODE2 Clock Register */ +#define REG_RTC_MODE1_PER (*(RwReg16*)0x40001414U) /**< \brief (RTC) MODE1 Period Register */ +#define REG_RTC_MODE0_COMP0 (*(RwReg *)0x40001418U) /**< \brief (RTC) MODE0 Compare Register 0 */ +#define REG_RTC_MODE1_COMP0 (*(RwReg16*)0x40001418U) /**< \brief (RTC) MODE1 Compare Register 0 */ +#define REG_RTC_MODE1_COMP1 (*(RwReg16*)0x4000141AU) /**< \brief (RTC) MODE1 Compare Register 1 */ +#define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg *)0x40001418U) /**< \brief (RTC) MODE2_ALARM Alarm Register 0 */ +#define REG_RTC_MODE2_ALARM_MASK0 (*(RwReg *)0x4000141CU) /**< \brief (RTC) MODE2_ALARM Alarm Mask Register 0 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for RTC peripheral ========== */ +#define RTC_GCLK_ID 2 +#define RTC_NUM_OF_ALARMS 1 +#define RTC_NUM_OF_COMP16 2 +#define RTC_NUM_OF_COMP32 1 + +#endif /* _SAMD20_RTC_INSTANCE_ */
diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_sercom0.h b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_sercom0.h new file mode 100644 index 0000000..6924157 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_sercom0.h
@@ -0,0 +1,132 @@ +/** + * \file + * + * \brief Instance description for SERCOM0 + * + * Copyright (c) 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD20_SERCOM0_INSTANCE_ +#define _SAMD20_SERCOM0_INSTANCE_ + +/* ========== Register definition for SERCOM0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM0_I2CM_CTRLA (0x42000800U) /**< \brief (SERCOM0) I2CM Control Register A */ +#define REG_SERCOM0_I2CS_CTRLA (0x42000800U) /**< \brief (SERCOM0) I2CS Control Register A */ +#define REG_SERCOM0_SPI_CTRLA (0x42000800U) /**< \brief (SERCOM0) SPI Control Register A */ +#define REG_SERCOM0_USART_CTRLA (0x42000800U) /**< \brief (SERCOM0) USART Control Register A */ +#define REG_SERCOM0_I2CM_CTRLB (0x42000804U) /**< \brief (SERCOM0) I2CM Control Register B */ +#define REG_SERCOM0_I2CS_CTRLB (0x42000804U) /**< \brief (SERCOM0) I2CS Control Register B */ +#define REG_SERCOM0_SPI_CTRLB (0x42000804U) /**< \brief (SERCOM0) SPI Control Register B */ +#define REG_SERCOM0_USART_CTRLB (0x42000804U) /**< \brief (SERCOM0) USART Control Register B */ +#define REG_SERCOM0_I2CM_DBGCTRL (0x42000808U) /**< \brief (SERCOM0) I2CM Debug Register */ +#define REG_SERCOM0_SPI_DBGCTRL (0x42000808U) /**< \brief (SERCOM0) SPI Debug Register */ +#define REG_SERCOM0_USART_DBGCTRL (0x42000808U) /**< \brief (SERCOM0) USART Debug Register */ +#define REG_SERCOM0_I2CM_BAUD (0x4200080AU) /**< \brief (SERCOM0) I2CM Baud Rate Register */ +#define REG_SERCOM0_SPI_BAUD (0x4200080AU) /**< \brief (SERCOM0) SPI Baud Rate Register */ +#define REG_SERCOM0_USART_BAUD (0x4200080AU) /**< \brief (SERCOM0) USART Baud Rate Register */ +#define REG_SERCOM0_I2CM_INTENCLR (0x4200080CU) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear Register */ +#define REG_SERCOM0_I2CS_INTENCLR (0x4200080CU) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear Register */ +#define REG_SERCOM0_SPI_INTENCLR (0x4200080CU) /**< \brief (SERCOM0) SPI Interrupt Enable Clear Register */ +#define REG_SERCOM0_USART_INTENCLR (0x4200080CU) /**< \brief (SERCOM0) USART Interrupt Enable Clear Register */ +#define REG_SERCOM0_I2CM_INTENSET (0x4200080DU) /**< \brief (SERCOM0) I2CM Interrupt Enable Set Register */ +#define REG_SERCOM0_I2CS_INTENSET (0x4200080DU) /**< \brief (SERCOM0) I2CS Interrupt Enable Set Register */ +#define REG_SERCOM0_SPI_INTENSET (0x4200080DU) /**< \brief (SERCOM0) SPI Interrupt Enable Set Register */ +#define REG_SERCOM0_USART_INTENSET (0x4200080DU) /**< \brief (SERCOM0) USART Interrupt Enable Set Register */ +#define REG_SERCOM0_I2CM_INTFLAG (0x4200080EU) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear Register */ +#define REG_SERCOM0_I2CS_INTFLAG (0x4200080EU) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear Register */ +#define REG_SERCOM0_SPI_INTFLAG (0x4200080EU) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear Register */ +#define REG_SERCOM0_USART_INTFLAG (0x4200080EU) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear Register */ +#define REG_SERCOM0_I2CM_STATUS (0x42000810U) /**< \brief (SERCOM0) I2CM Status Register */ +#define REG_SERCOM0_I2CS_STATUS (0x42000810U) /**< \brief (SERCOM0) I2CS Status Register */ +#define REG_SERCOM0_SPI_STATUS (0x42000810U) /**< \brief (SERCOM0) SPI Status Register */ +#define REG_SERCOM0_USART_STATUS (0x42000810U) /**< \brief (SERCOM0) USART Status Register */ +#define REG_SERCOM0_I2CM_ADDR (0x42000814U) /**< \brief (SERCOM0) I2CM Address Register */ +#define REG_SERCOM0_I2CS_ADDR (0x42000814U) /**< \brief (SERCOM0) I2CS Address Register */ +#define REG_SERCOM0_SPI_ADDR (0x42000814U) /**< \brief (SERCOM0) SPI Address Register */ +#define REG_SERCOM0_I2CM_DATA (0x42000818U) /**< \brief (SERCOM0) I2CM Data Register */ +#define REG_SERCOM0_I2CS_DATA (0x42000818U) /**< \brief (SERCOM0) I2CS Data Register */ +#define REG_SERCOM0_SPI_DATA (0x42000818U) /**< \brief (SERCOM0) SPI Data Register */ +#define REG_SERCOM0_USART_DATA (0x42000818U) /**< \brief (SERCOM0) USART Data Register */ +#else +#define REG_SERCOM0_I2CM_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) I2CM Control Register A */ +#define REG_SERCOM0_I2CS_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) I2CS Control Register A */ +#define REG_SERCOM0_SPI_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) SPI Control Register A */ +#define REG_SERCOM0_USART_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) USART Control Register A */ +#define REG_SERCOM0_I2CM_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) I2CM Control Register B */ +#define REG_SERCOM0_I2CS_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) I2CS Control Register B */ +#define REG_SERCOM0_SPI_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) SPI Control Register B */ +#define REG_SERCOM0_USART_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) USART Control Register B */ +#define REG_SERCOM0_I2CM_DBGCTRL (*(RwReg8 *)0x42000808U) /**< \brief (SERCOM0) I2CM Debug Register */ +#define REG_SERCOM0_SPI_DBGCTRL (*(RwReg8 *)0x42000808U) /**< \brief (SERCOM0) SPI Debug Register */ +#define REG_SERCOM0_USART_DBGCTRL (*(RwReg8 *)0x42000808U) /**< \brief (SERCOM0) USART Debug Register */ +#define REG_SERCOM0_I2CM_BAUD (*(RwReg16*)0x4200080AU) /**< \brief (SERCOM0) I2CM Baud Rate Register */ +#define REG_SERCOM0_SPI_BAUD (*(RwReg8 *)0x4200080AU) /**< \brief (SERCOM0) SPI Baud Rate Register */ +#define REG_SERCOM0_USART_BAUD (*(RwReg16*)0x4200080AU) /**< \brief (SERCOM0) USART Baud Rate Register */ +#define REG_SERCOM0_I2CM_INTENCLR (*(RwReg8 *)0x4200080CU) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear Register */ +#define REG_SERCOM0_I2CS_INTENCLR (*(RwReg8 *)0x4200080CU) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear Register */ +#define REG_SERCOM0_SPI_INTENCLR (*(RwReg8 *)0x4200080CU) /**< \brief (SERCOM0) SPI Interrupt Enable Clear Register */ +#define REG_SERCOM0_USART_INTENCLR (*(RwReg8 *)0x4200080CU) /**< \brief (SERCOM0) USART Interrupt Enable Clear Register */ +#define REG_SERCOM0_I2CM_INTENSET (*(RwReg8 *)0x4200080DU) /**< \brief (SERCOM0) I2CM Interrupt Enable Set Register */ +#define REG_SERCOM0_I2CS_INTENSET (*(RwReg8 *)0x4200080DU) /**< \brief (SERCOM0) I2CS Interrupt Enable Set Register */ +#define REG_SERCOM0_SPI_INTENSET (*(RwReg8 *)0x4200080DU) /**< \brief (SERCOM0) SPI Interrupt Enable Set Register */ +#define REG_SERCOM0_USART_INTENSET (*(RwReg8 *)0x4200080DU) /**< \brief (SERCOM0) USART Interrupt Enable Set Register */ +#define REG_SERCOM0_I2CM_INTFLAG (*(RwReg8 *)0x4200080EU) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear Register */ +#define REG_SERCOM0_I2CS_INTFLAG (*(RwReg8 *)0x4200080EU) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear Register */ +#define REG_SERCOM0_SPI_INTFLAG (*(RwReg8 *)0x4200080EU) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear Register */ +#define REG_SERCOM0_USART_INTFLAG (*(RwReg8 *)0x4200080EU) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear Register */ +#define REG_SERCOM0_I2CM_STATUS (*(RwReg16*)0x42000810U) /**< \brief (SERCOM0) I2CM Status Register */ +#define REG_SERCOM0_I2CS_STATUS (*(RwReg16*)0x42000810U) /**< \brief (SERCOM0) I2CS Status Register */ +#define REG_SERCOM0_SPI_STATUS (*(RwReg16*)0x42000810U) /**< \brief (SERCOM0) SPI Status Register */ +#define REG_SERCOM0_USART_STATUS (*(RwReg16*)0x42000810U) /**< \brief (SERCOM0) USART Status Register */ +#define REG_SERCOM0_I2CM_ADDR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) I2CM Address Register */ +#define REG_SERCOM0_I2CS_ADDR (*(RwReg *)0x42000814U) /**< \brief (SERCOM0) I2CS Address Register */ +#define REG_SERCOM0_SPI_ADDR (*(RwReg *)0x42000814U) /**< \brief (SERCOM0) SPI Address Register */ +#define REG_SERCOM0_I2CM_DATA (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) I2CM Data Register */ +#define REG_SERCOM0_I2CS_DATA (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) I2CS Data Register */ +#define REG_SERCOM0_SPI_DATA (*(RwReg16*)0x42000818U) /**< \brief (SERCOM0) SPI Data Register */ +#define REG_SERCOM0_USART_DATA (*(RwReg16*)0x42000818U) /**< \brief (SERCOM0) USART Data Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM0 peripheral ========== */ +#define SERCOM0_GCLK_ID_CORE 13 +#define SERCOM0_GCLK_ID_SLOW 12 +#define SERCOM0_INT_MSB 3 +#define SERCOM0_PMSB 3 + +#endif /* _SAMD20_SERCOM0_INSTANCE_ */
diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_sercom1.h b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_sercom1.h new file mode 100644 index 0000000..f84b239 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_sercom1.h
@@ -0,0 +1,132 @@ +/** + * \file + * + * \brief Instance description for SERCOM1 + * + * Copyright (c) 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD20_SERCOM1_INSTANCE_ +#define _SAMD20_SERCOM1_INSTANCE_ + +/* ========== Register definition for SERCOM1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM1_I2CM_CTRLA (0x42000C00U) /**< \brief (SERCOM1) I2CM Control Register A */ +#define REG_SERCOM1_I2CS_CTRLA (0x42000C00U) /**< \brief (SERCOM1) I2CS Control Register A */ +#define REG_SERCOM1_SPI_CTRLA (0x42000C00U) /**< \brief (SERCOM1) SPI Control Register A */ +#define REG_SERCOM1_USART_CTRLA (0x42000C00U) /**< \brief (SERCOM1) USART Control Register A */ +#define REG_SERCOM1_I2CM_CTRLB (0x42000C04U) /**< \brief (SERCOM1) I2CM Control Register B */ +#define REG_SERCOM1_I2CS_CTRLB (0x42000C04U) /**< \brief (SERCOM1) I2CS Control Register B */ +#define REG_SERCOM1_SPI_CTRLB (0x42000C04U) /**< \brief (SERCOM1) SPI Control Register B */ +#define REG_SERCOM1_USART_CTRLB (0x42000C04U) /**< \brief (SERCOM1) USART Control Register B */ +#define REG_SERCOM1_I2CM_DBGCTRL (0x42000C08U) /**< \brief (SERCOM1) I2CM Debug Register */ +#define REG_SERCOM1_SPI_DBGCTRL (0x42000C08U) /**< \brief (SERCOM1) SPI Debug Register */ +#define REG_SERCOM1_USART_DBGCTRL (0x42000C08U) /**< \brief (SERCOM1) USART Debug Register */ +#define REG_SERCOM1_I2CM_BAUD (0x42000C0AU) /**< \brief (SERCOM1) I2CM Baud Rate Register */ +#define REG_SERCOM1_SPI_BAUD (0x42000C0AU) /**< \brief (SERCOM1) SPI Baud Rate Register */ +#define REG_SERCOM1_USART_BAUD (0x42000C0AU) /**< \brief (SERCOM1) USART Baud Rate Register */ +#define REG_SERCOM1_I2CM_INTENCLR (0x42000C0CU) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear Register */ +#define REG_SERCOM1_I2CS_INTENCLR (0x42000C0CU) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear Register */ +#define REG_SERCOM1_SPI_INTENCLR (0x42000C0CU) /**< \brief (SERCOM1) SPI Interrupt Enable Clear Register */ +#define REG_SERCOM1_USART_INTENCLR (0x42000C0CU) /**< \brief (SERCOM1) USART Interrupt Enable Clear Register */ +#define REG_SERCOM1_I2CM_INTENSET (0x42000C0DU) /**< \brief (SERCOM1) I2CM Interrupt Enable Set Register */ +#define REG_SERCOM1_I2CS_INTENSET (0x42000C0DU) /**< \brief (SERCOM1) I2CS Interrupt Enable Set Register */ +#define REG_SERCOM1_SPI_INTENSET (0x42000C0DU) /**< \brief (SERCOM1) SPI Interrupt Enable Set Register */ +#define REG_SERCOM1_USART_INTENSET (0x42000C0DU) /**< \brief (SERCOM1) USART Interrupt Enable Set Register */ +#define REG_SERCOM1_I2CM_INTFLAG (0x42000C0EU) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear Register */ +#define REG_SERCOM1_I2CS_INTFLAG (0x42000C0EU) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear Register */ +#define REG_SERCOM1_SPI_INTFLAG (0x42000C0EU) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear Register */ +#define REG_SERCOM1_USART_INTFLAG (0x42000C0EU) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear Register */ +#define REG_SERCOM1_I2CM_STATUS (0x42000C10U) /**< \brief (SERCOM1) I2CM Status Register */ +#define REG_SERCOM1_I2CS_STATUS (0x42000C10U) /**< \brief (SERCOM1) I2CS Status Register */ +#define REG_SERCOM1_SPI_STATUS (0x42000C10U) /**< \brief (SERCOM1) SPI Status Register */ +#define REG_SERCOM1_USART_STATUS (0x42000C10U) /**< \brief (SERCOM1) USART Status Register */ +#define REG_SERCOM1_I2CM_ADDR (0x42000C14U) /**< \brief (SERCOM1) I2CM Address Register */ +#define REG_SERCOM1_I2CS_ADDR (0x42000C14U) /**< \brief (SERCOM1) I2CS Address Register */ +#define REG_SERCOM1_SPI_ADDR (0x42000C14U) /**< \brief (SERCOM1) SPI Address Register */ +#define REG_SERCOM1_I2CM_DATA (0x42000C18U) /**< \brief (SERCOM1) I2CM Data Register */ +#define REG_SERCOM1_I2CS_DATA (0x42000C18U) /**< \brief (SERCOM1) I2CS Data Register */ +#define REG_SERCOM1_SPI_DATA (0x42000C18U) /**< \brief (SERCOM1) SPI Data Register */ +#define REG_SERCOM1_USART_DATA (0x42000C18U) /**< \brief (SERCOM1) USART Data Register */ +#else +#define REG_SERCOM1_I2CM_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM1) I2CM Control Register A */ +#define REG_SERCOM1_I2CS_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM1) I2CS Control Register A */ +#define REG_SERCOM1_SPI_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM1) SPI Control Register A */ +#define REG_SERCOM1_USART_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM1) USART Control Register A */ +#define REG_SERCOM1_I2CM_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM1) I2CM Control Register B */ +#define REG_SERCOM1_I2CS_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM1) I2CS Control Register B */ +#define REG_SERCOM1_SPI_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM1) SPI Control Register B */ +#define REG_SERCOM1_USART_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM1) USART Control Register B */ +#define REG_SERCOM1_I2CM_DBGCTRL (*(RwReg8 *)0x42000C08U) /**< \brief (SERCOM1) I2CM Debug Register */ +#define REG_SERCOM1_SPI_DBGCTRL (*(RwReg8 *)0x42000C08U) /**< \brief (SERCOM1) SPI Debug Register */ +#define REG_SERCOM1_USART_DBGCTRL (*(RwReg8 *)0x42000C08U) /**< \brief (SERCOM1) USART Debug Register */ +#define REG_SERCOM1_I2CM_BAUD (*(RwReg16*)0x42000C0AU) /**< \brief (SERCOM1) I2CM Baud Rate Register */ +#define REG_SERCOM1_SPI_BAUD (*(RwReg8 *)0x42000C0AU) /**< \brief (SERCOM1) SPI Baud Rate Register */ +#define REG_SERCOM1_USART_BAUD (*(RwReg16*)0x42000C0AU) /**< \brief (SERCOM1) USART Baud Rate Register */ +#define REG_SERCOM1_I2CM_INTENCLR (*(RwReg8 *)0x42000C0CU) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear Register */ +#define REG_SERCOM1_I2CS_INTENCLR (*(RwReg8 *)0x42000C0CU) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear Register */ +#define REG_SERCOM1_SPI_INTENCLR (*(RwReg8 *)0x42000C0CU) /**< \brief (SERCOM1) SPI Interrupt Enable Clear Register */ +#define REG_SERCOM1_USART_INTENCLR (*(RwReg8 *)0x42000C0CU) /**< \brief (SERCOM1) USART Interrupt Enable Clear Register */ +#define REG_SERCOM1_I2CM_INTENSET (*(RwReg8 *)0x42000C0DU) /**< \brief (SERCOM1) I2CM Interrupt Enable Set Register */ +#define REG_SERCOM1_I2CS_INTENSET (*(RwReg8 *)0x42000C0DU) /**< \brief (SERCOM1) I2CS Interrupt Enable Set Register */ +#define REG_SERCOM1_SPI_INTENSET (*(RwReg8 *)0x42000C0DU) /**< \brief (SERCOM1) SPI Interrupt Enable Set Register */ +#define REG_SERCOM1_USART_INTENSET (*(RwReg8 *)0x42000C0DU) /**< \brief (SERCOM1) USART Interrupt Enable Set Register */ +#define REG_SERCOM1_I2CM_INTFLAG (*(RwReg8 *)0x42000C0EU) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear Register */ +#define REG_SERCOM1_I2CS_INTFLAG (*(RwReg8 *)0x42000C0EU) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear Register */ +#define REG_SERCOM1_SPI_INTFLAG (*(RwReg8 *)0x42000C0EU) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear Register */ +#define REG_SERCOM1_USART_INTFLAG (*(RwReg8 *)0x42000C0EU) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear Register */ +#define REG_SERCOM1_I2CM_STATUS (*(RwReg16*)0x42000C10U) /**< \brief (SERCOM1) I2CM Status Register */ +#define REG_SERCOM1_I2CS_STATUS (*(RwReg16*)0x42000C10U) /**< \brief (SERCOM1) I2CS Status Register */ +#define REG_SERCOM1_SPI_STATUS (*(RwReg16*)0x42000C10U) /**< \brief (SERCOM1) SPI Status Register */ +#define REG_SERCOM1_USART_STATUS (*(RwReg16*)0x42000C10U) /**< \brief (SERCOM1) USART Status Register */ +#define REG_SERCOM1_I2CM_ADDR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) I2CM Address Register */ +#define REG_SERCOM1_I2CS_ADDR (*(RwReg *)0x42000C14U) /**< \brief (SERCOM1) I2CS Address Register */ +#define REG_SERCOM1_SPI_ADDR (*(RwReg *)0x42000C14U) /**< \brief (SERCOM1) SPI Address Register */ +#define REG_SERCOM1_I2CM_DATA (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) I2CM Data Register */ +#define REG_SERCOM1_I2CS_DATA (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) I2CS Data Register */ +#define REG_SERCOM1_SPI_DATA (*(RwReg16*)0x42000C18U) /**< \brief (SERCOM1) SPI Data Register */ +#define REG_SERCOM1_USART_DATA (*(RwReg16*)0x42000C18U) /**< \brief (SERCOM1) USART Data Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM1 peripheral ========== */ +#define SERCOM1_GCLK_ID_CORE 14 +#define SERCOM1_GCLK_ID_SLOW 12 +#define SERCOM1_INT_MSB 3 +#define SERCOM1_PMSB 3 + +#endif /* _SAMD20_SERCOM1_INSTANCE_ */
diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_sercom2.h b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_sercom2.h new file mode 100644 index 0000000..10b49ad --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_sercom2.h
@@ -0,0 +1,132 @@ +/** + * \file + * + * \brief Instance description for SERCOM2 + * + * Copyright (c) 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD20_SERCOM2_INSTANCE_ +#define _SAMD20_SERCOM2_INSTANCE_ + +/* ========== Register definition for SERCOM2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM2_I2CM_CTRLA (0x42001000U) /**< \brief (SERCOM2) I2CM Control Register A */ +#define REG_SERCOM2_I2CS_CTRLA (0x42001000U) /**< \brief (SERCOM2) I2CS Control Register A */ +#define REG_SERCOM2_SPI_CTRLA (0x42001000U) /**< \brief (SERCOM2) SPI Control Register A */ +#define REG_SERCOM2_USART_CTRLA (0x42001000U) /**< \brief (SERCOM2) USART Control Register A */ +#define REG_SERCOM2_I2CM_CTRLB (0x42001004U) /**< \brief (SERCOM2) I2CM Control Register B */ +#define REG_SERCOM2_I2CS_CTRLB (0x42001004U) /**< \brief (SERCOM2) I2CS Control Register B */ +#define REG_SERCOM2_SPI_CTRLB (0x42001004U) /**< \brief (SERCOM2) SPI Control Register B */ +#define REG_SERCOM2_USART_CTRLB (0x42001004U) /**< \brief (SERCOM2) USART Control Register B */ +#define REG_SERCOM2_I2CM_DBGCTRL (0x42001008U) /**< \brief (SERCOM2) I2CM Debug Register */ +#define REG_SERCOM2_SPI_DBGCTRL (0x42001008U) /**< \brief (SERCOM2) SPI Debug Register */ +#define REG_SERCOM2_USART_DBGCTRL (0x42001008U) /**< \brief (SERCOM2) USART Debug Register */ +#define REG_SERCOM2_I2CM_BAUD (0x4200100AU) /**< \brief (SERCOM2) I2CM Baud Rate Register */ +#define REG_SERCOM2_SPI_BAUD (0x4200100AU) /**< \brief (SERCOM2) SPI Baud Rate Register */ +#define REG_SERCOM2_USART_BAUD (0x4200100AU) /**< \brief (SERCOM2) USART Baud Rate Register */ +#define REG_SERCOM2_I2CM_INTENCLR (0x4200100CU) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear Register */ +#define REG_SERCOM2_I2CS_INTENCLR (0x4200100CU) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear Register */ +#define REG_SERCOM2_SPI_INTENCLR (0x4200100CU) /**< \brief (SERCOM2) SPI Interrupt Enable Clear Register */ +#define REG_SERCOM2_USART_INTENCLR (0x4200100CU) /**< \brief (SERCOM2) USART Interrupt Enable Clear Register */ +#define REG_SERCOM2_I2CM_INTENSET (0x4200100DU) /**< \brief (SERCOM2) I2CM Interrupt Enable Set Register */ +#define REG_SERCOM2_I2CS_INTENSET (0x4200100DU) /**< \brief (SERCOM2) I2CS Interrupt Enable Set Register */ +#define REG_SERCOM2_SPI_INTENSET (0x4200100DU) /**< \brief (SERCOM2) SPI Interrupt Enable Set Register */ +#define REG_SERCOM2_USART_INTENSET (0x4200100DU) /**< \brief (SERCOM2) USART Interrupt Enable Set Register */ +#define REG_SERCOM2_I2CM_INTFLAG (0x4200100EU) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear Register */ +#define REG_SERCOM2_I2CS_INTFLAG (0x4200100EU) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear Register */ +#define REG_SERCOM2_SPI_INTFLAG (0x4200100EU) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear Register */ +#define REG_SERCOM2_USART_INTFLAG (0x4200100EU) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear Register */ +#define REG_SERCOM2_I2CM_STATUS (0x42001010U) /**< \brief (SERCOM2) I2CM Status Register */ +#define REG_SERCOM2_I2CS_STATUS (0x42001010U) /**< \brief (SERCOM2) I2CS Status Register */ +#define REG_SERCOM2_SPI_STATUS (0x42001010U) /**< \brief (SERCOM2) SPI Status Register */ +#define REG_SERCOM2_USART_STATUS (0x42001010U) /**< \brief (SERCOM2) USART Status Register */ +#define REG_SERCOM2_I2CM_ADDR (0x42001014U) /**< \brief (SERCOM2) I2CM Address Register */ +#define REG_SERCOM2_I2CS_ADDR (0x42001014U) /**< \brief (SERCOM2) I2CS Address Register */ +#define REG_SERCOM2_SPI_ADDR (0x42001014U) /**< \brief (SERCOM2) SPI Address Register */ +#define REG_SERCOM2_I2CM_DATA (0x42001018U) /**< \brief (SERCOM2) I2CM Data Register */ +#define REG_SERCOM2_I2CS_DATA (0x42001018U) /**< \brief (SERCOM2) I2CS Data Register */ +#define REG_SERCOM2_SPI_DATA (0x42001018U) /**< \brief (SERCOM2) SPI Data Register */ +#define REG_SERCOM2_USART_DATA (0x42001018U) /**< \brief (SERCOM2) USART Data Register */ +#else +#define REG_SERCOM2_I2CM_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) I2CM Control Register A */ +#define REG_SERCOM2_I2CS_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) I2CS Control Register A */ +#define REG_SERCOM2_SPI_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) SPI Control Register A */ +#define REG_SERCOM2_USART_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) USART Control Register A */ +#define REG_SERCOM2_I2CM_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) I2CM Control Register B */ +#define REG_SERCOM2_I2CS_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) I2CS Control Register B */ +#define REG_SERCOM2_SPI_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) SPI Control Register B */ +#define REG_SERCOM2_USART_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) USART Control Register B */ +#define REG_SERCOM2_I2CM_DBGCTRL (*(RwReg8 *)0x42001008U) /**< \brief (SERCOM2) I2CM Debug Register */ +#define REG_SERCOM2_SPI_DBGCTRL (*(RwReg8 *)0x42001008U) /**< \brief (SERCOM2) SPI Debug Register */ +#define REG_SERCOM2_USART_DBGCTRL (*(RwReg8 *)0x42001008U) /**< \brief (SERCOM2) USART Debug Register */ +#define REG_SERCOM2_I2CM_BAUD (*(RwReg16*)0x4200100AU) /**< \brief (SERCOM2) I2CM Baud Rate Register */ +#define REG_SERCOM2_SPI_BAUD (*(RwReg8 *)0x4200100AU) /**< \brief (SERCOM2) SPI Baud Rate Register */ +#define REG_SERCOM2_USART_BAUD (*(RwReg16*)0x4200100AU) /**< \brief (SERCOM2) USART Baud Rate Register */ +#define REG_SERCOM2_I2CM_INTENCLR (*(RwReg8 *)0x4200100CU) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear Register */ +#define REG_SERCOM2_I2CS_INTENCLR (*(RwReg8 *)0x4200100CU) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear Register */ +#define REG_SERCOM2_SPI_INTENCLR (*(RwReg8 *)0x4200100CU) /**< \brief (SERCOM2) SPI Interrupt Enable Clear Register */ +#define REG_SERCOM2_USART_INTENCLR (*(RwReg8 *)0x4200100CU) /**< \brief (SERCOM2) USART Interrupt Enable Clear Register */ +#define REG_SERCOM2_I2CM_INTENSET (*(RwReg8 *)0x4200100DU) /**< \brief (SERCOM2) I2CM Interrupt Enable Set Register */ +#define REG_SERCOM2_I2CS_INTENSET (*(RwReg8 *)0x4200100DU) /**< \brief (SERCOM2) I2CS Interrupt Enable Set Register */ +#define REG_SERCOM2_SPI_INTENSET (*(RwReg8 *)0x4200100DU) /**< \brief (SERCOM2) SPI Interrupt Enable Set Register */ +#define REG_SERCOM2_USART_INTENSET (*(RwReg8 *)0x4200100DU) /**< \brief (SERCOM2) USART Interrupt Enable Set Register */ +#define REG_SERCOM2_I2CM_INTFLAG (*(RwReg8 *)0x4200100EU) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear Register */ +#define REG_SERCOM2_I2CS_INTFLAG (*(RwReg8 *)0x4200100EU) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear Register */ +#define REG_SERCOM2_SPI_INTFLAG (*(RwReg8 *)0x4200100EU) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear Register */ +#define REG_SERCOM2_USART_INTFLAG (*(RwReg8 *)0x4200100EU) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear Register */ +#define REG_SERCOM2_I2CM_STATUS (*(RwReg16*)0x42001010U) /**< \brief (SERCOM2) I2CM Status Register */ +#define REG_SERCOM2_I2CS_STATUS (*(RwReg16*)0x42001010U) /**< \brief (SERCOM2) I2CS Status Register */ +#define REG_SERCOM2_SPI_STATUS (*(RwReg16*)0x42001010U) /**< \brief (SERCOM2) SPI Status Register */ +#define REG_SERCOM2_USART_STATUS (*(RwReg16*)0x42001010U) /**< \brief (SERCOM2) USART Status Register */ +#define REG_SERCOM2_I2CM_ADDR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) I2CM Address Register */ +#define REG_SERCOM2_I2CS_ADDR (*(RwReg *)0x42001014U) /**< \brief (SERCOM2) I2CS Address Register */ +#define REG_SERCOM2_SPI_ADDR (*(RwReg *)0x42001014U) /**< \brief (SERCOM2) SPI Address Register */ +#define REG_SERCOM2_I2CM_DATA (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) I2CM Data Register */ +#define REG_SERCOM2_I2CS_DATA (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) I2CS Data Register */ +#define REG_SERCOM2_SPI_DATA (*(RwReg16*)0x42001018U) /**< \brief (SERCOM2) SPI Data Register */ +#define REG_SERCOM2_USART_DATA (*(RwReg16*)0x42001018U) /**< \brief (SERCOM2) USART Data Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM2 peripheral ========== */ +#define SERCOM2_GCLK_ID_CORE 15 +#define SERCOM2_GCLK_ID_SLOW 12 +#define SERCOM2_INT_MSB 3 +#define SERCOM2_PMSB 3 + +#endif /* _SAMD20_SERCOM2_INSTANCE_ */
diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_sercom3.h b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_sercom3.h new file mode 100644 index 0000000..ed9b169 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_sercom3.h
@@ -0,0 +1,132 @@ +/** + * \file + * + * \brief Instance description for SERCOM3 + * + * Copyright (c) 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD20_SERCOM3_INSTANCE_ +#define _SAMD20_SERCOM3_INSTANCE_ + +/* ========== Register definition for SERCOM3 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM3_I2CM_CTRLA (0x42001400U) /**< \brief (SERCOM3) I2CM Control Register A */ +#define REG_SERCOM3_I2CS_CTRLA (0x42001400U) /**< \brief (SERCOM3) I2CS Control Register A */ +#define REG_SERCOM3_SPI_CTRLA (0x42001400U) /**< \brief (SERCOM3) SPI Control Register A */ +#define REG_SERCOM3_USART_CTRLA (0x42001400U) /**< \brief (SERCOM3) USART Control Register A */ +#define REG_SERCOM3_I2CM_CTRLB (0x42001404U) /**< \brief (SERCOM3) I2CM Control Register B */ +#define REG_SERCOM3_I2CS_CTRLB (0x42001404U) /**< \brief (SERCOM3) I2CS Control Register B */ +#define REG_SERCOM3_SPI_CTRLB (0x42001404U) /**< \brief (SERCOM3) SPI Control Register B */ +#define REG_SERCOM3_USART_CTRLB (0x42001404U) /**< \brief (SERCOM3) USART Control Register B */ +#define REG_SERCOM3_I2CM_DBGCTRL (0x42001408U) /**< \brief (SERCOM3) I2CM Debug Register */ +#define REG_SERCOM3_SPI_DBGCTRL (0x42001408U) /**< \brief (SERCOM3) SPI Debug Register */ +#define REG_SERCOM3_USART_DBGCTRL (0x42001408U) /**< \brief (SERCOM3) USART Debug Register */ +#define REG_SERCOM3_I2CM_BAUD (0x4200140AU) /**< \brief (SERCOM3) I2CM Baud Rate Register */ +#define REG_SERCOM3_SPI_BAUD (0x4200140AU) /**< \brief (SERCOM3) SPI Baud Rate Register */ +#define REG_SERCOM3_USART_BAUD (0x4200140AU) /**< \brief (SERCOM3) USART Baud Rate Register */ +#define REG_SERCOM3_I2CM_INTENCLR (0x4200140CU) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear Register */ +#define REG_SERCOM3_I2CS_INTENCLR (0x4200140CU) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear Register */ +#define REG_SERCOM3_SPI_INTENCLR (0x4200140CU) /**< \brief (SERCOM3) SPI Interrupt Enable Clear Register */ +#define REG_SERCOM3_USART_INTENCLR (0x4200140CU) /**< \brief (SERCOM3) USART Interrupt Enable Clear Register */ +#define REG_SERCOM3_I2CM_INTENSET (0x4200140DU) /**< \brief (SERCOM3) I2CM Interrupt Enable Set Register */ +#define REG_SERCOM3_I2CS_INTENSET (0x4200140DU) /**< \brief (SERCOM3) I2CS Interrupt Enable Set Register */ +#define REG_SERCOM3_SPI_INTENSET (0x4200140DU) /**< \brief (SERCOM3) SPI Interrupt Enable Set Register */ +#define REG_SERCOM3_USART_INTENSET (0x4200140DU) /**< \brief (SERCOM3) USART Interrupt Enable Set Register */ +#define REG_SERCOM3_I2CM_INTFLAG (0x4200140EU) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear Register */ +#define REG_SERCOM3_I2CS_INTFLAG (0x4200140EU) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear Register */ +#define REG_SERCOM3_SPI_INTFLAG (0x4200140EU) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear Register */ +#define REG_SERCOM3_USART_INTFLAG (0x4200140EU) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear Register */ +#define REG_SERCOM3_I2CM_STATUS (0x42001410U) /**< \brief (SERCOM3) I2CM Status Register */ +#define REG_SERCOM3_I2CS_STATUS (0x42001410U) /**< \brief (SERCOM3) I2CS Status Register */ +#define REG_SERCOM3_SPI_STATUS (0x42001410U) /**< \brief (SERCOM3) SPI Status Register */ +#define REG_SERCOM3_USART_STATUS (0x42001410U) /**< \brief (SERCOM3) USART Status Register */ +#define REG_SERCOM3_I2CM_ADDR (0x42001414U) /**< \brief (SERCOM3) I2CM Address Register */ +#define REG_SERCOM3_I2CS_ADDR (0x42001414U) /**< \brief (SERCOM3) I2CS Address Register */ +#define REG_SERCOM3_SPI_ADDR (0x42001414U) /**< \brief (SERCOM3) SPI Address Register */ +#define REG_SERCOM3_I2CM_DATA (0x42001418U) /**< \brief (SERCOM3) I2CM Data Register */ +#define REG_SERCOM3_I2CS_DATA (0x42001418U) /**< \brief (SERCOM3) I2CS Data Register */ +#define REG_SERCOM3_SPI_DATA (0x42001418U) /**< \brief (SERCOM3) SPI Data Register */ +#define REG_SERCOM3_USART_DATA (0x42001418U) /**< \brief (SERCOM3) USART Data Register */ +#else +#define REG_SERCOM3_I2CM_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) I2CM Control Register A */ +#define REG_SERCOM3_I2CS_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) I2CS Control Register A */ +#define REG_SERCOM3_SPI_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) SPI Control Register A */ +#define REG_SERCOM3_USART_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) USART Control Register A */ +#define REG_SERCOM3_I2CM_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) I2CM Control Register B */ +#define REG_SERCOM3_I2CS_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) I2CS Control Register B */ +#define REG_SERCOM3_SPI_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) SPI Control Register B */ +#define REG_SERCOM3_USART_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) USART Control Register B */ +#define REG_SERCOM3_I2CM_DBGCTRL (*(RwReg8 *)0x42001408U) /**< \brief (SERCOM3) I2CM Debug Register */ +#define REG_SERCOM3_SPI_DBGCTRL (*(RwReg8 *)0x42001408U) /**< \brief (SERCOM3) SPI Debug Register */ +#define REG_SERCOM3_USART_DBGCTRL (*(RwReg8 *)0x42001408U) /**< \brief (SERCOM3) USART Debug Register */ +#define REG_SERCOM3_I2CM_BAUD (*(RwReg16*)0x4200140AU) /**< \brief (SERCOM3) I2CM Baud Rate Register */ +#define REG_SERCOM3_SPI_BAUD (*(RwReg8 *)0x4200140AU) /**< \brief (SERCOM3) SPI Baud Rate Register */ +#define REG_SERCOM3_USART_BAUD (*(RwReg16*)0x4200140AU) /**< \brief (SERCOM3) USART Baud Rate Register */ +#define REG_SERCOM3_I2CM_INTENCLR (*(RwReg8 *)0x4200140CU) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear Register */ +#define REG_SERCOM3_I2CS_INTENCLR (*(RwReg8 *)0x4200140CU) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear Register */ +#define REG_SERCOM3_SPI_INTENCLR (*(RwReg8 *)0x4200140CU) /**< \brief (SERCOM3) SPI Interrupt Enable Clear Register */ +#define REG_SERCOM3_USART_INTENCLR (*(RwReg8 *)0x4200140CU) /**< \brief (SERCOM3) USART Interrupt Enable Clear Register */ +#define REG_SERCOM3_I2CM_INTENSET (*(RwReg8 *)0x4200140DU) /**< \brief (SERCOM3) I2CM Interrupt Enable Set Register */ +#define REG_SERCOM3_I2CS_INTENSET (*(RwReg8 *)0x4200140DU) /**< \brief (SERCOM3) I2CS Interrupt Enable Set Register */ +#define REG_SERCOM3_SPI_INTENSET (*(RwReg8 *)0x4200140DU) /**< \brief (SERCOM3) SPI Interrupt Enable Set Register */ +#define REG_SERCOM3_USART_INTENSET (*(RwReg8 *)0x4200140DU) /**< \brief (SERCOM3) USART Interrupt Enable Set Register */ +#define REG_SERCOM3_I2CM_INTFLAG (*(RwReg8 *)0x4200140EU) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear Register */ +#define REG_SERCOM3_I2CS_INTFLAG (*(RwReg8 *)0x4200140EU) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear Register */ +#define REG_SERCOM3_SPI_INTFLAG (*(RwReg8 *)0x4200140EU) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear Register */ +#define REG_SERCOM3_USART_INTFLAG (*(RwReg8 *)0x4200140EU) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear Register */ +#define REG_SERCOM3_I2CM_STATUS (*(RwReg16*)0x42001410U) /**< \brief (SERCOM3) I2CM Status Register */ +#define REG_SERCOM3_I2CS_STATUS (*(RwReg16*)0x42001410U) /**< \brief (SERCOM3) I2CS Status Register */ +#define REG_SERCOM3_SPI_STATUS (*(RwReg16*)0x42001410U) /**< \brief (SERCOM3) SPI Status Register */ +#define REG_SERCOM3_USART_STATUS (*(RwReg16*)0x42001410U) /**< \brief (SERCOM3) USART Status Register */ +#define REG_SERCOM3_I2CM_ADDR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) I2CM Address Register */ +#define REG_SERCOM3_I2CS_ADDR (*(RwReg *)0x42001414U) /**< \brief (SERCOM3) I2CS Address Register */ +#define REG_SERCOM3_SPI_ADDR (*(RwReg *)0x42001414U) /**< \brief (SERCOM3) SPI Address Register */ +#define REG_SERCOM3_I2CM_DATA (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) I2CM Data Register */ +#define REG_SERCOM3_I2CS_DATA (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) I2CS Data Register */ +#define REG_SERCOM3_SPI_DATA (*(RwReg16*)0x42001418U) /**< \brief (SERCOM3) SPI Data Register */ +#define REG_SERCOM3_USART_DATA (*(RwReg16*)0x42001418U) /**< \brief (SERCOM3) USART Data Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM3 peripheral ========== */ +#define SERCOM3_GCLK_ID_CORE 16 +#define SERCOM3_GCLK_ID_SLOW 12 +#define SERCOM3_INT_MSB 3 +#define SERCOM3_PMSB 3 + +#endif /* _SAMD20_SERCOM3_INSTANCE_ */
diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_sercom4.h b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_sercom4.h new file mode 100644 index 0000000..1aa5a29 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_sercom4.h
@@ -0,0 +1,132 @@ +/** + * \file + * + * \brief Instance description for SERCOM4 + * + * Copyright (c) 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD20_SERCOM4_INSTANCE_ +#define _SAMD20_SERCOM4_INSTANCE_ + +/* ========== Register definition for SERCOM4 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM4_I2CM_CTRLA (0x42001800U) /**< \brief (SERCOM4) I2CM Control Register A */ +#define REG_SERCOM4_I2CS_CTRLA (0x42001800U) /**< \brief (SERCOM4) I2CS Control Register A */ +#define REG_SERCOM4_SPI_CTRLA (0x42001800U) /**< \brief (SERCOM4) SPI Control Register A */ +#define REG_SERCOM4_USART_CTRLA (0x42001800U) /**< \brief (SERCOM4) USART Control Register A */ +#define REG_SERCOM4_I2CM_CTRLB (0x42001804U) /**< \brief (SERCOM4) I2CM Control Register B */ +#define REG_SERCOM4_I2CS_CTRLB (0x42001804U) /**< \brief (SERCOM4) I2CS Control Register B */ +#define REG_SERCOM4_SPI_CTRLB (0x42001804U) /**< \brief (SERCOM4) SPI Control Register B */ +#define REG_SERCOM4_USART_CTRLB (0x42001804U) /**< \brief (SERCOM4) USART Control Register B */ +#define REG_SERCOM4_I2CM_DBGCTRL (0x42001808U) /**< \brief (SERCOM4) I2CM Debug Register */ +#define REG_SERCOM4_SPI_DBGCTRL (0x42001808U) /**< \brief (SERCOM4) SPI Debug Register */ +#define REG_SERCOM4_USART_DBGCTRL (0x42001808U) /**< \brief (SERCOM4) USART Debug Register */ +#define REG_SERCOM4_I2CM_BAUD (0x4200180AU) /**< \brief (SERCOM4) I2CM Baud Rate Register */ +#define REG_SERCOM4_SPI_BAUD (0x4200180AU) /**< \brief (SERCOM4) SPI Baud Rate Register */ +#define REG_SERCOM4_USART_BAUD (0x4200180AU) /**< \brief (SERCOM4) USART Baud Rate Register */ +#define REG_SERCOM4_I2CM_INTENCLR (0x4200180CU) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear Register */ +#define REG_SERCOM4_I2CS_INTENCLR (0x4200180CU) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear Register */ +#define REG_SERCOM4_SPI_INTENCLR (0x4200180CU) /**< \brief (SERCOM4) SPI Interrupt Enable Clear Register */ +#define REG_SERCOM4_USART_INTENCLR (0x4200180CU) /**< \brief (SERCOM4) USART Interrupt Enable Clear Register */ +#define REG_SERCOM4_I2CM_INTENSET (0x4200180DU) /**< \brief (SERCOM4) I2CM Interrupt Enable Set Register */ +#define REG_SERCOM4_I2CS_INTENSET (0x4200180DU) /**< \brief (SERCOM4) I2CS Interrupt Enable Set Register */ +#define REG_SERCOM4_SPI_INTENSET (0x4200180DU) /**< \brief (SERCOM4) SPI Interrupt Enable Set Register */ +#define REG_SERCOM4_USART_INTENSET (0x4200180DU) /**< \brief (SERCOM4) USART Interrupt Enable Set Register */ +#define REG_SERCOM4_I2CM_INTFLAG (0x4200180EU) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear Register */ +#define REG_SERCOM4_I2CS_INTFLAG (0x4200180EU) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear Register */ +#define REG_SERCOM4_SPI_INTFLAG (0x4200180EU) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear Register */ +#define REG_SERCOM4_USART_INTFLAG (0x4200180EU) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear Register */ +#define REG_SERCOM4_I2CM_STATUS (0x42001810U) /**< \brief (SERCOM4) I2CM Status Register */ +#define REG_SERCOM4_I2CS_STATUS (0x42001810U) /**< \brief (SERCOM4) I2CS Status Register */ +#define REG_SERCOM4_SPI_STATUS (0x42001810U) /**< \brief (SERCOM4) SPI Status Register */ +#define REG_SERCOM4_USART_STATUS (0x42001810U) /**< \brief (SERCOM4) USART Status Register */ +#define REG_SERCOM4_I2CM_ADDR (0x42001814U) /**< \brief (SERCOM4) I2CM Address Register */ +#define REG_SERCOM4_I2CS_ADDR (0x42001814U) /**< \brief (SERCOM4) I2CS Address Register */ +#define REG_SERCOM4_SPI_ADDR (0x42001814U) /**< \brief (SERCOM4) SPI Address Register */ +#define REG_SERCOM4_I2CM_DATA (0x42001818U) /**< \brief (SERCOM4) I2CM Data Register */ +#define REG_SERCOM4_I2CS_DATA (0x42001818U) /**< \brief (SERCOM4) I2CS Data Register */ +#define REG_SERCOM4_SPI_DATA (0x42001818U) /**< \brief (SERCOM4) SPI Data Register */ +#define REG_SERCOM4_USART_DATA (0x42001818U) /**< \brief (SERCOM4) USART Data Register */ +#else +#define REG_SERCOM4_I2CM_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) I2CM Control Register A */ +#define REG_SERCOM4_I2CS_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) I2CS Control Register A */ +#define REG_SERCOM4_SPI_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) SPI Control Register A */ +#define REG_SERCOM4_USART_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) USART Control Register A */ +#define REG_SERCOM4_I2CM_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) I2CM Control Register B */ +#define REG_SERCOM4_I2CS_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) I2CS Control Register B */ +#define REG_SERCOM4_SPI_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) SPI Control Register B */ +#define REG_SERCOM4_USART_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) USART Control Register B */ +#define REG_SERCOM4_I2CM_DBGCTRL (*(RwReg8 *)0x42001808U) /**< \brief (SERCOM4) I2CM Debug Register */ +#define REG_SERCOM4_SPI_DBGCTRL (*(RwReg8 *)0x42001808U) /**< \brief (SERCOM4) SPI Debug Register */ +#define REG_SERCOM4_USART_DBGCTRL (*(RwReg8 *)0x42001808U) /**< \brief (SERCOM4) USART Debug Register */ +#define REG_SERCOM4_I2CM_BAUD (*(RwReg16*)0x4200180AU) /**< \brief (SERCOM4) I2CM Baud Rate Register */ +#define REG_SERCOM4_SPI_BAUD (*(RwReg8 *)0x4200180AU) /**< \brief (SERCOM4) SPI Baud Rate Register */ +#define REG_SERCOM4_USART_BAUD (*(RwReg16*)0x4200180AU) /**< \brief (SERCOM4) USART Baud Rate Register */ +#define REG_SERCOM4_I2CM_INTENCLR (*(RwReg8 *)0x4200180CU) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear Register */ +#define REG_SERCOM4_I2CS_INTENCLR (*(RwReg8 *)0x4200180CU) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear Register */ +#define REG_SERCOM4_SPI_INTENCLR (*(RwReg8 *)0x4200180CU) /**< \brief (SERCOM4) SPI Interrupt Enable Clear Register */ +#define REG_SERCOM4_USART_INTENCLR (*(RwReg8 *)0x4200180CU) /**< \brief (SERCOM4) USART Interrupt Enable Clear Register */ +#define REG_SERCOM4_I2CM_INTENSET (*(RwReg8 *)0x4200180DU) /**< \brief (SERCOM4) I2CM Interrupt Enable Set Register */ +#define REG_SERCOM4_I2CS_INTENSET (*(RwReg8 *)0x4200180DU) /**< \brief (SERCOM4) I2CS Interrupt Enable Set Register */ +#define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x4200180DU) /**< \brief (SERCOM4) SPI Interrupt Enable Set Register */ +#define REG_SERCOM4_USART_INTENSET (*(RwReg8 *)0x4200180DU) /**< \brief (SERCOM4) USART Interrupt Enable Set Register */ +#define REG_SERCOM4_I2CM_INTFLAG (*(RwReg8 *)0x4200180EU) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear Register */ +#define REG_SERCOM4_I2CS_INTFLAG (*(RwReg8 *)0x4200180EU) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear Register */ +#define REG_SERCOM4_SPI_INTFLAG (*(RwReg8 *)0x4200180EU) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear Register */ +#define REG_SERCOM4_USART_INTFLAG (*(RwReg8 *)0x4200180EU) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear Register */ +#define REG_SERCOM4_I2CM_STATUS (*(RwReg16*)0x42001810U) /**< \brief (SERCOM4) I2CM Status Register */ +#define REG_SERCOM4_I2CS_STATUS (*(RwReg16*)0x42001810U) /**< \brief (SERCOM4) I2CS Status Register */ +#define REG_SERCOM4_SPI_STATUS (*(RwReg16*)0x42001810U) /**< \brief (SERCOM4) SPI Status Register */ +#define REG_SERCOM4_USART_STATUS (*(RwReg16*)0x42001810U) /**< \brief (SERCOM4) USART Status Register */ +#define REG_SERCOM4_I2CM_ADDR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) I2CM Address Register */ +#define REG_SERCOM4_I2CS_ADDR (*(RwReg *)0x42001814U) /**< \brief (SERCOM4) I2CS Address Register */ +#define REG_SERCOM4_SPI_ADDR (*(RwReg *)0x42001814U) /**< \brief (SERCOM4) SPI Address Register */ +#define REG_SERCOM4_I2CM_DATA (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) I2CM Data Register */ +#define REG_SERCOM4_I2CS_DATA (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) I2CS Data Register */ +#define REG_SERCOM4_SPI_DATA (*(RwReg16*)0x42001818U) /**< \brief (SERCOM4) SPI Data Register */ +#define REG_SERCOM4_USART_DATA (*(RwReg16*)0x42001818U) /**< \brief (SERCOM4) USART Data Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM4 peripheral ========== */ +#define SERCOM4_GCLK_ID_CORE 17 +#define SERCOM4_GCLK_ID_SLOW 12 +#define SERCOM4_INT_MSB 3 +#define SERCOM4_PMSB 3 + +#endif /* _SAMD20_SERCOM4_INSTANCE_ */
diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_sercom5.h b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_sercom5.h new file mode 100644 index 0000000..5bc469f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_sercom5.h
@@ -0,0 +1,132 @@ +/** + * \file + * + * \brief Instance description for SERCOM5 + * + * Copyright (c) 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD20_SERCOM5_INSTANCE_ +#define _SAMD20_SERCOM5_INSTANCE_ + +/* ========== Register definition for SERCOM5 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM5_I2CM_CTRLA (0x42001C00U) /**< \brief (SERCOM5) I2CM Control Register A */ +#define REG_SERCOM5_I2CS_CTRLA (0x42001C00U) /**< \brief (SERCOM5) I2CS Control Register A */ +#define REG_SERCOM5_SPI_CTRLA (0x42001C00U) /**< \brief (SERCOM5) SPI Control Register A */ +#define REG_SERCOM5_USART_CTRLA (0x42001C00U) /**< \brief (SERCOM5) USART Control Register A */ +#define REG_SERCOM5_I2CM_CTRLB (0x42001C04U) /**< \brief (SERCOM5) I2CM Control Register B */ +#define REG_SERCOM5_I2CS_CTRLB (0x42001C04U) /**< \brief (SERCOM5) I2CS Control Register B */ +#define REG_SERCOM5_SPI_CTRLB (0x42001C04U) /**< \brief (SERCOM5) SPI Control Register B */ +#define REG_SERCOM5_USART_CTRLB (0x42001C04U) /**< \brief (SERCOM5) USART Control Register B */ +#define REG_SERCOM5_I2CM_DBGCTRL (0x42001C08U) /**< \brief (SERCOM5) I2CM Debug Register */ +#define REG_SERCOM5_SPI_DBGCTRL (0x42001C08U) /**< \brief (SERCOM5) SPI Debug Register */ +#define REG_SERCOM5_USART_DBGCTRL (0x42001C08U) /**< \brief (SERCOM5) USART Debug Register */ +#define REG_SERCOM5_I2CM_BAUD (0x42001C0AU) /**< \brief (SERCOM5) I2CM Baud Rate Register */ +#define REG_SERCOM5_SPI_BAUD (0x42001C0AU) /**< \brief (SERCOM5) SPI Baud Rate Register */ +#define REG_SERCOM5_USART_BAUD (0x42001C0AU) /**< \brief (SERCOM5) USART Baud Rate Register */ +#define REG_SERCOM5_I2CM_INTENCLR (0x42001C0CU) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear Register */ +#define REG_SERCOM5_I2CS_INTENCLR (0x42001C0CU) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear Register */ +#define REG_SERCOM5_SPI_INTENCLR (0x42001C0CU) /**< \brief (SERCOM5) SPI Interrupt Enable Clear Register */ +#define REG_SERCOM5_USART_INTENCLR (0x42001C0CU) /**< \brief (SERCOM5) USART Interrupt Enable Clear Register */ +#define REG_SERCOM5_I2CM_INTENSET (0x42001C0DU) /**< \brief (SERCOM5) I2CM Interrupt Enable Set Register */ +#define REG_SERCOM5_I2CS_INTENSET (0x42001C0DU) /**< \brief (SERCOM5) I2CS Interrupt Enable Set Register */ +#define REG_SERCOM5_SPI_INTENSET (0x42001C0DU) /**< \brief (SERCOM5) SPI Interrupt Enable Set Register */ +#define REG_SERCOM5_USART_INTENSET (0x42001C0DU) /**< \brief (SERCOM5) USART Interrupt Enable Set Register */ +#define REG_SERCOM5_I2CM_INTFLAG (0x42001C0EU) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear Register */ +#define REG_SERCOM5_I2CS_INTFLAG (0x42001C0EU) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear Register */ +#define REG_SERCOM5_SPI_INTFLAG (0x42001C0EU) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear Register */ +#define REG_SERCOM5_USART_INTFLAG (0x42001C0EU) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear Register */ +#define REG_SERCOM5_I2CM_STATUS (0x42001C10U) /**< \brief (SERCOM5) I2CM Status Register */ +#define REG_SERCOM5_I2CS_STATUS (0x42001C10U) /**< \brief (SERCOM5) I2CS Status Register */ +#define REG_SERCOM5_SPI_STATUS (0x42001C10U) /**< \brief (SERCOM5) SPI Status Register */ +#define REG_SERCOM5_USART_STATUS (0x42001C10U) /**< \brief (SERCOM5) USART Status Register */ +#define REG_SERCOM5_I2CM_ADDR (0x42001C14U) /**< \brief (SERCOM5) I2CM Address Register */ +#define REG_SERCOM5_I2CS_ADDR (0x42001C14U) /**< \brief (SERCOM5) I2CS Address Register */ +#define REG_SERCOM5_SPI_ADDR (0x42001C14U) /**< \brief (SERCOM5) SPI Address Register */ +#define REG_SERCOM5_I2CM_DATA (0x42001C18U) /**< \brief (SERCOM5) I2CM Data Register */ +#define REG_SERCOM5_I2CS_DATA (0x42001C18U) /**< \brief (SERCOM5) I2CS Data Register */ +#define REG_SERCOM5_SPI_DATA (0x42001C18U) /**< \brief (SERCOM5) SPI Data Register */ +#define REG_SERCOM5_USART_DATA (0x42001C18U) /**< \brief (SERCOM5) USART Data Register */ +#else +#define REG_SERCOM5_I2CM_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) I2CM Control Register A */ +#define REG_SERCOM5_I2CS_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) I2CS Control Register A */ +#define REG_SERCOM5_SPI_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) SPI Control Register A */ +#define REG_SERCOM5_USART_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) USART Control Register A */ +#define REG_SERCOM5_I2CM_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) I2CM Control Register B */ +#define REG_SERCOM5_I2CS_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) I2CS Control Register B */ +#define REG_SERCOM5_SPI_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) SPI Control Register B */ +#define REG_SERCOM5_USART_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) USART Control Register B */ +#define REG_SERCOM5_I2CM_DBGCTRL (*(RwReg8 *)0x42001C08U) /**< \brief (SERCOM5) I2CM Debug Register */ +#define REG_SERCOM5_SPI_DBGCTRL (*(RwReg8 *)0x42001C08U) /**< \brief (SERCOM5) SPI Debug Register */ +#define REG_SERCOM5_USART_DBGCTRL (*(RwReg8 *)0x42001C08U) /**< \brief (SERCOM5) USART Debug Register */ +#define REG_SERCOM5_I2CM_BAUD (*(RwReg16*)0x42001C0AU) /**< \brief (SERCOM5) I2CM Baud Rate Register */ +#define REG_SERCOM5_SPI_BAUD (*(RwReg8 *)0x42001C0AU) /**< \brief (SERCOM5) SPI Baud Rate Register */ +#define REG_SERCOM5_USART_BAUD (*(RwReg16*)0x42001C0AU) /**< \brief (SERCOM5) USART Baud Rate Register */ +#define REG_SERCOM5_I2CM_INTENCLR (*(RwReg8 *)0x42001C0CU) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear Register */ +#define REG_SERCOM5_I2CS_INTENCLR (*(RwReg8 *)0x42001C0CU) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear Register */ +#define REG_SERCOM5_SPI_INTENCLR (*(RwReg8 *)0x42001C0CU) /**< \brief (SERCOM5) SPI Interrupt Enable Clear Register */ +#define REG_SERCOM5_USART_INTENCLR (*(RwReg8 *)0x42001C0CU) /**< \brief (SERCOM5) USART Interrupt Enable Clear Register */ +#define REG_SERCOM5_I2CM_INTENSET (*(RwReg8 *)0x42001C0DU) /**< \brief (SERCOM5) I2CM Interrupt Enable Set Register */ +#define REG_SERCOM5_I2CS_INTENSET (*(RwReg8 *)0x42001C0DU) /**< \brief (SERCOM5) I2CS Interrupt Enable Set Register */ +#define REG_SERCOM5_SPI_INTENSET (*(RwReg8 *)0x42001C0DU) /**< \brief (SERCOM5) SPI Interrupt Enable Set Register */ +#define REG_SERCOM5_USART_INTENSET (*(RwReg8 *)0x42001C0DU) /**< \brief (SERCOM5) USART Interrupt Enable Set Register */ +#define REG_SERCOM5_I2CM_INTFLAG (*(RwReg8 *)0x42001C0EU) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear Register */ +#define REG_SERCOM5_I2CS_INTFLAG (*(RwReg8 *)0x42001C0EU) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear Register */ +#define REG_SERCOM5_SPI_INTFLAG (*(RwReg8 *)0x42001C0EU) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear Register */ +#define REG_SERCOM5_USART_INTFLAG (*(RwReg8 *)0x42001C0EU) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear Register */ +#define REG_SERCOM5_I2CM_STATUS (*(RwReg16*)0x42001C10U) /**< \brief (SERCOM5) I2CM Status Register */ +#define REG_SERCOM5_I2CS_STATUS (*(RwReg16*)0x42001C10U) /**< \brief (SERCOM5) I2CS Status Register */ +#define REG_SERCOM5_SPI_STATUS (*(RwReg16*)0x42001C10U) /**< \brief (SERCOM5) SPI Status Register */ +#define REG_SERCOM5_USART_STATUS (*(RwReg16*)0x42001C10U) /**< \brief (SERCOM5) USART Status Register */ +#define REG_SERCOM5_I2CM_ADDR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) I2CM Address Register */ +#define REG_SERCOM5_I2CS_ADDR (*(RwReg *)0x42001C14U) /**< \brief (SERCOM5) I2CS Address Register */ +#define REG_SERCOM5_SPI_ADDR (*(RwReg *)0x42001C14U) /**< \brief (SERCOM5) SPI Address Register */ +#define REG_SERCOM5_I2CM_DATA (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) I2CM Data Register */ +#define REG_SERCOM5_I2CS_DATA (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) I2CS Data Register */ +#define REG_SERCOM5_SPI_DATA (*(RwReg16*)0x42001C18U) /**< \brief (SERCOM5) SPI Data Register */ +#define REG_SERCOM5_USART_DATA (*(RwReg16*)0x42001C18U) /**< \brief (SERCOM5) USART Data Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM5 peripheral ========== */ +#define SERCOM5_GCLK_ID_CORE 18 +#define SERCOM5_GCLK_ID_SLOW 12 +#define SERCOM5_INT_MSB 3 +#define SERCOM5_PMSB 3 + +#endif /* _SAMD20_SERCOM5_INSTANCE_ */
diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_sysctrl.h b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_sysctrl.h new file mode 100644 index 0000000..afbac1d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_sysctrl.h
@@ -0,0 +1,114 @@ +/** + * \file + * + * \brief Instance description for SYSCTRL + * + * Copyright (c) 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD20_SYSCTRL_INSTANCE_ +#define _SAMD20_SYSCTRL_INSTANCE_ + +/* ========== Register definition for SYSCTRL peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SYSCTRL_INTENCLR (0x40000800U) /**< \brief (SYSCTRL) Interrupt Enable Clear Register */ +#define REG_SYSCTRL_INTENSET (0x40000804U) /**< \brief (SYSCTRL) Interrupt Enable Set Register */ +#define REG_SYSCTRL_INTFLAG (0x40000808U) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear Register */ +#define REG_SYSCTRL_PCLKSR (0x4000080CU) /**< \brief (SYSCTRL) Power and Clocks Status Register */ +#define REG_SYSCTRL_XOSC (0x40000810U) /**< \brief (SYSCTRL) XOSC Control Register */ +#define REG_SYSCTRL_XOSC32K (0x40000814U) /**< \brief (SYSCTRL) XOSC32K Control Register */ +#define REG_SYSCTRL_OSC32K (0x40000818U) /**< \brief (SYSCTRL) OSC32K Control Register */ +#define REG_SYSCTRL_OSCULP32K (0x4000081CU) /**< \brief (SYSCTRL) OSCULP32K Control Register */ +#define REG_SYSCTRL_OSC8M (0x40000820U) /**< \brief (SYSCTRL) OSC8M Control Register A */ +#define REG_SYSCTRL_DFLLCTRL (0x40000824U) /**< \brief (SYSCTRL) DFLL Config Register */ +#define REG_SYSCTRL_DFLLVAL (0x40000828U) /**< \brief (SYSCTRL) DFLL Calibration Value Register */ +#define REG_SYSCTRL_DFLLMUL (0x4000082CU) /**< \brief (SYSCTRL) DFLL Multiplier Register */ +#define REG_SYSCTRL_DFLLSYNC (0x40000830U) /**< \brief (SYSCTRL) DFLL Synchronization Register */ +#define REG_SYSCTRL_BOD33 (0x40000834U) /**< \brief (SYSCTRL) BOD33 Control Register */ +#define REG_SYSCTRL_BOD12 (0x40000838U) /**< \brief (SYSCTRL) BOD12 Control Register */ +#define REG_SYSCTRL_VREG (0x4000083CU) /**< \brief (SYSCTRL) VREG Control Register */ +#define REG_SYSCTRL_VREF (0x40000840U) /**< \brief (SYSCTRL) VREF Control Register A */ +#else +#define REG_SYSCTRL_INTENCLR (*(RwReg *)0x40000800U) /**< \brief (SYSCTRL) Interrupt Enable Clear Register */ +#define REG_SYSCTRL_INTENSET (*(RwReg *)0x40000804U) /**< \brief (SYSCTRL) Interrupt Enable Set Register */ +#define REG_SYSCTRL_INTFLAG (*(RwReg *)0x40000808U) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear Register */ +#define REG_SYSCTRL_PCLKSR (*(RoReg *)0x4000080CU) /**< \brief (SYSCTRL) Power and Clocks Status Register */ +#define REG_SYSCTRL_XOSC (*(RwReg16*)0x40000810U) /**< \brief (SYSCTRL) XOSC Control Register */ +#define REG_SYSCTRL_XOSC32K (*(RwReg16*)0x40000814U) /**< \brief (SYSCTRL) XOSC32K Control Register */ +#define REG_SYSCTRL_OSC32K (*(RwReg *)0x40000818U) /**< \brief (SYSCTRL) OSC32K Control Register */ +#define REG_SYSCTRL_OSCULP32K (*(RwReg8 *)0x4000081CU) /**< \brief (SYSCTRL) OSCULP32K Control Register */ +#define REG_SYSCTRL_OSC8M (*(RwReg *)0x40000820U) /**< \brief (SYSCTRL) OSC8M Control Register A */ +#define REG_SYSCTRL_DFLLCTRL (*(RwReg16*)0x40000824U) /**< \brief (SYSCTRL) DFLL Config Register */ +#define REG_SYSCTRL_DFLLVAL (*(RwReg *)0x40000828U) /**< \brief (SYSCTRL) DFLL Calibration Value Register */ +#define REG_SYSCTRL_DFLLMUL (*(RwReg *)0x4000082CU) /**< \brief (SYSCTRL) DFLL Multiplier Register */ +#define REG_SYSCTRL_DFLLSYNC (*(RwReg8 *)0x40000830U) /**< \brief (SYSCTRL) DFLL Synchronization Register */ +#define REG_SYSCTRL_BOD33 (*(RwReg *)0x40000834U) /**< \brief (SYSCTRL) BOD33 Control Register */ +#define REG_SYSCTRL_BOD12 (*(RwReg *)0x40000838U) /**< \brief (SYSCTRL) BOD12 Control Register */ +#define REG_SYSCTRL_VREG (*(RwReg16*)0x4000083CU) /**< \brief (SYSCTRL) VREG Control Register */ +#define REG_SYSCTRL_VREF (*(RwReg *)0x40000840U) /**< \brief (SYSCTRL) VREF Control Register A */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SYSCTRL peripheral ========== */ +#define SYSCTRL_BGAP_CALIB_MSB 11 +#define SYSCTRL_BOD12_CALIB_MSB 4 +#define SYSCTRL_BOD33_CALIB_MSB 5 +#define SYSCTRL_DFLL48M_COARSE_MSB 4 +#define SYSCTRL_DFLL48M_FINE_MSB 7 +#define SYSCTRL_DFLL48M_TESTEN_MSB 1 +#define SYSCTRL_GCLK_ID_DFLL48 0 +#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6 +#define SYSCTRL_POR33_ENTEST_MSB 1 +#define SYSCTRL_ULPVREF_DIVLEV_MSB 3 +#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1 +#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2 +#define SYSCTRL_VREF_CONTROL_MSB 48 +#define SYSCTRL_VREF_STATUS_MSB 7 +#define SYSCTRL_VREG_LEVEL_MSB 2 +#define SYSCTRL_BOD12_VERSION 0x110 +#define SYSCTRL_BOD33_VERSION 0x110 +#define SYSCTRL_DFLL48M_VERSION 0x200 +#define SYSCTRL_GCLK_VERSION 0x200 +#define SYSCTRL_OSCULP32K_VERSION 0x110 +#define SYSCTRL_OSC8M_VERSION 0x110 +#define SYSCTRL_OSC32K_VERSION 0x110 +#define SYSCTRL_VREF_VERSION 0x200 +#define SYSCTRL_VREG_VERSION 0x200 +#define SYSCTRL_XOSC_VERSION 0x110 +#define SYSCTRL_XOSC32K_VERSION 0x110 + +#endif /* _SAMD20_SYSCTRL_INSTANCE_ */
diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_tc0.h b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_tc0.h new file mode 100644 index 0000000..1ec47f4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_tc0.h
@@ -0,0 +1,106 @@ +/** + * \file + * + * \brief Instance description for TC0 + * + * Copyright (c) 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD20_TC0_INSTANCE_ +#define _SAMD20_TC0_INSTANCE_ + +/* ========== Register definition for TC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC0_CTRLA (0x42002000U) /**< \brief (TC0) Control A Register */ +#define REG_TC0_READREQ (0x42002002U) /**< \brief (TC0) Read Request Register */ +#define REG_TC0_CTRLBCLR (0x42002004U) /**< \brief (TC0) Control B Clear Register */ +#define REG_TC0_CTRLBSET (0x42002005U) /**< \brief (TC0) Control B Set Register */ +#define REG_TC0_CTRLC (0x42002006U) /**< \brief (TC0) Control C Register */ +#define REG_TC0_DBGCTRL (0x42002008U) /**< \brief (TC0) Debug Register */ +#define REG_TC0_EVCTRL (0x4200200AU) /**< \brief (TC0) Event Control Register */ +#define REG_TC0_INTENCLR (0x4200200CU) /**< \brief (TC0) Interrupt Enable Clear Register */ +#define REG_TC0_INTENSET (0x4200200DU) /**< \brief (TC0) Interrupt Enable Set Register */ +#define REG_TC0_INTFLAG (0x4200200EU) /**< \brief (TC0) Interrupt Flag Status and Clear Register */ +#define REG_TC0_STATUS (0x4200200FU) /**< \brief (TC0) Status Register */ +#define REG_TC0_COUNT8_COUNT (0x42002010U) /**< \brief (TC0) COUNT8 Count Register */ +#define REG_TC0_COUNT16_COUNT (0x42002010U) /**< \brief (TC0) COUNT16 Count Register */ +#define REG_TC0_COUNT32_COUNT (0x42002010U) /**< \brief (TC0) COUNT32 Count Register */ +#define REG_TC0_COUNT8_PER (0x42002014U) /**< \brief (TC0) COUNT8 Period Register */ +#define REG_TC0_COUNT32_PER (0x42002014U) /**< \brief (TC0) COUNT32 Period Register */ +#define REG_TC0_COUNT8_CC0 (0x42002018U) /**< \brief (TC0) COUNT8 Compare and Capture Register 0 */ +#define REG_TC0_COUNT8_CC1 (0x42002019U) /**< \brief (TC0) COUNT8 Compare and Capture Register 1 */ +#define REG_TC0_COUNT16_CC0 (0x42002018U) /**< \brief (TC0) COUNT16 Compare and Capture Register 0 */ +#define REG_TC0_COUNT16_CC1 (0x4200201AU) /**< \brief (TC0) COUNT16 Compare and Capture Register 1 */ +#define REG_TC0_COUNT32_CC0 (0x42002018U) /**< \brief (TC0) COUNT32 Compare and Capture Register 0 */ +#define REG_TC0_COUNT32_CC1 (0x4200201CU) /**< \brief (TC0) COUNT32 Compare and Capture Register 1 */ +#else +#define REG_TC0_CTRLA (*(RwReg16*)0x42002000U) /**< \brief (TC0) Control A Register */ +#define REG_TC0_READREQ (*(RwReg16*)0x42002002U) /**< \brief (TC0) Read Request Register */ +#define REG_TC0_CTRLBCLR (*(RwReg8 *)0x42002004U) /**< \brief (TC0) Control B Clear Register */ +#define REG_TC0_CTRLBSET (*(RwReg8 *)0x42002005U) /**< \brief (TC0) Control B Set Register */ +#define REG_TC0_CTRLC (*(RwReg8 *)0x42002006U) /**< \brief (TC0) Control C Register */ +#define REG_TC0_DBGCTRL (*(RwReg8 *)0x42002008U) /**< \brief (TC0) Debug Register */ +#define REG_TC0_EVCTRL (*(RwReg16*)0x4200200AU) /**< \brief (TC0) Event Control Register */ +#define REG_TC0_INTENCLR (*(RwReg8 *)0x4200200CU) /**< \brief (TC0) Interrupt Enable Clear Register */ +#define REG_TC0_INTENSET (*(RwReg8 *)0x4200200DU) /**< \brief (TC0) Interrupt Enable Set Register */ +#define REG_TC0_INTFLAG (*(RwReg8 *)0x4200200EU) /**< \brief (TC0) Interrupt Flag Status and Clear Register */ +#define REG_TC0_STATUS (*(RoReg8 *)0x4200200FU) /**< \brief (TC0) Status Register */ +#define REG_TC0_COUNT8_COUNT (*(RwReg8 *)0x42002010U) /**< \brief (TC0) COUNT8 Count Register */ +#define REG_TC0_COUNT16_COUNT (*(RwReg16*)0x42002010U) /**< \brief (TC0) COUNT16 Count Register */ +#define REG_TC0_COUNT32_COUNT (*(RwReg *)0x42002010U) /**< \brief (TC0) COUNT32 Count Register */ +#define REG_TC0_COUNT8_PER (*(RwReg8 *)0x42002014U) /**< \brief (TC0) COUNT8 Period Register */ +#define REG_TC0_COUNT32_PER (*(RwReg *)0x42002014U) /**< \brief (TC0) COUNT32 Period Register */ +#define REG_TC0_COUNT8_CC0 (*(RwReg8 *)0x42002018U) /**< \brief (TC0) COUNT8 Compare and Capture Register 0 */ +#define REG_TC0_COUNT8_CC1 (*(RwReg8 *)0x42002019U) /**< \brief (TC0) COUNT8 Compare and Capture Register 1 */ +#define REG_TC0_COUNT16_CC0 (*(RwReg16*)0x42002018U) /**< \brief (TC0) COUNT16 Compare and Capture Register 0 */ +#define REG_TC0_COUNT16_CC1 (*(RwReg16*)0x4200201AU) /**< \brief (TC0) COUNT16 Compare and Capture Register 1 */ +#define REG_TC0_COUNT32_CC0 (*(RwReg *)0x42002018U) /**< \brief (TC0) COUNT32 Compare and Capture Register 0 */ +#define REG_TC0_COUNT32_CC1 (*(RwReg *)0x4200201CU) /**< \brief (TC0) COUNT32 Compare and Capture Register 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC0 peripheral ========== */ +#define TC0_CC8_NUM 2 +#define TC0_CC16_NUM 2 +#define TC0_CC32_NUM 2 +#define TC0_DITHERING_EXT 0 +#define TC0_GCLK_ID 19 +#define TC0_OW_NUM 2 +#define TC0_PERIOD_EXT 0 +#define TC0_SHADOW_EXT 0 + +#endif /* _SAMD20_TC0_INSTANCE_ */
diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_tc1.h b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_tc1.h new file mode 100644 index 0000000..f5dbf4f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_tc1.h
@@ -0,0 +1,106 @@ +/** + * \file + * + * \brief Instance description for TC1 + * + * Copyright (c) 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD20_TC1_INSTANCE_ +#define _SAMD20_TC1_INSTANCE_ + +/* ========== Register definition for TC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC1_CTRLA (0x42002400U) /**< \brief (TC1) Control A Register */ +#define REG_TC1_READREQ (0x42002402U) /**< \brief (TC1) Read Request Register */ +#define REG_TC1_CTRLBCLR (0x42002404U) /**< \brief (TC1) Control B Clear Register */ +#define REG_TC1_CTRLBSET (0x42002405U) /**< \brief (TC1) Control B Set Register */ +#define REG_TC1_CTRLC (0x42002406U) /**< \brief (TC1) Control C Register */ +#define REG_TC1_DBGCTRL (0x42002408U) /**< \brief (TC1) Debug Register */ +#define REG_TC1_EVCTRL (0x4200240AU) /**< \brief (TC1) Event Control Register */ +#define REG_TC1_INTENCLR (0x4200240CU) /**< \brief (TC1) Interrupt Enable Clear Register */ +#define REG_TC1_INTENSET (0x4200240DU) /**< \brief (TC1) Interrupt Enable Set Register */ +#define REG_TC1_INTFLAG (0x4200240EU) /**< \brief (TC1) Interrupt Flag Status and Clear Register */ +#define REG_TC1_STATUS (0x4200240FU) /**< \brief (TC1) Status Register */ +#define REG_TC1_COUNT8_COUNT (0x42002410U) /**< \brief (TC1) COUNT8 Count Register */ +#define REG_TC1_COUNT16_COUNT (0x42002410U) /**< \brief (TC1) COUNT16 Count Register */ +#define REG_TC1_COUNT32_COUNT (0x42002410U) /**< \brief (TC1) COUNT32 Count Register */ +#define REG_TC1_COUNT8_PER (0x42002414U) /**< \brief (TC1) COUNT8 Period Register */ +#define REG_TC1_COUNT32_PER (0x42002414U) /**< \brief (TC1) COUNT32 Period Register */ +#define REG_TC1_COUNT8_CC0 (0x42002418U) /**< \brief (TC1) COUNT8 Compare and Capture Register 0 */ +#define REG_TC1_COUNT8_CC1 (0x42002419U) /**< \brief (TC1) COUNT8 Compare and Capture Register 1 */ +#define REG_TC1_COUNT16_CC0 (0x42002418U) /**< \brief (TC1) COUNT16 Compare and Capture Register 0 */ +#define REG_TC1_COUNT16_CC1 (0x4200241AU) /**< \brief (TC1) COUNT16 Compare and Capture Register 1 */ +#define REG_TC1_COUNT32_CC0 (0x42002418U) /**< \brief (TC1) COUNT32 Compare and Capture Register 0 */ +#define REG_TC1_COUNT32_CC1 (0x4200241CU) /**< \brief (TC1) COUNT32 Compare and Capture Register 1 */ +#else +#define REG_TC1_CTRLA (*(RwReg16*)0x42002400U) /**< \brief (TC1) Control A Register */ +#define REG_TC1_READREQ (*(RwReg16*)0x42002402U) /**< \brief (TC1) Read Request Register */ +#define REG_TC1_CTRLBCLR (*(RwReg8 *)0x42002404U) /**< \brief (TC1) Control B Clear Register */ +#define REG_TC1_CTRLBSET (*(RwReg8 *)0x42002405U) /**< \brief (TC1) Control B Set Register */ +#define REG_TC1_CTRLC (*(RwReg8 *)0x42002406U) /**< \brief (TC1) Control C Register */ +#define REG_TC1_DBGCTRL (*(RwReg8 *)0x42002408U) /**< \brief (TC1) Debug Register */ +#define REG_TC1_EVCTRL (*(RwReg16*)0x4200240AU) /**< \brief (TC1) Event Control Register */ +#define REG_TC1_INTENCLR (*(RwReg8 *)0x4200240CU) /**< \brief (TC1) Interrupt Enable Clear Register */ +#define REG_TC1_INTENSET (*(RwReg8 *)0x4200240DU) /**< \brief (TC1) Interrupt Enable Set Register */ +#define REG_TC1_INTFLAG (*(RwReg8 *)0x4200240EU) /**< \brief (TC1) Interrupt Flag Status and Clear Register */ +#define REG_TC1_STATUS (*(RoReg8 *)0x4200240FU) /**< \brief (TC1) Status Register */ +#define REG_TC1_COUNT8_COUNT (*(RwReg8 *)0x42002410U) /**< \brief (TC1) COUNT8 Count Register */ +#define REG_TC1_COUNT16_COUNT (*(RwReg16*)0x42002410U) /**< \brief (TC1) COUNT16 Count Register */ +#define REG_TC1_COUNT32_COUNT (*(RwReg *)0x42002410U) /**< \brief (TC1) COUNT32 Count Register */ +#define REG_TC1_COUNT8_PER (*(RwReg8 *)0x42002414U) /**< \brief (TC1) COUNT8 Period Register */ +#define REG_TC1_COUNT32_PER (*(RwReg *)0x42002414U) /**< \brief (TC1) COUNT32 Period Register */ +#define REG_TC1_COUNT8_CC0 (*(RwReg8 *)0x42002418U) /**< \brief (TC1) COUNT8 Compare and Capture Register 0 */ +#define REG_TC1_COUNT8_CC1 (*(RwReg8 *)0x42002419U) /**< \brief (TC1) COUNT8 Compare and Capture Register 1 */ +#define REG_TC1_COUNT16_CC0 (*(RwReg16*)0x42002418U) /**< \brief (TC1) COUNT16 Compare and Capture Register 0 */ +#define REG_TC1_COUNT16_CC1 (*(RwReg16*)0x4200241AU) /**< \brief (TC1) COUNT16 Compare and Capture Register 1 */ +#define REG_TC1_COUNT32_CC0 (*(RwReg *)0x42002418U) /**< \brief (TC1) COUNT32 Compare and Capture Register 0 */ +#define REG_TC1_COUNT32_CC1 (*(RwReg *)0x4200241CU) /**< \brief (TC1) COUNT32 Compare and Capture Register 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC1 peripheral ========== */ +#define TC1_CC8_NUM 2 +#define TC1_CC16_NUM 2 +#define TC1_CC32_NUM 2 +#define TC1_DITHERING_EXT 0 +#define TC1_GCLK_ID 19 +#define TC1_OW_NUM 2 +#define TC1_PERIOD_EXT 0 +#define TC1_SHADOW_EXT 0 + +#endif /* _SAMD20_TC1_INSTANCE_ */
diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_tc2.h b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_tc2.h new file mode 100644 index 0000000..addd7dd --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_tc2.h
@@ -0,0 +1,106 @@ +/** + * \file + * + * \brief Instance description for TC2 + * + * Copyright (c) 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD20_TC2_INSTANCE_ +#define _SAMD20_TC2_INSTANCE_ + +/* ========== Register definition for TC2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC2_CTRLA (0x42002800U) /**< \brief (TC2) Control A Register */ +#define REG_TC2_READREQ (0x42002802U) /**< \brief (TC2) Read Request Register */ +#define REG_TC2_CTRLBCLR (0x42002804U) /**< \brief (TC2) Control B Clear Register */ +#define REG_TC2_CTRLBSET (0x42002805U) /**< \brief (TC2) Control B Set Register */ +#define REG_TC2_CTRLC (0x42002806U) /**< \brief (TC2) Control C Register */ +#define REG_TC2_DBGCTRL (0x42002808U) /**< \brief (TC2) Debug Register */ +#define REG_TC2_EVCTRL (0x4200280AU) /**< \brief (TC2) Event Control Register */ +#define REG_TC2_INTENCLR (0x4200280CU) /**< \brief (TC2) Interrupt Enable Clear Register */ +#define REG_TC2_INTENSET (0x4200280DU) /**< \brief (TC2) Interrupt Enable Set Register */ +#define REG_TC2_INTFLAG (0x4200280EU) /**< \brief (TC2) Interrupt Flag Status and Clear Register */ +#define REG_TC2_STATUS (0x4200280FU) /**< \brief (TC2) Status Register */ +#define REG_TC2_COUNT8_COUNT (0x42002810U) /**< \brief (TC2) COUNT8 Count Register */ +#define REG_TC2_COUNT16_COUNT (0x42002810U) /**< \brief (TC2) COUNT16 Count Register */ +#define REG_TC2_COUNT32_COUNT (0x42002810U) /**< \brief (TC2) COUNT32 Count Register */ +#define REG_TC2_COUNT8_PER (0x42002814U) /**< \brief (TC2) COUNT8 Period Register */ +#define REG_TC2_COUNT32_PER (0x42002814U) /**< \brief (TC2) COUNT32 Period Register */ +#define REG_TC2_COUNT8_CC0 (0x42002818U) /**< \brief (TC2) COUNT8 Compare and Capture Register 0 */ +#define REG_TC2_COUNT8_CC1 (0x42002819U) /**< \brief (TC2) COUNT8 Compare and Capture Register 1 */ +#define REG_TC2_COUNT16_CC0 (0x42002818U) /**< \brief (TC2) COUNT16 Compare and Capture Register 0 */ +#define REG_TC2_COUNT16_CC1 (0x4200281AU) /**< \brief (TC2) COUNT16 Compare and Capture Register 1 */ +#define REG_TC2_COUNT32_CC0 (0x42002818U) /**< \brief (TC2) COUNT32 Compare and Capture Register 0 */ +#define REG_TC2_COUNT32_CC1 (0x4200281CU) /**< \brief (TC2) COUNT32 Compare and Capture Register 1 */ +#else +#define REG_TC2_CTRLA (*(RwReg16*)0x42002800U) /**< \brief (TC2) Control A Register */ +#define REG_TC2_READREQ (*(RwReg16*)0x42002802U) /**< \brief (TC2) Read Request Register */ +#define REG_TC2_CTRLBCLR (*(RwReg8 *)0x42002804U) /**< \brief (TC2) Control B Clear Register */ +#define REG_TC2_CTRLBSET (*(RwReg8 *)0x42002805U) /**< \brief (TC2) Control B Set Register */ +#define REG_TC2_CTRLC (*(RwReg8 *)0x42002806U) /**< \brief (TC2) Control C Register */ +#define REG_TC2_DBGCTRL (*(RwReg8 *)0x42002808U) /**< \brief (TC2) Debug Register */ +#define REG_TC2_EVCTRL (*(RwReg16*)0x4200280AU) /**< \brief (TC2) Event Control Register */ +#define REG_TC2_INTENCLR (*(RwReg8 *)0x4200280CU) /**< \brief (TC2) Interrupt Enable Clear Register */ +#define REG_TC2_INTENSET (*(RwReg8 *)0x4200280DU) /**< \brief (TC2) Interrupt Enable Set Register */ +#define REG_TC2_INTFLAG (*(RwReg8 *)0x4200280EU) /**< \brief (TC2) Interrupt Flag Status and Clear Register */ +#define REG_TC2_STATUS (*(RoReg8 *)0x4200280FU) /**< \brief (TC2) Status Register */ +#define REG_TC2_COUNT8_COUNT (*(RwReg8 *)0x42002810U) /**< \brief (TC2) COUNT8 Count Register */ +#define REG_TC2_COUNT16_COUNT (*(RwReg16*)0x42002810U) /**< \brief (TC2) COUNT16 Count Register */ +#define REG_TC2_COUNT32_COUNT (*(RwReg *)0x42002810U) /**< \brief (TC2) COUNT32 Count Register */ +#define REG_TC2_COUNT8_PER (*(RwReg8 *)0x42002814U) /**< \brief (TC2) COUNT8 Period Register */ +#define REG_TC2_COUNT32_PER (*(RwReg *)0x42002814U) /**< \brief (TC2) COUNT32 Period Register */ +#define REG_TC2_COUNT8_CC0 (*(RwReg8 *)0x42002818U) /**< \brief (TC2) COUNT8 Compare and Capture Register 0 */ +#define REG_TC2_COUNT8_CC1 (*(RwReg8 *)0x42002819U) /**< \brief (TC2) COUNT8 Compare and Capture Register 1 */ +#define REG_TC2_COUNT16_CC0 (*(RwReg16*)0x42002818U) /**< \brief (TC2) COUNT16 Compare and Capture Register 0 */ +#define REG_TC2_COUNT16_CC1 (*(RwReg16*)0x4200281AU) /**< \brief (TC2) COUNT16 Compare and Capture Register 1 */ +#define REG_TC2_COUNT32_CC0 (*(RwReg *)0x42002818U) /**< \brief (TC2) COUNT32 Compare and Capture Register 0 */ +#define REG_TC2_COUNT32_CC1 (*(RwReg *)0x4200281CU) /**< \brief (TC2) COUNT32 Compare and Capture Register 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC2 peripheral ========== */ +#define TC2_CC8_NUM 2 +#define TC2_CC16_NUM 2 +#define TC2_CC32_NUM 2 +#define TC2_DITHERING_EXT 0 +#define TC2_GCLK_ID 20 +#define TC2_OW_NUM 2 +#define TC2_PERIOD_EXT 0 +#define TC2_SHADOW_EXT 0 + +#endif /* _SAMD20_TC2_INSTANCE_ */
diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_tc3.h b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_tc3.h new file mode 100644 index 0000000..2e5648c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_tc3.h
@@ -0,0 +1,106 @@ +/** + * \file + * + * \brief Instance description for TC3 + * + * Copyright (c) 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD20_TC3_INSTANCE_ +#define _SAMD20_TC3_INSTANCE_ + +/* ========== Register definition for TC3 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC3_CTRLA (0x42002C00U) /**< \brief (TC3) Control A Register */ +#define REG_TC3_READREQ (0x42002C02U) /**< \brief (TC3) Read Request Register */ +#define REG_TC3_CTRLBCLR (0x42002C04U) /**< \brief (TC3) Control B Clear Register */ +#define REG_TC3_CTRLBSET (0x42002C05U) /**< \brief (TC3) Control B Set Register */ +#define REG_TC3_CTRLC (0x42002C06U) /**< \brief (TC3) Control C Register */ +#define REG_TC3_DBGCTRL (0x42002C08U) /**< \brief (TC3) Debug Register */ +#define REG_TC3_EVCTRL (0x42002C0AU) /**< \brief (TC3) Event Control Register */ +#define REG_TC3_INTENCLR (0x42002C0CU) /**< \brief (TC3) Interrupt Enable Clear Register */ +#define REG_TC3_INTENSET (0x42002C0DU) /**< \brief (TC3) Interrupt Enable Set Register */ +#define REG_TC3_INTFLAG (0x42002C0EU) /**< \brief (TC3) Interrupt Flag Status and Clear Register */ +#define REG_TC3_STATUS (0x42002C0FU) /**< \brief (TC3) Status Register */ +#define REG_TC3_COUNT8_COUNT (0x42002C10U) /**< \brief (TC3) COUNT8 Count Register */ +#define REG_TC3_COUNT16_COUNT (0x42002C10U) /**< \brief (TC3) COUNT16 Count Register */ +#define REG_TC3_COUNT32_COUNT (0x42002C10U) /**< \brief (TC3) COUNT32 Count Register */ +#define REG_TC3_COUNT8_PER (0x42002C14U) /**< \brief (TC3) COUNT8 Period Register */ +#define REG_TC3_COUNT32_PER (0x42002C14U) /**< \brief (TC3) COUNT32 Period Register */ +#define REG_TC3_COUNT8_CC0 (0x42002C18U) /**< \brief (TC3) COUNT8 Compare and Capture Register 0 */ +#define REG_TC3_COUNT8_CC1 (0x42002C19U) /**< \brief (TC3) COUNT8 Compare and Capture Register 1 */ +#define REG_TC3_COUNT16_CC0 (0x42002C18U) /**< \brief (TC3) COUNT16 Compare and Capture Register 0 */ +#define REG_TC3_COUNT16_CC1 (0x42002C1AU) /**< \brief (TC3) COUNT16 Compare and Capture Register 1 */ +#define REG_TC3_COUNT32_CC0 (0x42002C18U) /**< \brief (TC3) COUNT32 Compare and Capture Register 0 */ +#define REG_TC3_COUNT32_CC1 (0x42002C1CU) /**< \brief (TC3) COUNT32 Compare and Capture Register 1 */ +#else +#define REG_TC3_CTRLA (*(RwReg16*)0x42002C00U) /**< \brief (TC3) Control A Register */ +#define REG_TC3_READREQ (*(RwReg16*)0x42002C02U) /**< \brief (TC3) Read Request Register */ +#define REG_TC3_CTRLBCLR (*(RwReg8 *)0x42002C04U) /**< \brief (TC3) Control B Clear Register */ +#define REG_TC3_CTRLBSET (*(RwReg8 *)0x42002C05U) /**< \brief (TC3) Control B Set Register */ +#define REG_TC3_CTRLC (*(RwReg8 *)0x42002C06U) /**< \brief (TC3) Control C Register */ +#define REG_TC3_DBGCTRL (*(RwReg8 *)0x42002C08U) /**< \brief (TC3) Debug Register */ +#define REG_TC3_EVCTRL (*(RwReg16*)0x42002C0AU) /**< \brief (TC3) Event Control Register */ +#define REG_TC3_INTENCLR (*(RwReg8 *)0x42002C0CU) /**< \brief (TC3) Interrupt Enable Clear Register */ +#define REG_TC3_INTENSET (*(RwReg8 *)0x42002C0DU) /**< \brief (TC3) Interrupt Enable Set Register */ +#define REG_TC3_INTFLAG (*(RwReg8 *)0x42002C0EU) /**< \brief (TC3) Interrupt Flag Status and Clear Register */ +#define REG_TC3_STATUS (*(RoReg8 *)0x42002C0FU) /**< \brief (TC3) Status Register */ +#define REG_TC3_COUNT8_COUNT (*(RwReg8 *)0x42002C10U) /**< \brief (TC3) COUNT8 Count Register */ +#define REG_TC3_COUNT16_COUNT (*(RwReg16*)0x42002C10U) /**< \brief (TC3) COUNT16 Count Register */ +#define REG_TC3_COUNT32_COUNT (*(RwReg *)0x42002C10U) /**< \brief (TC3) COUNT32 Count Register */ +#define REG_TC3_COUNT8_PER (*(RwReg8 *)0x42002C14U) /**< \brief (TC3) COUNT8 Period Register */ +#define REG_TC3_COUNT32_PER (*(RwReg *)0x42002C14U) /**< \brief (TC3) COUNT32 Period Register */ +#define REG_TC3_COUNT8_CC0 (*(RwReg8 *)0x42002C18U) /**< \brief (TC3) COUNT8 Compare and Capture Register 0 */ +#define REG_TC3_COUNT8_CC1 (*(RwReg8 *)0x42002C19U) /**< \brief (TC3) COUNT8 Compare and Capture Register 1 */ +#define REG_TC3_COUNT16_CC0 (*(RwReg16*)0x42002C18U) /**< \brief (TC3) COUNT16 Compare and Capture Register 0 */ +#define REG_TC3_COUNT16_CC1 (*(RwReg16*)0x42002C1AU) /**< \brief (TC3) COUNT16 Compare and Capture Register 1 */ +#define REG_TC3_COUNT32_CC0 (*(RwReg *)0x42002C18U) /**< \brief (TC3) COUNT32 Compare and Capture Register 0 */ +#define REG_TC3_COUNT32_CC1 (*(RwReg *)0x42002C1CU) /**< \brief (TC3) COUNT32 Compare and Capture Register 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC3 peripheral ========== */ +#define TC3_CC8_NUM 2 +#define TC3_CC16_NUM 2 +#define TC3_CC32_NUM 2 +#define TC3_DITHERING_EXT 0 +#define TC3_GCLK_ID 20 +#define TC3_OW_NUM 2 +#define TC3_PERIOD_EXT 0 +#define TC3_SHADOW_EXT 0 + +#endif /* _SAMD20_TC3_INSTANCE_ */
diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_tc4.h b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_tc4.h new file mode 100644 index 0000000..a0cb706 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_tc4.h
@@ -0,0 +1,106 @@ +/** + * \file + * + * \brief Instance description for TC4 + * + * Copyright (c) 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD20_TC4_INSTANCE_ +#define _SAMD20_TC4_INSTANCE_ + +/* ========== Register definition for TC4 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC4_CTRLA (0x42003000U) /**< \brief (TC4) Control A Register */ +#define REG_TC4_READREQ (0x42003002U) /**< \brief (TC4) Read Request Register */ +#define REG_TC4_CTRLBCLR (0x42003004U) /**< \brief (TC4) Control B Clear Register */ +#define REG_TC4_CTRLBSET (0x42003005U) /**< \brief (TC4) Control B Set Register */ +#define REG_TC4_CTRLC (0x42003006U) /**< \brief (TC4) Control C Register */ +#define REG_TC4_DBGCTRL (0x42003008U) /**< \brief (TC4) Debug Register */ +#define REG_TC4_EVCTRL (0x4200300AU) /**< \brief (TC4) Event Control Register */ +#define REG_TC4_INTENCLR (0x4200300CU) /**< \brief (TC4) Interrupt Enable Clear Register */ +#define REG_TC4_INTENSET (0x4200300DU) /**< \brief (TC4) Interrupt Enable Set Register */ +#define REG_TC4_INTFLAG (0x4200300EU) /**< \brief (TC4) Interrupt Flag Status and Clear Register */ +#define REG_TC4_STATUS (0x4200300FU) /**< \brief (TC4) Status Register */ +#define REG_TC4_COUNT8_COUNT (0x42003010U) /**< \brief (TC4) COUNT8 Count Register */ +#define REG_TC4_COUNT16_COUNT (0x42003010U) /**< \brief (TC4) COUNT16 Count Register */ +#define REG_TC4_COUNT32_COUNT (0x42003010U) /**< \brief (TC4) COUNT32 Count Register */ +#define REG_TC4_COUNT8_PER (0x42003014U) /**< \brief (TC4) COUNT8 Period Register */ +#define REG_TC4_COUNT32_PER (0x42003014U) /**< \brief (TC4) COUNT32 Period Register */ +#define REG_TC4_COUNT8_CC0 (0x42003018U) /**< \brief (TC4) COUNT8 Compare and Capture Register 0 */ +#define REG_TC4_COUNT8_CC1 (0x42003019U) /**< \brief (TC4) COUNT8 Compare and Capture Register 1 */ +#define REG_TC4_COUNT16_CC0 (0x42003018U) /**< \brief (TC4) COUNT16 Compare and Capture Register 0 */ +#define REG_TC4_COUNT16_CC1 (0x4200301AU) /**< \brief (TC4) COUNT16 Compare and Capture Register 1 */ +#define REG_TC4_COUNT32_CC0 (0x42003018U) /**< \brief (TC4) COUNT32 Compare and Capture Register 0 */ +#define REG_TC4_COUNT32_CC1 (0x4200301CU) /**< \brief (TC4) COUNT32 Compare and Capture Register 1 */ +#else +#define REG_TC4_CTRLA (*(RwReg16*)0x42003000U) /**< \brief (TC4) Control A Register */ +#define REG_TC4_READREQ (*(RwReg16*)0x42003002U) /**< \brief (TC4) Read Request Register */ +#define REG_TC4_CTRLBCLR (*(RwReg8 *)0x42003004U) /**< \brief (TC4) Control B Clear Register */ +#define REG_TC4_CTRLBSET (*(RwReg8 *)0x42003005U) /**< \brief (TC4) Control B Set Register */ +#define REG_TC4_CTRLC (*(RwReg8 *)0x42003006U) /**< \brief (TC4) Control C Register */ +#define REG_TC4_DBGCTRL (*(RwReg8 *)0x42003008U) /**< \brief (TC4) Debug Register */ +#define REG_TC4_EVCTRL (*(RwReg16*)0x4200300AU) /**< \brief (TC4) Event Control Register */ +#define REG_TC4_INTENCLR (*(RwReg8 *)0x4200300CU) /**< \brief (TC4) Interrupt Enable Clear Register */ +#define REG_TC4_INTENSET (*(RwReg8 *)0x4200300DU) /**< \brief (TC4) Interrupt Enable Set Register */ +#define REG_TC4_INTFLAG (*(RwReg8 *)0x4200300EU) /**< \brief (TC4) Interrupt Flag Status and Clear Register */ +#define REG_TC4_STATUS (*(RoReg8 *)0x4200300FU) /**< \brief (TC4) Status Register */ +#define REG_TC4_COUNT8_COUNT (*(RwReg8 *)0x42003010U) /**< \brief (TC4) COUNT8 Count Register */ +#define REG_TC4_COUNT16_COUNT (*(RwReg16*)0x42003010U) /**< \brief (TC4) COUNT16 Count Register */ +#define REG_TC4_COUNT32_COUNT (*(RwReg *)0x42003010U) /**< \brief (TC4) COUNT32 Count Register */ +#define REG_TC4_COUNT8_PER (*(RwReg8 *)0x42003014U) /**< \brief (TC4) COUNT8 Period Register */ +#define REG_TC4_COUNT32_PER (*(RwReg *)0x42003014U) /**< \brief (TC4) COUNT32 Period Register */ +#define REG_TC4_COUNT8_CC0 (*(RwReg8 *)0x42003018U) /**< \brief (TC4) COUNT8 Compare and Capture Register 0 */ +#define REG_TC4_COUNT8_CC1 (*(RwReg8 *)0x42003019U) /**< \brief (TC4) COUNT8 Compare and Capture Register 1 */ +#define REG_TC4_COUNT16_CC0 (*(RwReg16*)0x42003018U) /**< \brief (TC4) COUNT16 Compare and Capture Register 0 */ +#define REG_TC4_COUNT16_CC1 (*(RwReg16*)0x4200301AU) /**< \brief (TC4) COUNT16 Compare and Capture Register 1 */ +#define REG_TC4_COUNT32_CC0 (*(RwReg *)0x42003018U) /**< \brief (TC4) COUNT32 Compare and Capture Register 0 */ +#define REG_TC4_COUNT32_CC1 (*(RwReg *)0x4200301CU) /**< \brief (TC4) COUNT32 Compare and Capture Register 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC4 peripheral ========== */ +#define TC4_CC8_NUM 2 +#define TC4_CC16_NUM 2 +#define TC4_CC32_NUM 2 +#define TC4_DITHERING_EXT 0 +#define TC4_GCLK_ID 21 +#define TC4_OW_NUM 2 +#define TC4_PERIOD_EXT 0 +#define TC4_SHADOW_EXT 0 + +#endif /* _SAMD20_TC4_INSTANCE_ */
diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_tc5.h b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_tc5.h new file mode 100644 index 0000000..c8cb90b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_tc5.h
@@ -0,0 +1,106 @@ +/** + * \file + * + * \brief Instance description for TC5 + * + * Copyright (c) 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD20_TC5_INSTANCE_ +#define _SAMD20_TC5_INSTANCE_ + +/* ========== Register definition for TC5 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC5_CTRLA (0x42003400U) /**< \brief (TC5) Control A Register */ +#define REG_TC5_READREQ (0x42003402U) /**< \brief (TC5) Read Request Register */ +#define REG_TC5_CTRLBCLR (0x42003404U) /**< \brief (TC5) Control B Clear Register */ +#define REG_TC5_CTRLBSET (0x42003405U) /**< \brief (TC5) Control B Set Register */ +#define REG_TC5_CTRLC (0x42003406U) /**< \brief (TC5) Control C Register */ +#define REG_TC5_DBGCTRL (0x42003408U) /**< \brief (TC5) Debug Register */ +#define REG_TC5_EVCTRL (0x4200340AU) /**< \brief (TC5) Event Control Register */ +#define REG_TC5_INTENCLR (0x4200340CU) /**< \brief (TC5) Interrupt Enable Clear Register */ +#define REG_TC5_INTENSET (0x4200340DU) /**< \brief (TC5) Interrupt Enable Set Register */ +#define REG_TC5_INTFLAG (0x4200340EU) /**< \brief (TC5) Interrupt Flag Status and Clear Register */ +#define REG_TC5_STATUS (0x4200340FU) /**< \brief (TC5) Status Register */ +#define REG_TC5_COUNT8_COUNT (0x42003410U) /**< \brief (TC5) COUNT8 Count Register */ +#define REG_TC5_COUNT16_COUNT (0x42003410U) /**< \brief (TC5) COUNT16 Count Register */ +#define REG_TC5_COUNT32_COUNT (0x42003410U) /**< \brief (TC5) COUNT32 Count Register */ +#define REG_TC5_COUNT8_PER (0x42003414U) /**< \brief (TC5) COUNT8 Period Register */ +#define REG_TC5_COUNT32_PER (0x42003414U) /**< \brief (TC5) COUNT32 Period Register */ +#define REG_TC5_COUNT8_CC0 (0x42003418U) /**< \brief (TC5) COUNT8 Compare and Capture Register 0 */ +#define REG_TC5_COUNT8_CC1 (0x42003419U) /**< \brief (TC5) COUNT8 Compare and Capture Register 1 */ +#define REG_TC5_COUNT16_CC0 (0x42003418U) /**< \brief (TC5) COUNT16 Compare and Capture Register 0 */ +#define REG_TC5_COUNT16_CC1 (0x4200341AU) /**< \brief (TC5) COUNT16 Compare and Capture Register 1 */ +#define REG_TC5_COUNT32_CC0 (0x42003418U) /**< \brief (TC5) COUNT32 Compare and Capture Register 0 */ +#define REG_TC5_COUNT32_CC1 (0x4200341CU) /**< \brief (TC5) COUNT32 Compare and Capture Register 1 */ +#else +#define REG_TC5_CTRLA (*(RwReg16*)0x42003400U) /**< \brief (TC5) Control A Register */ +#define REG_TC5_READREQ (*(RwReg16*)0x42003402U) /**< \brief (TC5) Read Request Register */ +#define REG_TC5_CTRLBCLR (*(RwReg8 *)0x42003404U) /**< \brief (TC5) Control B Clear Register */ +#define REG_TC5_CTRLBSET (*(RwReg8 *)0x42003405U) /**< \brief (TC5) Control B Set Register */ +#define REG_TC5_CTRLC (*(RwReg8 *)0x42003406U) /**< \brief (TC5) Control C Register */ +#define REG_TC5_DBGCTRL (*(RwReg8 *)0x42003408U) /**< \brief (TC5) Debug Register */ +#define REG_TC5_EVCTRL (*(RwReg16*)0x4200340AU) /**< \brief (TC5) Event Control Register */ +#define REG_TC5_INTENCLR (*(RwReg8 *)0x4200340CU) /**< \brief (TC5) Interrupt Enable Clear Register */ +#define REG_TC5_INTENSET (*(RwReg8 *)0x4200340DU) /**< \brief (TC5) Interrupt Enable Set Register */ +#define REG_TC5_INTFLAG (*(RwReg8 *)0x4200340EU) /**< \brief (TC5) Interrupt Flag Status and Clear Register */ +#define REG_TC5_STATUS (*(RoReg8 *)0x4200340FU) /**< \brief (TC5) Status Register */ +#define REG_TC5_COUNT8_COUNT (*(RwReg8 *)0x42003410U) /**< \brief (TC5) COUNT8 Count Register */ +#define REG_TC5_COUNT16_COUNT (*(RwReg16*)0x42003410U) /**< \brief (TC5) COUNT16 Count Register */ +#define REG_TC5_COUNT32_COUNT (*(RwReg *)0x42003410U) /**< \brief (TC5) COUNT32 Count Register */ +#define REG_TC5_COUNT8_PER (*(RwReg8 *)0x42003414U) /**< \brief (TC5) COUNT8 Period Register */ +#define REG_TC5_COUNT32_PER (*(RwReg *)0x42003414U) /**< \brief (TC5) COUNT32 Period Register */ +#define REG_TC5_COUNT8_CC0 (*(RwReg8 *)0x42003418U) /**< \brief (TC5) COUNT8 Compare and Capture Register 0 */ +#define REG_TC5_COUNT8_CC1 (*(RwReg8 *)0x42003419U) /**< \brief (TC5) COUNT8 Compare and Capture Register 1 */ +#define REG_TC5_COUNT16_CC0 (*(RwReg16*)0x42003418U) /**< \brief (TC5) COUNT16 Compare and Capture Register 0 */ +#define REG_TC5_COUNT16_CC1 (*(RwReg16*)0x4200341AU) /**< \brief (TC5) COUNT16 Compare and Capture Register 1 */ +#define REG_TC5_COUNT32_CC0 (*(RwReg *)0x42003418U) /**< \brief (TC5) COUNT32 Compare and Capture Register 0 */ +#define REG_TC5_COUNT32_CC1 (*(RwReg *)0x4200341CU) /**< \brief (TC5) COUNT32 Compare and Capture Register 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC5 peripheral ========== */ +#define TC5_CC8_NUM 2 +#define TC5_CC16_NUM 2 +#define TC5_CC32_NUM 2 +#define TC5_DITHERING_EXT 0 +#define TC5_GCLK_ID 21 +#define TC5_OW_NUM 2 +#define TC5_PERIOD_EXT 0 +#define TC5_SHADOW_EXT 0 + +#endif /* _SAMD20_TC5_INSTANCE_ */
diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_tc6.h b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_tc6.h new file mode 100644 index 0000000..c4ec54e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_tc6.h
@@ -0,0 +1,106 @@ +/** + * \file + * + * \brief Instance description for TC6 + * + * Copyright (c) 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD20_TC6_INSTANCE_ +#define _SAMD20_TC6_INSTANCE_ + +/* ========== Register definition for TC6 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC6_CTRLA (0x42003800U) /**< \brief (TC6) Control A Register */ +#define REG_TC6_READREQ (0x42003802U) /**< \brief (TC6) Read Request Register */ +#define REG_TC6_CTRLBCLR (0x42003804U) /**< \brief (TC6) Control B Clear Register */ +#define REG_TC6_CTRLBSET (0x42003805U) /**< \brief (TC6) Control B Set Register */ +#define REG_TC6_CTRLC (0x42003806U) /**< \brief (TC6) Control C Register */ +#define REG_TC6_DBGCTRL (0x42003808U) /**< \brief (TC6) Debug Register */ +#define REG_TC6_EVCTRL (0x4200380AU) /**< \brief (TC6) Event Control Register */ +#define REG_TC6_INTENCLR (0x4200380CU) /**< \brief (TC6) Interrupt Enable Clear Register */ +#define REG_TC6_INTENSET (0x4200380DU) /**< \brief (TC6) Interrupt Enable Set Register */ +#define REG_TC6_INTFLAG (0x4200380EU) /**< \brief (TC6) Interrupt Flag Status and Clear Register */ +#define REG_TC6_STATUS (0x4200380FU) /**< \brief (TC6) Status Register */ +#define REG_TC6_COUNT8_COUNT (0x42003810U) /**< \brief (TC6) COUNT8 Count Register */ +#define REG_TC6_COUNT16_COUNT (0x42003810U) /**< \brief (TC6) COUNT16 Count Register */ +#define REG_TC6_COUNT32_COUNT (0x42003810U) /**< \brief (TC6) COUNT32 Count Register */ +#define REG_TC6_COUNT8_PER (0x42003814U) /**< \brief (TC6) COUNT8 Period Register */ +#define REG_TC6_COUNT32_PER (0x42003814U) /**< \brief (TC6) COUNT32 Period Register */ +#define REG_TC6_COUNT8_CC0 (0x42003818U) /**< \brief (TC6) COUNT8 Compare and Capture Register 0 */ +#define REG_TC6_COUNT8_CC1 (0x42003819U) /**< \brief (TC6) COUNT8 Compare and Capture Register 1 */ +#define REG_TC6_COUNT16_CC0 (0x42003818U) /**< \brief (TC6) COUNT16 Compare and Capture Register 0 */ +#define REG_TC6_COUNT16_CC1 (0x4200381AU) /**< \brief (TC6) COUNT16 Compare and Capture Register 1 */ +#define REG_TC6_COUNT32_CC0 (0x42003818U) /**< \brief (TC6) COUNT32 Compare and Capture Register 0 */ +#define REG_TC6_COUNT32_CC1 (0x4200381CU) /**< \brief (TC6) COUNT32 Compare and Capture Register 1 */ +#else +#define REG_TC6_CTRLA (*(RwReg16*)0x42003800U) /**< \brief (TC6) Control A Register */ +#define REG_TC6_READREQ (*(RwReg16*)0x42003802U) /**< \brief (TC6) Read Request Register */ +#define REG_TC6_CTRLBCLR (*(RwReg8 *)0x42003804U) /**< \brief (TC6) Control B Clear Register */ +#define REG_TC6_CTRLBSET (*(RwReg8 *)0x42003805U) /**< \brief (TC6) Control B Set Register */ +#define REG_TC6_CTRLC (*(RwReg8 *)0x42003806U) /**< \brief (TC6) Control C Register */ +#define REG_TC6_DBGCTRL (*(RwReg8 *)0x42003808U) /**< \brief (TC6) Debug Register */ +#define REG_TC6_EVCTRL (*(RwReg16*)0x4200380AU) /**< \brief (TC6) Event Control Register */ +#define REG_TC6_INTENCLR (*(RwReg8 *)0x4200380CU) /**< \brief (TC6) Interrupt Enable Clear Register */ +#define REG_TC6_INTENSET (*(RwReg8 *)0x4200380DU) /**< \brief (TC6) Interrupt Enable Set Register */ +#define REG_TC6_INTFLAG (*(RwReg8 *)0x4200380EU) /**< \brief (TC6) Interrupt Flag Status and Clear Register */ +#define REG_TC6_STATUS (*(RoReg8 *)0x4200380FU) /**< \brief (TC6) Status Register */ +#define REG_TC6_COUNT8_COUNT (*(RwReg8 *)0x42003810U) /**< \brief (TC6) COUNT8 Count Register */ +#define REG_TC6_COUNT16_COUNT (*(RwReg16*)0x42003810U) /**< \brief (TC6) COUNT16 Count Register */ +#define REG_TC6_COUNT32_COUNT (*(RwReg *)0x42003810U) /**< \brief (TC6) COUNT32 Count Register */ +#define REG_TC6_COUNT8_PER (*(RwReg8 *)0x42003814U) /**< \brief (TC6) COUNT8 Period Register */ +#define REG_TC6_COUNT32_PER (*(RwReg *)0x42003814U) /**< \brief (TC6) COUNT32 Period Register */ +#define REG_TC6_COUNT8_CC0 (*(RwReg8 *)0x42003818U) /**< \brief (TC6) COUNT8 Compare and Capture Register 0 */ +#define REG_TC6_COUNT8_CC1 (*(RwReg8 *)0x42003819U) /**< \brief (TC6) COUNT8 Compare and Capture Register 1 */ +#define REG_TC6_COUNT16_CC0 (*(RwReg16*)0x42003818U) /**< \brief (TC6) COUNT16 Compare and Capture Register 0 */ +#define REG_TC6_COUNT16_CC1 (*(RwReg16*)0x4200381AU) /**< \brief (TC6) COUNT16 Compare and Capture Register 1 */ +#define REG_TC6_COUNT32_CC0 (*(RwReg *)0x42003818U) /**< \brief (TC6) COUNT32 Compare and Capture Register 0 */ +#define REG_TC6_COUNT32_CC1 (*(RwReg *)0x4200381CU) /**< \brief (TC6) COUNT32 Compare and Capture Register 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC6 peripheral ========== */ +#define TC6_CC8_NUM 2 +#define TC6_CC16_NUM 2 +#define TC6_CC32_NUM 2 +#define TC6_DITHERING_EXT 0 +#define TC6_GCLK_ID 22 +#define TC6_OW_NUM 2 +#define TC6_PERIOD_EXT 0 +#define TC6_SHADOW_EXT 0 + +#endif /* _SAMD20_TC6_INSTANCE_ */
diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_tc7.h b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_tc7.h new file mode 100644 index 0000000..52fe4e6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_tc7.h
@@ -0,0 +1,106 @@ +/** + * \file + * + * \brief Instance description for TC7 + * + * Copyright (c) 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD20_TC7_INSTANCE_ +#define _SAMD20_TC7_INSTANCE_ + +/* ========== Register definition for TC7 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC7_CTRLA (0x42003C00U) /**< \brief (TC7) Control A Register */ +#define REG_TC7_READREQ (0x42003C02U) /**< \brief (TC7) Read Request Register */ +#define REG_TC7_CTRLBCLR (0x42003C04U) /**< \brief (TC7) Control B Clear Register */ +#define REG_TC7_CTRLBSET (0x42003C05U) /**< \brief (TC7) Control B Set Register */ +#define REG_TC7_CTRLC (0x42003C06U) /**< \brief (TC7) Control C Register */ +#define REG_TC7_DBGCTRL (0x42003C08U) /**< \brief (TC7) Debug Register */ +#define REG_TC7_EVCTRL (0x42003C0AU) /**< \brief (TC7) Event Control Register */ +#define REG_TC7_INTENCLR (0x42003C0CU) /**< \brief (TC7) Interrupt Enable Clear Register */ +#define REG_TC7_INTENSET (0x42003C0DU) /**< \brief (TC7) Interrupt Enable Set Register */ +#define REG_TC7_INTFLAG (0x42003C0EU) /**< \brief (TC7) Interrupt Flag Status and Clear Register */ +#define REG_TC7_STATUS (0x42003C0FU) /**< \brief (TC7) Status Register */ +#define REG_TC7_COUNT8_COUNT (0x42003C10U) /**< \brief (TC7) COUNT8 Count Register */ +#define REG_TC7_COUNT16_COUNT (0x42003C10U) /**< \brief (TC7) COUNT16 Count Register */ +#define REG_TC7_COUNT32_COUNT (0x42003C10U) /**< \brief (TC7) COUNT32 Count Register */ +#define REG_TC7_COUNT8_PER (0x42003C14U) /**< \brief (TC7) COUNT8 Period Register */ +#define REG_TC7_COUNT32_PER (0x42003C14U) /**< \brief (TC7) COUNT32 Period Register */ +#define REG_TC7_COUNT8_CC0 (0x42003C18U) /**< \brief (TC7) COUNT8 Compare and Capture Register 0 */ +#define REG_TC7_COUNT8_CC1 (0x42003C19U) /**< \brief (TC7) COUNT8 Compare and Capture Register 1 */ +#define REG_TC7_COUNT16_CC0 (0x42003C18U) /**< \brief (TC7) COUNT16 Compare and Capture Register 0 */ +#define REG_TC7_COUNT16_CC1 (0x42003C1AU) /**< \brief (TC7) COUNT16 Compare and Capture Register 1 */ +#define REG_TC7_COUNT32_CC0 (0x42003C18U) /**< \brief (TC7) COUNT32 Compare and Capture Register 0 */ +#define REG_TC7_COUNT32_CC1 (0x42003C1CU) /**< \brief (TC7) COUNT32 Compare and Capture Register 1 */ +#else +#define REG_TC7_CTRLA (*(RwReg16*)0x42003C00U) /**< \brief (TC7) Control A Register */ +#define REG_TC7_READREQ (*(RwReg16*)0x42003C02U) /**< \brief (TC7) Read Request Register */ +#define REG_TC7_CTRLBCLR (*(RwReg8 *)0x42003C04U) /**< \brief (TC7) Control B Clear Register */ +#define REG_TC7_CTRLBSET (*(RwReg8 *)0x42003C05U) /**< \brief (TC7) Control B Set Register */ +#define REG_TC7_CTRLC (*(RwReg8 *)0x42003C06U) /**< \brief (TC7) Control C Register */ +#define REG_TC7_DBGCTRL (*(RwReg8 *)0x42003C08U) /**< \brief (TC7) Debug Register */ +#define REG_TC7_EVCTRL (*(RwReg16*)0x42003C0AU) /**< \brief (TC7) Event Control Register */ +#define REG_TC7_INTENCLR (*(RwReg8 *)0x42003C0CU) /**< \brief (TC7) Interrupt Enable Clear Register */ +#define REG_TC7_INTENSET (*(RwReg8 *)0x42003C0DU) /**< \brief (TC7) Interrupt Enable Set Register */ +#define REG_TC7_INTFLAG (*(RwReg8 *)0x42003C0EU) /**< \brief (TC7) Interrupt Flag Status and Clear Register */ +#define REG_TC7_STATUS (*(RoReg8 *)0x42003C0FU) /**< \brief (TC7) Status Register */ +#define REG_TC7_COUNT8_COUNT (*(RwReg8 *)0x42003C10U) /**< \brief (TC7) COUNT8 Count Register */ +#define REG_TC7_COUNT16_COUNT (*(RwReg16*)0x42003C10U) /**< \brief (TC7) COUNT16 Count Register */ +#define REG_TC7_COUNT32_COUNT (*(RwReg *)0x42003C10U) /**< \brief (TC7) COUNT32 Count Register */ +#define REG_TC7_COUNT8_PER (*(RwReg8 *)0x42003C14U) /**< \brief (TC7) COUNT8 Period Register */ +#define REG_TC7_COUNT32_PER (*(RwReg *)0x42003C14U) /**< \brief (TC7) COUNT32 Period Register */ +#define REG_TC7_COUNT8_CC0 (*(RwReg8 *)0x42003C18U) /**< \brief (TC7) COUNT8 Compare and Capture Register 0 */ +#define REG_TC7_COUNT8_CC1 (*(RwReg8 *)0x42003C19U) /**< \brief (TC7) COUNT8 Compare and Capture Register 1 */ +#define REG_TC7_COUNT16_CC0 (*(RwReg16*)0x42003C18U) /**< \brief (TC7) COUNT16 Compare and Capture Register 0 */ +#define REG_TC7_COUNT16_CC1 (*(RwReg16*)0x42003C1AU) /**< \brief (TC7) COUNT16 Compare and Capture Register 1 */ +#define REG_TC7_COUNT32_CC0 (*(RwReg *)0x42003C18U) /**< \brief (TC7) COUNT32 Compare and Capture Register 0 */ +#define REG_TC7_COUNT32_CC1 (*(RwReg *)0x42003C1CU) /**< \brief (TC7) COUNT32 Compare and Capture Register 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC7 peripheral ========== */ +#define TC7_CC8_NUM 2 +#define TC7_CC16_NUM 2 +#define TC7_CC32_NUM 2 +#define TC7_DITHERING_EXT 0 +#define TC7_GCLK_ID 22 +#define TC7_OW_NUM 2 +#define TC7_PERIOD_EXT 0 +#define TC7_SHADOW_EXT 0 + +#endif /* _SAMD20_TC7_INSTANCE_ */
diff --git a/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_wdt.h b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_wdt.h new file mode 100644 index 0000000..9dca4c8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_Atmel_SAMD20_XPlained/RTOSDemo/src/ASF/sam0/utils/cmsis/samd20/include/instance/instance_wdt.h
@@ -0,0 +1,71 @@ +/** + * \file + * + * \brief Instance description for WDT + * + * Copyright (c) 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD20_WDT_INSTANCE_ +#define _SAMD20_WDT_INSTANCE_ + +/* ========== Register definition for WDT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_WDT_CTRL (0x40001000U) /**< \brief (WDT) Control Register */ +#define REG_WDT_CONFIG (0x40001001U) /**< \brief (WDT) Configuration Register */ +#define REG_WDT_EWCTRL (0x40001002U) /**< \brief (WDT) Early Warning Control Register */ +#define REG_WDT_INTENCLR (0x40001004U) /**< \brief (WDT) Interrupt Enable Clear Register */ +#define REG_WDT_INTENSET (0x40001005U) /**< \brief (WDT) Interrupt Enable Set Register */ +#define REG_WDT_INTFLAG (0x40001006U) /**< \brief (WDT) Interrupt Flag Status and Clear Register */ +#define REG_WDT_STATUS (0x40001007U) /**< \brief (WDT) Status Register */ +#define REG_WDT_CLEAR (0x40001008U) /**< \brief (WDT) Clear Register */ +#else +#define REG_WDT_CTRL (*(RwReg8 *)0x40001000U) /**< \brief (WDT) Control Register */ +#define REG_WDT_CONFIG (*(RwReg8 *)0x40001001U) /**< \brief (WDT) Configuration Register */ +#define REG_WDT_EWCTRL (*(RwReg8 *)0x40001002U) /**< \brief (WDT) Early Warning Control Register */ +#define REG_WDT_INTENCLR (*(RwReg8 *)0x40001004U) /**< \brief (WDT) Interrupt Enable Clear Register */ +#define REG_WDT_INTENSET (*(RwReg8 *)0x40001005U) /**< \brief (WDT) Interrupt Enable Set Register */ +#define REG_WDT_INTFLAG (*(RwReg8 *)0x40001006U) /**< \brief (WDT) Interrupt Flag Status and Clear Register */ +#define REG_WDT_STATUS (*(RoReg8 *)0x40001007U) /**< \brief (WDT) Status Register */ +#define REG_WDT_CLEAR (*(WoReg8 *)0x40001008U) /**< \brief (WDT) Clear Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for WDT peripheral ========== */ +#define WDT_GCLK_ID 1 + +#endif /* _SAMD20_WDT_INSTANCE_ */